VHDLXILINX & DESIGN IMPLEMENTATION ON FPGA

Introduction to VHDL The VHDL language and is mainly intended as a companion for the Digital Design Laboratory. Introduction VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. In the mid-1980s the U.S. Department of Defense and the IEEE sponsored the development of this hardware description language with the goal to develop very high-speed integrated circuit. It has become now one of industrys standard languages used to describe digital systems. The other widely used hardware description language is Verilog. Both are powerful languages that allow you to describe and simulate complex digital systems. A third HDL language is ABEL(Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This tutorial deals with VHDL, as described by the IEEE standard 10761993.Al t h o u g h these languages look s i mi l a r as conventional

p r o g r a mmi n g languages, there are some important differences. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed(computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows incorporation of timing Specifications (gate delays) as well as to describe a system as an interconnection of different components. Levels of representation and abstraction

A digital system can be represented at different levels of abstraction.This keeps the description and design of complex systems manageable. Behavioral, Structural and Physical The highest level of abstraction is the behavioral level that describes a system in terms of what it does (or how it behaves) rather than in terms of its components and interconnection between them. A behavioral description specifies the relationship between the input and output signals. This could be a Boolean expression or a more a b s t r a c t d e s c r i p t i o n s u c h a s t h e R e g i s t e r Tr a n s f e r o r Al g o r i t h mi c l e v e l . As a n example, let us consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used whenever the car key is inserted in the ignition lock At the behavioral level this could be expressed as, Warning = Ignition_on AND ( Door_open OR Seatbelt_off) The structural level, on the other hand, describes a system as a collection of gates and components that are interconnected to perform a desired function. A structural description could be compared to a schematic of interconnected logic gates. It is a representation that is usually closer to the physical realization of a system. Structural representation of a buzzer circuit.VHDL allows one to describe a digital system at the structural or the behavioral level.The behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic. The dataflow representation describes how data moves through the system. This is typically done in terms of data flow between registers (Register Transfer level). The data flow model makes use of concurrent statements that are executed in parallel as soon as data arrives at the input. On the other hand, sequential statements are executed in the sequence that they are

specified. VHDL allows both concurrent and sequential signal assignments that will determine the manner in which they are executed. Basic Structure of a VHDL file A digital system in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity declaration a n d a n architecture body O n e c a n c o n s i d e r t h e e n t i t y declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in Figure.

Vhdl entity In a typical design there will be many such entities connected together to perform the desired function. VHDL uses reserved keywords that cannot be used as signal names or identifiers.Keywords and user-defined identifiers are case insensitive.

Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and extra spaces. VHDL is a strongly typed language which implies that one has always to declare the typeof every object that can have a value,such as signals, constants and variables

Top down design approch Abstraction Level VHDL supports designing at many different levels of abstraction. Three of them are very important: Behavioral level Register-Transfer Level Gate Level

Behavioral Level This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design. Register-Transfer Level Designs using the Register-Transfer Level specify the

characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing bounds operations are scheduled to occur at certain times. Modern RTL code definition is "Any code that is synthesizable is called RTL code". Gate Level Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.

Introduction to FPGA FPGA stands for Field Programmable Gate Array which has the array of logic module, I/O module and routing tracks (programmable interconnect). FPGA can be configured by end user to implement specific circuitry. Speed is up to 100 MHz but at present speed is in GHz. Main applications are DSP, FPGA based computers, logic emulation, ASIC and ASSP. FPGA can be

programmed mainly on SRAM (StaticR a n d o m Ac c e s s M e mo r y) . I t i s Volatile and ma i n advantage of using S R A M programming

technology is re-configurability. Issues in FPGA technology are complexity of logic element, clock support, IO support and

interconnections(Routing).

FPGA Design Flow FPGA contains a two dimensional arrays of logic blocks and logic blocks. Both the logic blocks and

interconnections between

interconnects are programmable.Logic blocks are programmed to implement a desired function and the interconnects are programmed using the switch boxes to connect the logic blocks. To be more clear,if we want to implement a complex design (CPU for instance), then the design is divided into small sub functions and each sub function is implemented using one logic block. Now, to get our desired design (CPU), all the sub functions implemented in logic blocks must be connected and this is done by programming the interconnects.

Internal structure of FPGA

FPGA alternative to the custom ICs, can be used to implement an entire System On one Chip (SOC). The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to implement a design and this is done after the FPGA is manufactured. This brings the name Field Programmable.Custom ICs are expensive and takes long time to design so they are useful when produced in bulk amounts. But FPGAs are easy to implement with in a short time with the help of Computer Aided Designing (CAD) tools (because there is no p h ys i c a l l a yo u t p r o c e s s , n o ma s k ma k i n g , a n d n o I C ma n u f a c t u r i n g ) . S o ma n y disadvantages of FPGAs are, they are slow compared to custom ICs as they cant handle vary complex designs and also they draw more power.

Xilinx logic block consists of one Look Up Table (LUT) and one FlipFlop.An LUT is used to implement number of different functionality. The input lines to the logic block go into the LUT and enable it. The output of the LUT gives the result of the logic function that it implements and the output of logic block is registered or unregistered output from the LUT. SRAM is used to implement a LUT.A k-input logic function is implemented using 2^k * 1 size SRAM. Number of different possible functions for k input LUT is2^2^k. Advantage of such an architecture is that it supports implementation of so many logic functions, however the disadvantage is unusually large number of memory cells required to implement such a logic block in case number of inputs is large.

Input LUT based implementation of logic block

LUT based design provides for better logic block utilization. A k input LUT based logic block can be implemented in number of different ways with trade off between performance and logic density.An n-LUT can be shown as a direct implementation of a function truth-table.E a c h o f t h e l a t c h holds the value of the function corresponding to one input combination. For Example: 2- LUT can be used to implement 16 types of functions like AND , OR, A+not B .... etc.

Inteconnects A wire segment can be described as two end points of an interconnect with no programmable switch between them. A sequence of one or more wire segments in an FPGA can be termed as a track.Typically an FPGA has logic blocks, interconnects and switch blocks( I n p u t / Ou t p u t blocks). S wi t c h

b l o c k s l i e i n t h e p e r i p h e r y o f l og i c b l o c k s a n d interconnect. Wire segments are connected to logic blocks through switch blocks. Depending on the required design, one logic block is connected to another and so on. FPGA Design Flow In this part of tutorial we are going to have a short intro on FPGA design flow.A simplified version of design flow is given in the flowing diagram.

FPGA Design Flow

Design Entry There are different techniques for design entry. Schematic based, Hardware Description Language and combination of both etc. . Selection of a method depends on the design and designer. If the designer wants to deal more with Hardware, then Schematic entry is the better choice. When the design is complex or the designer thinks the design in an algorithmic way then HDL is the better choice. Language based entry is faster but lag in performance and density. HDLs represent a level of a b s t r a c t i o n t h a t c a n i s o l a t e t h e d e s i g n e r s f r o m t h e d e t a i l s o f t h e h a r d w a r e implementation. Schematic based entry gives designers much more visibility into the hardware. It is the better choice for those who are hardware oriented. Another method but rarely used is state-machines. It is the better choice for the designers who think the design as a series of states. But the tools for state

machine entry are limited. In this documentation we are going to deal with the HDL based design entry. Synthesis The process which translates VHDL or Verilog code into a device netlist formate. i.e a complete circuit with logical elements( gates, flip flops, etc) for the design.If the design contains more than one sub designs, ex. to implement a processor,we need a CPU as one design element and RAM as another and so on, then the synthesis process generates netlist for each design element Synthesis process will check code syntax and analyze the hierarchy of the design which ensures that the design is optimized for the design architecture, the designer has selected. The resulting netlist(s) is saved to an NGC( Native Generic Circuit) file (for Xilinxsynthesis Technology (XST)).

FPGA synthesis Implementation This process consists a sequence of three steps 1.translate 2.map 3.place and route

Translate Process combines all the input netlists and constraints to a logic design file.This information is saved as a NGD (Native Generic Database) file. This can be doneusing NGD Build program. Here, defining constraints is nothing but, assigning the ports in the design to the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying time requirements of the design. This information is stored in a file named UCF (User Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.

FPGA translate Map Process divides the whole circuit with logical elements into sub blocks such that they can be fit into the FPGA logic blocks. That means map process fits

the logic defined by the NGD file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input Output Blocks (IOB)) and generates an NCD (Native Circuit Description) file which physically represents the design mapped to the components of FPGA. MAP program is used for this purpose.

FPGA MAP Place and Route PAR program is used for this process. The place and route process places thes ub blocks from the map process into logic blocks according to the constraints and connects the logic blocks. Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the time but it may effect some other constraint. So trade off between all the constraints is taken account by the place and route process.The PAR tool takes the mapped NCD

file as input and produces a completely routed NCD file as output. Output NCD file consists the routing information.

The PAR tool takes the mapped NCD file as input and produces a completely routed NCD file as output. Output NCD file consists the routing information.

Place and route

Device Programming No w t h e d e s i g n mu s t b e l o a d e d o n t h e F P G A. B u t t h e d e s i g n mu s t b e converted to a format so that the FPGA can accept it. BITGEN program deals with the conversion. The routed NCD file is then given to the BITGEN program to generate a bit stream (a .BIT file) which can be used to configure the target FPGA device. This can be done using a cable. Selection of cable depends on the design. Design Verification Verification can be done at different stages of the process steps. Behaviour Simulation(RTL Simulation) This is first of all simulation steps; those are encountered throughout the hierarchy of the design flow. This simulation is performed before synthesis process to v e r i f y R T L ( b e h a v i o r a l ) c o d e a n d t o c o n f i r m t h a t

t h e d e s i g n i s f u n c t i o n i n g a s intended. Behavioral simulation can be performed on either VHDL or Verilog designs. In this process, signals and variables are observed, procedures and functions are traced and breakpoints are set. This is a very fast simulation and so allows the designer to change the HDL code if the required functionality is not met with in a short time period. Since the design is not yet synthesized to gate level,timing and resource usage properties are still unknown. Functional Simulation(Post Translate Simulation) Functional simulation gives information about the logic

operation of the circuit designer can verify the functionality of the design using this process after the Translate process. If the functionality is not as expected, then the designer has to made changes in the code and again follow the design flow steps. Static Timing Analysis This can be done after MAP or PAR processes Post MAP timing report lists signal path delays of the design derived from the design logic. Post Place and Route timing report incorporates timing delay information to provide a comprehensive timing summary of the design. XILINX Xilinx is the world's largest supplier of programmable logic devices, the inventor of the field programmable gate array (FPGA) and the first semiconductor company with a fables manufacturing model.The Xilinx software can do simulation and synthesis .The entire processor will be implemented using the Xilinx FPGAs. So it wont spend much time to wiring up that part of the circuit. However, the designer have to wire the switches and lights that are used to control the processor, and have to wire the Xilinx part itself to the switches and lights, but this shouldn't be too bad. The designer will

also use the backplane bus in the lab kit so that the Triscuit will be built on two boards: one for the Xilinx chip, and one for the switches and lights. The HDL Editor feature provides e x t e n s i v e e d i t a n d s e a r c h c a p a b i l i t i e s wi t h l a n g u a g e - s p e c i f i c c o l o r c o d i n g o f keywords, as well as integrated on-line syntax checking to scan VHDL code for errors. The Language

Assistant feature speeds design entry by providing a lookup list of typical language constructs and commonly used synthesis modules like

counters,accumulators, and adders. XST Design Flow Overview The following figure shows the flow of files through the XST software.Design Entry Overview. Design entry can create source files to represent the design.The top-level design source file can be any of the following formats: Hardware Description Language (HDL), such as VHDL or Verilog Schematic (SCH) Embedded processor (XMP) ISE Design Suite The ISE Design Suite: Logic Edition allows you to go from design entry,through implementation and verification, to device

programming from within the

unified environment of the ISE Project

Navigator or from the command line. This edition includes exclusive tools and technologies to help achieve optimal design results, including the following: Xilinx Synthesis Technology (XST) - synthesizes VHDL, Verilog, or mixed language designs.

ISim - enables you to perform functional and timing simulations for VHDL,Verilog and mixed VHDL/Verilog designs. Plan Ahead software - enables you to do advanced FPGA floor planning. The Plan Ahead software includes I/O Planner, an environment designed to help you to import or create Ahead software includes I/O Planner, an environment designed to help you to import or create the initial I/O Port list, group the related ports into separate folders called Interfaces and assign them to package pins. I/O Planner supports fully automatic pin placement or semi- automated interactive modes to allow controlled I/O Port assignment. With early, intelligent decisions in FPGA I/O assignments, you can more easily optimize the connectivity between the PCB and FPGA.

CORE Generator software - provides an extensive library of Xilinx Logi CORE IP from basic elements to complex, system level IP cores. Smart Guide technology - enables you to use results from a previous implementation to guide the next

i m p l e m e n t a t i o n f o r f a s t e r i n c r e m e n t a l implementation. Design Preservation - enables you to use placement and routing for unchanged blocks from a previous implementation to reduce iterations in the timing closure phase. Partial Reconfiguration - enables dynamic design modification of a configured FPGA. The ISE software uses Partition technology to define and implement static and reconfigurable regions of the device. This feature requires an additional license code.

XPower Analyzer enables you to analyze power consumption for Xilinx FPGA and CPLD devices. Power Optimization for Virtex-6 devices minimizes logic toggling to reduce dynamic power consumption. IMPACT enables you to directly configure Xilinx FPGAs or program Xilinx CPLDs and PROMs with the Xilinx cables. It also enables you to create programming files, read back and verify design configuration data, debug configuration problems,and execute SVF and XSVF files. ChipScope Protocol assists with in circuit verification. Note Design Preservation a n d P a r t i a l R e c o n f i g u r a t i o n a r e s u p p o r t e d f o r t h e c o m ma n d l i n e t o o l s a n d t h e s tandalone version of the Plan Ahead software.

Properties of device parameters

Process Window The processes windows list the available processes

(corresponding to the process selected in the processes window). Typically you will select a particular process that you want to perform on the selected source file This can include a simulation, implementation, etc. To run a process you can double click on the process.When a process has been successfully executed a red tick-off icon appears. When you r u n a h i g h - l e v e l p r o c e s s , t h e P r o j e c t N a v i g a t o r wi l l a u t o ma t i c a l l y r u n a l l t h e associated lower-level processes. Integrated Software Environment (ISE) is the Xilinx design software suite.This overview explains the general progression of a design through ISE from

start to finish. ISE enables the design to be initiated with any of a number of different source types, including: HDL (VHDL, Verilog HDL, ABEL) Schematic design files EDIF State Machines IP Cores From source files, ISE enables quick verification of the functionality of these sources using the integrated simulation capabilities, including Model Sim Xilinx Edition and the HDL Bencher test bench generator. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD, and finally produce a bit stream for the device configuration. Design Entry 1. ISE Text Editor - The ISE Text Editor is provided in ISE for entering design code and viewing reports. 2. Schematic Editor - The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows creating, viewing, and editing schematics and symbols for the Design Entry step of the Xilinx design flow. 3. CORE Generator - The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders, to system-level building blocks such as filters,transforms, FIFOs, and memories. 4. Constraints Editor - The Constraints Editor allows to create and modify the most commonly used timing constraints.

5. PACE - The Pin out and Area Constraints Editor (PACE) allows viewing and editing I/O, Global logic, and Area Group constraints. 6. State CAD State Machine Editor - State CAD allows to specify states, transitions,and actions in a graphical editor. The state machine will be created in HDL. Implementation 1. Translate - The Translate process runs NGD Build to merge all of the input netlists as well as design constraint information into a Xilinx database file. 2. Map - The Map program maps a logical design to a Xilinx FPGA. 3. Place and Route (PAR) - The PAR program accepts the mapped design, places and routes the FPGA, and produces output for the bit stream generator. 4. Floor planner - The Floor planner allows viewing a graphical representation of the FPGA, and to view and modify the placed design. 5. FPGA Editor - The FPGA Editor allows viewing and modifying the physical implementation, including routing. 6. Timing Analyzer - The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. With Timing Analyzer, analysis can be performed immediately after mapping, placing or routing an FPGA design, and after fitting and routing a CPLD design. Features Memory Editor Window. Post Map and Post Translate flow supported in Project Navigator. Support of simulation of Embedded designs in XPS and Project Navigator ISim Hardware Co-Simulation Limited Access feature. Introduction to XILINXs Spartan-3 Kit

The Spartan-3 family of Field Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost sensitive consumer electronic applications. The eight member family offers densities ranging from 50,000 to five million system gates. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan -3 FPGAs are ideally suited to a wide range of consumer electronics applications; including broadband access, home networking,display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask

programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs.Also, FPGA programmability permits design upgrades in the field with no hardware replacement.

Spartan 3 FPGA kit

Boundary Scan (JTAG) Mode In Boundary Scan mode, dedicated pins are used for configuring the FPGA.The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP).FPGA configuration using the Boundary Scan mode is compatible with the IEEESTD 1149.1-1993 standard and IEEE Std 1532 for

In System Configurable (ISC)d e v i c e s . C o n f i g u r a t i o n t h r o u g h t h e B o u n d a r y S c a n p o r t i s a l wa ys a v a i l a b l e , regardless of the selected configuration mode. In some cases, however, the mode pin setting may affect proper programming of the device due to various interactions.

For example, if the mode pins are set to Master Serial or Master Parallel mode,and the associated PROM is already programmed with a valid configuration image,then there is potential for configuration interference between the JTAG and PROM data. Selecting the Boundary Scan mode disables the other modes and is the most reliable mode when programming via JTAG. Swithces,Buttons And Knob Slide Switches The Spartan-3 Starter Kit board has eight slide switches. The slide switches are located in the lower right corner of the board and are labeled SW7 through SW0.Switch SW7 is the left- most switch, and SW0 is the right-most switch.

Slide switches

Operation : When in the UP or ON position, a switch connects the FPGA pin to 3.3V,a logic High. When DOWN or in the OFF position, the switch connects the FPGA pinto ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active de- bouncing circuitry,

although such circuitry could easily be added to the FPGA design programmed on the board. Push Button Switches The Spartan-3 Starter Kit board has eight momentary contact push-buttonswitches. The push buttons are located in the lower left corner of the board.

Push Button Switches

Operation: Pressing a push button connects the associated FPGA pin to 3.3V. Use an internal pull- down resistor within the FPGA pin to generate a logic Low when the button is not pressed. There is active de-bouncing circuitry on the push button. Discrete LEDs The Spartan-3 Starter Kit board has eight individual surface mount LEDs located above the slide switches. The LEDs are labeled LED7 through LED0. LED7is the left-most LED, LED0 the right-most LED.

Discrete LEDs Operation

Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3 device via a 390 current limi ting resistor. To light an individual LED, drive the associated FPGA control signal High. Clock Connections Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. Each of the clock inputs also optimally connects to an associated DCM. Voltage Control The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9. Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set for 3.3 V. The on-board oscillator is a 3.3V device and might not perform as expected when jumper JP9 is set for 2.5V. Auxillary Clock Oscillatory Socket The provided 8-pin socket accepts clock oscillators that fit the 8 pin DIP footprint. Use this socket if the FPGA application requires a frequency other than50MHz. Alternatively, use the FPGAs Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on board 50 MHz oscillator.