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. There are not enough free electrons and holes in an intrinsic semi-conductor to produce a usable current. The electrical action of these can be modified by doping means adding impurity atoms to a crystal to increase either the number of free holes or no of free electrons. When a crystal has been doped, it is called a extrinsic semi-conductor. They are of two types • n-type semiconductor having free electrons as majority carriers • p-type semiconductor having free holes as majority carriers By themselves, these doped materials are of little use. However, if a junction is made by joining ptype semiconductor to n-type semiconductor a useful device is produced known as diode. It will allow current to flow through it only in one direction. The unidirectional properties of a diode allow current flow when forward biased and disallow current flow when reversed biased. This is called rectification process and therefore it is also called rectifier. How is it possible that by properly joining two semiconductors each of which, by itself, will freely conduct the current in any direct refuses to allow conduction in one direction. Consider first the condition of p-type and n-type germanium just prior to joining fig. 1. The majority and minority carriers are in constant motion. The minority carriers are thermally produced and they exist only for short time after which they recombine and neutralize each other. In the mean time, other minority carriers have been produced and this process goes on and on. The number of these electron hole pair that exist at any one time depends upon the temperature. The number of majority carriers is however, fixed depending on the number of impurity atoms available. While the electrons and holes are in motion but the atoms are fixed in place and do not move.

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Fig.1 As soon as, the junction is formed, the following processes are initiated fig. 2.

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Holes from the p-side diffuse into n-side where they recombine with free electrons. Free electrons from n-side diffuse into p-side where they recombine with free holes. The diffusion of electrons and holes is due to the fact that large no of electrons are concentrated in one area and large no of holes are concentrated in another area. When these electrons and holes begin to diffuse across the junction then they collide each other and negative charge in the electrons cancels the positive charge of the hole and both will lose their charges. The diffusion of holes and electrons is an electric current referred to as a recombination current. The recombination process decay exponentially with both time and distance from the junction. Thus most of the recombination occurs just after the junction is made and very near to junction.

3

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A measure of the rate of recombination is the lifetime defined as the time required for the density of carriers to decrease to 37% to the original concentration

The impurity atoms are fixed in their individual places. The atoms itself is a part of the crystal and so cannot move. When the electrons and hole meet, their individual charge is cancelled and this leaves the originating impurity atoms with a net charge, the atom that produced the electron now lack an electronic and so becomes charged positively, whereas the atoms that produced the hole now lacks a positive charge and becomes negative. The electrically charged atoms are called ions since they are no longer neutral. These ions produce an electric field as shown in fig. 3. After several collisions occur, the electric field is great enough to repel rest of the majority carriers away of the junction. For example, an electron trying to diffuse from n to p side is repelled by the negative charge of the p-side. Thus diffusion process does not continue indefinitely but continues as long as the field is developed.

Fig.3 This region is produced immediately surrounding the junction that has no majority carriers. The majority carriers have been repelled away from the junction and junction is depleted from carriers. The junction is known as the barrier region or depletion region. The electric field represents a potential difference across the junction also called space charge potential or barrier potential . This potential is 0.7v for Si at 25o celcious and 0.3v for Ge. The physical width of the depletion region depends on the doping level. If very heavy doping is used, the depletion region is physically thin because diffusion charge need not travel far across the junction before recombination takes place (short life time). If doping is light, then depletion is more wide (long life time). The symbol of diode is shown in fig. 4. The terminal connected to p-layer is called anode (A) and the terminal connected to n-layer is called cathode (K)

4

Fig.4 Reverse Bias: If positive terminal of dc source is connected to cathode and negative terminal is connected to anode, the diode is called reverse biased as shown in fig. 5.

Fig.5 When the diode is reverse biased then the depletion region width increases, majority carriers move away from the junction and there is no flow of current due to majority carriers but there are thermally produced electron hole pair also. If these electrons and holes are generated in the vicinity of junction then there is a flow of current. The negative voltage applied to the diode will tend to attract the holes thus generated and repel the electrons. At the same time, the positive voltage will attract the electrons towards the battery and repel the holes. This will cause current to flow in the circuit. This current is usually very small (interms of micro amp to nano amp). Since this current is due to minority carriers and these number of minority carriers are fixed at a given temperature therefore, the current is almost constant known as reverse saturation current ICO. In actual diode, the current is not almost constant but increases slightly with voltage. This is due to surface leakage current. The surface of diode follows ohmic law (V=IR). The resistance under reverse bias condition is very high 100k to mega ohms. When the reverse voltage is increased, then at certain voltage, then breakdown to diode takes place and it conducts heavily. This is due to avalanche or zener breakdown. The characteristic of the diode is shown in fig. 6.

Number of majority carriers are fixed in semiconductor. Therefore as each electron is eliminated at the junction. this comes from battery. there is a flow of carriers and thus flow of current. then majority carriers are pushed towards junction. one hole must be created in p-layer.5 Fig. At the same time. .6 Forward bias: When the diode is forward bias. This is formed by extracting one electron from p-layer. a new electron must be introduced. when they collide and recombination takes place. Therefore.

It is considered as a fictitious element that allow us to predict time delay. This region behaves as the dielectric material used for making capacitors. thereby creating more ions.6 Lecture-2: Diode Space charge capacitance CT of diode: Reverse bias causes majority carriers to move away from the junction. there fore it is defined as dQ / dV. If the amount of charge to be moved across the junction is increased. the time delay is greater. (E-1) where. CT is not constant.that is a factor of 107. The p-type and n-type conducting on each side of dielectric act as the plate. (E-2) Relationship between Diode Current and Diode Voltage An exponential relationship exists between the carrier density and applied potential of diode junction as given in equation E-3. . it follows that diffusion capacitance varies directly with the magnitude of forward current. it depends upon applied voltage. dQ is the increase in charge caused by a change dV in voltage. This exponential relationship of the current iD and the voltage vD holds over a range of at least seven orders of magnitudes of current . The incremental capacitance CT is defined by Since Therefore. Hence the thickness of depletion region increases. then also a capacitance is defined called diffusion capacitance CD (rate of change of injected charge with voltage) to take into account the time delay in moving the charges across the junction by the diffusion process. (E-3) Where. When p-n junction is forward biased.

n. and the diode has a very small equivalent resistance. The conductance is therefore very large. the curve is approximated by a straight line with a very large slope. n is in the range of 1.60 x 10-19 joules/volt k = Boltzmann's constant: 1. For germanium diodes.6. For silicon diodes. Since the slope is the conductance (i. diffusion. the curve sections are close to being straight lines.7 iD= Current through the diode (dependent variable in this expression) vD= Potential difference across the diode terminals (independent variable in this expression) IO= Reverse saturation current (of the order of 10-15 A for small signal diodes. 1.38 x l0-23 joules /° K T = Absolute temperature in degrees Kelvin (°K = 273 + temperature in °C) n = Empirical scaling constant between 0.e. the curve is approximated by a straight line of slope close to zero. levels of doping and purity of materials.5 and 2. sometimes referred to as the Exponential Ideality Factor The empirical constant. and the equivalent resistance is very high. For voltages less than VON. yielding (E-4) At room temperature (25°C) with forward-bias voltage only the first term in the parentheses is dominant and the current is approximately given by (E-5) The current-voltage (l-V) characteristic of the diode. is a number that can vary according to the voltage and current levels. n is usually considered to be close to 1. k T/ q becomes 52 mV.. If n=1. However. i / v). Among the quantities affecting the value of n are the diode manufacture. the exponent values are such that for voltages and currents experienced in practical circuits. It depends on electron drift. the value of k T/ q is 26 mV at 25°C. n is assumed 1 for all junctions all throughout unless otherwise noted. the conductance is very small in this region. but IO is a strong function of temperature) q = Electron charge: 1. When n=2. Equation (E-3) can be simplified by defining VT =k T/q. as defined by (E-3) is illustrated in fig. . and carrier recombination in the depletion region. For voltages above VON.3 to 1. The curve in the figure consists of two exponential curves.

(E-6) This slope is the equivalent conductance of the diode at the specified values of vD or iD.Diode Voltage relationship The slope of the curves of fig. The dynamic resistance is the reciprocal of this expression.8 Fig. (E-9) . To eliminate the exponential function. (E-8) The approximation applies if the diode is forward biased.1 changes as the current and voltage change since the l-V characteristic follows the exponential relationship of relationship of equation (E-4).1 . we substitute equation (E-4) into the exponential of equation (E-7) to obtain (E-7) A realistic assumption is that IO<< iD equation (E-7) then yields. We can approximate the slope as a linear function of the diode current. Differentiate the equation (E-4) to find the slope at any arbitrary value of vDor iD.

the turn-on voltage. or 25°C. 2 .Dependence of iD on temperature versus vD for real diode (kT = -2. we can approximate it as a constant if the variation of iD is small. Temperature Effects: Temperature plays an important role in determining the characteristic of diodes. vON. decreases. TNew= new temperature of diode in °C. VON (TNew) = diode voltage at new temperature. Alternatively. Rf is composed of rd and the contact resistance. As temperature increases. This is illustrated in fig. Troom= room temperature. 2. This corresponds to approximating the exponential function as a straight line within a specific operating range. The contact resistance is a relatively small resistance composed of the resistance of the actual connection to the diode and the resistance of the semiconductor prior to the junction. VON(Troom ) = diode voltage at room temperature. .0 mV /°C) where. The reverse-bias resistance is extremely large and is often approximated as infinity. kT = temperature coefficient in V/°C.9 Although rd is a function of id. a decrease in temperature results in an increase in vON. Normally. The temperature relationship is described by equation VON(TNew ) ? VON(Troom) = kT(TNew ? T room) (E-10) Fig. where VON varies linearly with temperature which is evidenced by the evenly spaced curves for increasing temperature in 25 °C increments. the term Rf to denote diode forward resistance.

15/°C ( for silicon) and T1 and T2 are two arbitrary temperatures. standard engineering practice permits approximation as a constant. . IO also depends on temperature.5 mV/°C for germanium diodes kT = -2. In other words. Values of kT for the various types of diodes at room temperature are given as follows: kT= -2. At room temperature.0 mV/°C for silicon diodes The reverse saturation current. IO approximately doubles for every 5 °C increase in temperature for silicon.10 Although kT varies with changing operating parameters. The expression for the reverse saturation current as a function of temperature can be approximated as (E-11) where Ki= 0. it increases approximately 16% per °C for silicon and 10% per °C for germanium diodes. and for every 7 °C for germanium.

. Troom= 25° C. What is the voltage. VON (TNew ) = 0.2: Find the output current for the circuit shown in fig. Given VON (TNew ) = VON (Troom) + KT (Tnew ? Troom) VON (Troom) = 0. a 0.55 V Example .7 + (-2 x 10-3 ) (100-75) = 0.1(a). TNew= 100° C Therefore.11 Lecture -3: Diode Operating Point Example . VON.7 V. across the diode at 100°C? Solution: The temperature relationship is described by VON (TNew) ? VON(Troom) = KT (TNew ? Troom) or.7 V drop exists across its terminals.1: When a silicon diode is conducting at a temperature of 25°C.

The output voltage is given by . 1(b). 1(b).12 Fig. This is true since the only external source is 10 V.1. even taking the voltage division into account. The equivalent circuit then becomes that of fig. as shown in fig. The Thevenin's equivalent of the circuit between A and B is given by fig.. the problem becomes one of simple dc circuit analysis. 1(c). either open circuit or short circuit). with the diode replaced by a short circuit. Once we determine the state of the ideal diode in this model (i. It is reasonable to assume that the diode is forward biased.e. which clearly exceeds the turn-on voltage of the diode.Circuit for Example 2 Solutions: Since the problem contains only a dc source. we use the diode equivalent circuit.

7V.1 sin 1000t. We need to determine the dynamic resistance so we can establish the resistance of the forward-biased junction for the ac signal. 2. has a source voltage of Vs = 1. Assume that nVT = 40 mV VON = 0.66V Example . Assuming that the contact resistance is negligible Rf= rD Now we can replace the forward-biased diode with a 10 W resistor. iD.7 V Solution: We use KVL for dc equation to yield Vs= VON+ ID RL Fig. we have. then Vo = 3.13 or. If VON= 0.2 This sets the dc operating point of the diode. Find the current. Again using KVL.1 + 0.2 W . and Rf= 0. vs= Rf id + RL id .3 The circuit of fig.

The point of intersection of straight line and diode characteristic gives the operating point as shown in fig.14 The diode current is given by I = 4 + 0.IdRL This equation involves two unknowns and cannot be solved. the diode is always forward-biased. 4. . The straight line represented by the above equation is known as the load line. I = 0. The other equation in terms of these two variables VD & Id. and the solution is complete. I = V / RL. Small Signal Operation of Real diode: Consider the diode circuit shown in fig. V = VD + Id RL VD = V. The load line passes through two points. 3. VD = V and VD= 0. 3 The slope of this line is equal to 1/ RL. Fig.91 sin 1000 t mA Since iD is always positive. is given by the static characteristic.

Therefore.15 Fig. as the diode voltage varies. 6. Say V = 1V. . diode current also varies. The resulting input voltage is the sum of dc voltage and sinusoidal ac voltage. RL=10 ohm. The intersection of load line and diode characteristic for different input voltages gives the output voltage as shown in fig. sinusoidally. 4 Fig. 5 Let us consider a circuit shown in fig. 5 having dc voltage and sinusoidal ac voltage.

It is obtained by taking the ratio of Δ V D/ Δ ID at operating point. Dynamic Resistance Δ rD = Δ VD / Δ ID Fig. Since only ac response of the circuit is considered DC Source is not shown in the equivalent circuit of fig.16 Fig. 7 . 7. 6 In certain applications only ac equivalent circuit is required. The resistance rf represents the dynamic resistance or ac resistance of the diode.

2 . When it is reverse biased resistance offered is infinity. The characteristic and the equivalent circuit of the diode is shown in fig. The characteristic and the equivalent circuit is shown in fig. for Si diode then it conducts and offers zero resistance.7V. resistance offered is zero.7 V. Fig. 2. The drop across the diode is 0. Fig. When reverse biased it offers infinite resistance.17 Lecture . Second Approximation: • • When forward voltage is more than 0. 1.4: Applications of Diode Diode Approximation: (Large signal operations): 1. It acts as a perfect switch. 1 2. Ideal Diode: • • When diode is forward biased.

Fig. The output characteristic and the equivalent circuit is shown in fig. then the diode conducts and the voltage drop across the diode becomes 0. 3.7 + ID Rf. 3rd Approximation: • When forward voltage is more than 0. 4 . Fig.7 V and it offers resistance Rf (slope of the current) VD= 0. then the diode equivalent circuit is as shown in fig.7 V. 4. 3 • When reverse biased resistance offered is very high & not infinity.18 3.

Fig. Therefore. 5 Solution: (a).19 Example . (b) V1 = V. then one upper diode is forward biased and lower diode is unbiased. 6. Fig.1: Calculate the voltage output of the circuit shown in fig. then the diodes are unbiased. (c) V 1 = V2 = V knew voltage = Vr Forward resistance of each diode is Rf. 5 for following inputs (a) V1 = V2 = 0. The resultant circuit using third approximation of diode will be as shown in fig. 6 . V2 = 0. When both V1 and V2 are zero . When V1 = V and V2 = 0. Vo = 0 V (b).

8 . The resultant circuit using third approximation of diode will be as shown in Fig. Applications of diode: Half wave Rectifier: The single ? phase half wave rectifier is shown in fig. then both the diodes are forward biased and conduct. we get (c) When both V1 and V2 are same as V. 8. Fig. 7. 7 Applying KVL.20 Fig.

It supplies current in both half cycles of the input voltage. D is reverse biased. The diode must be capable to withstand this voltage. The average current rating must be greater than Iavg Full Wave Rectifier: A single ? phase full wave rectifier using center tap transformer is shown in fig. 9. 10. Thus the output voltage is same as the input voltage. and therefore output voltage is zero. 9 In positive half cycle. The output voltage waveform is shown in fig. In the negative half cycle.21 Fig. The maximum voltage across the diode is Vm. The average output voltage of the rectifier is given by The average output current is given by When the diode is reverse biased. entire transformer voltage appears across the diode. Therefore PIV half wave rating of diode should be equal to Vm in case of single-phase rectifiers. . D is forward biased and conducts.

. But D2 is reverse biased and does not conduct. In the second half cycle D2 is forward biased.22 Fig. It is also called 2 ? pulse midpoint converter because it supplies current in both the half cycles. and conducts and D1 is reverse biased. therefore PIV rating of the diode should be 2 Vm. The output voltage waveform is shown in fig. The average output voltage is given by and the average load current is given by When D1 conducts. then full secondary voltage appears across D2. 11 In the first half cycle D1 is forward biased and conducts. 10 Fig. 11.

Fig. 2-pulse center tap rectifier is used because only one diode drop is there. The ripple factor is the measure of the purity of dc output of a rectifier and is defined as Therefore. 2 In the positive half cycle. 1. D1 & D4 are forward biased and D2 & D3 are reverse biased.23 Lecture-5: Clipper Circuits Bridge Rectifier: The single ? phase full wave bridge rectifier is shown in fig. For low dc output. The main disadvantage is that it requires four diodes. It also provides currents in both the half cycle of input supply. In the negative half cycle. D2 & D3 are forward biased. and D1 & D4 are reverse biased. . The output voltage waveform is shown in fig.4V) becomes significant. 1 Fig. 2 and it is same as full wave rectifier but the advantage is that PIV rating of diodes are V m and only single secondary transformer is required. When low dc voltage is required then secondary voltage is low and diodes drop (1. It is the most widely used rectifier.

Fig. clips the input signal above a reference voltage (VR). 4 . The transfer characteristic (vo vs vi) and the output voltage waveform for a given input voltage are also discussed. if vi > VR. 4. vo = vi and. vo= VR. diode is reversed biased and does not conduct. Some of the clipper circuits are discussed here.24 Clippers: Clipping circuits are used to select that portion of the input wave which lies above or below some reference level. Therefore. Clipper Circuit 1: The circuit shown in fig. The transfer characteristic of the clippers is shown in fig. If vi < VR. 3. diode is forward biased and thus. In this clipper circuit. 3 Fig.

6. Fig. vo = vi and. 5 clips the input signal below reference voltage VR. If vi < VR. 6 .25 Clipper Circuit 2: The clipper circuit shown in fig. 5 Fig. In this clipper circuit. If vi > VR. diode is forward biased. diode is reverse biased. vo = VR The transfer characteristic of the circuit is shown in fig.

26 Clipper Circuit 3: To clip the input signal between two independent levels (VR1< VR2 ). vi ≥ VR2. The diodes D1 & D2 are assumed ideal diodes. 7. VR1 < vi < VR2 vo = vi The transfer characteristic of the clipper is shown in fig. 8. when vi ≤ VR1. Fig. vo=VR1 and. 7 Fig. 8 . For this clipper circuit. the clipper circuit is shown in fig. vo= VR2 and.

9 Solution: When diode D1 is off. . i1 = 0.27 Example ? 1: Draw the transfer characteristic of the circuit shown in fig.25 V both the diodes are ON.5 V Therefore. i2 = 0 and vp = 10 ( 0.5 = 0.5 V and 21. Between 7.25 = 7. D1 is reverse biased only if vi < 7. 9. and vo = 10 .5 x 0. Fig.1 ) + 2.5 V vp = vo = 7.5 For D2 to be reverse biased.4 vi + 1.5 V If D2 is off and D1 is ON.0.04 vi . D2 must be ON.

10. 10 The transfer characteristic of the circuit is shown in fig. .28 Fig.

Clipper Circuit 4: Consider the clipper circuit shown in fig. The current i in the circuit is given by . The equivalent circuit. 1 Fig.6: Clipper and Clamper Circuits Clippers: In the clipper circuits. diodes are assumed to be ideal device. 2. discussed so far. diode D is forward biased and conducts. 1 to clip the input signal above reference voltage Fig. 2 When vi < (VR+ Vr). diode D is reverse biased and therefore. vo= vi.29 Lecture . in this case is shown in fig. the transfer characteristics of the clipper circuits will be modified. If third approximation circuit of diode is used. and when vi > ( VR + Vr ).

3. which clips the input signal below the reference level (VR). diode D is reverse biased. Fig. If vi > (VR ? Vr). thus vO = vi and when vi < (vR -Vr). 4. . 3 Clipper Circuit 5: Consider the clipper circuit shown in fig. 5.30 The transfer characteristic of the circuit is shown in fig. D condcuts and the equivalent circuit becomes as shown in fig.

b. 7(a) assuming that the diodes are a. . For both cases. Fig.7 V. 6. 6 Example .1: Find the output voltage v out of the clipper circuit of fig. The transfer characteristic of the circuit is shown in fig.31 Therefore. assume RF is zero. Von = 0. ideal.

33 V. When vinis negative and vin > . vout = 6. then vout = -4V The resulting output wave shape is shown in fig. 7(a) Fig.4. then At vin = 8 V(peak).32 Fig. . 7(b) Solution: (a). then vout = vin and when vin is positive and vin > 3. When vinis positive and vin < 3. 7(b). then vout = vin When vin is negative and vin < -4.

vin is positive and vin < 3. . When VON = 0.7 V.4. which introduces +10 V in the input will produce the output that swings ideally from 0 V to +20 V. then vout = vin When vin < .56 V. 7(b).7 V.7 V. The complete waveform is lifted up by +10 V. When vin is negative and vin > -4. which introduces a negative dc voltage equal to peak value of input in the input signal.33 (b). then vout = .4. then When vin = 8V. Clamper Circuits: Clamping is a process of introducing a dc level into a signal. vout = 6. 8. Negative Diode clamper: A negative diode clamper is shown in fig. a positive dc clamper. if the input voltage swings from -10 V and +10 V.7 V. then vout = vin When vin > 3. For example.7 V The resulting output wave form is shown in fig.7 V.

34 Let the input signal swings form +10 V to -10 V. At that Vi starts to drop which means the anode of D is negative relative to cathode. which is also the output must be zero during the time from 0 to t1. 9. Fig. 10 . its voltage. the diode conducts. ( VD = vi . The capacitor charges during this period to 10 V. Assuming an ideal diode. with the polarity shown. 10.vc ) thus reverse biasing the diode and preventing the capacitor from discharging. Fig. During first positive half cycle as V i rises from 0 to 10 V. and the resultant output voltage is the sum of instantaneous input voltage and dc voltage (-10 V). therefore the equivalent circuit becomes an input supply in series with -10 V dc voltage as shown in fig. Since the capacitor is holding its charge it behaves as a DC voltage source while the diode appears as an open circuit.

the dc source is reverse biasing the diode. After that Vi starts to drop which means the anode of D is negative relative to cathode. which is also the output must be zero during the time from 0 to t1. 3. 1. the diode conducts. During input voltage variation from ?5 V to -10 V. The operation of the circuit is same as of negative clamper. Fig. 1 Fig. . with the polarity shown. As shown in fig. During first negative half cycle as Vi rises from 0 to -10 V. The input voltage swings from +10 V to -10 V.7: Clamper Circuits Positive Clamper: The positive clamper circuit is shown in fig. After that D becomes reverse biased and open circuited. 4. Since the capacitor is holding its charge it behaves as a DC voltage source while the diode appears as an open circuit. (V D= vi vC) thus reverse biasing the diode and preventing the capacitor from discharging. which introduces positive dc voltage equal to the peak of input signal. a dc source is required. To clamp the input signal by a voltage other than peak value. The capacitor charges during this period to 10 V. 2. In the negative half cycle when the voltage exceed 5V then D conduct. 2 Let the input signal swings form +10 V to -10 V.35 Lecture . Fig. Then complete ac signal is shifted upward by 5 V. therefore the equivalent circuit becomes an input supply in series with +10 V dc voltage and the resultant output voltage is the sum of instantaneous input voltage and dc voltage (+10 V). its voltage. 3. Assuming an ideal diode. the capacitor charges to 5 V with the polarity shown in fig. The output waveform is shown in fig.

The voltage waveform is shown in fig.36 Fig. At the peak of the positive half cycle D1 is reverse biased and D2 is forward biased. 3 Fig. 5 Fig. The circuit produces a dc voltage. 5. and D2 is reverse based. e.g. Capacitor voltage increases continuously and finally becomes 20V. C2 will change toward 2Vp. 4 Voltage Doubler : A voltage doubler circuit is shown in fig. 6. 6 At the peak of the negative half cycle D1 is forward based. Because the source and C1 are in series. . which is double the peak input voltage. Fig. This charges C1 to the peak voltage Vp with the polarity shown.

C1 voltage becomes 0 and C2 charges to +10V. Fig. D2 becomes forward biased and conducts and at t2.e. 7(a) During 0 to t1. when Vi is 10V total voltage change is 20V. let the input voltage varies from -10 V to +10 V. the input voltage is negative. If C1 = C2 = C. The different stages of circuit from 0 to t10 are shown in fig. both the capacitor voltages charge to +10 V i. Fig. 7(b) During t1 to t2. 7b. 7(c) .37 To understand the circuit operation. D1 is forward biased the capacitor is charged to ?10 V with the polarity as shown in fig. 7(a). Fig.

C1 again charges to +10V Fig.38 From t2 to t3 there is no conduction as both D1 and D2 are reverse biased. 7(e) Again during t6 to t7 there is no conduction and during t7 to t8. D1 conducts. 7(f) . During t3 to t4 D1 is forward biased and conducts. 7(d) During t4 to t5 both D1 and D2 are reverse biased and do not conduct. The capacitor C1 recharges to 10 V. The capacitor C2 voltage becomes +15 V and C1 voltage becomes +5 V. Fig. During t5 to t6 D2 is forward biased and conducts. Fig.

Fig.5V.39 During t8 to t9 both D1 and D2 are reverse biased and there is no conduction. This process continues till the capacitor C1 voltage becomes +20V.5 V and C1 voltage becomes 7. During t9 to t10 D2 conducts and capacitor C2 voltage becomes + 17. 7(g) .

Since the Zener effect (avalanche) occurs at a predictable point. The reverse voltage at which the avalanche occurs is called the breakdown or Zener voltage. A heavily doped diode has a low Zener breakdown voltage. the carrier collides with crystal ions and imparts sufficient energy to disrupt a covalent bond. A typical Zener diode characteristic is shown in fig. a new electron-hole pair is generated. This action continues and thereby disrupts the covalent bonds. where the characteristic curve remains at VZ (near the knee of the curve). is 0. the diode can be used as a voltage reference. the electron can be torn from the covalent bond thus causing the number of electron-hole pair combinations to multiply. If the reverse voltage exceeds the breakdown voltage. The process is referred to as impact ionization. In addition to the original carrier. The use of a sufficiently strong electric field at the junction can cause a direct rupture of the bond. The maximum reverse current. 1. This pair may pick up sufficient energy from the applied field to collide with another crystal ion and create still another electron-hole pair. The value of reverse voltage at which this occurs is controlled by the amount ot doping of the diode. and is illustrated in the figure. This mechanism is called high field emission or Zener breakdown. The circuit symbol for the Zener diode is different from that of a regular diode. while a lightly doped diode has a high Zener breakdown voltage. At voltages above approximately 8V. IZ(max). the predominant mechanism is the avalanche breakdown. There is a second mechanism that disrupts the covalent bonds. the zener diode will normally not be destroyed as long as the current does not exceed maximum value and the device closes not over load. If the electric field exerts a strong force on a bound electron.40 Lecture .1/ IZ(max). When a thermally generated carrier (part of the reverse saturation current) falls down the junction and acquires energy of the applied potential. avalanche multiplication or avalanche breakdown. .8: Zener Diode Zener Diode: The diodes designed to work in breakdown region are called zener diode. which the Zener diode can withstand is dependent on the design and construction of the diode. A design guideline that the minimum Zener current.

Thus. 1 .41 Fig.7 V. The power dissipation of a zener diode equals the product of its voltage and current. zener diode can be used as a voltage regulator in the configuration shown in fig.IZ(max) ) is a limiting factor in power supply design. 2 for regulating the dc voltage. . PZ= VZ IZ The amount of power which the zener diode can withstand ( VZ. When it works in breakdown region the voltage across it is constant (VZ) and the current through diode is decided by the external resistance.Zener diode characteristic The power handling capacity of these diodes is better. Zener Regulator: When zener diode is forward biased it works as a diode and drop across it is 0. It maintains the output voltage constant even through the current through it changes.

the output voltage varies slightly as shown in fig. . If second approximation of zener diode is considered. The intersection point of the load line and the zener characteristic gives the output voltage and zener current. The first approximation of zener diode is a voltage source of Vz magnitude and second approximation includes the resistance also. The zener ON state resistance produces more I * R drop as the current increases. 5. Rs is used to limit the current. To operate the zener in breakdown region Vs should always be greater then Vz. 3. 4.42 Fig. The load line is plotted along with zener characteristic in fig. 2 Fig. operating point also changes simultaneously but voltage across zener is almost constant. The two approximate equivalent circuits are shown in fig. 3 The load line of the circuit is given by Vs= Is Rs + Vz. If the Vs voltage changes. As the voltage varies form V1 to V2 the operating point shifts from Q1 to Q2.

43 The voltage at Q1 is V1 = I1 RZ +VZ and at Q2 V2 = I2 RZ +VZ Thus. 6 and load current Is= Iz + IL . the current through RS is given by Fig. The zener will work in the breakdown region only if the Thevenin voltage across zener is more than VZ . If zener is operating in breakdown region. change in voltage is V2 ? V1 = ( I2 ? I1 ) RZ Δ VZ =Δ IZ RZ Design of Zener regulator circuit: A zenere regulator circuit is shown in fig. The varying load current is represented by a variable load resistance RL. 6.

we examine the two extremes of input/output conditions. This keeps the voltage drop across Rs constant and hence the output voltage. The design challenge is to choose a value of Rs which permits the diode to maintain a relatively constant output voltage.1 times the maximum (i. If the input voltage should increase. • The current through the diode. iL is maximum (IL max) and the source voltage. we use an accepted rule of thumb that the minimum Zener current should be 0. the current IZ should decrease by the same percentage in order to maintain load current constant Is. iL. that is.. Equation (E-4) thus represents one equation in two unknowns. iZ. as follows: The current through the diode. • When these characteristics of the two extremes are inserted into Equation (E-1). the range of output load currents. iZ. In order to assure that the diode remains in the constant voltage (breakdown) region. we know the range of input voltages. If input voltage falls. even when the input source voltage varies and the load current also varies. (E-1) (E-2) The variable quantities in Equation (E-2) are vZ and iL. If the load IL should increase. For the circuit shown in figure. that extra voltage is dropped across the resistance Rs. the maximum and minimum Zener current. 10%). We now analyze the circuit to determine the proper choice of Rs. the zener diode passes a larger current. vs is minimum (Vs min). is a minimum (IZ min) when the load current. the current IZ falls such that VZ is constant.44 The circuit is designed such that the diode always operates in the breakdown region and the voltage VZ across it remains fairly constant even though the current IZ through it vary considerably. To avoid the non-constant portion of the characteristic curve. A second equation is found from the characteristic of zener. and the desired Zener voltage. In the practical application the source voltage.e. is minmum (iL min) and the source voltage vsis minimum(Vs max). varies and the load current also varies. vs. we find (E-3) (E-4) In a practical problem. is a maximum (IZ max) when the load current. .

45 (E-5) Solving the equations E-4 and E-5. the value of R s. a 1W. we get. The manufacturer specifies the maximum power the diode can dissipate. is calculated from Equation (E-3). . For example. (E-6) Now that we can solve for the maximum Zener current. Zener diodes are manufactured with breakdown voltages VZ in the range of a few volts to a few hundred volts. 10 V zener can operate safely at currents up to 100mA.

1 Solution: (a). Verify your design using a computer simulation. We must also select the proper resistor power rating. we must determine the power rating of the Zener diode. from Equation (E-3). where we use the maximum for each value.533 A Then. b. and power rating for the Zener. The maximum power dissipated in the Zener diode is given by the product of voltage and current. we have I Zmax = 0. R i . We use the equations from the previous section to first calculate the maximum current in the zener diode and then to find the input resistor value. Repeat the design problem for the following conditions: The load current ranges from 20 mA to 200 mA and the source voltage ranges from 10. The maximum power in the resistor is given by the product of voltage with current. The design consists of choosing the proper value of resistance.46 Lecture . Use a 10-volt Zener diode in both cases Fig.3 W Finally. 1 for the following conditions: a.9: Special Purpose Diodes Example 1: Design a 10-volt Zener regulator as shown in fig. .2 V to 14 V. From the Equation (E-6). P R = ( I Zmax + I Lmin ) (V smax ? V Z ) = 6. The load current ranges from 100 mA to 200 mA and the source voltage ranges from 14 V to 20 V. It is not sufficient to specify only the resistance of R i . we find R i as follows.

b. . Fig. 2 Seven Segment Display : Fig. arsenic and phosphorus. f. yellow. e. In light emitting diode. I n ordinary diodes this energy is in the form of heat. Each LED is called a Segment. d. This material blocks the passage of light. 2.53 x 10 = 5.as shown in fig. LEDs are made of different materials such as gallium. It can display any letters a. 3. g. c.5V. Typical LED current is between 10 mA to 50 mA. Ordinary diodes are made of Ge or Si. Each recombination radiates energy as electron falls from higher energy level to a lower energy level. blue. this energy is in the form of light. It contains seven rectangular LEDs. orange or infrared (invisible). 3 Seven segment displays are used to display digits and few alphabets.3 W Light Emitting Diode : In a forward biased diode free electrons cross the junction and enter into p-layer where they recombine with holes.47 P z = V z l zmax = 0. The LED's forward voltage drop is more approximately 1. External resistors are used to limit the currents to safe Values. green. LEDs can radiate red. The symbol of LED is shown in fig.

but while they exist they can contribute to the reverse current. 4. These carriers exist because thermal energy keeps on producing free electrons and holes. the amount of light striking the junction can control the reverse current in a diode. a reverse current flows due to minority carriers. 5 In other words.48 Fig. through a . Fig. It is sensitive to the light. A photo diode is made on the same principle. The lifetime of the minority carriers is short. it too can produce free electrons. Photo diode : When a diode is reversed biased as shown in fig. In this diode. 5. When light energy bombards a p-n junction. 4 The LEDs of seven-segment display are connected in either in common anode configuration or in common cathode configuration as shown in fig.

6 . They can be used to isolate two circuits of different voltage levels. Opto Coupler: It combines a LED and a photo diode in a single package as shown in fig. LED radiates the light depending on the current through LED. The stronger the light.49 window light falls to the junction. Fig. the greater the minority carriers and larger the reverse current. Because of this. The only contact between the input and output is a beam of light. The advantage of an opto coupler is the electrical isolation between the input and output circuits. it is possible to have an insulation resistance between the two circuits of the order of thousands of mega ohms. This light fails on photo diode and this sets up a reverse current. 6.

Fig. VEB = f1(VCB. The current directions are shown in fig. The complete transistor can be described by the following two relations.11: Common Base Configuration The Common Base Configuration : If the base is common to the input and output circuits. Holes flow from emitter to collector and few holes flow down towards ground out of the base terminal. 1 For a pnp transistor the largest current components are due to holes. 2. it is know as common base configuration as shown in fig. For a forward biased junction. IE) The output characteristic: The collector current IC is completely determined by the input current IE and the VCB voltage. 1.50 BIPOLAR JUNCTION TRANSISTOR Lecture . It is a plot of IC versus VCB. The transistor consists of two diodes placed in series back to back (with two cathodes connected together). The relationship is given in fig. which give the input voltage VEB and output current IC in terms of the output voltage (VCB) and input current IE. IE) IC= f2(VCB. The curves are known as the output or collector or static characteristics. . (IE = IC + IB ). with emitter current IE as parameter. VEB is positive and for a reverse biased junction VCB is negative. 1. The complete characteristic can be divided in three regions.

The collector current is almost constant and work as a current source. The collector current slightly increases with voltage. is called saturation region. If diode is sufficiently forward biased the current changes rapidly. Then the collector current is small and equals the reverse saturation current ICO of the collector junction considered as a diode. Active region: In this region the collector diode is reverse biased and the emitter diode is forward biased. In the active region. This is due to early effect. that it is usually neglected. there is large change in collector current with small changes in collector voltage. Saturation region: The region to the left of the ordinate VCB = 0. characteristic in which both emitter and collector junction are forward biased.2 (1). The difference is so small. Then there is less chance for recombination within the base region. there is a flow of holes from p to n. This reduces the base current. (2). then space charge width increases. Consider first that the emitter current is zero. At higher voltage collector gathers in a few more electrons.51 Figure 7. It does not depend upon emitter current. When collector diode is forward biased. A forward bias means. dcIE will reach the collector. the collector current is essentially independent of collector voltage and depends only upon the emitter current. then a fraction of IE ie. If the forward current IB is increased. . that p is made positive with respect to n. Because dc is. and above the IE = 0. This changes the collector current direction. the magnitude of the collector current is slightly less that of emitter current. less than one but almost equal to unity. If the collector voltage is increased. this decreased the effective base width.

7 or 0. It means collector to base current with emitter open. The characteristics IE = 0. and hence base can attract more holes from the emitter. Because of the early effect the emitter current increases for same VEB. (The diode becomes better diode). input characteristic is simply the forward biased characteristic of the emitter to base diode for various collector voltages. the emitter current increases for a given VEB since the collector now removes minority carriers from the base. therefore. is shifted from the character when VCB = open. When the collector is shorted to the base. The collector current is same as I CO.3) the emitter current is very small. 3. The curve with the collector open represents the forward biased emitter diode. Cut off region: The region below IE = 0 and to the right of VCB for which emitter and collector junctions are both reversed biased is referred to cutoff region. Fig. The Input Characteristic: In the active region the input diode is forward biased. Below cut in voltage (0. This mean that the curve VCB= 0. is similar to other characteristics but not coincident with horizontal axis. ICBO is frequently used for ICO. fig. This is also temperature dependent. 3 Equivalent circuit of a transistor: (Common Base) .52 (3).

4. The equivalent circuits of npn and pnp transistors are shown in fig. Therefore. emitter diode acts like a forward bias diode and collector diode acts like a current source.53 In an ideal transistor. The current source arrow points for conventional current. dc= 1. 4 Lecture -12: Common Base Amplifier . Fig. This means all emitter electrons entering the base region go on to the collector. The current source is controlled by emitter current. collector current equals emitter current. For transistor action.

IC RC. The dc collector current is same as IE and VCB is given by VCB = VCC . This ac voltage produces small fluctuation in currents and voltages. The dc equivalent circuit is obtained by reducing all ac sources to zero and opening all capacitors. 1. The load resistance RL is also connected to collector through coupling capacitor so the fluctuation in collector base voltage will be observed across RL. The ac source vin is connected to emitter through a coupling capacitor so that it blocks dc. The VEE source forward biases the emitter diode and VCC source reverse biased collector diode.54 Common Base Amplifier: The common base amplifier circuit is shown in Fig. r'e represents the ac resistance of the diode as shown in Fig. . 2. Fig. 1 These current and voltage fix the Q point. The ac equivalent circuit is obtained by reducing all dc sources to zero and shorting all coupling capacitors.

The .55 Fig. 3. the operating point swings sinusoidally about Q point (A to B). 2 Fig. input voltage and current will be sinusoidal but if the input voltage is large then current will no longer be sinusoidal because of the non linearity of diode curve. Fig . the transistor operates at Q point (point of intersection of load line and input characteristic). and arc A B can be approximated by a straight line and diode appears to be a resistance given by If the input signal is small. the emitter current and voltage also change. the points A and B are close to Q. shows the diode curve relating IE and VBE. When the ac signal is applied. In the absence of ac signal.3 If the ac signal is small. If the signal is small.

Higher up the Q point small will be the value of r' e because the same change in VBE produces large change in IE.56 emitter current is elongated on the positive half cycle and compressed on negative half cycle. r'e = 25mV / IE Proof In general. T is the temperature and K is a constant. In the ac equivalent circuit. or. To a close approximation the small changes in collector current equal the small changes in emitter current. Therefore the output will also be distorted. Voltage gain: Since the ac input voltage source is connected across r'e. Therefore.t V. V is the drop across diode. the current ?iC' is shown upward because if ?ie' increases. The value of (q / KT) at 25°C is approximately 40.r. From calculation it can be proved that. r'e is the ratio of ΔVBE and Δ IE and its value depends upon the location of Q. then ?iC' also increases in the same direction. Therefore. the current through a diode is given by Where q is he charge on electron. we get. On differentiating w. the ac emitter current is given by . The slope of the curve at Q determines the value of r'e.

Vin = ie r'e The output voltage is given by Vout = ic (RC || RL) Under open circuit condition vout = ic Rc Example-1 Find the voltage gain and output of the amplifier shown in fig. Vout = 1. Fig. if input voltage is 1. 4 Solution: The emitter dc current I E is given by Therefore.6 and.5mV.57 ie = Vin / r'e or.5 x 56.6 = 84. emitter ac resistance = or. AV= 56. 4.9 mV .

Therefore. 5. Solution: The ac equivalent circuit with ac source resistance is shown in fig. Fig.58 Example-2 Repeat example-1 if ac source has resistance R s = 100 W . voltage gain of the amplifier = and.1 mV . 5 The emitter ac current is given by or.5 x 8.71 =13. Vout = 1.

In this. With higher values of VCE collector gathers slightly more electrons and therefore base current reduces. VCE ) IC = f2( IB.E. 2. Normally this effect is neglected. 1. configuration the emitter is made common to the input and output. It is also referred to as grounded emitter configuration. . VCE ) Input Characteristic: The curve between IB and VBE for different values of VCE are shown in fig. base current and output voltages are taken as impendent parameters and input voltage and output current as dependent parameters VBE = f1 ( IB. therefore the characteristic is similar to diode one. 1 In C. (Early effect). It is most commonly used configuration.59 Lecture -13: Common Emitter Configuration Common Emitter Curves: The common emitter configuration of BJT is shown in fig. When collector is shorted with emitter then the input characteristic is the characteristic of a forward biased diode when VBE is zero and IB is also zero. Fig. Since the base emitter junction of a transistor is a diode.

For fixed value of IB and is shown in fig. 3 (1) Active Region: In this region collector junction is reverse biased and emitter junction is forward biased. It is the area to the right of VCE = 0. 3.60 Fig. In this region transistor current responds most sensitively to IB. . IC is not varying much dependent on VCE but slopes are greater than CE characteristic.5 V and above IB= 0. it must operate in this region. Fig. If transistor is to be used as an amplifier. 2 Output Characteristic: The output characteristic is the curve between VCE and IC for various values of IB. For fixed value of IB. The output characteristics can again be divided into three parts.

Reverse collector saturation current ICBO also varies with temperature.1% (0. Consider the circuit shown in fig. dc may be as large as 0. Therefore the curves are subjected to large variations for the same type of transistors. thedc is very nearly equal to zero.g. therefore.1 V for Ge and 0 V for Si. Accordingly in order to cut off transistor it is not enough to reduce I B to zero.996 / (1-0. cut off means IE = 0. A transistor is not at cut off if the base current is simply reduced to zero (open circuited) under this condition.001) e. IC = ICO. dc increases by 0. Since even in the neighborhood of cut off. from 0. then the collector current is known as ICBO (approximately equal to ICO).1 V is sufficient for cut off a transistor. Then dc increases from 0. In summary.996 as VCE increases from a few volts to 10V. VBB is the reverse voltage applied to reduce the emitter current to zero. IB = -ICBO . Reverse Collector Saturation Current ICBO: When in a physical transistor emitter current is reduced to zero. Hence even with IB= 0. and VBE is a reverse voltage whose magnitude is of the order of 0.995) = 200 to 0. In Si.995 / (1-0. It is found that reverse voltage of 0. IC = IE= ICO / ( 1-αdc) = ICEO The actual collector current with base open is designated as ICEO. but it is necessary to reverse bias the emitter junction slightly. avalanche multiplication and variability from sample to sample.996) = 250 or about 25%. IE = 0. But because of early effect. (2) Cut Off: Cut off in a transistor is given by IB = 0. IC= ICO. at zero base current.61 If dc is truly constant then IC would be independent of VCE. 4. then IC=10 ICO(approximately).9 for Ge. IC= IE= ICO so that transistor is very close to cut off. IB = -IC = -ICO .995 to 0. This shows that small change in reflects large change in . IC = ICO.

(3). ICBO = 100 m A. dc is known as dc current gain and in designated hfE ( dc = hfE).Saturation Region: In this region both the diodes are forward biased by at least cut in voltage.1 V Then .1 V Fig.62 If we require.VBB + ICBO RB < .1 Volts. The dc is an indication if how well the transistor works. In terms of h parameters. 4 If RB = 100 K. In this region the transistor collector current is approximately given by VCC / R C and independent of base current.0.0. where all the current rapidly reduces to zero. Hence transistor must be capable to withstand this reverse voltage before breakdown voltage exceeds. Hence saturation region is very close to zero voltage axis. Since the voltage VBE and VBC across a forward is approximately 0. VCE = VCB + VBE = . Large Signal Current Gain βdc :The ratio Ic / IB is defined as transfer ratio or large signal current gaindc Where IC is the collector current and IB is the base current. Normal transistor action is last and it acts like a small ohmic resistance. The typical value of dc varies from 50 to 300. VBE = .VBC + VBE is also few tenths of volts. Knowing the maximum collector current anddc the minimum base current can be found which will be needed to saturate the transistor. .7 V therefore. Then VBB must be 10.

ICBO.63 This expression of dc is defined neglecting reverse leakage current (ICO). ICO = ICBO Cut off of a transistor means IE = 0. the expression for the dc can be obtained as follows: dc in terms of dc is given by Since. the above expressiondc gives the collector current increment to the base current change form cut off to IB and hence it represents the large signal current gain of all common emitter transistor. . then IC= ICBO and IB = . Therefore. Taking reverse leakage current (ICO) into account.

1.IB RB Normally VBE is taken 0.14: Biasing Techniques for CE Amplifiers Biasing Circuit Techniques or Locating the Q . IB = VBB/ RB. For linear amplification. IC increases. This means forward biasing the base emitter junction and reverse biasing collector base junction. If exact voltage is required. and VBE = VBB. . VCE decreases proportionally). 2. The load line for the input circuit is drawn on input characteristic. The source VBB. then the input characteristic ( IB vs VBE) of the transistor should be used to solve the above equation.Point: Fixed Bias or Base Bias: In order for a transistor to amplify. For VBE = 0.7V or 0. If an ac signal is connected to the base of the transistor. Fig. 1 The dc base current through RB is given by IB = (VBB .64 Lecture .3V.VBE) / RB or VBE = VBB . The two points of the load line can be obtained as given below For IB = 0. through a current limit resistor RB forward biases the emitter diode and VCC through resistor RC (load resistance) reverse biases the collector junction as shown in fig.point. The intersection of this line with input characteristic gives the operating point Q as shown in fig. the transistor should operate in active region ( If IE increases. it has to be properly biased. This gives variation in IB and hence IC. then variation in V BE is about Q .

IC RC This equation involves two unknown VCE and IC and therefore can not be solved. IC= VCC / RC The intersection of this line which is also called dc load line and the characteristic gives the operating point Q as shown in fig. 3. To solve this equation output characteristic ( ICvs VCE) is used. Fig. 3 . 2 In the output circuit. the load equation can be written as VCE = VCC. The load equation is the equation of a straight line and given by two points: IC= 0.65 Fig. & VCE = VCC VCE = 0.

IC= IC(sat). then it operates at cut off. The intersection of the load line and IB = IB(max) characteristic is known as saturation point . If a transistor is operating as an amplifier then Q point must be selected carefully. If IB > IB (sat) it always operates in saturation region. At cut off the emitter diode comes out of forward bias and normal transistor action is lost. 4 VBB = IB RB+ VBE IB = (VBB ? VBE ) / RB If IB> IB(sat). . At this point base current is zero and collector current is almost negligibly small. To a close approximation. 4. If the IB is less than IB (sat). If the transistor operates at saturation or cut off points and no where else then it is operating as a switch is shown in fig.66 The point at which the load line intersects with IB = 0 characteristic is known as cut off point. then it operates at saturation. Fig. VCE ( cut off) ≈ VCC (approximately). Although we can select the operating point any where in the active region by choosing different values of R B & RC but the various transistor ratings such as maximum collector dissipation PC(max) maximum collector voltage VC(max) and IC(max) & VBE(max) limit the operating range. the transistor will operate in active region. If IB = 0. At this point collector diodes comes out of reverse bias and again transistor action is lost. To a close approximation. At this point IB= IB(max). The IB(sat) is the minimum current required to operate the transistor in saturation region. IC(sat) ≈ VCC / RC(approximately ).

collector junction is reverse biased and transistor is operating in its active region.55 V Therefore. 5.7 Therefore. IC = β IB = 2. i. It may be clipped from one side or both sides or it may be distorted one. As a result of this collector current and collector voltage also varies and the amplified output is obtained.7 = 2. β =100. therefore.0.e. Example-1 Find the transistor current in the circuit shown in fig. Solution: For the base circuit.55 .55 V Since. Since ICO << IB. 5 . 5 = 200 x IB + 0.67 Once the Q point is established an ac input is connected. Fig.3 x 2.15 mA From the collector circuit. Due to this the ac source the base current varies. If the Q-point is not selected properly then the output waveform will not be exactly the input waveform. if ICO= 20nA.15 = 3. VCE = 10 . VCE = VCB + VBE Thus. VCB = 3.

0107 = 3. Solution: The circuit is shown in fig.3 x 1. Assuming transistor is operating in its saturation region. Since ICO << IB.2 If a resistor of 2K is connected in series with emitter in the circuit as shown in fig.2V . Solution: IE = IB + IC = IB + 100 IB = 101 IB For the base circuit. VCB = 10 .7 + 2k x 101 IB Therefore. β =100.7 .0.93 V Therefore collector junction is reverse biased and transistor is operating in its active region. 7. Fig. VBE (sat)= 0.2 x 101 x 0. 6. Since the base resistance is reduced. the base current must have increased and there is a possibility that the transistor has entered into saturation region.8 V and VCE (sat) = 0.3 Repeat the example-1 if RB is replaced by 50k. Given ICO= 20 nA. find the currents. 6 Example .07 . 5 = 200 x IB + 0.68 Example . therefore.07 mA From the collector circuit. IC = βIB = 1.

we get. and The minimum base current required for operating the transistor in saturation region is Since IB > IB(min). 7 Example . Solving these equations. 8. Since the base resistance is reduced. the base current must have increased and there is a possibility that the transistor has entered into saturation region.96mA and IB = 0. transistor is operating in its saturation region. Solution: The circuit is shown in fig. Fig.69 Therefore. Assuming transistor is operating in its saturation region.4 Repeat the example-2 if RB is replaced by 50k. IC = 1. therefore.0035mA The minimum base current required for operating the transistor in saturation region is .

5 = 50 x IB + 0.70 Since I B < I B(min) . For the base circuit. transistor is operating in its active region and not in saturation.71 .7 + 2k x 101 IB Therefore.0171 = 0.3 x 1. 8 . therefore.0.7 .2 x 101 x 0.716 V Fig.71mA From the collector circuit. IC = 1. The base and the collector currents can be recalculated assuming the transistor to be in active region. VCB = 10 .

Fig. 1. 2 Fig. the output is clipped in negative half cycle as shown in fig. then the output is clipped in positive cycle as shown in fig.71 Lecture . Near saturation 3. Fig. 1 If the operating point is selected near saturation region. Near cut off 2. 1. 3 . 2. In the middle of active region If the operating point is selected near the cutoff region.15: Stability of Operating Point Let us consider three operating points of transistor operating in common emitter amplifier.

In biasing circuit shown in fig. The first circuit for biasing the transistor is CE configuration is fixed bias. 4(b). 4(a).e. The new operating point may be completely unsatisfactory. the output characteristic shifts downward. 5. Stability of quiescent operating point: Let us assume that the transistor is replaced by an other transistor of same type. 3. To avoid the use of two supplies the base resistance RB is connected to VCC as shown in fig. If input is large then clipping at both sides will take place.72 If the operating point is selected in the middle of active region. In this circuit Q point is very unstable. IB = VCC/ RB Since IB is constant therefore it is called fixed bias circuit. output characteristic shifts upward. to maintain operating point stable. The dc of the two transistors of same type may not be same. IB should be allowed to change so as to maintain VCE & IC constant as βdc changes. IB = (VCC ? VBE ) / RB Voltage across base emitter junction is approximately 0. . ifdc increases then for same IB. then there is no clipping and the output follows input faithfully as shown in fig. therefore the operating point shifts from Q to Q1 as shown in fig.7 V. 4(b) Now VCC is still forward biasing emitter diode. Therefore. The base resistance RB is selected by noting the required base current IB for operating point Q. Since IB is maintained constant. Fig. 4(a) Fig. If dc decreases. two different power supplies are required. Since VCC is usually very high i. Therefore.

∂ IC / ∂ βdc and ∂ IC / ∂ VBE. 5 A second cause for bias instability is a variation in temperature. ICO doubles for every 10oC rise in temperature. This increase in IC changes the characteristic and hence the operating point. then circuit is thermally instable. transistors are used which provide compensating voltages and currents to maintain the operating point constant. keeping βdc and VCE constant S = ∂ IC / ∂ ICO If S is large. stabilization techniques 2. stability factor S is defined as the rate of change of collector current with respect to the ICO. IC will increase ( βdc IB + (1+ β dc ) ICO )and so on. To compare different biasing circuits. Stability Factor: The operating point can be made stable by keeping IC and VCE constant. The collector current IC causes the collector junction temperature to rise. The reverse saturation current changes with temperature. There are two techniques to make Q point stable. The other stability factors are. The bias circuit. In second. which provide stability with ICO. temperature sensitive devices such as diodes. resistor biasing circuits are used which allow IB to vary so as to keep IC relatively constant with variations in β dc. which in turn increases ICO. As a result of this growth ICO. also show stability even if β and VBEchanges.73 Fig. IC = β dc B I + (I + β dc ) ICO . S cannot be less than unity. Specifically. 1. It may be possible that this process goes on and the ratings of the transistors are exceeded. ICO and VBE. compensation techniques In first.

S = 101.74 Differentiating with respect to IC. . IB & IC are independent. Therefore and S = 1 + βdc. If βdc=100. which means IC increases 101 times as fast as ICO. Such a large change definitely operate the transistor in saturation. In fixed bias circuit.

If dc increases. Thus the stability of the Q point is better. S is less compared to fixed bias circuit. The feedback term is used because output current ( IC) produces a change in input current ( IB ). Fig. which partially offsets the original increase in β dc. the collector current increases.75 Lecture . the voltage across resistor R E is used to offset the changes in β dc. In this case. In this circuit. shows the emitter feedback bias circuit... The reduced base current result in less collector current. This increases the emitter voltage which decrease the voltage across base resistor and reduces base current.16: Biasing Techniques Emitter Feedback Bias: Fig. . RE is common in input and output circuits. 1. 1 In this case Since IE = IC + IB Therefore.

76 Further,

If IC is to be made insensitive to βdc than

RE cannot be made large enough to swamp out the effects of βdc without saturating the transistor. Collector Feedback Bias: In this case, the base resistor is returned back to collector as shown in fig. 2. If temperature increases. βdc increases. This produces more collectors current. As IC increases, collector emitter voltage decreases. It means less voltage across RB and causes a decrease in base current this decreasing IC, and compensating the effect of βdc.

Fig. 2 In this circuit, the voltage equation is given by

Circuit is stiff sensitive to changes in βdc. The advantage is only two resistors are used. Then,

77 Therefore,

It is better as compared to fixed bias circuit. Further,

Circuit is still sensitive to changes in βdc. The advantage is only two resistors are used. Voltage Divider Bias: If the load resistance RC is very small, e.g. in a transformer coupled circuit, then there is no improvement in stabilization in the collector to base bias circuit over fixed bias circuit. A circuit which can be used even if there is no dc resistance in series with the collector, is the voltage divider bias or self bias. fig. 3. The current in the resistance RE in the emitter lead causes a voltage drop which is in the direction to reverse bias the emitter junction. Since this junction must be forward biased, the base voltage is obtained from the supply through R1, R2 network. If Rb = R1 || R2 equivalent resistance is very ? very small, then VBE voltage is independent of ICO and ∂ IC / ∂ ICO → 0. For best stability R1 & R2 must be kept small.

Fig. 3

78 If IC tends to increase, because of ICO, then the current in RC increases, hence base current is decreased because of more reverse biasing and it reduces IC . To analysis this circuit, the base circuit is replaced by its thevenin's equivalent as shown in fig. 4.

Fig. 4 Thevenin's voltage is

Rb is the effective resistance seen back from the base terminal.

If VBE is considered to be independent of IC, then

79 The smaller the value of Rb, the better is the stabilization but S cannot be reduced be unity. Hence IC always increases more than ICO. If Rb is reduced, then current drawn from the supply increases. Also if RE is increased then to operate at same Q-point, the magnitude of VCC must be increased. In both the cases the power loss increased and reduced η. In order to avoid the loss of ac signal because of the feedback caused by RE, this resistance is often by passed by a large capacitance (> 10µF) so that its reactance at the frequency under consideration is very small. Emitter Bias: Fig. 5, shown the emitter bias circuit. The circuit gets this name because the negative supply VEE is used to forward bias the emitter junction through resistor RE. VCC still reverse biases collector junction. This also gives the same stability as voltage divider circuit but it is used only if split supply is available.

Fig. 5 In this circuit, the voltage equation is given by

and Note that this is not a desirable Q-point location since VBB is very close to VBE.80 Lecture .5K and Rs = 7K .We find Rac = RC || Rload= 500 W and Rdc = RC + RE =1. 1. Variation in VBE therefore significantly change IC. Then . A 2N3904 transistor is used with β = 180.17: Biasing Techniques Example-1 Determine the Q-point for the CE amplifier given in fig. Also determine the Pout(ac) and the dc power delivered to the circuit by the source. if R1 = 1. RE = 100and RC = Rload = 1K . Fig. The value of VCE representing the quiescent value associated with ICQ is found as follows. 1 Solution: We first obtain the Thevenin equivalent.1K.

The various stages of moving ground are shown in fig. However.81 Since the Q-point is on the lower half of the ac load line. e. 2. Moving Ground Around: Ground is a reference point that can be moved around. . the maximum possible symmetrical output voltage swing is The ac power output can be calculated as The power drawn from the dc source is given by The power loss in the transistor is given by The Q-point in this example is not in the middle of the load line so that output swing is not as great as possible. if the input signal is small and maximum output is not required. a small IC can be used to reduce the power dissipated in the circuit. consider a collector feedback bias circuit.g.

82 Fig. . 3. 2 Biasing a pnp Transistor: The biasing of pnp transistor is done similar to npn transistor except that supply is of opposite polarity The various biasing circuits of pnp transistor are shown in fig.

4. calculate IC and VCE Solution: Fig. 3 Example 2: For the circuit shown in fig. 4 .83 Fig.

18: Small Signal CE Amplifiers Small Signal CE Amplifiers: CE amplifiers are very popular to amplify the small signal ac. As long as the input signal is small. This produces fluctuations in the base current and hence in the collector current of the same shape and frequency. The CE amplifier configuration is shown in fig. if the input signal is too large. After a transistor has been biased with a Q point near the middle of a dc load line. At the same time it does not allow the dc to pass through it. . This clips the peaks of the input and the amplifier is no longer linear. Fig. Hence it is also called blocking capacitor. On the other hand. The fluctuations along the load line will drive the transistor into either saturation or cut off.84 Lecture . 1 The coupling capacitor (CC ) passes an ac signal from one point to another. the transistor will use only a small part of the load line and the operation will be linear. ac source can be coupled to the base. The output will be enlarged sine wave of same frequency. The amplifier is called linear if it does not change the wave shape of the signal. 1.

decreases. 2. 2 For example in fig. The Cb capacitor looks like a short to an ac signal and therefore emitter is said ac grounded. except that it couples an ungrounded point to a grounded point. The bypass capacitor Cb is similar to a coupling capacitor.85 Fig.1R is taken as design rule. which is open to dc and shorted for ac. The size of the coupling capacitor depends upon the lowest frequency to be coupled. Similarly R L may be the load resistance or equivalent resistance of a complex network. for lowest frequency XC 0. A bypass capacitor does not disturb the dc voltage at emitter because it looks open to dc current. As a design rule XCb 0. One can use superposition theorem for analysis . For this series reactance XC should be very small compared to series resistance RS. the ac voltage at point A is transmitted to point B. Analysis of CE amplifier: In a transistor amplifier. and current increases until it reaches to its maximum value vin / R. The current in the loop is given by As frequency increases. The simplest way to analyze this circuit is to split the analysis in two parts: dc analysis and ac analysis. The circuit to the left of A may be a source and a series resistor or may be the Thevenin equivalent of a complex circuit.1RE at lowest frequency. . The coupling capacitor acts like a switch. Normally. the dc source sets up quiescent current and voltages. Therefore the capacitor couples the signal properly from A to B when XC<< R. The ac source then produces fluctuations in these current and voltages.

3 For ac equivalent circuits reduce dc voltage sources to zero and open current sources and short all capacitors. Phase Inversion: Because of the fluctuation is base current. reduce all ac voltage sources to zero and open all ac current sources and open all capacitors. The total voltage across any branch is the sum of the dc voltage and ac voltage across that branch.86 AC & DC Equivalent Circuits: For dc equivalent circuit. Fig. 3 dc current and voltages can be calculated. This circuit is used to calculate ac currents and voltage as shown in fig. With this reduced circuit shown in fig. 4 The total current in any branch is the sum of dc and ac currents through that branch. Fig. . meaning it is 180o out of phase with input. 4. The ac output voltage is inverted with respect to the ac input voltage. collector current and collector voltage also swings above and below the quiescent voltage.

causing the collector current to increase. 5 . This produces a large voltage drop across the collector resistor. the voltage output decreases and negative half cycle of output voltage is obtained.87 During the positive half cycle base current increase. Fig. on the negative half cycle of input voltage less collector current flows and the voltage drop across the collector resistor decreases. Conversely. therefore. and hence collector voltage increases we get the positive half cycle of output voltage as shown in fig. 5.

1 Assuming IC = IC(approx).c load line is . In the absence of ac signal. the output circuit voltage equation can be written as The slop of the d. Therefore. therefore Q-point is selected slightly upward. . Fig. this load line passes through Q point. the output impedance becomes RC || RL which is less than (RC +RE). When considering the ac equivalent circuit. the output voltage fluctuations will now be corresponding to ac load line as shown in fig. Therefore ac load line is a line of slope (-1 / ( RC || RL) ) passing through Q point. 1. 2.88 Lecture . means slightly shifted to saturation side.19: Analysis of CE amplifier AC Load line: Consider the dc equivalent circuit fig. Under this condition. Q-point is not in the middle of load line.

3.ie RC (The minus sign is used here to indicate phase inversion) Further vout = .e.(Vin RC) / r'e . Fig. 3 The input voltage appears directly across the emitter diode. Therefore emitter current ie = Vin / r'e. a current source and emitter diode which offers ac resistance r'e. collector current approximately equals emitter current and iC = ie and vout = . 2 Voltage gain: To find the voltage gain. The ac equivalent circuit is shown in fig. consider an unloaded CE amplifier. Since. The transistor can be replaced by its collector equivalent model i.89 Fig.

v in = ie r'e ≈ βi β r'e zin (base) = β r'e. The simplified ac equivalent circuit is shown in fig. Zin = R1 || R2 || β r'e The Thevenin voltage appearing at the output is vout = A vin The Thevenin impedance is the parallel combination of RC and the internal impedance of the current source. . In a normal frequency range of an amplifier. 4. the input impedance zin is the parallel combination of R1 . therefore it has an infinite internal impedance. The collector current source is an ideal source. The input impedance of an amplifier determines how much current the amplifier takes from the ac source.90 Therefore voltage gain A = vout / vin = -RC / r'e The ac source driving an amplifier has to supply alternating current to the amplifier. zout = RC. iin are peak to peak values or rms values The impedance looking directly into the base is symbolized zin (base) and is given by Z in(base) = vin / ib . Since. R2 and β r'e. From the ac equivalent circuit. where all capacitors look like ac shorts and other reactance are negligible. the ac input impedance is defined as zin= vin/ iin Where vin.

Fig. 4 Example-1: Select R1 and R2 for maximum output voltage swing in the circuit shown in fig.91 Fig. V'CC = 2 VCEQ The quiescent value for VCE is the given by . 5. 5 Solution: We first determine ICQ for the circuit For maximum swing.

ignoring the non-linearity's at saturation and cutoff. The maximum output voltage swing. From the manufacturer's specification. we find R1 and R2. β for the 2N3904 is 180.92 VCEQ= (3.13 mA) (500 ) = 1.87 mW . The maximum average power dissipated in the transistor is P(transistor)= VCEQ ICQ = (1.1 βRE. 6.13V.1 x 100) + 0. would then be The load lines are shown on the characteristics of fig.56 V The intersection of the ac load line on the vCE axis is V'CC = 3.56 (V)) (3.044 V Since we know VBB and RB.13 x 10-3) (1. RB = 0.7 = 1.1(180 )(100) = 1. So. Fig.13 mA) =4.8 K VBB = (3. RB is set equal to 0. 6 The maximum power dissipated by the transistor is calculated to assure that it does not exceed the specifications.

a resistance rE is inserted in series with the emitter and therefore emitter is no longer ac grounded. and the emitter is bootstrapped to the base for ac as well as for dc. To make it stable. fig .93 This is well within the 350 mW maximum given on the specification sheet. the collector circuit is given by . In this case. If rE is much greater than r'e almost all of the ac input signal appears at the emitter. But in many applications we need a stable voltage gain is required. 7 Because of this the ac emitter current flows through rE and produces an ac voltage at the emitter. The maximum conversion efficiency is The swamped Amplifier: The ac resistance of the emitter diode r'e equals 25mV / IE and depends on the temperature. a change in voltage is acceptable. In some applications. Any change in r'e will change the voltage gain in CE amplifier.7. Fig.

If swamping is heavy. .94 Now r'e has a less effect on voltage gain. voltage gain varies with temperature. swamping means rE >> r'e If swamping is less. then gain reduces very much.

1 Solution: The maximum voltage across the amplifier is 10 V since the power supply can be visualized as a 10V power supply with a ground in the center. Determine the resistor values of the bias circuitry..1 with two power supplies.g.7 V. The output load is 2KΩ. If this leads to a contradiction. unobtainable resistor values).1 β RE = 0. Thus. We will have to select the value for RC and we are really not given enough information to do so. Selecting RE as 400Ω will not appreciably reduce the collector current yet it will help in maintaining a reasonable value of VBB. or ?bad? component values (e. Let choose RC = Rload. the maximum undistorted output voltage swing. the ground has no significance to the operation of the amplifier since the input and output are isolated from the power supplies by capacitors. we can come back and modify our choice. Obtain an overall gain of |A V | ≥ 100 and maximum output voltage swing.20: Design of Amplifier Example -1 (Common Emitter Amplifier Design) Design a common-emitter amplifier with a transistor having a β =200 and VBE = 0. Let Rsource= 100 Ohms. We will have to (arbitrarily) select a value of RB or RE. RB = 0. We don't have enough information to solve for RB ? we can't use the bias stability criterion since we don't have the value of RE either. and the stage voltage gain. vsource.1 (200)(400) = 8 K Ω . In this case. Fig. Rsource is the resistance associated with the source. Use the CE configuration shown in fig.95 Lecture . Let us select a value for RE that is large enough to obtain a reasonable value of VBB.

it has a low input impedance.29 V Now we can determine the gain of the amplifier itself. and VBE = -0. VCC = -24V. The bias resistors are determined by Since we designed the bias circuit to place the quiescent point in the middle of the ac load line. Av = -10. Using voltage division. Example-2 (Emitter-Resistor Amplifier Design) Design an emitter-resistor amplifier as shown in fig. The value of Rin can be obtained as Thus the overall gain of the amplifier is This shows that the common-emitter amplifier provides high voltage gain. we will use Note that we are carrying out our calculations to four places so that we can get accuracy to three places. we can determine the gain of the overall circuit.7 V. 2 to drive a 2 KΩ load using a pnp silicon transistor. Determine all element values and . it is very noisy.94 x 10-3 ) (2 K Ω || 2 K Ω ) =5. we can use Vout(undistorted p-p) 1. However. β = 200. and it does not have the stability of the emitter resistor common emitter amplifier.8 (2.96 To insure that we have the maximum voltage swing at the output.

Therefore. 2 Solution: (a) RC = Rload We use the various equations derived in previous lecture in order to derive the parameters of the circuit. RC = Rload RC = 0. From the voltage gain. 3.97 calculate Ai. we can solve for R'E. So R'E = re + RE = 100 Ω We can find the quiescent value of the collector current IC form the collector-emitter loop using the equation for the condition of maximum output swing.1 Rload RC = 10 Rload Fig. Rin. . ICQ and the maximum undistorted symmetrical output voltage swing for three values of RC as given below: 1. 2.

91K W .886 V R1 =3. Since we now know β and RE.7 V Ai = -1.4 mA r'e = 0. we follow the steps of part (a) to find RC =20 K Ω ICQ =-1.52 V R1 = 2.64K Ω VBB = -0.5 V Thus current gain Ai = -9.84 V (C) RC =10 Rload Ri = 390 Ω R2 =4.1 and input impedance Rin = 1.45 Ω RB = 360 Ω VBB = -1.14 K Ω R2 = 3.64 Rin = 327 Ω Once again. We can use the design guideline.8 ICQ (Rload || RC ) = 13.9 V Ai =-14.07 mA r'e = 24.28K Ω R2 = 85.5 Rin = 2.6 K Ω The maximum undistorted symmetrical peak to peak output swing is then Vout (P-P) = 1.2 Ω RB = 3. the biasing circuitry can be designed in the same manner and given by VBB = -1.98 This is small enough that we shall ignore it to find that RE = 100 Ω.1 Rload we repeat the steps of parts (a) to find RC =200 Ω ICQ =-57.1 β RE = 2 k Ω As designed earlier. RB = 0.7K Ω vout(p-p) = 18.6K Ω vout(p-p) = 3.82 K Ω (b) RC = 0.

8 V 3. it may be necessary to do additional analysis to find the optimum ratio of RC to Rload.3 (Capacitor-Coupled Emitter-Resistor Amplifier Design) Design an emitter-resistor amplifier as shown in fig. ICQ RC = Rload RC = 0. A pnp transistor is used and maximum symmetrical output swing is required.5 V 20. this choice will provide performance that meets specifications. In some applications. β =200 and R load = 1K Ω.99 We now compare the results obtained Table-I for the purpose of making the best choice for RC. Fig.64 -14. It can be used as a guide to develop a reasonable designs. Example.9 V Table .5 Rin 1. . In most cases.07mA Ai -9. RC = Rload has the most desirable performance in the CE amplifier stage. 3 Solution: As designed earlier.1 Rload RC = 10 Rload -7.4 mA -1. 3 with AV =-10.1 Comparsion for the three selections of RC It indicates that of the three given ratios of RC to Rload.5 mA -57.1 -1. we shall chose RC = Rload = 10 kΩ.91W vout(p-p) 13.82K W 327 W 2.

We need to know the value of r'e to fine RE. we find R'E= 50 Ω.1 (200) (46. Since is no such specification. we would use it to solve for the value of RB. we use the expression RB =0. and .1 β RE = 0. The equation is The quantity. Substituting AV. so RE = R'E) Rac = RE + RC || Rload = 550 Ω Rdc = RE + RC = 1050 Ω Now. We first find Rac and Rdc.100 The voltage gain is given by where R'E= RE + r'e. and then calculate the Q point as follows (we assume r'e is small.6) = 932 Ω Then continuing with the design steps. is found as follows Then RE = 50 . Rload and RC in this equation. r'e .. the first step is to calculate the quiescent collector current needed to place the Q-point into the center of the ac load line (i.67 Ω If there were a current gain or input resistance specification for this design. maximum swing).e.re = 46.

4. The maximum undistorted peak to peak output swing is given by 1. Fig. 4 .101 The last equality assumes that rO is large compared to RC.8 | ICQ | ( RC || Rload )=1.75 V The power delivered into the load and the maximum power dissipated by the transistor are found as The load lines for this circuit are shown in fig.8 ( 0.0075 ) ( 500 ) = 6.

vout = vin . 1 Therefore.102 Lecture . A CC amplifier is like a heavily swamped CE amplifier with a collector resistor shorted and output taken across emitter resistor. vout = 1. vout = 2.3V.21: Common Collector Amplifier Common Collector Amplifier: If a high impedance source is connected to low impedance amplifier then most of the signal is dropped across the internal impedance of the source.vBE Fig. therefore collector is ac grounded. Fig. this circuit is also called emitter follower. there is no phase inversion between input and output.3V If vin is 3V. When input source drives the base. The output circuit voltage equation is given by VCE = VCC ? IE RE . As vin increases. shows a common collector (CC) amplifier. To avoid this problem common collector amplifier is used in between source and CE amplifier. output appears across emitter resistor. 1. Since vout follows exactly the vin therefore. because VBE is very small. Since there is no resistance in collector circuit. It is also called grounded collector amplifier. If vin is 2V. vout increases. It increases the input impedence of the CE amplifier without significant change in input voltage.

. vin = ie (RE + r'e ) Therefore. 1. 2. 4. The emitter is replaced by ac resistance r'e.103 Since IE ≈ IC ∴ IC = (VCC ? VCE ) / RE This is the equation of dc load line. The dc load line is shown in Fig. it is a unity gain amplifier. 3. Fig. The practical emitter follower circuit is shown in Fig. shows an emitter follower driven by a small ac voltage. Voltage gain: Fig. A = RE / ( RE +r'e ) Since r'e << RE Fig. 3 ∴ A≈ 1. The input is applied at the base of transistor and output is taken across the emitter resistor. Therefore. 2 The ac output voltage is given by vout = RE ie and. shows the ac equivalent circuit of the amplifier. Fig.

some of the ac signal is lost across the source resistor. Because of the biasing resistor and input impedance of the base.104 Fig. 4 The ac source (vS) with a series resistance RS drives the transistor base. 5 The input impedance at the base is given by . Fig. The ac equivalent circuit is shown in Fig. 5.

5. it becomes a source vin and a series resistance (R1 || R2 || RS ) as shown in Fig. zin ≈ R1 || R2 Therefore input impedance is very high. Thus. Fig. 6. zin = R1 || R2|| β (r'e + RE) Since β RE is very large as compared to R1 and R2. 6 .105 The total input impedance of an emitter follower includes biasing resistors in parallel with input impedance of the base. Applying Thevenin's theorem to the base circuit of Fig.

VCEQ = VCC ? ICQ RE = 9.106 Example 1: Find the Q-point of the emitter follower circuit of fig.67 K Ω From the bias equation we have Example . We found that the quiescent collector current is 4.5 V . Solution: The Q-Point location has already been calculated in Example-1. (RE || RLoad) = 2(4.2 Find the output voltage swing of the circuit of fig. Continuing the analysis. The Output voltage swing = 2 . 7.03 V V'CC = VCEQ + ICQ (RE || RLoad ) = 10. Fig. 7 Solution: We first find the Thevenin's equivalent of the base bias circuitry.95 x 10-3) (300) = 2.97V This is less than the maximum possible output swing. 7 with R1 = 10 KΩ and R2 = 20 KΩ. IC peak . Assume the transistor has a β of 100 and input capacitor C is very-very large.95 mA. RB = R1 || R2 = 6.

8. Fig. 8 .107 The load lines for this problem are shown in Fig.

.108 Lecture . Fig. If r' e(1) is also neglected then the input impedance of 1 becomes. The dc emitter current of the second stage is IE2 = (VTH ? 2 vBE ) / (RE ) The dc emitter current of the first stage that is the base current of second stage is given by IE1 ≈ IE2 / β 2 If r'e(2) is neglected then input impedance of second stage is Zin (2) = β2 RE This is the impedance seen by the first transistor. The overall gain is close to unity. The voltage divider produces VTH to the input base. The main advantage of Darlington amplifier is very large increase in input impedence and an equal decrease in output impedance .22: Power Amplifier Darlington Amplifier: It consists of two emitter followers in cascaded mode as shown in fig. 1. 1 DC Analysis: The first transistor has one VBE drop and second transistor has second VBE drop.

Example-1 Design a single stage npn emitter follower amplifier as shown in fig. so the approximate input impedance of Darlington amplifier is Zin = R1 || R2 Output impedance: The Thevenin impedance at the input is given by RTH = RS || R1 || R2 Similar to single stage common collector amplifier.109 Zin (1) = β1 β2 RE which is extremely high because of the products of two betas. 2 with β =60. . t he output impedance of the amplifier is very small.7V. Therefore. Rsource =1 KΩ. VBE =0. the output impedance of the two stages zout(1) and zout(2) are given by. and VCC= 12V. Determine the circuit element values for the stage to achieve Ai = 10 with a 100 Ω load.

This yields a third equation. 2 Solution: We must select R1. RE = Rload= 100 W Now finding the load line slopes. This is usually the case for emitter follower circuits. These two equations are specified by the current gain and the placement of the Q-point. We could derive a similar result for RE and Rload in the CC amplifier. Using the equation for current gain we find Everything in this equation is known except RB.110 Fig. R2 and RE. We shall therefore begin by constraining REto be equal to Rload. it can be ignored. but we only have two equations. Rac = RE || Rload =50 W Rdc = RE = 100 V Since the amplitude of the input is not specified. We solve for RB with the result RB = 1500 W VBB is found from the base loop. the best choice for a CE amplifier is to make R C =R load. We now find the value of r'e Since re is insignificant compared to RE || Rload. As discussed earlier. we choose the quiescent current to place the Qpoint in the center of the ac load line for maximum swing. .

we find R1 = 13.8 K Ω R2 = 1. Ptransistor. Pload. RE = 400Ω VBE = 0.68 K Ω The voltage gain of the CC amplifier is approximately unity.2 V The power dissipated in the load. are Example-2 (Capacitor-Coupled CB Design) Design a CB amplifier using an npn transistor as shown in fig. The input resistance is given by Rin = RB || [ β ( R E || Rload ) ] = 1 kΩ The output resistance is given by The maximum peak to peak symmetrical output swing is given by Vout(p-p) ? 1. . Rload= 2KΩ.7V. and the maximum power required of the transistor. VCC= 24 V.111 Continuing with the design as discussed earlier. Design this amplifier for a voltage gain of 20.8 | ICQ| (RE || Rload ) = 7. 3 with β = 100.

40 KΩ For maximum swing. 3 Solution: Since there are fewer equations than there are unknowns. we set ICQ to We now find that The current gain is given by and input impedance is given by . so we set RC = Rload = 2 K Ω Then we have. we need an additional constraint. Rac = 1.40 K Ω and Rdc =2.112 Fig.

113 We use the bias equation to find the parameters of the input bias circuitry. The bias resistors are then given by The maximum peak-to-peak undistorted output voltage is Vout(peak-peak) = 1.8 | ICQ | (Rload || RC) = 11.3 V .

de-rating (i. 1. we assume periodic waveforms where T is the period.114 Lecture .e. providing a "safety margin" from derived values) is used to improve the reliability of a device. Fig. Frequently. we must let T approach infinity in equation E-1.. 1. 1 Derivation of Power Equations Average power is calculated as follows: For dc: (E-1) For ac: (E-2) In the ac equation. This is similar to using safety factors in the design of mechanical systems where the system is designed to withstand values that exceed the maximum. Designers normally select components having the lowest power handling capability suitable for the design. Power considerations also affect transistor selection.23: Power Considerations Power considerations Power rating is an important consideration in selecting bias resistors since they must be capable of withstanding the maximum anticipated (worst case) power without overheating. Looking at the CE amplifier of fig. the . If the signal is not periodic. Consider a common emitter amplifier circuit shown in fig.

respectively. (E-6) In most practical circuits. IR2 R2 + IR1 R1 = VCC (E-5) These two equations can be solved for the currents to yield. We will therefore assume that the power supplied by the source is approximately equal to the power dissipated in the transistor and in R1 and R2. The last equality of Equation (E-7) assumes that the average value of ic(t) is zero. Kirchhoff's current law (KCL) yields a relationship between these two currents and the base quiescent current. IR1 = IR2 ? IB (E-4) KVL yields the base loop equation (assuming VEE = 0).115 power supplied by the power source is dissipated either in R1 and R2 or in the transistor (and its associated collector and emitter circuitry). The average power dissipated by the transistor itself (not including any external circuitry) is (E-8) For zero signal input. For example. the power due to IB is negligible relative to the power dissipated in the transistor and in R1 and R2. this becomes P(transitor) = VCEQ ICQ Where VCEQ and ICQ are the quiescent (dc) values of the voltage and current. it applies if the input ac signal is a sinusoidal waveform. . The source current has a dc quiescent component designated by iCEQ and the ac component is designated by ic(t). This quantity is given by (E-7) Where the source voltage VCC is a constant value. This is a reasonable assumption. The power in R1 and R2 (the bias circuitry) is given by (E-3) where IR1 and IR2 are the (downward) currents in the two resistors.

We define conversion efficiency as .e. the transistor is selected for zero input signal so it will handle the maximum (worst case) power dissipation of VCEQ ICQ. where we note that the frequency of the instantaneous power sinusoid is 2ω. 2 Putting these time functions in Equation (E-7) yields the power equation. This is shown in fig. the transistor will dissipate an average power between VCEQ ICQ and one half of this value.. Depending on the amplitude of the input signal. We will need a measure of efficiency to determine how much of the power delivered by the source appears as signal power at the output. Therefore.116 For an input signal with maximum possible swing (i. Fig. Q-point in middle and operating to cutoff and saturation). 2. (E-10) From the above derivation. we see that the transistor dissipates its maximum power (worst case) when no ac signal input is applied.

The output of one amplifier is the input to another stage. The load on the first amplifier is the input resistance of the second amplifier. 3 In fig. In practice. The two power levels of input and output of an amplifier are compared on a logarithmic scale rather than linear scale. Fig. The number of bels by which the output power P2 exceeds the input power P1 is defined as . the overall voltage gain is ABC. To represent the gain of the cascade amplifier. in designing or analyzing multistage amplifier. the overall voltage gain is the product of the voltage gain of each stage.117 Cascade Amplifier: To increases the voltage gain of the amplifier. we start at the output and proceed toward the input. In this way the overall voltage gain can be increased. multiple amplifier are connects in cascade. The various stages need not have the same voltage and current gain. That is. when number of amplifier stages are used in succession it is called a multistage amplifier or cascade amplifier. 3. the voltage gains are represents in dB. The amount of gain in a stage is determined by the load on the amplifier stage. 3. the earlier stages are often voltage amplifiers and the last one or two stages are current amplifiers. The voltage amplifier stages assure that the current stages have the proper input swing. A n-stage amplifier can be represented by the block diagram as shown in fig. which is governed by the input resistance to the next stage. Therefore.

The grounded emitter stage amplifies the signal. Otherwise. In this case the signal developed across the collector resistor of each stage is coupled into the base of the next stage. . 1. An ac source with a source resistance R S drives the input of an amplifier.118 Because of dB scale the gain can be directly added when a number of stages are cascaded. Also the dc voltage at the output of one stage should not be permitted to go to the input of the next.RC coupling: Fig. The cascaded stages amplify the signal and the overall gain equals the product of the individual gains. 1. the biasing of the next stage are disturbed. The three couplings generally used are. 4 shows RC coupling the most commonly used method of coupling from one stage to the next. which is then coupled to next CE stage the signal is further amplified to get larger output. Types of Coupling: In a multistage amplifier the output of one stage makes the input of the next stage. Normally a network is used between two stages so that a minimum loss of voltage occurs when the signal passes through this network to the next stage. 2. RC coupling Impedance coupling Transformer coupling. 3.

4 The coupling capacitors pass ac but block dc Because of this the stages are isolated as for as dc is concerned.c. As the frequency keeps decreasing. This is necessary to avoid shifting of Q-points. a point is reached at which capacitors no longer look like a. These bypass capacitors also place a lower limit on the frequency response. These amplifiers are suitable for frequencies above 10 Hz. The drawback of this approach is the lower frequency limit imposed by the coupling capacitor. . At this frequency the voltage gain starts to decrease because of the local feedback and the overall gain of the amplifier drops significantly. Without them. shorts.119 Fig. The bypass capacitors are needed because they bypass the emitters to ground. the voltage gain of each stage would be lost.

Primed variables denote output stage quantities and unprimed variables denote input stage quantities. 2. 1. This equivalent is shown in fig.24: Cascade Amplifiers Example . Fig. Fig.1 Determine the current and voltage gains for the two-stage capacitor-coupled amplifier shown in fig. 1 Solution: We develop the hybrid equivalent circuit for the multistage amplifier. 2 Calculations for the output stages are as follows .120 Lecture .

2 by extracting four current dividers as shown in fig. can be found by applying the equations derived earlier. Alternatively. Ai. we analyze fig. The input resistance is determined as: The current gain. 3.121 For the input stage. . where the first stage requires using the correct value for Rload derived form the value of Rin to the next stage.

The input resistance of the second stage is The current in R'in is iload and is given by Again.122 Fig. Thus. 3(c): The current gain is then Ai =927 . i load is current-divided at the input to the second stage. 3 The current division of the input stage is The output of the first stage is coupled to the input of he second stage in fig. 3(b). The output current is found from fig.

we find the voltage gain: Impedance Coupling: At higher frequency impedance coupling is used. inductors pass dc but block ac. 4 The advantage is that no signal power is wasted in collector resistors. It is suitable at radio frequency above 20 KHz. As the frequency increases. There is no power loss in primary winding because of low resistance. XL approaches infinity and each inductor appears open. The secondary winding is used to give input to next stage. .123 Now using the gain impedance formula. There is no coupling capacitor. 5. Fig. These RF chokes are relatively expensive and their impedance drops off at lower frequencies. the inductors are called RFchokes. The dc isolation between the two stages provided by the transformer itself. 4. the resistors RC is replaced by the primary winding of the transformer. The collector resistance is replaced by an inductor as shown in fig. When used in this way. Fig. Transformer Coupling: In this case a transformer is used to transfer the ac output voltage of the first stage to the input of the second stage. In other words.

the frequencies are 54 to 216 MHz. Tuned Transformer Coupling: In this case a capacitor is shunted across primary winding to get resonance as shown in fig. In AM radio receivers. 6. This is the principle behind tuning in a radio station or TV channel. 6 . Transformer coupling is still used in RF amplifiers. RF signal have frequencies 550 to 1600 KHz. 5 At low frequency the size and cost of the transformer increases.124 Fig. At these frequency the size and cost of the transformer reduces. At this frequency the gain is maximum and at other frequencies the gain reduces very much. This allows us to filter out all frequencies except the resonant frequency and those near it. In TV receivers. CS capacitor is used to make other point of transformer grounded. so that ac signal is applied between base and ground. Fig.

We note that re is sufficiently small to be neglected. . Fig. Since the problem statement requires a current gain of 80. solving for RB yields Now solving for the bias resistors. Then. 7 for a current gain of Ai = 80. We use the equations from Chapter 5 to find the base resistance RB.2 Design a transformer-coupled amplifier as shown in fig. the amplifier must have a current gain of 10 because the transformer provides an additional gain of 8.125 Example . Find the power supplied to the load and the power required from the supply. 7 Solution: We first use the design equation to find the location of the Q-point for maximum output swing.

The efficiency is the ratio of the load to source power. . The power delivered by the source is given by The power dissipated in the load is We have restricted operation to the linear region by eliminating 5% of the maximum swing near cutoff and saturation.126 The design is now complete.

The gain is constant for a limited band of frequencies. shows frequency response curve of a RC coupled amplifier. 2. These capacitors can no longer be replaced by the short circuit approximation. Fig. This signal may be obtained from anywhere e.g. But when the frequency is low. radio or TV receiver circuit. 1. 2 Fig. On both sides of the mid frequency range. If the loudspeakers are to reproduce the sound faithfully. the capacitors are ac shorted so the input voltage appears directly acrossr'e but at low frequency the XC is significant and some voltage drops . e. 3. AVM. 1 Fig. the amplifier used must amplify all the frequency components of signal by same amount. assuming capacitors are offering some impedance. The ac equivalent is shown in fig.127 Lecture . Consider an RC coupled amplifier circuit shown in fig.g. This range is called midfrequency band and gain is called mid band gain. In mid-frequency band. If it does not do so. Such a signal is not of a single frequency. In mid band frequency range. For very low and very high frequencies the gain is almost zero. the coupling capacitors and bypass capacitors are as good as short circuits. The curve is usually plotted on a semilog graph paper with frequency range on logarithmic scale so that large frequency range can be accommodated. First consider coupling capacitor. But it consists of a band of frequencies. the output of the loudspeaker will not be the exact replica of the original sound.25: Frequency Response of Amplifier Frequency curve of an RC coupled amplifier: A practical amplifier circuit is meant to raise the voltage level of the input signal. the gain decreases. When this happen then it means distortion has been introduced by the amplifier. from 20 Hz to 20 KHz.

Now the emitter is not ac grounded. an ac voltage is developed i1 * RE. It would not be exactly 180o but decided by the reactance. Due to ac current i1 in RE. The input vin at the base decreases. Fig. Thus output voltage reduces. The XC reactance not only reduces the gain but also change the phase between input and output. A current i1 passes through RE and rest of the current passes through C. With the polarity marked at an instant. The function of this capacitor is to bypass ac and blocks dc The impedence of this capacitor in mid frequency band is very low as compared to RE so it behaves like ac short but as the frequency decrease the XCE becomes more and no longer behaves like ac short. . 3 Similarly at low frequency. The ac emitter current i. At zero frequency. Thus the effective VL voltage is given by Vbe = Vs ? RE. The voltage across RL also reduces because some voltage drop takes place across XC. the capacitors are open circuited therefore output voltage reduces to zero.128 across XC.e. as shown in fig. The lower the frequency the more will be XC and lesser will be the output voltage. Thus decreasing output voltage. The other component due to which gain decreases at low frequencies is the bypass capacitor. output capacitor reactance also increases. divides into two parts i1 and i2. 4.

This feedback effect is more. Fig. 5. As the frequency of the input signal increases. The other factor responsible for the reduction in gain at higher frequencies is the presence of various capacitors as shown in fig. negative feedback takes place in the circuit and the gain decreases. The output also reduces. The lower the frequency. the lesser will be the gain. Thus reducing the voltage gain of the amplifier at higher frequencies as shown in fig. Because of this. This reduction in gain is due to negative feedback. 4 Thus the effective voltage input is reduced. Firstly the of the transistor decreases at higher frequency.129 Fig. 6. They are not physically connected but inherently present with the device. again the gain of the amplifier reduces. 5 The capacitor Cbc between the base and the collector connects the output with the input. when Cbc provides a path for higher frequency ac currents .

130 The capacitance Cbe offers a low input impedance at higher frequency thus reduces the effective input signal and so the gain falls. Similarly, Cce provides a shunting effect at high frequencies in the output side and reduces gain of the amplifier. Besides these junction capacitances there are wiring capacitance CW1 and CW2. These reactance are very small but at high frequencies they become 5 to 20 p.f. For a multistage amplifier, the effect of the capacitances Cce,CW1 and CW2 can be represented by single shunt capacitance. CS = CW1 + CW2 +Cce. At higher frequency, the capacitor CS offers low input impedance and thus reduces the output.

Fig. 6 Bandwidth of an amplifier: The gain is constant over a frequency range. The frequencies at which the gain reduces to 70.7% of the maximum gain are known as cut off frequencies, upper cut off and lower cut off frequency. fig. 7, shows these two frequences. The difference of these two frequencies is called Band width (BW) of an amplifier. BW = f2 ? f1.

131

Fig. 7 At f1 and f2, the voltage gain becomes 0.707 Am(1 / 2). The output voltage reduces to 1 / 2 of maximum output voltage. Since the power is proportional to voltage square, the output power at these frequencies becomes half of maximum power. The gain on dB scale is given by 20 log10(V2 / V1) = 10 log 10 (V2 / V1)2 = 3 dB. 20 log10(V2 / V1) = 20 log10(0.707) =10 log10 (1 / 2)2 = 10 log10(1 / 2) = -3 dB. If the difference in gain is more than 3 dB, then it can be detected by human. If it is less than 3 dB it cannot be detected. Direct Coupling: For applications, where the signal frequency is below 10 Hz, coupling and bypass capacitors cannot be used. At low frequencies, these capacitors can no longer be treated as ac short circuits, since they offer very high impedance. If these capacitors are used then their values have to be extremely large e.g. to bypass a 100 ohm emitter resistor at 10 Hz, we need a capacitor of approximately 1600 F. The lower the frequency the worse the problem becomes. To avoid this, direct coupling is used. This means designing the stages without coupling and bypass capacitors, so that the direct current is coupled as well as alternating current. As a result, there is no lower frequency limit. The amplifier enlarges the signal no matter have low frequency including dc or zero frequency. One Supply Circuit: Fig. 8, shows a two stage direct coupled amplifier, no coupling or bypass capacitors are used. With a quiescent input voltage 1.4 V, emitter voltage = 1.4 - 0.7 = 0.7 V

132

The output varies from +6V to +8V.

Fig. 8 The main disadvantage is variation in transistor characteristic with variation in temperature. This causes IC and VC to change. Because of the direct coupling the voltage changes are coupled from one stage to next stage, appearing at the final output as an amplified voltage. The unwanted change is called drift.

133 Grounded Reference Input For the above amplifier, we need a quiescent voltage of 1.4V. In most applications, it is necessary to have grounded reference input one where the quiescent input voltage is 0 V, as shown in fig. 9.

Fig. 9 The quiescent V CE of the first transistor is only 0.7V and the quiescent of the second transistor is only 1.4V. Both the transistors are operating in active region because VCE(sat) is only 0.1 volt. The input is only in mV, which means that these transistors continue to operate in the active region when a small signal is present.

h12. The positive directions of voltages and currents are shown in fig. 1.134 Lecture .26: h-Parameters Small signal low frequency transistor Models: All the transistor amplifiers are two port networks having two voltages and two currents. Fig. =hr = fraction of output voltage at input with input open circuited or reverse voltage gain with input open circuited to ac (dimensions). The equations can be written as where h11. . = hi = input impedance with output short circuit to ac. h21 and h22 are called h-parameters. If the input current i1 and output voltage v2 are taken independent then other two quantities i2 and v1 can be expressed in terms of i1 and V2. 1 Out of four quantities two are independent and two are dependent.

135 = hf = negative of current gain with output short circuited to ac. iB. hfe . 2.h ib are h parameters of common emitter and common collector amplifiers Using two equations the generalized model of the amplifier can be drawn as shown in fig. e. This is also known as forward short circuit current gain. = ho = output admittance with input open circuited to ac. iC .vC. then suffixes e.b or c are also included. and vB represent total instantaneous currents and voltages iB and vC can be taken as independent variables and vB.g. If these parameters are specified for a particular configuration. IC as dependent variables. . The current entering the load is negative of I2. 2 The hybrid model for a transistor amplifier can be derived as follow: Let us consider CE configuration as show in fig. 3. Fig. The variables.

The Δ v B.vC . Using Taylor 's series expression. Δ vC. The partial derivatives are taken keeping the collector voltage or base current constant. and neglecting higher order terms we obtain. 3 vB = f1 (iB .iC. . Δ iB.136 Fig. Δ iC represent the small signal (incremental) base and collector current and voltage and can be represented as vb .vC ) IC = f2 ( iB . vC ). The model for CE configuration is shown in fig. 4.ib .

Fig.137 Fig. shows the output characterisitcs of CE amplifier. 5 The current increments are taken around the quiescent point Q which corresponds to iB = IB and to the collector voltage VCE = VC .parameters: To determine the four h-parameters of transister amplifier. Fig. 5. input and output characteristic are used. The output characteristic depicts the relationship between output voltage and output current with input current as parameter. 4 Determination of h . Input characteristic depicts the relationship between input voltage and input current with output voltage as parameter.

Typical CE h-parametersof transistor 2N1573 are given below: hie = 1000 ohm. The parameter hre can be obtained from the ratio (VB2? V B1 ) and (VC2? V C1 ) for at Q.138 The value of hoe at the quiescent operating point is given by the slope of the output characteristic at the operating point (i. hie is the slope of the appropriate input on fig. 6. Fig.e.5 * 10 ?4 hfe = 50 hoe = 25 A / V . hre = 2. at the operating point (slope of tangent EF at Q). slope of tangent AB). 6 A vertical line on the input characteristic represents constant base current.

27: h-parameters Analysis of a transistor amplifier using h-parameters: To form a transistor amplifier it is only necessary to connect an external load and signal source as indicated in fig. 1 Consider the two-port network of CE amplifier. The quantities of interest are the current gain. Ai is defined as the ratio of output to input currents. and output impedence. Fig. voltage gain.139 Lecture . 1 and to bias the transistor properly. Fig. 2. (Phasor notations are used assuming sinusoidal voltage input). RS is the source resistance and ZL is the load impedence h-parameters are assumed to be constant over the operating range. . The ac equivalent circuit is shown in fig. 2 Current gain: For the transistor amplifier stage. input impedence.

1' ) is the input impedence Zi Voltage gain: The ratio of output voltage to input voltage gives the gain of the transistors.140 Input Impedence: The impedence looking into the amplifier input terminals ( 1. Output Admittance: It is defined as .

Consider input source to be a current source IS in parallel with a resistance RS as shown in fig. 3 In this case. Fig. 3.141 Av is the voltage gain for an ideal voltage source (Rv = 0). overall current gain AIS is defined as .

These parameters may be converted into CC and CB values. Fig. 4 hrc in terms of CE parameter can be obtained as follows.142 To analyze multistage amplifier the h-parameters of the transistor used are obtained from manufacture data sheet. 4 For CE transistor configuaration Vbe = hie Ib + hre Vce Ic = h fe Ib + hoe Vce The circuit can be redrawn like CC transistor configuration as shown in fig. 5. The manufacture data sheet usually provides h-parameter in CE configuration. For example fig. Vbc = hie Ib + hrc Vec Ic = hfe Ib + hoe Vec .

143 Fig. 5 .

Fig.1 For the circuits shown in fig. hfe = 50.28: h-parameters Example . 2. h oc= 25 A / V. hfe = -51. hre = 6 * 10 -4. (CE?CC configuration) various h-parameters are given h ie = 2K. hic = 2K. Fig. 2 . 1 The small signal model of the transistor amplifier is shown in fig. hre = 1.144 Lecture . 1. hoc = 25 A / V.

the collector resistance of first stage is shunted by the input impedence of last stage. The effective source resistance R'S2 for the second stage is R01 || RC1 .65K . Therefore the analysis is started with last stage. It is convenient. input impedence and voltage gain. Thus RS2 = R'01 = 4. Then output impedence is calculated starting from first stage and moving towards end. to first compute current gain.145 In the circuit.

146 Lecture . and Overall voltage gain of the amplifier is given by . 3.24: Frequency response Overall current gain of the amplifier is Ai and is given by The equivalent circuit of the amplifier is shown in fig. Therefore. From the circuit it is clear that the current ic1 is divided into two parts.

Ic = hfe IB . 3 Simplified common emitter hybrid model: In most practical cases it is appropriate to obtain approximate values of A V .01.h re ≈ 0. this voltage may be neglected in comparison with h ic Ib drop across h provided RL is not very large. 4 shows the CE amplifier equivalent circuit in terms of h-parameters Since 1 / hoe in parallel with RL is approximately equal to RL if 1 / hoe >> RL then hoe may be neglected. If load resistance RL is small than hoe and hre can be neglected. How the circuit can be modified without greatly reducing the accuracy. 4 Since h fe. Fig. A i etc rather than calculating exact values. Under these conditions. hre vc = hre Ic RL = hre hfe Ib RL . Fig.147 Fig. ie .

I C = 0. the calculations for CC and CB can be done. To stabilize voltage gain A V of each stage. On the same lines. The resistor provides negative feedback and provide stabilization. it should be independent of hfe. even for same type of transistor. 5. A simple and effective way is to connect an emitter resistor Re as shown in fig. True value depends upon RS and lies between 40 K and 80K. . Fig. When Vs = 0. hfe may vary widely from device to device. aging and the operating point. Moreover. CE amplifier with an emitter resistor: The voltage gain of a CE stage depends upon hfe. 5 An approximate analysis of the circuit can be made using the simplified model. and an external voltage is applied at the output we fined Ib = 0. This transistor parameter depends upon temperature.148 Output impedence seems to be infinite.

The output resistance is infinite for the .149 Subject to above approximation A approximate model. V is completely stable.

But these amplifier need large voltage input. 1. a power amplifier does not truly amplify the signal power but converts the dc power into signal power. Therefore. Consider the case of radio receiver. DC and AC load lines: Consider a CE amplifier as shown in fig. In multistage amplifier. Fig.2 ohm). therefore. Thus. In these amplifies. the purpose of a radio receiver is to produce the transmitted programmes with sufficient loudness. power amplifiers are used to put sufficient power into the signal. it is necessary to amplify the magnitude of input signal by means of small amplifiers to a level that is sufficient to drive the power amplifier stages.29: Power Amplifier Power amplifier The amplifiers in multistage amplifier near the load end in almost all-electronic system employ large signal amplifiers (Power amplifiers) and the purpose of these amplifiers is to obtain power again.150 Lecture . the emphasis is on power gain in amplifier near the load.e impedence of loud speaker is 3. A power amplifier draws a large amount of dc power form dc source and convert it into signal power. the collector currents are much larger because the load resistances are small (i. Since the radio signal received at the receiver output is of very low power. 1 .

2 Q is the operative point. the transistor operates at the Q point shown in fig. Fig. When no signal is present. 3. 4.151 The dc equivalent circuit gives the dc load line as shown in fig. 3 This circuit produces ac load line. 4 . ICQ and V CEQ are quiescent current and voltage. Fig. The ac equivalent circuit is shown in fig. 2. Fig.

operating point swings along the ac load line rather than dc load line. the collector voltage swings from Q-point towards cutoff. During the positive half cycle of ac source. voltage. Class A operation: In a class ?A' operation transistor operates in active region at all times. The maximum negative swing from the Q-point is 0 ? V CEQ = . the collector voltage swing from the Q-point towards saturation. Voltage gain of loaded amplifier . The saturation and cut off points on the ac load line are different from those on the dc load line.152 When a signal is present. On the negative cycle. The maximum positive swing from the Q-point is V CEQ + ICQ rC ? VCEQ = I CQ r C. For a large signal clipping can occur on either side or both sides. The ac output compliance (maximum peak to peak unclipped voltage) is given by the smaller of these two approximate values: PP = 2 I CQ rC or PP = 2 V CEQ. This implies that collector current flows for 360° of the ac cycle.V CEQ.

( Negative sign is due to phase inversion. 5 . 5.153 Current gain ac input power to the base Pin = V in i b ac output power point = . Maximum ac load power is obtained when the output unclipped voltage equals ac output compliance PP. Fig.V out * i C.) The variation of PL with VPP is shown in fig.

6 It decreases when the peak to peak load voltage increases.154 When no signal drives the amplifier. otherwise temperature increases and transistor may damage. voltage and current P DQ = V CEQ * I CQ When there is no input signal. 6. Fig. the power dissipation of the transistor equals the product of d. PD is maximum as shown in fig. . heat sinks are used that dissipates the heat produced. To reduce the temperature. When Q-point is at the center of ac load line then peak swing above and below Q-point is equal. The power dissipation must be less than the rating of transistor.

the dc source must supply an average current of I S = I 1 + I 2. Therefore. Fig.1. P S = V CC IS Therefore. The dc source voltage multiplied by the dc current drain gives the ac power supplied to an amplifier. efficiency of the amplifier. η = (P L (max) / P S ) * 100 % . 1 Assuming a stiff voltage divider circuit. the dc source VCC must supply direct current to the voltage divider and the collector circuit. whether the ac signal is present or not. This is the total dc current drain. the dc current drain of the voltage divider circuit is I 1 = V CC / (R 1 +R 2 ) In the collector circuit. the dc current drain is I 2 = I CQ In a class A amplifier.155 Lecture . the sinusoidal variations in collector current averages to zero.30: Power Amplifier Class A current drain: In a class A amplifier shown in fig.

2 The ratio of number of turns is so selected that the impedence referred to primary side can be matched with the output impedence of the amplifier. This results in more current and no power transfer to the load R L. 1.. The reason is that these circuits draw considerable current from the supply even in the absence of input signals. ICQ 2 * (R C + R E ). 2. In class A amplifier. be replaced by an inductance whose dc resistance is zero and there is no dc voltage drop across the choke as shown in fig. Class B amplifier: The efficiency (η) of class A amplifier is poor. P L (max) = maximum ac load line power. R E cannot be made zero because this will give rise to bias stability problem. R C can also not be made zero because effective load resistance gets shorted. however. The impedence matching is done with the help of transformer. . the loud speaker gets less power. Since in most application the load is loudspeaker.156 Where. To reduce this wastage of power R C and R E should be made zero. If it is not. as shown in fig. therefore power amplifier drives the loudspeaker. The R C resistance can.e. and the maximum power transfer takes place only when load impedence is equal to the source impedence. there is a wastage of power in resistor R C and R E i. Fig.

3. two transistors are used in push pull arrangement. load power is large and efficiency (η) is more.157 In class B operation the transistor collector current flows for only 180° of the ac cycle. Because the biasing resistors are equal each emitter diode is biased with the same voltage. 5.6V and 0. it clips off a half cycle. To avoid the resulting distortion. 4 & fig. VCEQ = VCC / 2. fig.7V i. The dc & ac equivalent circuit are shown in fig. shows how a npn and pnp transistor emitter followers are connected in push pull arrangement. I CQ = 0. 3 . The distortion is low. The advantages of class B operation are • • Lower transistor power dissipation Reduced current drain.e. Fig. Push pull circuit: When a transistor operates in class B. This means that one transistor conducts during positive half cycle and other transistor conducts during negative half cycle. This biases the emitter diode of each transistor between 0. As a result half the supply voltage is dropped across each transistor. The biasing resistors are selected so that Q-point is set at cutoff. This implies that the Q-point is located approximately at cutoff on both dc and ac load lines.

V CEQ = V CC / 2 i. 6.e. Any significant increase in V BE with temperature can move the Q-point up the dc load line to dangerously high currents. The voltage swing of the conducting transistor can go from cut off to saturation. The dc load line is vertical as shown in fig.158 Fig. 5 Since there is no dc resistance in the collector or emitter circuits. Fig. Ac load line is given by I C(sat) = I CQ + (V CEQ / r E ) V CE (cut off) = V CEQ + I CQ r E I CQ = 0. rE = R L ) V CE (cut off) = V CC / 2. PP = VCC Voltage gain of loaded amplifier: . that transistor's operating point swings along the ac load line and the operating point of the other transistor remains at cut off. the dc saturation current is infinite. In the next half cycle. 6 When either transistor is conducting. I C(sat) = V CC / 2RL ( i. Therefore. 4 Fig. The most difficult thing is setting up a stable Q-point at cut off. the other transistor does the same thing.e.

In the positive half cycle of input voltage.e. the upper transistor conducts and the lower one cut off. In the negative half cycle of input voltage.159 AV= R L / (R L + r'e ) Z in (base) R L + r'e ) ( Z out = r'e + (r B ) / A P =A V * Ai Without signal the capacitor charges up to VCC / 2 relative to ground. The current flow through RL is such as direct as to make output positive. negative output. . so that the output voltage approximately equals the input voltage. the source sees a high input impedence looking into either base and the load sees a low output impedence. During either half cycle. is off. but capacitor acts like a battery source and discharges). the upper transistor cuts off and the lower transistor conducts. no current can flow from VCC through Q. The lower transistor acts like an ordinary emitter follower and produces a load voltage approximately equal to the input voltage (i. Since Q. The upper transistor acts like an ordinary emitter follower.

Since the clipping occurs between the time one transistor cuts off and the time the other comes on. 1 shows the ac equivalent circuit of a class B push pull amplifier. 1.7 V to overcome the barrier potential. This means locating the Q-point slightly above cut off as shown in fig. Then the incoming voltage has to rise to about 0. Because of this no current flows through Q. when the signal is less than 0. it no longer is a sine wave. In fact. 2 .7 V. This means that collector current flows for more than 180 degrees but less than 360°.160 Lecture . the slight forward bias must be applied to each emitter diode.31: Class B Power Amplifiers Cross over distortion: Fig. it is called cross over distortion. 1 The signal output is distorted. this is class AB operation. To eliminate cross over distortion. Fig. If no bias is applied the output of class B amplifier looks like as shown in fig. Fig. Because of clipping action between half cycles. The action is similar on the other half cycle no current flows in Q2 until ac voltage is more negative the ? 0.7 V. 2. Suppose that no bias is applied to the emitter diodes.

Load power is given by Since the ac output compliance equals the peak-to-peak voltage.6 and 0. When no signal is present I2 = ICQ and the current drain is small. each transistor drops half the supply voltage. then the upper transistor has a half sine wave of current through it with a peak value of IC(sat) = VCEQ / RL The average value of half sine wave is given by The dc power is supplied to the circuit is PS = VCC is under no signal conditions.161 Class A amplifier introduces non-linear distortion in input wave means elongates one half cycle and compresses one half cycle. But when a signal uses the entire ac load line. . But when a signal is present. the dc power supplied to the circuit reaches a maximum. two complement any transistors are required. Because of the series connection. is given by non-linear distortion is much less than class A. In this case it can be further reduced because both half cycles are identical in shape.7. the maximum load power is Where. the Qpoint slightly above cut off. To avoid cross over distortion. Biasing a class B amplifier: In class B amplifier. the dc power is small because the current drain is minimum. I1 = current through biasing resistance. with the correct VBE somewhere between 0. This can be reduced by swamping. the current drain increase because the upper collector current becomes large. If the entire ac load line is used.

As the Q-point moves toward higher collector currents. The biasing does not solve thermal instability problem. If the diode curve is identical to the VBE curve of the transistor (VBE . When the temperature increases collector current increases. VBE requirement decreases by 2 mV per degree rise in temperature. the base current is much smaller than the current through the resistor and diode. 4. pnp transistor can be used as a current mirror. 3 One way to avoid thermal run away is to use diode bias. I1 = I C . IE ). Therefore as the temperature increases. The diode current equals the emitter and also collector current. The voltage divider produces a stiff drive for each diode. If the VBE curve of the transistor matches the diode curve. the fixed voltage on each emitter diode forces the collector current to increase and this gives rise to thermal run away.162 If there is an increase in VBE by few mV it produces 10 times as much emitter current. Because of this it is difficult to find standard resistors that can produce the correct VBE and it needs an adjustable resistor. the temperature of the transistor increases further reducing the required V BE . and this is equivalent to Q-point moving up along the vertical dc load line. This is called a current mirror. . For this reason. 3. I1 and I2 are approximately equal. Because for a given collector current. The collector current is set by controlling the resistor current. the collector equals the resistor current. Fig. Diode bias of class B push pull emitter follower relies on two current mirrors as shown in fig. Therefore I1 is nearly equal to IC. It is based on the concept of current mirror as shown in fig. Similarly.

Q1. and the lower half is a pnp current mirror as shown in fig. Part of the power to the transistor goes to load. and the ac collector current through transistor. zero input) Q1 is in cutoff mode. the diode curve must match the VBE curves of the transistor over a wide temperature range.163 Fig. The ac signal source adds an insignificant additional amunt of power since base currents are small relative to collector currents. and the other part is dissipated by the transistor itself. Collector current flows during the positive half of the output signal waveform. 4 The upper half is an npn current mirror. Therefore we only need to integrate this component of the power supply signal over the first half cycle. Power Calculations for Class B Push-Pull Amplifier The power delivered by the ac source is split between the transistor and the resistors in the bias circuitry. Under quiescent conditions (i. The average power supplied by the dc source is iCC(t) is the total current and is composed of two components: the dc current through the base bias resistor and diode combination. 4.e. The following equations specify the various power relationships in the circuit. . For diode bias to be immune to changes in temperature. This is easily done in ICs .

assuming a sinusoidal input. we find the power being dissipated in the transistors the power dissipated by a single transistor is one half of this value. It is often used in output circuits where efficiency important design requirement. This amplifier is more efficient than a Class A amplifier.164 The maximum values of collector current and power delivered to the transistor are The ac output power. we are assuming that the base current is negligible. Thus. . The efficiency of the Class B push-pull amplifier is the ratio of the output power to the power delivered to the transistor. Thus we neglect the power dissipated by the bias circuitry. If we subtract the power to the load from the power supplied to the transistors. is The maximum ac output power is found by substituting ICmax for IC1max to get The total power supplied to the stage is the sum of the power to the transistor and the power to the bias and compensation circuitry.

it is important that the power rating is equal to or exceeds the maximum power Pmax.165 Therefore. In choosing a transistor. .

166

Lecture - 32: Power Amplifier Class C amplifier: A class C amplifier can produce more power than a class B amplifier. Consider the case of a radio transmitter in which the audio signals are raised in their frequency to the medium or short wave band to that they can be easily transmitted. The high frequency introduced is in radio frequency range and it serves as the carrier of the audio signal. The process of raising the audio signal to radio frequency called modulation. The modulated wave has a relatively narrow band of frequencies centered around the carrier frequencies. At any instant, there are several transmitter transmitting programmes simultaneously. The radio receiver selects the signals of desired frequencies to which it is tuned, amplifies it and converts it back to audio range. Therefore, tuned voltage amplifiers are used. In short, the tuned voltage amplifiers selects the desired radio frequency signal out of a number of RF signals present at that instant and then amplifies the selected RF signal to the desired level as shown in fig. 1.

Fig. 1 Class C operation means that the collector current flows for less than 180° of the ac cycle. This implies that the collector current of a class C amplifier is highly non-sinusoidal because current flows in pulses. To avoid distortion, class C amplifier makes use of a resonant tank circuit. This results in a sinusoidal output voltage. The resonant tank circuit is tuned to the frequency of the input signal. When the circuit has a high quality factor (Q) parallel resonance occurs at approximately

167

At the resonance frequency, the impedence of the parallel resonant circuit is very high as shown in fig. 2 and is purely resistive. When the circuit is tuned to the resonant frequency, the voltage across RL is maximum and sinusoidal. The higher the Q of the circuit, the faster the gain drops off on either side of resonance

Fig. 2

Fig. 3 The dc equivalent circuit is shown fig. 3. No bias is applied to the transistor. Therefore, its Q-point is at cut off on the dc load line VBE = 0.7V. Therefore no IL current flows until input is more than 0.7 V. Also dc resistance is RS (the resistance of inductor) which is very small and therefore dc load line is almost vertical. There is no danger of thermal runway because there is no current other than from leakage. The IC(sat) current is given by

168

where rC is the collector resistance. The voltage VCE(sate) is given by

when ICQ = 0, VCEQ = VCC

When the Q of a resonant circuit is greater than 10. One can use the approximate ac equivalent circuit. The series resistance of the inductor is lumped into the collector resistance. At resonance, the peak-to-peak load voltage reaches a maximum. The bandwidth of a resonant circuit is given by Band width (BW) = f 2 ? f 1 f 1 = Lower cut off frequency. f 2 = Upper cut off frequency The bandwidth is related to the resonant frequency and the circuit Q as below: BW = f r / Q This means a large Q produces small BW equivalent to sharp tuning. These amplifiers have Q greater than 10. This means that the BW is less than 10% of the resonant frequencies. These amplifiers are also called narrow band amplifier. When the tank circuit is resonant the ac load impedence seen by the collector current source is purely resistive and the collector current is minimum. Above and below resonance, the ac load impedence decreases and the collector current decreases. Any coil or inductor has some series resistance RS as shown in fig. 4. The Q of all coil is given by. QL=XL/RL

169

Fig. 4 The series resistance can be replaced by parallel resistance RP . This equivalent resistance is given by R P = Q L RL Now all the losses in the coil are now being represented by the parallel resistance RP and series resistance RS no longer exists XC cancels XL at resonance. Leaving only RP in parallel with RL. Therefore, RC = RP || RL Q of the overall circuit = rC / XL

Since the circuit has only one resistor. A simple current source The simple two transistor current source shown in fig. The emitter currents are equal since the transistors are matched and emitters and bases are in parallel. One type of current source used to provide a fixed current is the fixed bias transistor circuit. If we sum the currents of Q2. When the current source is used to replace a large resistor the Thevenin resistance of the current source is the equivalent resistance value. IB + IC =IE So . 1 A reference current is the input to a transistor connected as a diode. The problem with this type of current source is that it requires too many resistors to be practically implemented on IC. The disadvantage of this circuit is that the reference current is approximately equal to the current source. we obtain.33: Current Sources Current Sources There are different methods of simulating a dc current source for integrated circuit amplifier biasing. In this circuit. Fig. The transistor Q1 and Q2 are identical devices fabricated on the same IC chip. The resistors in the following circuits are small and easy to fabricate on IC chips. where RE = 0. it can be easily fabricated on an IC chip. 1 is commonly used in ICs.170 Lecture . Q2 is in linear mode. since the collector voltage (output) is higher than the base voltage. The voltage across this transistor drives the second transistor.

It is therefore. (E-4) For a forward biased base-emitter junction diode. the current gain is approximately unity and the current mirror has reproduced the input current. For the base circuit. That is Widlar Current Source Large resistors are often required to maintain small currents of the order of few ?A and these large resistors occupy correspondingly large areas on the IC chip. One such device is the Widlar current source as shown in fig. the emitter current is given by Since iE ≈ iC = IC and n = 1 and (E-5) . One disadvantage of this current source is that its Thevenin resistance (RTH) is limited by the r o (1 / hoe) of the transistor.171 Summing currents at the collector of Q1 we obtain If β is large. desirable to replace these large resistors with current sources. The two transistors are assumed perfectly matched. 2.

we get (E-6) We have assumed that both the transistors are matched so that ICO. Thus Hence. β =100 and VBE = 0. 2 Substituting VBE1 and VBE2 from (E-5) to (E-4).172 Fig. β and VT are the same for both the transistors. Example-1 Design a Widlar current source to provide a constant current source of 3 ?A with VCC = 12V. (E-8) For design purposes.7V R1 . = 50 kO. The Widlar circuit can also be used to simulate a high resistance. IC1 is usually known since it is used as the reference for all current sources on the entire chip and IC2 is t he desired output current. (E-7) where.

The Wilson current source as shown in fig. . uses the negative feedback provided by Q3 to raise the output impedance Fig. As such.2 .173 Solution: The circuit is given in fig. IE2 =(β + 1) IB2 = IC3 (E-9) Since the base of Q1 is connected to the base of Q3. the collector current of Q2 remains almost constant providing high output impedance. 3 The difference between the reference current and IC1 is the base current of Q2. the currents in Q1 are approximately independent of the voltage of the collector of Q2. Applying KVL to the Q1 transistor we get. Using the equation (E-7) we can calculate R2 or R2 = 36 kΩ Wilson Current Source Another current source transistor configuration that provides a very large parallel resistance is the Wilson current source which uses three transistors and provides this capability an the output is almost independent of the internal transistor characteristics. 3.

the emitter current of Q2 becomes (E-12) The collector current of Q2 is (E-13) Solving for IC3 yields (E-14) Summing currents at the base of Q2. Thus. current in the feedback path splits equally between the bases of Q 1 and Q3 leading so that IB1 = IB3 and therefore IC1 = IC3. VBE1= VBE2 = VBE3 and β1 = β2 = β3 With identical transistors. Applying Kirchhoff's current law at the emitter of Q2 yields IE2 = IC3 + IB3 + IB1 (E-10) Using the relationship between collector and base currents (E-11) Since all three transistors are matched.174 Let us now see that IC2 is approximately equal to IREF. (E-15) (E-16) Since IC1 = IC3. we substitute IC3 to obtain (E-17) and solving for IC2 .

which makes the current source a Widlar current source. VBE = 0. In these types of circuits. lateral transistors can be used since it is not important that b be large. The errors in base current. Example -2: For the circuit shown in fig. do accumulate when multiple outputs are used and the current gain tends to deviate from unity. Lateral transistors usually have a β of approximately 20 which is more than adequate for current sources. determine the emitter current in transistor Q3. Fig. the currents can be different from the reference current. (E-19) Therefore. If the current is approximately the same as the reference voltage.175 (E-18) Equation (E-10) shows that β has little effect upon IC2 since. Given that β = 100. . When using the Widlar circuit. the simple current source can be used as shown in fig. Thus the amount of current delivered by this source can be determined by the size of the emitter resistor. for reasonable values of β. IC2 = IREF Multiple Current sources Using Current Mirrors A number of current sources can be obtained from a single reference voltage. 4 Notice that Q4 has an emitter resistance. This type of circuit is useful in integrated circuit chips as the one reference circuit can be used to develop current sources throughout the chip. 4 for Q2 and Q3. 5. however.715V.

176

Fig. 5 Solution: Since all transistor are identical, there VBE voltage drop will be same.

Let IB be the base current of each transistor and IC be the collector current of Q1 and Q2. Therefore,

177

UNI-JUNCTION TRANSISTOR Lecture - 34: Uni-junction transistor Uni-junction transistor The UJT as the name implies, is characterized by a single pn junction. It exhibits negative resistance characteristic that makes it useful in oscillator circuits. The symbol for UJT is shown in fig. 1. The UJT is having three terminals base1 (B1), base2 (B2) and emitter (E). The UJT is made up of an N-type silicon bar which acts as the base as shown in fig. 2. It is very lightly doped. A P-type impurity is introduced into the base, producing a single PN junction called emitter. The PN junction exhibits the properties of a conventional diode.

Fig. 1

Fig .2

A complementary UJT is formed by a P-type base and N-type emitter. Except for the polarity of voltage and current the characteristic is similar to those of a conventional UJT. A simplified equivalent circuit for the UJT is shown in fig. 3. VBB is a source of biasing voltage connected between B2 and B1. When the emitter is open, the total resistance from B2 to B1 is simply the resistance of the silicon bar, this is known as the inter base resistance R BB. Since the Nchannel is lightly doped, therefore RBB is relatively high, typically 5 to 10K ohm. RB2 is the resistance between B2 and point ?a', while RB1 is the resistance from point ?a' to B1, therefore the interbase resistance RBB is RBB = RB1 + RB2

178

Fig. 3 The diode accounts for the rectifying properties of the PN junction. VD is the diode's threshold voltage. With the emitter open, IE = 0, and I1 = I 2 . The interbase current is given by I1 = I2 = VBB / R BB . Part of VBB is dropped across RB2 while the rest of voltage is dropped across RB1. The voltage across RB1 is Va = VBB * (RB1 ) / (RB1 + RB2 ) The ratio RB1 / (RB1 + RB2 ) is called intrinsic standoff ratio

η = RB1 / (RB1 + RB2 ) i.e. Va = η VBB .

The ratio is a property of UJT and it is always less than one and usually between 0.4 and 0.85. As long as IB = 0, the circuit of behaves as a voltage divider. Assume now that vE is gradually increased from zero using an emitter supply VEE . The diode remains reverse biased till vE voltage is less than η VBB and no emitter current flows except leakage current. The emitter diode will be reversed biased. When vE = VD +η VBB, then appreciable emitter current begins to flow where VD is the diode's threshold voltage. The value of vE that causes, the diode to start conducting is called the peak point voltage and the current is called peak point current IP. VP = VD + η VBB. The graph of fig. 4 shows the relationship between the emitter voltage and current. vE is plotted on the vertical axis and IE is plotted on the horizontal axis. The region from vE = 0 to vE = VP is called cut off region because no emitter current flows (except for leakage). Once vE exceeds the peak point voltage, IE increases, but v E decreases. up to certain point called valley point (VV and IV).

179 This is called negative resistance region. Beyond this, IE increases with vE this is the saturation region, which exhibits a positive resistance characteristic. The physical process responsible for the negative resistance characteristic is called conductivity modulation. When the vE exceeds VP voltage, holes from P emitter are injected into N base. Since the P region is heavily doped compared with the N-region, holes are injected to the lower half of the UJT.

Fig. 4 The lightly doped N region gives these holes a long lifetime. These holes move towards B1 to complete their path by re-entering at the negative terminal of VEE. The large holes create a conducting path between the emitter and the lower base. These increased charge carriers represent a decrease in resistance RB1, therefore can be considered as variable resistance. It decreases up to 50 ohm. Since η is a function of RB1 it follows that the reduction of RB1 causes a corresponding reduction in intrinsic standoff ratio. Thus as IE increases, RB1 decreases, η decreases, and Va decreases. The decrease in V a causes more emitter current to flow which causes further reduction in RB1, η, and Va. This process is regenerative and therefore Va as well as vE quickly drops while IE increases. Although RB decreases in value, but it is always positive resistance. It is only the dynamic resistance between VV and VP. At point B, the entire base1 region will saturate with carriers and resistance RB1 will not decrease any more. A further increase in Ie will be followed by a voltage rise. The diode threshold voltage decreases with temperature and RBB resistance increases with temperature because Si has positive temperature coefficient.

Note. When the capacitor charges up to VP . The reduction in R B1 causes capacitor C voltage to drop very quickly to the valley voltage VV because of the fast time constant due to the low value of RB1 and R1. the diode remains reverse biased as long as VE < VP . rises exponentially with a time constant τ=RC As long as VE < VP. Fig. IE = 0. The negative dynamic resistance region of UJT can be used to realize an oscillator.35: Uni-junction transistor UJT Relaxation Oscillator: The characteristic of UJT was discussed in previous lecture. The interbase voltage VBB is the difference between VCC and the voltage drops across R1 and R2. It includes two resistors R1 and R2 for taking two outputs R2 may be a few hundred ohms and R1 should be less than 50 ohms. The voltage across C.180 Lecture . RB1 and RB2 are inter-resistance of UJT while R1 and R2 is the actual resistor. which is also VE . 1. RB1 is in series with R1 and RB2 is in series with R2 . Usually RBB is much larger than R1 and R2 so that VBB approximately equal to V. The dc source VCC supplies the necessary bias. The circuit of UJT relaxation oscillator is shown in fig. As soon as VE drops below Va . the diode conducts and RB1 decreases and capacitor starts discharging. It is having negative resistance region. 1 As soon as power is applied to the circuit capacitor begins to charge toward V.

2. The period T can therefore be approximated as follows: Fig.181 + VD the diode is no longer forward biased and it stops conduction. 2 . The emitter voltage is shown in fig. VE rises exponentially toward VCC but drops to a very low value after it reaches VP. The time for the VE to drop from VP to VV is relatively small and usually neglected. It now reverts to the previous state and C begins to charge once more toward VCC .

182 There are two additional outputs possible for the UJT oscillation one of these is the voltage developed at B1 due to capacitor discharge while the other is voltage developed at B2 as shown in fig. If R1 is too large. The duration of outputs at B1 and B2 are determined by C discharge time. 3. If R1 = 0. C discharges very quickly and very narrow pulse is produced at the output. causing a corresponding voltage drop at B2. If R2 = 0. in addition to providing a source of pulse at B2. no pulse can be generated at B2. its positive resistance may swamp the negative resistance and prevent the UJT form switching back after it has fired. If R1 is very small. When UJT fires (at t = T) Va drops. R2. obviously no pulses appear at B1. . is useful for temperature stabilization of the UJT's peak point voltage .

that the current through R should be slightly greater than the peak point. VE drops to the valley voltage VV . R is required to pass only the capacitor charging current. otherwise the UJT is taken into saturation region and does not switch back. This provides a constant VP and. frequency of oscillation. It is therefore. The temperature coefficient of RBB is positive. Vp decreases. Rs is essentially independent of temperature.183 VP = VD + η VBB. R must supply the peak current. necessary. R therefore must be selected large enough to ensure that . IE should not be allowed to increases beyond the valley point IV. It is therefore possible to select R2 so that VBB increases with temperature by the same amount as VD decreases. Once the UJT fires. in turn. Figure 31.3 Selection of R and C: In the circuit. As the temperature increases. At the instant when VP is reached.

.184 As long as R is chosen between these extremes. reliable operation results.

4. 1. Fig. In a conventional transistor. In FET the operation depends upon the flow of majority carriers only.185 Field Effect Transistor Lecture -36: Field Effect Transistor Field Effect Transistor: The field effect transistor is a semiconductor device. 5. It has thermal stability. . 1 Ohmic contacts are then added on each side of the channel to bring the external connection. Operation of FET: Consider a sample bar of N-type semiconductor. That is why it is called bipolar transistor. Thus if a voltage is applied across the bar. the operation depends upon the flow of majority and minority carriers. It exhibits no offset voltage at zero drain current. 2. It is less noisy than a bipolar transistor. The input to conventional transistor amplifier involves a forward biased PN junction with its inherently low dynamic impedance. 6. This is called N-channel and it is electrically equivalent to a resistance as shown in fig. The input to FET involves a reverse biased PN junction hence the high input impedance of the order of M-ohm. JFET (Junction Field Effect Transistor) 2. There are two of field effect transistors: 1. It is called unipolar device. 1. the current flows through the channel. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) The FET has several advantages over conventional transistor. 3. which depends for its operation on the control of current by an electric field. The main disadvantage is its relatively small gain bandwidth product in comparison with conventional transistor. It is relatively immune to radiation.

electrons are the majority carriers. Both depletion regions are therefore subject to greater reverse voltage near the drain. The width of this channel determines the resistance between drain and source. Therefore the depletion region width increases as we move towards drain. The conductivity of this channel is normally zero because of the unavailability of current carriers. Both the gates are internally connected and they are grounded yielding zero gate source voltage (VGS =0). Hence the circuit behaves like a dc voltage VDS applied across a resistance RDS. points close to the drain are at a higher positive potential. a depletion region is formed on the two sides of the reverse biased PN junction. leaving only uncovered positive ions on the n side and negative ions on the p side.186 The terminal from where the majority carriers (electrons) enter the channel is called source designated by S. These impurity regions are called gates (gate1 and gate2) as shown in fig. 2. The current carriers have diffused across the junction. The resulting current is the drain current ID. 2 . If VDS increases. ID increases proportionally. The depletion region width increases with the magnitude of reverse bias. The potential at any point along the channel depends on the distance of that point from the drain. relative to ground. Now on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any method for creating pn junction. The flow of electrons from source to drain is now restricted to the narrow channel between the no conducting depletion regions. For an N-channel device. The terminal through which majority carriers leaves the channel is called drain and designated by D. Fig. The word gate is used because the potential applied between gate and source controls the channel width and hence the current. As with all PN junctions. then points close to the source.

called the pinch of voltage VP. both depletion regions extend further into the channel. when the reverse voltage exceeds a certain level. Instead. (Drain to source current with gate shorted). ID also increases. 3 As with all pn junctions. This is called pinch off or saturation region. Suppose that VDS is gradually linearly increased linearly from 0V. The current in this region is maximum current that FET can produce and designated by IDSS. At this point further increase in VDS do not produce corresponding increase in ID. with increasing current. 4. there is more voltage. and hence a higher channel resistance. the resistance is also greater and the current remains relatively constant. resulting in a no more cross section. The gate source voltage is zero therefore VGS= 0. the conducting portion of the channel begins to constrict and ID begins to level off until a specific value of VDS is reached. The region is called ohmic region. .187 Consider now the behavior of drain current ID vs drain source voltage VDS. Thus even though. the ohmic voltage drop between the source and the channel region reverse biased the junction. as VDS increases. avalanche breakdown of pn junction occurs and ID rises very rapidly as shown in fig. Fig. therefore it follows ohm's law. Consider now an N-channel JFET with a reverse gate source voltage as shown in fig. Since the channel behaves as a semiconductor resistance. 3.

e. The gate voltage that produces cut off is symbolized VGS(off) . Suppose that VGS= 0 and that due of VDS at a specific point along the channel is +5V with respect to ground. In this case the drain current is cut off.188 Fig. pinch off will occur for smaller values of | VDS |. 5. A family of curves for different values of VGS(negative) is shown in fig.(-1) = 6V. and the maximum drain current will be smaller. all the free electrons from the source go to the drain i. only a very small reverse current flows through it. the channel width decreases as VGS is made more negative. the depletion layers touch each other and the conducting channel pinches off (disappears). Thus ID value changes correspondingly. 4 Fig. If VGS is decreased from 0 to ?1V the net reverse bias near the point is 5 . Since the gate source junction is a reverse biased silicon diode. 5 The additional reverse bias. Because the gate draws almost negligible reverse current the input resistance . ID = IS. Ideally gate current is zero. As a result. When the gate voltage is negative enough. Thus for any fixed value of V DS. It is same as pinch off voltage. Therefore reverse voltage across either p-n junction is now 5V.

The disadvantage is less control over output current i. FET takes larger changes in input voltage to produce changes in output current.e. .189 is very high 10's or 100's of M ohm. Therefore where high input impedance is required. JFET is preferred over BJT. For this reason. JFET has less voltage gain than a bipolar amplifier.

Q point is selected on the basis of ac performance i. frequency response. Using these values the transductance curve can be plotted. 2. Gate Bias: Fig.e. Fig. Biasing the FET: The FET can be biased as an amplifier. power. gain. 1 By reading the value of ID and VGS for a particular value of VDS. The transductance curve is a part of parabola. Consider the common source drain characteristic of a JFET.190 Lecture -37: Biasing the Field Effect Transistor Transductance Curves: The transductance curve of a JFET is a graph of output current (ID) vs input voltage (VGS) as shown in fig. the transductance curve can be plotted. It has an equation of Data sheet provides only IDSS and VGS(off) value. shows a simple gate bias circuit. current and voltage ratings. . 1. noise. Q point must be selected somewhere in the saturation region. For linear amplification.

At Q1.191 Fig. ID= 0. The reason is that there is considerable variation between the maximum and minimum values of FET parameters e. ID= 0.004 (1-(1/2))2 = 1 mA. Gate bias applies a fixed voltage to the gate. 3. 2 Separate VGS supply is used to set up Q point. This is the worst way to select Q point. if VGS= -1V the Q point may very from Q1 to Q2 depending upon the JFET parameter is use. This fixed voltage results in a Q point that is highly sensitive to the particular JFET used.(1/8))2 = 12. 3 . Fig.3 mA At Q2. IDSS Minimum 4mA Maximum 13mA VGS(off) -2V -8V This implies that the minimum and maximum transductance curves are displaced as shown in fig.g. The variation in drain current is very large. For instance.016 (1 .

the more negative the gate source voltage becomes. 4 Since the gate source junction is reverse biased. Similarly. the voltage drop across RS increases because the ID RS increases. The overall effect is to partially offset the original increase in drain current. This means that the gate source voltage equals the negative of the voltage across the source resistor. The source to ground voltage equals the product of the drain current and the source resistance. Rearranging the equation: ID = -VGS / RS The graph of this equation is called self base line a shown in Fig. 4. VG= 0. Only a drain supply is used and no gate supply. This is a form of a local feedback similar to that used with bipolar transistors. VGS = VG ? VS = 0 ? IDRS VGS = -ID RS. The idea is to use the voltage across RS to produce the gate source reverse voltage.192 Self Bias: Fig. shows a self bias circuit another way to bias a FET. hence reverse bias decreases and ID increases. drop across RS decreases. 5. ∴ VS= ID R S. The gate source voltage is the difference between the gate voltage and the source voltage. Fig. negligible gate current flows through RG and so the gate voltage with respect to ground is zero. . This increases the gate source reverse voltage which makes the channel narrow and reduces the drain current. If drain current increases. if ID decreases. The greater the drain current.

When RS is small. The current IQ is such that IA > IQ > IB. A and B are the optimum points for the two extreme curves. The slope of the line is (-1 / RS). To find the optimum resistance RS. The slope of this line gives the resistance value RS( VGS = -ID RS). A and B points are joined such that it passes through origin. Q and B all points are in straight line. The transductance curve varies widely for FET (because of variation in IDSS and VGS(off)) as shown in fig. 6 . Fig. In between there is an optimum value of RS that sets up a Q point near the middle of the transductance curve.193 Fig. The actual curve may be in between there extremes. so that Q-point is correct for all the curves. Here A. 5 The operating point on transductance curve is the intersection of self bias line and transductance curve. the Q point is far up the transductance curve and the drain current is large. If the source resistance is very large (-1 / RS is small) then Q-point is far down the transductance curve and the drain current is small. 6.

VGG = VGS + ID RS or VGS = VGG? ID RS .ID RS is not valid.194 Consider the case where a line drawn to pass between points A and B does not pass through the origin. Such a bias relationship may be obtained by adding a fixed bias to the gate in addition to the source self bias as shown in fig. The equation of this line is VGS = VGG ? ID RS. The equation VGS = . Fig. 7 In this circuit. 7. VGG = RS IG + VGS + ID RS Since RS IG = 0.

195 Lecture -38: Biasing the Field Effect Transistor Voltage Divider Bias : The biasing circuit based on single power supply is shown in fig. The drain current ID is given by and the dc voltage from the drain to ground is VD = VDD ? ID RD. . This is similar to the voltage divider bias used with a bipolar transistor. 1 The Thevenin voltage VTH applied to the gate is The Thevenin resistance is given as The gate current is assumed to be negligible. Fig. VTH is the dc voltage from gate to ground. 1.

In a BJT. VGS is not negligible.7 = 17. The current increases slightly from Q2 to Q1. 2 There is a problem in JFET. Difference in ID (min) and ID (max) is less VD (max) = 30 ? 2. Fig. with only minor variations from one transistor to other. Therefore. VBE is approximately 0. In a FET.13 * 4. 3. For this reason. However.196 If VTH is large enough to swamp out VGS the drain current is approximately constant for any JFET as shown in fig.5 V . voltage divider bias is less effective with.7V. 2. It is therefore. VGS can vary several volts from one JFET to another.7 = 20 V VD (min) = 30 ? 2.67 * 4. voltage divider bias maintains ID nearly constant. FET than BJT. Consider a voltage divider bias circuit shown in fig. difficult to make VTH large enough to swamp out VGS.

its collector current is given by IC = (VEE ? VBE ) / RE. 4 The bipolar transistor is emitter biased. 4. . Fig. 3 Current Source Bias: This is another way to produce solid Q point. Using two power supplies: The current source bias can be used to make ID constant fig.197 Fig. The aim is to produce a drain current that is independent of VGS. Voltage divider bias and self bias attempt to do this by swamping out of variations in VGS.

Using One power supply: When only a positive supply is available. .198 Because the bipolar transistor acts like a current source. Assuming a stiff voltage divider. The current source effectively wipes out the influence of VGS. both Q points have the same value of drain current. the bipolar transistor is voltage divider biased. the circuit shown in fig. In this case. This forces the FET drain current equal the bipolar collector current. the emitter and collector currents are constant for all bipolar transistors. can be used to set up a constant drain current. it no longer influences the value of drain current. Although VGS is different for each Q point. it forces the drain current to equal the bipolar collector current. 5. ID = IC Since IC is constant.

Fig. than a change in VGS produces a change in ID. The ratio of ID and VGS is the value of gm between A and B points. 6 The value of gm can be obtained from the transductance curve as shown in fig.199 Fig. . The second parameter rd is the drain resistance. If A and B points are considered. In a nutshell. 6. then same change in VGS produces more change in ID. the more effective is gate voltage in controlling gate current. 5 Transductance: The transductance of a FET is defined as Because the changes in ID and VGS are equivalent to ac current and voltage. gm tells us how much control gate voltage has over drain current. Therefore. Typical value of gm is 2000 m A / V. This equation can be written as The unit of gm is mho or siemems. Higher the value of gm. gm value is higher. If C and D points are considered.

200 .

JFET can also be used as an amplifier. The maximum value is designated as gmo. This model is applicable at low frequencies. gm has its maximum value. From the ac equivalent model The amplification factor µ for FET is defined as When VGS = 0. 1. Fig. 1 The resistance between the gate and the source RGS is very high. The ac equivalent circuit of a JFET is shown in fig. Again consider the equation. The drain of a JFET acts like a current source with a value of gm Vgs. .201 Lecture -39: FET a amplifier Similar to Bipolar junction transistor.

Since an ac current flows through the drain resistor. 2. This produces a sinusoidal drain current. VGS(off) can be determined FET as Amplifier: Fig. An amplified ac voltage is obtained at the output. Measuring IDSS and gm. shows a common source amplifier. Since the positive half cycle of input voltage produces the negative half cycle of output voltage. which means that the drain voltage is decreasing. Fig. 3. . we get phase inversion in a CS amplifier. The ac equivalent circuit is shown in fig.202 As VGS increases. An increase in gate source voltage produces more drain current. 2 When a small ac signal is coupled into the gate it produces variations in gate source voltage. gm decreases linearly.

3 The ac output voltage is vout = . At low frequencies. A Vin is output voltage and RD is the output impedance. a JFET distorts large signals. this is parallel combination of R1|| R2|| RGS. 4. 4 Zin is the input impedance. Because the ac source is directly connected between the gate source terminals therefore ac input voltage equals Vin = Vgs The voltage gain is given by The further simplified model of the amplifieris shown in fig. . it is parallel combination of R1 & R2. Since RGS is very large. 5. as shown in fig. Fig.gm v gS RD Negative sign means phase inversion.203 Fig. Because of nonlinear transductance curve.

In that case a part of the curve is used and operation is approximately linear. Now the source is no longer ac ground as shown in fig. The ac equivalent circuit is shown in fig. we get a non-sinusoidal output current in which positive half cycle is elongated and negative cycle is compressed. 7. 6 This distortion is undesirable for an amplifier. Then the voltage gain approaches an ideal value of RD / rS. This type of distortion is called Square law distortion because the transductance curve is parabolic. 5 Fig. . The drain current through rS produces an ac voltage between the source and ground. Since RGS approaches infinity therefore. Fig. Some times swamping resistor is used to minimize distortion and gain constant. One way to minimize this is to keep the signal small. If rS is large enough the local feedback can swamp out the non-linearity of the curve.204 Given a sinusoidal input voltage. all the drain current flows through r S producing a voltage drop of gm VgS rS. 6.

rS must be greater than 1 / gm only then . 7 The voltage gain reduces but voltage gain is less effective by change in gm.205 Fig.

5mA and iD = 5. the Q point for the dc bias current can be determined graphically.e. 1 Solution: We select an operating region which is approximately in the middle of the curves. This locates the Q point in the linear region of the characteristic curves.8 V and vGS = -1.40: JFET Applications Example-1: Determine gm for an n-channel JFET with characteristic curve shown in fig. iD = 8.2 V. a normalized curve) as shown in fig. Therefore. that is. The relationship between iD and vGS can be plotted on a dimensionless graph (i. Fig.206 Lecture . .5 mA. between vGS = -0. The dc bias current at the Q point should lie between 30% and 70% of IDSS. 1.. 2 . the transductance of the JFET is given by Design of JFET amplifier: To design a JFET amplifier.

. The slope of the curve is gm. This gives a wide range of values for vds that keep the transistor in the pinch ?off mode. is found from the slope of the curve at the point iD / IDSS = 0.3. Solution: Let us select the Q-point as given below: The transconductance.3VP.5 and vGS / VP =0. Hence. gm. Choose a reasonable location for the Q-point.2 and is given by Example-2 Determine g m for a JFET where IDSS = 7 mA.5 V and VDD = 15V. A reasonable procedure for locating the quiescent point near the center of the linear operating region is to select IDQ ≈ IDSS / 2 and VGSQ ≈ 0. Note that this is near the midpoint of the curve. 2 The vertical axis of this graph is iD / IDSS and the horizontal axis is vGS / VP. The transductance at the Q-point can be found from the slope of the curve of fig. Next we select vDS ≈ VDD / 2.207 Fig. VP = -3.

Fig. The JFET is normally saturated well below the knee of the drain curve. Fig. it is like a closed switch. 3 Fig. The idea is to use two points on the load line: cut off and saturation. 5. When VGS is equal to or more negative than VGS(off) .208 JEFT as Analog Switch: JFET can be used as an analog switch as shown in fig. Only these two points are used for operation when used as a switch. the JFET is saturated and operates at the upper end of the load line. the JFT is saturated and the switch is closed When Vcont is more negative FET is like an open switch. It is the major application of a JFET. 5. When Vcont=0. 3. 4 When VGS =0. 4. 5 FET as a series switch: . FET as a Shunt Switch: FET can be used as a shunt switch as shown in fig. When it is saturated. it is like an open switch. For this reason the drain current is much smaller than IDSS .This is shown in fig. The equivalent circuit is also shown in fig. it is cut off and operates at lower end of the load line (open and closed switch). When JFET is cut off.

6. Fig. It is better than shunt switch. Analog multiplexer is a circuit that selects one of the output lines as shown in fig. the FET is a closed switch. When Vcon= negative. 7 . Fig.209 JFET can also be used as series switch as shown in fig. When control is zero. When any control voltage becomes zero the input is transmitted to the output. the FET is an open switch. 7. 6 Multiplexing: One of the important application of FET is in analog multiplexer. When control voltages are more negative all switches are open and output is zero.

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