1 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM

CHAPTER 1 INTRODUCTION
1.1 Evolution of computer aided designs:-

VHDL is a hardware description language intended for documenting and modeling digital System ranging from a small chip to a large system. It can be used to model a digital system at Any level of abstraction ranging from the architectural level down to the gate level.

The language was initially developed specially for department of defense VHSIC (very high speed integrated circuits) contractors. However, due to an overwhelming need in the industry For a standard hardware description language, the VHSIC hardware description language (VHDL) was selected and later approved to become an IEEE standard called the IEEE std 1076-1987. The language was updated again in 1993 to include a number of clarifications in addition to a number of new features like report statement and pulse rejection limit.

Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were SSI (small scale integration) chips

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2 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM where the gate count was very small. As technologies became sophisticate, designers were able to lace circuits with hundreds of gates on a single chip. The traditional design methods are convenient as long as the system is simple and gates involved in final implementation are limited for larger systems, inputs and outputs are more and obtaining the truth table or table can be difficult if not impossible and the processes started getting very complicated and designers felt the need to automate these processes. Computer aided design (cad) techniques began to evolve. Chip designers began to use the circuit and logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the board, and the layout was done on paper or by hand on graphic computer terminal.

With the advent of VLSI (very large scale integration) technology, designers could design single chips with more than 1,00,000 transistors. Because of complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer aided techniques became critical for verification and design of VLSI digital circuits.

Computer programs to do automatic placement and routing for circuit layouts also became popular. The designers were now building gate level digital circuits manually on graphic terminals. They would build small building blocks and then derive higher- level blocks from them. This process would continue until

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3 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM they had built the top-level block. Logic simulators came into existence to verify the functionality of these circuits before they were fabricated on chip.

As designs got larger and more complex, logic simulation assumed an important role in the design process. Designers could iron out functional bugs in the architecture using simulation, before chop was designed further.

1.2 Emergence of HDLs:-

For longtime, programming languages such as FORTRAN, PASCAL and C were being used to describe computer programming that were sequential in nature. Similar in the digital field, designers felt the need for a standard language to describe digital circuits. Thus, hardware description languages (HDLs) came into the existence. HDL allowed the designers to model concurrency of processes found in hardware elements. Hardware description languages such as verilog HDL and VHDL became popular. Verilog HDL originating in 1983 at gateway design automation. Later, VHDL was developed under contract from DARPA. Both verilog and VHDL Simulators to simulate large digital circuits quickly gained acceptance from designers.

Even though DHLS were popular for large verification, designers had to manually translate the HDL based design into a schematic circuit with

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4 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM interconnections between gates. The advent of logic synthesis in the late 1980s changed the design methodology radically. Digital circuits could be described at a register transfer level (RTL) by use of a HDL. Thus, the designers had to specify how the data flows between registers and how the design processed the data. Logic synthesis tools from the RTL description automatically extracted the details of gates and their interconnections to implement the circuit. Thus, logic synthesis pushed the HDLs into forefront of digital design. Designers no longer had to manually place gates to build logic circuits. They could describe complex circuits at an abstract level in terms of functionality and data flow by designing those circuits in HDLs. Logic synthesis tools would implement the specified functionality in terms of gate interconnections.

HDLs also began to be used for system-level design. HDLs were used for simulation of system boards, inter connect buses, FPGAs (Field Programmable Gate Arrays) and PALs (Programmable Array Logic). A common approach is to design each IC chip using an HDL, and then verify system functionality via simulation.

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3 TYPICAL DESIGN FLOW:- Typical design flow for designing VLSI IC circuits is shown in figure DESIGN SPECIFICATIONS BEHAVIORAL DESCRIPTION RTL DESCRIPTION FUNCTIONAL VERIFICATION & TESTING LOGIC SYNTHESIS GATE LEVEL NETLIST LOGICAL VERIFICATION & TESTING FLOOR PLANNING PHYSICAL LAYOUT LAYOUT VERIFICATION IMPLIMENTATION fig 1.5 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 1.1 Typical design flow for designing VLSI IC circuits VJIT .

By describing designs in HDLs. Logic synthesis tools can automatically convert the design to any fabrication technology. they can optimize and modify the RTL description until it meets the desired functionality. This cuts down design cycle time significantly because the probability of hitting a functional bug a later time in the gatelevel net list of physical layout is minimized.6 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 1. They simply input the RTL description to the logic synthesis tools and crate a new gate-level net list. Designers can write their RTL description without choosing a specific fabrication technology. A textual description with comments is an easier way to develop a circuit.  Designing with HDLs is analogous to computer programming. Most design bugs are eliminated at this point. Using the new fabrication technology.4 IMPROTANCE OF HDLs:- HDLs have many advantages compared to traditional schematic-based design:  Design can be described at a very abstract level be use of HDLs. Since designers work at the RTL level.  The logic synthesis tools will optimize the circuit in area and timing for the new technology. If a new technology emerges Designers don’t need to redesign their circuit. functional verification of the design can be done early in the design cycle. VJIT .

HDLs are almost certainly a trend of the future. No digital circuit designer can afford to ignore HDL-based design. With rapidly increasing complexities of digital circuits and increasingly sophisticated CAD tools. HDLs will probably be the only method for large digital designs. VJIT . compared to gate-level schematics.7 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM This also provides a concise representation of the design. Gate-level schematics are almost in comprehensible for very complex design.

1 Use of VHDL tools in VLSI design:IC designers are always looking for a ways to increase their productivity without degrading the quality of their designs. Therefore. Now logic synthesis tools can automatically produce a gate level net list. allowing designers to formulate their design in a high level description such as VHDL. Many designs created manually. in terms of chip area occupied and ic signal speed. VJIT . as evidenced by the recent availability of logic synthesis tools using the very high speed integrated circuit hardware description language(VHDL).Logic synthesis provided two fundamental capabilities. but are much faster to do. and optimization to decrease the circuit’s area and increase its speed. these tools have grown to be capable for producing designs as good as a human designer.8 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 2 INTRODUCTION TO VHDL 2. Now logic synthesis is helping to bring about a switch to design using a hardware description language (HDL) to describe the structure and behavior of circuits. Automatic translation of high-level descriptions into logic designs. it is no wonder that they have embraced logic synthesis tools. In the last few years.

In addition. In logic synthesis process. VJIT . the minimized equations are mapped into a set of gates the non-synthesized portions of the logic are also mapped into a technology specific integrated circuit (ASIC) vendor library in which to implement the chi. creating it can easily absorb 80% of the gate level design time. Once the functionality has been thoroughly verified through simulation. the designer reformulates the design in terms of large structural blocks such as registers.9 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM The ability to translate a high level description into a net list automatically can improve design efficiency markedly. arithmetic units. so that the logic synthesis tool may efficiently apply the gates available in that library. It quickly gives designers an accurate estimate of their logic potential speed and chip real estate needs. capturing its intended functionality rather than its implementation. the tool’s first step is to minimize the logical equations complexity and hence size by finding common terms that can be used repeatedly. In a design methodology based on synthesis. and combinational logic typically constitutes only about 20% of a chip’s area. designers can quickly implement a verify of architectural choices and compare area and speed characteristics. The resulting description is called register transfer level(RTL) since the equation describes how data is transferred from one register to another. storage registers. the designer begins by describing a design’s behavior in high level code. In a translation step called technology mapping.

VJIT . designers must choose the trade off point that is best for a specific. Asynchronous designs require that designers formulate timing constraints explicitly. Logic synthesis has achieved its greatest success of synchronous designs that have significant amounts of combinational logic. Although it might be desirable to build a give circuit that is both small and fast. chip area and power goals. These goals can apply to the entire IC or the portions of the logic.10 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM The primary consideration in the entire synthesis process is the quality of the resulting circuit. Quality in logic synthesis is measured by how close the circuit comes to meeting the designer speed. The ability to steer the synthesis process towards various solutions allows designers to implement rapidly many versions of a circuit and choose the solution best suited for their specific situation. The ability of synthesis tools to synthesize sequential logic and optimize it in any chosen technology makes designs quickly as improved technologies become available and to try out a circuit in several technologies and then choose the best one. Unlike the behavior of synchronous designs is not affected by events such as the arrival of signals. area typically trades off with speed. Designers can therefore explore their options in a way that has not been practical before. the designer directs the process towards the most desirable solution. By devising a set of constraints that the synthesis tools have to meet. Furthermore. Thus.

Logic synthesis tools are becoming capable of more behavioral. Thus in a fraction of time it would take a designer to do one manual version.level tasks. so those human designers do as little of it as possible. on others hand make many process overall the possible logic combinations of a circuit. applying the same simulation and test vectors from the design behavioral level all the way down to the gate level. A number of languages known as the hardware description languages (HDLs) have been developed for this purpose. This integrated approach reduces the problems that can result from different descriptions of the same design. HDL Statements can be describing circuits in terms of the structure of he structures or behavior or both. the tools iterate through many solutions to determine the best one. Tight integration of timing analysis with in the optimization algorithms enables some synthesis system to quickly find circuit critical paths – the path determines the overall clock rate and re-optimize when necessary. the synthesis tools must first be able to understand the RTL description. Existing logic synthesis tools are moving up the designer VJIT . it will allow designers to concentrate less on the details of the circuit and more on its actual function and behavior. When a designer starts a synthesis process by translating an RTL description into a netlist. As logic synthesis matures. such as synthesizing sequential logic and deciding if and where the storage elements are needed in a design. One reason HDLs are so powerful. in fact is that they support both a variety of design description. Syntheses tools.11 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM modifying logic manually is tedious and takes a great deal of time. A HDL simulator handles all those descriptions.

The concept of packages and configurations allow the creation of design libraries for the reuse of previously designed parts. while behavioral research is extending down to the RTL level.12 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM ladder. With VHDL we can quickly describe the capability described as follows: VJIT .2 Scope of VHDL:- VHDL satisfies all the requirements for the hierarchical description of electronic circuits from system level down to switch level. given designers a complete set of tools to automate designs from concept to layout. It can support all levels of timing specification and constraints and is capable of detecting and signaling timing violations.3 WHY VHDL? A design engineer in electronic industry used hardware description language to keep pace with the productivity of the competitors. 2. The language models the reality of concurrency present in digital system and supports the recursively of finite state machines. 2. Eventually they will merge.

we can target many device architectures. Simulating a large description before synthesizing can save considerable time. 2.independent design:- VHDL permits to create a design with out to first choose a device implementation.2 Devices.3. one synthesis tool to another.13 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 2.3. design description can be taken from one simulator to another. we can optimize our design for resource utilization performance. Without being familiar with it. VJIT .3. As VHDL is a standard.1 Power and flexibility:- VHDL has powerful language constructs with which to write succinct code descriptions of complex control logic.3 Portability:- VHDL portability permits to simulate the same design description that we have synthesized. With one design description. It permits multiple style of design description. and one platform to another means design description can be used in multiple projects. 2. It also has multiple levels of design description for controlling design implementation. It supports design libraries and creation of reusable language for design and simulation.

the exact code used with the PLD can be used with the ASIC and because VHDL is a well –defined language. VHDL facilitates the development of application specific integrated circuit (ASIC).3.4 Benchmarking capabilities:- Device independent design and portability allows benchmarking a design using different device architectures and different synthesis tools. 2. Programmable logic VJIT . 2.5 ASIC Migration:- The efficiency that VHDL generated. We can take a completed design description and synthesize it.3.6 Quick Time-to-Market and low cost:- VHDL and programmable logic pair will together facilitate a speedy design process. create logic for it. allows our product to hit the market quickly if it has been synthesized on a CPLD or FPGA. VHDL permits to be described quickly.3. Sometimes. evaluate the results and finally choose the device-a CLD or an FPGA that best fits our design requirements. When production volume reaches appropriate levels. we can be assured that out ASIC vendor will deliver a device with expected functionality.14 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 2.

Synthesis makes it all possible. VJIT .15 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM eliminates NRE expenses and facilitates quick design iterations. VHDL and programmable logic as powerful vehicle to bring the products in market record time.

3. 2. 3. maximum frequency of operation and critical paths. Simulate the post-layout design model. we must have a clear idea of design objective and requirements. Synthesis. 5.16 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 3 DESIGN SYNTHESIS The design process can be explained in six steps: 1.1 Define the design requirements Before launching into writing code for our design. Progress the device. Describe the design in VHDL (formulate and code the design). VJIT . the function of the design required setup and clock-to-output times. 4. Define the design requirements. That is. 6. Simulate the source code. optimize and fit the design on to a suitable device.

1 Synthesis: It is a process by which net lists or equations are created from design descriptions.2 Optimization: VJIT . to the logic implementation we intended. we have to write an efficient code that is realized. through synthesis. Optimize. we should code the design referring to the block. and Fit the design 3.4. This is more efficient for larger designs. and state diagrams such that the code is syntactically and semantically correct. for which synthesis and lace and route can take a couple of hours. Code the design: after deciding upon a design methodology. allowing us to make corrections with the least possible impact o the schedule.2 Describe the design in VHDL Formulate the design: having and idea of design requirements. flaws can be detected early in the design cycle. dataflow.4 Synthesis. 3. 3.3 Stimulate the source code With source code simulation.17 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 3. which many be abstracted.4. 3. VHDL synthesis software tools convert VHDL descriptions to technology specific net lists or set of equations.

4. clock-to-output. If we are unable to meet our design objectives. such as setup. then we need to either resynthesize. This reduces the product-term utilization and number of logic block inputs required for any given expression. 3. and placing it into a logic device.5 Simulate the Post-layout design model A post layout simulation will enable us to verify.products.3 Fitting: Fitting is process of taking the logic produced by the synthesis and optimization process. transforming the logic (if necessary) to obtain the best fit. not only the functionality of our design. which is then further optimized for a minimal literal count. Optimization for CPLDs involves reducing the logic to minimal sum-of. 3. and/or fit our design to a new logic device. VJIT . and register-toregister times.18 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM The optimization process depends on three things: the form of the Boolean expression. It is a term typically used to describe the process of allocating resources for CPLD-type architectures. but also timing. the type of resources available and automatic or used applied synthesis directives (sometimes called constraints).

This architectural arrangement makes more efficient use of the available silicon die area.1 Programmable interconnects The programmable interconnect (PI) routes signals from i/os to logic block inputs.19 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 4 PROGRAMMABLE LOGIC PRIMERS In this chapter. product terms and macro cells. Instead of making the PLD larger with more inputs. improve reliability and reduce cost. as well as the decisions that go into selecting on appropriate device for an application. or from block outputs(macro cell outputs) to the inputs of he it or other VJIT . we introduce the defining features of programmable logic design architectures and of many popular devices. 4. each similar to a small PLD like the 22V10.1. 4. The logic blocks communicate with one another using signals routed via a programmable interconnects. they also use less board space. leading to better performance and reduced cost.1 Complex Programmable Logic devices (CPLD) CPLDs extend the concept of the PLD to higher level of integration to improve system performance. A CPLDs contains multiple logic blocks.

Some logic blocks have local feedback so that macro cell outputs used in the same logic block do not route through the global programmable interconnect. VJIT . there is one multiplexer for each input to a logic block. With multiplexer based interconnect. Signals in the PI are connected to the inputs of a number of multiplexer are programmed to allow one input for each multiplexer to propagate into a logic block. An output from a logic block can connect to PI terms through a memory element (such as an EPROM cell). Device inputs can connect to PI terms as well. increases routability in the PI to connect to the input of several multiplexer for each logic block. provide that not all of the inputs to a logic block are already being used. Array based interconnect allows any signal in the PI to route to any logic block. This interconnect scheme implement a full cross-point switch. Each term in the pi is represented by a vertical wire and is assigned as an input (through a sense amplifier) to a given logic block. allowing each signal the PI to connect to the input. Most CPLDs use one of the two implementations for the programmable interconnect: Array based interconnects or multiplexer based interconnect. that is. Any input to the programmable interconnect can be routed into any logic block. Using wider multiplexer.20 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM logic blocks. so there is one PI term for each input to a logic block. it is fully routable.

a product term distribution scheme and macro cells. 4. Concept that a particular macro cell can use a product-term is term and product-term steering and VJIT . Sixteen or more macro cells logic block enough inputs from PI to the logic block exists.1. 4.4 Product-term distribution. Cypress and MAX family allocated four product terms per macro cell while allowing expander product-terms.1. With expander product-terms.3 Produt-term arrays The size of the array identifies the average number of the product terms per macro cell and maximum number of product terms per logic block. the additional products-terms are allocated only to those macro cells that can make use of them.2 Logic blocks Each logic block has product term array. Each CPLD will have a specific product term array.1. Also important are the number of inputs to the logic block the number of terms and the product terms and the product term distribution scheme.21 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 4. A logic block usually ranges in size from 4 to 20 macro cells. it is typically expressed in the terms of macro cells. to allocate individually t any micro cell or macro cell. The size of a block is a measure of its capacity.

I/o cells contains switch matrix or output routing pools in which a one-to-one connection is made between an i/o macro cell output and an i/o. Polarity control enables the implementation of either the true or the complement of an expression. 4. input macro cells and buried macro cells. VJIT . Buried macro cell is similar to i/o macro cell expect that its output can propagate directly to an i/o. depending on the state of output enable and to provide a data for incoming signals. CPLDs have i/o macro cells. An input macro cell is associated with pin.5 Macro cells CPLDs include macro cells that provide flip-flops and polarity control.1.22 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM the concept that the multiple macro cells may use same product. advantage of this scheme is flexibility in determining where logic can be placed in a logic block in relation to where the i/o cell is located.6 I/O Cells I/O cells are used to drive a signal off the device.term is termed product-term sharing. 4. rather its output its output is fed back to PI.1.

The FPGA configuration is generally specified using a hardware description language (HDL). Logic blocks can be configured to perform complex combinational functions. or merely simple logic VJIT .1 Field programmable gate arrays (FPGA) A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "fieldprogrammable". The ability to update the functionality after shipping. FPGAs contain programmable logic components called "logic blocks". similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration. but this is increasingly rare). as they were for ASICs. offer advantages for many applications.23 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 5 FIELD PROGRAMMABLE GATE ARRAY 5. partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost). and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. FPGAs can be used to implement any logical function that an ASIC could perform.

24 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels.

A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

FPGA architecture is an array of logic cells that communicate with i/o via wires routing channels. In a FPGA, existing wire resources that run in horizontal and vertical columns (routing channels) are connected via programmable elements. These routing wires also connect logic to i/0s. Logic cells have less

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25 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM functionality than the combined product terms and macro cells of CPLDs, but large functions can be created cascading logic cells.

1. Performance- the ability for real system design to operate at increasingly higher frequencies.

2. Density and capacity- the ability to increase integration, to place more and more in a chip (system in a chip), and use all available gates with in the FPGA, they’re by providing a cost effective solution.

3. Ease of use – the ability for system designers to bring their products to market quickly, leveraging the availability of easy-to-use software tools for logic synthesis as well as lace and route, in addition to architectures that enables late design that effect logic, routing, and i/o resources without a significantly adverse effect on timing.

4. In- system programmability and in circuit re-programmability the ability to program or reprogram a device while it is in-system, mainstreaming, and inverters as well as allowing for field upgrades and user configurability.

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26 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 5.1 History

The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable), however programmable logic was hard-wired between logic gates.In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992. Some of the industry’s foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985. Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.

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27 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Xilinx continued unchallenged and quickly growing from 1985 to the mid1990s, when competitors sprouted up, eroding significant market-share. By 1993, Actel was serving about 18 percent of the market. The 1990s were an explosive period of time for FPGAs, both in sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications. FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a researcher working at the University of Sussex, merged genetic algorithm technology and FPGAs to create a sound recognition device.

Thomson’s algorithm configured an array of 10 x 10 cells in a Xilinx FPGA chip to discriminate between two tones, utilising analogue features of the digital chip. The application of genetic algorithms to the configuration of devices like FPGAs is now referred to as Evolvable hardware.

5.2 FPGA design and programming

To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualisation of a design.

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The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route. which have been compared to the equivalent of assembly languages. simulation. Other predefined circuits are available from developer communities such as OpenCores (typically released VJIT . place and route results via timing analysis. and other verification methodologies. the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA.28 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Then. although in an attempt to reduce the complexity of designing in HDLs. and typically released under proprietary licenses). Once the design and validation process is complete. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. there are moves to raise the abstraction level through the introduction of alternative languages. These predefined circuits are commonly called ip cores and are available from FPGA vendors and third-party IP suppliers (rarely free. The user will validate the map. there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. To simplify the design of complex systems in FPGAs. usually performed by the FPGA company's proprietary place-and-route software. using an electronic design automation tool. National Instrument's LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module available to target and program FPGA hardware. a technology-mapped netlist is generated. The most common HDLs are VHDL and Verilog.

BSD or similar license).31Features • Low-cost. an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. • SelectIO™ interface signaling. In a typical design flow. . high-performance logic solution for high-volume. 5. consumeroriented applications.3 Spartan-3E FPGA: 5. Then.8 differential I/O standards including LVDS. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. RSDS VJIT . and other sources. the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors.18 single-ended signal standards . after the synthesis engine has mapped the design to a netlist.29 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM under free and open source licenses such as the GPL.622+ Mb/s data transfer rate per I/O .

Clock skew elimination .14V to 3.Frequency synthesis .Up to 520 Kbits of total distributed RAM • Digital Clock Manager (up to four DCMs) .Signal swing ranging from 1. fast multiplexers .1/1532 • SelectRAM™ hierarchical memory .Up to 1.Wide.High resolution phase shifting • Eight global clock lines and abundant routing VJIT .Dedicated 18 x 18 multipliers .Abundant logic cells with shift register capability . DDR2 SDRAM support up to 333 Mbps • Logic resources .JTAG logic compatible with IEEE 1149.Double Data Rate (DDR) support .465V .Termination by Digitally Controlled Impedance .30 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM .Fast look-ahead carry logic .DDR.872 Kbits of total block RAM .

31 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM • Fully supported by Xilinx ISE® • MicroBlaze™ and PicoBlaze™ process • Pb-free packaging options • Automotive Spartan-3 XA Family variant. The Spartan-3 family is not pin-compatible with any previous Xilinx FPGA family or with other platforms among the Spartan-3 Generation FPGAs. additional VCCO lines are bonded out to pins that were ―not connected‖ in the smaller device. Thus. When the need for future logic resources outgrows the capacity of the Spartan-3 device in current use.4 Spartan-3E FPGA Compatibility Within the Spartan-3 family. Larger devices may add extra VREF and VCCO lines to support a greater number o I/Os. it is important to plan for future upgrades at the time of the board’s initial design by laying out connections to the extra pins. more pins can convert from user I/Os to VREF lines. a larger device in the same package can serve as a direct replacement. it is important to follow the following VCCO rules: VJIT . Also. In the larger device. all devices are pin-compatible by package. Rules Concerning Banks When assigning I/Os to banks. 5.

LVDS_EXT. apply 2. Apply the same voltage to VCCO Bank 5 during parallel configuration or a Readback operation. as in the CP132 and TQ144 packages. Only one of the following standards is allowed onoutputs per bank: LVDS.5V. TheXilinx development software checks for this. VJIT .3V-Tolerant Configuration Interface section. see the 3. LDT. or RSDS. If none of the standards assigned to the I/Os of the (interconnected) bank(s) uses VCCO. This restriction is for the eight banks in each device. even if the VCCO levels are shared across banks. tie all associatedVCCO lines to 2.32 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Leave no VCCO pins unconnected on the FPGA. Set all VCCO lines associated with the (interconnected) bank to the same voltage level.5V to VCCO Bank 4 from power-on to the end of configuration. The VCCO levels used by all standards assigned to the I/Os of the (interconnected) bank(s) must agree.3V signals and power.In general. For information on how to program the FPGA using 3.

That specification documents the requirements that a successful traffic light controller must meet. It consists of an operation specification that describes the different functions the controller must perform.1 shows the location of the traffic lights. cycling through the states correctly.1 INTRODUCTION Traffic lights are integral part of modern life. and responding to outside inputs. VJIT . The traffic light controller is designed to meet a complex specification.33 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 6 INTRODUCTION TO TRAFFIC LIGHT CONTROLLER 6. The controller to be designed controls the traffic lights of a busy highway (HWY) intersecting a side road (SRD) that has relatively lighter traffic load. and a detailed protocol for running the traffic lights. Each of these requirements sets imposed new constraints on the design and introduced new problems to solve. a user interface description specifying what kind of interface the system must present to users. Figure 1. Sensors at the intersection detect the presence of cars on the highway and side road. Their proper operation can spell the difference between smooth flowing traffic and four-lane gridlock. Proper operation entails precise timing.

The input handler also latches some input signals and guarantees that other input signals will be single pulses. Crossover between side road and highway The heart of the system is a finite state machine (FSM) that directs the unit to light the main and side street lights at appropriate times for the specified time intervals.1. In order to safely process these external inputs. The slow clock solves VJIT . regardless of their duration. the controller needs to be informed every second that a second of real time has elapsed. the design also includes a slow clock generator. we can design an input handler that synchronizes asynchronous inputs to the system clock. This pulsification greatly simplifies the design by ensuring that most external inputs are high for one and only one clock cycle. This unit depends on several inputs which are generated outside the system. In addition to the FSM and input handler.34 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Fig 6. Because the specification requires that timing parameters are specified in seconds.

In order to store the users timing parameters. Finally. In addition to generating a once per second pulse. and the control of the actual traffic lights. The timer subsystem does that job. displaying these parameters by reading the RAM locations. The divider provides a one-second clock that is used by the timer as a count interval. we use a static RAM whose address and control lines are supplied by the FSM.35 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM this problem by generating a slow clock pulse that is high for one cycle on the system clock during every second of real time. This same bus can drive the HEX-LED display. The heart of the controller is the FSM. The timer is a counter unit that counts for a number of one second intervals that are specified by data stored in the static RAM. it informs the FSM controller after exactly that number of seconds has elapsed. the synchronizers ensure that all inputs to the FSM are synchronized to the system clock. The RAM data lines are on a tristate bus which is shared by the timer unit and a tristate enabled version of the data value signals. Lastly. VJIT . When given a particular number of seconds to count down from. we have storage and output components. we need to be able to count down from a specified number of seconds. The timer and the divider control various timing issues in the system. which comprises the output subsystem along with the actual traffic light LEDs. This FSM controls the loading of static RAM locations with timing parameters.

Various adaptive signal systems have demonstrated network performance enhancement from 5 percent to over 30 percent.2 LITERATURE REVIEW Intelligent Transportation Systems (ITS) applications for traffic signals – including communications systems. and maintenance/failure response times. Traffic light controller communication and sensor networks are the enabling technologies that allow adaptive signal control to be deployed. real-time data collection and analysis. The Texas Traffic Light Synchronization program reduced delays by 23 percent by updating traffic signal control equipment and optimizing signal timing. Incorporating Traffic light controller into the planning. traffic responsive. Some examples of the benefits of using ITS applications for traffic signal control include: Updated traffic signal control equipment used in conjunction with signal timing optimization can reduce congestion. Coordinated signal systems improve operational efficiency. adaptive control systems. design. and operation of traffic signal control VJIT . Adaptive signal systems improve the responsiveness of signal timing in rapidly changing traffic conditions. incident and special event management. and maintenance management systems – enable signal control systems to operate with greater efficiency. Sharing traffic signal and operations data with other systems will improve overall transportation system performance in freeway management.36 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 6.

or updating equipment. municipalities have worked to synchronize.1 percent in fuel consumption. with reductions of 24.S. interconnected traffic signals. in some applications. and. closed loop signal systems. or otherwise upgrade their traffic signal systems in recent years. according to U. ITS technology enables the process of traffic signal timing to be performed more efficiently by enhancing data collection and system monitoring capabilities and. optimizing signal timing is considered a low-cost approach to reducing congestion. 9. coordinating adjacent signals.2 percent in stops. Several optimize. In fact. The Fuel Efficient Traffic Signal Management program in California showed a benefit-cost VJIT .6 percent in delay. centrally controlled or monitored traffic signal systems. and traffic adaptive signal control help make the traffic signal timing process efficient and cost effective.000 traffic signals in the United States.100 per signal per update. as many as 75 percent could be made to operate more efficiently by adjusting their timing plans. and 14.500 to $3. Department of Transportation estimates. automating the process entirely. lower vehicle operating costs. ITS tools such as automated traffic data collection. costing from $2.37 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM systems will provide motorists with recognizable improvements in travel time. There are more than 330. Below is an example of the benefits some have realized: The Traffic Light Synchronization program in Texas shows a benefit-cost ratio of 62:1. and reduced vehicle emissions.

3 PROTOCOL The protocol or the design rules we incorporated in designing a traffic light controller are laid down: We too have the same three standard signals of a traffic light controller that is RED. and 10 percent in travel time. We have decided on having a green signal or motion signal VJIT . there must be staff available to respond 6.000 gallons and a cost savings of $1. without which some failures may go unnoticed for months. resulting in an annual fuel savings of 26.38 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM ratio of 17:1. Augustine.  We have two roads – the highway road and the side road or country road with the highway road having the higher priority of the two that is it is given more time for motion which implies that the green signal remains for a longer time along the highway side rather than on the country side. and 8 percent in travel time. showed reductions of 36 percent in arterial delay.1 million. with reductions of 14 percent in delay. 13 percent in stops. 49 percent in arterial stops. Florida. and YELLOW which carry their usual meanings that of stop go and wait respectively. Although communications networks allow almost instantaneous notification of equipment failure. Improvements to an 11-intersection arterial in St. 8 percent in fuel consumption. GREEN.

2. 6.4 THE OBJECTIVES The following line up as the main objectives of the project. Transform the word description of the protocol into a finite state machine transition diagram. This ensures no jamming of traffic and any accidents at the turnings. 3.39 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM on the highway side for a period of 80 seconds and that on the country road of 40 seconds and the yellow signal for a time length of 20 seconds. Implement the design onto a FPGA. 4.  We can have provisions for two exceptions along the roads one along the highway and the other along the country side which interrupt the general cycle whenever a exceptions like an emergency vehicle or any such kind of exceptions which have to be addressed quickly.  We have taken into consideration a two way traffic that is the opposite directions along the highway side will be having the same signals that is the movements along the both direction on a single road will be same at any instant of time. VJIT . 1. When these interrupts occur the normal sequence is disturbed and the cycle goes into different states depending on its present state and the interrupt occurrs. Implement a simple finite state machine using VHDL. Simulate the operation of the finite state machine.

using whatever value is on the timing parameter selection switches for the RAM address. The read function causes the controller to enter the memory read state. It responds to the input signals processed by the input handling module and provides the output and control signals needed to make the system function. The FSM has four main groups of states corresponding to the four modes in which the traffic light controller can operate. The second major state group corresponds to the memory write function.1 THE FINITE STATE MACHINE The FSM-FINITE STATE MACHINE is the heart of traffic light controller. Once in that state. In this mode. That combinatorial process also sets the outputs for the next clock cycle. When in the memory write state. the system uses the value of the VJIT . This design uses a standard two process finite state machine where one process is used to change states on every clock cycle while the other process is used to combinatorically calculate what the next state should be based on the current inputs and the current state. the system remains there until reset.40 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 7 THE STATE MACHINE 7. The memory read state also ensures that write enable for the RAM is disabled since the system is only trying to read previously stored values in RAM. the FSM transitions to the memory write state and then returns to the start state.

This ensures that the new value is actually written to RAM.1 DEFINITION OF THE FSM A finite-state machine (FSM) or finite-state automation . It is a behavior model composed of a finite number of states. similar to a flow graph in which one can inspect the way logic runs when certain conditions are met. and an output feature. one at a time without going backward.41 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM timing parameter selection switches for the RAM address lines as in the memory read state. and actions. That ensures that we never write to the RAM while either data or address values are changing. The operation of an FSM begins from one of the states (called a start state). transitions between those states. an input feature that reads symbols in a sequence. VJIT . is a mathematical abstraction sometimes used to design digital logic or computer programs. however only a certain set of states mark a successful flow of operation (called accept states). which may be in the form of a user interface. goes through transitions depending on input to different states and can end in any of those available. 7. One crucial feature of this design is that the system is only in the memory write state for one cycle. It has finite internal memory.1. but asserts the memory write enable control signal. or simply a state machine. once the model is implemented. thus the RAM write enable is never high for more than a single clock cycle.

it can be said to record information about the past.rules or conditions which must be met to allow a state transition. . A current state is determined by past states of the system. which may possibly trigger rules and lead to state transitions.g. As such.states which define behavior and may produce actions. D flip-flops) to store the current state 2) combinational logic to compute the next state 3) combinational logic to compute the output 7.e. ..1.state transitions which are movement from one state to another. . i.2 WORKING PRINCIPLE OF AN FSM Finite state machines consist of 4 main elements.1. The number and VJIT . it reflects the input changes from the system start to the present moment.input events which are either externally or internally generated.2 Notion of States in Sequential Machines A state machine is a type of sequential circuit structure which can allow you to create more elaborate types of digital systems.42 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 7. A state machine consists of: 1) memory elements (e.

A transition indicates a state change and is described by a condition that would need to be fulfilled to enable the transition. 7. inputs. An action is a description of an activity that is to be performed at a given moment. if the memory is three bits long. A basic FSM has a memory section that holds the present state of the machine (stored in FF) and a control section that controls the next state of the machine (by clocks.The outputs and VJIT . and present state).1.g. there are 8 possible states.43 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM names of the states typically depend on the different possible states of the memory. e. There are several action types: Entry action which is performed when entering the state Exit action which is performed when exiting the state Input action which is performed depending on present state and input conditions Transition action which is performed when performing a certain transition.3 IMPLEMENTATION OF A FSM State Variable: The variable held in the SM (FF) that determines its present state.

The best way to visualize a FSM is to think of it as a flow chart or a directed graph of states. Fig 7. Received input events act as triggers. which cause an evaluation of some kind of the rules that govern the transitions from the current state to other states. though as will be shown.44 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM internal flip flops (FF) progress through a predictable sequence of states in response to a clock and other control inputs. and a current state which remembers the product of the last state transition.1 A POSSIBLE FINITE STATE MACHINE VJIT . there are more accurate abstract modeling techniques that can be used. A finite state machine must have an initial state which provides a starting point.

allowing for easy testing .Low processor overhead. and perhaps a small amount of logic to determine the current state. VJIT . quick to implement and quick in execution FSM is an old knowledge representation and system modeling technique. Only the code for the current state need be executed.Due to their simplicity.4 ADVANTAGES OF FSM . and it is easy to incorporate many other techniques . and its been around for a long time. the state transition can be predicted. There are a number of ways to implement a FSM based system in terms of topology.FSMs are relatively flexible. FSMs are quick to design. well suited to domains where execution time is shared between modules or subsystems.Their simplicity make it easy for inexperienced developers to implement with little to no extra knowledge (low entry level) . given a set of inputs and a known current state.45 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 7. with lots of examples to learn from .1.Predictability (in deterministic FSM).Easy to transfer from a meaningful abstract representation to a coded implementation . as such it is well proven even as an artificial intelligence technique.

it is immediately obvious whether a state is achievable from another state.46 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM .. However. the outputs are computed by a combinational logic block whose inputs are only the flip-flops state outputs.2 TYPES OF STATE MACHINES There are two basic ways to design clocked sequential circuits . The state diagram for a Mealy machine associates an output value with each transition edge (in contrast to the state diagram for a Moore machine. Accordingly. which associates an output value with each state).1 MEALY MACHINE In the theory of computation. the state machines. 7. the outputs may change asynchronously in response to any change in the inputs.i. a Mealy machine is a finite- state machine whose output values are determined both by its current state and by the values of its inputs. 7. VJIT . In a Mealy machine.e. A combinational logic block maps the inputs and the current state into the necessary flip-flop inputs to store the appropriate next state just like Mealy machine.2.Easy determination of reachability of a state. the outputs are a function of the present state and the value of the inputs. when represented in an abstract form. and what is required to achieve the state.

whose output values are determined both by its current state and by the values of its inputs. The outputs change synchronously with the state transition triggered by the active clock edge.47 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM fjig 7. A combinational logic block maps the inputs and the current state into the necessary flip-flop inputs to store the appropriate next state just like Mealy machine.2 MOORE MACHINE A Moore machine is a finite-state machine whose output values are etermined solely by its current state. VJIT .2. (This is in contrast to a Mealy machine. the outputs are computed by a combinational logic block whose inputs are only the flip-flops state outputs. which associates an output value with each transition edge).) The state diagram for a Moore machine associates an output value with each state (in contrast to the state diagram for a Mealy machine. However.

Clocked sequential systems are a restricted form of Moore machine where the state changes only when the global clock signal changes. The instant the current state changes.3 MECHANISM Most digital electronic systems are designed as clocked sequential systems. A typical electronic Moore machine includes a combinational logic chain to decode the current state into the outputs (lambda). There are design VJIT . those changes ripple through that chain. and a global clock signal is connected to the "clock" input of the flip-flops. and almost instantaneously the outputs change (or don't change).2.48 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM fhdhhj 7. Typically the current state is stored in flip-flops.

Then define the next states and outputs from the state diagram. Draw a state diagram (bubble) to implement the problem. etc. VJIT . until the Moore machine changes state again. power stays connected to the motors. Define all present states and inputs in a binary sequence. Define the actual problem. The outputs then stay the same indefinitely (LEDs stay bright. but most systems are designed so that glitches during that brief transition time are ignored or are irrelevant.49 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM techniques to ensure that no glitches occur on the outputs during that brief period while those changes are rippling through the chain. Classical Design: Makes use of state tables.5 CLASSICAL DESIGN APPROACH 1. and Karnaugh Mapping to find FF input control logic. 7. 7. FF excitation tables. 2. solenoids stay energized. VHDL Design: Uses case statements or IF THEN ELSE statements to set the design and the logic synthesis tools to define equation. 3. 4. Make a state table.).2.4 FSM DESIGN TECHNIQUES FSM’s can be designed in two appropriate ways.2.

6. we proceed with the VHDL design approach for implementation of our design .2. Find the output values for each present state/input combination. Without any doubt.  An FSM uses a CASE statement on the enumerated type state variable. VJIT . Use FF excitation tables to determine in what states the FF inputs must be to cause a present state to next state transition. 7. Simplify Boolean logic for each FF input and output equations and design logic.50 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 5.6 VHDL FSM DESIGN APPROACH   Uses an enumerated type to declare state variables. Enumerated Type: A user-defined type in which all possible values of a named identifier are listed in a type definition. 7.

the changes to red and yellow and then moves to state 3 where the lights change to red both. We initially reset them.51 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM STATE DIAGRAM FOR TRAFFIC LIGHT CONTROLLER Fig 7. moving to state 1.1 State diagram for Traffic light controller We consider 2 roads opposite to each other with 5 possible states from 1 to 5. signal on 1 side goes read and other goes green. A Similar process takes place for the remaining states VJIT . And again upto a certain time count. After a certain time period. so that State S0 shows red on both signals.

the highest density of on-chip memory. off-the-shelf programmable Xilinx device. In a single. reduce bill of materials. and get products to market faster than ever before. Xilinx Rocket I/O transceivers offer a complete VJIT . digital clock managers.1. The result is that Xilinx FPGAs helps designers to simplify board layout.1 INTRODUCTION Xilinx leads one of the fastest growing segments of the semiconductor industry – programmable logic devices. systems architects can take advantage of microprocessors.1 Xilinx FPGAs The Xilinx FPGA Spartan3e series has redefined programmable logic by expanding the traditional capabilities of field programmable gate arrays (FPGAs) with new levels of integration and features that address high performance system design issues. Xilinx FPGA Spartan3e FPGAs are available with up to four immersed IBM PowerPC 405 processors and up to 16 high-speed transceivers that operate at 3. multi-gigabit serial transceivers. 8.52 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 8 XILINX 8.125 gigabits per second. on-chip termination and more.

Project Navigator Interface The Project Navigator Interface is divided into four main sub windows.832 logic cells. and debug hardware and software simultaneously at speed. supporting 10 Gigabit Ethernet with XAUI. therefore.168 to 50. as seen in Figure 1-1. even after the product has shipped. Xilinx FPGA Spartan3e devices range in density from 3.2.53 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM serial interface solution. PCI Express and SerialATA. you can maintain revision control through the use of snapshots. On the top left is the Sources in Project window which hierarchically VJIT . Each IBM PowerPC in Xilinx FPGA Spartan3e FPGAs run at 300-plus MHz. delivering 450 Dhrystone MIPS. and is supported by IBM CoreConnect bus technology. Overview of ISE and Synthesis Tools Overview of ISE ISE controls all aspects of the design flow. You can also access the files and documents associated with your project. you can access all of the various design entry and design implementation tools. Through the Project Navigator interface. 8. systems designers can for the first time partition and repartition their systems between hardware and software at any time during the development cycle. Project Navigator maintains a flat directory structure. With Xilinx FPGA Spartan3e FPGAs.

54 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM displays the elements included in the project. and which is updated during all project actions. Default Layout can always restore the default layout. These windows are discussed in more detail in the following sections. Each window may be resized. errors. The third window at the bottom of the Project Navigator is the Console window which displays status messages. Beneath the Sources in Project window is the Processes for Current Source window which displays available processes. The fourth window to the right is a multidocument Interface (MDI) window for viewing ASCII text files and HDL Bencher™ Waveforms. undocked from Project Navigator or moved to a new location within the main Project Navigator window. and warnings. Selecting View Restore. Figure 1-1: Project Navigator VJIT .

HDL files have this + to show the entities (VHDL) or modules (Verilog) within the file. Select Help_ISE Help Contents. For a complete list of possible source types and their associated icons. If a file contains lower levels of hierarchy. which provide information for the user. You can expand the hierarchy by clicking the +. schematic. The icon indicates the file type (HDL file.55 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Sources in Project Window This window consists of three tabs. the icon has a + to the left of the name. and design source files. A snapshot is a copy of the project including VJIT . Module View The Module View tab displays the project name. for example). seethe Project Navigator online help. Each tab is discussed in further detail below. select the Index tab and click Source / file types. Snapshot View The Snapshot View tab displays all snapshots associated with the project currently open in Project Navigator. or text file. any user documents. the specified part type and design flow/synthesis tool. core. Each file in the Module View has an associated icon. You can open a file for editing by double-clicking on the filename.

Processes for Current Source Window This window contains the Process View tab. The Process Window provides access to the following functions VJIT . All information displayed in the Snapshot View is read-only. you can run the functions necessary to define. and source files for all snapshots. From the Process View tab. Using snapshots provides an excellent version control system. and synthesis and simulation subdirectories. A snapshot is stored with the project for which is taken. user documents. run and view your design. and can be viewed in the Snapshot View. Process View The Process View tab is context sensitive and changes based upon the source type selected in the Sources for Project window. Library View The Library View tab displays all libraries associated with the project open in Project Navigator.56 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM all files in the working directory. enabling sub teams to do simultaneous development on the same design. You can view the reports.

Synthesis Provides access to Check Syntax. instantiation templates. Implement Design Provides access to implementation tools. For example.57 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Design Entry Utilities Provides access to symbol generation. View RTL Schematic. This varies depending on the synthesis tools you use. synthesis. Generate Programming File Provides access to the configuration tools and bit stream generation. The Processes for Current Source window incorporates auto make technology. User Constraints Provides access to editing location and timing constraints. and simulation library compilation. design flow reports. and point tools. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step. Launch MTI. HDL Converter. when you run VJIT . View Command Line Log File. and synthesis reports.

and from the menu select Go to Source. Warning and Error messages may also be viewed separately from other console text messages by selecting either the Warnings or Errors tab at the bottom of the console window. expand Design Entry Utilities and select View Command Line Log File. Console Window The Console window displays errors. The HDL source file opens and the cursor moves to the line with the error.58 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM the Implementation process. Project Navigator also runs the synthesis process because implementation is dependent on up-to-date synthesis results. while warnings have a yellow box. Error Navigation to Source You can navigate from a synthesis error or warning message in the Console window to the location of the error in a source HDL file. select the error or warning message. and informational messages. Note: To view a running log of command line arguments in the Console window. VJIT . right-click the mouse. Errors are signified by a red box next to the message. To do so. warnings.

The synthesis tool uses the design’s HDL code and generates a supported netlist type (EDIF or NGC for the Xilinx® implementation tools).xilinx. VJIT . Next. and from the menu select go to Solution Record.com website. The synthesis tools perform three general steps (although all synthesis tools further breakdown these general steps) to create the netlist: Analyze / Check Syntax Checks the syntax of the source code. These type of errors or warnings can be identified by the web icon to the left of the error. The default web browser opens and displays all solution records applicable to this message. To navigate to the solution record. right-click the mouse.59 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Error Navigation to Solution Record You can navigate from an error or warning message in the Console window to the relevant solution records on the support. you will synthesize the design. select the error or warning message. Synthesizing the Design So far you have used XST for verifying syntax.

Map Translates the components from the compile stage into the target technology’s The RTL Viewer XST can generate a schematic representation of the HDL code that you have entered. 2. click + next to Synthesize to expand the process hierarchy. In Project Navigator. VJIT . Double-click View RTL Schematic. To view a schematic representation of your RTL code: 1.60 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Compile Translates and optimizes the HDL code into a set of components that the synthesis tool can recognize. A schematic view of the code is helpful for analyzing your design to see a graphical connection between the various components that XST has inferred.

Other options include controlling the maximum fan out of a signal from a flip-flop or setting the desired frequency of the design.vhd (or stopwatch. 3. in the ―Modifying Constraints‖ section above. Click the Constraint File Options tab. Click the Synthesis Options tab. One option is to control synthesis by optimizing based on area or speed. From the menu.v). 7. set the global synthesis options: 1. 2.61 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM FIGGGGGGGG Entering Synthesis Options through ISE Synthesis options enable you to modify the behavior of the synthesis tool to optimize according to the needs of the design. Click the Netlist Options tab. and select the stopwatch. 4. 5. and set the Default Frequency to 50MHz. Click OK to accept these values.ctr file created in LeonardoSpectrum. select Properties. Select stopwatch. and ensure that the Do Not Write NCF box is unchecked. VJIT . 6. Right-click the Synthesis process. For this tutorial.

To launch the design in LeonardoSpectrum’s RTL viewer. A schematic view of the code is helpful for analyzing your design to see a graphical connection between the various components that LeonardoSpectrum has inferred. Select stopwatch. LeonardoSpectrum Synthesis Processes Overview of Behavioral Simulation Flow Behavioral simulation is done before the design is synthesized to verify that the logic you have created is correct.62 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 8. double-click the View RTL Schematic process. This allows a designer to find and fix any bugs in the design before spending time with Synthesis or Implementation. The following figure displays the design in an RTL view.v) and double-click the Synthesize process in theProcesses for Source window The RTL/Technology Viewer LeonardoSpectrum can generate a schematic representation of the HDL code that you have entered.vhd (or stopwatch. VJIT .

This Guide is available with the collection of software manual and is accessible from ISE by selecting Help___Online Documentation.xilinx. refer to Chapter 6 of Synthesis and Verification Guide. VJIT . For additional information about simulation and for a list of the other supported simulators.or from the web at http://support.63 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Xilinx® ISE provides an integrated flow with the ModelTech ModelSim simulator that allows simulations to be run from the Xilinx Project Navigator graphical user interface (GUI). The examples in this tutorial show how to use this integrated flow.com/support/sw_manuals/xilinx6/.

entity tlc is port(clk. architecture beh of tlc is signal state.sb) begin ra<='0'.y.ga.yb<='0'.gb<='0'. type light is(r.std_logic_1164. end tlc. ra.sa.ga<='0'.ya.g).1 Source code: library ieee.rb<='0'.sa.sb:in std_logic.64 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 9 SOURCE CODE AND SIMULATION RESULTS 9.gb.rb. ya<='0'. use ieee.all.yb:buffer std_logic). signal lighta. case state is VJIT . nextstate : integer range 0 to 12.lightb:light. begin process(state.

process(clk) begin if clk='1' then state<=nextstate.yb<='1'. end if. when 5=>ga<='1'.rb<='1'. end process. when 7 to 10=>ra<='1'. VJIT . if(sa='1' or sb='0')then nextstate<=12. end process. nextstate<=0.gb<='1'. when 12=> ra<='1'.rb<='1'.65 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM when 0 to 4 => ga<='1'. nextstate<=7. nextstate<=state+1. when 6=>ya<='1'. when 11=>ra<='1'.gb<='1'. end if. end if. end case. nextstate<=state+1.rb<='1'. if sb='1' then nextstate<=6.

2 Simulation Result: simulation output waveform for traffic light controller VJIT . lightb<=r when rb='1' else y when yb='1'else g when gb='1'. end beh. 9.66 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM lighta<=r when ra='1' else y when ya='1'else g when ga='1'.

Inc. --> Parameter TMPDIR set to D:/New Folder (2)/traffic/traffic/xst/projnav.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation VJIT .67 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 10 SYNTHESIS REPORT Release 10.33 secs --> Parameter xsthdpdir set to D:/New Folder (2)/traffic/traffic/xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.xst K.00 secs Total CPU time to Xst completion: 0. All rights reserved.33 secs --> Reading design: tlc.31 (nt) Copyright (c) 1995-2008 Xilinx.1 .tmp Total REAL time to Xst completion: 0.

1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================== =============== * Synthesis Options Summary * ========================================================== =============== ---.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.Source Parameters Input File Name Input Format : "tlc.1) Device utilization summary 9.68 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.prj" : mixed VJIT .

Target Parameters Output File Name Output Format Target Device : "tlc" : NGC : xc3s500e-4-fg320 ---.69 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Ignore Synthesis Constraint File : NO ---.Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing : tlc : YES : Auto : No : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES VJIT .

70 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM ROM Style Mux Extraction Resource Sharing : Auto : YES : YES : NO Asynchronous To Synchronous Multiplier Style : auto Automatic Register Balancing : No ---.General Options Optimization Goal : Speed VJIT .Target Options Add IO Buffers Global Maximum Fanout : YES : 500 : 24 Add Generic Clock Buffer(BUFG) Register Duplication Slice Packing : YES : YES Optimize Instantiated Primitives : NO Use Clock Enable Use Synchronous Set Use Synchronous Reset Pack IO Registers into IOBs Equivalent register Removal : Yes : Yes : Yes : auto : YES ---.

71 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Optimization Effort Library Search Order Keep Hierarchy Netlist Hierarchy RTL Output Global Optimization Read Cores Write Timing Constraints Cross Clock Analysis Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio BRAM Utilization Ratio Verilog 2001 Auto BRAM Packing Slice Utilization Ratio Delta :1 : tlc.lso : NO : as_optimized : Yes : AllClockNets : YES : NO : NO :/ : <> : maintain : 100 : 100 : YES : NO :5 ========================================================== =============== * HDL Compilation * ========================================================== =============== VJIT .

WARNING:HDLParsers:3607 .vhd". Architecture beh of Entity tlc is up to date. and is now defined in "D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd".Unit work/tlc is now defined in a different file.vhd".Unit work/tlc/beh is now defined in a different file. and is now defined in "D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd". It was defined in "D:/vhdl/traffic/aaaaaaa. Compiling vhdl file "D:/New Folder (2)/traffic/traffic/aaaaaaa. It was defined in "D:/vhdl/traffic/aaaaaaa. ========================================================== =============== * Design Hierarchy Analysis * ========================================================== =============== Analyzing hierarchy for entity <tlc> in library <work> (architecture <beh>).72 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM WARNING:HDLParsers:3607 . ========================================================== * HDL Analysis * ========================================================== VJIT .vhd" in Library work.

It is preferable to declare it as output.vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation. INFO:Xst:1739 .vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation.vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation.HDL ADVISOR ."D:/New Folder (2)/traffic/traffic/aaaaaaa."D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation. VJIT .73 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Analyzing Entity <tlc> in library <work> (Architecture <beh>). INFO:Xst:1739 HDL ADVISOR "D:/New Folder (2)/traffic/traffic/aaaaaaa."D:/New Folder (2)/traffic/traffic/aaaaaaa.HDL ADVISOR . INFO:Xst:1739 . INFO:Xst:1739 .vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.HDL ADVISOR . It is preferable to declare it as output."D:/New Folder (2)/traffic/traffic/aaaaaaa. It is preferable to declare it as output. INFO:Xst:1739 -HDL ADVISOR . It is preferable to declare it as output.

vhd" line 33: One or more signals are missing in the process sensitivity list.. To enable synthesis of FPGA/CPLD hardware. XST will assume that all necessary signals are present in the sensitivity list. VJIT . It is preferable to declare it as output.74 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM INFO:Xst:1739 -HDL ADVISOR . The missing signals are: <nextstate> Entity <tlc> analyzed. WARNING:Xst:819 .vhd" line 5: declaration of a buffer port will make it difficult for you to validate this design by simulation."D:/New Folder (2)/traffic/traffic/aaaaaaa. Please note that the result of the synthesis may differ from the initial design specification. Synthesizing Unit <tlc>. Related source file is "D:/New Folder (2)/traffic/traffic/aaaaaaa."D:/New Folder (2)/traffic/traffic/aaaaaaa.. Unit <tlc> generated. ========================================================== =============== * HDL Synthesis * ========================================================== =============== Performing bidirectional port resolution.vhd".

Latches may be generated from incomplete case or if statements.Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This unconnected signal will be trimmed during the optimization process. This situation will potentially lead to setup/hold violations and.HDL ADVISOR . VJIT .Found 4-bit latch for signal <state>. This unconnected signal will be trimmed during the optimization process. You should carefully review if it was in your intentions to describe such a latch. Found 4-bit adder for signal <nextstate$addsub0000>. INFO:Xst:2371 . Found 4-bit 13-to-1 multiplexer for signal <nextstate$mux0000>.Signal <lightb> is assigned but never used. Summary: inferred 1 Adder/Subtractor(s). We do not recommend the use of latches in FPGA/CPLD designs. WARNING:Xst:737 . as a result.75 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM WARNING:Xst:646 . as they may lead to timing problems. WARNING:Xst:737 . We do not recommend the use of latches in FPGA/CPLD designs.Signal <lighta> is assigned but never used. as they may lead to timing problems. Unit <tlc> synthesized. inferred 4 Multiplexer(s). to simulation problems. WARNING:Xst:646 .Found 4-bit latch for signal <nextstate>. This situation may come from an incomplete case statement (all selector values are not covered). Latches may be generated from incomplete case or if statements.

HDL ADVISOR .76 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM INFO:Xst:1767 .Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. ========================================================== =============== HDL Synthesis Report Macro Statistics # Adders/Subtractors 4-bit adder # Latches 4-bit latch # Multiplexers 4-bit 13-to-1 multiplexer :1 :2 :2 :1 :1 :1 ========================================================== =============== * Advanced HDL Synthesis * ========================================================== =============== VJIT . For improved clock frequency you may try to disable resource sharing.

77 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Loading device for application Rf_Device from file '3s500e.1\ISE. ========================================================== =============== Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors 4-bit adder # Latches 4-bit latch # Multiplexers 4-bit 13-to-1 multiplexer :1 :2 :2 :1 :1 :1 ========================================================== =============== * Low Level Synthesis * ========================================================== =============== VJIT .nph' in environment C:\Xilinx\10.

========================================================== =============== Final Register Report Found no macro ========================================================== =============== ========================================================== =============== * Partition Report * ========================================================== =============== VJIT .....78 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Optimizing unit <tlc> .. Building and optimizing final netlist . actual ratio is 0. Found area constraint ratio of 100 (+ 5) on block tlc.. Mapping all equations. Final Macro Processing ...

ngr : tlc : NGC : Speed : NO Design Statistics # IOs :9 VJIT . ------------------------------- ========================================================== =============== * Final Report * ========================================================== =============== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy : tlc.79 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Partition Implementation Status ------------------------------- No Partitions were found in this design.

80 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Cell Usage : # BELS # # LUT3 LUT4 : 12 :2 : 10 :8 :8 :1 :1 :8 :2 :6 # FlipFlops/Latches # LD # Clock Buffers # BUFGP # IO Buffers # # IBUF OBUF ========================================================== =============== Device utilization summary: --------------------------- Selected Device : 3s500efg320-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: 7 out of 4656 0% 0% 0% 8 out of 9312 12 out of 9312 VJIT .

--------------------------- ========================================================== =============== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.81 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Number of IOs: Number of bonded IOBs: Number of GCLKs: 9 9 out of 1 out of 232 24 3% 4% --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. VJIT . FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design VJIT . INFO:Xst:2169 . and XST is not able to identify which are the primary clock signals.82 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Clock Information: -------------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | --------------------------------------+------------------------+-------+ nextstate_not0001(nextstate_not0001:O)| NONE(*)(nextstate_0) | 4 clk | BUFGP |4 | | --------------------------------------+------------------------+-------+ (*) This 1 clock signal(s) are generated by combinatorial logic.HDL ADVISOR . Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

207ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================== =============== Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 23 / 6 ------------------------------------------------------------------------Offset: Source: Destination: Source Clock: 6.207ns (Levels of Logic = 2) state_2 (LATCH) gb (PAD) clk falling VJIT .83 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.

00 secs Total CPU time to Xst completion: 4.9% logic.555ns route) (74.704 0.652ns logic.41 secs --> Total memory usage is 158008 kilobytes VJIT .676 1. 1.1% route) ========================================================== =============== Total REAL time to Xst completion: 4.447 gb1 (gb_OBUF) 3.84 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Data Path: state_2 to gb Gate Net fanout Delay Delay Logical Name (Net Name) Cell:in->out ---------------------------------------.-----------LD:G->Q LUT4:I0->O OBUF:I->O 11 0.272 gb_OBUF (gb) ---------------------------------------Total 6.207ns (4. 25.108 state_2 (state_2) 2 0.

85 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM Number of errors : Number of warnings : Number of infos : 0 ( 0 filtered) 7 ( 0 filtered) 9 ( 0 filtered) VJIT .

86 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 11 RTL Schematics: RTL Schematics: VJIT .

87 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CHAPTER 12 VJIT .

taking designing of AES . qualitative and total security improvement of this pro \ VJIT . Thus there is scope for both quantitative.In our project.we are successful in bringing the AES in our design implementation using VHDL. VHDL coupled with simulation tools provides the designers with option of modeling in parts and the advantages of checking the correctness of the design as it evolves.88 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM CONCLUSION The Project mainly deals with the chip level modeling. During the course of the project we have realized and experienced the definite advantages that a hardware description language offers over the conventional method of designing. There is a great scope for development in the project . we also learned about the AES that are in market today.

www.pdf www.pdf www.digilentinc.xilinx.J 2.xilinx..com/itp/xilinx10/books/docs/qst/qst.STEPHEN BROWN AND ZVONKO VRANESIC 4..com/support/sw_manuals/xilinx6/.PERRY 3. VJIT .89 FPGA-BASED ADVANCED REAL TIME TRAFFIC LIGHT CONTROLLER SYSTEM BIBLOGRAPHY BOOKS: 1.DOUGLAS L.com/.com/appnotes/ise-10.xess.BHASKAR./Tutorials/.HALL ― VHDL PRIMER ― ― VHDL ― ―FUNDEMENTAS OF DIGITAL LOGIC WITH VHDL DESIGN‖ ―MICROPROCESSORS AND INTERFACING‖ WEB SITES: http://support.DOUGLAS V.

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