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DESIGN AND SIMULATION OF CMOS INVERTER WITH TANNER TOOL
Un de r t h e Gu idan c e of Dr. Man is h a Pat t an aik
Designed by - Basanta Bhowmik
Jayveer Singh Bhadauriya
Co n t e n t s :
S ch em a t ic d es ign ……………………………………………..0 3 -1 9 Pr e la you t s im u la t ion ………………………………………..2 0 -2 6 La you t d es ign ………………………………………………….2 7 -5 0 Des ign r u le ch eck (DRC)…………………………………….5 1 -5 3 E xt r a ct ion ………………………………………………………5 4 -5 6 La you t Vs s ch em a t ic(LVS )………………………………….5 7 -6 2 Pos t la you t s im u la t ion ………………………………………6 3 -6 5 Gen er a t ion of GDS II file(MAS K)…………………………..6 6 -7 2 Ap p en d ix ……………………………………………………….7 3 -7 6 MOS IS Des ign r u le …………………………………………….7 3 E xt r a ct ed file/ La you t Net lis t …………………………………7 4 GDS II E xp or t file……………………………….....................7 5 GDS II Im p or t file….….…………………………………………7 6
S c h e m at ic de s ign o f In v e rt e r
What is schematic Design: There are many phases or progressions of a design. A common term you will hear when working with a Designer is “Schematic Design”. This phase is early in the design process. Schematic Design establishes the general scope, conceptual ideas, the scale and relationship of the various program elements. The primary objective of schematic design is to arrive at a clearly defined feasible concept based on the most promising design solutions.
Op en in g S -ed it p la t for m : Fir s t of a ll d ou b le click on t h e icon of s -ed it on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0
A new window will open: .
Go to >>file >> New >> New Design Select New Design .
One dialog box will appear Design Name : Give the name your design as you wish Create a Folder : Give the path where you want to save the S-Edit Files. Then Click on ‘OK’ .
Give the path where Libraries are stored . As for example C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13.tanner .Now to add libraries in your work click on Add .0\Libraries\All\All. left on the library window.
Now to create new cell Go to cell menu >> New view -Select ‘New view’ .
The new cell will appear like below: Design = your design name Cell = cell no. Design name should be changed only when you are going to design another circuit) View type = schematic Interface name = “by default” View name = “by default” Then press “OK”. . ( cell no you can change but your design name inv will be same for different cell.
You can again bring these window from view menu bar.Then a cell will be appeared where we can draw the schematic of any circuit. then you can close the Find & command window. You can change grid distance by clicking on black screen and then scroll the mouse. In the black window you have seen some white bubble arranged in specific order. This is called grid. . If you want your screen big enough for design space .
To make any circuit schematic . for example inverter a) Go to >>libraries & click on device then all device will be open. .
:.b) Select any device e.g. instance (then the dailog box instance cell will appear. then click on .NMOS Device.) .
Then click DONE or press ESC. Go to properties >> change the parameter values as your requirement. Now before clicking DONE you have to DRAG the selected device into the cell and drop it where you want it to FIX .In instance cell You can change the values of various device parameters according to your requirements. .
. For inverter we need another Pmos.Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit.
Go to tool bar and select wire. .Now connect two device with wire.
Similarly to give input & output port in the circuit . . select input port that shown by red ellipse.
Then click OK Similarly give Output Port name. .Now you can give Port name as you wish in the dailog box. NOTE : you can rotate the port (short cut key “R”).
For that Go to liberaries >> MISC >>Select VDD or GND . after completed these steps.Now. you should give the supply (VDD) & ground (GND).
Now you have to create a source of VDD. By doing all the above steps you have completed schematic of Inverter . you can give any value in vdd .lets take vdd =5v. For that go to libraries >>spice_element >> and then select voltage source of type DC .
For s im u la t ion go t o>> t ools >> T-s p ice>> ‘ok ’ . That’s why you need to simulate the design which is called Pr e la you t s im u la t ion .Pre lay o u t s im u lat io n After schematic design you have to check whether your design match with the specification required or not .
Then click on the bar shown by red ellipse .A T-spice window will open.
On the T-spice command you can see in the left hand side Analysis.A “T-spice command Tool “ dialog box will open as shown beow. Output Settings Table Voltage source Optimization . Current source Files Initialization.
For that Go to >> T-spice command tool >> Files >> Include >> browse TSMC .18um\MODEL_0. Step 1 : You have to include TSMC 0.18 µm Technology file .18µm files >> Insert command.Lets start doing transient analysis of Inverter.IIIT-3AC288AD0A\Desktop\TSMC 0.18. C:\Documents and Settings\Bhowmik.md .
Step2 : Then to give Input T-spice command tool >> Voltage source >> select type of input you want to give(lets take bit) >> Insert command Step 3: Analysis T-spice command tool >> Analysis >> select type of analysis you want to give(lets take transient) >> Insert command step 4: Output T-spice command tool >> Output >> which output you want to see >> Insert Command .File is included shown by highlight.
. Then Run by clicking red ellipse shown on left above corner.The total spice netlist will come like this. Now save it .
Output of Pre layout simulation of Inverter .
There is a continuing need for the creation of new layoutdesigns which reduce the dimensions of existing integrated circuits and simultaneously increase their functions.Layout Design What is Layout Design: A layout-design of an IC refers essentially to the 3-dimensional character of the elements and interconnections of an IC.0 >> L-Edit v 13. Pro c e du re o f Lay o u t De s ign in 0 .0 .1 8 µm CMOS Te c h n o lo gy (MOS IS >> Mam in 0 8 ) Op en in g L-ed it p la t for m : Fir s t of a ll d ou b le click on t h e icon of L-ed it on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.
75 µm w= 1.50 µm .5 µm L= 3. We will start the layout of Inverter with NMOS PMOS w= 1.5 µm L =2.A window will come like below.
.>> select A dialog box will come as shown in fig Select layout and then press ‘ok’.For inverter layout Go to file>> new….
A new layout window will open .
.Carefully observe the Red ellipse which will be frequently used for your Design.
In TSMC .Before starting layout design you have to set the Technology you want to used. available Technology are Charterd China_hj Generic0_25 µm Mosis Orbit So to set the Technology Go to >> File >> Replace setup and then select .18 µm Technology.
A small dialog box will come and it tells you . Mosis design rule are given in appendix.0 >>L-edit and LVS >> TECH >> Mosis >> mamin08 or mamin12 or …………or………… >> press ok After pressing ‘ok’ . That means you have to follow Mosis design rule in your entire design.Technology are going to be changes. Lets take in the above set up you set Mosis ->Mamin08 Technology. Click on browse >> Tanner EDA >> Tanner Tools v13.A dialog box will come. . In that stage press ok.
You can choose your own for better understandig and drawing the design. For that Go to >> set up >> Design >> then select In the” Set up design layout2 “dialog box you have seen there are many technology units. Also for “Technology to micron mapping “ I have taken 1 lambda=0.5 micron . I have choosen Lambda rule for convenience.Now lets recheck your technology set up.you can choose any one of them for your design. .
In the same way select grid For design convenience and properly maintain the DRC . Atlast press ok . Now you properly create the environment for design. . I have taken Major diplayed grid=10 lambda Minor diplayed grid=1 lambda (You put according to your calculation) Like that many other parameter you can change that’s depends upto you.
You have two option for any Design . We will follow first procedure.Lets take example of Inverter First: For inverter design first of all you have to create a PMOS and a NMOS in the same window. The device will come in cell window. But In the library some standard devices available which are not enough for your requirement all the time .g mamin08) >> press ok >> a series of devices which are available in the library will come >> seect EXT_NMOS or EXT_PMOS >> press ok . BY default The cell window is P-type. So for design Pmos you need N-substrate that means Select N-well >> select switch to draging box (left upper corner of the window) >> draw . Or Second:You can bring a PMOS and NMOS from the Library .source and drain will be P-type and pollysilicon Gate. For that Go to Cell >> Instance >> browse the Technology what you are using (e.That’s why you need a good practice to Design all the way from start to end of the Design. For PMOS you need a N –type substrate .which is already available. So first of all design a PMOS.This is a bad practice.
Then Select P-select >> select switch to draging box (left upper corner of the window) >> draw
Now Select Active >> select switch to draging box (left upper corner of the window) >> draw
Now Select Active >> select switch to draging box (left upper corner of the window) >> draw
In the same way draw Nmos . So the procedure is first draw a n-select then then draw the active area and then polysilicon gate.Here not required p-well because the window is already p-type. .
After designing Nmos and Pmos you have to connect them .g PMOS source and substrate will be connected to VDD and Nmos source and substrate will be connected to Gnd.Nmos drain are connected to output and both gate are connected to Input. Pmos . e.Vdd and Gnd you have to take Metal 1 layer.drain . For source . To connect Pmos substrare to Vdd you need N-select and Metal -1 layer .
To connect Nmos substrare to Gnd you need P-select and Metal -1 layer .
Now connect source and vdd of pMOS by Metal-1 layer .
Put active contact of size 2µm×2 µm .
.shown by red ellipse.Now connect nMOS drain to pMOS drain and nMOS source to Gnd by metal-1 layer.
Put active contact . .
To make contact on Polysilicon.Now Connect both Gate as shown below. you need metal-1 (3µm×3 µm)layer and Poly contact of size (2µm×2 µm) .
To give name to input output port. click to “Switch to drawing ports” as shown below: .
After clicking on the “Switch to drawing ports”. . click on that part of the layout where you want to give name of the port. As for example to give name Vdd you have to select the Metal-1 layer shown in figure.
. Then save your design.After giving name to each port. your layout look like as shown below.
DESIGN RULE CHECK(DRC) Design Rule Check (DRC) is the area of Electronic Design Automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules. check out “DRC Standard Rule Set” then press OK. Design rules are specific to a particular semiconductor manufacturing process. Go to >>setup DRC >> select One dialog box will come as shown below. Design rule checking is a major step during Physical verification signoff on the design. Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. .
Now run” DRC” shown by red ellipse. .
After running “DRC”. if there is no error that means your design satisfies Design rule check. .
probably for the same reason the netlisting is broken) allows you to compare a schematic and an extracted physical layout to verify that they are equivalent ( i. . The extracted view also allows you to run LVS (Layout vs Schematic). click on “setup extract”. the netlisting is not working at that moment. signals are connected the same way) To extract. Unfortunately. This tool (which is also not working at the moment. check extract standard rule set if it is not checked and then click on pencil icon as shown below. then a setup extract dialog box will open. but we can still generate the extracted view from which a netlist can be generated (once we fix the installation).e. you need to extract the spice netlist from the layout then simulate it.EXTRACT To verify the functionality and timing of this inverter.
0 >> L –edit and LVS >> Tech >> Mosis >> mamin08. . Output-> Names. Then Press ‘OK’.include mamin08.md file must be included in spice included Statement.After clicking on pencil icon. in that window give path of Extract Definition File. Subcircuit-> optional.write . Note: (check General -> open output file after extracting and all others are optional . If you not give proper path of Extract definition file then a dialog box will come showing you “I/O Error cannot open file”. “Setup Extract Standard Rule Set” window will open. Browse >> My document >> Tanner EDA >> Tanner Tools v13.End statement .Write verbose spice statements. All others are optional.
drain area. Then warning will come like below. A extracted file or netlist contaninig device details like connections. Netlist or Extracted file of the inverter shown in appendix.At this stage click on Ignore all. perimeter.and juntion capacitances will come .source area.aspect ratio . .To extract click on EXT toolbar shown by highlighting.
the terminals of these devices. If the two netlists match. At this point it is said to be "LVS clean . 2. LVS checking software recognizes the drawn shapes of the layout that represent the electrical Components of the circuit. It then runs the database through many area based logic operations. Area based logical operations use polygon areas as inputs and generate output polygon areas from these operations. . These operations are used to define the device recognition layers. This netlist is compared by the "LVS" software against a similar schematic or circuit diagram's netlist. as well as the connections between them. LVS Checking involves : 1. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. then the circuit passes the LVS check and a message will come “the circuit are equal”. 3. and the locations of pins (also known as hierarchical connection points).Lay o u t Vs s c h e m at ic (LVS ) The Layout Versus Schematic (LVS) is the class of EDA verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. A similar reduction is performed on the "source" Schematic netlist. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. Reduction: In the time of reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database. the wiring conductors and via structures.
Op en in g LVS p la t for m : Fir s t of a ll d ou b le click on t h e icon of LVS V1 3 .0 >> LVS v 13.0 .0 on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.
A new window will come as shown below. .
Then go to >>file >> new >> LVS setup >> ok .
the are basically optional.options.Select input. paracitics. After checking click on run verification(shown by red ellipse) .md file from both netlist ). merge device. In the input you have to import Layout netlist and Schematic netlist. Note: (don’t forget to remove .include……………… . Select output.performance . device parameter.
That means your LVS checking is complete and your layout design perfectly same as schematic of your design. In final report a message will shows “The circuits are equal”. .A dialog box verification will come.
The electrical performance of a full-custom design can be best analyzed by performing a postlayout simulation on the extracted circuit net-list. At this point. in order to achieve the desired circuit performance under "realistic" conditions. the designer should have a complete mask layout of the intended circuit/system. until the post-layout simulation results satisfy the original design requirements.e. and any glitches that may occur due to signal delay mismatches. you should perform a post-layout simulation from the extracted view. The procedure is identical to that for simulating from the schematic view. taking into account all of the circuit parasitics. and should have passed the DRC and LVS steps with no violations. the influence of circuit parasitics (such as parasitic capacitances and resistances). In order to get an idea of how the design would work from your layout.Po s t lay o u t s im u lat io n The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design. This may require multiple iterations on the design. you should modify some of the transistor dimensions and/or the circuit topology. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed. If the results of post-layout simulation are not satisfactory.. i. .
For post layout simulation Open layout netlist >> rest of the process is same as prelayout simulation. .
Output of post layout simulation : .
GDSII is like Gerber for PCBs.Ge n e rat io n o f GDS II file (MAS K) GDS II stream format.13um) . It is a binary file format representing planar geometric shapes. Crosstalk. and other information about the layout in hierarchical form. text labels. This is especially true for the new nanometer technologies (below 0. or creating photomasks. is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. including Metal top layer(s). The data can be used to reconstruct all or part of the artwork to be used in sharing layouts. common acronym GDSII. route problems. and other DRCs are taken under account to shorten up the "Timing Closure" cycle process. Signal Integrity. Alike Gerber. critical placements. The Term RTL-to-GDSII refers to a design methodology where already in the RTL stage. It is a format that ASIC Foundries accept for the manufacture of ASICs/VLSIs (mainly standard cells). transferring artwork between different tools. GDSII contains Masks layers (as many as 24 to 30).
To generate GDS II file go to >> File >> Export Mask Data >> GDSII >> ok .
After Exporting .This is basically optional.00 seconds . Elapsed Time: 0. It will tell you the details of Exporting.a GDSII Export file will come .A Export GDSII dialog box will come . Shown by red ellipse If you want log file to save . Summary: Export Successful. click on the “Export” button.then first click on it and give a new name . Like below. Last of the report something written .
Then close the layout cell(not layout window) and import GDSII (MASK) file. For that go to >> File >> Import Mask Data >> GDSII >>ok .
.Click on the “Import”.
Press “ok” .
As for example in the below shows a mask of Inverter .After Importing you will get MASK of your Design.
Appe n dix MOS IS De s ign ru le Rule number RI R2 R3 R4 R5 R6 R7 Description Active area rules Minimum active area width Minimum active area spacing Polysilicon rules Minimum poly width Minimum poly spacing Minimum gate extension of poly over active Minimum poly-active edge spacing (poly outside active area) Minimum poly-active edge spacing (poly inside active area) Metal rules Minimum metal width Minimum metal spacing Contact rules Poly contact size Minimum poly contact spacing Minimum poly contact to poly edge spacing Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size Minimum active contact spacing (on the same active region) Minimum active contact to active edge spacing Minimum active contact to metal edge spacing Minimum active contact to poly edge spacing Minimum active contact spacing (on different active regions) λ Rule 3λ 3λ 2λ 2λ 2λ 1λ 3λ R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 3λ 3λ 2λ 2λ 1λ 1λ 3λ 2λ 2λ 1λ 1λ 3λ 6λ .
75u AD=12.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13.6875p PS=14u $ (25 7 28 12.19:26 .01 .5u AS=15.Extracted file/Netlist of Layout * Circuit Extracted by Tanner Research's L-Edit Version 13.5u W=2.5 28 34.md * Warning: Layers with Unassigned AREA Capacitance. * <PMOS Capacitor> * <Pad Comment> * <NMOS Capacitor> * <PCAP Capacitor> M1 Out In Gnd Gnd NMOS L=1. * <PMOS Capacitor> * <NMOS Capacitor> * <PCAP Capacitor> * Warning: Layers with Unassigned FRINGE Capacitance.5) * Total Nodes: 4 * Total Elements: 2 * Total Number of Shorted Elements not written to the SPICE file: 0 * Output Generation Elapsed Time: 0.875p PD=15.5u AD=14.20 * Extract Definition File: C:\Documents and Settings\Bhowmik.5u W=3.5) M2 Out In Vdd Vdd PMOS L=1.5u AS=11.0\L-Edit and LVS\Tech\Mosis\mamin08.75p PS=16u $ (25 27.tdb * Cell: Cell0 Version 1.include mamin08.ext * Extract Date and Time: 08/28/2011 . * TDB File: E:\layout\layout\Layout2.01 / Extract Version 13.000 sec * Total Extract Elapsed Time: 10.375p PD=14.484 sec .END .
Completed writing actual GDSII data .. Writing actual GDSII data . Fracture polygons: OFF Manufacturing grid for circle and curve approximation: 0. Checking GDSII Numbers . Checking for Hidden Layers and Objects .GDSII Export File GDSII Export. 1 database unit = 0...gds Option Settings: Do not export hidden objects: ON Overwrite data type on export: ON Calculate MOSIS checksum: OFF Check for self-intersecting polygons and wires: OFF Write XrefCells as links: OFF Preserve case of cell names: ON Restrict cell names to 32 characters... Summary: Export Successful. TDB File: E:\layout\layout\Layout2....001 Lambda All ports with port boxes will be converted to point ports Checking XrefCell links . All cells are being exported Use custom GDSII units: 1 database unit = 0...tdb GDSII File: E:\layout\layout\Layout2.001 user units. Elapsed Time: 0.0005 microns.00 seconds ...
0 error(s).gds ....08 seconds .. 8 warning(s) Import Successful Elapsed Time: 1.tmp Option Settings: Treat unique GDS data types on a layer as different layers: ON Using original GDSII database resolution: 0..III\LOCALS~1\Temp\tdb6C..gds SetupFile: C:\DOCUME~1\BHOWMI~1.GDSII Import File GDSII Import. GDSII File: E:\layout\layout\Layout2. Summary: E:\layout\layout\Layout2.0005 microns Warning #33: Found unknown GDSII layer 47 (Action: Created a new layer GDS_47_DT_00 for GDSII number 47 and Data type 0) Warning #33: Found unknown GDSII layer 46 (Action: Created a new layer GDS_46_DT_00 for GDSII number 46 and Data type 0) Warning #33: Found unknown GDSII layer 43 (Action: Created a new layer GDS_43_DT_00 for GDSII number 43 and Data type 0) Warning #33: Found unknown GDSII layer 49 (Action: Created a new layer GDS_49_DT_00 for GDSII number 49 and Data type 0) Warning #33: Found unknown GDSII layer 42 (Action: Created a new layer GDS_42_DT_00 for GDSII number 42 and Data type 0) Warning #33: Found unknown GDSII layer 45 (Action: Created a new layer GDS_45_DT_00 for GDSII number 45 and Data type 0) Warning #33: Found unknown GDSII layer 44 (Action: Created a new layer GDS_44_DT_00 for GDSII number 44 and Data type 0) Warning #33: Found unknown GDSII layer 48 (Action: Created a new layer GDS_48_DT_00 for GDSII number 48 and Data type 0) Checking for Cell Name Conflicts. Resolving External Cell References.
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