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State transition diagram:

Reset

S0 000

U/D

S1 001

U/D

S2 010

U/D

S3 011

U/D'

U/D'

U/D'

U/D'

U/D

U/D'

U/D

U/D
S7 111 S6 110

U/D
S5 101

U/D
S4 100

U/D'

U/D'

U/D'

CT

State transition table for 3-bit synchronous binary up/down counter has shown below:

State S0 S1 S2 S3 S4 S5 S6 S7

PS 000 001 010 011 100 101 110 111

U/D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

NS 111 001 000 010 001 011 010 100 011 101 100 110 101 111 110 000

J2K2 1 X 0 X 0 X 0 X 0 X 0 X 0 X 1 X X 1 X 0 X 0 X 0 X 0 X 0 X 0 X 1

J1K1 1 X 0 X 0 X 1 X X 1 X 0 X 0 X 1 1 X 0 X 0 X 1 X X 1 X 0 X 0 X 1

J0K0 1 X 1 X X 1 X 1 1 X 1 X X 1 X 1 1 X 1 X X 1 X 1 1 X 1 X X 1 X 1

CT 0 0 0 0 0 0 0 1

K-MAP:

00 0 1

01 U/D` X 0 X

11

10 U/D X 0 X

J2 = U/D`Q1`Q0`+U/DQ1Q0

00 0 1 X

01 X 0

11 X

10 X 0

U/D`

U/D

K2= U/D`Q1`Q0`+ U/D Q1Q0

00 0 1

01 U/D` U/D`

11 U/D U/D X X

10 X X

J1=

00 0 1 K1= X X

01 X X

11

10 U/D U/D U/D` U/D`

00 0 1 1 1

01 X X

11 X X

10 1 1

J0= 1

00 X X

01 1 1

11 1 1

10 X X

K0= 1

00 0 1 0 0

01 0 0

11 0 1

10 0 0

CT= Q2Q1Q0

Part 2:
Design of a Synchronous Controller A digital system is controlled by a synchronous sequential controller which its operation is described by the state transition diagram of Figure 1.

State table: State Present state


Q2 Q1 Q0

Sync.I/P
ST RE T WAI T

N.STATE FLIP- FLOPS


Q2 Q1 Q0
J2 K2 J1 K1 J0 K0

OUTPUT RE D X 1 X 1 0 BU SY 0

S0

0 1

X X 0 1 X X X X X X

X X X X X X X X 0 1

0 0 0 1 0

0 0 1 0 0

1 0 1 1 0

0 0 0 1 0

X 0 X 0 X 1 X 0

X 1 X 0

S1

X X

X X 0 X X 0 X 1

S2

X X

X X 1

S3

X X

X 0

X X 0

S4

1 1

X X

1 0

1 1

1 1

X 0 X 1

X 0 X 0

X 0 X 0

K MAP:

00 0 1 0 X

01

11 RET X 0 X

10 X X

J2=RET*Q0*Q1`

00 0 1 X X

01 X 0

11 X

10 X X

WAIT

K2= WAIT*Q1

00 0 1 0 X

01

11 RET 1 X X

10 X X

J1=Q0*RET`

00

01

11
6

10

0 1

X X

X X

1 0

X X

K1=Q2`

00 0 1

01 ST X X X

11 X X

10 X X

J0=ST`

00 0 1 X X

01 0 0

11 1 0

10 X X

K0= Q1*Q2`

00 0 1 X

01 0 X

11

10 0 X X

Ready=

00 0 1 X

01 0 X

11

10 0 X X

Busy: