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Cadence OpAmp Schematic Design Tutorial for
TSMC CMOSP35
Till Kuendiger, Joseph Schrey, Iman Taha, Yi Lin,
Tao Dai, Li Liang, SongTao Huang, Yue Huang
December 7, 2001
Contents
Preface iv
1 Introduction 1
1.1 Review of CMOS FET’s . . . . . . . . . . . . . . . . . . . . . 1
1.2 Creating a New Library in Cadence . . . . . . . . . . . . . . . 2
1.3 Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Virtuoso Schematic Editor . . . . . . . . . . . . . . . . 4
1.3.2 Virtuoso Symbol Editor . . . . . . . . . . . . . . . . . 5
1.3.3 Aﬃrma Analog Circuit Design Environment . . . . . . 6
1.3.4 The Waveform Window . . . . . . . . . . . . . . . . . 7
1.3.5 The Cadence Calculator . . . . . . . . . . . . . . . . . 8
1.4 Generating the Characteristic MOSFET Curves . . . . . . . . 9
1.4.1 Nchannel EnhancementType MOSFET . . . . . . . . 9
1.4.2 Pchannel EnhancementType MOSFET . . . . . . . . 14
2 An Introduction to OpAmps 17
2.1 Parameters of an OpAmp . . . . . . . . . . . . . . . . . . . . 17
2.1.1 Oﬀset Voltage . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.2 Input Current . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.3 Input Common Mode Voltage Range . . . . . . . . . . 19
2.1.4 Maximum Output Voltage Swing . . . . . . . . . . . . 19
2.1.5 Output Impedance . . . . . . . . . . . . . . . . . . . . 20
2.1.6 CommonMode Rejection Ratio . . . . . . . . . . . . . 20
2.1.7 Supply Voltage Rejection Ratio . . . . . . . . . . . . . 21
2.1.8 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.9 Unity Gain Bandwidth and Phase Margin . . . . . . . 22
2.1.10 Settling Time . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 Methodology of Choosing OpAmp Parameters . . . . . . . . 24
2.3 How to Adjust the Parameters . . . . . . . . . . . . . . . . . 25
i
CONTENTS ii
2.3.1 Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.2 Procedure of Optimization . . . . . . . . . . . . . . . 25
2.3.3 Optimize the Parameters of the OpAmp . . . . . . . 27
2.3.4 How to get the Quiescent point in a complex circuit . 33
2.4 Target OpAmp Speciﬁcations . . . . . . . . . . . . . . . . . . 34
3 Current Mirrors and Biasing Networks 35
3.1 Ideal Characteristics of a Current Mirror . . . . . . . . . . . . 36
3.2 Basic Current Mirror Derivation . . . . . . . . . . . . . . . . 36
3.3 Benchmark Test Circuit . . . . . . . . . . . . . . . . . . . . . 38
3.4 Examined Current Mirrors . . . . . . . . . . . . . . . . . . . . 39
3.4.1 Basic Current Mirror . . . . . . . . . . . . . . . . . . . 39
3.4.2 Cascade/Cascode Current Mirror . . . . . . . . . . . . 41
3.4.3 Wilson Current Mirror . . . . . . . . . . . . . . . . . . 43
3.4.4 Modiﬁed Wilson Current Mirror . . . . . . . . . . . . 44
3.4.5 Reduced Cascade Current Mirror . . . . . . . . . . . . 45
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Diﬀerential Input Stage 48
4.1 The Unbuﬀered OpAmp . . . . . . . . . . . . . . . . . . . . 48
4.2 Small Signal Equivalent Circuits . . . . . . . . . . . . . . . . 49
4.3 The Frequency Response . . . . . . . . . . . . . . . . . . . . . 53
4.4 Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5 Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.6 Adding R
z
in series with C
c
. . . . . . . . . . . . . . . . . . . 60
4.7 Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . 61
4.8 Large Signal Consideration . . . . . . . . . . . . . . . . . . . 62
4.9 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.10 The CommonMode Range . . . . . . . . . . . . . . . . . . . 64
4.11 Important Relationships for The Design . . . . . . . . . . . . 66
4.12 Tradeoﬀs for Increasing the Gain of the Two Stage OpAmp. 66
4.13 Design Methodology for the Two Stage OpAmp . . . . . . . 67
4.14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.15 Limitations of the Two Stage OpAmp . . . . . . . . . . . . . 72
4.16 The Cascode OpAmp . . . . . . . . . . . . . . . . . . . . . . 72
5 Inverting Ampliﬁers 76
5.1 Inverter with Active Resistor Load . . . . . . . . . . . . . . . 77
5.2 Inverter with Current Source/Sink Load . . . . . . . . . . . . 83
5.3 PushPull Inverter . . . . . . . . . . . . . . . . . . . . . . . . 87
CONTENTS iii
5.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6 Control Network and Output Stage 95
6.1 Classiﬁcation of Output Stage . . . . . . . . . . . . . . . . . . 96
6.2 ClassA Output Stage . . . . . . . . . . . . . . . . . . . . . . 96
6.2.1 Simple output ampliﬁer using a ClassA, currentsource
inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.2 CommonDrain (SourceFollower) Output Ampliﬁer . 98
6.2.3 Power Analysis . . . . . . . . . . . . . . . . . . . . . . 98
6.3 ClassB Output Stage . . . . . . . . . . . . . . . . . . . . . . 99
6.3.1 PushPull, Inverting CMOS ampliﬁer . . . . . . . . . 99
6.3.2 Power Analysis . . . . . . . . . . . . . . . . . . . . . . 101
6.4 ClassAB Output Stage . . . . . . . . . . . . . . . . . . . . . 101
6.5 Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . 102
6.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.7 Design Considerations . . . . . . . . . . . . . . . . . . . . . . 106
6.7.1 Negative Feedback . . . . . . . . . . . . . . . . . . . . 106
6.7.2 Frequency Compensation . . . . . . . . . . . . . . . . 106
7 Integrating the SubCircuits 108
7.1 Overall Performance . . . . . . . . . . . . . . . . . . . . . . . 109
7.2 The Measurement of Some Main Parameters . . . . . . . . . 110
7.2.1 Input Oﬀset Voltage . . . . . . . . . . . . . . . . . . . 110
7.2.2 CommonMode Rejection Ratio (CMRR) . . . . . . . 112
7.2.3 Output Resistance  R
o
. . . . . . . . . . . . . . . . . 114
7.3 Delivering Power to the Load/Instantaneous Power . . . . . . 117
7.4 Improving the Output Buﬀer . . . . . . . . . . . . . . . . . . 118
7.4.1 Stabilizing the Output . . . . . . . . . . . . . . . . . . 120
7.4.2 The Final Schematic . . . . . . . . . . . . . . . . . . . 121
8 Closing Remarks 122
8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9 Bibliography 124
Preface
The purpose of this document is to familiarize the reader with the Cadence
set of tools in order to do analog microelectronic circuits. The design process
will use TSMC’s CMOSP35 technology and as a result requires access to the
restricted technology ﬁles.
iv
Chapter 1
Introduction
This tutorial assumes that the user is working in the CMC supplied envi
ronment for CMOSP35 design.
1.1 Review of CMOS FET’s
The Complimentary Metal Oxide SemiConductor Field Eﬀect Transistor is
a four terminal device: Base, Emitter, Collector and Substrate. Unlike the
Bipolar Transistor the MOSFET is a symmetrical device: the source and
drain can be interchanged.
The models which SPICE uses for the CMOSP35 technology are very
accurate, however, are too complex to be used by humans. A quick overview
of the device operation follows, for a more complete discussion please refer
to an appropriate text book. The gate of the device is insulated from the
rest of the device, meaning that no current will ﬂow into the gate of a
MOSFET. The substrate connection, for an Nchannel transistor, is always
connected to V
SS
(which usually means ground). When the voltage on the
gate of the device is large enough an inversion layer forms under the gate,
between the drain and source. This means that a channel of charge carriers
exists between the two Ntype regions. For an Nchannel transistor these
charge carriers will be electrons. This allows current to ﬂow from the source
terminal to the drain terminal. Some generalized relationships are stated
below.
1
CHAPTER 1. INTRODUCTION 2
I
ds
= µ
eff
C
ox
W
L
__
V
g
−V
fb
−2ψ
B
−
V
ds
2
_
V
ds
_
−µ
eff
C
ox
W
L
_
2
√
2ε
si
qN
a
3C
ox
_
(2ψ
B
+V
ds
)
3
2
−(2ψ
B
)
3
2
_
_
(1.1)
1.2 Creating a New Library in Cadence
Once Cadence has been started the icfb window is shown. This is the main
window for Cadence; all messages, including error and warning messages,
will be displayed in this window.
Figure 1.1: Cadence icfb Window with CMOSP35 technology
In order to create a new library select the following menu options:
Tools → Library Manager
From the Library Manager window it is possible to access all available
libraries and to create new libraries. In order to create a new library:
File → New → Library
This will popup a new window where the library name can be speciﬁed.
In this example we will use the name mylib.
Once you have entered the name of the library which is to be created,
press OK. The next dialog will ask information about the technology ﬁle
which is to be associated with the new library. For this tutorial we will be
using CMOSP35, therefore, select Attach to existing techﬁle: this will bring
another dialog window which lets us select which technology ﬁle we will use.
Select cmosp35.
CHAPTER 1. INTRODUCTION 3
Figure 1.2: Cadence Library Manager
Figure 1.3: New
Library Dialog
Window
Figure 1.4: Technol
ogy File For New Library
Window
Figure 1.5: Attach Design Library Window
CHAPTER 1. INTRODUCTION 4
1.3 Schematic Capture
In this section we will be showing step by step how to enter a circuit
schematic into Cadence’s Virtuoso Schematic Editor and how to create a
symbol view for the schematic using the Virtuoso Symbol Editor. This sec
tion will not give a circuit directly, but rather leave the reader to use some
of the schematics presented later in the document (Section 1.4 is a good
starting circuit for a novice user).
In order to create a new Cell View, open the Library Manager and click
on the new library which has been created, followed by:
File → New → Cell View
A dialog window will appear asking for the name of the new Cell View:
enter OpAmp. This will automatically open the schematic capture session.
1.3.1 Virtuoso Schematic Editor
Figure 1.6) is the main window from which all of the schematic capture is
performed. Along the left boarder of the window are iconbuttons which
allow for easy access to the more common commands. Moving the mouse
cursor over these windows will show a tooltip which explains which com
mand is executed with each button. All commands are also available via the
menus at the top of the window. Most commands will also have a shortcut
key associated with them.
When a schematic is entered the Insert Instance but is used (alterna
tively Add → Instance may be used) is used in order to place components
into the schematic. We will mostly be using transistors, resistors and ca
pacitors (which are found in the library cmosp35) and power supplies and
grounds (which are found in the library analogLib). If the exact name of
the desired cell is not known the Browse button may be used to open the
Library Manager and graphically select the component. Components are
connected with narrow wires which may also be added via the iconbuttons
or the menus.
When an instance of a component is added to a schematic all of the
available parameters to the model may be set. These parameters may be
changed later using the Properties option. Some parameters are mandatory
to be entered (e.g. power supply voltage) whereas some parameters will
default to certain values if they are not entered. Values may also be set to
variables, by entering a string instead of a numeric value, which can be set
CHAPTER 1. INTRODUCTION 5
Figure 1.6: Cadence Virtuoso Schematic Editor
in the simulation stage.
Once a design has been entered, it can be saved with a Check and Save
iconbutton. This will do a general check of the circuit in order to make sure
that all circuits have and ground and that all device terminals are connected
to something.
An example of schematics for generating the characteristic curves is
shown in Section 1.4. We will not discuss all of the options available for
this window since they are very numerous and are mostly selfexplanatory.
1.3.2 Virtuoso Symbol Editor
Once the schematic for the circuit is done, a symbol view must be created.
This is the view which is used when an instance of the circuit is put into
another schematic (e.g. a test bench circuit). Create a ”default symbol” by
clicking:
Design → Create Cell View → From Cell View
Simply except the defaults and this opens the Symbol Editor. On start
up the symbol editor will have a plain looking rectangle with terminal pins
for each I/O pin inserted in the schematic. Once again we will simply accept
the defaults and
In order to use the circuit which has been created is it necessary to
create a test bench circuit. This test bench circuit is created similarly to
the original circuit, except that no symbol is generally required. The symbol
of the newly created circuit may be inserted as any other subcircuit.
CHAPTER 1. INTRODUCTION 6
1.3.3 Aﬃrma Analog Circuit Design Environment
Once a test bench circuit has been created and saved it is possible to start
the simulation environment:
Tools → Analog Environment
The Aﬃrma window, ﬁgure 1.7, is the window from which all simulations
are conﬁgured and executed.
Figure 1.7: Aﬃrma Analog Environment Simulation Window
In order to run a simulation there are several things which must be
deﬁned:
• Selecting a simulator. The Avant StarHSPICE simulator is the best
simulator available; in order to select the simulator: Setup → Simu
lator. In the dialog window which appears change the simulator se
lection to hspiceS; click OK. It is also important to deﬁne the en
vironment for the simulator so that all of the correct models ﬁles
are used by the simulator: Setup → Environment. The dialog box
which appears contains a ﬁeld entitled Include File. Set this ﬁeld to
/CMC/kits/cmosp35/models/hspice/icdhspice.init,click OK.
• Setting variables from the schematic. If there are any parameter set
tings which are set to variables, these variables must be copied from
the cell view to the analog environment: Variables → Copy From Cell
view. All variables which appear in the cell view will now be listed in
the bottom left of the Aﬃrma window. By doubleclicking the vari
ables it is possible to change the value of the variable for the next
simulation run. All variables must be assigned values before a simula
tion may be performed.
CHAPTER 1. INTRODUCTION 7
• Selecting and conﬁguring the simulations. There are several types of
simulations which may be performed at the same time. In order to
choose the simulation settings: Simulation → Choose. Most of the
parameters available in the simulation settings are relatively straight
forward and are left to the reader to lookup.
• Selecting which variables are saved/plotted from the simulation. The
last step required to run a simulation is to set which variables should
be plotted and saved. By default not all variables are saved since
this could lead to vary large amounts a data being generated by the
simulation, this becomes more important for larger designs. In order
to plot/save a set of values: Outputs → To Be Plotted → Select on
Schematic. This allows the user to click on all nodes (voltages) and
device terminals (currents entering/leaving) in the schematic. The
schematic should reﬂect which nodes/terminals have been selected.
Once the selection is done press ESC.
Simulation may now be started by using the menu system or with the
iconbuttons located on the right side of the Aﬃrma window.
1.3.4 The Waveform Window
Once the simulation is complete all outputs which were selected to be plot
ted, will be in Waveform Window, Figure 1.8.
Figure 1.8: Waveform Window
The Waveform Window allows may customizations in order to generate
desired plots; it is possible to add annotations, titles, modify plot ranges
& axis and add additional plots. Most of these options are fairly straight
CHAPTER 1. INTRODUCTION 8
forward and will not be discussed in detail, the reader is encouraged to
experiment with the various display options.
One of the more advanced features available from the window is the
calculator which is discussed in the next section.
1.3.5 The Cadence Calculator
The Cadence Calculator is an extremely powerful tool for analyzing data
generated by the simulation. Some of the many features of the Calculator
are: basic arithmetic operations on waveforms, Discrete Fourier Transforms,
Total Harmonic Distortion analysis, and many more.
Figure 1.9: Cadence Calculator
The calculator allows entry of waveform information by a variety of ways.
One way of easily accessing the data is to use the wave button and followed
by selecting one of the waveform’s displayed in the waveform window. If the
simulation contains a larger number of simulated values than the browser
button may be employed to browse through all of the information stored
from the simulation.
The order in which operations are entered into the calculator may be
counter intuitive to new users: The calculator uses a Postﬁx notation. The
table below shows some examples of the default order of operations:
a +b a, b, +
a ∗ b +c a, b, ∗, c, +
sin a + cos b b, cos, a, sin, +
In the above table each letter represents one expression/waveform from the
simulation. The display stack options is useful for evaluating large expres
sions. In order to learn more about the many functions available in the
calculator the reader should refer to the Cadence documentation.
CHAPTER 1. INTRODUCTION 9
1.4 Generating the Characteristic MOSFET Curves
The enhancementtype MOSFET (MetalOxide Semiconductor FieldEﬀect
Transistor) is the most widely used ﬁeldeﬀect transistor in the FET family,
which signiﬁcance is on par with that of the bipolar junction transistor,with
each having its own areas of application. The currentcontrol mechanism is
based on an electric ﬁeld established by the voltage applied to the control
terminal. And the current is conducted by only type of carrier(electrons or
holes) depending on the type of FET (N channel or P channel).
1.4.1 Nchannel EnhancementType MOSFET
The transistor is fabricated on a Ptype substrate, which is a singlecrystal
silicon wafer that provides physical support for the device. Two heavily
doped ntype regions, the source and the drain regions, are created in the
substrate. A thin (about 0.1um) layer of silicon dioxide(SiO2) is grown
on the surface of the substrate, covering the area between the source the
drain regions. Metal is deposited on top of the oxide layer to form the gate
electrode of the device. Metal contacts are also made to the source region,
the drain region,and the substrate, also known as the body. Thus, four
terminals are brought out: the Gate(G), the Source(S), the Drain(D), and
the Body(B).
Observe that the substrate forms PN junctions with the source and drain
regions. In normal operation these PN junctions are kept reversebiased at
all time. Since the drain will be at a positive voltage relative to the source,
the two PN junctions can be eﬀectively cut oﬀ by simply connecting the sub
strate terminal to the source terminal.Here, the substrate will be considered
as having no eﬀect on device operation, and the MOSFET will be treated
as a 3terminal device, with the terminals being the gate(G), the source(S),
and the drain(D). We applied a voltage to the gate controls current ﬂow
between source and drain. This current will ﬂow in the longitudinal direc
tion from drain to source in the region called ”channel region”. Note that
this region has a length L and a width W, two important parameters of the
MOSFET. Typically, L is in the range 1 to 10 µm, and W is in the range 2
to 500 µm.
The operation with V
ds
With no bias voltage applied to the gate, two backtoback diodes exist
in series between drain and source. They prevent current conduction from
drain to source when a voltage V
ds
is applied. In fact, the path between
drain and source has a very high resistance (of the order of 10
12
Ω)
CHAPTER 1. INTRODUCTION 10
With a positive voltage, which exceed the threshold voltage V
t
, applied
to the gate, the transistor induced a nchannel. When applying a positive
voltage V
ds
between drain and source, as shown in the ﬁgure below,
Figure 1.10: NChannel Test Circuit
The voltage V
ds
cause a current i
D
to ﬂow through the induced N chan
nel. Current is carried by free electrons travelling from source to drain. The
magnitude of i
D
depends on the density of electrons in the channel, which in
turn depends on the magnitude of V
GS
. As V
GS
exceeds V
t
, more electrons
are attracted into the channel. We may visualize the increase in charge
carriers in the channel as an increase in the channel depth. The result is a
channel of increased conductance or equivalently reduced resistance.
Let V
GS
be held constant at a value greater than V
t
(for example 2V),
and increase the V
DS
from 0 to 3.3V. As V
DS
is increased, the I
D
− V
DS
curve is shown in
Eventually, when V
DS
is increased to the value that reduces the voltage
between gate and channel at the drain end to V
t
, that is :
V
GS
−V
DS
= V
t
or
V
DS
= V
GS
−V
t
the channel depth at the drain end decreases to almost zero, and the channel
is said to be pinched oﬀ. Increase V
DS
beyond this value has little eﬀect
(theoretically, no eﬀect) on the channel shape, and the current through the
channel remain constant at the value reached for V
DS
= V
GS
− V
t
. The
drain current thus saturates at this value, and the MOSFET is said to
CHAPTER 1. INTRODUCTION 11
Figure 1.11: I
D
−V
DS
Curve
have entered the saturation region of operation. The voltage V
DS
at which
saturation occurs is named V
DS,sat
V
DS,sat
= V
GS
−V
t
Obviously, for every value of V
GS
≥ V
t
, there is a corresponding value of
V
DS,sat
. The device operates in the saturation region if V
DS
≥ V
DS,sat
. The
region of the I
D
− V
DS
characteristic obtained for V
DS
< V
DS
,sat is called
the triode region.
The I
D
−V
DS
Characteristics
The Figure above shows a typical set of I
D
−V
DS
characteristics, which
are a family of curves, each measured at a constant V
GS
. We can see that
there are three distinct regions of operation: the cutoﬀ region, the triode
region, and the saturation region. The saturation region is used if the FET
is to operate as a ampliﬁer. For operation as a switch, the cutoﬀ and triode
regions are utilized.
1. Triode
If V
GS
> V
t
and V
DS
≤ V
GS
− V
t
, then the nchannel is continuous
all the way from S to D. The S and D are connected by a conductor
(or a resistor) of a given resistance. The drain current increases if
the voltage drop between S and D increases. The channel resistance
CHAPTER 1. INTRODUCTION 12
Figure 1.12: I
D
−V
DS
Curve
depends on how much charge is injected at the Send, which in turn
is controlled by v
GS
. The Drain current I
d
depends on both v
GS
and
V
GD
(or V
DS
). The I
D
− V
DS
characteristics can be approximately
described by the relationship
I
D
= K [2(V
GS
−V
t
)V
DS
−V
DS
· V
DS
] (1.2)
in which K is a device parameter given by
K = 0.5U
n
· C
ox
_
W
L
_ _
A
V
2
_
(1.3)
U
n
physical constant known as the electron mobility(its value in
this case applies for the electrons in the induced n channel)
C
ox
oxide capacitance, the capacitance per unit area of the
gatetobody capacitor for which the oxide layer serves as
dielectric.
L,W the length and the width of the channel.
Since for a given fabrication process the quantity (0.5U
n
*C
ox
) is a
constant, approximately 10µA/V
2
for the standard NMOS process
with a 0.1µm oxide thickness. So the aspect ratio of
W
L
determines its
conductivity parameter K.
CHAPTER 1. INTRODUCTION 13
If V
DS
is suﬃciently small so that we can neglect the V
DS
· V
DS
in
equation 1.2, then the I
D
− V
DS
characteristics near the origin the
relationship
I
D
∼
= 2K(V
GS
−V
t
)V
DS
(1.4)
This linear relationship represents the operation of the MOS transistor
as a linear resistance R
DS
R
DS
=
V
DS
I
D
=
1
2K(V
GS
−V
t
)
(1.5)
2. Saturation
If V
GS
> V
t
and V
DS
≥ V
GS
−V
t
, then Nchannel is induced at the S
end, but the channel is depleted at the Dend. That is, the Nchannel
is pinched oﬀ at the Drainend. Increasing V
ds
beyond V
ds−(sat)
, or
equivalently decreasing V
GD
below V
t
, creates a fully depleted region
between the inversion nchannel and the drain region. An electric
ﬁeld is set up in this region, pointing from the Drain region toward
the inversion channel. Carrier electrons in the Nchannel that reach
the depletion boundary are swept across the depletion region into the
Drain. This is similar to PN junction diode where the minority carrier
electrons of the Pside are swept to the nside by the builtin ﬁeld
whenever they reach the depletion boundary. Once the drainend of
channel is pinched oﬀ, the current no longer depends on the voltage
apply between S and D.
The boundary between the triode region and the saturation region is
characterized by
V
DS
= V
GS
−V
t
(1.6)
Substituting it into Equation 1.2 gives the saturation value of the
current I
D
is
I
D
= K(V
GS
−V
t
) · (V
GS
−V
t
) (1.7)
Thus in saturation the MOSFET provides a drain current whose value
is independent of the drain voltage V
DS
and is determined by the gate
voltage V
GS
according to the squarelaw relationship.
The complete independence of I
D
on V
DS
in saturation and the corre
sponding inﬁnite output resistance at the drain is an idealization based
on the premise that once the channel is pinched oﬀ at the drain end,
further increases in V
DS
have no eﬀect on the channel’s shape. In prac
tice, increasing V
DS
beyond v
DS
,sat does aﬀect the channel somewhat.
CHAPTER 1. INTRODUCTION 14
Speciﬁcally, as V
DS
is increased, the channel pinchoﬀ point is moved
slightly away from the drain toward the source. Thus the eﬀective
channel is reduced, a phenomenon called channellength modulation.
Since the channel resistance is proportional to the channel length, the
channel resistance is decreased. This results in the slight increase of
the drain current beyond the saturation level. Now since K is in
versely proportional to the channel length (Equation 1.3), so, K and,
correspondingly, I
D
, increases with V
DS
. Mathematically, the channel
length modulation introduces a V
DS
dependent term in I
D
:
I
D
= K(V
GS
−V
t
)(V
GS
−V
t
)(1 +λ · V
DS
) (1.8)
λ the channellength modulation parameter:0.005 < λ < 0.03
From Fig.nid.ps we extrapolated the straightline I
D
−V
DS
character
istics in saturation, intercept the V
DS
axis at the point V
DS
=
−1
λ
=
−V
A
. So v
A
is in the range 200 to 30 volts. It should be obvious that
channellength modulation makes the output resistance in saturation
ﬁnite. Let the output resistance Rout as
R
out
=
1
λ · K(V
GS
−V
t
) · (V
GS
−V
t
)
V
GS
= constant (1.9)
approximated by
R
out
∼
=
1
λ · I
D
(1.10)
substituted by λ =
1
V
A
R
out
∼
=
V
A
I
D
(1.11)
Thus the output resistance is inversely proportional to the DC bias
current I
D
.
3. Cutoﬀ
If V
GS
< V
t
(and of course, V
GD
< V
t
), then the no nchannel is present
and no current ﬂows.
1.4.2 Pchannel EnhancementType MOSFET
A Pchannel enhancementtype MOSFET (PMOS transistor) is fabricated
on an Ntype substrate with p+ regions for the drain and the source, and
holes as charge carriers. The device operates in the same manner as the
Nchannel device except the V
GS
and V
DS
are negative and the threshold
CHAPTER 1. INTRODUCTION 15
Figure 1.13: PChannel Test Circuit
voltage V
t
is negative. Also the current i
D
enters the source terminal and
leaves through the drain terminal.
To induce a channel we apply a gate voltage that is more negative than
V
t
, and apply a drain voltage that is more negative than the source voltage
(i.e. V
DS
is negative or, equivalently, v
SD
is positive). The current i
D
is
given by the same equation as for NMOS, and the K is given by
K = 0.5 · U
p
· C
ox
_
W
L
_
(1.12)
where U
p
is the mobility of holes in the induced p channel. Typically, U
p
∼
=
0.5U
n
, with the result that for the same W/L ratio a PMOS transistor has
half the value of K as the NMOS device.
The I
D
− V
DS
characteristics is shown above. The current I
D
is given
by the same equation used for NMOS.
I
D
= K(V
GS
−V
t
)(V
GS
−V
t
)(1 +λ · V
DS
)
where V
GS
, V
t
, λ, and V
DS
are all negative.
PMOS technology was originally the dominant one. However, because
NMOS devices can be made smaller and thus operate faster, and because
NMOS requires lower supply voltages than PMOS, NMOS technology has
virtually replaced PMOS. Nevertheless, it is important to develop the PMOS
CHAPTER 1. INTRODUCTION 16
Figure 1.14: I
D
−V
DS
Curve
transistor for two reasons: PMOS devices are still available for discrete
circuit design, and more importantly, both PMOS and NMOS transistors
are utilized in CMOS circuits!
Chapter 2
An Introduction to OpAmps
2.1 Parameters of an OpAmp
This section will discuss OpAmp parameters. The designer of an OpAmp
must have a clear understanding of what OpAmp parameters mean and
their impact on circuit design. The selection of any OpAmp must be based
on an understanding of what particular parameters are most important to
the application. In the next section, we will discuss the method of measure
ment of these diﬀerent parameters
2.1.1 Oﬀset Voltage
All OpAmps require a small voltage between their inverting and noninvert
ing inputs to balance mismatches due to unavoidable process variations. The
required voltage is known as the input oﬀset voltage and is abbreviated V
os
.
V
os
is normally modelled as a voltage source driving the noninverting input.
Generally, Bipolar input OpAmps typically oﬀer better oﬀset parameters
than JFET or CMOS input OpAmps. There are two other parameters re
lated to and aﬀect V
os
: the average temperature coeﬃcient of input oﬀset
voltage, and the input oﬀset voltage longterm drift. The average temper
ature coeﬃcient of input oﬀset voltage, a V
os
, speciﬁes the expected input
oﬀset drift over temperature. Its units is
_
mV
o
C
¸
. V
os
is measured at the tem
perature extremes of the part, and a V
os
is computed as
V
os
o
C
. Normal aging in
semiconductors causes changes in the characteristics of devices. The input
oﬀset voltage longterm drift speciﬁes how V
os
is expected to change with
time. Its units are
mV
month
. Input oﬀset voltage is of concern anytime that
DC accuracy is required of the circuit. One way to null the oﬀset is to use
external null inputs on a single OpAmp package (2.1). A potentiometer is
17
CHAPTER 2. AN INTRODUCTION TO OPAMPS 18
Figure 2.1: Oﬀset Voltage Adjust
connected between the null inputs with the adjustable terminal connected
to the negative supply through a series resistor. The input oﬀset voltage
is nulled by shorting the inputs and adjusting the potentiometer until the
output is zero. However, even if the V
os
is nulled at the beginning, it will
change with temperature and some other conditions.
2.1.2 Input Current
The input circuitry of all OpAmps requires a certain amount of bias current
for proper operation. The input bias current, I
IB
, is computed as the average
of the two inputs:
I
IB
=
(I
N
+I
P
)
2
(2.1)
CMOS and JFET inputs oﬀer much lower input current than standard bipo
lar inputs. The diﬀerence between the bias currents at the inverting and
noninverting inputs is called the input oﬀset current, I
os
= I
N
+I
P
. Oﬀset
current is typically an order of magnitude less than bias current.
Input bias current is of concern when the source impedance is high. If
the OpAmp has high input bias current, it will load the source and a lower
than expected voltage is seen. The best solution is to use an OpAmp with
either CMOS or JFET input. The source impedance can also be lowered by
using a buﬀer stage to drive the OpAmp that has high input bias current.
In the case of bipolar inputs, oﬀset current can be nulliﬁed by matching
the impedance seen at the inputs. In the case of CMOS or JFET inputs,
the oﬀset current is usually not an issue and matching the impedance is
not necessary. The average temperature coeﬃcient of input oﬀset current,
CHAPTER 2. AN INTRODUCTION TO OPAMPS 19
Figure 2.2: Output Voltage Swing
I
os
, speciﬁes the expected input oﬀset drift over temperature. Its units are
_
mA
o
C
¸
.
2.1.3 Input Common Mode Voltage Range
The input common voltage is deﬁned as the average voltage at the inverting
and noninverting input pins. If the common mode voltage gets too high or
too low, the inputs will shut down and proper operation ceases. The com
mon mode input voltage range, VICR, speciﬁes the range over which normal
operation is guaranteed. For instance, Rail to rail input OpAmps use com
plementary N and P channel devices in the diﬀerential inputs. When the
commonmode input voltage nears either rail, at least one of the diﬀerential
inputs is still active, and the commonmode input voltage range includes
both power rails.
2.1.4 Maximum Output Voltage Swing
The maximum output voltage, V
OM
, is deﬁned as the maximum positive
or negative peak output voltage that can be obtained without waveform
clipping, when quiescent DC output voltage is zero. V
OM
is limited by
the output impedance of the ampliﬁer, the saturation voltage of the output
transistors, and the power supply voltages. This is shown pictorially in 2.2.
CHAPTER 2. AN INTRODUCTION TO OPAMPS 20
This emitter follower structure cannot drive the output voltage to ei
ther rail. Railtorail output OpAmps use a common emitter (bipolar) or
common source (CMOS) output stage. With these structures, the output
voltage swing is only limited by the saturation voltage (bipolar) or the on
resistance (CMOS) of the output transistors, and the load being driven.
2.1.5 Output Impedance
Diﬀerent data sheets list the output impedance under two diﬀerent condi
tions. Some data sheets list closedloop output impedance while others list
openloop output impedance, both designated by Z
o
. Z
o
is deﬁned as the
small signal impedance between the output terminal and ground. Generally,
values run from 50 to 200Ω .
Common emitter (bipolar) and common source (CMOS) output stages
used in railtorail output OpAmps have higher output impedance than
emitter follower output stages. Output impedance is a design issue when
using railtorail output OpAmps to drive small resistive or large capacitive
loads. If the load is mainly resistive, the output impedance will limit how
close to the rails the output can go. If the load is capacitive, the extra phase
shift will erode phase margin. 2.3 shows how output impedance aﬀects the
output signal assuming Z
o
is mostly resistive.
Figure 2.3: Eﬀect of Output Impedance
2.1.6 CommonMode Rejection Ratio
Commonmode rejection ratio, CMRR, is deﬁned as the ratio of the dif
ferential voltage ampliﬁcation to the commonmode voltage ampliﬁcation,
A
dif
A
com
. Ideally this ratio would be inﬁnite with common mode voltages being
totally rejected.
The commonmode input voltage aﬀects the bias point of the input dif
ferential pair. Because of the inherent mismatches in the input circuitry,
CHAPTER 2. AN INTRODUCTION TO OPAMPS 21
changing the bias point changes the oﬀset voltage, which, in turn, changes
the output voltage.
2.1.7 Supply Voltage Rejection Ratio
Supply voltage rejection ratio, kSVR (AKA power supply rejection ratio,
PSRR), is the ratio of power supply voltage change to output voltage change.
The power voltage aﬀects the bias point of the input diﬀerential pair.
Because of the inherent mismatches in the input circuitry, changing the bias
point changes the oﬀset voltage, which, in turn, changes the output voltage.
For a dual supply OpAmp, KSV R =
V CC
V OS
or KSV R =
V
DD
V OS
. The term
V
CC
means that the plus and minus power supplies are changed symmetri
cally. For a single supply OpAmp, KSV R =
V CC
V OS
or KSV R =
V
DD
V OS
. Also
note that the mechanism that produces kSVR is the same as for CMRR.
Therefore kSVR as published in the data sheet is a DC parameter like
CMRR. When kSVR is graphed vs. frequency, it falls oﬀ as the frequency
increases.
2.1.8 Slew Rate
Slew rate, SR, is the rate of change in the output voltage caused by a step
input. Its units are V/ms or V/ms. 2.4 shows slew rate graphically.
Figure 2.4: Slew Rate
The primary factor controlling slew rate in most amps is an internal
compensation capacitor CC, which is added to make the OpAmp unity
gain stable. Referring to 2.5, voltage change in the second stage is lim
ited by the charging and discharging of the compensation capacitor CC.
The maximum rate of change is when either side of the diﬀerential pair is
conducting 2IE. Essentially SR =
2IE
CC
. However, that not all OpAmps
have compensation capacitors. In OpAmps without internal compensation
capacitors, the slew rate is determined by internal OpAmp parasitic capac
itances. Uncompensated OpAmps have greater bandwidth and slew rate,
but the designer must ensure the stability of the circuit.
CHAPTER 2. AN INTRODUCTION TO OPAMPS 22
Figure 2.5: Op amp schematic simpliﬁed
In OpAmps, power consumption is traded for noise and speed. In order
to increase slew rate, the bias currents within the OpAmp are increased.
2.1.9 Unity Gain Bandwidth and Phase Margin
Unitygain bandwidth (B1) and gain bandwidth product (GBW) are very
similar. B1 speciﬁes the frequency at which A
V D
of the OpAmp is 1.
GBW speciﬁes the gainbandwidth product of the OpAmp in an open loop
conﬁguration and the output loaded:
GBW = AV D · f (2.2)
Phase margin at unity gain (fm) is the diﬀerence between the amount of
phase shift a signal experiences through the OpAmp at unity gain and
180
o
:
fm = 180
o
−f@B1 (2.3)
Gain margin is the diﬀerence between unity gain and the gain at 180
o
phase
shift:
Gain margin = 1 −Gain@180
o
phase shift (2.4)
In order to make the OpAmp stable, a capacitor, C
C
, is purposely fabricated
on chip in the second stage (2.5). This type of frequency compensation is
CHAPTER 2. AN INTRODUCTION TO OPAMPS 23
termed dominant pole compensation. The idea is to cause the openloop
gain of the OpAmp to roll oﬀ to unity before the output phase shifts by
180
o
. 2.5 is very simpliﬁed, and there are other frequency shaping elements
within a real OpAmp. 2.6 shows a typical gain vs. frequency plot for an
internally compensated OpAmp.
Figure 2.6: Voltage Ampliﬁcation and Phase Shift vs. Frequency
Phase margin and gain margin are diﬀerent ways of specifying the sta
bility of the circuit. Since railtorail output OpAmps have higher output
impedance, a signiﬁcant phase shift is seen when driving capacitive loads.
This extra phase shift erodes the phase margin, and for this reason most
CMOS OpAmps with railtorail outputs have limited ability to drive ca
pacitive loads.
CHAPTER 2. AN INTRODUCTION TO OPAMPS 24
2.1.10 Settling Time
It takes a ﬁnite time for a signal to propagate through the internal circuitry
of an OpAmp. Therefore, it takes a period of time for the output to react
to a step change in the input. In addition, the output normally overshoots
the target value, experiences damped oscillation, and settles to a ﬁnal value.
Settling time, t
s
, is the time required for the output voltage to settle to
within a speciﬁed percentage of the ﬁnal value given a step input. Settling
time is a design issue in data acquisition circuits when signals are changing
rapidly.
Figure 2.7: Settling Time
2.2 Methodology of Choosing OpAmp Parame
ters
The methodology of choosing the parameters of the transistors, and their
relationships, then it will be possible to get the desired quiescent point to
ensure the ideal wave output.
Here we will to present a method of choosing the parameter in an Op
CHAPTER 2. AN INTRODUCTION TO OPAMPS 25
Amp circuit, and in the same way we can get a very eﬃcient optimization
method. Further more in this way we can learn how to combine diﬀerent
parts of a circuit together, and deal with more complex circuits. First of all
we must clarify the relationship among diﬀerent parameters, then we can
ﬁnish our job orderly. The quiescent point is very important for our design.
2.3 How to Adjust the Parameters
To simplify the discussion, we will concentrate on the simplest OTA Op
Amp 2.8 and demonstrate how to adjust its parameters to get the proper DC
gain. At the same time we try to extend the method to other sophisticated
architectures.
2.3.1 Speciﬁcation
Here we are asked to design an OpAmp, whose V
DD
= 3.3 V , V
SS
=
0 V , input bias voltage = 1.65V (Input V
0
= 1.65 V ). Swing of output
(Considering the current source V
DD
will occupy some voltage, the swing
should be 0 →3 V .)
Figure 2.8: Circuit with Default Parameters
2.3.2 Procedure of Optimization
1. Draw a circuit with default parameters.(See Figure 2.8).
2. Adjust the current source value I
0
. The current value takes highest
priority of all of the parameters, all of the other parameters will be
chosen to match the current value.
CHAPTER 2. AN INTRODUCTION TO OPAMPS 26
From the circuit, we know that when the OpAmp is working in the
common mode (which means the V
1
= V
0
= 1.65 V ), then the current
through the two (2) diﬀerential ampliﬁers is symmetric, so the value
of I
1
=
1
2
· I
0
. V
out
= 1.65 V , V
ref
= 1.65 V , from here we can
decide what is the maximum and minimum value we can get through
a PMOS. We design a very simple circuit to test the current value
from the drain of a PMOS (Figure 2.9). When changing the width of
the channel of the PMOS, we can get a set of values of the current
value of the drain(Figure 2.10). Considering the width of the active
load should not to be too large so we can get better gain. The range
of the length should be 400nm → 2000 nm, then I
1
should be from
86.4366µA → 800.00µA. So the I
0
should be double I
1
it should be
from 170µA →1700µA.
Figure 2.9: Simple Test Circuit for Drain Current
We can choose any value inside the range, so we regard the 400µm as
the initial value of our design.
3. Decide the width of the channel of the active load. From Figure 2.9 we
perform a parametric analysis. The value of the width of the channel,
through which we can get the proper value for the quiescent point. It
is about 1.25µm.
4. We can assign an arbitrary big value to the width of the diﬀerential
CHAPTER 2. AN INTRODUCTION TO OPAMPS 27
Figure 2.10: Simple Test Circuit  Parametric Analysis of Channel Width
ampliﬁer, suppose we choose a value 5 times bigger than the width of
the active load.
5. Do the simulation and compare the gain we get with the gain we want.
Figure 2.11: Simple Test Circuit  DC Response/Gain
2.3.3 Optimize the Parameters of the OpAmp
1. According to the gain of the speciﬁcation, decide the width of the
diﬀerential ampliﬁer.
G
m
=
_
2K
n
I
0
·
_
W
L
__1
2
R
out
= V
e
L
1
I
0
CHAPTER 2. AN INTRODUCTION TO OPAMPS 28
A
V
= G
m
R
out
= V
e
_
2K
n
W
1
L
1
I
0
_
frac12
There are three (3) variables that will aﬀect A
V
, W, L and I
0
.
If there is small diﬀerence between the two (2) gains, then what we
need to do is just to adjust the value of the length and the width of
the channel of diﬀerential ampliﬁer, otherwise we must reduce the I
0
.
2. Reduce I
0
; according to the fabricating technology, the width of the
channel of the transistor cannot be less than 350µ m, which means we
cannot reduce the I
0
less than 170µA. As mentioned above, otherwise
the quiescent point cannot be at the middle of the curve. (See Figure
2.12), this will distort the input waveform. Each time I
0
is adjusted
the width of the active load should be changed accordingly. Thus
another way to adjust I
0
must be devised.
Figure 2.12: Waveform Distortion
3. Further reducing I
0
. First, we can cascade active loads together, be
cause the voltage is on the cascade active load, there is less voltage
across each transistor, so the I
0
can be reduced dramatically. However,
it becomes more complex to further optimize the circuit. See ﬁgure
2.13
CHAPTER 2. AN INTRODUCTION TO OPAMPS 29
Figure 2.13: Active Loads Cascaded Together
Figure 2.14: Cascaded Active Loads  DC Response/Gain
CHAPTER 2. AN INTRODUCTION TO OPAMPS 30
4. Cascade OpAmp  adjusting the quiescent point: If after all of the
above eﬀort, we still cannot get the proper gain, we have to use a
cascade OpAmp. The key to optimizing the cascade OpAmp is the
quiescent point, which guarantees the proper operation of the circuit.
Please refer the Figure 2.15 (Output curve of ﬁrst the stage).
The output of the ﬁrst stage is linear in the area of (0.5 V →2.15 V ).
So we should adjust the quiescent point of the input of the second
stage.
Figure 2.15: Output Curve of the First Stage
Checking the 2 stage OpAmp, as in Figure 2.16
Figure 2.16: Two Stage OpAmp Circuit
In the second stage ampliﬁer, we get the waveform as shown in Figure
2.17 and Figure 2.18: We notice that the operating point of the am
pliﬁer begins to work is about 0V, actually at this point the output of
CHAPTER 2. AN INTRODUCTION TO OPAMPS 31
Figure 2.17: Second Stage Waveform
the ﬁrst stage is in the nonlinear area. That means the wave we get
isn’t the best.
Figure 2.18: Second Stage Circuit
We can change the parameters of the two (2) transistors, however,
it will have little aﬀect on the nonlinear problem. (See Figure 2.19
NonLinear Problem). Thus we must use another topology. (Figure
2.20).
CHAPTER 2. AN INTRODUCTION TO OPAMPS 32
Figure 2.19: NonLinear Problem
Figure 2.20: Diﬀerent Topology to overcome NonLinear Problem
CHAPTER 2. AN INTRODUCTION TO OPAMPS 33
We then get the resulting waveform shown in Figure 2.21.
Figure 2.21: Resulting Waveform
We can adjust the circuit in another way, to change the input linear
area of the second stage. To simplify the problem we can change the
output stage.
Figure 2.22: Circuit with Modiﬁed Output Stage
2.3.4 How to get the Quiescent point in a complex circuit
Keeping a good quiescent point is very important and can be easily forgotten
as the circuits become more complex. There are certain ways to design with
the help of the computer, and establish models for diﬀerent stages.
CHAPTER 2. AN INTRODUCTION TO OPAMPS 34
2.4 Target OpAmp Speciﬁcations
The table below deﬁnes the best and worst cases for several key OpAmp
parameters, in addition the target OpAmp parameters for this design are
listed. These values are based upon textbook values, fabricated OpAmp
datasheets and from other research. During its design these key parameters
were always kept at close hand.
Speciﬁcation Worst Case Target Case Best Case
Gain 100 →1, 000 1, 000 →100, 000 1,000,000+
Frequency Range (Hz) 1020,000 10200,000 5500,000
Bandwidth 5.0 KHz 20.0 KHz 50.0 KHz
Input Voltage ±1 mV ±1 µV ±0.1 µV
Output Resistance 500 KΩ 1 MΩ 10 MΩ
Power Consumption mW µW nW
CMRR > 40 dB > 50dB > 60dB
Slew Rate 3 V/µsec 2 V/µsec 0.5 V/µsec
THD 1% 0.1% 0.01%
Parasitic Capacitance 1.0 µF 1.0 nF 1.0 fF
Rise Time 1 µsec 0.1 µsec 0.001 µsec
Settling Time 10 µsec 1 µsec 0.1 µsec
Chapter 3
Current Mirrors and Biasing
Networks
One of the most important parts of an analog design is the biasing circuity.
The purpose of the bias circuity is establish an appropriate DC operating
point for the transistor. With the correct DC operating point established a
stable and predictable DC drain current I
D
and a DC drainsource voltage
ensures operation in the saturation region for all input signals that may be
encountered. This component forms the basis for an operational ampliﬁer
whereby various circuits like the diﬀerential pair, gain stage and output
stage rely on its ﬂawless stable operation.
For the Operational Ampliﬁer design ﬁve diﬀerent types of current mir
rors were examined; Basic Current Mirror, Cascade/Cascode Current Mir
ror, Wilson Current Mirror, Modiﬁed Wilson Current Mirror and Reduced
Cascade/Cascode Current Mirror. The advantages and disadvantages of
each type of current mirror will be outlined later.
The ﬁve current mirrors which were examined were designed in Cadence
and were placed into a standard test circuit consisting of a basic diﬀeren
tial pair with active load and basic commonsource ampliﬁer output stage
with a 10KΩ load. These current mirrors were then subjected to several
tests including; DC Sweep, current mirror output impedance and stability
of current supplied across dynamic voltage range.
The ability of a current mirror to hold current constant, the number of
transistors used and their sizes are the general deﬁning factors on whether
a current mirror is ”Good” or not. These factors were considered when de
ciding on the current mirror to be used in the OpAmp Design.
35
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 36
3.1 Ideal Characteristics of a Current Mirror
1. Output current linearly related to the input current. I
out
= A· I
in
.
2. Input Resistance is zero.
3. Output resistance is inﬁnity.
3.2 Basic Current Mirror Derivation
Below is the derivation of the simple current mirror.
Q1 is operating in the saturation region since its drain is shorted to its
gate.
Thus,
I
D1
=
1
2
K
n
_
W
L
_
1
(V
GS
−V
t
)
2
(3.1)
Note we neglect channellength modulation and assume λ = 0.
The drain current of Q1 is supplied by V
DD
through a resistor, R.
Assuming gate currents to be approximately 0.
I
D1
= I
ref
=
V
DD
−V
GS
R
(3.2)
Now looking at Q2,
It has the same V
gs
as Q1, and assuming it is operating in saturation, its
drain current, which is the output current I
o
of the current source will be,
I
O
= I
D2
=
1
2
K
n
_
W
L
_
2
(V
GS
−V
t
)
2
(3.3)
Again neglecting channellength modulation.
Using equations 1,2 and 3 we are able to relate the output current I
o
to
the reference current I
ref
.
Rearranging equation 1 and substituting I
ref
= I
d1
I
ref
_
W
L
_
1
=
1
2
K
n
_
W
L
_
1
(V
GS
−V
t
))
2
(3.4)
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 37
We know,
I
O
=
_
1
2
K
n
(V
GS
−V
t
)
2
_ _
W
L
_
(3.5)
So substituting into equation 3.5,
I
O
=
I
ref
_
W
L
_
1
·
_
W
L
_
2
I
O
I
ref
=
_
W
L
_
2
_
W
L
_
1
(3.6)
Thus we have a relationship whereby modifying the width and length we
can change the output current.
Thus if the transistors were matched, i.e. width and lengths equal and
other parameters the same we have,
I
O
I
ref
= 1 (3.7)
I
O
= I
ref
(3.8)
This is called a current mirror since the reference current is ”mirrored”
or held constant at the output.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 38
3.3 Benchmark Test Circuit
The purpose of the test circuit is to establish a benchmark which could be
used to evaluate the performance and design of each of the diﬀerent types
of biasing circuits. This test circuit was kept the same for all tests and the
transistor sizes were set to the smallest possible optimum values. The test
circuit itself consists of a basic diﬀerential pair (W=1900nm, L=350nm), a
basic two transistor active load (W=800nm, L=350nm) and common source
ampliﬁer (W=800nm, L=350nm).
Figure 3.1: Benchmark Test Circuit Schematic
The widths of the transistors were adjusted so that the current supplied
to the diﬀerential pair was between 6.50µA and 7.00µA. Then the output
impedance was measured, as well as, the overall size of the transistors once
the desired current was achieved. These results were recorded out would
help to choose which current mirror would be the ”Winner”.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 39
3.4 Examined Current Mirrors
3.4.1 Basic Current Mirror
We will now examine the most fundamental and simple type of current
mirror, the Basic Current mirror (See Figure 3.2). This type of current
mirror uses a minimum of (3) three transistors. The derivation shown earlier
shows the general operation of a current mirror whereby current is held
constant regardless of the voltage being supplied.
Figure 3.2: Basic Current Mirror Schematic
This circuit is very simple and does a very good job of supplying constant
current, however, it does not supply absolutely stable current. See ﬁgure 3.3,
the output current supplied to the active load and the output impedance.
Figure 3.3: Basic Current Mirror Simulation Results
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 40
The main advantage of this current mirror is its simplicity and ease
of implementation, however, the major disadvantage is that the current
supplied is not completely stable.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 41
3.4.2 Cascade/Cascode Current Mirror
The second current mirror examined was the Cascade/Cascode Current Mir
ror. This current mirror uses a minimum of (5) ﬁve transistors, these tran
sistors can be seen in the Figure 3.4.
Figure 3.4: Cascade/Cascode Current Mirror Schematic
This circuit is a little bit more complex than the simple current mirror
with (2) two extra transistors and would be more than enough for any design.
The main disadvantage to this current mirror is that it is not very good at
supplying higher amounts of current, in particular to the output stages. It
was given very high consideration when deciding which current mirror to
use for the OpAmp design.
Figure 3.5: Cascade/Cascode Current Mirror Simulation Results
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 42
The main advantage to this design is that it provides stable current
and it has relatively small transistor sizes. In addition to this we have a
higher output resistance compared to the basic current mirror. The main
disadvantage to this type of current mirror is a reduced dynamic range.
Thus, it scored high in our choice for current mirrors when testing.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 43
3.4.3 Wilson Current Mirror
The third current mirror examined was the Wilson current mirror. This
current mirror uses a minimum of (4) four transistors. In the Figure 3.6 you
can see the circuit layout.
Figure 3.6: Wilson Current Mirror Schematic
This circuit is not as complex as the cascade current mirror and does
provide good stable current, however, to provide the benchmark 6.50 →
7.00µA very large transistors (200µm) had to be used, and thus, given that
the current ”best”, cascade current mirror provided similar qualities but
with much smaller transistor sizes this current mirror was ranked very low.
Figure 3.7: Wilson Current Mirror Simulation Results
As stated above this design was not considered for the OpAmp design
and the cascade current mirror was the current best.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 44
3.4.4 Modiﬁed Wilson Current Mirror
The fourth current mirror examined was the Modiﬁed Wilson current mirror.
This current mirror uses a minimum of (5) ﬁve transistors and has a similar
layout as the cascade current mirror. This current mirror was expected to
perform similar to the regular Wilson current mirror. You can see the circuit
schematic in Figure 3.8.
Figure 3.8: Modiﬁed Wilson Current Mirror Schematic
Upon testing the results revealed that the initial idea that it would per
form similarly to the regular Wilson current mirror were conﬁrmed. It had
similar results with the output current as output resistance and the transis
tor sizes needed to attain the benchmark current we also large (200u).
Figure 3.9: Modiﬁed Wilson Current Mirror Simulation Results
Upon seeing these results, the Modiﬁed Wilson current mirror was not
to be chosen as the current mirror for the OpAmp design.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 45
3.4.5 Reduced Cascade Current Mirror
The ﬁfth and ﬁnal current mirror examined was the Reduced Cascade cur
rent mirror. This current mirror used a minimum of (6) six transistors and
had a similar layout to that of the basic cascade current mirror. The word
”Reduced” in the name refers to the reduced voltage at which the current
reaches a stable output, it is usually about (1/2) onehalf of the usual volt
age.
Figure 3.10: Reduced Cascade Current Mirror Schematic
This current mirror is a bit more complex and the transistor sizes are
comparable to the basic cascade current mirror. However, the reduced cas
cade current mirror oﬀers a reduced voltage and is able to provide higher
amounts of current. This is very useful in the output stages were higher
amounts of current are needed to bias the output stages.
Figure 3.11: Reduced Cascade Current Mirror Simulation Results
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 46
The results of this current mirror appeared to be the most promising
for the OpAmp design, it provided stable current, it was able to provide
higher amounts of output current if necessary, as well as, it reduced the volt
age at which the current was stable compared to the other current mirrors
examined.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 47
3.5 Conclusion
The decision to use the Reduced Cascade/Cascode Current Mirror in the de
sign of this OpAmp are now shown here. First, the reduced cascade/cascode
current mirror provided stable and linear current in all test situations. Sec
ondly, it provided very high output resistance and a very low input resis
tance. Third, it was able to supply larger amounts of current which were
needed to drive the output stage. Lastly, given it had a few extra transistors
their sizes were small compared to other current mirror setups looked at. In
the table below you can see the current mirrors ranked from best to worst
(top to bottom) as well as a few of the ranking criterion and their evaluation.
The Basic Cascade/Cascode current mirror would have also done a very
good job in the design, however with the reduced cascade’s reduced voltage
it oﬀered a bit of an advantage over the basic cascade current mirror.
Current Mirrors Min # of FET’s Current Output Input Complexity Transistor Sizes
Ranked: (Best to Worst) including I
ref
Stability Resistance Resistance needed to achieve
Transistors Ref 7.0µA Current
Reduced Cascade/Cascode 6+2N Excellent Very High Very Low Very High Small
Basic Cascade/Cascode 3+2N Very Good Very High Very Low Very High Very Small
Basic Wilson 2+2N Good High Very Low Moderate Very Large
Modiﬁed Wilson 3+2N Good High Very Low Moderate Very Large
Basic 2+N Poor Low Very Low Simple Small
N = Number of times current is mirrored. (In these designs N = 2,
diﬀerential Pair Biasing and Output Stage)
Chapter 4
Diﬀerential Input Stage
4.1 The Unbuﬀered OpAmp
Figure 4.1: Two Stage OpAmp
The ampliﬁer shown in ﬁgure 4.1 can be segregated into:
1. Biasing block.
2. Diﬀerential input stage.
3. Output stage.
48
CHAPTER 4. DIFFERENTIAL INPUT STAGE 49
The biasing block, consists of M8, M9, and M5. The bias current greatly
aﬀects the performance of the ampliﬁer. The diﬀerential input stage is
composed of M1, M2, M3, M4 with: M1 matching M2, M3 matching M4.
The output stage consists of M6 and M7.
4.2 Small Signal Equivalent Circuits
Figure 4.2: NFET and Its Small Signal Model
In the analysis of a FET ampliﬁer circuits, the FET can be replaced by
the equivalent circuit model, 4.2. Where:
r
o
=
V A
I
D
Where V A =
1
λ
g
m
is the transconductance parameter = K
n
W
L
(V
GS
−V
t
)
Therefore, the small signal model parameters:
g
m
and r
o
depends on the DC bias of the FET.
Ideal constant DC voltage sources are replaced by short circuits, this is a
result of the fact that the voltage across an ideal constant DC voltage source
does not change and thus there will always be a zero voltage signal across
a constant DC voltage source. The signal current of an ideal constant DC
current source will always be zero thus an ideal constant DC current source
can be replaced by an open circuit.
For the gate drain connected FET device, the model is as shown in ﬁgure
4.3.
Since v
ds
= v
gs
(the eﬀective resistance =
v
gs
v
gs
·g
m
=
1
g
m
)
Figure 4.4 shows only the diﬀerential input stage of the circuit. In ﬁgure
4.1 M5 are replaced by current source I
ss
. The small signal analysis of the
CHAPTER 4. DIFFERENTIAL INPUT STAGE 50
Figure 4.3: MOSFET Resistor and Its Small Signal Model
diﬀerential input stage can be accomplished with the assistance of the model
shown in ﬁgure 4.5 which is only appropriate for diﬀerential analysis when
both sides of the ampliﬁer are assumed to be perfectly matched. If this
condition is satisﬁed, then the point where the two sources of M1 and M2
are connected can be considered at AC ground. The body eﬀect is neglected.
Figure 4.4: CMOS Diﬀerential Ampliﬁer using nchannel Input Devices
The model in ﬁgure 4.6 is the simpliﬁed to the model shown in ﬁgure
4.5. Since: M1 matches M2, M3 matches M4 (The point where S1, S2 of
M1, M2 are connected can be considered at AC ground.) Since S3, S4 are
CHAPTER 4. DIFFERENTIAL INPUT STAGE 51
Figure 4.5: The Exact Model for the CMOS Diﬀerential Ampliﬁer
AC ground, therefore S1, S2, S3, S4 can be joined up in a node.
Figure 4.6: The Simpliﬁed Equivalent Model
Referring to ﬁgure 4.6:
C
1
= c
gd1
+c
gs3
+c
gs4
C
2
= c
gd2
C
3
= c
gd4
Any small signal on gate of M1 will result in a small signal current i
d1
, which
will ﬂow from drain to source of M1.
i
d1
= g
m1
· v
gs1
CHAPTER 4. DIFFERENTIAL INPUT STAGE 52
and also be mirrored from M3 to M4
g
m4
· v
gs4
= i
d1
Now since S1, S2, S3, S4 have the same potential (one node)
i
d1
will also ﬂow from the source to drain of M2. g
m2
· v
gs2
= −i
d1
i
out
= i
d1
−(−i
d1
) = 2i
d1
(4.1)
r
out
= r
o2
r
o4
(4.2)
i
d1
= g
m1
· v
gs1
Since v
gs1
= v
gs2
v
id
= v
gs1
+v
gs2
Therefore, v
id
= 2v
gs1
i
d1
v
id
=
g
m1
v
gs1
2
vgs
=
g
m
1
2
v
id
=
2i
d1
g
m1
(4.3)
Now the small signal output voltage is simply:
v
out
= i
out
r
out
(Substitute 4.1 and 4.2)
v
out
= 2i
d1
· (r
o2
r
o4
) (4.4)
Now dividing 4.4 over 4.3 :
v
out
v
id
=
2i
d1
(r
o2
r
o4
)
2i
d1
g
m1
v
out
vid
= g
m1,2
(r
o2
r
o4
) (4.5)
Now:
g
m1,2
= (2β
1,2
I
D1,2
)
1
2
(r
o2
r
o4
)
∼
=
1
2λI
D,2
(since r =
1
λI
)
Therefore,
v
out
v
id
∼
= (2β
1,2
I
D1,2
)
1
2
·
_
1
2λI
D1,2
_
CHAPTER 4. DIFFERENTIAL INPUT STAGE 53
v
out
v
id
∼
= K ·
_
W
1,2
L
1,2
I
D1,2
_1
2
·
_
1
λ
_
K is a constant, uncontrollable by the designer. The eﬀect of λ on the
gain diminishes as L increases, such that
1
λ
is directly proportional to the
channel length.
Then a proportionality can be established between
W
1,2
L
1,2
and the drain
current versus the small signal gain such that:
v
out
v
id
∝
_
W
1,2
L
1,2
I
D1,2
_1
2
Therefore,
small signal gain ∝
_
W
1,2
L
1,2
I
D1,2
_1
2
(4.6)
The constant was not included since the value is not dependent on anything
the designer can adjust.
Conclusions:
1. Increasing W
1,2
, L
1,2
or both increases the gain.
2. Decreasing the drain current through M1, M2 which is also
1
2
I
D6
,
increases the gain.
4.3 The Frequency Response
Referring back to the model of the input stage: ﬁgure 4.6. We will work to
eliminate all low impedance nodes (having high RC time):
If,
1
c
1
·
1
g
m3
1
[c
2
· (r
o2
r
o4
)]
Then the node (D1=D2=G3=G4) is a low impedance node (with large RC
time) Now: c
3
is assumed to be zero. In most applications of diﬀerential
ampliﬁers, this assumption turns out to be valid. Then the model to be
considered for the high frequency response analysis is turned to be as shown
in ﬁgure 4.7.
In the conﬁguration where the small signal is applied to the gate of M4
while the gate of M2 is grounded, v
gs2
= 0, v
id
= v
gs1
. Now:
g
m4
v
gs4
= i
d1
= g
m1
v
gs1
= g
m1
v
id
CHAPTER 4. DIFFERENTIAL INPUT STAGE 54
Figure 4.7: High Frequency Small Signal Model with Parasitic Capacitors
Now redrawing the model in Figure 4.7 with the new parameters will
result in the model shown in Figure 4.8.
Figure 4.8: Model of the Input Stage used to Determine the Frequency Response
The high frequency output can be given by:
v
o1
= g
m1
v
id
· (r
o2
r
o4
) ·
1
_
1 +S ·
1
c2(r
o2
r
o4
)
_
The freq. Response =
v
o1
v
i
d
= g
m1
· (r
o2
r
o4
) ·
1
_
1 +S ·
1
c
2
(r
o2
r
o4
_
Now let us consider the input and the output stage shown in ﬁgure 4.9.
The capacitor C
c
in Figure 4.8 is removed for the purpose of the ﬁrst
analysis. C
1
, C
2
represent the total lumped capacitance from each ground.
Since the output nodes associated with each output is a high impedance,
these nodes will be the dominant frequency dependent nodes in the circuit.
Since each node in a circuit contributes a high frequency pole, the frequency
response will be dominated by the high impedance nodes.
Figure 4.10 is the model derived for Figure 4.9 making use of Figure 4.8
to determine the frequency response of the twostage OpAmp.
To determine the exact value for c
1
, c
2
, Figure 4.11 shows the parasitic
capacitors explicitly for the input and the output stage which include the
bulk depletion capacitors (c
gb
, c
sb
, c
db
) and the overlap capacitors (c
gs
, c
gd
).
CHAPTER 4. DIFFERENTIAL INPUT STAGE 55
Figure 4.9: Two Stage OpAmp with Lumped Parasitic Capacitors
Figure 4.10: Model Used to Determine the Frequency Response of the TwoStage
OpAmp
Miller theorem was used to determine the eﬀect of the bridging capacitor
c
gd6
connected from the gate to drain of M6. Miller theorem approximates
the eﬀects of gatedrain capacitor by replacing the bridging capacitor with
an equivalent input capacitor of value c
gd
(1+A2) and the equivalent output
capacitor with a value of c
gd
(1 +
1
A2
). Where:
CHAPTER 4. DIFFERENTIAL INPUT STAGE 56
Figure 4.11: Two Stage OpAmp with Parasitic Capacitors Shown Explicitly
A2: gain across the original bridging capacitor and is, from ﬁgure 4.10:
A2 =
v
o
v
o1
= −g
m6
· v
o1
r
o6
r
o7
v
o1
A2 = −g
m6
(r
o6
r
o7
) (4.7)
Thus c1, c2 for ﬁg(10) can be determined by examining ﬁgure 4.11.
c
1
= c
db4
+c
gd4
+c
db2
+c
gd2
+c
gs6
+c
gd6
· (1 +A2)
c
2
= c
db6
+c
db7
+c
gd7
+c
gd6
·
_
1 +
1
A2
_
+c
L
Now assume c
1
< c
2
(the pole associated with the diﬀamp output
_
1
c
1
(r
o2
r
o4
)
_
will be lower in frequency than the pole associated with the output of the
output stage
_
1
c
2
(r
o6
r
o7
)
_
.
Also from the high frequency model ﬁgure 4.10:
v
o
v
id
=
_
v
o
v
o1
_
·
_
v
o1
v
id
_
·
_
1
1 +
S
c
2
·(r
o6
r
o7
)
_
·
_
1
1 +
S
c
1
·(r
o2
r
o4
)
_
CHAPTER 4. DIFFERENTIAL INPUT STAGE 57
v
o
v
o1
= g
m6
· (r
o6
r
o7
)
1
_
1 +
S
c
2
·(r
o6
r
o7
)
_
v
o1
v
id
= g
m1
· (r
o2
r
o4
) ·
_
1
1 +
S
c
1
·(r
o2
r
o4
)
_
Therefore, the frequency response
v
o
v
id
= [g
m6
· (r
o6
r
o7
)] · [g
m1
· (r
o2
r
o4
)]
·
_
1
1 +
S
c
1
·(r
o2
r
o4
)
_
·
_
1
(1 +
S
c
2
·(r
o6
r
o7
)
_
(4.8)
And the poles are:
P
1
=
1
c
1
· (r
o2
r
o4
)
(4.9)
P
2
=
1
c
2
· (r
o6
r
o7
)
(4.10)
4.4 Phase Margin
The phase margin is the diﬀerence between the phase at the frequency at
which the magnitude plot reaches 0dB and the phase at the frequency at
which the phase has shifted −180
o
. It is recommended for stability reasons
that the phase margin of any ampliﬁer be at least 45
o
(60
o
is recommended).
A phase margin below 45
o
will result in long settling time and increased
propagation delay. The OpAmp system can also be thought of as a simple
second order linear control system with the phase margin directly aﬀecting
the transient response of the system.
Phase margin measurement procedure with the Cadence design tool, the
phase margin can be measured by applying the following steps:
1. Obtain the AC response simulation
2. Delete all the outputs in the Aﬃrma window
3. Select the AC response curve (it will turn to yellow).
4. From the Aﬃrma window: Result →direct plot →AC magnitude and
phase
CHAPTER 4. DIFFERENTIAL INPUT STAGE 58
5. Follow the prompt at the bottom of the schematic window and select
the output node
6. From the Aﬃrma window : output → to be plotted
7. You will get the magnitude and the phase frequency response. Split
the graphs.
Figure 4.12: Miller Phase Margin Measurement
4.5 Compensation
The goal of the compensation task is to achieve a phase margin greater than
45
o
. Now we will include C
c
and the model will be as in Figure 4.13
Keeping in mind that the two poles of the system without compensation
as determined previously are:
P
1
=
1
c
1
· (r
o2
r
o4
)
CHAPTER 4. DIFFERENTIAL INPUT STAGE 59
Figure 4.13: Model Used to Determine the Frequency Response of the TwoStage
OpAmp
P
2
=
1
c
2
· (r
o6
r
o7
)
Two results come from adding the compensation capacitor C
c
:
1. The eﬀective capacitance shunting r
o2
r
o4
is increased by the additive
amount of approximately g
m1
· r
o2
r
o4
· C
c
. This moves P
1
down by
a signiﬁcant amount. C
c
will dominate the value of c
1
and will cause
the pole P
1
to roll oﬀ much earlier than without C
c
to a new location.
2. P
2
is moved to a higher frequency.
Let r
1
= r
o2
r
o4
, r
2
= r
o6
r
o7
,
v
o
v
id
=
g
m1
g
m6
r
1
r
2
_
1 −S
C
c
g
m6
_
1 +S [r
1
(c
1
+C
c
) +r
2
(c
2
+C
c
) +g
m6
r
1
r
2
] +S
2
r
1
r
2
[c
1
c
2
+C
c
(c
1
+c
2
)]
(4.11)
A general second order polynomial can be written as:
P(S) = 1 +aS +bS
2
=
_
1 −
S
P
1
__
1 −
S
P
2
_
= 1 −S
_
1
P
1
+
1
P
2
_
+
S
2
P
1
P
2
If  P
2
 P
1
 then:
P(S) = 1 −
S
P
1
+
S
2
P
1
P
2
CHAPTER 4. DIFFERENTIAL INPUT STAGE 60
Therefore, P
1
, P
2
may be written in terms of a, b as:
P
1
=
−1
a
P
2
=
−a
b
The key in this technique is the assumption that the magnitude of the root
P
2
is greater than the magnitude of the root P
1
P
1
=
−1
r
1
(c
1
+C
c
) +r
2
(c
2
+C
c
) +g
m6
r
1
r
2
C
c
P
1
∼
=
−1
g
m6
r
1
r
2
C
c
P
2
= −
r
1
(c
1
+C
c
) +r
2
(c
2
+C
c
) +g
m6
r
1
r
2
C
c
r1
r
2(c
1
c
2
+C
c
(c
1
+c
2
))
P
2
∼
=
−g
m6
C
c
c
1
c
2
+c
2
C
c
+c
1
C
c
P
2
∼
= −
g
m6
c
2
(4.12)
The second pole should not begin to aﬀect the frequency response until after
the magnitude response is below 0dB.
It is of interest to note that a zero occurs in the righthandplane (RHP)
due to the feed forward path through C
c
. The RHP zero is located at:
Z
1
=
g
m6
C
c
(4.13)
This RHP zero has negative consequences on our phase margin, causing the
phase plot to shift −180
o
more quickly. To avoid the eﬀect of RHP zero, one
must try to move the zero well beyond the point at which the magnitude
plot reaches 0dB (suggested rule of thumb: factor of 10 greater)
4.6 Adding R
z
in series with C
c
One remedy to the ”zero problem” is to add a resistor R
z
in series with C
c
Z
1
=
1
_
C
c
_
1
g
m6
−R
z
__ (4.14)
CHAPTER 4. DIFFERENTIAL INPUT STAGE 61
And the zero can be pushed into the LHP where it adds phase shifts and
increases phase margin if:
R
z
>
1
g
m6
(4.15)
The zero location is in the RHP, when R
z
= 0. As R
z
increases in
value, the zero gets pushed to inﬁnity at the point at which R
z
=
1
g
m6
.
Once R
z
>
1
g
m6
, the zero appears in the LHP where its phase shifts adds to
the overall phase response. Thus improving the phase margin. This type of
compensation is referred to as lead compensation and is commonly used as a
simple method for improving the phase margin. One should be careful about
using R
z
, since the absolute values of the resistors are not well predicted.
The value of the resistor should be simulated over its max and min values to
ensure that no matter if the zero is pushed into the LHP or RHP, that value
of the zero is always 10 times greater than the gain bandwidth product.
4.7 Gain Bandwidth Product
GBW for the compensated OpAmp is the open loop gain multiplied by the
bandwidth of the ampliﬁer (as set by P
2
).
GBW = g
m1
r
1
g
m6
r
2
·
_
1
g
m6
r
1
C
c
r
2
_
GBW
∼
=
g
m1
C
c
(4.16)
GBW ∝
_
I
D1,2
·
W
1,2
L
1,2
_1
2
C
c
Therefore, the most eﬃcient way to increase GBW is to decrease C
c
.
The value of C
c
must be large enough to aﬀect the initial rolloﬀ frequency
as larger C
c
improves phase margin. Therefore, to know the value of C
c
:
1. We need to know the GBW speciﬁcation.
2. Iteratively choosing the values for
W
1,2
L
1,2
and I
D1,2
and then solving for
C
c
.
Conclusions:
P
2
should be > GBW Therefore,
g
m6
c
2
>
g
m1,2
C
c
C
c
> C
2
·
_
g
m1,2
g
m6
_
(4.17)
CHAPTER 4. DIFFERENTIAL INPUT STAGE 62
Practically speaking, the load capacitor usually dominates the value of c
2
,
so c
2
= c
L
C
c
> c
L
·
_
g
m1,2
g
m6
_
(4.18)
Therefore, the eﬀect of c
L
on phase margin is as follows: Minimum size of
Cc directly depend on the size of c
L
. For example if the zero is 10 times
larger than GBW, then in order to achieve a 45
o
phase margin, P
2
must be
least 1.22 times higher than GBW. And to get a phase margin of 60
o
P
2
must be 2.2 times greater than GBW.
4.8 Large Signal Consideration
Analysis and design can be greatly simpliﬁed by separating DC or bias
calculations from small signal calculations. That is once a stable operating
point has been established and all DC quantities are calculated, we may
then perform AC analysis. Figure 4.14 shows the large signal equivalent
circuit model for nchannel MOSFET in saturation. The model for pchannel
CMOS is similar except for K
p
instead of K
n
.
Figure 4.14: LargeSignal Equivalent Circuit Model in Saturation
For Nchannel MOSFET to be in saturation:
1. V
GS
≥ V
t
2. V
DS
≥ (V
GS
−V
t
)
And the drain saturation current is given by:
I
D
=
1
2
· K
n
·
W
L
· (V
GS
−V
t
)
2
CHAPTER 4. DIFFERENTIAL INPUT STAGE 63
If β = K
n
·
W
L
Then,
I
D
=
1
2
· β (V
GS
−V
t
)
2
(4.19)
For Pchannel MOSFET to be in saturation:
1. V
GS
≤ V
t
2. V
DS
≤ (V
GS
−V
t
)
Equation 4.19 can be written as:
V
GS
=
_
2I
D
β
_1
2
+V
t
(4.20)
For the Nchannel:
1. V
DS
≥ (V
GS
−V
t
). Now by substituting V
GS
:
2. V
DS
≥
_
2I
D
β
_1
2
The large signal characteristics that are important include the Common
mode range, slew rate, and output signal swing
4.9 Slew Rate
The slew rate is deﬁned as the maximum rate of change of the output volt
age due to change in the input voltage. For this particular ampliﬁer, the
maximum output voltage is ultimately limited by how fast the tail current
device M5 can charge and discharge the compensation capacitor, the slew
rate can then be approximated as:
SR =
dV
o
dt
SR ≈
I
D5
C
c
Typically, the diﬀamp is the major limitation when considering slew
rate. However, the tradeoﬀ issues again come into play. If I
D5
is increased
too much, the gain of the diﬀamp may decrease below a satisfactory amount.
If Cc is made too small then the phase margin may decrease below an
acceptable amount.
CHAPTER 4. DIFFERENTIAL INPUT STAGE 64
4.10 The CommonMode Range
Commonmode range is deﬁned as the range between the maximum and
minimum commonmode voltages for which the ampliﬁer behaves linearly.
Referring to 4.15, suppose that the common mode voltage is DC value and
that the diﬀerential signal is also shown. If the common mode voltage is
swept from ground to V
DD
, there will be a range for which the ampliﬁer
will behave normally and where the gain of the ampliﬁer is relatively con
stant. Above or below that range, the gain drops considerably because the
commonmode voltage forces one or more devices into the triode region.
The maximum commonmode voltage is limited by both M1 and M2
going into triode. This point can be deﬁned by a borderline equation in
which
(For M1, M2 to stay in saturation)
V
D1,2
≥ (V
G1,2
−V
t1
)
Now:
V
D1
= V
DD
−V
SG3
Therefore,
V
G1
≤ V
DD
−V
G3
+V
t1
Substitute the value of V
GS
from equation 4.20 and V
t3
= −ve value because
it is p type CMOS:
V
G1
≤ V
DD
−
_
2I
D3
β
3
_1
2
−V
t3
+V
t1
Now since I
D3
=
1
2
I
D5
:
V
G1
≤ V
DD
−
_
I
D5
β
3
_1
2
−V
t3
+V
t1
(4.21)
V
G1
≤ V
DD
−
_
L
3
I
D5
W
3
K
3
_1
2
−V
t3
+V
t1
(4.22)
The minimum voltage is limited by M5 being driven into nonsaturation
by the commonmode voltage source.
V
D5
≥ V
SS
+V
G5
−V
t5
V
D5
= V
G1,2
−V
GS1,2
CHAPTER 4. DIFFERENTIAL INPUT STAGE 65
Therefore,
V
G1,2
−V
GS1,2
≥ V
SS
+V
G5
−V
t5
V
G1,2
≥ V
SS
+V
G5
−V
t5
+V
GS1,2
Since, V
GS
=
_
2I
D
β
_1
2
+V
t
(From 4.20)
Therefore,
V
G1,2
≥ V
SS
+
_
2I
D5
β
5
_1
2
+
_
I
D5
β
1
_1
2
+V
t5
−V t5 +V
t1
V
G1,2
≥ V
SS
+
_
2I
D5
β
5
_1
2
+
_
I
D5
β
1
_1
2
+V
t1
V
G1,2
≥ V
SS
+
_
2L
5
I
D5
W
5
K
5
_1
2
+
_
L
1
I
D5
W
1
K
1
_1
2
+V
t1
(4.23)
Determining the CMR for the twostage OpAmp (Figure 4.15).
Figure 4.15: Determining the CMR for the TwoStage OpAmp
CHAPTER 4. DIFFERENTIAL INPUT STAGE 66
4.11 Important Relationships for The Design
Relate W
3
, W
4
to W
5
M3, M4 carry half of I
tail
, then the widths of M3 and
M4 can be determined by assuming that v
sg3
= V
sg4
= V
gs5
. Using 16:
I
d3,4
I
d5
=
0.5K
P
_
W
L
_
3,4
_
V
gs3,4
−V
2
t
_
0.5K
n
_
W
L
_
5
(V
gs5
−V
t
)
≈
K
P
_
W
L
_
3,4
K
n
_
W
L
_
5
And since L3 = L5 and Kn = 3Kp, then that leads to the conclusion
that:
W
3,4
= 1.5W
5
(4.24)
Therefore, the width of M3, M4 can be determined in terms of W
5
.
Relate W
6
, W
7
to W
5
. The values for M6 and M7 are determined by the
amount of load capacitance attached to the output. If a large capacitance is
present, the width of M6 and M7 will need to be large so as to provide enough
sinking and sourcing current to and from the load capacitor. Suppose it was
decided that the current needed for M6 and M7 was twice that of M5. Then:
W
7
= 2W
5
(4.25)
W
6
= 6W
5
(Because W
6
is PType so to account for the diﬀerence K values)
4.12 Tradeoﬀs for Increasing the Gain of the Two
Stage OpAmp.
Using the equations in the summary above, the tradeoﬀ issues for increasing
the gain of the two stage OpAmp are summarized in the following table.
We wish to... Thus we could... Some Secondary eﬀects are...
Increase DC gain Increase
W
L
1,2
Decrease phase margin
Increase GBW
Increase CMR
Decrease ID5 Decrease SR
Increase CMR
Increase CMRR
Increase phase margin
Increase
W
L
6
Increase phase margin
Increase output swing
Decrease I
D6
Decrease output currents drive
Decrease phase margin
CHAPTER 4. DIFFERENTIAL INPUT STAGE 67
4.13 Design Methodology for the Two Stage Op
Amp
Design methodology is a topology dependent subject and it is highly depen
dent on the analysis of the circuit. The purpose on the design tool is not
to replace the analysis completely. The analysis rather guides the designer’s
thoughts and while doing the design and helps to make the results of the
design tool make sense.
The following design methodology is developed for the two stage OpAmp
analyzed above.
1. To deﬁne the requirements, set the speciﬁcations, and deﬁne the bound
ary conditions. Boundary conditions The TSMC 0.35 CMOS Technol
ogy is used. Process speciﬁcations: V
t
, K
, C
ox
, ..etc. Because there
are 12 models for NFET and 12 models for PFET automatically
selected within Cadence tool so the process parameters cannot be de
termined at this stage.
Supply voltage: 0 → 3.3 V Operating temperature: 0 to 70
o
C,
Requirements, Gain, GBW, CMRR Slew rate, Input common mode
range: V
in
(min), V
in
(max), Output voltage swing: V
out
(max), V
out
(min),
PSRR, Oﬀset, Output Load.
2. Choose the smallest length that will keep the channel modulation pa
rameter ( constant and give good matching for current mirrors. The
value used is 350nm
3. Design the two stages without C
c
, R
z
, or C
L
, for the best dc response.
Design the devices sizes for proper dc performance. It is important
that before any AC analysis is performed, the values of the DC points
in the circuit be checked to ensure that every device is in saturation.
Failure to do so will result in very wrong answers. This step is accom
plished as follows:
(a) Calculate the minimum value for the compensation capacitor C
c
.
From 40: C
c
0.22 C
L
. Get C
L
from the requirements
(b) Get the slew rate from the requirement and then calculate the
minimum value for the tail current I
D5
from: ID5 = SR. C
c
CHAPTER 4. DIFFERENTIAL INPUT STAGE 68
(c) Using cadence design tool, simulate the two stage ampliﬁer with
starting widths of: 800nm for n type devices, 1.9µm for p type
devices. Get the circuit to work and test the DC response.
(d) Measure I
D5
. Now try to optimize the OpAmp for maximum
gain by:
i. Measure the existing I
D5
. To get the desired value of I
D5
calculated in B, simultaneously change W5 and the width of
the related devices:
W
3,4
= 1.5W
5
W
6
= 6W
5
W
7
= 2W
5
ii. Check the operating points of all the devices (M1, M2, M3,
M4, M5, M6, and M7) to make sure that the devices are in
saturation. All design parameters can be known from Ca
dence by doing the following:
Aﬃrma Window: Results → Print → DC Operating Points
iii. Increase the gain by increasing the size of W
1,2
. You may
perform parametric analysis for diﬀerent width size. You
can not decide on the ﬁnal value of W1,2 at this point even
you may get high gain, because of the trade oﬀ issues and
the secondary eﬀect, particularly on the phase margin which
can not be measured till the ac analysis is performed.
iv. At this point you can extract the process parameters: V
t
, K, C
ox
...etc. Knowing K for the devices is now important to calcu
late V
G
(min) and V
G1
(max) to make sure that M1, M2, M3,
M4 and M5 are not operating near the boundary, 4.22,4.23
causing one of the devices to operate outside the saturation
region.
v. If any of the devices are brought out of saturation or are
working at the minimum condition required for saturation,
then it should be brought back to saturation.
vi. Repeat 14 until all the transistors are in saturation while
the dc gain is increased.
CHAPTER 4. DIFFERENTIAL INPUT STAGE 69
(e) Measure the CMR and the gain. Compare with the required
speciﬁcations.
4. (a) Add up C
c
and C
L
to the ampliﬁer. The value of C
L
is from
the speciﬁcations while the value of C
c
is previously calculated in
Step3A
(b) Check the phase margin condition (4.18), as now you can know
all the process parameter from cadence.
(c) Verify that the phase margin is > 45
o
by measuring it using the
procedure in 44.
(d) If the phase margin is not > 45
o
then it should be corrected
by changing the value of C
c
or R
2
, referring to (4.15, 4.18). A
parametric analysis may be preformed for diﬀerent C
c
sizes.
(e) Calculate the slew rate according to the new Cc value that makes
the phase margin > 45
o
. If it is less than the speciﬁcation then
perform the following steps:
i. Calculate the required I
D5
from (22). Substitute the last
value of C
c
and the required SR.
ii. Perform DC analysis only and return back to Step3D, with
the desired value of I
D5
as calculated above.
5. (a) Calculate the required R
z
using (4.14)
(b) Add R
z
to the circuit and perform an AC analysis. Check the
diﬀerence in the phase response.
6. Measure the slew rate, GBW, P2 and the phase margin. Compare
with the speciﬁcations.
4.14 Design Example
Figure 4.16 shows a two stage opamp designed using the above design
methodology and optimized for maximum gain. Figure 4.17 shows the gain
for the large signal consideration(DC response). Figure 4.18 shows the fre
quency response. Figure 4.19 shows the phase margin measurements.
CHAPTER 4. DIFFERENTIAL INPUT STAGE 70
Figure 4.16: TwoStage OpAmp using design Methodology
Figure 4.17: Gain for the Large Signal Analysis
CHAPTER 4. DIFFERENTIAL INPUT STAGE 71
Figure 4.18: Frequency Response
Figure 4.19: Phase Margin
CHAPTER 4. DIFFERENTIAL INPUT STAGE 72
4.15 Limitations of the Two Stage OpAmp
1. Insuﬃcient gain
2. Limited stable bandwidth caused by the instability to control the
higher order poles of the opamp.
3. Poor power supply rejection ratio.
4.16 The Cascode OpAmp
The motivation for using the cascode conﬁguration to increase the gain can
be seen by examining how the gain of the twostage opamp could be in
creased. There are three ways in which the gain of the two stage opamp
could be increased:
1. Add additional gain stage
2. Increase the transconductance of the ﬁrst or the second stage.
3. Increase the output resistance seen by the ﬁrst or second stage.
Due to possible instability, the ﬁrst approach is not attractive. Of the
latter two approaches, the third is the more attractive way because the out
put resistance increases in proportion to a decrease current [ r
o
= 1/λ ],
whereas the transconductance increases as the square root of the increase in
bias current [ g
m
= (2 ∗ B ∗ I
D
)
1
/2]. Thus it is generally more eﬃcient to
increase ro rather than g
m
.
Figure 4.20 shows a cascode diﬀerential stage. Figure 4.21 shows the
DC response for an unoptimized conﬁguration to serve as indication for
the whole project and to help in deciding about the best input stage to be
considered in the ﬁnal opamp design. The transistors Mc1 and Mc2 perform
the resistance multiplication, while Mc3 is used to keep the drain voltage of
the input transistor matched, which helps to reduce the voltage oﬀset.
Rout ( [gmc2 . roc2 . ro4 ] —— [ gmc1. roc1. ro2 ]. A = gm1.R
out
One of the disadvantages of this design is the requirement for the addi
tional bias voltages V
B1
, V
B2
. Further more, the common mode input range
is reduced due to the extra voltage drop required by the two cascode devices,
Mc1, Mc2. In many cases, the CMR limitation is not important since the
noninverting input of the opamp will be connected to ground.
CHAPTER 4. DIFFERENTIAL INPUT STAGE 73
Figure 4.20: Cascode Diﬀerential Stage
Folded Cascode OpAmp Figure 4.22 shows a folded cascode diﬀerential
stage. Figure 4.23 shows the DC response for an unoptimized conﬁguration
to serve as indication for the whole project and to help in deciding about
the best input stage to be considered in the ﬁnal opamp design.
This circuit uses a currentfolding circuit technique to permit direct con
nection of the drains of the pchannel diﬀerential ampliﬁer to the sources of
the cascode devices. This requires two additional transistors (M5 and M6),
operate in much the same manner as the previous cascode circuit. Here
however, the input commonmode range is larger because only three tran
sistors are now stacked in the input chain between the two power supplies
(as compared to ﬁve in the conventional cascode circuit). The folded cas
code circuit is frequently used as a singlestage opamp. Its voltage gain can
be determined as: A = gm1 R
o
Where Ro is the output resistance: R
o
= [
gmc1. roc1(ro6——ro2)] —— [ gmc2. roc2. ro3)]
CHAPTER 4. DIFFERENTIAL INPUT STAGE 74
Figure 4.21: DC Response for Unoptimized Circuit
Figure 4.22: Folded Cascode Diﬀerential Stage
CHAPTER 4. DIFFERENTIAL INPUT STAGE 75
Figure 4.23: DC Response for Unoptimized Circuit
Chapter 5
Inverting Ampliﬁers
In this section, we introduce an important conﬁguration that is extensively
employed in the design of integrated circuits: the inverting ampliﬁer. The
inverting ampliﬁer is also called commonsource ampliﬁer or inverter. It is
usually used as the basic gain stage for CMOS circuits. Later we will see
that inverter is used in the gain stage of the ﬁnal circuit.
Typically, the inverter has three kinds of conﬁgurations. The ﬁrst one
uses the commonsource conﬁguration with an active resistor as a load. The
second one uses a current sources/sink as an active load. The third one uses
the input voltage to control both the amplifying transistor and the load
transistor, this conﬁguration is also known as pushpull ampliﬁer. In this
section, the three conﬁgurations will be discussed respectively in terms of
their output swing, smallsignal voltage gain, input and output resistance
and 3 dB frequency.
76
CHAPTER 5. INVERTING AMPLIFIERS 77
5.1 Inverter with Active Resistor Load
The typical circuit of the ﬁrst type has been shown in Figure 5.1. This
circuit uses a commonsource, Nchannel transistor M1 with a Pchannel
transistor M2 as the load of M1.
Figure 5.1: Simple Inverter Circuit
The parameters of the circuit are as follows: V
DD
= 3.3V, V
SS
= 0V ;
W
1
= 10.8µm, L
1
= 10µm, V
TN
= 0.5V ; W
2
= 28µm, L
2
= 10µm, V
TP
=
−0.7V . We set the operating point at 1.65V and DC current at 106.7µA,
so V
gs1
= 1.65V , I
d1
= 106.7µA, I
d2
= −106.7µA Under these conditions,
V
ds1
= 1.365V V
ds2
= V
gs2
= −1.935V . Thus we can calculate β
1
and β
2
which we will need for future calculations. Since
I
d1
=
µ
N
C
ox
W
1
2L
1
(V
gs1
−V
TN
)
2
106.7 · 10
−6
=
µ
N
C
ox
W
1
2L
1
(1.65 −0.5)
2
So β
1
=
µ
N
C
ox
W
1
2L
1
= 171.6µA/V
2
, K
p
= µ
p
C
ox
= 52.9µA/V
2
Use the same way, we have:
β
2
=
µ
P
C
ox
W
2
L
2
= 148.2µA/V
2
, K
p
= µ
P
C
ox
= 52.9µA/V
2
CHAPTER 5. INVERTING AMPLIFIERS 78
1. Transfer Characteristics
Figure 5.2 illustrates the Cadence simulation result of the largesignal
characteristics of this circuit. This plot shows the I
d
versus V
ds
char
acteristics of M1 and the ”load line” plotted on the same graph. The
voltagetransfer curve is shown in Figure 5.3.
Figure 5.2: Inverter Type 1: Parametric Analysis sweeping V
in
Figure 5.3: VoltageTransfer Curve
From these ﬁgures, we can observe that this type of inverting ampliﬁer
has low gain since the slope of the V
out
versus V
in
is small.
CHAPTER 5. INVERTING AMPLIFIERS 79
2. Output Swing
From these curves, it is obvious that this inverter has limited output
voltage range (point A and point B in Figure 5.2). We will ﬁnd the
maximum output voltage and minimum output voltage.
With the gate and drain connected together, M2 always works in the
saturated region as long as  V
ds2
> V
TP
, and V
ds2
= V
gs2
= V
TP

+
_
2I
d2
β
2
. When V
in
is zero, M1 is cutoﬀ, and the drain current of M1
I
d1
is also zero, V
ds2
= V
TP
. So V
out
(max) is approximately equal
to:
V
out
(max) = V
DD
−  V
TP
= 3.3 −0.7 = 2.6(V )
When V
in
increases until V
in
> V
TN
, M1 conducts, and V
out
begins to
drop. When V
out
> V
in
−V
TN
, M1 enters saturated region. When V
out
further drops until V
out
< V
in
−V
TN
, M1 enters nonsaturated region.
This is the region where the minimum output voltage happens. Since
M1 is in nonsaturated region, the drain current of M1 should be:
I
d1
= β
1
_
(V
DD
−V
SS
−V
TN
)(V
out
−V
SS
) −
(V
out
−V
SS
)
2
2
_
Because M2 is in saturated region, the drain current of M2 should be:
I
d2
=
β
2
2
(V
DD
−V
out
−  V
TP
)
2
Equating the above two equations, and simplifying V
TN
= V
TP
= V
T
in order to simplify the calculation. We can get the approximate value
of V
out
(min).
V
out
(min) ≈ V
DD
−V
T
−
V
DD
−V
SS
−V
T
_
1 +
β
2
β
1
= 3.3 −0.5 −
3.3 −0.5
_
1 +
148.2
171.6
= 0.7 V
You may notice that in Figure 5.3, the V
out
(max) is around 3V, dif
ferent from our calculation. This is because the subthreshold eﬀect of
transistors. We usually suppose that no current ﬂows in transistors
when V
in
< V
TN
. But in reality, there is current conducting through
transistors when V
in
< V
TN
, and I
d
has an exponential relationship
with V
ds
at this region. This is called subthreshold eﬀect. It is this
CHAPTER 5. INVERTING AMPLIFIERS 80
eﬀect that results in the diﬀerence between our calculation and the
simulation result.
3. SmallSignal Voltage Gain.
There are two methods to calculate the smallsignal voltage gain.
(a) The principle of the ﬁrst method is this: the gain is found when
M1 works in saturated region, and the drain current of M1 and
M2 are always equal. Therefore, I
d1
is:
I
d1
=
β
1
2
(V
in
−V
SS
−V
TN
)
2
and since M2 always operates in saturation, I
d2
is:
I
d2
=
β
2
2
(V
DD
−V
out
−V
TP
)
2
Equating the above equations. Because A
V
is the derivative of
V
out
V
in
, we have
A
V
=
∂V
out
∂V
in
= −
_
β
1
β
2
_1
2
= −
_
K
N
W
1
L
1
K
P
W
2
W
1
_1
2
(b) Another method to ﬁnd A
V
is from the smallsignal model. The
smallsignal model of the inverter with an activeresistor load is
shown in Figure 5.4.
Figure 5.4: Inverter: SmallSignal Model
The gain can be expressed as:
A
V
=
v
out
v
in
=
−g
m1
g
ds1
+g
m2
+g
ds2
∼
= −
_
K
N
W
1
L
1
K
P
W
2
L
2
_1
2
CHAPTER 5. INVERTING AMPLIFIERS 81
where g
m2
g
ds1
, g
ds2
.
We get the same results from the two methods. According to the
Cadence simulation result, g
m1
= 172µ, g
m2
= 155.5µ, so A
V
=
−1.1, which is a fairly low gain. So this type of inverter is suitable
for situations where lowgain inverting stage is desired. Besides,
we can see from the A
V
expression that in order to improve the
gain, we can either increase the ratio of
W
1
L
1
or decrease the ratio
of
W
2
L
2
.
4. Input and Output Resistance
From the smallsignal model, we can ﬁnd that the input and output
resistance is
r
in
= ∞
r
out
=
1
g
ds1
+g
m2
+g
ds2
∼
=
1
g
m2
=
1
155.5 · 10
−6
= 6.4 kΩ
We can see that the output resistance of the activeresistor load in
verter is low because of the diodeconnected transistor M2. The re
sulting low output resistance can be very useful in situations where a
large bandwidth is the main expectation from an inverting gain stage.
5. Upper 3 dB Frequency
When discussing the frequency response of the inverter, we need to
take the internal capacitors into consideration. Figure 5.5 illustrates
the resulting smallsignal model.
C
1
= C
gs1
C
2
= C
bd1
+C
gs2
+C
bd2
C
3
= C
gd1
r
2
= r
out
=
1
g
out
r
1
= r
in
= ∞
Using nodal analysis, we may write:
V
out
(s)(g
out
+sC
2
) +C
3
[V
out
(s) −V
in
(s)] +g
m
V
in
(s) = 0,
where s = jω
CHAPTER 5. INVERTING AMPLIFIERS 82
Figure 5.5: Inverter: SmallSignal Model
So the transfer function
V
out
(s)
V
in
(s)
is:
A
V
(s) = −
g
m
_
1 −s
_
C
3
g
m
__
g
out
_
1 +s
_
(C
2
+C
3
)
g
out
__ = A
V M
1 −
s
Z
1
1 +
s
P
1
(5.1)
where A
V M
is the midband gain, Z
1
is the zero and P
1
is the pole and
A
V M
= −
g
m1
g
out
=
−g
gm1
g
ds1
+g
m2
+g
ds2
, Z
1
=
g
m1
C
2
, P
1
=
−g
out
C
2
+C
3
From this formula, we ﬁnd that inverter has a ﬁrstorder transfer func
tion. So the 3 dB frequency can be written as:
ω
H
=
g
out
C
2
+C
3
=
g
m2
+g
ds1
+g
ds2
C
db1
+C
gd1
+C
gs2
+C
db2
(5.2)
From this equation, we can get to the conclusion that the 3 dB fre
quency of the active resistor load inverter is approximately propor
tional to the square root of the drain current. So in order to increase
the bandwidth, we can increase the drain current because r
out
will
decrease. Unfortunately, this will also decrease the gain.
Lacking of accurate values of these capacitors, we cannot calculate an
accurate value of the 3 dB frequency. But it still can be found from
the frequency response because 3 dB frequency is the point where the
gain drops to 0.707A
V
. Simulation results of the frequency response
of the activeresistor load inverter is shown in Figure 5.6. From this
curve, we determine the 3 dB frequency to be 26.12MHz, which is a
fairly wide bandwidth.
CHAPTER 5. INVERTING AMPLIFIERS 83
Figure 5.6: Frequency Response of the ActiveResistor Load Inverter
5.2 Inverter with Current Source/Sink Load
The second type of inverter uses active load. There are a number of ways to
conﬁgure active load, such as cascade current sink, current mirror, reduced
cascade current sink and so on. Here we will use current mirror. The circuit
is shown in Figure 5.7.
In order to compare the performances of this type with the ﬁrst one,
set the operating point the same as the ﬁrst one, i.e. V
gs1
= 1.65V , I
d1
=
106.7µA, V
gs2
= −1.935V , I
d2
= −106.7µA, I
d3
= I
d4
= 106.7µA.
From
I
d
=
µC
ox
W
2L
(V
gs
−V
T
)
2
, K
N
= 158.9µA/V
2
, K
P
= 52.0µA/V
2
We can calculate out:
W
1
= 10.8µm; L
1
= 10µm; W
2
= 28µm; L
2
= 10µm;
W
3
= 28µm; L
3
= 10µm; W
4
= 18.5µm; L
4
= 10µm
CHAPTER 5. INVERTING AMPLIFIERS 84
Figure 5.7: Inverter Circuit with Current Source/Sink Load
1. Output Swing.
The largesignal characteristics and voltagetransfer curve are respec
tively shown in Figure 5.8 and Figure 5.9.
Figure 5.8: Inverter Type 2: Parametric Analysis sweeping V
in
CHAPTER 5. INVERTING AMPLIFIERS 85
Figure 5.9: VoltageTransfer Curve
Observing these curves, we can ﬁnd that this type of inverter still
experiences the limitation for output swing(point A in Figure 5.8).
This limitation can be found by a method similar to that used for the
active resistor inverter.
Basically, we can divide the transfer curve into four distinct segments.
In segment 1, V
in
< V
TN
, M1 is cutoﬀ. M2 is conducted, but there is
no current. So V
out
(max) is equal to V
DD
since M2 can pull output
voltage up to V
DD
. In segment 2, V
in
increases to V
in
> V
TN
, M1
begins to conduct, and V
out
decreases as V
in
increase. M2 works in
nonsaturation region. In segment 3, V
in
further increases, making
both M1 and M2 operates in saturation. V
out
dropped quickly. The
transfer curve is almost linear and very steep, indicating large voltage
gain. In segment 4, V
in
increases to V
in
> V
out
+V
TN
, and M1 enters
nonsaturation region. This is the segment where V
out
(min) happens.
From the above analysis, we can see that V
out
(max) = V
DD
= 3.3 V ,
and the lower limit can be found when M1 is in the nonsaturation
CHAPTER 5. INVERTING AMPLIFIERS 86
region. V
out
(min) can be written as
V
out
= (V
DD
−V
TN
)
_
_
_
1 −
_
1 −
_
β
2
β
1
__
V
DD
−(V
DD
−V
gs2
) −  V
TP

V
DD
−V
TN
_
2
_1
2
_
_
_
= (3.3 −0.5)
_
_
_
1 −
_
1 −
_
148.2
171.7
__
3.3 −1.365 −0.7
3.3 −0.5
_
2
_1
2
_
_
_
= 0.3 V
(5.3)
2. SmallSignal Voltage Gain.
The smallsignal voltage gain can be found from its smallsignal model
Figure 5.10.
Figure 5.10: Inverter Type 2: Small Signal Model V
in
The gain can be expressed as
A
V
=
v
out
v
in
= −g
m1
(r
ds1
r
ds2
) =
−g
m1
g
ds1
+g
ds2
Because g
ds1
= λ
1
I
d
,g
ds2
= λ
2
I
d
and g
m1
=
√
2β
1
I
d
A
V
= −
_
2µ
N
C
os
W
1
L
1
I
d
_
1
λ
1
+λ
2
_
Here we notice a signiﬁcant result. The gain increases as the DC
operating current decreases. This occurs because the output conduc
tance r
ds1
and r
ds2
is inversely proportional to the current whereas the
transconductance g
m1
is proportional to square root of the bias cur
rent. So we can increase the gain of this type of inverter by decreasing
CHAPTER 5. INVERTING AMPLIFIERS 87
the biasing current I
d
. According to the Cadence simulation result,
g
m1
= 172.3µ, g
ds1
= 392.3n, g
ds1
= 855.9n, so
A
V
= −
g
m1
g
ds1
+g
ds2
= −
172.3 · 10
−6
392.3 · 10
−9
+ 855.9 · 10
−9
= −137.6
3. Output Resistance.
From the smallsignal model, we can ﬁnd that the output resistance is
r
out
=
1
g
ds1
+g
ds2
=
1
392.3 · 10
−9
+ 855.9 · 10
−9
= 0.8MΩ
From these calculation results, we can see that under the same biasing
conditions, this current source load inverter has a much higher gain and
output resistance when comparing to the active resistor load inverter.
But you will see soon that the high output resistance results in a
narrow bandwidth.
4. 3 dB Frequency. The frequency response can be found by using Figure
5.5. But in this case, C is
C
1
= C
gs1
+C
gs2
C
2
= C
db1
+C
db2
C
3
= C
gd1
+C
gd2
So 3 dB frequency is
ω
H
=
g
out
C
2
+C
3
=
g
ds1
+g
ds2
C
db1
+C
gd1
+C
gd2
+C
bd2
(5.4)
Simulation result of the frequency response of this inverter is shown
in Figure 5.11. From this curve, we measure the 3 dB frequency is
3.75MHz, which is a lower frequency compared to the active resistor
load inverter. This is due to the higher output resistance.
5.3 PushPull Inverter
One of the disadvantages of the current source inverter introduced above is
that it requires a biasing voltage. If the gate of M2 in Figure 5.7 is taken
to the gate of M1, the pushpull CMOS inverter is achieved. In this circuit,
CHAPTER 5. INVERTING AMPLIFIERS 88
Figure 5.11: Frequency Response of the Inverter with Current Source/Sink Load
Figure 5.12: PushPull Inverter Circuit
both biasing and amplifying transistors are driven by the input signal. The
typical circuit is shown in Figure 5.12.
Still, like the above two circuits, set the operating point at 1.65V, i.e.
V
gs1
= 1.65V , I
d1
= 106.7µA, V
gs2
= −1.65V , I
d2
= −106.7µA From
I
d
=
µC
ox
W
2L
(V
gs
−V
T
)
2
, K
N
= 158.9µA/V
2
, K
P
= 52.9µA/V
2
CHAPTER 5. INVERTING AMPLIFIERS 89
We can get,
W
1
= 10.8µm, L
1
= 10µm, W
2
= 48.1µm, L
2
= 10µm;
1. Output Swing.
The largesignal characteristics and voltagetransfer curve are respec
tively illustrated in Figure 5.13 and Figure 5.14.
Figure 5.13: Inverter Type 3: Parametric Analysis Sweeping V
in
Figure 5.14: VoltageTransfer Curve
CHAPTER 5. INVERTING AMPLIFIERS 90
Comparing the largesignal voltage transfer characteristics between
the currentmirror and pushpull inverter, it is seen that this type
of inverter shows two advantages. First, the pushpull inverter will
have a higher gain. This is due to the fact that both transistors are
being driven by V
in
. Second, the output swing of pushpull inverter
is capable of operating from V
DD
to V
SS
, whereas a current mirror
inverter cannot drive all the way to V
SS
.
2. SmallSignal Voltage Gain.
The smallsignal voltage gain can be found from its smallsignal model
Figure 5.15.
Figure 5.15: Inverter Type 3: Small Signal Model
The smallsignal voltage gain can be expressed as
A
V
=
v
out
v
in
= −
g
m1
+g
m2
g
ds1
+g
ds2
Because g
ds1
= λ
1
I
d
, g
ds2
= λ
2
I
d
, g
m1
=
√
2β
1
I
d
and g
m2
=
√
2β
2
I
d
:
A
V
=
v
out
v
in
= −
g
m1
+g
m2
g
ds1
+g
ds2
= −
(2β
1
)
1
2
+ (2β
2
)
1
2
(λ
N
+λ
P
)
√
I
d
(5.5)
From this equation, we can get to the conclusion that the smallsignal
voltage gain of pullpull inverter is inversely proportional to the square
root of DC current. In order to increase gain, we can decrease the DC
operating current. This is the same as the current mirror inverter.
According to the Cadence simulation result, g
m1
= 172.1µ, g
ds1
=
547.7n, g
m2
= 208.2µ, g
ds1
= 761.4n, so
A
V
=
v
out
v
in
= −
g
m1
+g
m2
g
ds1
+g
ds2
= −
172.1 · 10
−6
+ 208.2 · 10
−9
547.7 · 10
−9
+ 761.4 · 10
−9
= −290.5
CHAPTER 5. INVERTING AMPLIFIERS 91
This result shows that under the same DC current, pushpull inverter
has a much higher gain than the other two types.
3. Output Resistance and 3 dB Frequency ω
H
.
From the smallsignal model, we can ﬁnd that the output resistance
and 3 dB frequency are the same as the current mirror inverter, which
are
r
out
=
1
g
ds1
+g
ds2
and
ω
H
=
g
out
C
2
+C
3
=
g
ds1
+g
ds2
C
bd1
+C
gd1
+C
gd2
+C
bd2
In this case,
r
out
=
1
547.7 · 10
−9
+ 761.4 · 10
−9
= 0.76 MΩ
Simulation result of the frequency response of the pushpull inverter
is shown in Figure 5.16, and the 3 dB frequency is 2.98MHz.
Figure 5.16: Frequency Response of the PushPull Inverter
CHAPTER 5. INVERTING AMPLIFIERS 92
5.4 Comparison
We have ﬁnished the analysis of the three types of inverters: active load
inverter, current source inverter and pushpull inverter. Main performances
of the three inverters are concluded in the following table.
Type 1 Type 2 Type 3
Active Resistor Load Current Source Load PushPull
Operating Point V
gs1
= 1.65, I
d1
= 1.06.7µA
Output V
out
(max) = 2.6V V
out
(max) = 3.3V V
out
(max) = 3.3V
Swing V
out
(min) = 0.8V V
out
(min) = 0.3V V
out
(min) = 0V
Gain 1.1 137.6 290.5
Output Resistance 64kΩ 0.8MΩ 0.76MΩ
3dB Frequency 26.12MHz 3.75MHz 2.98MHz
The comparison shows that under the same DC current, the active resistor
load inverter has the lowest gain but the best bandwidth. So this type of
inverter is suitable for situations where low gain and wide bandwidth is
desired. Pushpull inverter has the highest gain and output swing. But we
all know that this type of inverter may cause crossover distortion. The
performance of the current source load inverter is between the other two
types, which is a modest gain and output swing.
5.5 Application
In the ﬁnal circuit, the second type of inverter is used to make a crossover
stage. The purpose of this stage is to provide gain and drive to the two out
put transistors. Figure 5.17 illustrates the basic conﬁguration of a crossover
stage.
CHAPTER 5. INVERTING AMPLIFIERS 93
Figure 5.17: Application 1
In this diagram, the two inverters consisting of M1, M3 and M2, M4
are the crossover stage. You can see that these two inverters are the cur
rent mirror load inverter introduced above. Figure 5.18 shows the practical
circuit in the our group’s design.
Figure 5.18: Application 2
In this circuit, the crossover stage is achieved with transistors M9, M22,
M23 and M10, M24, M25. Here the current mirror is replaced by reduced
cascade current source to bias the inverting ampliﬁer, and it comes from
CHAPTER 5. INVERTING AMPLIFIERS 94
our biasing subcircuit. The input of the inverters is from the ﬁrst stage, i.e.
diﬀerential stage. The output of the ﬁrst inverter consisting of M9, M22,
M23 will drive transistor M11 of the output stage, and the second inverter
consisting of M10, M24, M25 will drive M12 of the output stage.
The performance of the two inverters is similar to that of the current
mirror load inverter introduced above. This is the speciﬁc application of
the current source load inverter. This stage can provide high gain for the
circuit. It’s high input and output resistance make it match well with both
the diﬀerential stage and the output stage.
Chapter 6
Control Network and Output
Stage
The primary objective of the CMOS output stage is to function as a current
transformer. Most output stages have a high current gain and a low voltage
gain. The speciﬁc requirements of an output stage might be:
1. Provide suﬃcient output power in the form of voltage or current.;
2. Avoid signal distortion.;
3. Be eﬃcient. (The eﬃciency can be deﬁned as the ratio of the power
dissipated on the load against the power delivered from the supply);
4. Provide protection from abnormal conditions. (Short circuit, over tem
perature and so on).
The second requirement results from the fact that the signal swings are large
and the nonlinearity normally not encountered in smallsignal ampliﬁers
will become important. The third requirement is born out of the need to
minimize power dissipation in the driver transistors themselves compared
with that dissipated in the load. The fourth requirement is normally met
with CMOS output stages since MOS devices are selflimiting.
An important function of the output stage is to provide the ampliﬁer
with a low output resistance so that it can deliver the output signal to the
load without loss of gain. Since the output stage is the ﬁnal stage of the
ampliﬁer, it usually deals with relatively large signals. Thus the smallsignal
approximations and models either are not applicable or must be used with
care. Nevertheless, linearity remains a very important requirement. In fact,
95
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 96
a measure of quality of the output stage is the total harmonic distortion
(THD) it introduces.
6.1 Classiﬁcation of Output Stage
Several approaches to implementing the output ampliﬁer will now be in
troduced here. Output stages are classiﬁed according to the drain current
waveform that results when an input signal is applied. For example, in a
ClassA ampliﬁer, the transistor conducts for the entire cycle of the input
signal, while in a ClassB ampliﬁer, a transistor only conducts for half of the
cycle of the input sine wave. And the ClassAB ampliﬁer, involves biasing
the transistor at a nonzero DC current much smaller the peak current of the
sinewave signal. As a result, the transistor conducts for an interval slightly
greater than half a cycle. The resulting conduction angle is greater than
180
o
but much less than 360
o
. The ClassAB ampliﬁer has another transis
tor that conducts for an interval slightly greater than that of the negative
halfcycle, and the currents from the two transistors are combined in the
load.
6.2 ClassA Output Stage
Here we introduce two kinds of ClassA ampliﬁer output stages:
6.2.1 Simple output ampliﬁer using a ClassA, currentsource
inverter
The circuit in Figure 6.1 will reduce the output resistance and increase the
current driving capability. The output resistance can also be seen in Figure
6.2.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 97
Figure 6.1: Reduced Output Resistance/Increased Current Driving Circuit.
Figure 6.2: Output Resistance for a ClassA Output Stage.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 98
6.2.2 CommonDrain (SourceFollower) Output Ampliﬁer
The circuit conﬁguration shown in Figure 6.3 has both large current gain
and low output resistance. But since the source is the output node, the MOS
device becomes dependent on the body eﬀect. The body eﬀect causes the
threshold voltage V
t
to increase as the output voltage is increased, creating
a situation where the maximum output is substantially lower than V
DD
. It
is seen that two Nchannel devices are used, rather than a Pchannel and an
Nchannel.
The eﬃciency of the source follower can be shown to be similar to the
classA ampliﬁer. The distortion of the source follower will be better than
the ClassA ampliﬁer because of the inherent negative feedback of the source
follower. Eﬃciency is deﬁned as the ratio of the power dissipated in R
L
(load
resistor) to the power required from the power supplies.
Figure 6.3: ClassA Output Stage  Source Follower Circuit.
6.2.3 Power Analysis
Next, we see that if the bias current, I, is properly selected the output voltage
can swing from 0 to V
DD
with the quiescent value being 1.65V (the absolute
maximum value should be
V
DD
2
). Now, assuming that the bias current, I,
is selected to allow a maximum negative load current of
V
DD
2R
L
, the drain
current of the upper transistor will swing from 0 → 2I with the quiescent
value being I. So the instantaneous power dissipation in the transistor should
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 99
be: PD
1
= V
ds1
· i
d1
. The maximum instantaneous power dissipation in the
upper transistor is V
DD
·
I
2
. So the upper transistor must be able to withstand
a continuous power dissipation of V
DD
·
I
2
(I =
V
DD
2∗R
L
).
The power conversion eﬃciency of an output stage is deﬁned as
E
ff
=
load power(P
L
)
supply power(P
S
)
(6.1)
For the ClassA output stage, the average load power will be
P
L
=
V
2
o
2 · R
L
(6.2)
Since the current in the lower transistor is constant (I), the power drawn
from the negative supply is V
DD
·
I
2
. The average current in the upper
transistor is equal to I, and thus the average power drawn from the positive
supply is V
DD
·
I
2
. Thus, the maximum eﬃciency attainable is 25% when
V
o
=
1
2
· V
DD
. Because this is a rather low value, the ClassA output stage
is rarely used in large power applications. Note, that in practice the output
voltage is limited to lower values in order to avoid transistor saturation and
associated nonlinear distortion. Thus, the eﬃciency achieved is usually in
the 10% to 20% range.
6.3 ClassB Output Stage
6.3.1 PushPull, Inverting CMOS ampliﬁer
The PushPull ampliﬁer (Figure 6.4) has the advantage of better eﬃciency.
It is well known that a ClassB, pushpull ampliﬁer has a maximum eﬃciency
of 78.5% which means that less quiescent current is needed to meet the
outputcurrent demands of the ampliﬁer. The circuit operates in a push
pull fashion: Nchannel transistor pushes current into the load when V
in
is
positive, and Pchannel transistor pulls current from the load when V
in
is
negative. Note that there exists a range of V
in
centered around zero where
both transistors are cut oﬀ and V
out
is zero. This ”Dead Band” results
in the crossover distortion. The crossover distortion of a ClassB output
stage can be reduced substantially by employing a highgain OpAmp and
overall negative feedback. A more practical method for reducing and almost
eliminating crossover distortion is found in the ClassAB ampliﬁer. The
output voltage swing is limited to a threshold voltage below V
DD
and above
V
SS
.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 100
Figure 6.4: ClassB Output Stage  PushPull Circuit.
Figure 6.5: ClassB Output Stage  Transfer Characteristics.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 101
Figure 6.6: Output Resistance for a ClassB (and ClassAB) Output Stage.
6.3.2 Power Analysis
To calculate the powerconversion eﬃciency, E
ff
, of the ClassB stage, we
neglect the crossover distortion and consider the case of an output sinusoid
of peak amplitude V
o
. So P
L
=
V
2
o
2·R
L
The current drawn from each supply
will consist of half sine waves of peak amplitude. Thus, the average current
drawn from each of the two power supplies will be
V
o
π
· R
L
.
E
ff
=
load power(P
L
)
supply power(P
S
)
It follows that the maximum eﬃciency is obtained when V
o
is at its
maximum
V
DD
2
. The powerconversion eﬃciency is 78.5%. This value is
much larger than that obtained in the ClassA stage.
6.4 ClassAB Output Stage
Crossover distortion can be virtually eliminated by biasing the complemen
tary output transistor at a small, nonzero current. The result is the Class
AB output stage. (See Figure 6.7). The ClassAB stage operates in much
the same manner as the ClassB circuit, with one important exception: for
small input, both transistors conduct, and as input is increased or decreased,
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 102
one of the two transistors takes over the operation. Since the transition is a
smooth one, crossover distortion will be almost totally eliminated.
Figure 6.7: ClassAB Output Stage Schematic.
This type of ampliﬁer is sometimes called an operational transconduc
tance ampliﬁer (OTA). It is very useful in driving capacitive loads. And
because it based on a ﬂoating current source, the output voltage can swing
from V
SS
to V
DD
. And the power relationships in the ClassAB stage are
almost identical to those derived for ClassB circuit in the previous section.
6.5 Short Circuit Protection
The circuit shown in Figure 6.8 shows a ClassAB output stage equipped
with protection against the eﬀect of shortcircuiting the output while the
stage is sourcing current. The large current that ﬂows through M1 in the
event of a short circuit will develop a voltage drop across R1 of suﬃcient
value to turn M2 on. The drain of M2 will then conduct most of the current
I
bias
, robbing M1 of its base drive. The current through M1 will thus be
reduced to a safe operating level. This method of shortcircuit protection
is eﬀective in ensuring device safety, but it has the disadvantage that un
der normal operation about 0.5V drop might appear across each R. This
means that the voltage swing at the output will be reduced by that much,
in each direction. On the other hand, the inclusion of the resistors provides
the additional beneﬁt of protecting the output transistors against thermal
runaway.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 103
Figure 6.8: ShortCircuit Protection Circuit Schematic.
6.6 Conclusion
After having studied several diﬀerent kinds of the output stages, and based
on the analysis above, the decision to use the ClassAB output stage was
ﬁnal. Again, the most important factors being:
1. It has high powerconversion eﬃciency (Maximum 78.5%).
2. It has low output resistance.
3. It can eliminate the crossover distortion in Class B.
Figure 6.9 shows the ﬁnal output stage used; the CrossoverClassB output
stage. It can be divided to two stages: one is the normal ClassB stage,
the other is the crossover stage. It provides the gain, bias, compensation
and drive to the two transistors in the ﬁnal stage. These two stages form
the ClassAB stage, and provide good performance. The total harmonic
distortion in this circuit is very small, only 0.05%. Figures 6.10, 6.11 and
6.13 show the three main types of analysis performed, AC Response, DC
Response and Transient Response, respectively.
Harmonic Analysis: The distortion of an ampliﬁer is always identiﬁed by
its response to the sinewave input signal. It is generated by the nonlinearity
of the ampliﬁer transfer characteristics. So if we know that the input signal
is:
V
in
(ω) = V sin ωt (6.3)
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 104
Figure 6.9: Final Output Stage with Crossover + ClassB.
Figure 6.10: AC Response of The Final Output Stage.
Then the output distortion should be:
V
out
(ω) = a
1
·V sin (ωt)+a
2
·V sin (2ωt)+a
3
·V sin (3ωt)+...+a
n
·V sin(nωt)
(6.4)
So the i
th
harmonic distortion (HD) is deﬁned as the magnitude of the i
th
harmonic to the magnitude of the 1
st
harmonic. For example, the second
harmonic distortion is HD
2
=
a
2
a
1
And the total harmonic distortion (THD)
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 105
Figure 6.11: DC response of The Final Output Stage.
Figure 6.12: Transient Response of The Final Output Stage.
is deﬁned as:
THD =
_
_
a
2
2
+a
2
3
+... +a
2
n
¸
a
1
(6.5)
Normally, the harmonic distortion of an ideal ampliﬁer should be less
than 1.0%.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 106
6.7 Design Considerations
While working on the output stage, an important phenomena was seen:
when the gain is increased the slope is increased and the linear range will
decrease. So if the gain is very high and the input signal is not small enough,
there will be harmonic distortion. In the ﬁnal circuit, the magnitude of
the input signal is 1µ, so there is almost no harmonic distortion. If the
magnitude of the input signal is increased harmonic distortion will begin to
appear. For example, when the magnitude is 100µV , the harmonic distortion
is around 10%. Is there a way that could deal with the harmonic distortion
when the input signal is increased to get higher output swing?
6.7.1 Negative Feedback
Negative feedback is always employed in the ampliﬁer design to eﬀect one
or more of the following properties:
• Desensitize the gain: that is, make the value of the gain less sensitive
to variations in the value of circuit components, such as variations that
might be caused by the changes in temperature.
• Reduce nonlinear distortion: that is, make the output proportional to
the input, make the gain constant independent of signal level.
• Reduce the eﬀect of noise: that is, minimize the contribution to the
output of unwanted electric signals generated by the circuit compo
nents and extraneous interference.
• Control the input and output impedances: that is, raise or lower in
put and output impedances by the selection of appropriate feedback
topology.
• Extend the bandwidth of the ampliﬁer.
All of the above desirable properties are obtained at the expense of a re
duction in gain and at the risk of the ampliﬁer becoming unstable (that is
oscillating).
6.7.2 Frequency Compensation
From the bode plot, we know that if the closedloopAmpliﬁer has one or two
poles, it is stable because the maximum phase shift of output is always less
than 180 degrees. But if there are more than 2 poles, it will become unstable.
CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 107
That means the ampliﬁer will oscillate. So in order to keep it stable, we
must use the frequency compensation. A popular method for frequency
compensation involves connecting a feedback capacitor to an inverting stage
in the ampliﬁer. This causes the pole formed at the input of the ampliﬁer
stage to shift to a lower frequency and thus become dominant, while the pole
formed at the output of the ampliﬁer stage is moved to a very high frequency
and thus becomes unimportant. This process is known as pole splitting. And
there are two parameters that are very important in the feedback ampliﬁer
design: gain margin and phase margin. The gain margin represents the
amount by which the loop gain can be increased while stability is maintained.
Feedback ampliﬁers are usually designed to have suﬃcient gain margin to
allow for the inevitable changes in loop gain with temperature, time and
so on. On the other hand, for a stable ampliﬁer, the phase lag must be
less than 180
o
. And feedback ampliﬁers are normally designed with a phase
margin of at least 45
o
. The amount of phase margin has a profound eﬀect
on the shape of the closeloop magnitude response.
Figure 6.13: Phase of the Crossover Output Stage.
Chapter 7
Integrating the SubCircuits
The last steps in the design ﬂow are to combine the circuits and test the
full schematic in order to ensure that there are no unexpected interactions
between the various subcircuits. The larger the design the more diﬃcult
these interactions can become to understand. Figure 7.1 shows the full
schematic representations.
Figure 7.1: Schematic of Entire OpAmp
108
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 109
7.1 Overall Performance
A simulation of the completed circuit was performed with a purely resistance
load of 100 MΩs (shown in ﬁgure 7.2) and an input signal of 1KHz with
a magnitude of 1 µV . It can be seen from the transient analysis that the
output waveform is linearly ampliﬁed around the operating voltage of 1.65
V. The gain is approximately 95· 10
4
(easily seen on the AC Response). The
diﬀerential input voltage, in the DC Sweep, is being measured relative to
the operating voltage of 1.65 V.
Figure 7.2: Overall Performance with 1 µV ,1KHz Input
A close up of the DC Sweep transition region can be seen in ﬁgure 7.3.
The input voltage swing range can be seen to be approximately 16 µV
Figure 7.3: DC Performance – with 1 µV ,1KHz Input
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 110
7.2 The Measurement of Some Main Parameters
In this part, we introduce some methods to measure parameters and then
apply some of them into the design of the OpAmp to evaluate it.
7.2.1 Input Oﬀset Voltage
Figure 7.4: Measurement of Oﬀset Voltage
Method: in 7.4, DUT is the OpAmp measured. We presume it’s an
ideal OpAmp which has it’s noninverting pin connected to an oﬀset voltage
source. Although there is no input signal, V
out
doesn’t equal to zero because
of the oﬀset voltage (V
os
).
For an ideal OpAmp: V
+
= V
−
For this circuit: V
+
= V
os
V
−
= V
out
·
_
R
2
R
1
+R
2
_
Then V
os
= V
out
·
_
R
2
R
1
+R
2
_
The result curve shows that when V
in
= 0, V
out
= 2.173V , because
R
2
R
1
+R
2
=
100
100 + 1M
= 10
−4
so
V
os
= 2.173 · 10
−4
= 0.217mv
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 111
Figure 7.5: Schematic for Measuring Oﬀset Voltage
Figure 7.6: Result Plot of Oﬀset Voltage Test
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 112
7.2.2 CommonMode Rejection Ratio (CMRR)
Figure 7.7: Measurement of CMRR
Figure 7.8: Schematic for Measuring CMRR
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 113
Figure 7.9: Test Results of CMRR Simulation
Method:
CMRR(dB) = 20 log
A
d
A
c
(7.1)
A
d
is the diﬀerential mode signal gain of OpAmp.
A
c
is the common mode signal gain of OpAmp.
For the 7.11, signal source is a low frequency AC signal. We get the following:
Figure 7.10: Equation
By calculating it:
Figure 7.11: Equation
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 114
Figure 7.12: Equation
Generally, A
d
A
c
, A
d
1, and (1 +A
d
) · R
2
R
1
, so approximately,
CMRR =
A
d
A
c
=
R
1
R
2
V
out
V
in
(7.2)
In the test circuit – 7.11,
R
1
R
2
= 10
4
, so
CMRR(dB) = 20 log 10
4
·
V
in
V
out
(7.3)
From the curve of 7.9, the amplitude of V
o
ut is about 0.55mV and the
amplitude of the input signal has been set to 1mV. So we can get the result
of our design’s CMRR is
CMRR(dB) = 20 log
_
10
4
·
1
0.55
_
= 85.2 dB (7.4)
7.2.3 Output Resistance  R
o
Method: Mr.Sedra and Mr.Smith provide us a method to get the closeloop
output resistance. (microelectronic circuits. Third edition. Pages 94 to
95). The schematic is below:
Figure 7.13: Derivation of the closedloop output resistance
In order to ﬁnd the output resistance of a closedloopAmpliﬁer, we short
the signal source, which makes the inverting and noninverting conﬁgura
tions identical and apply a test voltage V
x
to the output as shown in Figure
7.14. Then the output resistance R
out
=
V x
I
can be obtained by straightfor
ward analysis of the circuit.
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 115
We get the result directly(procedures omitted):
R
out
= (R
1
+R
2
)(
R
o
1 +Ab
) (7.5)
Note that R
out
is the ”closedloop resistance of Opamp” and R
o
is the
”openloop resistance”. The former one varies according to diﬀerent feed
back networks but the latter is a very important inherent characteristic of
the Opamp. From equation 7.5, Normally R
o
is much smaller than R
1
+R
2
,
so we get:
R
out
=
R
o
1 +Ab
(7.6)
b is deﬁned as: b =
R
1
R
1
+R
2
Consider the situation described as the schematic below:
Figure 7.14:
At this situation, R
1
⇒ 0 and R
2
⇒ ∞ , then b = 0, R
out
= R
o
. So
by calculating R
out
=
V
x
I
, we should get the openloop resistance simultane
ously.
Simulation result of our Opamp’s output resistance is some curves like:
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 116
Figure 7.15: Schematic for Measuring Output Resistance
Figure 7.16: Result of Output Resistance Test
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 117
7.3 Delivering Power to the Load/Instantaneous
Power
The maximum amount of power which can be delivered to the load can
easily be tested by decreasing the resistance of the load. We shall see that
the if the load becomes too small the OpAmp will not be able to maintain
the correct output voltage. See Figure 7.17.
Figure 7.17: AC & DC Simulation for a Parametric Load with 1 µV ,1KHz Input
It is obvious that the amount of current which the circuit can supply is
not enough. In order to increase the driving power which the circuit has, it is
necessary to increase the strength
_
W
L
_
of the pushpull output transistors.
Figure 7.18 shows the instantaneous power of the OpAmp at 1KHz through
a 10MΩ load.
Figure 7.18: Instantaneous Power
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 118
7.4 Improving the Output Buﬀer
A simpliﬁed schematic for testing the improved output buﬀer is shown in
ﬁgure 7.19. By increasing the transistor widths to: 15µm for the Nchannel
and 32.84µm for the Pchannel; we can improve the amount of power the
OpAmp can supply. Two capacitors have been added to the control network
in this schematic. These Miller Capacitors are required for stability.
Figure 7.19: Output Test Schematic
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 119
Figure 7.20: AC & DC Simulation with larger Output Transistors for 1 µV ,1KHz
Input
The size of the output transistors may be increased further if the design
speciﬁcations require more current to be delivered. The larger the output
transistors the more care must be taken in making sure that the transistors
are equally matched.
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 120
7.4.1 Stabilizing the Output
Without the new Miller Capacitors the OpAmp becomes unstable. This
was found in preliminary results; shown in ﬁgure 7.21. It should be noted
that the noise on the output is increasing with time, however, this instability
is not seen in the frequency simulation. This seems to be a limitation of the
HSPICE AC simulation.
Figure 7.21: Instability due to lack of Miller Capacitors
The frequency domain representation of the transient signal was calcu
lated from the 3 msec → 4 msec, using a rectangular data window. The
noise can be seen clearly at approximately 100KHz. Once the Miller Ca
pacitors are in place (with a value of 0.1 pF) this harmonic is completely
removed.
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 121
7.4.2 The Final Schematic
The ﬁnal Schematic for the OpAmp design is in ﬁgure 7.22.
Figure 7.22: Final OpAmp Schematic
Chapter 8
Closing Remarks
8.1 Conclusion
This project was a huge success from its beginning to its tentative com
pletion. By using a team oriented approach to the design methodology it
was possible to bring together such an intricate project. Many challenges
were incurred and resolved soundly and swiftly through the cooperation and
input of all of the group members. Each member of the group has become
a ”Miniexpert” in their area of their design and since these designs all ﬁt
together in a larger puzzle knowledge of the other areas has also been gained
my each group member.
122
CHAPTER 8. CLOSING REMARKS 123
8.2 Future Work
Due to the time limitations of this course, (5 Months), only the design
methodology was covered in this tutorial. The next step in the realization
of this Operational Ampliﬁer is its layout and fabrication. Layout being the
placing of the actual transistors down to the metal and poly layers. This
next step will have its own design methodology and its own set of challenges,
including troubleshooting, simulating and software testing.
Once the layout step has been completed the next step would be to have
the Operational Ampliﬁer fabricated. The fabrication can take several weeks
to several months once it has been sent to the fabricator. This time delay
is a result of the fabricator waiting to get enough designs to fabricate them
on a whole wafer of silicon, to fabricate (10) Operational Ampliﬁers on a
whole piece of silicon would not be cost eﬃcient. Thus, once the fabricator
completes this step the fabricated chips would be set back and would go to
the next stage which is actual hardware testing of the OpAmp.
The hardware testing of the Operational Ampliﬁer would involve phys
ically connecting the OpAmp chip to a power supply and putting in an
input signal and then viewing its output signal on an oscilloscope. Here the
DC and AC tests could be run as well as the protection of the circuit tested.
Chapter 9
Bibliography
1. A.S. Sedra And K.C. Smith, Microelectronic Circuits  4
th
Edi
tion, Oxford University Press, New York, 1998 ISBN: 0195116631,
Pages 221874
2. Allan R. Hambley, Electronics  2
nd
Edition, PrenticeHall, Upper
Saddle River, New Jersey, 2000, ISBN: 0136919820, Pages 211328
3. WaiKai Chen, The VLSI Handbook, CRC Press, Boca Raton,
Florida, 1999, ISBN: 0849385938
4. Ashok Ambardar, Analog and Digital Signal Processing, Brooks
Cole Publishing Company, Paciﬁc Grove, California, ISBN: 0534
95409X
5. James W. Milsson And Susan A. Riedel, Electric Circuits  5
th
Edi
tion, AddisonWesley Publishing Company, Reading, Massachusetts,
1996, ISBN: 020155707X, Pages 177211
124
Contents
Preface 1 Introduction 1.1 Review of CMOS FET’s . . . . . . . . . . . . . . . 1.2 Creating a New Library in Cadence . . . . . . . . . 1.3 Schematic Capture . . . . . . . . . . . . . . . . . . 1.3.1 Virtuoso Schematic Editor . . . . . . . . . . 1.3.2 Virtuoso Symbol Editor . . . . . . . . . . . 1.3.3 Aﬃrma Analog Circuit Design Environment 1.3.4 The Waveform Window . . . . . . . . . . . 1.3.5 The Cadence Calculator . . . . . . . . . . . 1.4 Generating the Characteristic MOSFET Curves . . 1.4.1 Nchannel EnhancementType MOSFET . . 1.4.2 Pchannel EnhancementType MOSFET . . 2 An Introduction to OpAmps 2.1 Parameters of an OpAmp . . . . . . . . . . . . . 2.1.1 Oﬀset Voltage . . . . . . . . . . . . . . . . 2.1.2 Input Current . . . . . . . . . . . . . . . . 2.1.3 Input Common Mode Voltage Range . . . 2.1.4 Maximum Output Voltage Swing . . . . . 2.1.5 Output Impedance . . . . . . . . . . . . . 2.1.6 CommonMode Rejection Ratio . . . . . . 2.1.7 Supply Voltage Rejection Ratio . . . . . . 2.1.8 Slew Rate . . . . . . . . . . . . . . . . . . 2.1.9 Unity Gain Bandwidth and Phase Margin 2.1.10 Settling Time . . . . . . . . . . . . . . . . 2.2 Methodology of Choosing OpAmp Parameters . 2.3 How to Adjust the Parameters . . . . . . . . . . i . . . . . . . . . . . . . iv 1 1 2 4 4 5 6 7 8 9 9 14 17 17 17 18 19 19 20 20 21 21 22 24 24 25
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS 2.3.1 2.3.2 2.3.3 2.3.4 Target Speciﬁcation . . . . . . . . . . . . . . . . . . . . . . Procedure of Optimization . . . . . . . . . . . . . . Optimize the Parameters of the OpAmp . . . . . . How to get the Quiescent point in a complex circuit OpAmp Speciﬁcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii 25 25 27 33 34
2.4
3 Current Mirrors and Biasing Networks 3.1 Ideal Characteristics of a Current Mirror 3.2 Basic Current Mirror Derivation . . . . 3.3 Benchmark Test Circuit . . . . . . . . . 3.4 Examined Current Mirrors . . . . . . . . 3.4.1 Basic Current Mirror . . . . . . . 3.4.2 Cascade/Cascode Current Mirror 3.4.3 Wilson Current Mirror . . . . . . 3.4.4 Modiﬁed Wilson Current Mirror 3.4.5 Reduced Cascade Current Mirror 3.5 Conclusion . . . . . . . . . . . . . . . .
35 . 36 . 36 . 38 . 39 . 39 . 41 . 43 . 44 . 45 . 47 48 48 49 53 57 58 60 61 62 63 64 66 66 67 69 72 72
4 Diﬀerential Input Stage 4.1 The Unbuﬀered OpAmp . . . . . . . . . . . . . . . . . . . . 4.2 Small Signal Equivalent Circuits . . . . . . . . . . . . . . . . 4.3 The Frequency Response . . . . . . . . . . . . . . . . . . . . . 4.4 Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Adding Rz in series with Cc . . . . . . . . . . . . . . . . . . . 4.7 Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . 4.8 Large Signal Consideration . . . . . . . . . . . . . . . . . . . 4.9 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 The CommonMode Range . . . . . . . . . . . . . . . . . . . 4.11 Important Relationships for The Design . . . . . . . . . . . . 4.12 Tradeoﬀs for Increasing the Gain of the Two Stage OpAmp. 4.13 Design Methodology for the Two Stage OpAmp . . . . . . . 4.14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Limitations of the Two Stage OpAmp . . . . . . . . . . . . . 4.16 The Cascode OpAmp . . . . . . . . . . . . . . . . . . . . . .
5 Inverting Ampliﬁers 76 5.1 Inverter with Active Resistor Load . . . . . . . . . . . . . . . 77 5.2 Inverter with Current Source/Sink Load . . . . . . . . . . . . 83 5.3 PushPull Inverter . . . . . . . . . . . . . . . . . . . . . . . . 87
2. . . . . .4. . . . . . . . . . . . . . . . . . . . .2 CommonDrain (SourceFollower) Output Ampliﬁer . . . . . . . 6. . . . . . . . 6. 6. . . . . . . . . . . . . . .1 Overall Performance . . . . 7. . . . . . 6.2 The Final Schematic . . . . . . 6. . . . . . . . . . . . . . . . . . . . . . .4 5. . . . . 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Simple output ampliﬁer using a ClassA. . . . . . . 7 Integrating the SubCircuits 7. . . . . . . . .2 ClassA Output Stage . . . . . . . . . . . . . . . . . . . . . . .2. 6. . . . . 123 9 Bibliography 124 . . .1 Input Oﬀset Voltage . . . . . . currentsource inverter . . 6. . . . . . . . . . . .3 ClassB Output Stage . . . . . . . . . iii 92 92 95 96 96 96 98 98 99 99 101 101 102 103 106 106 106 108 109 110 110 112 114 117 118 120 121 6 Control Network and Output Stage 6. . .7 Design Considerations . . .2 The Measurement of Some Main Parameters . .1 PushPull. . . 6. . . . . 6. . . . . .3 Delivering Power to the Load/Instantaneous Power 7. .2 Frequency Compensation . . . 6. .3 Power Analysis . . .5 Short Circuit Protection . . .3. .6 Conclusion . . .2. . . . . . . . 7. . . . . . . . .Ro . .2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . .2 CommonMode Rejection Ratio (CMRR) . . . . . . .5 Comparison . .2. . . . . . . . . . . . .2. . . . . . . . . . .7. . . . . . . . . . . . . 6. . . . . . . . . . . . . . . . Inverting CMOS ampliﬁer . . . . . . . . . . .1 Negative Feedback . . . .3. . . . . . . . . . . .4 Improving the Output Buﬀer . . . . . . 6. . . . . . . . . . . . .7. 6. . . . . . . . . . . . . . . . .CONTENTS 5. . . . . .4. . . . .1 Classiﬁcation of Output Stage . . . . . . . . . . . . . . . . . . 122 8. . . . . 7. . . .3 Output Resistance . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Conclusion . . . . . . . .1 Stabilizing the Output . . . . . .2 Power Analysis . . . . .4 ClassAB Output Stage . . . . 7. . . . . 7. . . 8 Closing Remarks 122 8. . . . . . . . . . . . . . . . . . . 7. . . .2. . .
Preface The purpose of this document is to familiarize the reader with the Cadence set of tools in order to do analog microelectronic circuits. iv . The design process will use TSMC’s CMOSP35 technology and as a result requires access to the restricted technology ﬁles.
are too complex to be used by humans. 1 . This means that a channel of charge carriers exists between the two Ntype regions. The gate of the device is insulated from the rest of the device. For an Nchannel transistor these charge carriers will be electrons. between the drain and source. 1. A quick overview of the device operation follows. The models which SPICE uses for the CMOSP35 technology are very accurate. for a more complete discussion please refer to an appropriate text book. Some generalized relationships are stated below. Unlike the Bipolar Transistor the MOSFET is a symmetrical device: the source and drain can be interchanged. The substrate connection. is always connected to VSS (which usually means ground).Chapter 1 Introduction This tutorial assumes that the user is working in the CMC supplied environment for CMOSP35 design. This allows current to ﬂow from the source terminal to the drain terminal. Emitter. meaning that no current will ﬂow into the gate of a MOSFET. for an Nchannel transistor. Collector and Substrate.1 Review of CMOS FET’s The Complimentary Metal Oxide SemiConductor Field Eﬀect Transistor is a four terminal device: Base. When the voltage on the gate of the device is large enough an inversion layer forms under the gate. however.
For this tutorial we will be using CMOSP35. In order to create a new library: File → New → Library This will popup a new window where the library name can be speciﬁed.1: Cadence icfb Window with CMOSP35 technology In order to create a new library select the following menu options: Tools → Library Manager From the Library Manager window it is possible to access all available libraries and to create new libraries.2 Creating a New Library in Cadence Once Cadence has been started the icfb window is shown. will be displayed in this window. therefore. Select cmosp35. . Figure 1. including error and warning messages. The next dialog will ask information about the technology ﬁle which is to be associated with the new library. Once you have entered the name of the library which is to be created. In this example we will use the name mylib. This is the main window for Cadence. INTRODUCTION 2 Ids = µef f Cox Vds Vg − Vf b − 2ψB − Vds 2 √ 3 3 W 2 2εsi qNa − µef f Cox (2ψB + Vds ) 2 − (2ψB ) 2 L 3Cox W L (1. press OK.CHAPTER 1. select Attach to existing techﬁle: this will bring another dialog window which lets us select which technology ﬁle we will use.1) 1. all messages.
5: Attach Design Library Window Figure 1.CHAPTER 1.2: Cadence Library Manager Figure 1.4: Technology File For New Library Window .3: Library Window New Dialog Figure 1. INTRODUCTION 3 Figure 1.
but rather leave the reader to use some of the schematics presented later in the document (Section 1.1 Virtuoso Schematic Editor Figure 1. power supply voltage) whereas some parameters will default to certain values if they are not entered. We will mostly be using transistors. This section will not give a circuit directly.CHAPTER 1. If the exact name of the desired cell is not known the Browse button may be used to open the Library Manager and graphically select the component. followed by: File → New → Cell View A dialog window will appear asking for the name of the new Cell View: enter OpAmp. Along the left boarder of the window are iconbuttons which allow for easy access to the more common commands. INTRODUCTION 4 1. Moving the mouse cursor over these windows will show a tooltip which explains which command is executed with each button. by entering a string instead of a numeric value. Some parameters are mandatory to be entered (e. These parameters may be changed later using the Properties option.3 Schematic Capture In this section we will be showing step by step how to enter a circuit schematic into Cadence’s Virtuoso Schematic Editor and how to create a symbol view for the schematic using the Virtuoso Symbol Editor.6) is the main window from which all of the schematic capture is performed.4 is a good starting circuit for a novice user). All commands are also available via the menus at the top of the window. Values may also be set to variables. resistors and capacitors (which are found in the library cmosp35) and power supplies and grounds (which are found in the library analogLib).3. In order to create a new Cell View. 1. When an instance of a component is added to a schematic all of the available parameters to the model may be set. When a schematic is entered the Insert Instance but is used (alternatively Add → Instance may be used) is used in order to place components into the schematic. This will automatically open the schematic capture session. Most commands will also have a shortcut key associated with them. Components are connected with narrow wires which may also be added via the iconbuttons or the menus.g. which can be set . open the Library Manager and click on the new library which has been created.
4. On startup the symbol editor will have a plain looking rectangle with terminal pins for each I/O pin inserted in the schematic.6: Cadence Virtuoso Schematic Editor in the simulation stage. INTRODUCTION 5 Figure 1.2 Virtuoso Symbol Editor Once the schematic for the circuit is done.g. Create a ”default symbol” by clicking: Design → Create Cell View → From Cell View Simply except the defaults and this opens the Symbol Editor. This is the view which is used when an instance of the circuit is put into another schematic (e. Once again we will simply accept the defaults and In order to use the circuit which has been created is it necessary to create a test bench circuit. . This will do a general check of the circuit in order to make sure that all circuits have and ground and that all device terminals are connected to something. it can be saved with a Check and Save iconbutton. The symbol of the newly created circuit may be inserted as any other subcircuit. This test bench circuit is created similarly to the original circuit.3. a symbol view must be created. An example of schematics for generating the characteristic curves is shown in Section 1. Once a design has been entered.CHAPTER 1. except that no symbol is generally required. We will not discuss all of the options available for this window since they are very numerous and are mostly selfexplanatory. 1. a test bench circuit).
It is also important to deﬁne the environment for the simulator so that all of the correct models ﬁles are used by the simulator: Setup → Environment. The Avant StarHSPICE simulator is the best simulator available. in order to select the simulator: Setup → Simulator. INTRODUCTION 6 1. these variables must be copied from the cell view to the analog environment: Variables → Copy From Cell view. . • Setting variables from the schematic. Figure 1.click OK.7.CHAPTER 1. All variables must be assigned values before a simulation may be performed.init.3 Aﬃrma Analog Circuit Design Environment Once a test bench circuit has been created and saved it is possible to start the simulation environment: Tools → Analog Environment The Aﬃrma window. If there are any parameter settings which are set to variables.7: Aﬃrma Analog Environment Simulation Window In order to run a simulation there are several things which must be deﬁned: • Selecting a simulator.3. Set this ﬁeld to /CMC/kits/cmosp35/models/hspice/icdhspice. click OK. In the dialog window which appears change the simulator selection to hspiceS. is the window from which all simulations are conﬁgured and executed. All variables which appear in the cell view will now be listed in the bottom left of the Aﬃrma window. The dialog box which appears contains a ﬁeld entitled Include File. ﬁgure 1. By doubleclicking the variables it is possible to change the value of the variable for the next simulation run.
8: Waveform Window The Waveform Window allows may customizations in order to generate desired plots.4 The Waveform Window Once the simulation is complete all outputs which were selected to be plotted. The schematic should reﬂect which nodes/terminals have been selected. In order to choose the simulation settings: Simulation → Choose.8.CHAPTER 1. Simulation may now be started by using the menu system or with the iconbuttons located on the right side of the Aﬃrma window. Figure 1. There are several types of simulations which may be performed at the same time. modify plot ranges & axis and add additional plots. it is possible to add annotations. Most of these options are fairly straight .3. • Selecting which variables are saved/plotted from the simulation. 1. By default not all variables are saved since this could lead to vary large amounts a data being generated by the simulation. In order to plot/save a set of values: Outputs → To Be Plotted → Select on Schematic. titles. will be in Waveform Window. Once the selection is done press ESC. This allows the user to click on all nodes (voltages) and device terminals (currents entering/leaving) in the schematic. Figure 1. INTRODUCTION 7 • Selecting and conﬁguring the simulations. The last step required to run a simulation is to set which variables should be plotted and saved. Most of the parameters available in the simulation settings are relatively straight forward and are left to the reader to lookup. this becomes more important for larger designs.
+ b. . and many more. The order in which operations are entered into the calculator may be counter intuitive to new users: The calculator uses a Postﬁx notation. INTRODUCTION 8 forward and will not be discussed in detail. 1. cos.3. + In the above table each letter represents one expression/waveform from the simulation. One way of easily accessing the data is to use the wave button and followed by selecting one of the waveform’s displayed in the waveform window. sin. If the simulation contains a larger number of simulated values than the browser button may be employed to browse through all of the information stored from the simulation. the reader is encouraged to experiment with the various display options. Some of the many features of the Calculator are: basic arithmetic operations on waveforms. b. One of the more advanced features available from the window is the calculator which is discussed in the next section. The display stack options is useful for evaluating large expressions. b. Total Harmonic Distortion analysis. a. c. + a.9: Cadence Calculator The calculator allows entry of waveform information by a variety of ways. ∗. In order to learn more about the many functions available in the calculator the reader should refer to the Cadence documentation. Discrete Fourier Transforms. Figure 1.CHAPTER 1.5 The Cadence Calculator The Cadence Calculator is an extremely powerful tool for analyzing data generated by the simulation. The table below shows some examples of the default order of operations: a+b a∗b+c sin a + cos b a.
and the substrate. and the drain(D). are created in the substrate. the source and the drain regions. Since the drain will be at a positive voltage relative to the source. 1. We applied a voltage to the gate controls current ﬂow between source and drain.4 Generating the Characteristic MOSFET Curves The enhancementtype MOSFET (MetalOxide Semiconductor FieldEﬀect Transistor) is the most widely used ﬁeldeﬀect transistor in the FET family.CHAPTER 1. Typically. A thin (about 0. the Source(S).1 Nchannel EnhancementType MOSFET The transistor is fabricated on a Ptype substrate. and the Body(B). The currentcontrol mechanism is based on an electric ﬁeld established by the voltage applied to the control terminal. the path between drain and source has a very high resistance (of the order of 1012 Ω) . In fact.with each having its own areas of application. two important parameters of the MOSFET. the substrate will be considered as having no eﬀect on device operation. which signiﬁcance is on par with that of the bipolar junction transistor. Thus. Two heavily doped ntype regions. Note that this region has a length L and a width W. four terminals are brought out: the Gate(G). the source(S). And the current is conducted by only type of carrier(electrons or holes) depending on the type of FET (N channel or P channel). which is a singlecrystal silicon wafer that provides physical support for the device. also known as the body. They prevent current conduction from drain to source when a voltage Vds is applied. the Drain(D). In normal operation these PN junctions are kept reversebiased at all time. INTRODUCTION 9 1. Observe that the substrate forms PN junctions with the source and drain regions. Metal contacts are also made to the source region. L is in the range 1 to 10 µm. The operation with Vds With no bias voltage applied to the gate. and the MOSFET will be treated as a 3terminal device. covering the area between the source the drain regions.Here.1um) layer of silicon dioxide(SiO2) is grown on the surface of the substrate. This current will ﬂow in the longitudinal direction from drain to source in the region called ”channel region”. two backtoback diodes exist in series between drain and source. Metal is deposited on top of the oxide layer to form the gate electrode of the device.4. the two PN junctions can be eﬀectively cut oﬀ by simply connecting the substrate terminal to the source terminal. and W is in the range 2 to 500 µm. with the terminals being the gate(G). the drain region.
We may visualize the increase in charge carriers in the channel as an increase in the channel depth.CHAPTER 1. As VGS exceeds Vt . Let VGS be held constant at a value greater than Vt (for example 2V). The result is a channel of increased conductance or equivalently reduced resistance. Increase VDS beyond this value has little eﬀect (theoretically. that is : VGS − VDS = Vt or VDS = VGS − Vt the channel depth at the drain end decreases to almost zero. applied to the gate. and increase the VDS from 0 to 3. the transistor induced a nchannel. no eﬀect) on the channel shape. the ID − VDS curve is shown in Eventually. When applying a positive voltage Vds between drain and source. which in turn depends on the magnitude of VGS .3V. as shown in the ﬁgure below. As VDS is increased. The drain current thus saturates at this value. The magnitude of iD depends on the density of electrons in the channel. and the current through the channel remain constant at the value reached for VDS = VGS − Vt . Figure 1.10: NChannel Test Circuit The voltage Vds cause a current iD to ﬂow through the induced N channel. which exceed the threshold voltage Vt . and the channel is said to be pinched oﬀ. more electrons are attracted into the channel. INTRODUCTION 10 With a positive voltage. and the MOSFET is said to . Current is carried by free electrons travelling from source to drain. when VDS is increased to the value that reduces the voltage between gate and channel at the drain end to Vt .
1.sat is called the triode region.11: ID − VDS Curve have entered the saturation region of operation.sat VDS. then the nchannel is continuous all the way from S to D. Triode If VGS > Vt and VDS ≤ VGS − Vt . there is a corresponding value of VDS. the cutoﬀ and triode regions are utilized. the triode region.sat = VGS − Vt Obviously. The region of the ID − VDS characteristic obtained for VDS < VDS .CHAPTER 1.sat . The saturation region is used if the FET is to operate as a ampliﬁer. The drain current increases if the voltage drop between S and D increases. We can see that there are three distinct regions of operation: the cutoﬀ region. which are a family of curves. and the saturation region. for every value of VGS ≥ Vt . The channel resistance . each measured at a constant VGS . The voltage VDS at which saturation occurs is named VDS. The S and D are connected by a conductor (or a resistor) of a given resistance.sat . INTRODUCTION 11 Figure 1. For operation as a switch. The device operates in the saturation region if VDS ≥ VDS. The ID − VDS Characteristics The Figure above shows a typical set of ID − VDS characteristics.
1µm oxide thickness. So the aspect ratio of W determines its L conductivity parameter K. The Drain current Id depends on both vGS and VGD (or VDS ).W physical constant known as the electron mobility(its value in this case applies for the electrons in the induced n channel) oxide capacitance. the length and the width of the channel. the capacitance per unit area of the gatetobody capacitor for which the oxide layer serves as dielectric.2) L.5Un · Cox Un Cox W L A V2 (1.CHAPTER 1. which in turn is controlled by vGS .12: ID − VDS Curve depends on how much charge is injected at the Send.3) (1. The ID − VDS characteristics can be approximately described by the relationship ID = K [2(VGS − Vt )VDS − VDS · VDS ] in which K is a device parameter given by K = 0. Since for a given fabrication process the quantity (0. approximately 10µA/V 2 for the standard NMOS process with a 0.5Un *Cox ) is a constant. INTRODUCTION 12 Figure 1. .
Once the drainend of channel is pinched oﬀ. pointing from the Drain region toward the inversion channel. That is. The boundary between the triode region and the saturation region is characterized by VDS = VGS − Vt (1.6) Substituting it into Equation 1.CHAPTER 1.5) . then Nchannel is induced at the Send. Increasing Vds beyond Vds−(sat) . In practice. An electric ﬁeld is set up in this region. VDS 1 = ID 2K(VGS − Vt ) (1. INTRODUCTION 13 If VDS is suﬃciently small so that we can neglect the VDS · VDS in equation 1. increasing VDS beyond vDS .4) = This linear relationship represents the operation of the MOS transistor as a linear resistance RDS RDS = 2. the current no longer depends on the voltage apply between S and D. further increases in VDS have no eﬀect on the channel’s shape. This is similar to PN junction diode where the minority carrier electrons of the Pside are swept to the nside by the builtin ﬁeld whenever they reach the depletion boundary.2 gives the saturation value of the current ID is ID = K(VGS − Vt ) · (VGS − Vt ) (1. then the ID − VDS characteristics near the origin the relationship ID ∼ 2K(VGS − Vt )VDS (1. Carrier electrons in the Nchannel that reach the depletion boundary are swept across the depletion region into the Drain. but the channel is depleted at the Dend. The complete independence of ID on VDS in saturation and the corresponding inﬁnite output resistance at the drain is an idealization based on the premise that once the channel is pinched oﬀ at the drain end.sat does aﬀect the channel somewhat. creates a fully depleted region between the inversion nchannel and the drain region.2. or equivalently decreasing VGD below Vt . Saturation If VGS > Vt and VDS ≥ VGS − Vt . the Nchannel is pinched oﬀ at the Drainend.7) Thus in saturation the MOSFET provides a drain current whose value is independent of the drain voltage VDS and is determined by the gate voltage VGS according to the squarelaw relationship.
and holes as charge carriers.CHAPTER 1. INTRODUCTION 14 Speciﬁcally. Mathematically. 3. as VDS is increased.nid.ps we extrapolated the straightline ID − VDS characteristics in saturation.11) = ID Thus the output resistance is inversely proportional to the DC bias current ID .005 < λ < 0. ID . Now since K is inversely proportional to the channel length (Equation 1. Since the channel resistance is proportional to the channel length. correspondingly. It should be obvious that channellength modulation makes the output resistance in saturation ﬁnite. Cutoﬀ If VGS < Vt (and of course.10) VA Rout ∼ (1. This results in the slight increase of the drain current beyond the saturation level. So vA is in the range 200 to 30 volts. the channel pinchoﬀ point is moved slightly away from the drain toward the source. 1.2 Pchannel EnhancementType MOSFET A Pchannel enhancementtype MOSFET (PMOS transistor) is fabricated on an Ntype substrate with p+ regions for the drain and the source.4. a phenomenon called channellength modulation. so. The device operates in the same manner as the Nchannel device except the VGS and VDS are negative and the threshold . then the no nchannel is present and no current ﬂows. K and. Thus the eﬀective channel is reduced. increases with VDS .3).8) the channellength modulation parameter:0. Let the output resistance Rout as Rout = λ · K(VGS 1 − Vt ) · (VGS − Vt ) Rout ∼ = substituted by λ = 1 VA VGS = constant (1. intercept the VDS axis at the point VDS = −1 = λ −VA .9) approximated by 1 λ · ID (1. VGD < Vt ). the channel length modulation introduces a VDS dependent term in ID : ID = K(VGS − Vt )(VGS − Vt )(1 + λ · VDS ) λ (1. the channel resistance is decreased.03 From Fig.
Up ∼ = 0. PMOS technology was originally the dominant one. Typically. VDS is negative or. λ. Nevertheless. The current iD is given by the same equation as for NMOS. However. and VDS are all negative.12) where Up is the mobility of holes in the induced p channel. and because NMOS requires lower supply voltages than PMOS. because NMOS devices can be made smaller and thus operate faster. and apply a drain voltage that is more negative than the source voltage (i. ID = K(VGS − Vt )(VGS − Vt )(1 + λ · VDS ) where VGS .5Un . NMOS technology has virtually replaced PMOS. The ID − VDS characteristics is shown above.CHAPTER 1.13: PChannel Test Circuit voltage Vt is negative. Vt . with the result that for the same W/L ratio a PMOS transistor has half the value of K as the NMOS device. To induce a channel we apply a gate voltage that is more negative than Vt .5 · Up · Cox W L (1.e. The current ID is given by the same equation used for NMOS. Also the current iD enters the source terminal and leaves through the drain terminal. INTRODUCTION 15 Figure 1. and the K is given by K = 0. it is important to develop the PMOS . vSD is positive). equivalently.
INTRODUCTION 16 Figure 1. both PMOS and NMOS transistors are utilized in CMOS circuits! . and more importantly.CHAPTER 1.14: ID − VDS Curve transistor for two reasons: PMOS devices are still available for discretecircuit design.
The required voltage is known as the input oﬀset voltage and is abbreviated Vos . a Vos . Its units are month .Chapter 2 An Introduction to OpAmps 2. and the input oﬀset voltage longterm drift. The input oﬀset voltage longterm drift speciﬁes how Vos is expected to change with mV time.1. A potentiometer is 17 . and a Vos is computed as Vos . One way to null the oﬀset is to use external null inputs on a single OpAmp package (2. Bipolar input OpAmps typically oﬀer better oﬀset parameters than JFET or CMOS input OpAmps.1 Parameters of an OpAmp This section will discuss OpAmp parameters. The average temperature coeﬃcient of input oﬀset voltage. The designer of an OpAmp must have a clear understanding of what OpAmp parameters mean and their impact on circuit design. speciﬁes the expected input oﬀset drift over temperature. Its units is mV . we will discuss the method of measurement of these diﬀerent parameters 2. The selection of any OpAmp must be based on an understanding of what particular parameters are most important to the application. Vos is measured at the temoC perature extremes of the part.1 Oﬀset Voltage All OpAmps require a small voltage between their inverting and noninverting inputs to balance mismatches due to unavoidable process variations.1). There are two other parameters related to and aﬀect Vos : the average temperature coeﬃcient of input oﬀset voltage. Input oﬀset voltage is of concern anytime that DC accuracy is required of the circuit. In the next section. Normal aging in oC semiconductors causes changes in the characteristics of devices. Vos is normally modelled as a voltage source driving the noninverting input. Generally.
is computed as the average of the two inputs: (IN + IP ) IIB = (2.1.2 Input Current The input circuitry of all OpAmps requires a certain amount of bias current for proper operation. Ios = IN + IP . If the OpAmp has high input bias current. AN INTRODUCTION TO OPAMPS 18 Figure 2. Oﬀset current is typically an order of magnitude less than bias current. In the case of bipolar inputs. it will load the source and a lower than expected voltage is seen. The best solution is to use an OpAmp with either CMOS or JFET input. even if the Vos is nulled at the beginning. IIB . 2.1: Oﬀset Voltage Adjust connected between the null inputs with the adjustable terminal connected to the negative supply through a series resistor. The average temperature coeﬃcient of input oﬀset current. Input bias current is of concern when the source impedance is high. it will change with temperature and some other conditions. The input bias current. The source impedance can also be lowered by using a buﬀer stage to drive the OpAmp that has high input bias current. oﬀset current can be nulliﬁed by matching the impedance seen at the inputs. the oﬀset current is usually not an issue and matching the impedance is not necessary.CHAPTER 2. In the case of CMOS or JFET inputs. The input oﬀset voltage is nulled by shorting the inputs and adjusting the potentiometer until the output is zero. The diﬀerence between the bias currents at the inverting and noninverting inputs is called the input oﬀset current. However.1) 2 CMOS and JFET inputs oﬀer much lower input current than standard bipolar inputs. .
the inputs will shut down and proper operation ceases.1. If the common mode voltage gets too high or too low. at least one of the diﬀerential inputs is still active. Its units are mA oC .4 Maximum Output Voltage Swing The maximum output voltage. when quiescent DC output voltage is zero.2. . The common mode input voltage range. Rail to rail input OpAmps use complementary N and P channel devices in the diﬀerential inputs. the saturation voltage of the output transistors. This is shown pictorially in 2. AN INTRODUCTION TO OPAMPS 19 Figure 2.2: Output Voltage Swing Ios . VOM .CHAPTER 2.3 Input Common Mode Voltage Range The input common voltage is deﬁned as the average voltage at the inverting and noninverting input pins. VOM is limited by the output impedance of the ampliﬁer. and the commonmode input voltage range includes both power rails. VICR. is deﬁned as the maximum positive or negative peak output voltage that can be obtained without waveform clipping. speciﬁes the expected input oﬀset drift over temperature. 2. For instance.1. and the power supply voltages. When the commonmode input voltage nears either rail. speciﬁes the range over which normal operation is guaranteed. 2.
Ideally this ratio would be inﬁnite with common mode voltages being totally rejected. Because of the inherent mismatches in the input circuitry.1. If the load is capacitive. Common emitter (bipolar) and common source (CMOS) output stages used in railtorail output OpAmps have higher output impedance than emitter follower output stages.CHAPTER 2. the output impedance will limit how close to the rails the output can go. the extra phase shift will erode phase margin. AN INTRODUCTION TO OPAMPS 20 This emitter follower structure cannot drive the output voltage to either rail.3 shows how output impedance aﬀects the output signal assuming Zo is mostly resistive. Generally.6 CommonMode Rejection Ratio Commonmode rejection ratio. Some data sheets list closedloop output impedance while others list openloop output impedance. With these structures. 2.5 Output Impedance Diﬀerent data sheets list the output impedance under two diﬀerent conditions. Zo is deﬁned as the small signal impedance between the output terminal and ground. values run from 50 to 200Ω . is deﬁned as the ratio of the differential voltage ampliﬁcation to the commonmode voltage ampliﬁcation. Figure 2. both designated by Zo . and the load being driven. Adif Acom . 2. CMRR. Railtorail output OpAmps use a common emitter (bipolar) or common source (CMOS) output stage. If the load is mainly resistive. the output voltage swing is only limited by the saturation voltage (bipolar) or the on resistance (CMOS) of the output transistors. The commonmode input voltage aﬀects the bias point of the input differential pair. Output impedance is a design issue when using railtorail output OpAmps to drive small resistive or large capacitive loads.3: Eﬀect of Output Impedance 2.1. .
changes the output voltage. 2. AN INTRODUCTION TO OPAMPS 21 changing the bias point changes the oﬀset voltage. which is added to make the OpAmp unity gain stable. Figure 2.5. is the ratio of power supply voltage change to output voltage change.4: Slew Rate The primary factor controlling slew rate in most amps is an internal compensation capacitor CC. The maximum rate of change is when either side of the diﬀerential pair is conducting 2IE. changing the bias point changes the oﬀset voltage.CHAPTER 2. changes the output voltage.1. The term V OS OS VCC means that the plus and minus power supplies are changed symmetriV cally. When kSVR is graphed vs. KSV R = V CC or KSV R = V DD . frequency.7 Supply Voltage Rejection Ratio Supply voltage rejection ratio. In OpAmps without internal compensation capacitors. Referring to 2. 2. For a single supply OpAmp. it falls oﬀ as the frequency increases. in turn. Also V OS OS note that the mechanism that produces kSVR is the same as for CMRR. Its units are V/ms or V/ms. V For a dual supply OpAmp. SR. kSVR (AKA power supply rejection ratio. but the designer must ensure the stability of the circuit. the slew rate is determined by internal OpAmp parasitic capacitances. in turn. PSRR). that not all OpAmps CC have compensation capacitors. The power voltage aﬀects the bias point of the input diﬀerential pair. 2. Essentially SR = 2IE . Uncompensated OpAmps have greater bandwidth and slew rate. KSV R = V CC or KSV R = V DD . which. Because of the inherent mismatches in the input circuitry. . However.4 shows slew rate graphically. Therefore kSVR as published in the data sheet is a DC parameter like CMRR.1.8 Slew Rate Slew rate. which. is the rate of change in the output voltage caused by a step input. voltage change in the second stage is limited by the charging and discharging of the compensation capacitor CC.
In order to increase slew rate. the bias currents within the OpAmp are increased.9 Unity Gain Bandwidth and Phase Margin Unitygain bandwidth (B1) and gain bandwidth product (GBW) are very similar.3) Gain margin is the diﬀerence between unity gain and the gain at 180o phase shift: Gain margin = 1 − Gain@180o phase shif t (2. This type of frequency compensation is . CC .2) Phase margin at unity gain (fm) is the diﬀerence between the amount of phase shift a signal experiences through the OpAmp at unity gain and 180o : f m = 180o − f @B1 (2.5).5: Op amp schematic simpliﬁed In OpAmps. 2. is purposely fabricated on chip in the second stage (2. B1 speciﬁes the frequency at which AV D of the OpAmp is 1.4) In order to make the OpAmp stable.CHAPTER 2. GBW speciﬁes the gainbandwidth product of the OpAmp in an open loop conﬁguration and the output loaded: GBW = AV D · f (2. a capacitor.1. AN INTRODUCTION TO OPAMPS 22 Figure 2. power consumption is traded for noise and speed.
6 shows a typical gain vs. Since railtorail output OpAmps have higher output impedance. This extra phase shift erodes the phase margin. and there are other frequency shaping elements within a real OpAmp.6: Voltage Ampliﬁcation and Phase Shift vs. a signiﬁcant phase shift is seen when driving capacitive loads. and for this reason most CMOS OpAmps with railtorail outputs have limited ability to drive capacitive loads. The idea is to cause the openloop gain of the OpAmp to roll oﬀ to unity before the output phase shifts by 180o .5 is very simpliﬁed. 2. Figure 2.CHAPTER 2. frequency plot for an internally compensated OpAmp. Frequency Phase margin and gain margin are diﬀerent ways of specifying the stability of the circuit. . 2. AN INTRODUCTION TO OPAMPS 23 termed dominant pole compensation.
In addition. ts . is the time required for the output voltage to settle to within a speciﬁed percentage of the ﬁnal value given a step input.7: Settling Time 2. Here we will to present a method of choosing the parameter in an Op . experiences damped oscillation. it takes a period of time for the output to react to a step change in the input. then it will be possible to get the desired quiescent point to ensure the ideal wave output. AN INTRODUCTION TO OPAMPS 24 2. Settling time.1. the output normally overshoots the target value. Therefore.10 Settling Time It takes a ﬁnite time for a signal to propagate through the internal circuitry of an OpAmp.2 Methodology of Choosing OpAmp Parameters The methodology of choosing the parameters of the transistors. and their relationships. Figure 2. and settles to a ﬁnal value.CHAPTER 2. Settling time is a design issue in data acquisition circuits when signals are changing rapidly.
Adjust the current source value I0 . input bias voltage = 1. and deal with more complex circuits.65 V ).(See Figure 2. then we can ﬁnish our job orderly. whose VDD = 3.8). Swing of output (Considering the current source VDD will occupy some voltage. At the same time we try to extend the method to other sophisticated architectures.65V (Input V0 = 1. 2. First of all we must clarify the relationship among diﬀerent parameters. the swing should be 0 → 3 V .3. all of the other parameters will be chosen to match the current value. The quiescent point is very important for our design. we will concentrate on the simplest OTA OpAmp 2. 2. Further more in this way we can learn how to combine diﬀerent parts of a circuit together.3 V . 2. The current value takes highest priority of all of the parameters.8: Circuit with Default Parameters 2. and in the same way we can get a very eﬃcient optimization method. VSS = 0 V .3.3 How to Adjust the Parameters To simplify the discussion. Draw a circuit with default parameters.2 Procedure of Optimization 1. AN INTRODUCTION TO OPAMPS 25 Amp circuit.CHAPTER 2.) Figure 2. .8 and demonstrate how to adjust its parameters to get the proper DC gain.1 Speciﬁcation Here we are asked to design an OpAmp.
so the value of I1 = 1 · I0 . Figure 2.25µm. Vout = 1. The value of the width of the channel.4366µA → 800.9). we know that when the OpAmp is working in the common mode (which means the V1 = V0 = 1. so we regard the 400µm as the initial value of our design.CHAPTER 2.9 we perform a parametric analysis. 4. then I1 should be from 86. Vref = 1. We design a very simple circuit to test the current value from the drain of a PMOS (Figure 2. from here we can 2 decide what is the maximum and minimum value we can get through a PMOS. through which we can get the proper value for the quiescent point. The range of the length should be 400nm → 2000 nm.9: Simple Test Circuit for Drain Current We can choose any value inside the range. We can assign an arbitrary big value to the width of the diﬀerential .65 V ). From Figure 2. then the current through the two (2) diﬀerential ampliﬁers is symmetric. So the I0 should be double I1 it should be from 170µA → 1700µA. When changing the width of the channel of the PMOS. It is about 1.00µA. AN INTRODUCTION TO OPAMPS 26 From the circuit. Decide the width of the channel of the active load. Considering the width of the active load should not to be too large so we can get better gain.10).65 V . we can get a set of values of the current value of the drain(Figure 2.65 V . 3.
3.CHAPTER 2.10: Simple Test Circuit .3 Optimize the Parameters of the OpAmp 1. Gm = 2Kn I0 · Rout = Ve W L L1 I0 1 2 . 5. suppose we choose a value 5 times bigger than the width of the active load. Figure 2. According to the gain of the speciﬁcation.Parametric Analysis of Channel Width ampliﬁer.DC Response/Gain 2. Do the simulation and compare the gain we get with the gain we want. decide the width of the diﬀerential ampliﬁer.11: Simple Test Circuit . AN INTRODUCTION TO OPAMPS 27 Figure 2.
which means we cannot reduce the I0 less than 170µA. then what we need to do is just to adjust the value of the length and the width of the channel of diﬀerential ampliﬁer. the width of the channel of the transistor cannot be less than 350µ m. Further reducing I0 .12: Waveform Distortion 3. according to the fabricating technology. we can cascade active loads together. otherwise the quiescent point cannot be at the middle of the curve. AN INTRODUCTION TO OPAMPS AV = Gm Rout = Ve 2Kn W1 L1 I0 f rac12 28 There are three (3) variables that will aﬀect AV . If there is small diﬀerence between the two (2) gains. First. W.12). so the I0 can be reduced dramatically. because the voltage is on the cascade active load. 2. Each time I0 is adjusted the width of the active load should be changed accordingly. However. Thus another way to adjust I0 must be devised. there is less voltage across each transistor. (See Figure 2.13 . See ﬁgure 2. otherwise we must reduce the I0 . L and I0 . this will distort the input waveform. As mentioned above.CHAPTER 2. it becomes more complex to further optimize the circuit. Reduce I0 . Figure 2.
DC Response/Gain .13: Active Loads Cascaded Together Figure 2. AN INTRODUCTION TO OPAMPS 29 Figure 2.14: Cascaded Active Loads .CHAPTER 2.
CHAPTER 2. actually at this point the output of . Cascade OpAmp . The key to optimizing the cascade OpAmp is the quiescent point. which guarantees the proper operation of the circuit. as in Figure 2.5 V → 2. AN INTRODUCTION TO OPAMPS 30 4.adjusting the quiescent point: If after all of the above eﬀort.15: Output Curve of the First Stage Checking the 2 stage OpAmp. we get the waveform as shown in Figure 2.18: We notice that the operating point of the ampliﬁer begins to work is about 0V. Please refer the Figure 2. The output of the ﬁrst stage is linear in the area of (0.15 V ). So we should adjust the quiescent point of the input of the second stage. Figure 2. we have to use a cascade OpAmp. we still cannot get the proper gain.16 Figure 2.15 (Output curve of ﬁrst the stage).16: Two Stage OpAmp Circuit In the second stage ampliﬁer.17 and Figure 2.
AN INTRODUCTION TO OPAMPS 31 Figure 2. Figure 2.19 NonLinear Problem).17: Second Stage Waveform the ﬁrst stage is in the nonlinear area.20).CHAPTER 2. That means the wave we get isn’t the best. (See Figure 2. it will have little aﬀect on the nonlinear problem. however. . (Figure 2.18: Second Stage Circuit We can change the parameters of the two (2) transistors. Thus we must use another topology.
AN INTRODUCTION TO OPAMPS 32 Figure 2.CHAPTER 2.20: Diﬀerent Topology to overcome NonLinear Problem .19: NonLinear Problem Figure 2.
22: Circuit with Modiﬁed Output Stage 2. To simplify the problem we can change the output stage.21. AN INTRODUCTION TO OPAMPS We then get the resulting waveform shown in Figure 2. to change the input linear area of the second stage. There are certain ways to design with the help of the computer. Figure 2. and establish models for diﬀerent stages. 33 Figure 2.4 How to get the Quiescent point in a complex circuit Keeping a good quiescent point is very important and can be easily forgotten as the circuits become more complex.CHAPTER 2.3. .21: Resulting Waveform We can adjust the circuit in another way.
1 µsec 1 µsec Best Case 1.0 µF 1 µsec 10 µsec Target Case 1.000 20.5 V /µsec 0.CHAPTER 2. Speciﬁcation Gain Frequency Range (Hz) Bandwidth Input Voltage Output Resistance Power Consumption CMRR Slew Rate THD Parasitic Capacitance Rise Time Settling Time Worst Case 100 → 1.01% 1.000 5.1% 1. fabricated OpAmp datasheets and from other research. 000 1020.1 µsec . in addition the target OpAmp parameters for this design are listed.000 50.1 µV 10 M Ω nW > 60dB 0.0 KHz ±1 µV 1 MΩ µW > 50dB 2 V /µsec 0. AN INTRODUCTION TO OPAMPS 34 2.0 KHz ±1 mV 500 KΩ mW > 40 dB 3 V /µsec 1% 1. 000 10200. These values are based upon textbook values.0 KHz ±0. 000 → 100. During its design these key parameters were always kept at close hand.0 f F 0.000+ 5500.001 µsec 0.000.0 nF 0.4 Target OpAmp Speciﬁcations The table below deﬁnes the best and worst cases for several key OpAmp parameters.
These current mirrors were then subjected to several tests including. These factors were considered when deciding on the current mirror to be used in the OpAmp Design. The ability of a current mirror to hold current constant. the number of transistors used and their sizes are the general deﬁning factors on whether a current mirror is ”Good” or not. The ﬁve current mirrors which were examined were designed in Cadence and were placed into a standard test circuit consisting of a basic diﬀerential pair with active load and basic commonsource ampliﬁer output stage with a 10KΩ load. current mirror output impedance and stability of current supplied across dynamic voltage range. Basic Current Mirror. With the correct DC operating point established a stable and predictable DC drain current ID and a DC drainsource voltage ensures operation in the saturation region for all input signals that may be encountered. The purpose of the bias circuity is establish an appropriate DC operating point for the transistor.Chapter 3 Current Mirrors and Biasing Networks One of the most important parts of an analog design is the biasing circuity. Cascade/Cascode Current Mirror. DC Sweep. gain stage and output stage rely on its ﬂawless stable operation. Modiﬁed Wilson Current Mirror and Reduced Cascade/Cascode Current Mirror. This component forms the basis for an operational ampliﬁer whereby various circuits like the diﬀerential pair. 35 . Wilson Current Mirror. The advantages and disadvantages of each type of current mirror will be outlined later. For the Operational Ampliﬁer design ﬁve diﬀerent types of current mirrors were examined.
Using equations 1.2) Now looking at Q2.2 Basic Current Mirror Derivation Below is the derivation of the simple current mirror. 2. Input Resistance is zero. Assuming gate currents to be approximately 0. and assuming it is operating in saturation.1 Ideal Characteristics of a Current Mirror 1. Q1 is operating in the saturation region since its drain is shorted to its gate. The drain current of Q1 is supplied by VDD through a resistor. 1 IO = ID2 = Kn 2 W L 2 (VGS − Vt )2 (3. 3.3) Again neglecting channellength modulation. ID1 = Iref = VDD − VGS R (3. 1 ID1 = Kn 2 W L (VGS − Vt )2 (3.1) 1 Note we neglect channellength modulation and assume λ = 0. Output current linearly related to the input current. which is the output current Io of the current source will be. Output resistance is inﬁnity. CURRENT MIRRORS AND BIASING NETWORKS 36 3. Iout = A · Iin .CHAPTER 3. It has the same Vgs as Q1. its drain current.2 and 3 we are able to relate the output current I o to the reference current Iref . R.4) . 3. Rearranging equation 1 and substituting Iref = Id1 Iref W L 1 1 = Kn 2 W L 1 (VGS − Vt ))2 (3. Thus.
6) Thus we have a relationship whereby modifying the width and length we can change the output current. IO = Iref W L 1 · W L 2 IO = Iref W L 2 W L 1 (3.5) So substituting into equation 3.8) (3.5. width and lengths equal and other parameters the same we have.e.7) This is called a current mirror since the reference current is ”mirrored” or held constant at the output. IO = 1 Kn (VGS − Vt )2 2 W L 37 (3. . IO =1 Iref IO = Iref (3. Thus if the transistors were matched. CURRENT MIRRORS AND BIASING NETWORKS We know. i.CHAPTER 3.
L=350nm).50µA and 7. L=350nm) and common source ampliﬁer (W=800nm. .CHAPTER 3. as well as. CURRENT MIRRORS AND BIASING NETWORKS 38 3. L=350nm). the overall size of the transistors once the desired current was achieved. a basic two transistor active load (W=800nm. Then the output impedance was measured.3 Benchmark Test Circuit The purpose of the test circuit is to establish a benchmark which could be used to evaluate the performance and design of each of the diﬀerent types of biasing circuits. The test circuit itself consists of a basic diﬀerential pair (W=1900nm. Figure 3. This test circuit was kept the same for all tests and the transistor sizes were set to the smallest possible optimum values. These results were recorded out would help to choose which current mirror would be the ”Winner”.00µA.1: Benchmark Test Circuit Schematic The widths of the transistors were adjusted so that the current supplied to the diﬀerential pair was between 6.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS
39
3.4
3.4.1
Examined Current Mirrors
Basic Current Mirror
We will now examine the most fundamental and simple type of current mirror, the Basic Current mirror (See Figure 3.2). This type of current mirror uses a minimum of (3) three transistors. The derivation shown earlier shows the general operation of a current mirror whereby current is held constant regardless of the voltage being supplied.
Figure 3.2: Basic Current Mirror Schematic This circuit is very simple and does a very good job of supplying constant current, however, it does not supply absolutely stable current. See ﬁgure 3.3, the output current supplied to the active load and the output impedance.
Figure 3.3: Basic Current Mirror Simulation Results
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS
40
The main advantage of this current mirror is its simplicity and ease of implementation, however, the major disadvantage is that the current supplied is not completely stable.
CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS
41
3.4.2
Cascade/Cascode Current Mirror
The second current mirror examined was the Cascade/Cascode Current Mirror. This current mirror uses a minimum of (5) ﬁve transistors, these transistors can be seen in the Figure 3.4.
Figure 3.4: Cascade/Cascode Current Mirror Schematic This circuit is a little bit more complex than the simple current mirror with (2) two extra transistors and would be more than enough for any design. The main disadvantage to this current mirror is that it is not very good at supplying higher amounts of current, in particular to the output stages. It was given very high consideration when deciding which current mirror to use for the OpAmp design.
Figure 3.5: Cascade/Cascode Current Mirror Simulation Results
it scored high in our choice for current mirrors when testing. The main disadvantage to this type of current mirror is a reduced dynamic range. . In addition to this we have a higher output resistance compared to the basic current mirror. Thus.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 42 The main advantage to this design is that it provides stable current and it has relatively small transistor sizes.
6 you can see the circuit layout. This current mirror uses a minimum of (4) four transistors.6: Wilson Current Mirror Schematic This circuit is not as complex as the cascade current mirror and does provide good stable current. In the Figure 3. Figure 3.3 Wilson Current Mirror The third current mirror examined was the Wilson current mirror.7: Wilson Current Mirror Simulation Results As stated above this design was not considered for the OpAmp design and the cascade current mirror was the current best. . given that the current ”best”. however.00µA very large transistors (200µm) had to be used.CHAPTER 3. cascade current mirror provided similar qualities but with much smaller transistor sizes this current mirror was ranked very low. CURRENT MIRRORS AND BIASING NETWORKS 43 3. Figure 3.50 → 7. to provide the benchmark 6. and thus.4.
CURRENT MIRRORS AND BIASING NETWORKS 44 3. This current mirror was expected to perform similar to the regular Wilson current mirror.9: Modiﬁed Wilson Current Mirror Simulation Results Upon seeing these results. .CHAPTER 3. Figure 3.8. You can see the circuit schematic in Figure 3.4. the Modiﬁed Wilson current mirror was not to be chosen as the current mirror for the OpAmp design.8: Modiﬁed Wilson Current Mirror Schematic Upon testing the results revealed that the initial idea that it would perform similarly to the regular Wilson current mirror were conﬁrmed. It had similar results with the output current as output resistance and the transistor sizes needed to attain the benchmark current we also large (200u).4 Modiﬁed Wilson Current Mirror The fourth current mirror examined was the Modiﬁed Wilson current mirror. This current mirror uses a minimum of (5) ﬁve transistors and has a similar layout as the cascade current mirror. Figure 3.
Figure 3. Figure 3. However. it is usually about (1/2) onehalf of the usual voltage. This is very useful in the output stages were higher amounts of current are needed to bias the output stages.4.10: Reduced Cascade Current Mirror Schematic This current mirror is a bit more complex and the transistor sizes are comparable to the basic cascade current mirror.CHAPTER 3. the reduced cascade current mirror oﬀers a reduced voltage and is able to provide higher amounts of current.11: Reduced Cascade Current Mirror Simulation Results . CURRENT MIRRORS AND BIASING NETWORKS 45 3. The word ”Reduced” in the name refers to the reduced voltage at which the current reaches a stable output.5 Reduced Cascade Current Mirror The ﬁfth and ﬁnal current mirror examined was the Reduced Cascade current mirror. This current mirror used a minimum of (6) six transistors and had a similar layout to that of the basic cascade current mirror.
CHAPTER 3. . it was able to provide higher amounts of output current if necessary. CURRENT MIRRORS AND BIASING NETWORKS 46 The results of this current mirror appeared to be the most promising for the OpAmp design. as well as. it provided stable current. it reduced the voltage at which the current was stable compared to the other current mirrors examined.
however with the reduced cascade’s reduced voltage it oﬀered a bit of an advantage over the basic cascade current mirror. In the table below you can see the current mirrors ranked from best to worst (top to bottom) as well as a few of the ranking criterion and their evaluation. Third. Secondly.5 Conclusion The decision to use the Reduced Cascade/Cascode Current Mirror in the design of this OpAmp are now shown here. diﬀerential Pair Biasing and Output Stage) .0µA Current Small Very Small Very Large Very Large Small Very High Very High Moderate Moderate Simple N = Number of times current is mirrored. The Basic Cascade/Cascode current mirror would have also done a very good job in the design. (In these designs N = 2. First. Lastly. it was able to supply larger amounts of current which were needed to drive the output stage. given it had a few extra transistors their sizes were small compared to other current mirror setups looked at. Current Mirrors Ranked: (Best to Worst) Reduced Cascade/Cascode Basic Cascade/Cascode Basic Wilson Modiﬁed Wilson Basic Min # of FET’s including Iref Transistors 6+2N 3+2N 2+2N 3+2N 2+N Current Stability Excellent Very Good Good Good Poor Output Resistance Very High Very High High High Low Input Resistance Very Very Very Very Very Low Low Low Low Low Complexity Transistor Sizes needed to achieve Ref 7. the reduced cascade/cascode current mirror provided stable and linear current in all test situations.CHAPTER 3. CURRENT MIRRORS AND BIASING NETWORKS 47 3. it provided very high output resistance and a very low input resistance.
Output stage. 48 .1 The Unbuﬀered OpAmp Figure 4.1: Two Stage OpAmp The ampliﬁer shown in ﬁgure 4. 2. Diﬀerential input stage.1 can be segregated into: 1.Chapter 4 Diﬀerential Input Stage 4. Biasing block. 3.
M4 with: M1 matching M2.3. The signal current of an ideal constant DC current source will always be zero thus an ideal constant DC current source can be replaced by an open circuit.2 Small Signal Equivalent Circuits Figure 4. The small signal analysis of the . and M5. M2. Ideal constant DC voltage sources are replaced by short circuits. In ﬁgure 4. the small signal model parameters: gm and ro depends on the DC bias of the FET.CHAPTER 4. 4.2: NFET and Its Small Signal Model In the analysis of a FET ampliﬁer circuits.2. The output stage consists of M6 and M7. v Since vds = vgs (the eﬀective resistance = vgsgsm = g1 ) ·g m Figure 4. the model is as shown in ﬁgure 4. consists of M8. Where: ro = Where V A ID 1 VA= λ gm is the transconductance parameter = Kn W (VGS − Vt ) L Therefore. The diﬀerential input stage is composed of M1. M3 matching M4. the FET can be replaced by the equivalent circuit model. 4. For the gate drain connected FET device.4 shows only the diﬀerential input stage of the circuit.1 M5 are replaced by current source Iss . The bias current greatly aﬀects the performance of the ampliﬁer. M9. M3. DIFFERENTIAL INPUT STAGE 49 The biasing block. this is a result of the fact that the voltage across an ideal constant DC voltage source does not change and thus there will always be a zero voltage signal across a constant DC voltage source.
S2 of M1. M3 matches M4 (The point where S1. DIFFERENTIAL INPUT STAGE 50 Figure 4. Figure 4. then the point where the two sources of M1 and M2 are connected can be considered at AC ground. Since: M1 matches M2. M2 are connected can be considered at AC ground.5 which is only appropriate for diﬀerential analysis when both sides of the ampliﬁer are assumed to be perfectly matched. The body eﬀect is neglected.3: MOSFET Resistor and Its Small Signal Model diﬀerential input stage can be accomplished with the assistance of the model shown in ﬁgure 4.) Since S3. If this condition is satisﬁed. S4 are .4: CMOS Diﬀerential Ampliﬁer using nchannel Input Devices The model in ﬁgure 4.CHAPTER 4.5.6 is the simpliﬁed to the model shown in ﬁgure 4.
id1 = gm1 · vgs1 . therefore S1.5: The Exact Model for the CMOS Diﬀerential Ampliﬁer AC ground. which will ﬂow from drain to source of M1.6: C1 = cgd1 + cgs3 + cgs4 C2 = cgd2 C3 = cgd4 Any small signal on gate of M1 will result in a small signal current id1 .CHAPTER 4. DIFFERENTIAL INPUT STAGE 51 Figure 4. S2. Figure 4. S3. S4 can be joined up in a node.6: The Simpliﬁed Equivalent Model Referring to ﬁgure 4.
3) Now the small signal output voltage is simply: vout = iout rout (Substitute 4.2) (4.2 ID1.1) (4.2 ) 2 · vid 2λID1. gm2 · vgs2 = −id1 iout = id1 − (−id1 ) = 2id1 rout = ro2 Since vgs1 = vgs2 vid = vgs1 + vgs2 Therefore. vid = 2vgs1 id1 vid = = vid = gm1 vgs1 2vgs gm 1 2 2id1 gm1 ro4 id1 = gm1 · vgs1 52 (4.5) gm1.4 over 4. S2.2 ID1.2) (4.2 ) 2 1 2λID.2 (ro2 ro4 ) vid Now: (ro2 ro4 ) ∼ = Therefore.1 and 4.2 = (2β1.4) vout = 2id1 · (ro2 ro4 ) Now dividing 4. S4 have the same potential (one node) id1 will also ﬂow from the source to drain of M2.2 (4.CHAPTER 4.2 (since r = 1 ) λI 1 . S3.3 : vout 2id1 (ro2 ro4 ) = 2id1 vid g m1 vout = gm1. DIFFERENTIAL INPUT STAGE and also be mirrored from M3 to M4 gm4 · vgs4 = id1 Now since S1. 1 1 vout ∼ = (2β1.
vgs2 = 0.2 Therefore. Increasing W1.2 Then a proportionality can be established between L1.6.2 1 2 53 · 1 λ K is a constant. W1.2 L1.CHAPTER 4. The eﬀect of λ on the 1 gain diminishes as L increases. vid = vgs1 . 4. 2. In the conﬁguration where the small signal is applied to the gate of M4 while the gate of M2 is grounded.2 . 1 1 1 [c2 · (ro2 ro4 )] c1 · gm3 Then the node (D1=D2=G3=G4) is a low impedance node (with large RC time) Now: c3 is assumed to be zero. In most applications of diﬀerential ampliﬁers. We will work to eliminate all low impedance nodes (having high RC time): If.2 and the drain current versus the small signal gain such that: W1.2 1 2 1 2 (4. Then the model to be considered for the high frequency response analysis is turned to be as shown in ﬁgure 4. uncontrollable by the designer. Now: gm4 vgs4 = id1 = gm1 vgs1 = gm1 vid .2 ID1. Conclusions: 1.6) The constant was not included since the value is not dependent on anything the designer can adjust.3 The Frequency Response Referring back to the model of the input stage: ﬁgure 4. Decreasing the drain current through M1.7.2 or both increases the gain.2 vout ∼ =K · vid L1. such that λ is directly proportional to the channel length. L1. M2 which is also increases the gain. 1 2 ID6 .2 small signal gain ∝ ID1.2 L1.2 vout ∝ vid ID1. DIFFERENTIAL INPUT STAGE W1. W1. this assumption turns out to be valid.
the frequency response will be dominated by the high impedance nodes.9 making use of Figure 4. C2 represent the total lumped capacitance from each ground.CHAPTER 4. c2 . Since each node in a circuit contributes a high frequency pole. . C1 . Figure 4. cgd ). these nodes will be the dominant frequency dependent nodes in the circuit. Figure 4. To determine the exact value for c1 .8. cdb ) and the overlap capacitors (cgs . Figure 4. DIFFERENTIAL INPUT STAGE 54 Figure 4.8: Model of the Input Stage used to Determine the Frequency Response The high frequency output can be given by: vo1 = gm1 vid · (ro2 T he f req. The capacitor Cc in Figure 4.9.7 with the new parameters will result in the model shown in Figure 4.7: High Frequency Small Signal Model with Parasitic Capacitors Now redrawing the model in Figure 4.8 is removed for the purpose of the ﬁrst analysis. Since the output nodes associated with each output is a high impedance. Response = ro4 ) · 1 1+S· 1 c2(ro2 ro4 ) vo1 = gm1 · (ro2 vi d ro4 ) · 1 1+S· 1 c2 (ro2 ro4 Now let us consider the input and the output stage shown in ﬁgure 4.11 shows the parasitic capacitors explicitly for the input and the output stage which include the bulk depletion capacitors (cgb . csb .10 is the model derived for Figure 4.8 to determine the frequency response of the twostage OpAmp.
9: Two Stage OpAmp with Lumped Parasitic Capacitors Figure 4.10: Model Used to Determine the Frequency Response of the TwoStage OpAmp Miller theorem was used to determine the eﬀect of the bridging capacitor cgd6 connected from the gate to drain of M6.CHAPTER 4. Where: . DIFFERENTIAL INPUT STAGE 55 Figure 4. Miller theorem approximates the eﬀects of gatedrain capacitor by replacing the bridging capacitor with an equivalent input capacitor of value cgd (1 + A2) and the equivalent output 1 capacitor with a value of cgd (1 + A2 ).
Also from the high frequency model ﬁgure 4.CHAPTER 4. DIFFERENTIAL INPUT STAGE 56 Figure 4.10: vo vo1 vo = · · vid vo1 vid 1+ 1 S c2 ·(ro6 ro7 ) · 1 1+ S c1 ·(ro2 ro4 ) . c1 = cdb4 + cgd4 + cdb2 + cgd2 + cgs6 + cgd6 · (1 + A2) c2 = cdb6 + cdb7 + cgd7 + cgd6 · 1 + 1 A2 + cL (4.10: vo ro6 ro7 = −gm6 · vo1 vo1 vo1 A2 = −gm6 (ro6 ro7 ) A2 = Thus c1. from ﬁgure 4.7) 1 Now assume c1 < c2 (the pole associated with the diﬀamp output c1 (ro2 ro4 ) will be lower in frequency than the pole associated with the output of the 1 output stage c2 (ro6 ro7 ) .11.11: Two Stage OpAmp with Parasitic Capacitors Shown Explicitly A2: gain across the original bridging capacitor and is. c2 for ﬁg(10) can be determined by examining ﬁgure 4.
9) (4.CHAPTER 4. The OpAmp system can also be thought of as a simple second order linear control system with the phase margin directly aﬀecting the transient response of the system. DIFFERENTIAL INPUT STAGE vo = gm6 · (ro6 vo1 ro7 ) 1 1+ S c2 ·(ro6 ro7 ) 57 vo1 = gm1 · (ro2 ro4 ) · vid 1+ Therefore.8) 1 c1 · (ro2 ro4 ) 1 c2 · (ro6 ro7 ) (4. It is recommended for stability reasons that the phase margin of any ampliﬁer be at least 45o (60o is recommended). the frequency response vo = [gm6 · (ro6 ro7 )] · [gm1 · (ro2 ro4 )] vid · And the poles are: P1 = P2 = 1 1+ S 1 S c1 ·(ro2 ro4 ) c1 ·(ro2 ro4 ) · 1 (1 + S c2 ·(ro6 ro7 ) (4. Phase margin measurement procedure with the Cadence design tool.10) 4. From the Aﬃrma window: Result → direct plot → AC magnitude and phase . the phase margin can be measured by applying the following steps: 1. Obtain the AC response simulation 2. Delete all the outputs in the Aﬃrma window 3.4 Phase Margin The phase margin is the diﬀerence between the phase at the frequency at which the magnitude plot reaches 0dB and the phase at the frequency at which the phase has shifted −180o . 4. A phase margin below 45o will result in long settling time and increased propagation delay. Select the AC response curve (it will turn to yellow).
Figure 4.CHAPTER 4. Split the graphs.13 Keeping in mind that the two poles of the system without compensation as determined previously are: P1 = 1 c1 · (ro2 ro4 ) .5 Compensation The goal of the compensation task is to achieve a phase margin greater than 45o . You will get the magnitude and the phase frequency response. DIFFERENTIAL INPUT STAGE 58 5. Now we will include Cc and the model will be as in Figure 4. Follow the prompt at the bottom of the schematic window and select the output node 6.12: Miller Phase Margin Measurement 4. From the Aﬃrma window : output → to be plotted 7.
Cc will dominate the value of c1 and will cause the pole P1 to roll oﬀ much earlier than without Cc to a new location. r2 = ro6 ro7 . The eﬀective capacitance shunting ro2 ro4 is increased by the additive amount of approximately gm1 · ro2 ro4 · Cc . This moves P1 down by a signiﬁcant amount. DIFFERENTIAL INPUT STAGE 59 Figure 4.CHAPTER 4. vo = vid 1 + S [r1 (c1 + Cc ) + r2 (c2 + Cc ) + gm6 r1 r2 ] + S 2 r1 r2 [c1 c2 + Cc (c1 + c2 )] (4. 2. Let r1 = ro2 ro4 . P2 is moved to a higher frequency.13: Model Used to Determine the Frequency Response of the TwoStage OpAmp P2 = 1 c2 · (ro6 ro7 ) Two results come from adding the compensation capacitor Cc : 1.11) A general second order polynomial can be written as: P (S) = 1 + aS + bS 2 = If  P2   P1  then: P (S) = 1 − 1− S P1 1− S P2 =1−S 1 1 + P1 P2 + S2 P1 P2 gm1 gm6 r1 r2 1 − S gCc m6 S2 S + P1 P1 P2 .
To avoid the eﬀect of RHP zero. The RHP zero is located at: Z1 = gm6 Cc (4. P1 .CHAPTER 4.13) This RHP zero has negative consequences on our phase margin. DIFFERENTIAL INPUT STAGE Therefore. b as: P1 = P2 = −1 a 60 −a b The key in this technique is the assumption that the magnitude of the root P2 is greater than the magnitude of the root P1 P1 = −1 r1 (c1 + Cc ) + r2 (c2 + Cc ) + gm6 r1 r2 Cc P1 ∼ = P2 = − −1 gm6 r1 r2 Cc r1 (c1 + Cc ) + r2 (c2 + Cc ) + gm6 r1 r2 Cc r1r 2(c1 c2 + Cc (c1 + c2 )) P2 ∼ = −gm6 Cc c1 c2 + c 2 C c + c 1 C c ∼ gm6 P2 = − c2 (4.12) The second pole should not begin to aﬀect the frequency response until after the magnitude response is below 0dB. one must try to move the zero well beyond the point at which the magnitude plot reaches 0dB (suggested rule of thumb: factor of 10 greater) 4. P2 may be written in terms of a. causing the phase plot to shift −180o more quickly.6 Adding Rz in series with Cc 1 Cc 1 gm6 One remedy to the ”zero problem” is to add a resistor Rz in series with Cc Z1 = (4. It is of interest to note that a zero occurs in the righthandplane (RHP) due to the feed forward path through Cc .14) − Rz .
DIFFERENTIAL INPUT STAGE 61 And the zero can be pushed into the LHP where it adds phase shifts and increases phase margin if: 1 (4. One should be careful about using Rz . Conclusions: P2 should be > GBW Therefore. the most eﬃcient way to increase GBW is to decrease C c .2 Cc Therefore. to know the value of Cc : 1.2 · W1. As Rz increases in 1 value.2 L1. 4. The value of Cc must be large enough to aﬀect the initial rolloﬀ frequency as larger Cc improves phase margin. since the absolute values of the resistors are not well predicted. that value of the zero is always 10 times greater than the gain bandwidth product. The value of the resistor should be simulated over its max and min values to ensure that no matter if the zero is pushed into the LHP or RHP. the zero gets pushed to inﬁnity at the point at which Rz = gm6 .2 L1. GBW = gm1 r1 gm6 r2 · 1 gm6 r1 Cc r2 (4.16) 1 2 gm1 GBW ∼ = Cc GBW ∝ ID1. 1 Once Rz > gm6 .2 and then solving for gm6 c2 > gm1. Cc > C 2 · W1. We need to know the GBW speciﬁcation.CHAPTER 4.15) Rz > gm6 The zero location is in the RHP. 2.2 and ID1. This type of compensation is referred to as lead compensation and is commonly used as a simple method for improving the phase margin.2 Cc gm1. Iteratively choosing the values for Cc .17) . when Rz = 0. Thus improving the phase margin.2 gm6 (4. the zero appears in the LHP where its phase shifts adds to the overall phase response. Therefore.7 Gain Bandwidth Product GBW for the compensated OpAmp is the open loop gain multiplied by the bandwidth of the ampliﬁer (as set by P2 ).
we may then perform AC analysis. then in order to achieve a 45o phase margin. 4. so c2 = cL gm1. Figure 4. And to get a phase margin of 60o P2 must be 2.8 Large Signal Consideration Analysis and design can be greatly simpliﬁed by separating DC or bias calculations from small signal calculations. VDS ≥ (VGS − Vt ) And the drain saturation current is given by: ID = W 1 · Kn · · (VGS − Vt )2 2 L .22 times higher than GBW.2 times greater than GBW. For example if the zero is 10 times larger than GBW.2 (4. The model for pchannel CMOS is similar except for Kp instead of Kn . That is once a stable operating point has been established and all DC quantities are calculated. DIFFERENTIAL INPUT STAGE 62 Practically speaking.14: LargeSignal Equivalent Circuit Model in Saturation For Nchannel MOSFET to be in saturation: 1.CHAPTER 4. the load capacitor usually dominates the value of c2 . Figure 4. VGS ≥ Vt 2.18) Cc > c L · gm6 Therefore. P2 must be least 1. the eﬀect of cL on phase margin is as follows: Minimum size of Cc directly depend on the size of cL .14 shows the large signal equivalent circuit model for nchannel MOSFET in saturation.
the tradeoﬀ issues again come into play.19) 1 · β (VGS − Vt )2 2 For Pchannel MOSFET to be in saturation: 1. For this particular ampliﬁer. and output signal swing 4. Now by substituting VGS : 2.CHAPTER 4. However. . ID = (4. DIFFERENTIAL INPUT STAGE If β = Kn · W L 63 Then. the maximum output voltage is ultimately limited by how fast the tail current device M5 can charge and discharge the compensation capacitor. If Cc is made too small then the phase margin may decrease below an acceptable amount. VDS ≥ (VGS − Vt ). VGS ≤ Vt 2. If ID5 is increased too much. slew rate. the diﬀamp is the major limitation when considering slew rate.20) The large signal characteristics that are important include the Commonmode range. VDS ≥ 2ID β 1 2 1 2 2ID β + Vt (4.19 can be written as: VGS = For the Nchannel: 1. the slew rate can then be approximated as: dVo dt ID5 SR ≈ Cc SR = Typically. VDS ≤ (VGS − Vt ) Equation 4. the gain of the diﬀamp may decrease below a satisfactory amount.9 Slew Rate The slew rate is deﬁned as the maximum rate of change of the output voltage due to change in the input voltage.
2 − VGS1. the gain drops considerably because the commonmode voltage forces one or more devices into the triode region.20 and Vt3 = −ve value because it is p type CMOS: VG1 ≤ VDD − Now since ID3 = 1 ID5 : 2 VG1 ≤ VDD − VG1 ID5 β3 1 2 2ID3 β3 1 2 − Vt3 + Vt1 − Vt3 + Vt1 1 2 (4.15. VG1 ≤ VDD − VG3 + Vt1 Substitute the value of VGS from equation 4.2 − Vt1 ) Now: VD1 = VDD − VSG3 Therefore.10 The CommonMode Range Commonmode range is deﬁned as the range between the maximum and minimum commonmode voltages for which the ampliﬁer behaves linearly. Referring to 4. The maximum commonmode voltage is limited by both M1 and M2 going into triode.CHAPTER 4. there will be a range for which the ampliﬁer will behave normally and where the gain of the ampliﬁer is relatively constant.2 . DIFFERENTIAL INPUT STAGE 64 4. If the common mode voltage is swept from ground to VDD .21) L3 ID5 ≤ VDD − W3 K 3 − Vt3 + Vt1 (4. suppose that the common mode voltage is DC value and that the diﬀerential signal is also shown. Above or below that range.22) The minimum voltage is limited by M5 being driven into nonsaturation by the commonmode voltage source.2 ≥ (VG1. VD5 ≥ VSS + VG5 − Vt5 VD5 = VG1. This point can be deﬁned by a borderline equation in which (For M1. M2 to stay in saturation) VD1.
VGS = Therefore.2 ≥ VSS + VG1.2 ≥ VSS + 1 2 + Vt1 1 2 2L5 ID5 + W5 K 5 L1 ID5 + W1 K 1 + Vt1 (4. 2ID β 1 2 65 + Vt (From 4. Figure 4.15). DIFFERENTIAL INPUT STAGE Therefore. VG1.2 ≥ VSS + VG5 − Vt5 + VGS1.CHAPTER 4.2 − VGS1.15: Determining the CMR for the TwoStage OpAmp .23) Determining the CMR for the twostage OpAmp (Figure 4.2 Since.20) 1 2 1 2 VG1.2 ≥ VSS + 2ID5 β5 + 2ID5 β5 ID5 β1 1 2 + Vt5 − V t5 + Vt1 ID5 β1 1 2 VG1.2 ≥ VSS + VG5 − Vt5 VG1.
W7 to W5 . M4 can be determined in terms of W5 .5KP W 3.5Kn L 5 (Vgs5 − Vt ) Kn W L 3. Using 16: KP 0. If a large capacitance is present. We wish to.CHAPTER 4.11 Important Relationships for The Design Relate W3 .12 Tradeoﬀs for Increasing the Gain of the Two Stage OpAmp.4 W L 5 And since L3 = L5 and Kn = 3Kp. then that leads to the conclusion that: W3.24) Therefore.5W5 (4. Using the equations in the summary above.25) 4.. the width of M3. the width of M6 and M7 will need to be large so as to provide enough sinking and sourcing current to and from the load capacitor. DIFFERENTIAL INPUT STAGE 66 4..4 Vgs3. Increase DC gain Thus we could. M4 carry half of Itail . Then: W7 = 2W5 W6 = 6W5 (Because W6 is PType so to account for the diﬀerence K values) (4. then the widths of M3 and M4 can be determined by assuming that vsg3 = Vsg4 = Vgs5 . Increase W L1. The values for M6 and M7 are determined by the amount of load capacitance attached to the output.2 Some Secondary eﬀects are..4 = 1.. Increase GBW Increase CMR Decrease SR Increase CMR Increase CMRR Increase phase margin Increase phase margin Increase output swing Decrease output currents drive Decrease phase margin Decrease phase margin Decrease ID5 Increase W L6 Decrease ID6 . W4 to W5 M3. Relate W6 . Suppose it was decided that the current needed for M6 and M7 was twice that of M5...4 L ≈ = W Id5 0. the tradeoﬀ issues for increasing the gain of the two stage OpAmp are summarized in the following table.4 − Vt2 Id3.
. The value used is 350nm 3. It is important that before any AC analysis is performed. the values of the DC points in the circuit be checked to ensure that every device is in saturation. for the best dc response.etc. The analysis rather guides the designer’s thoughts and while doing the design and helps to make the results of the design tool make sense.CHAPTER 4. Output Load.35 CMOS Technology is used. Failure to do so will result in very wrong answers. Supply voltage: 0 → 3.3 V Operating temperature: 0 to 70o C. The following design methodology is developed for the two stage OpAmp analyzed above. Design the devices sizes for proper dc performance. Cox . K . Boundary conditions The TSMC 0. This step is accomplished as follows: (a) Calculate the minimum value for the compensation capacitor Cc . Gain. Process speciﬁcations: Vt . Cc . Vin (max).22 CL .13 Design Methodology for the Two Stage OpAmp Design methodology is a topology dependent subject and it is highly dependent on the analysis of the circuit. Rz . 2. Get CL from the requirements (b) Get the slew rate from the requirement and then calculate the minimum value for the tail current ID5 from: ID5 = SR. or CL . Output voltage swing: Vout (max). Vout (min). Oﬀset. 1. GBW. set the speciﬁcations. PSRR. Input common mode range: Vin (min). and deﬁne the boundary conditions. Design the two stages without Cc . CMRR Slew rate. . To deﬁne the requirements. Because there are 12 models for NFET and 12 models for PFET automatically selected within Cadence tool so the process parameters cannot be determined at this stage. DIFFERENTIAL INPUT STAGE 67 4. From 40: Cc 0. The purpose on the design tool is not to replace the analysis completely. Requirements. Choose the smallest length that will keep the channel modulation parameter ( constant and give good matching for current mirrors.
4. iv.2 . Knowing K for the devices is now important to calculate VG (min) and VG1 (max) to make sure that M1. Increase the gain by increasing the size of W1.. particularly on the phase margin which can not be measured till the ac analysis is performed.9µm for p type devices.CHAPTER 4.. To get the desired value of ID5 calculated in B. vi. . M4 and M5 are not operating near the boundary. M2.etc.5W5 W6 = 6W5 W7 = 2W5 ii. and M7) to make sure that the devices are in saturation. 4. Now try to optimize the OpAmp for maximum gain by: i. If any of the devices are brought out of saturation or are working at the minimum condition required for saturation. Get the circuit to work and test the DC response. At this point you can extract the process parameters: Vt . because of the trade oﬀ issues and the secondary eﬀect. Repeat 14 until all the transistors are in saturation while the dc gain is increased. Cox .22.23 causing one of the devices to operate outside the saturation region. M6. v. M2.2 at this point even you may get high gain. Measure the existing ID5 . You may perform parametric analysis for diﬀerent width size. K. simultaneously change W5 and the width of the related devices: W3. 1. M4. M5. M3. Check the operating points of all the devices (M1. DIFFERENTIAL INPUT STAGE 68 (c) Using cadence design tool. All design parameters can be known from Cadence by doing the following: Aﬃrma Window: Results → Print → DC Operating Points iii. You can not decide on the ﬁnal value of W1.4 = 1. M3. simulate the two stage ampliﬁer with starting widths of: 800nm for n type devices. (d) Measure ID5 . then it should be brought back to saturation.
Perform DC analysis only and return back to Step3D. Substitute the last value of Cc and the required SR. ii. Figure 4. referring to (4. with the desired value of ID5 as calculated above.16 shows a two stage opamp designed using the above design methodology and optimized for maximum gain. (e) Calculate the slew rate according to the new Cc value that makes the phase margin > 45o .18).18 shows the frequency response.CHAPTER 4. 4. P2 and the phase margin. 4. GBW.15. The value of CL is from the speciﬁcations while the value of Cc is previously calculated in Step3A (b) Check the phase margin condition (4.18). A parametric analysis may be preformed for diﬀerent Cc sizes. Compare with the required speciﬁcations. (c) Verify that the phase margin is > 45o by measuring it using the procedure in 44. 6. If it is less than the speciﬁcation then perform the following steps: i. Measure the slew rate. Check the diﬀerence in the phase response. . (a) Add up Cc and CL to the ampliﬁer.14) (b) Add Rz to the circuit and perform an AC analysis.17 shows the gain for the large signal consideration(DC response).14 Design Example Figure 4. Calculate the required ID5 from (22). Figure 4. (d) If the phase margin is not > 45o then it should be corrected by changing the value of Cc or R2 . as now you can know all the process parameter from cadence. 4.19 shows the phase margin measurements. DIFFERENTIAL INPUT STAGE 69 (e) Measure the CMR and the gain. 5. (a) Calculate the required Rz using (4. Figure 4. Compare with the speciﬁcations.
17: Gain for the Large Signal Analysis .CHAPTER 4. DIFFERENTIAL INPUT STAGE 70 Figure 4.16: TwoStage OpAmp using design Methodology Figure 4.
CHAPTER 4. DIFFERENTIAL INPUT STAGE 71 Figure 4.18: Frequency Response Figure 4.19: Phase Margin .
the third is the more attractive way because the output resistance increases in proportion to a decrease current [ ro = 1/λ ].21 shows the DC response for an unoptimized conﬁguration to serve as indication for the whole project and to help in deciding about the best input stage to be considered in the ﬁnal opamp design. The transistors Mc1 and Mc2 perform the resistance multiplication. whereas the transconductance increases as the square root of the increase in bias current [ gm = (2 ∗ B ∗ ID )1 /2]. Increase the transconductance of the ﬁrst or the second stage. Rout ( [gmc2 . Mc1. A = gm1. Further more. Figure 4. Increase the output resistance seen by the ﬁrst or second stage. ro2 ]. Figure 4. 3. which helps to reduce the voltage oﬀset.CHAPTER 4. ro4 ] —— [ gmc1. Thus it is generally more eﬃcient to increase ro rather than gm .Rout One of the disadvantages of this design is the requirement for the additional bias voltages VB1 . VB2 . Add additional gain stage 2. the ﬁrst approach is not attractive. DIFFERENTIAL INPUT STAGE 72 4.15 Limitations of the Two Stage OpAmp 1. while Mc3 is used to keep the drain voltage of the input transistor matched. Limited stable bandwidth caused by the instability to control the higher order poles of the opamp. the CMR limitation is not important since the noninverting input of the opamp will be connected to ground. In many cases. the common mode input range is reduced due to the extra voltage drop required by the two cascode devices. roc1. Poor power supply rejection ratio. Of the latter two approaches. roc2 . There are three ways in which the gain of the two stage opamp could be increased: 1.20 shows a cascode diﬀerential stage. Insuﬃcient gain 2. 4. Mc2. Due to possible instability. 3.16 The Cascode OpAmp The motivation for using the cascode conﬁguration to increase the gain can be seen by examining how the gain of the twostage opamp could be increased. .
The folded cascode circuit is frequently used as a singlestage opamp. Figure 4. roc2. roc1(ro6——ro2)] —— [ gmc2.23 shows the DC response for an unoptimized conﬁguration to serve as indication for the whole project and to help in deciding about the best input stage to be considered in the ﬁnal opamp design.CHAPTER 4. This requires two additional transistors (M5 and M6). the input commonmode range is larger because only three transistors are now stacked in the input chain between the two power supplies (as compared to ﬁve in the conventional cascode circuit). operate in much the same manner as the previous cascode circuit. Here however. Its voltage gain can be determined as: A = gm1 Ro Where Ro is the output resistance: Ro = [ gmc1. DIFFERENTIAL INPUT STAGE 73 Figure 4. This circuit uses a currentfolding circuit technique to permit direct connection of the drains of the pchannel diﬀerential ampliﬁer to the sources of the cascode devices. ro3)] .20: Cascode Diﬀerential Stage Folded Cascode OpAmp Figure 4.22 shows a folded cascode diﬀerential stage.
21: DC Response for Unoptimized Circuit Figure 4.CHAPTER 4. DIFFERENTIAL INPUT STAGE 74 Figure 4.22: Folded Cascode Diﬀerential Stage .
CHAPTER 4.23: DC Response for Unoptimized Circuit . DIFFERENTIAL INPUT STAGE 75 Figure 4.
the inverter has three kinds of conﬁgurations. The second one uses a current sources/sink as an active load. The ﬁrst one uses the commonsource conﬁguration with an active resistor as a load. It is usually used as the basic gain stage for CMOS circuits. we introduce an important conﬁguration that is extensively employed in the design of integrated circuits: the inverting ampliﬁer. 76 .Chapter 5 Inverting Ampliﬁers In this section. smallsignal voltage gain. the three conﬁgurations will be discussed respectively in terms of their output swing. input and output resistance and 3 dB frequency. In this section. The third one uses the input voltage to control both the amplifying transistor and the load transistor. Later we will see that inverter is used in the gain stage of the ﬁnal circuit. The inverting ampliﬁer is also called commonsource ampliﬁer or inverter. Typically. this conﬁguration is also known as pushpull ampliﬁer.
7µA Under these conditions. Id1 = 106. Vds1 = 1. VSS = 0V .65V . This circuit uses a commonsource.3V.1.6µA/V 2 . W2 = 28µm. L1 = 10µm.5V .365V Vds2 = Vgs2 = −1.1: Simple Inverter Circuit The parameters of the circuit are as follows: VDD = 3. we have: β2 = µP Cox W2 = 148.65V and DC current at 106. We set the operating point at 1.1 Inverter with Active Resistor Load The typical circuit of the ﬁrst type has been shown in Figure 5.7µA.2µA/V 2 . Thus we can calculate β1 and β2 which we will need for future calculations. INVERTING AMPLIFIERS 77 5. Since Id1 = 106. Id2 = −106. so Vgs1 = 1.9µA/V 2 2L1 Use the same way. L2 = 10µm. W1 = 10.8µm.9µA/V 2 L2 .7 · 10−6 = µN Cox W1 (Vgs1 − VT N )2 2L1 µN Cox W1 (1. Kp = µP Cox = 52. Nchannel transistor M1 with a Pchannel transistor M2 as the load of M1. Kp = µp Cox = 52.5)2 2L1 So β1 = µN Cox W1 = 171. VT P = −0.7µA.65 − 0. Figure 5. VT N = 0.7V .CHAPTER 5.935V .
Figure 5. This plot shows the Id versus Vds characteristics of M1 and the ”load line” plotted on the same graph.CHAPTER 5.3: VoltageTransfer Curve From these ﬁgures.2: Inverter Type 1: Parametric Analysis sweeping Vin Figure 5.3. . Transfer Characteristics 78 Figure 5.2 illustrates the Cadence simulation result of the largesignal characteristics of this circuit. The voltagetransfer curve is shown in Figure 5. we can observe that this type of inverting ampliﬁer has low gain since the slope of the Vout versus Vin is small. INVERTING AMPLIFIERS 1.
With the gate and drain connected together.5 1+ 148.5 − VDD − VSS − VT 1+ 3. Output Swing 79 From these curves.3.3 − 0. and Vds2 = Vgs2 = VT P  + 2Id2 . This is the region where the minimum output voltage happens. M1 enters nonsaturated region. So Vout (max) is approximately equal to: Vout (max) = VDD −  VT P = 3. INVERTING AMPLIFIERS 2. Since M1 is in nonsaturated region. We will ﬁnd the maximum output voltage and minimum output voltage.7 V You may notice that in Figure 5. This is called subthreshold eﬀect. it is obvious that this inverter has limited output voltage range (point A and point B in Figure 5. and Id has an exponential relationship with Vds at this region.7 = 2. M1 enters saturated region. M1 conducts.3 − 0. and the drain current of M1 β2 Id1 is also zero.6 β2 β1 = 0.2). Vout (min) ≈ VDD − VT − = 3. It is this .CHAPTER 5. the drain current of M1 should be: Id1 = β1 (VDD − VSS − VT N )(Vout − VSS ) − (Vout − VSS )2 2 Because M2 is in saturated region. and Vout begins to drop. This is because the subthreshold eﬀect of transistors. M2 always works in the saturated region as long as  Vds2 > VT P . there is current conducting through transistors when Vin < VT N . the Vout (max) is around 3V. Vds2 = VT P . the drain current of M2 should be: Id2 = β2 (VDD − Vout −  VT P )2 2 Equating the above two equations.6(V ) When Vin increases until Vin > VT N .2 171. different from our calculation. When Vout further drops until Vout < Vin − VT N . When Vin is zero. We usually suppose that no current ﬂows in transistors when Vin < VT N . M1 is cutoﬀ. When Vout > Vin − VT N . and simplifying VT N = VT P = VT in order to simplify the calculation. We can get the approximate value of Vout (min). But in reality.3 − 0.
we have ∂Vout AV = =− ∂Vin β1 β2 1 2 =− 1 KN W1 L 1 2 K P W2 W1 (b) Another method to ﬁnd AV is from the smallsignal model. The smallsignal model of the inverter with an activeresistor load is shown in Figure 5.4. Because AV is the derivative of Vout Vin . Id1 is: Id1 = β1 (Vin − VSS − VT N )2 2 and since M2 always operates in saturation. and the drain current of M1 and M2 are always equal.CHAPTER 5. Id2 is: Id2 = β2 (VDD − Vout − VT P )2 2 Equating the above equations. (a) The principle of the ﬁrst method is this: the gain is found when M1 works in saturated region. Figure 5.4: Inverter: SmallSignal Model The gain can be expressed as: vout −gm1 ∼− AV = = = vin gds1 + gm2 + gds2 1 KN W1 L 2 KP W2 L 1 2 . Therefore. INVERTING AMPLIFIERS 80 eﬀect that results in the diﬀerence between our calculation and the simulation result. There are two methods to calculate the smallsignal voltage gain. SmallSignal Voltage Gain. 3.
C1 = Cgs1 C2 = Cbd1 + Cgs2 + Cbd2 C3 = Cgd1 gout r1 = rin = ∞ Using nodal analysis. Input and Output Resistance From the smallsignal model.1. so AV = −1. Upper 3 dB Frequency When discussing the frequency response of the inverter. The resulting low output resistance can be very useful in situations where a large bandwidth is the main expectation from an inverting gain stage. We get the same results from the two methods. we can either increase the ratio of W1 or decrease the ratio L 2 of W2 .5 · 10−6 We can see that the output resistance of the activeresistor load inverter is low because of the diodeconnected transistor M2. we may write: Vout (s)(gout + sC2 ) + C3 [Vout (s) − Vin (s)] + gm Vin (s) = 0. Figure 5. So this type of inverter is suitable for situations where lowgain inverting stage is desired. which is a fairly low gain. where s = jω r2 = rout = 1 .CHAPTER 5. we need to take the internal capacitors into consideration. gm2 = 155. INVERTING AMPLIFIERS 81 where gm2 gds1 . gds2 . According to the Cadence simulation result.4 kΩ = gds1 + gm2 + gds2 gm2 155. L 4. we can ﬁnd that the input and output resistance is rin = ∞ rout = 1 1 ∼ 1 = = 6. gm1 = 172µ. Besides. we can see from the AV expression that in order to improve the 1 gain.5µ.5 illustrates the resulting smallsignal model. 5.
we can increase the drain current because rout will decrease. So in order to increase the bandwidth.CHAPTER 5. Simulation results of the frequency response of the activeresistor load inverter is shown in Figure 5. Lacking of accurate values of these capacitors. So the 3 dB frequency can be written as: ωH = gm2 + gds1 + gds2 gout = C2 + C 3 Cdb1 + Cgd1 + Cgs2 + Cdb2 (5. But it still can be found from the frequency response because 3 dB frequency is the point where the gain drops to 0. we determine the 3 dB frequency to be 26.5: Inverter: SmallSignal Model So the transfer function Vout (s) Vin (s) is: C3 gm (C2 +C3 ) gout AV (s) = − gm 1 − s gout 1 + s = AV M 1− 1+ s Z1 s P1 (5. .1) where AV M is the midband gain. we can get to the conclusion that the 3 dB frequency of the active resistor load inverter is approximately proportional to the square root of the drain current. we cannot calculate an accurate value of the 3 dB frequency. Z1 is the zero and P1 is the pole and AV M = − −ggm1 gm1 gm1 −gout = .6. Z1 = . we ﬁnd that inverter has a ﬁrstorder transfer function. which is a fairly wide bandwidth. Unfortunately. this will also decrease the gain. P1 = gout gds1 + gm2 + gds2 C2 C2 + C 3 From this formula.12MHz. INVERTING AMPLIFIERS 82 Figure 5.2) From this equation. From this curve.707AV .
Id1 = 106.0µA/V 2 2L We can calculate out: W1 = 10. From Id = µCox W (Vgs − VT )2 . i.8µm. current mirror. KN = 158.65V .7µA. In order to compare the performances of this type with the ﬁrst one.9µA/V 2 .935V . W4 = 18.7. L1 = 10µm. The circuit is shown in Figure 5. INVERTING AMPLIFIERS 83 Figure 5.CHAPTER 5. Here we will use current mirror. W2 = 28µm.5µm. KP = 52. such as cascade current sink. L2 = 10µm.7µA. Id2 = −106.e. Id3 = Id4 = 106.7µA. L4 = 10µm . W3 = 28µm. There are a number of ways to conﬁgure active load. reduced cascade current sink and so on. Vgs1 = 1.2 Inverter with Current Source/Sink Load The second type of inverter uses active load.6: Frequency Response of the ActiveResistor Load Inverter 5. L3 = 10µm. Vgs2 = −1. set the operating point the same as the ﬁrst one.
CHAPTER 5. Output Swing. The largesignal characteristics and voltagetransfer curve are respectively shown in Figure 5. Figure 5.9. INVERTING AMPLIFIERS 84 Figure 5.8 and Figure 5.7: Inverter Circuit with Current Source/Sink Load 1.8: Inverter Type 2: Parametric Analysis sweeping Vin .
Basically. The transfer curve is almost linear and very steep. In segment 2. This limitation can be found by a method similar to that used for the active resistor inverter. In segment 4. we can divide the transfer curve into four distinct segments. M1 begins to conduct. we can ﬁnd that this type of inverter still experiences the limitation for output swing(point A in Figure 5. So Vout (max) is equal to VDD since M2 can pull output voltage up to VDD . Vin < VT N . Vout dropped quickly. but there is no current. This is the segment where Vout (min) happens. In segment 1. Vin increases to Vin > Vout + VT N . In segment 3. and Vout decreases as Vin increase. making both M1 and M2 operates in saturation. and M1 enters nonsaturation region. M2 works in nonsaturation region. INVERTING AMPLIFIERS 85 Figure 5. and the lower limit can be found when M1 is in the nonsaturation . M1 is cutoﬀ. Vin increases to Vin > VT N .CHAPTER 5. M2 is conducted. From the above analysis.9: VoltageTransfer Curve Observing these curves. indicating large voltage gain. we can see that Vout (max) = VDD = 3.3 V .8). Vin further increases.
CHAPTER 5. This occurs because the output conductance rds1 and rds2 is inversely proportional to the current whereas the transconductance gm1 is proportional to square root of the bias current.5 2 1 2 (5.3) The smallsignal voltage gain can be found from its smallsignal model Figure 5.365 − 0.3 V 2. Figure 5. INVERTING AMPLIFIERS region.3 − 1.10: Inverter Type 2: Small Signal Model Vin The gain can be expressed as AV = Because gds1 vout −gm1 = −gm1 (rds1 rds2 ) = vin gds1 + gds2 √ = λ1 Id . 86 VDD − (VDD − Vgs2 ) −  VT P  VDD − VT N 1 2 2 3.10.gds2 = λ2 Id and gm1 = 2β1 Id AV = − 2µN Cos W1 L1 Id 1 λ1 + λ 2 Here we notice a signiﬁcant result.2 = (3. The gain increases as the DC operating current decreases.7 3. So we can increase the gain of this type of inverter by decreasing .7 = 0.5) 1 − 1 − 171.3 − 0. Vout (min) can be written as β2 Vout = (VDD − VT N ) 1 − 1 − β1 148. SmallSignal Voltage Gain.3 − 0.
11. we measure the 3 dB frequency is 3.5. . But you will see soon that the high output resistance results in a narrow bandwidth. we can see that under the same biasing conditions.6 gds1 + gds2 392. From the smallsignal model. the pushpull CMOS inverter is achieved.8M Ω −9 + 855.3µ. INVERTING AMPLIFIERS 87 the biasing current Id . If the gate of M2 in Figure 5. gds1 = 855. The frequency response can be found by using Figure 5.3 PushPull Inverter One of the disadvantages of the current source inverter introduced above is that it requires a biasing voltage. In this circuit. gm1 = 172. which is a lower frequency compared to the active resistor load inverter. This is due to the higher output resistance. 3 dB Frequency. we can ﬁnd that the output resistance is rout = 1 1 = = 0. Output Resistance. so AV = − 172. According to the Cadence simulation result. gds1 = 392.3n.CHAPTER 5. But in this case.7 is taken to the gate of M1.9 · 10−9 3.3 · 10−9 + 855.3 · 10 From these calculation results. 4.9n. From this curve. this current source load inverter has a much higher gain and output resistance when comparing to the active resistor load inverter.4) Simulation result of the frequency response of this inverter is shown in Figure 5.3 · 10−6 gm1 =− = −137. C is C1 = Cgs1 + Cgs2 C2 = Cdb1 + Cdb2 C3 = Cgd1 + Cgd2 So 3 dB frequency is ωH = gout gds1 + gds2 = C2 + C 3 Cdb1 + Cgd1 + Cgd2 + Cbd2 (5.9 · 10−9 gds1 + gds2 392. 5.75MHz.
Id2 = −106. Id1 = 106.9µA/V 2 . Vgs1 = 1. Still. KN = 158.65V .11: Frequency Response of the Inverter with Current Source/Sink Load Figure 5. like the above two circuits.CHAPTER 5. INVERTING AMPLIFIERS 88 Figure 5.7µA.65V .12.e.65V. KP = 52. The typical circuit is shown in Figure 5.9µA/V 2 2L . Vgs2 = −1. i.12: PushPull Inverter Circuit both biasing and amplifying transistors are driven by the input signal. set the operating point at 1.7µA From Id = µCox W (Vgs − VT )2 .
L1 = 10µm. W1 = 10.CHAPTER 5. Figure 5.13 and Figure 5. Output Swing.14: VoltageTransfer Curve . 89 The largesignal characteristics and voltagetransfer curve are respectively illustrated in Figure 5.1µm. 1. INVERTING AMPLIFIERS We can get.14. L2 = 10µm.13: Inverter Type 3: Parametric Analysis Sweeping Vin Figure 5. W2 = 48.8µm.
7 · 10−9 + 761. First.15.7n. The smallsignal voltage gain can be found from its smallsignal model Figure 5. we can get to the conclusion that the smallsignal voltage gain of pullpull inverter is inversely proportional to the square root of DC current. whereas a current mirror inverter cannot drive all the way to VSS .4 · 10−9 .4n. the output swing of pushpull inverter is capable of operating from VDD to VSS .1µ. This is due to the fact that both transistors are being driven by Vin . SmallSignal Voltage Gain. INVERTING AMPLIFIERS 90 Comparing the largesignal voltage transfer characteristics between the currentmirror and pushpull inverter. we can decrease the DC operating current. According to the Cadence simulation result. gm1 = 2β1 Id and gm2 = 2β2 Id : 1 1 vout gm1 + gm2 (2β1 ) 2 + (2β2 ) 2 √ =− =− vin gds1 + gds2 (λN + λP ) Id (5. gm2 = 208. gm1 = 172.2µ. Second. gds2 AV = vout gm1 + gm2 =− vin gds1 + gds2 √ √ = λ2 Id . This is the same as the current mirror inverter. gds1 = 761.2 · 10−9 vout =− =− = −290.15: Inverter Type 3: Small Signal Model The smallsignal voltage gain can be expressed as AV = Because gds1 = λ1 Id . 2.CHAPTER 5.5 vin gds1 + gds2 547. In order to increase gain. gds1 = 547.5) From this equation. so AV = gm1 + gm2 172.1 · 10−6 + 208. Figure 5. the pushpull inverter will have a higher gain. it is seen that this type of inverter shows two advantages.
and the 3 dB frequency is 2. Output Resistance and 3 dB Frequency ωH . rout = 547. 3. we can ﬁnd that the output resistance and 3 dB frequency are the same as the current mirror inverter. which are 1 rout = gds1 + gds2 and ωH = In this case.4 · 10−9 gds1 + gds2 gout = C2 + C 3 Cbd1 + Cgd1 + Cgd2 + Cbd2 Simulation result of the frequency response of the pushpull inverter is shown in Figure 5.76 M Ω + 761. pushpull inverter has a much higher gain than the other two types.16: Frequency Response of the PushPull Inverter . From the smallsignal model.CHAPTER 5. INVERTING AMPLIFIERS 91 This result shows that under the same DC current.98MHz. Figure 5.7 · 10−9 1 = 0.16.
98MHz Operating Point Output Swing Gain Output Resistance 3dB Frequency The comparison shows that under the same DC current.5 0.6 290.6V Vout (min) = 0.3V Vout (min) = 0V 137. Id1 = 1. the active resistor load inverter has the lowest gain but the best bandwidth. The performance of the current source load inverter is between the other two types.17 illustrates the basic conﬁguration of a crossover stage.CHAPTER 5. So this type of inverter is suitable for situations where low gain and wide bandwidth is desired.8M Ω 0.7µA Vout (max) = 3. the second type of inverter is used to make a crossover stage. current source inverter and pushpull inverter. 5. .5 Application In the ﬁnal circuit.8V 1.76M Ω 3. Pushpull inverter has the highest gain and output swing. Type 1 Active Resistor Load Vgs1 Vout (max) = 2. But we all know that this type of inverter may cause crossover distortion. Main performances of the three inverters are concluded in the following table.3V Vout (max) = 3.4 Comparison We have ﬁnished the analysis of the three types of inverters: active load inverter.1 64kΩ 26.75MHz 2. INVERTING AMPLIFIERS 92 5.06.65.3V Vout (min) = 0. The purpose of this stage is to provide gain and drive to the two output transistors. which is a modest gain and output swing. Figure 5.12MHz Type 2 Type 3 Current Source Load PushPull = 1.
18 shows the practical circuit in the our group’s design. M22.CHAPTER 5. Here the current mirror is replaced by reduced cascade current source to bias the inverting ampliﬁer. and it comes from . M24.18: Application 2 In this circuit. Figure 5. M25. Figure 5. INVERTING AMPLIFIERS 93 Figure 5. the two inverters consisting of M1. M23 and M10. M3 and M2. the crossover stage is achieved with transistors M9.17: Application 1 In this diagram. M4 are the crossover stage. You can see that these two inverters are the current mirror load inverter introduced above.
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94
our biasing subcircuit. The input of the inverters is from the ﬁrst stage, i.e. diﬀerential stage. The output of the ﬁrst inverter consisting of M9, M22, M23 will drive transistor M11 of the output stage, and the second inverter consisting of M10, M24, M25 will drive M12 of the output stage. The performance of the two inverters is similar to that of the current mirror load inverter introduced above. This is the speciﬁc application of the current source load inverter. This stage can provide high gain for the circuit. It’s high input and output resistance make it match well with both the diﬀerential stage and the output stage.
Chapter 6
Control Network and Output Stage
The primary objective of the CMOS output stage is to function as a current transformer. Most output stages have a high current gain and a low voltage gain. The speciﬁc requirements of an output stage might be: 1. Provide suﬃcient output power in the form of voltage or current.; 2. Avoid signal distortion.; 3. Be eﬃcient. (The eﬃciency can be deﬁned as the ratio of the power dissipated on the load against the power delivered from the supply); 4. Provide protection from abnormal conditions. (Short circuit, over temperature and so on). The second requirement results from the fact that the signal swings are large and the nonlinearity normally not encountered in smallsignal ampliﬁers will become important. The third requirement is born out of the need to minimize power dissipation in the driver transistors themselves compared with that dissipated in the load. The fourth requirement is normally met with CMOS output stages since MOS devices are selflimiting. An important function of the output stage is to provide the ampliﬁer with a low output resistance so that it can deliver the output signal to the load without loss of gain. Since the output stage is the ﬁnal stage of the ampliﬁer, it usually deals with relatively large signals. Thus the smallsignal approximations and models either are not applicable or must be used with care. Nevertheless, linearity remains a very important requirement. In fact, 95
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96
a measure of quality of the output stage is the total harmonic distortion (THD) it introduces.
6.1
Classiﬁcation of Output Stage
Several approaches to implementing the output ampliﬁer will now be introduced here. Output stages are classiﬁed according to the drain current waveform that results when an input signal is applied. For example, in a ClassA ampliﬁer, the transistor conducts for the entire cycle of the input signal, while in a ClassB ampliﬁer, a transistor only conducts for half of the cycle of the input sine wave. And the ClassAB ampliﬁer, involves biasing the transistor at a nonzero DC current much smaller the peak current of the sinewave signal. As a result, the transistor conducts for an interval slightly greater than half a cycle. The resulting conduction angle is greater than 180o but much less than 360o . The ClassAB ampliﬁer has another transistor that conducts for an interval slightly greater than that of the negative halfcycle, and the currents from the two transistors are combined in the load.
6.2
ClassA Output Stage
Here we introduce two kinds of ClassA ampliﬁer output stages:
6.2.1
Simple output ampliﬁer using a ClassA, currentsource inverter
The circuit in Figure 6.1 will reduce the output resistance and increase the current driving capability. The output resistance can also be seen in Figure 6.2.
1: Reduced Output Resistance/Increased Current Driving Circuit. Figure 6. CONTROL NETWORK AND OUTPUT STAGE 97 Figure 6.2: Output Resistance for a ClassA Output Stage. .CHAPTER 6.
Now. 6. So the instantaneous power dissipation in the transistor should . The eﬃciency of the source follower can be shown to be similar to the classA ampliﬁer. the MOS device becomes dependent on the body eﬀect.CHAPTER 6.2 CommonDrain (SourceFollower) Output Ampliﬁer The circuit conﬁguration shown in Figure 6. 2 is selected to allow a maximum negative load current of VDD .3 Power Analysis Next.65V (the absolute maximum value should be VDD ).Source Follower Circuit. The body eﬀect causes the threshold voltage Vt to increase as the output voltage is increased. the drain 2RL current of the upper transistor will swing from 0 → 2I with the quiescent value being I. The distortion of the source follower will be better than the ClassA ampliﬁer because of the inherent negative feedback of the source follower.3: ClassA Output Stage . I. Figure 6. It is seen that two Nchannel devices are used. rather than a Pchannel and an Nchannel. Eﬃciency is deﬁned as the ratio of the power dissipated in RL (load resistor) to the power required from the power supplies. creating a situation where the maximum output is substantially lower than VDD . assuming that the bias current. I. is properly selected the output voltage can swing from 0 to VDD with the quiescent value being 1.2. CONTROL NETWORK AND OUTPUT STAGE 98 6. But since the source is the output node. we see that if the bias current.2.3 has both large current gain and low output resistance.
.5% which means that less quiescent current is needed to meet the outputcurrent demands of the ampliﬁer. This ”Dead Band” results in the crossover distortion. Thus. and Pchannel transistor pulls current from the load when Vin is negative. Note. the ClassA output stage 2 is rarely used in large power applications.3. that in practice the output voltage is limited to lower values in order to avoid transistor saturation and associated nonlinear distortion. the eﬃciency achieved is usually in the 10% to 20% range. Note that there exists a range of Vin centered around zero where both transistors are cut oﬀ and Vout is zero. Because this is a rather low value. the maximum eﬃciency attainable is 25% when 2 Vo = 1 · VDD . The circuit operates in a pushpull fashion: Nchannel transistor pushes current into the load when Vin is positive.2) Since the current in the lower transistor is constant (I).1 ClassB Output Stage PushPull. So the upper transistor must be able to withstand 2 VDD a continuous power dissipation of VDD · I (I = 2∗RL ). Inverting CMOS ampliﬁer The PushPull ampliﬁer (Figure 6.3 6. It is well known that a ClassB. the average load power will be PL = Vo2 2 · RL (6. The average current in the upper 2 transistor is equal to I.1) For the ClassA output stage. the power drawn from the negative supply is VDD · I . 6. The maximum instantaneous power dissipation in the upper transistor is VDD · I . The crossover distortion of a ClassB output stage can be reduced substantially by employing a highgain OpAmp and overall negative feedback. 2 The power conversion eﬃciency of an output stage is deﬁned as Ef f = load power(PL ) supply power(PS ) (6. A more practical method for reducing and almost eliminating crossover distortion is found in the ClassAB ampliﬁer. The output voltage swing is limited to a threshold voltage below VDD and above VSS . Thus. CONTROL NETWORK AND OUTPUT STAGE 99 be: P D1 = Vds1 · id1 .4) has the advantage of better eﬃciency.CHAPTER 6. pushpull ampliﬁer has a maximum eﬃciency of 78. and thus the average power drawn from the positive supply is VDD · I .
.5: ClassB Output Stage .Transfer Characteristics. Figure 6.4: ClassB Output Stage .CHAPTER 6. CONTROL NETWORK AND OUTPUT STAGE 100 Figure 6.PushPull Circuit.
(See Figure 6. π Ef f = load power(PL ) supply power(PS ) It follows that the maximum eﬃciency is obtained when Vo is at its maximum VDD . The result is the ClassAB output stage. Ef f .7). of the ClassB stage. 6.3.2 Power Analysis To calculate the powerconversion eﬃciency.CHAPTER 6.4 ClassAB Output Stage Crossover distortion can be virtually eliminated by biasing the complementary output transistor at a small. we neglect the crossover distortion and consider the case of an output sinusoid 2 Vo of peak amplitude Vo . both transistors conduct. the average current drawn from each of the two power supplies will be Vo · RL . The ClassAB stage operates in much the same manner as the ClassB circuit. nonzero current. and as input is increased or decreased. with one important exception: for small input.6: Output Resistance for a ClassB (and ClassAB) Output Stage. 6. So PL = 2·RL The current drawn from each supply will consist of half sine waves of peak amplitude. . CONTROL NETWORK AND OUTPUT STAGE 101 Figure 6. Thus. The powerconversion eﬃciency is 78.5%. This value is 2 much larger than that obtained in the ClassA stage.
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102
one of the two transistors takes over the operation. Since the transition is a smooth one, crossover distortion will be almost totally eliminated.
Figure 6.7: ClassAB Output Stage Schematic. This type of ampliﬁer is sometimes called an operational transconductance ampliﬁer (OTA). It is very useful in driving capacitive loads. And because it based on a ﬂoating current source, the output voltage can swing from VSS to VDD . And the power relationships in the ClassAB stage are almost identical to those derived for ClassB circuit in the previous section.
6.5
Short Circuit Protection
The circuit shown in Figure 6.8 shows a ClassAB output stage equipped with protection against the eﬀect of shortcircuiting the output while the stage is sourcing current. The large current that ﬂows through M1 in the event of a short circuit will develop a voltage drop across R1 of suﬃcient value to turn M2 on. The drain of M2 will then conduct most of the current Ibias , robbing M1 of its base drive. The current through M1 will thus be reduced to a safe operating level. This method of shortcircuit protection is eﬀective in ensuring device safety, but it has the disadvantage that under normal operation about 0.5V drop might appear across each R. This means that the voltage swing at the output will be reduced by that much, in each direction. On the other hand, the inclusion of the resistors provides the additional beneﬁt of protecting the output transistors against thermal runaway.
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103
Figure 6.8: ShortCircuit Protection Circuit Schematic.
6.6
Conclusion
After having studied several diﬀerent kinds of the output stages, and based on the analysis above, the decision to use the ClassAB output stage was ﬁnal. Again, the most important factors being: 1. It has high powerconversion eﬃciency (Maximum 78.5%). 2. It has low output resistance. 3. It can eliminate the crossover distortion in Class B. Figure 6.9 shows the ﬁnal output stage used; the CrossoverClassB output stage. It can be divided to two stages: one is the normal ClassB stage, the other is the crossover stage. It provides the gain, bias, compensation and drive to the two transistors in the ﬁnal stage. These two stages form the ClassAB stage, and provide good performance. The total harmonic distortion in this circuit is very small, only 0.05%. Figures 6.10, 6.11 and 6.13 show the three main types of analysis performed, AC Response, DC Response and Transient Response, respectively. Harmonic Analysis: The distortion of an ampliﬁer is always identiﬁed by its response to the sinewave input signal. It is generated by the nonlinearity of the ampliﬁer transfer characteristics. So if we know that the input signal is: Vin (ω) = V sin ωt (6.3)
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104
Figure 6.9: Final Output Stage with Crossover + ClassB.
Figure 6.10: AC Response of The Final Output Stage. Then the output distortion should be: Vout (ω) = a1 ·V sin (ωt)+a2 ·V sin (2ωt)+a3 ·V sin (3ωt)+...+an ·V sin(nωt) (6.4) th harmonic distortion (HD) is deﬁned as the magnitude of the i th So the i harmonic to the magnitude of the 1st harmonic. For example, the second a2 harmonic distortion is HD2 = a1 And the total harmonic distortion (THD)
11: DC response of The Final Output Stage.CHAPTER 6. the harmonic distortion of an ideal ampliﬁer should be less than 1.5) Normally. is deﬁned as: a2 + a2 + ..12: Transient Response of The Final Output Stage.. + a2 n 2 3 a1 T HD = (6. Figure 6. .0%. CONTROL NETWORK AND OUTPUT STAGE 105 Figure 6.
Is there a way that could deal with the harmonic distortion when the input signal is increased to get higher output swing? 6. • Control the input and output impedances: that is. CONTROL NETWORK AND OUTPUT STAGE 106 6. 6. For example.2 Frequency Compensation From the bode plot. we know that if the closedloopAmpliﬁer has one or two poles.7. when the magnitude is 100µV . . So if the gain is very high and the input signal is not small enough. But if there are more than 2 poles. All of the above desirable properties are obtained at the expense of a reduction in gain and at the risk of the ampliﬁer becoming unstable (that is oscillating). make the output proportional to the input. it will become unstable. • Reduce nonlinear distortion: that is. make the gain constant independent of signal level. raise or lower input and output impedances by the selection of appropriate feedback topology. If the magnitude of the input signal is increased harmonic distortion will begin to appear. an important phenomena was seen: when the gain is increased the slope is increased and the linear range will decrease.CHAPTER 6.7 Design Considerations While working on the output stage. make the value of the gain less sensitive to variations in the value of circuit components. minimize the contribution to the output of unwanted electric signals generated by the circuit components and extraneous interference. the magnitude of the input signal is 1µ. the harmonic distortion is around 10%.1 Negative Feedback Negative feedback is always employed in the ampliﬁer design to eﬀect one or more of the following properties: • Desensitize the gain: that is. so there is almost no harmonic distortion. there will be harmonic distortion. • Extend the bandwidth of the ampliﬁer. • Reduce the eﬀect of noise: that is. it is stable because the maximum phase shift of output is always less than 180 degrees. In the ﬁnal circuit. such as variations that might be caused by the changes in temperature.7.
13: Phase of the Crossover Output Stage. we must use the frequency compensation. The gain margin represents the amount by which the loop gain can be increased while stability is maintained.CHAPTER 6. On the other hand. And there are two parameters that are very important in the feedback ampliﬁer design: gain margin and phase margin. A popular method for frequency compensation involves connecting a feedback capacitor to an inverting stage in the ampliﬁer. Figure 6. Feedback ampliﬁers are usually designed to have suﬃcient gain margin to allow for the inevitable changes in loop gain with temperature. And feedback ampliﬁers are normally designed with a phase margin of at least 45o . This process is known as pole splitting. So in order to keep it stable. . for a stable ampliﬁer. CONTROL NETWORK AND OUTPUT STAGE 107 That means the ampliﬁer will oscillate. the phase lag must be less than 180o . while the pole formed at the output of the ampliﬁer stage is moved to a very high frequency and thus becomes unimportant. time and so on. The amount of phase margin has a profound eﬀect on the shape of the closeloop magnitude response. This causes the pole formed at the input of the ampliﬁer stage to shift to a lower frequency and thus become dominant.
Figure 7. Figure 7.1: Schematic of Entire OpAmp 108 .Chapter 7 Integrating the SubCircuits The last steps in the design ﬂow are to combine the circuits and test the full schematic in order to ensure that there are no unexpected interactions between the various subcircuits. The larger the design the more diﬃcult these interactions can become to understand.1 shows the full schematic representations.
1 Overall Performance A simulation of the completed circuit was performed with a purely resistance load of 100 M Ωs (shown in ﬁgure 7. The gain is approximately 95 · 104 (easily seen on the AC Response).3. The input voltage swing range can be seen to be approximately 16 µV Figure 7. INTEGRATING THE SUBCIRCUITS 109 7. is being measured relative to the operating voltage of 1.CHAPTER 7. It can be seen from the transient analysis that the output waveform is linearly ampliﬁed around the operating voltage of 1. Figure 7.2: Overall Performance with 1 µV .3: DC Performance – with 1 µV . The diﬀerential input voltage.65 V.2) and an input signal of 1KHz with a magnitude of 1 µV . in the DC Sweep.65 V.1KHz Input A close up of the DC Sweep transition region can be seen in ﬁgure 7.1KHz Input .
2 The Measurement of Some Main Parameters In this part. Vout doesn’t equal to zero because of the oﬀset voltage (Vos ). we introduce some methods to measure parameters and then apply some of them into the design of the OpAmp to evaluate it. Vout = 2. INTEGRATING THE SUBCIRCUITS 110 7.1 Input Oﬀset Voltage Figure 7.217mv . Although there is no input signal. because R2 100 = = 10−4 R1 + R2 100 + 1M so Vos = 2. We presume it’s an ideal OpAmp which has it’s noninverting pin connected to an oﬀset voltage source. 7. DUT is the OpAmp measured.173 · 10−4 = 0.CHAPTER 7.4.4: Measurement of Oﬀset Voltage Method: in 7. For an ideal OpAmp: For this circuit: Then V + = V− V+ = Vos V− = Vout · Vos = Vout · R2 R1 +R2 R2 R1 +R2 The result curve shows that when Vin = 0.173V .2.
INTEGRATING THE SUBCIRCUITS 111 Figure 7.5: Schematic for Measuring Oﬀset Voltage Figure 7.6: Result Plot of Oﬀset Voltage Test .CHAPTER 7.
CHAPTER 7.8: Schematic for Measuring CMRR .2 CommonMode Rejection Ratio (CMRR) Figure 7.7: Measurement of CMRR Figure 7. INTEGRATING THE SUBCIRCUITS 112 7.2.
9: Test Results of CMRR Simulation Method: CM RR(dB) = 20 log Ad Ac Ad Ac (7.11. INTEGRATING THE SUBCIRCUITS 113 Figure 7. is the common mode signal gain of OpAmp.CHAPTER 7. We get the following: Figure 7.1) is the diﬀerential mode signal gain of OpAmp.11: Equation .10: Equation By calculating it: Figure 7. signal source is a low frequency AC signal. For the 7.
2 dB (7.13: Derivation of the closedloop output resistance In order to ﬁnd the output resistance of a closedloopAmpliﬁer.Sedra and Mr.2. Then the output resistance Rout = VIx can be obtained by straightforward analysis of the circuit.4) 7.11. . Pages 94 to 95).3) CM RR (dB) = 20 log 104 · From the curve of 7. which makes the inverting and noninverting conﬁgurations identical and apply a test voltage Vx to the output as shown in Figure 7.2) Ad = CM RR = Ac In the test circuit – 7.Smith provide us a method to get the closeloop output resistance.Ro Method: Mr. so approximately. and (1 + Ad ) · R2 R1 R2 Vout Vin R1 . so Vin Vout (7. the amplitude of Vo ut is about 0. Third edition. we short the signal source. The schematic is below: Figure 7. ( microelectronic circuits .14. Ad Ac . Ad 1.9.CHAPTER 7. R1 R2 = 104 . INTEGRATING THE SUBCIRCUITS 114 Figure 7.55 = 85. (7. So we can get the result of our design’s CMRR is CM RR(dB) = 20 log 104 · 1 0.3 Output Resistance .12: Equation Generally.55mV and the amplitude of the input signal has been set to 1mV.
5) Note that Rout is the ”closedloop resistance of Opamp” and Ro is the ”openloop resistance”. From equation 7.CHAPTER 7. then b = 0.5. so we get: Ro Rout = (7. Rout = Ro . INTEGRATING THE SUBCIRCUITS We get the result directly(procedures omitted): Rout = (R1 + R2 )( Ro ) 1 + Ab 115 (7. The former one varies according to diﬀerent feedback networks but the latter is a very important inherent characteristic of the Opamp.6) 1 + Ab b is deﬁned as: b = R1R1 2 +R Consider the situation described as the schematic below: Figure 7. Simulation result of our Opamp’s output resistance is some curves like: . we should get the openloop resistance simultaneI ously. R1 ⇒ 0 and R2 ⇒ ∞ . Normally Ro is much smaller than R1 +R2 .14: At this situation. So by calculating Rout = Vx .
INTEGRATING THE SUBCIRCUITS 116 Figure 7.CHAPTER 7.15: Schematic for Measuring Output Resistance Figure 7.16: Result of Output Resistance Test .
CHAPTER 7.1KHz Input It is obvious that the amount of current which the circuit can supply is not enough. Figure 7. Figure 7.18: Instantaneous Power .17: AC & DC Simulation for a Parametric Load with 1 µV .3 Delivering Power to the Load/Instantaneous Power The maximum amount of power which can be delivered to the load can easily be tested by decreasing the resistance of the load. In order to increase the driving power which the circuit has. See Figure 7. L Figure 7.18 shows the instantaneous power of the OpAmp at 1KHz through a 10M Ω load.17. it is necessary to increase the strength W of the pushpull output transistors. INTEGRATING THE SUBCIRCUITS 117 7. We shall see that the if the load becomes too small the OpAmp will not be able to maintain the correct output voltage.
INTEGRATING THE SUBCIRCUITS 118 7.84µm for the Pchannel. we can improve the amount of power the OpAmp can supply. Two capacitors have been added to the control network in this schematic.19. These Miller Capacitors are required for stability. By increasing the transistor widths to: 15µm for the Nchannel and 32. Figure 7.4 Improving the Output Buﬀer A simpliﬁed schematic for testing the improved output buﬀer is shown in ﬁgure 7.CHAPTER 7.19: Output Test Schematic .
CHAPTER 7. INTEGRATING THE SUBCIRCUITS 119 Figure 7.20: AC & DC Simulation with larger Output Transistors for 1 µV .1KHz Input The size of the output transistors may be increased further if the design speciﬁcations require more current to be delivered. . The larger the output transistors the more care must be taken in making sure that the transistors are equally matched.
1 Stabilizing the Output Without the new Miller Capacitors the OpAmp becomes unstable. The noise can be seen clearly at approximately 100KHz.1 pF ) this harmonic is completely removed. however. INTEGRATING THE SUBCIRCUITS 120 7. . It should be noted that the noise on the output is increasing with time. Once the Miller Capacitors are in place (with a value of 0.CHAPTER 7. this instability is not seen in the frequency simulation.21. shown in ﬁgure 7. This was found in preliminary results.4. Figure 7.21: Instability due to lack of Miller Capacitors The frequency domain representation of the transient signal was calculated from the 3 msec → 4 msec. using a rectangular data window. This seems to be a limitation of the HSPICE AC simulation.
22.22: Final OpAmp Schematic . Figure 7.4.CHAPTER 7. INTEGRATING THE SUBCIRCUITS 121 7.2 The Final Schematic The ﬁnal Schematic for the OpAmp design is in ﬁgure 7.
Chapter 8 Closing Remarks 8. Many challenges were incurred and resolved soundly and swiftly through the cooperation and input of all of the group members. 122 .1 Conclusion This project was a huge success from its beginning to its tentative completion. By using a team oriented approach to the design methodology it was possible to bring together such an intricate project. Each member of the group has become a ”Miniexpert” in their area of their design and since these designs all ﬁt together in a larger puzzle knowledge of the other areas has also been gained my each group member.
CHAPTER 8. only the design methodology was covered in this tutorial.2 Future Work Due to the time limitations of this course. including troubleshooting. CLOSING REMARKS 123 8. simulating and software testing. Layout being the placing of the actual transistors down to the metal and poly layers. This next step will have its own design methodology and its own set of challenges. once the fabricator completes this step the fabricated chips would be set back and would go to the next stage which is actual hardware testing of the OpAmp. Here the DC and AC tests could be run as well as the protection of the circuit tested. The next step in the realization of this Operational Ampliﬁer is its layout and fabrication. The fabrication can take several weeks to several months once it has been sent to the fabricator. . This time delay is a result of the fabricator waiting to get enough designs to fabricate them on a whole wafer of silicon. (5 Months). Thus. Once the layout step has been completed the next step would be to have the Operational Ampliﬁer fabricated. to fabricate (10) Operational Ampliﬁers on a whole piece of silicon would not be cost eﬃcient. The hardware testing of the Operational Ampliﬁer would involve physically connecting the OpAmp chip to a power supply and putting in an input signal and then viewing its output signal on an oscilloscope.
Chapter 9 Bibliography 1. 1999.C. 2000. Massachusetts.4th Edition. 1998 ISBN: 0195116631.2nd Edition. PrenticeHall. Upper Saddle River. Riedel. WaiKai Chen. The VLSI Handbook. Paciﬁc Grove. Reading. ISBN: 0136919820. Electronics . ISBN: 0849385938 4. Boca Raton. Sedra And K. CRC Press. A. New Jersey. Florida. Ashok Ambardar.5th Edition.S. Microelectronic Circuits . ISBN: 053495409X 5. California. ISBN: 020155707X. Smith. BrooksCole Publishing Company. Electric Circuits . New York. Allan R. James W. Milsson And Susan A. Oxford University Press. Pages 211328 3. 1996. Pages 177211 124 . Analog and Digital Signal Processing. AddisonWesley Publishing Company. Pages 221874 2. Hambley.