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A

Compal Confidential
2

NEW50/70/80/90 M/B Schematics Document


Intel Arrandale Processor with DDRIII + Ibex Peak-M
ATI Madision/Park

2010-01-07

REV:1.0

2009/08/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page

NEW70 M/B LA-5891P Schematic

Date:

Friday, January 08, 2010

Sheet
E

of

59

Rev
1.0

Clock Generator

Compal Confidential

IDT: 9LVS3199AKLFT
Realtek: RTM890N-631-VB-GRT

Model Name : NEW50/70/80/90


File Name : LA5891P

133/120/100/96/14.318MHZ to PCH

Fan Control

page 38

page 12

PEG(DIS)

100MHz

PCI-E 2.0x16 5GT/s PER LANE

Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel

Intel

133MHz

Madision/Park

page 10,11

1.5V DDRIII 800/1066

Processor
rPGA988A

LVDS(DIS)

page 4,5,6,7,8,9

HDMI(DIS)

CRT(DIS)
FDI x8
(UMA)

HDMI Conn.

CRT Conn.

page 31
2

BANK 0, 1, 2, 3

Arrandale (UMA/DIS)

page
22,23,24,25,26,27,28

LVDS Conn.

page 30

page 29

HDMI(UMA)

USB conn x3
USB port 1

100MHz

100MHz

2.7GT/s

1GB/s x4

LVDS(UMA)
CRT(UMA)
TMDS(UMA)

HDMI
Level Shift

DMI x4

Intel
Ibex Peak-M

USB port 0, 2 on
USB/B
page 36

Bluetooth
Conn

CMOS Camera

Card Reader
RTS5160

USB port 11

USB port 8

USB port 9

page 36

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

page 29

page 36
2

page 31

port 2

MINI Card x2
WLAN, WWAN
USB port 12,13
page 35

port 1

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

SATA HDD
Conn. page

32

TI TPS6017
page 41

page 13

SATA CDROM
Conn. page 32
LPC BUS

33MHz

Int. Speaker

ENE KB926

Phone Jack x 2

page 41

page 41

page 37

USB/B 2Port
USB Port0,2 page 36

Touch Pad

Int.KBD

page 38

LS-5892P
page 34

Audio AMP

port 1

Sub-board
LS-5891P

Power On/Off CKT.

page 40

SPI ROM x1

page 33

page 34

page 15

ALC272X

SPI

BCM57780

RJ45

RTC CKT.

HDA Codec

page 13,14,15,16
17,18,19,20,21

100MHz

LAN(GbE)
port 0

PCH

100MHz

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

page 38

CPU XDP

Card Reader
USB Port9 page 36

page 5

BIOS ROM
DC/DC Interface CKT.
4

page 38

Power Circuit DC/DC


page 40~48

LS-5893P

page 38

LS-5894P

Power/B

PCH XDP

LID_SW/B

page 38

page 21

LS-5895P
3G
USB Port10,13page 35

2009/08/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Block Diagrams
Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
E

of

59

Rev
1.0

SIGNAL

STATE
Full ON

Power Plane

S1

S3

S5

Adapter power supply (19V)

Description

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

HIGH

HIGH

ON

ON

ON

ON

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

ON

OFF

OFF

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VSDGPU

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VTT

+1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.05VS_PCH

+1.05VS_VTT to +1.05VS_PCH power for PCH

ON

OFF

OFF

Board ID

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

0
1
2
3
4
5
6
7

ON

OFF

OFF

ON

OFF

OFF

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_EC

+3VALW always to KBC

ON

ON

ON*

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

ON

ON

ON*

+3V

+3VALW to +3V power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5V

+5VALW to +5V switched power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Device

Address

Smart Battery

0001 011X b

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

Address

BTO Option Table


BTO Item
UMA
UMA Only
Discrete
Discrete Only
GPU ALL Components
VRAM
Switchable
Connector
3G
Blue Tooth
Unpop
UMA HDMI
Discrete HDMI
UMA & DIS POP HDMI
GPU Madision
GPU Park
NEW70,80 LED
NEW50,90 LED

PCB Revision
0.1
0.2
0.3
1.0

USB Port Table


3

PCH SM Bus address

USB 2.0 USB 1.1 Port

Device

Address

Clock Generator (9LVS3199AKLFT,


RTM890N-631-VB-GRT)

1101 0010b

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

Option

UMAHD@

VGAHD@

UMA

VGA

SG
NO HDMI

HDMI@

3G & BT Config
3G SKU: 3G@
BT SKU: BT@

SG@

LED BOM config


NEW70,80 SKU: 7080@
NEW50,90 SKU: 5090@

UHCI0
UHCI1
EHCI1

GPU BOM Config


Madision SKU: MADI@
Park
SKU: PARK@
VRAM BOM Config
X761@: X76198BOL01 Park Samsung 512MB
X762@: X76198BOL02 Park Hynix 512MB
X763@: X76198BOL03 Madision Samsung 1024MB
X764@: X76198BOL04 Madision Hynix 1024MB
X765@: X76198BOL05 Park AMD 512MB
X766@: X76198BOL06 Madision AMD 1024MB

UHCI2
UHCI3
UHCI4
EHCI2

UHCI5
UHCI6

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB/B (Right Side)
USB Port (Left Side)
USB/B (Right Side)

BOM Structure
UMA@
UMAO@
DIS@
DISO@
VGA@
X76@
SG@
CONN@
3G@
BT@
@
UMAHD@
VGAHD@
HDMI@
MADI@
PARK@
7080@
5090@

X76@
ID3 , ID1 : VRAM Vender
Location

ID2: VRAM Size


Location

VRAM_ID3

VRAM_ID1

Samsung

R492

R474

HYNIX

R491

R474

AMD

R491

R473

VRAM

Camera
Card Reader
SIM Card
Blue Tooth
Mini Card(WLAN)
Mini Card(GPS)

VRAM

VRAM_ID2

8PCS 64Mx16
4PCS 64Mx16

R482

R483

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
AMD: SA00003PF20 (S IC D3 23EY2387MB-12)

BOM Config
UMA W/O HDMI SKU:
UMA W/ HDMI SKU:
Discrete W/O HDMI SKU:
Discrete W/ HDMI SKU:
Switchable W/O HDMI SKU:
Switchable W HDMI SKU:

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
2

EC SM Bus2 address
Device

Board ID / SKU ID Table for AD channel

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Clock

HIGH

Core voltage for Arrandale GPU (only for arrandaleCPU)

+1.5V to +1.5VS switched power rail

+VS

HIGH

Core voltage for GPU

+1.5VS to +1.5VSDGPU switched power rail for GPU

+V

LOW

+VGA_CORE

+1.5VSDGPU

+VALW

HIGH

+VGFX_CORE

+1.5VS

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

S1(Power On Suspend)

Voltage Rails
VIN

BT@/3G@/UMA@/UMAO@
BT@/3G@/UMA@/UMAO@/HDMI@/UMAHD@
BT@/3G@/DIS@/DISO@/VGA@/HDMI@/VGAHD@
BT@/3G@/DIS@/UMA@/VGA@/SG@
BT@/3G@/DIS@/UMA@/VGA@/SG@/HDMI@/VGAHD@
B

2009/08/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

BT@/3G@/DIS@/DISO@/VGA@

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
E

of

59

Rev
1.0

JCPU1E

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P2
DMI_PTX_HRX_P3

B24
D23
B23
A22

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_HTX_PRX_N0
DMI_HTX_PRX_N1
DMI_HTX_PRX_N2
DMI_HTX_PRX_N3

D24
G24
F23
H23

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P2
DMI_HTX_PRX_P3

D25
F24
E23
G23

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

E22
D21
D19
D18
G21
E19
F21
G18

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7

D22
C21
D20
C18
G22
E20
F20
G19

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

F17
E17

FDI_FSYNC[0]
FDI_FSYNC[1]

H_FDI_INT

C17

FDI_INT

15 H_FDI_LSYNC0
15 H_FDI_LSYNC1

F18
D17

FDI_LSYNC[0]
FDI_LSYNC[1]

15 H_FDI_FSYNC0
15 H_FDI_FSYNC1
15

Intel(R) FDI

H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7

15mil

PCI EXPRESS -- GRAPHICS

A24
C23
B22
A21

DMI

10mil

PEG_IRCOMP

R485
1

2 49.9_0402_1%

EXP_RBIAS

R493
1

2 750_0402_1%

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

B26
A26
B27
A25

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

C69
C72
C76
C84
C87
C96
C105
C106
C121
C123
C129
C141
C149
C160
C161
C167

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_GTX_HRX_N15
PEG_GTX_HRX_N14
PEG_GTX_HRX_N13
PEG_GTX_HRX_N12
PEG_GTX_HRX_N11
PEG_GTX_HRX_N10
PEG_GTX_HRX_N9
PEG_GTX_HRX_N8
PEG_GTX_HRX_N7
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
PEG_GTX_HRX_N4
PEG_GTX_HRX_N3
PEG_GTX_HRX_N2
PEG_GTX_HRX_N1
PEG_GTX_HRX_N0

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

C71
C75
C81
C86
C95
C98
C99
C113
C115
C128
C140
C142
C151
C153
C165
C174

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_GTX_HRX_P15
PEG_GTX_HRX_P14
PEG_GTX_HRX_P13
PEG_GTX_HRX_P12
PEG_GTX_HRX_P11
PEG_GTX_HRX_P10
PEG_GTX_HRX_P9
PEG_GTX_HRX_P8
PEG_GTX_HRX_P7
PEG_GTX_HRX_P6
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
PEG_GTX_HRX_P3
PEG_GTX_HRX_P2
PEG_GTX_HRX_P1
PEG_GTX_HRX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

C586
C561
C584
C559
C582
C557
C580
C555
C578
C553
C576
C551
C574
C549
C572
C547

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

C585
C560
C583
C558
C581
C556
C579
C554
C577
C552
C575
C550
C573
C548
C571
C546

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

R58
3.01K_0402_1%

R61
3.01K_0402_1%
R60
3.01K_0402_1%

1 DIS@
@
1

R59
3.01K_0402_1%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

2
2
2
2

WW41 Recommend not pull down


PCIE2.0 Jitter is over on ES1

R497
0_0402_5%
@
1
2
@
1
2

H_RSVD17_R
H_RSVD18_R

R501
0_0402_5%

DMI_PTX_HRX_N[0..3] 15
DMI_PTX_HRX_P[0..3] 15

15
15

PEG_GTX_HRX_N[0..15] 22
PEG_GTX_HRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

B19
A19

RSVD15
RSVD16

A20
B20

RSVD17
RSVD18

U9
T9

RSVD19
RSVD20

AC9
AB9

RSVD21
RSVD22

C1
A3

DMI_HTX_PRX_N[0..3] 15
DMI_HTX_PRX_P[0..3] 15
H_FDI_TXN[0..7]
H_FDI_TXP[0..7]

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

RSVD32
RSVD33

AJ13
AJ12

RSVD34
RSVD35

AH25
AK26

RSVD36
RSVD_NCTF_37

AL26
AR2

RSVD38
RSVD39

AJ26
AJ27

(CFD Only)
(CFD Only)

RESERVED

JCPU1A
DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3

RSVD_NCTF_40
RSVD_NCTF_41

AP1
AT2

RSVD_NCTF_42
RSVD_NCTF_43

AT3
AR1

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65

E15
F15
A2
D15
C15
AJ15
AH15

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

RSVD_NCTF_23
RSVD_NCTF_24

J29
J28

RSVD26
RSVD27

A34
A33

RSVD_NCTF_28
RSVD_NCTF_29

C35
B35

RSVD_NCTF_30
RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0
CONN@

VSS

R146
0_0402_5%
RSVD64_R 2
@
RSVD65_R 2
@
R147
0_0402_5%

1
1

AP34

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals Mapping


eDP Singal
PEG Singals
eDP_TX0
PEG_HTX_C_GRX_P15
eDP_TX#0 PEG_HTX_C_GRX_N15
eDP_TX1
PEG_HTX_C_GRX_P14
eDP_TX#1 PEG_HTX_C_GRX_N14
eDP_TX2
PEG_HTX_C_GRX_P13
eDP_TX#2 PEG_HTX_C_GRX_N13
eDP_TX3
PEG_HTX_C_GRX_P12
eDP_TX#3 PEG_HTX_C_GRX_N12
eDP_AUX
PEG_GTX_C_HRX_P13
eDP_AUX# PEG_GTX_C_HRX_N13
eDP_HPD# PEG_GTX_C_HRX_P12
5

Lane Reversal
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3

H_FDI_FSYNC0
H_FDI_FSYNC1

R519 1 DISO@ 2 1K_0402_5%


R517 1 DISO@ 2 1K_0402_5%

H_FDI_INT

R513 1 DISO@ 2 1K_0402_5%

H_FDI_LSYNC0
H_FDI_LSYNC1

R520 1 DISO@ 2 1K_0402_5%


R515 1 DISO@ 2 1K_0402_5%

CheckList0.8 1.22
Auburndale Graphics Disable

CFG0 - PCI-Express Configuration Select

CFG4 - Display Port Presence

*1:Single PEG
0:Bifurcation enabled

*1:Disabled; No Physical Display Port


attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

CFG3 - PCI-Express Static Lane Reversal

*:Default

*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

PROCESSOR (1/6) DMI,FDI,PEG


Size
B
Date:

Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

JCPU1B
H_COMP2

AT24

COMP2

R521 2

1 49.9_0402_1%

H_COMP1

G16

COMP1

R503 2

1 49.9_0402_1%

H_COMP0

AT26

COMP0

SKTOCC#_R

AH24

SKTOCC#

T7

PAD

18

R547 1
0_0402_5%

H_PECI

H_PECI_R

AT15

H_PROCHOT#

54 H_PROCHOT#

R124 1
0_0402_5%

18 H_THERMTRIP#

PROCHOT#

THERMTRIP#

H_CPURST#

AP26

RESET_OBS#

H_PM_SYNC_R

AL15

PM_SYNC

R122 1
0_0402_5%

H_CPUPW RGD_1

AN14

VCCPWRGOOD_1

H_VTTPW RGD 1
@
R540

R126
1
1.5K_0402_1%

H_CPUPW RGD_0

H_PW RGD_XDP R489 1


0_0402_5%

AN27

PM_DRAM_PW RGD_R

2 H_VTTPW RGD_R
0_0402_5%
2

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

H_PW RGD_XDP_R

AM26

TAPPWRGOOD

PLT_RST#_R

AL14

RSTIN#

A16
B16

BCLK_ITP
BCLK_ITP#

AR30
AT30

PEG_CLK
PEG_CLK#

E16
D16

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

SM_DRAMRST#

2009/2/4
#414044 DG
Update Rev1.11

CLK_CPU_XDP
CLK_CPU_XDP#

2009/08/14
remove DP REF SSCLK

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

CLK_CPU_DP_R
CLK_CPU_DP#_R

CLK_CPU_DP_R
CLK_CPU_DP#_R

PM_EXT_TS#[0]
PM_EXT_TS#[1]

AN15
AP15

PM_EXTTS#0
PM_EXTTS#1_R

PRDY#
PREQ#

AT28
AP27

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

AN28
AP28
AT27

XDP_TCLK
XDP_TMS
XDP_TRST#

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

DBR#

AN25

XDP_DBR#_R

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

2 0_0402_5%
2 0_0402_5%

1
R567

2
100K_0402_5%
R539 1
R538 1
R548 1

+1.05VS_VTT

2009/08/14 #425302
CP_S3PowerReduction
WhitePaper_Rev1.0

SM_DRAMRST# 10
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

R504 1
R510 1

F6

+1.05VS_VTT

2 10K_0402_5%
2 10K_0402_5%
2 0_0402_5%

SM_RCOMP_0 R578 1
SM_RCOMP_1 R576 1
SM_RCOMP_2 R573 1

XDP_PRDY#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

R89
R496
R495
R90
R62

XDP_TRST#

R499 1

XDP_TDI_R
XDP_TDO_M

R488 1
R475 1

@
@
@
@
@

1
1
1
1
1

51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%

2
2
2
2
2

PM_EXTTS#0_1 10,11

2 51_0402_5%

2 100_0402_1%
2 24.9_0402_1%
2 130_0402_1%

R87

2 0_0402_5%
2 0_0402_5%

XDP_TDI
XDP_TDO

R480
0_0402_5%

2 0_0402_5% XDP_DBRESET#

XDP_DBRESET# 15,21
XDP_TDI_M
XDP_TDO_R

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

1
R481 1
R476

2
2 0_0402_5%
0_0402_5%

JTAG MAPPING 2009/09/16 update

2009/2/4
Delete dampling resistor for
power noise and Layout space
issue

IC,AUB_CFD_rPGA,R1P0
CONN@

Scan Chain
(Default)

STUFF -> R488 , R480 , R476


NO STUFF -> R475 , R481

CPU Only

STUFF -> R488 ,R475


NO STUFF -> R480 , R481 , R476

GMCH Only

STUFF -> R481,R476


NO STUFF -> R488, R475 , R480

R125
750_0402_1%

CLK_CPU_BCLK 18
CLK_CPU_BCLK# 18

AL1
AM1
AN1

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

17,21,33,37 PLT_RST#

AK15

PECI

R123 1
0_0402_5%

R150 1
0_0402_5%

15 PM_DRAM_PW RGD

H_THERMTRIP#_R

R121 1
0_0402_5%

18 H_CPUPW RGD

AN26

CATERR#

PWR MANAGEMENT

15 H_PM_SYNC

AK14

THERMAL

H_CATERR#

BCLK
BCLK#

1 20_0402_1%

COMP3

R507 2

CLOCKS

AT23

DDR3
MISC

H_COMP3

JTAG & BPM

1 20_0402_1%

MISC

R512 2

+1.05VS_VTT

R127
R88
R91

2
2
2

1 49.9_0402_1%
1 68_0402_5%
1 68_0402_5%

H_CATERR#
H_PROCHOT#
H_CPURST#
JP2

2009/8/14
change back to 2K

U38
H_VTTPW RGD 2

+3VALW

MC74VHC1G08DFT2G_SC70-5

H_VTTPW RGD_R

XDP_OBS2
XDP_OBS3

XDP_OBS0
XDP_OBS1

R550
2K_0402_1%
1
2
R542

52 H_VTTPW RGD

XDP_PREQ#
XDP_PRDY#

1K_0402_1%

XDP_OBS4
XDP_OBS5

#425302
CP_S3PowerReduction
WhitePaper_Rev0.7

R152
@
1.1K_0402_1%

U11
B 2

Need to check Voltage Level

+1.5V_1

R151

H_VTTPW RGD

MC74VHC1G08DFT2G_SC70-5
<BOM Structure>

R197
1K_0402_5%
H_CPUPW RGD 1
2 H_PW RGOOD_R
R84 1
2 PBTN_OUT#_XDP
15,21,37 PBTN_OUT#
0_0402_5%
+1.05VS_VTT
H_PW RGD_XDP
1
C211
@
21 SMB_DATA_S3
0.1U_0402_16V4Z
21 SMB_CLK_S3
2
XDP_TCLK

1.5K_0402_1%

XDP_OBS6
XDP_OBS7

+3VALW

XDP Connector

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

H_RESET#_R

R83
1K_0402_5%
1
2
@
1
2

H_CPURST#
PLT_RST#

R85
0_0402_5%
CLK_CPU_XDP
CLK_CPU_XDP#
H_RESET#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

+1.05VS_VTT

2 R81
1K_0402_5%
2 R79
51_0402_5%

1
1

+3VS
+1.05VS_VTT

SAMTE_BSH-030-01-L-D-A

CONN@

PM_DRAM_PW RGD_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2
5

R149

2009/04/23
Intel CRB 1.55 Update
Change R68 to 1.1K_1%, R71 to 3.01K_1%
4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

750_0402_1%

R148
@
3.01K_0402_1%

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

PROCESSOR (2/6) CLK,JTAG


Size
B
Date:

Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

10
10
10

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

10 DDR_A_CAS#
10 DDR_A_RAS#
10 DDR_A_W E#

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AC3
AB2
U7

DDR_A_CAS#
DDR_A_RAS#
DDR_A_W E#

AE1
AB3
AE9

SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AA6
AA7
P7

Y6
Y5
P6

DDR_A_CLK1 10
DDR_A_CLK1# 10
DDR_A_CKE1 10

SA_CS#[0]
SA_CS#[1]

AE2
AE8

DDR_A_CS0# 10
DDR_A_CS1# 10

SA_ODT[0]
SA_ODT[1]

AD8
AF9

DDR_A_ODT0 10
DDR_A_ODT1 10

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_CLK0 10
DDR_A_CLK0# 10
DDR_A_CKE0 10

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

DDR SYSTEM MEMORY A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C9
F8
J9
N9
AH7
AK9
AP11
AT13

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

C8
F9
H9
M9
AH8
AK10
AN11
AR13

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

11
11
11

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

11 DDR_B_CAS#
11 DDR_B_RAS#
11 DDR_B_W E#

JCPU1D

11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
11 DDR_B_DQS#[0..7]
11 DDR_B_DQS[0..7]
11 DDR_B_MA[0..15]

JCPU1C

10 DDR_A_D[0..63]
10 DDR_A_DM[0..7]
10 DDR_A_DQS#[0..7]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15]

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AB1
W5
R7

SB_BS[0]
SB_BS[1]
SB_BS[2]

DDR_B_CAS#
DDR_B_RAS#
DDR_B_W E#

AC5
Y7
AC6

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

W8
W9
M3

DDR_B_CLK0 11
DDR_B_CLK0# 11
DDR_B_CKE0 11

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

V7
V6
M2

DDR_B_CLK1 11
DDR_B_CLK1# 11
DDR_B_CKE1 11

SB_CS#[0]
SB_CS#[1]

AB8
AD6

DDR_B_CS0# 11
DDR_B_CS1# 11

SB_ODT[0]
SB_ODT[1]

AC7
AD1

DDR_B_ODT0 11
DDR_B_ODT1 11

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

D4
E1
H3
K1
AH1
AL2
AR4
AT8

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D5
F4
J4
L4
AH2
AL4
AR5
AR8

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (3/6) DDRIII


Size
B
Date:

Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

JCPU1F

WW15 MOW
+CPU_CORE

Peak 21A

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

10U_0805_6.3V6M
+CPU_CORE

C258

C274

C286

C282

10U_0805_6.3V6M

C288

C284

10U_0805_6.3V6M

10U_0805_6.3V6M

C281

2
10U_0805_6.3V6M

10U_0805_6.3V6M
1

C676

10U_0805_6.3V6M

C677

10U_0805_6.3V6M
1

C669

C674

10U_0805_6.3V6M

10U_0805_6.3V6M
1

C657

C652

10U_0805_6.3V6M

10U_0805_6.3V6M
1

C679

C262

10U_0805_6.3V6M

C232

10U_0805_6.3V6M

(Place these capacitors between inductor and socket on Bottom)


+CPU_CORE
1
+

10U_0805_6.3V6M

1
C268

C667

C242

10U_0805_6.3V6M
1

C223

C257

10U_0805_6.3V6M
1

C261

C269

C275

C155

2
2

330U_X_2VM_R6M

330U_X_2VM_R6M
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors under CPU socket, top layer)

CSC (Current Sense Configuration)


8/25
+1.05VS_VTT
CPU_VID0

R436 1
R451 1

2 1K_0402_1%
2 1K_0402_1%

CPU_VID1

R437 1
R452 1

2 1K_0402_1%
2 1K_0402_1%

22U_0805_6.3V6M

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

C278

C277

22U_0805_6.3V6M
2
2
22U_0805_6.3V6M

CPU_VID2

R438 1
R453 1

CPU_VID3

R439 1
R454 1

2 1K_0402_1%
2 1K_0402_1%

CPU_VID4

R440 1
R455 1

2 1K_0402_1%
2 1K_0402_1%

PSI#

AN33

H_PSI#

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

CPU_VID0 54
CPU_VID1 54
CPU_VID2 54
CPU_VID3 54
CPU_VID4 54
CPU_VID5 54
CPU_VID6 54
H_DPRSLPVR 54
@

VTT_SELECT

G15

H_VTTVID1

2 1K_0402_1%
2 1K_0402_1%
C157

CPU_VID6

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

+CPU_CORE

R441 1
R456 1
R442 1
R457 1

@
@

H_DPRSLPVR R443 1
R458 1

H_PSI#

R444 1
R459 1

C276

22U_0805_6.3V6M
C270

C256

22U_0805_6.3V6M

22U_0805_6.3V6M

C241

22U_0805_6.3V6M

C231

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

2 1K_0402_1%
2 1K_0402_1%
2 1K_0402_1%
2 1K_0402_1%

+CPU_CORE
22U_0805_6.3V6M

2 1K_0402_1%
2 1K_0402_1%
2 1K_0402_1%
2 1K_0402_1%

C222

54

C651

22U_0805_6.3V6M
C658

C666

22U_0805_6.3V6M

22U_0805_6.3V6M

C665

22U_0805_6.3V6M

C668

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)


B

T8
PAD

VTT Rail
H_VTTVID1 = low, 1.1V
H_VTTVID1 = high, 1.05V

Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V
+CPU_CORE

ISENSE

VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT

AN35

AJ34
AJ35
B15
A15

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

IMVP_IMON 54

VCCSENSE_R R450 1
VSSSENSE_R R449 1

2 0_0402_5%
2 0_0402_5%

VTT_SENSE 52

VSS_SENSE_VTT
R523 1

1
R435
VCCSENSE
VSSSENSE

2
100_0402_1%

1
R448

2
100_0402_1%

+CPU_CORE

VCCSENSE 54
VSSSENSE 54

1
+

1
+

C541

330U_X_2VM_R6M

2 0_0402_5%

330U_X_2VM_R6M

C136

1
+

C251

330U_X_2VM_R6M

330U_X_2VM_R6M

C134

2
330U_X_2VM_R6M

TOP side (under inductor)

+CPU-CORE
Decoupling
SPCAP,Polymer

2009/08/01

Issued Date

C,uF

ESR, mohm

4X470uF

4m ohm/4

16X22uF

3m ohm/12

16X10uF

3m ohm/16

Stuffing Option
2X470uF

Compal Electronics, Inc.

Compal Secret Data

Security Classification

IC,AUB_CFD_rPGA,R1P0
CONN@

C97

MLCC 0805 X5R

2010/08/01

Deciphered Date

Title

PROCESSOR (4/6) PWR,Bypass

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

+1.05VS_VTT

CPU_VID5

POWER

+1.05VS_VTT
10U_0805_6.3V6M
10U_0805_6.3V6M

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

+1.05VS_VTT

CPU VIDS

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

SENSE LINES

CPU CORE SUPPLY

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

Continuous 18A

1.1V RAIL POWER

48A

Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

+VGFX_CORE
JCPU1G

C272

C673

C672

+
UMA@

UMA@

UMA@
2

UMA@
2

2
330U_X_2VM_R6M

22U_0805_6.3V6M
10U_0805_6.3V6M

J24
J23
H25

VTT1_45
VTT1_46
VTT1_47

15A

GRAPHICS

091211 EMI ADD 0.1U

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

3A

C260

FDI

22U_0805_6.3V6M

AR22
AT22

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

AM22
AP22
AN22
AP23
AM23
AP24
AN24

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

AR25
AT25
AM24

VCC_AXG_SENSE 53
VSS_AXG_SENSE 53
D

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6
GFXVR_EN
GFXVR_DPRSLPVR_R

R92

R99

GFXVR_EN

53
53
53
53
53
53
53

1
R98

Reserved for +1.5V to +1.5V_1


GFXVR_EN 53
GFXVR_DPRSLPVR 53
GFXVR_IMON 53

2 0_0402_5%

+1.5V_1

22U_0805_6.3V6M

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

1U_0402_6.3V4Z

1U_0402_6.3V4Z

22U_0805_6.3V6M

2
1

C307

C308

C309

C306

22U_0805_6.3V6M

1.1V

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

C310

C303

C315

@ JUMP_43X118

+ C326
330U_D2_2V_Y

J2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
22U_0805_6.3V6M

+1.5VS
C

Short for +1.5VS to +1.5V_1


11/03 add four 0.1u 0402
Intel suggest for S3 reduse
+1.5V_1

+1.5V

P10
N10
L10
K10

C267

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

J22
J20
J18
H21
H20
H19

VCCPLL1
VCCPLL2
VCCPLL3

L26
L27
M26

C797
2

0.1U_0402_16V4Z

C798
2

0.1U_0402_16V4Z

C799
2

0.1U_0402_16V4Z

C800
2

0.1U_0402_16V4Z

10U_0805_6.3V6M

C283
22U_0805_6.3V6M
B

+1.8VS

0.6A

1.8V

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

+1.05VS_VTT

VTT0_59
VTT0_60
VTT0_61
VTT0_62

PEG & DMI

22U_0805_6.3V6M
B

C285

@ JUMP_43X118

@ JUMP_43X118

+1.05VS_VTT

+1.5V
J4

1 DISO@ 2 1K_0402_5%

+1.05VS_VTT

C287

2
470_0402_5%

J3

+1.05VS_VTT

C253

VAXG_SENSE
VSSAXG_SENSE

- 1.5V RAILS

DDR3

C675
UMA@

C250

GRAPHICS VIDs

POWER

1
R514
0_0402_5%
DISO@

C610
0.1U_0402_16V4Z

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

SENSE
LINES

10U_0805_6.3V6M
22U_0805_6.3V6M

2.2U_0603_6.3V4Z

+1.8VS_VCCSFR
C230
1U_0402_6.3V4Z

IC,AUB_CFD_rPGA,R1P0
CONN@

C224

1U_0402_6.3V4Z

C235

R97
0_0805_5%
1
2

40mil
C234

C233

2 22U_0805_6.3V6M

4.7U_0805_10V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (5/6) PWR


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

IC,AUB_CFD_rPGA,R1P0
CONN@

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

NCTF

JCPU1H

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

H_NCTF1
H_NCTF2

@
@

PAD T14
PAD T19

H_NCTF6
H_NCTF7

@
@

PAD T18
PAD T15

IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (6/6) VSS


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

of

59

Rev
1.0

+1.5V

DIMMA VREFDQ M1 Circuit

JDIMM1

6 DDR_A_DQS#[0..7]
+DIMM_VREFDQA

+1.5V

6 DDR_A_D[0..63]

6 DDR_A_DM[0..7]
+DIMM_VREFDQA

R222

DDR_A_D0
DDR_A_D1
C402
DDR_A_DM0

0.1U_0402_16V4Z

6 DDR_A_MA[0..15]

20mil

C401

6 DDR_A_DQS[0..7]

1K_0402_1%

2.2U_0603_6.3V4Z
DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9
R227

DDR_A_DQS#1
DDR_A_DQS1

1K_0402_1%

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2

DIMMA & DIMMB VREFCA circuit


+1.5V
1

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

+DIMM_VREFCA

R203

DDR_A_DM3

1K_0402_1%
+1.5V

R201

R254
0_0402_5%
1 @
2

1K_0402_1%

DDR_A_D26
DDR_A_D27

#425302
CP_S3PowerReduction
WhitePaper_Rev1.0

20mil

DDR_A_CKE0

DDR_A_BS2

DDR_A_CKE0

DIMM_DRAMRST#
1
Q17
BSS138LT1G_SOT23-3

5 SM_DRAMRST#

RST_GATE

DIMM_DRAMRST# 11

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9

C422

RST_GATE

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

0.047U_0402_16V7K

6
6
6
6
6
6

DDR_A_CLK0
DDR_A_CLK0#

DDR_A_CLK0
DDR_A_CLK0#

DDR_A_MA10
DDR_A_BS0

DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_A_CS1#

DDR_A_CS1#

DDR_A_D32
DDR_A_D33

Layout Note:
Place near JDIMM1

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA

DDR_A_D40
DDR_A_D41

+1.5V

DDR_A_DM5
10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D42
DDR_A_D43

10U_0805_6.3V6M

C355

C356

10U_0805_6.3V6M

C405

C404

10U_0805_6.3V6M

C406

10U_0805_6.3V6M

C362

0.1U_0402_16V4Z

C363

C399

C400
2

C354

+ C425
330U_2.5V_M_R15
@

DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51

0.1U_0402_16V4Z

DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

Layout Note:
Place near JDIMM1.203 & JDIMM1.204
R218 1

2 10K_0402_5%

C403
2.2U_0603_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C398

+3VS
+0.75VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D

DDR_A_DM1
DIMM_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

R274
1K_0402_1%

18

+1.5V

R217

205

0.1U_0402_16V4Z
10K_0402_5%

G1

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_CKE1

DDR_A_CKE1 6

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#

DDR_A_CLK1 6
DDR_A_CLK1# 6

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 6
DDR_A_RAS# 6

DDR_A_CS0#
DDR_A_ODT0

DDR_A_CS0# 6
DDR_A_ODT0 6

DDR_A_ODT1

+DIMM_VREFCA

DDR_A_ODT1 6

20mil

DDR_VREF_CA_DIMMA R202 1

2 0_0402_5%

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39

C358
2.2U_0603_6.3V4Z

DDR_A_D44
DDR_A_D45

C361
0.1U_0402_16V4Z
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0_1
D_CK_SDATA
D_CK_SCLK

PM_EXTTS#0_1 5,11
D_CK_SDATA 11,12
D_CK_SCLK 11,12

+0.75VS

206

FOX_AS0A626-U8RN-7F

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1
C391
2

1
C388

1
C397

C396

DDR3 SO-DIMM A
H=8mm

C394
10U_0805_6.3V6M

2009/08/01

Issued Date

1U_0402_6.3V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
1U_0402_6.3V4Z

2010/08/01

Deciphered Date

Title

DDRIII-SODIMM SLOT1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Sheet

Tuesday, December 29, 2009


1

10

of

59

Rev
1.0

+1.5V
+1.5V
JDIMM2

2008/9/8 #400755
Calpella Clarksfield
DDR3 SO-DIMM
VREFDQ Platform
Design Guide Change Details

6 DDR_B_DQS#[0..7]
6 DDR_B_D[0..63]
6 DDR_B_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+DIMM_VREFDQB
C433
2.2U_0603_6.3V4Z

C431

6 DDR_B_DQS[0..7]

DDR_B_D0
DDR_B_D1

DDR_B_DM0

DDR_B_D2
DDR_B_D3

6 DDR_B_MA[0..15]

0.1U_0402_16V4Z
DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DIMMB VREFDQ M1 Circuit

DDR_B_D10
DDR_B_D11

+1.5V
1

DDR_B_D16
DDR_B_D17

+DIMM_VREFDQB

R282

DDR_B_DQS#2
DDR_B_DQS2

1K_0402_1%

DDR_B_D18
DDR_B_D19

20mil

DDR_B_D24
DDR_B_D25

R281
1K_0402_1%
2

DDR_B_DM3
DDR_B_D26
DDR_B_D27

DDR_B_CKE0

DDR_B_BS2

DDR_B_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

6
6

DDR_B_CLK0
DDR_B_CLK0#

DDR_B_MA10
DDR_B_BS0

DDR_B_BS0

6
6

Layout Note:
Place near JDIMM2

DDR_B_CLK0
DDR_B_CLK0#

DDR_B_WE#
DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_B_CS1#

DDR_B_CS1#

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMB

DDR_B_D32
DDR_B_D33

+1.5V
10U_0805_6.3V6M

0.1U_0402_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

0.1U_0402_16V4Z

DDR_B_D34
DDR_B_D35

10U_0805_6.3V6M

C436

10U_0805_6.3V6M 2

C420

C418

C416

C429

C430

C417

C419

C395
330U_2.5V_M_R15

DDR_B_D40
DDR_B_D41

C437

C435

DDR_B_DM5
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

DDR_B_D42
DDR_B_D43

0.1U_0402_16V4Z

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6

Layout Note:
Place near JDIMM2.203 & JDIMM2.204

DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

+0.75VS

DDR_B_DM7
1U_0402_6.3V4Z
DDR_B_D58
DDR_B_D59
C413

2
1U_0402_6.3V4Z

C412

C427

C426

1 C411

R279 1
+3VS

10U_0805_6.3V6M

R278
C432
2.2U_0603_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C428
0.1U_0402_16V4Z

2
10K_0402_5%

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13

DDR_B_DM1
DIMM_DRAMRST#

2009/08/01

DIMM_DRAMRST# 10

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_B_CKE1

DDR_B_CKE1 6

DDR_B_MA15
DDR_B_MA14
C

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDR_B_CS0#
DDR_B_ODT0
DDR_B_ODT1

20mil

DDR_B_CLK1 6
DDR_B_CLK1# 6
DDR_B_BS1 6
DDR_B_RAS# 6
DDR_B_CS0# 6
DDR_B_ODT0 6
DDR_B_ODT1 6

DDR_VREF_CA_DIMMB R270 1

+DIMM_VREFCA

2 0_0402_5%

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39

C414
2.2U_0603_6.3V4Z

DDR_B_D44
DDR_B_D45

C415
0.1U_0402_16V4Z
B

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#0_1
D_CK_SDATA
D_CK_SCLK

PM_EXTTS#0_1 5,10
D_CK_SDATA 10,12
D_CK_SCLK 10,12

+0.75VS
A

DDR3 SO-DIMM B
H=4mm

FOX_AS0A626-U4RN-7F
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2 10K_0402_5%

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2010/08/01

Deciphered Date

Title

DDRIII-SODIMM SLOT2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

11

of

59

Rev
1.0

SM010014520 3000ma 220ohm@100mhz DCR 0.04


+CLK_1.05VS
+1.05VS_VTT

L76 2
1
FBMA-L11-201209-221LMA30T_0805
1
1
C774
C782
10U_0805_10V4Z
10U_0805_10V4Z
2
2

C757

40mil

0.1U_0402_16V4Z
L69
2
1
FBMA-L11-201209-221LMA30T_0805

+3VS

+CLK_3VS

SM010014520 3000ma 220ohm@100mhz DCR 0.04

40mil

C770

C737

0.1U_0402_16V4Z

C740

10U_0805_10V4Z
2

0.1U_0402_16V4Z

10U_0805_10V4Z

40mil
0.1U_0402_16V4Z

C768
C781
10U_0805_10V4Z

C741

L75
2
1
FBMA-L11-201209-221LMA30T_0805

+1.5VS

0.1U_0402_16V4Z

L74
2
1
FBMA-L11-201209-221LMA30T_0805
+CLK_1.5VS
@

SM010014520 3000ma 220ohm@100mhz DCR 0.04

C750

10U_0805_10V4Z

C742

C771

C769
0.1U_0402_16V4Z

0.1U_0402_16V4Z

+CLK_3VS

+CLK_3VS

Clock Generator

+CLK_1.5VS
U47

14 CLK_BUF_DREF_96M
14 CLK_BUF_DREF_96M#

CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
R679 1
R719 1

23 VGA_CLK_27M

14 CLK_BUF_PCIE_SATA
14 CLK_BUF_PCIE_SATA#
14 CLK_BUF_CPU_DMI
14 CLK_BUF_CPU_DMI#

@
@

2 33_0402_5%
2 33_0402_5%

27M_CLK
27M_CLK_SS

CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
+CLK_1.05VS

H_STP_CPU#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33

VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48
VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#

SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#

32
31
30
29
28
27
26
25

VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC

24
23
22
21
20
19
18
17

D_CK_SCLK
D_CK_SDATA
REF_0/CPU_SEL R682 1

D_CK_SCLK 10,11
D_CK_SDATA 10,11
CLK_BUF_ICH_14M 14

2 33_0402_5%

CLK_XTAL_IN
CLK_XTAL_OUT
CK505_PW RGD
CLK_BUF_CPU_BCLK
CLK_BUF_CPU_BCLK#

CLK_BUF_CPU_BCLK 14
CLK_BUF_CPU_BCLK# 14

+CLK_1.05VS
+CLK_1.5VS

IDT SA00003HR00

TGND

SLG8SP587VTR_QFN32_5X5

IDT: 9LRS3199AKLFT, SA000030P00

SILEGO: SLG8SP587V(WF), SA00002XY10


+3VS

Low Power:
+3VS

Silego Have Internal Pull-Up

R678
4.7K_0402_5%
1
2

3
S

14,21,35 PCH_SMBDATA

IDT Have Internal Pull-Down

D_CK_SDATA
S

100MHz

100MHz

3
S

D_CK_SCLK
Y4
14.31818MHZ 20PF 7A14300003

Q45
2N7002E-T1-GE3_SOT23-3

Change to 5x3.2

CLK_XTAL_OUT

2009/08/01

Deciphered Date

C755
1

C762
27P_0402_50V8J
2
1

Compal Electronics, Inc.


2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

15,54

27P_0402_50V8J

Compal Secret Data

Security Classification
Issued Date

2
1

CLK_XTAL_IN

133MHz

14,21,35 PCH_SMBCLK

CPU_1

133MHz

VGATE

2
CLK_ENABLE# 54
G
Q48
2N7002E-T1-GE3_SOT23-3

R677
4.7K_0402_5%
1
2
+3VS

2
G

0 (Default)

CPU_0

R691
0_0402_5%
@
1
2

+3VS

2 10K_0402_5% REF_0/CPU_SEL

PIN 30

CK505_PW RGD

D
+3VS

Q46
2N7002E-T1-GE3_SOT23-3

FOR Realtek
R683 1

+3VS

H_STP_CPU#

2 10K_0402_5%

2
G

R690 1

R693
10K_0402_5%

Realtek: RTM890N-631-VB-GRT, SA00003HQ10

IDT 9LVS3199AKLFT NC

IDT: 9LVS3199AKLFT, SA00003HR00

Title

Clock Generator (CK505)


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009


G

Sheet

12

of
H

59

Rev
1.0

+RTCBATT
PCH_RTCRST#
PCH_RTCX1

OSC

R615
10M_0402_5%

U41A

C722
2
1

B13
D13

PCH_RTCX2

+RTCBATT_R

REV1.0

32.768KHZ_12.5PF_Q13MC14610002

OSC

NC

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

D33
B33
C32
A32

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4 / LFRAME#

C34

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

A34
F34

SERIRQ

AB9

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_DTX_C_PRX_N0 32
SATA_DTX_C_PRX_P0 32
SATA_PTX_DRX_N0 32
SATA_PTX_DRX_P0 32

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_DTX_C_PRX_N1 32
SATA_DTX_C_PRX_P1 32
SATA_PTX_DRX_N1 32
SATA_PTX_DRX_P1 32

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
AD6
AD5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
AB3
AB1

RTCX1
RTCX2

modify to 330K

2 1M_0402_5%

SM_INTRUDER#

A16

INTRUDER#

R212 1

2 330K_0402_1% PCH_INTVRMEN

A14

INTVRMEN

HDA_BITCLK_PCH

A30

HDA_BCLK

HDA_SYNC_PCH

D29

HDA_SYNC

R330

(HDA_SYNC Have internal Pull-Down) 40 HDA_SYNC_AUDIO

R327

(SPKR Have internal Pull-Down)


40 HDA_RST_AUDIO#

40

R328

2
33_0402_5%
2
33_0402_5%

PCH_SPKR

PCH_SPKR

2
33_0402_5%

HDA_RST_PCH#

40 HDA_SDIN0
R650
1K_0402_5%
@
1
2

PCH_SPKR

1
2
R237
10K_0402_5%

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

HDA_SDOUT_PCH

B29

HDA_SDO

PCH_GPIO33#

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

HDA_SDO ,This signal has a weak internal pull-down


resistor. Should not be Pull High

Have internal PD

SERIRQ
40 HDA_SDOUT_AUDIO

R324

If GPIO33 pull down, ME will not working.


For factory update ME, pull down resistor pull
under door.

2
33_0402_5%

GPIO33 can not pull down


(manufacturing environments)

PCH_GPIO33#
D

PCH_JTAG_TCK

M3

JTAG_TCK

K3

JTAG_TMS

21 PCH_JTAG_TDI

K1

JTAG_TDI

21 PCH_JTAG_TDO

J2

JTAG_TDO

J4

TRST#

21 PCH_JTAG_TCK

2
G

Q39

21 PCH_JTAG_TMS

S
2N7002E-T1-GE3_SOT23-3

37 ME_OVERRIDE

R580
100K_0402_5%

+1.05VS_PCH

PCH_SPI_CLK_1 R665 1

2 0_0402_5%

PCH_SPI_CLK

PCH_SPI_CS0#

2 15_0402_5%

PCH_SPI_CS0#_R AV3

2009/08/23
Debug Port DG1.7 P27.28

R662 1
T24 PAD

PCH_SPI_MOSI_1 R664 1
TDO,TDI,TMS
Pull Up for Production Units PCH_SPI_MISO_1 R661
1
unpop TDO,TDI,TMS resister

PCH_SPI_CS1#

BA2

SERIRQ

AY3

2 15_0402_5%

PCH_SPI_MOSI AY1

2 33_0402_5%

PCH_SPI_MISO

51_0402_5% 2
200_0402_5% 2
100_0402_5% 2

1 R644
1 R724
1 R722

PCH_JTAG_TDO

51_0402_5% 2
200_0402_5% 2
100_0402_5% 2

1 R645
1 R728
1 R727

PCH_JTAG_TDI

51_0402_5% 2
20K_0402_5% 2
10K_0402_5% 2

1 R643
1 R721
1 R723

PCH_JTAG_RST#

AF16

SATAICOMPI

AF15

4.7K_0402_5%

R647

SATA_COMP

0
1

R205 1

2 37.4_0402_1%

PCH_SATALED# R652 1

2 10K_0402_5%

SATALED#

T3

SATA0GP / GPIO21

Y9

SPI_MOSI
SPI_MISO

SATA1GP / GPIO19

V1

PCH_SATALED# 38

+3VS
B

GPIO21 Project ID2

R267 1

R260 1 SG@

PCH_GPIO21 21
PCH_GPIO19 21

TDO:
Reserved on ES1 Sample
Mount R724, R722 on ES2 Sample

2 10K_0402_5%
2 10K_0402_5%

R259
DISO@
10K_0402_5%

R268
10K_0402_5%

+3VS

MP mount R646, R644,


R645, R643 and remove
others

U18
+3VS

R301 1
R271 1

2 3.3K_0402_5%
2 3.3K_0402_5%

PCH_SPI_CS0#
SPI_W P1#
SPI_HOLD1#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1

PCH_SPI_CLK_1 @

MX25L3205DM2I-12G SOP 8P
SA000021A00

dGPU
iGPU
SG

PCH_JTAG_TCK

*
+3VS

SATA for ODD

+3VS

SPI_CS1#

AV1

SATA for HDD1

+1.05VS_PCH

SATAICOMPO

SPI ROM Footprint 200mil

20mil

0.1U_0402_16V4Z

PCH_GPIO21

NEW50/70/80/90
NEW71/91

PCH_JTAG_TMS

GPIO21

Project ID

2008 Intel MOW36/MOW50

1 R646
1 R726
1 R725

37

+CHGRTC
C724

2/10 SATA2, SATA3 not support on HM55

IBEXPEAK-M_FCBGA107
@

1
C729

2
10P_0402_50V8J

GPIO19

GPIO37

PCH_GPIO19

VGA_PRSNT_L#

0
0
1

0
1
X

S3 CRB 1.1 Change to 4.7K

R663

PCH_SPI_MOSI

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MOSI This signal has a weak internal pull-down


resistor. This signal must be sampled low.
5

2009/08/01

Issued Date

enable iTPM: SPI_MOSI High

Compal Electronics, Inc.

Compal Secret Data

Security Classification
1K_0402_5% 2

SPI_CS0#

+3V

51_0402_5% 2
200_0402_5% 2
100_0402_5% 2

20mil

LPC_FRAME# 37

SPI_CLK

SPI

21 PCH_JTAG_RST#

GPIO33 has a weak internal pull-up


NOTE: Asserting the GPIO33 low on the rising
edge of PWROK will also halt Intel Management
Engine after chipset bringup and disable
runtime Intel Management Engine features.
This is a debug mode and must not be
asserted after manfacturing/ debug.

D8
BAS40-04_SOT23-3
+RTCVCC

+3VS

37
37
37
37

INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs
40 HDA_BITCLK_AUDIO

HDA_SYNC
On Die PLL VR is supplied by
1.5V when sampled High,
1.8V when sampled Low.

R213 1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

HDA for AUDIO

SRTCRST#

SATA

1
2
R675
@
10K_0603_5%
C365
1U_0603_10V6K
1
2

D17

IHDA

close to RAM door

RTCRST#

PCH_SRTCRST#

LPC

+RTCVCC

RC Delay 18~25mS

C14

JTAG

+RTCVCC

PCH_RTCRST#

RTC

18P_0402_50V8J
PCH_SRTCRST#

1
2
R214
20K_0402_1%

NC

1
2
R671
@
10K_0603_5%
C366
1U_0603_10V6K
1
2

R336
1K_0402_5%

20mil

X2

close to RAM door

C723
18P_0402_50V8J
2
1

RC Delay 18~25mS

1
2
R215
20K_0402_1%

+RTCVCC

Title

PCH (1/9) SATA,HDA,SPI, LPC


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

13

of

59

Rev
1.0

1. Connect Directly
EXPRESS CARD, MINI1, MINI2
2. Level Shift1, Pull-Up to +3VS
CLOCK GEN, DIMM1, DIMM2
3. Level Shift2, Pull-Up to +3VS
LAN
4. Level Shift3, Pull-Up to +3VS
CPU & PCH XDP

U41B

AK48
AK47

33 CLK_PCIE_LAN#
33 CLK_PCIE_LAN

For PCIE LAN


R258 1

2 0_0402_5%

R266 1

2 0_0402_5%

PCH_GPIO73

AM43
AM45

35 CLK_PCIE_MINI1#
35 CLK_PCIE_MINI1

For Wireless LAN


35 MINI1_CLKREQ#
21 PCH_GPIO18

P9

PCH_GPIO18

U4
AM47
AM48

PCH_GPIO20

21 PCH_GPIO20

N4
AH42
AH41

PCH_GPIO25

2009/08/25: Change back to +3V


remove mini2

+3V

2009/08/25: remove mini2 clk

R241

A8
AM51
AM53

MINI2_CLKREQ#_1

M9

SMBus

PCH_SML1CLK

SML1DATA / GPIO75

G12

PCH_SML1DAT

CL_CLK1

T13

CL_DATA1

T11

CL_RST1#

T9

PEG_A_CLKRQ# / GPIO47

H1

PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLK_PEG_VGA# 22
CLK_PEG_VGA 22

CLKOUT_DMI_N
CLKOUT_DMI_P

AN4
AN2

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AT1
AT3

PCH_GPIO44

H6
AK53
AK51

AW24
BA24

CLK_BUF_CPU_DMI# 12
CLK_BUF_CPU_DMI 12

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_BUF_CPU_BCLK# 12
CLK_BUF_CPU_BCLK 12

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

CLK_BUF_DREF_96M# 12
CLK_BUF_DREF_96M 12

AH13
AH12

CLK_BUF_PCIE_SATA# 12
CLK_BUF_PCIE_SATA 12

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

P41

CLKIN_PCILOOPBACK

J42

CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3# / GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26

PCH_GPIO56

P13

+3VS

MINI1_CLKREQ# R265 1
PCH_GPIO20
R649 1

2009/08/13: Change back to +3V

PCH_GPIO25

R624 1

PEG_B_CLKRQ# / GPIO56

CLK_BUF_ICH_14M

1
R163

XTAL25_IN
XTAL25_OUT

AH51
AH53

XCLK_RCOMP

AF38

CLKOUTFLEX0 / GPIO64

1
C319

R563
DISO@
0_0402_5%
1
2

12

2
10P_0402_50V8J

1109 RF request

C693
UMA@
27P_0402_50V8J
1
2

XTAL25_IN
XTAL25_OUT
XCLK_RCOMP

R170 1

2 90.9_0402_1%

Project Structure ID

T45

CLKOUTFLEX1 / GPIO65

P43

CLKOUTFLEX2 / GPIO66

T42

PROJECT_ID0

N50

2
10_0402_5%

CLK_PCI_FB 17

PROJECT_ID1

CLKOUTFLEX3 / GPIO67

R156 1
R144 1

+3VS

R564
1M_0402_5%
UMA@

EC_LID_OUT#
PCH_SMBCLK
PCH_SMBDATA

R623 1
R602 1
R626 1

2 10K_0402_5%
2 2.2K_0402_5%
2 2.2K_0402_5%

PCH_GPIO60

R208 1

2 10K_0402_5%

PCH_SML1CLK
PCH_SML1DAT

R639 1
R249 1

2 2.2K_0402_5%
2 2.2K_0402_5%

PCH_GPIO74

R207 1

2 10K_0402_5%

PCH_GPIO44
PCH_GPIO56
PCH_GPIO73

R244 1
R206 1
R257 1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

Change to 5x3.2

C694
27P_0402_50V8J
UMA@

2 10K_0402_5%
2 10K_0402_5%

2 10K_0402_5%

+3VS

PCH_SML1CLK

EC_SMB_CK2

EC_SMB_CK2 23,37

Q19A
DMN66D0LDW -7_SOT363-6
+3VS

Pull high +3VS at KB926 side

PCH_SML1DAT

EC_SMB_DA2

EC_SMB_DA2 23,37

Q19B
DMN66D0LDW -7_SOT363-6

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Y2
25MHZ_20PF_7A25000012
UMA@

2 10K_0402_5%

R157 1

R167 1
1216 GPIO65
PULL HIGH:PVT
PULL DOWN:DVT

+1.05VS_PCH

Project Structure
GPIO21 GPIO65 GPIO66
Structure
ID2
ID1
ID0
0
DVT
0
0
0
0
1
*
0
1
0
PVT

+3V

+3V

PEG_CLKREQ# 23
R276
SG@
2.2K_0402_5%

6/9 MOW23 Request add 25MHz crystal


supporting Integrated Graphics

1222 GPIO66
PULL HIGH:8L
PULL DOWN:6L

2 10K_0402_5%

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

IBEXPEAK-M_FCBGA107

2 10K_0402_5%
2 10K_0402_5%

9/1: Change to +3VS

CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44

Q18
R247
SG@
DISO@
2.2K_0402_5%

2N7002E-T1-GE3_SOT23-3

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ2# / GPIO20

R277
@
10K_0402_5%

2
G
1

PEG_CLKREQ#_R

AD43
AD45

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

Clock Flex

AJ50
AJ52

+3VSDGPU
R275
SG@
10K_0402_5%

R636
UMA@
10K_0402_5%

10K_0402_5%
MINI2_CLKREQ#_1

DGPU_PW R_EN 18,21,39,43

+3V

PCH_GPIO74

E10

33 LAN_CLKREQ#

M14

SML1CLK / GPIO58

SML1ALERT# / GPIO74

BG34
BJ34
BG36
BJ36

PERN7
PERP7
PETN7
PETP7

G8

AT34
AU34
AU36
AV36

2/10 PCIE7, PCIE8 not support on HM55

C6

PERN6
PERP6
PETN6
PETP6

SML0CLK
SML0DATA

BA34
AW34
BC34
BD34

PCH_GPIO60

PERN5
PERP5
PETN5
PETP5

2009/08/25: remove PCIE5

For Mini2

PCH_SMBDATA 12,21,35

J14

BF33
BH33
BG32
BJ32

PCH_SMBDATA

PERN4
PERP4
PETN4
PETP4

PCH_SMBCLK 12,21,35

C8

EC_LID_OUT# 37

BA32
BB32
BD32
BE32

SML0ALERT# / GPIO60

PCH_SMBCLK

PERN3
PERP3
PETN3
PETP3

SMBDATA

H14

AU30
AT30
AU32
AV32

SMBCLK

EC_LID_OUT#

PERN2
PERP2
PETN2
PETP2

SMBALERT# / GPIO11

B9

1
1

PCIE_DTX_C_PRX_N2 AW30
PCIE_DTX_C_PRX_P2 BA30
0.1U_0402_16V7K
PCIE_PTX_DRX_N2 BC30
0.1U_0402_16V7K
PCIE_PTX_DRX_P2 BD30

PERN1
PERP1
PETN1
PETP1

Link

C332 2
C334 2

1
1

Controller

PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

2
2

PEG

35
35
35
35

C335
C339

PCI-E*

For Wireless LAN

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

BG30
BJ30
BF29
BH29

From CLK BUFFER

33
33
33
33

For PCIE LAN

REV1.0

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
0.1U_0402_16V7K
PCIE_PTX_DRX_N1
0.1U_0402_16V7K
PCIE_PTX_DRX_P1

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

PCH (2/9) PCIE, SMBUS, CLK


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Friday, January 08, 2010

Sheet
1

14

of

59

Rev
1.0

DMI_PTX_HRX_N[0..3]

4 DMI_PTX_HRX_N[0..3]

DMI_PTX_HRX_P[0..3]

4 DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]

4 H_FDI_TXN[0..7]

U41C

R600
49.9_0402_1%
1
2

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3

BE22
BF21
BD20
BE18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P2
DMI_PTX_HRX_P3

BD22
BH21
BC20
BD18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BH25
DMI_COMP

DMI_ZCOMP

BF25

1 0_0402_5%
1 0_0402_5%

EC_ACIN

B17

PWROK
MEPWROK

A10

PCH_RSMRST#

C16

SUS_PW R_DN_ACK

M1

EC_SW I#

BH13

H_FDI_FSYNC1

FDI_LSYNC0

BJ12

H_FDI_LSYNC0

FDI_LSYNC1

BG14

H_FDI_LSYNC1

SYS_PWROK

LAN_RST#
DRAMPWROK
RSMRST#

J12

PCH_PCIE_W AKE#

CLKRUN# / GPIO32

Y1

PM_CLKRUN#

SUS_STAT# / GPIO61

P8

PCH_GPIO61
SUSCLK

P5

PCH_ACIN

P7

ACPRESENT / GPIO31

PCH_GPIO72

A6

BATLOW# / GPIO72

PWRBTN#

PCH_PCIE_W AKE#

33,35

PM_CLKRUN# 37

PAD

T10

SUSCLK / GPIO62

F3

SLP_S5# / GPIO63

E4

PM_SLP_S5# 37

SLP_S4#

H7

PM_SLP_S4# 37

SLP_S3#

P12

SLP_M#

K8

PM_SLP_M#

PAD

T11

TP23

N2

PM_SLP_DSW # @

PAD

T22

SUS_PWR_DN_ACK / GPIO30

PBTN_OUT#

1
R240

37

FDI_FSYNC1

SUSCLK 37

PM_SLP_S3# 37

@
1 0_0402_5%

R605 2
Q41
MMBT3906_SOT23-3
PCH_RSMRST#
1
3

EC_RSMRST# 37

23,37

H_FDI_FSYNC0

M6

D9

5,21,37 PBTN_OUT#
2
10K_0402_5%
2
D6
CH751H-40PT_SOD323-2

H_FDI_INT

BF13

SYS_PW ROK_R

5 PM_DRAM_PW RGD

BJ14

WAKE#

LAN_RST#

+3V

FDI_INT
FDI_FSYNC0

SYS_RESET#

K5

37 SUS_PW R_DN_ACK

H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7

T6

SYS_PW ROK

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

EC_SW I#

F14

PMSYNCH

RI#

SLP_LAN# / GPIO29

BJ10
F6

H_PM_SYNC

R604
10K_0402_5%

PM_SLP_LAN#

1
R598

IBEXPEAK-M_FCBGA107

2
4.7K_0402_5%

+3V

D20A

R620 2
R631 2

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

XDP_DBRESET#

System Power Management

SYS_PW ROK
VGATE

H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7

DMI_IRCOMP

09/09/14 WW37 PCH WAKE# PU 10K

5,21 XDP_DBRESET#

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

2
B

+1.05VS_PCH
SUS_PW R_DN_ACK
2
10K_0402_5%
PCH_GPIO72
2
8.2K_0402_5%
EC_SW I#
2
10K_0402_5%
PCH_PCIE_W AKE#
2
10K_0402_5%
PM_SLP_LAN#
2
10K_0402_5%

BD24
BG22
BA20
BG20

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

+3V

DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P2
DMI_HTX_PRX_P3

FDI

PM_CLKRUN#
2
8.2K_0402_5%

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI

+3VS

REV1.0

DMI_HTX_PRX_N0 BC24
DMI_HTX_PRX_N1 BJ22
DMI_HTX_PRX_N2 AW20
DMI_HTX_PRX_N3 BJ20

H_FDI_TXP[0..7]

4 H_FDI_TXP[0..7]

1
R648
1
R628
1
R198
1
R641
1 @
R248

DMI_HTX_PRX_P[0..3]

4 DMI_HTX_PRX_P[0..3]

1
R657

DMI_HTX_PRX_N[0..3]

4 DMI_HTX_PRX_N[0..3]

1
6
2

EC_PW ROK
VGATE

4
3

EC_PW ROK 37,39


VGATE

12,54

P
SYS_PW ROK

D20B
U44
2

BAV99DW -7_SOT363

R591
2.2K_0402_5%

MC74VHC1G08DFT2G_SC70-5

21

SYS_PW ROK

BAV99DW -7_SOT363

+3VS

SYS_PW ROK

1
R606

2
10K_0402_5%

EC_PW ROK

1
R632

2
10K_0402_5%

LAN_RST#

1
R617

2
10K_0402_5%

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

No used Integrated LAN,


connecting LAN_RST# to GND
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

PCH (3/9) DMI, FDI, PM


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

15

of

59

Rev
1.0

U41D

29 DPST_PW M
29 PCH_LCD_CLK
29 PCH_LCD_DATA

11/21 intel JIM suggest Pull high at LVDS Conn


@

2 2.2K_0402_5%

PCH_LCD_CLK

R131 1

2 2.2K_0402_5%

PCH_LCD_DATA

2 10K_0402_5%

LCTLA_CLK

R132 1

R133 1

2 10K_0402_5%

LCTLB_DATA

R546 1

2 2.2K_0402_5%

PCH_CRT_CLK

R545 1

2 2.2K_0402_5%

PCH_CRT_DATA

08/20 add UMA@


R551
R552
R553

1
UMA@
1
UMA@
1
UMA@

2
2
2

L_DDC_CLK
L_DDC_DATA

LCTLA_CLK
LCTLB_DATA

AB46
V48

L_CTRL_CLK
L_CTRL_DATA

AP39
AP41

LVD_IBG
LVD_VBG

R162 1 UMA@ 2
0_0402_5%

LVD_VREF

AT43
AT42

LVD_VREFH
LVD_VREFL

29 PCH_TXOUT0+
29 PCH_TXOUT1+
29 PCH_TXOUT2+

PCH_CRT_B
150_0402_1%
PCH_CRT_G
150_0402_1%
PCH_CRT_R
150_0402_1%

LVDSA_CLK#
LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

BB47
BA52
AY48
AV47

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

BB48
BA50
AY49
AV48

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AP48
AP47

LVDSB_CLK#
LVDSB_CLK

AY53
AT49
AU52
AT53

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AY51
AT48
AU50
AT51

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

AA52
AB53
AD53

CRT_BLUE
CRT_GREEN
CRT_RED

PCH_CRT_CLK
PCH_CRT_DATA

30 PCH_CRT_CLK
30 PCH_CRT_DATA

ENBKL

R135 1 UMAO@ 2 0_0402_5%

1A
2A
1OE#
2OE#

CRT_HSYNC
CRT_VSYNC

T51
T53

SDVO_SCLK 31
SDVO_SDATA 31
R171 1

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

BG44
BJ44
AU38

PCH_DPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

DDPC_CTRLCLK
DDPC_CTRLDATA

Y49
AB49

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

BE44
BD44
AV40

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

2 100K_0402_5%
PCH_DPB_HPD

C313
C305
C320
C323
C317
C314
C327
C325

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

UMAHD@
UMAHD@
UMAHD@
UMAHD@
UMAHD@
UMAHD@
UMAHD@
UMAHD@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

31

PCH_TMDS_D2# 31
PCH_TMDS_D2 31
PCH_TMDS_D1# 31
PCH_TMDS_D1 31
PCH_TMDS_D0# 31
PCH_TMDS_D0 31
PCH_TMDS_CK# 31
PCH_TMDS_CK 31

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

REV1.0

U50
U52

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

BC46
BD46
AT38

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

1
2

IGPU_BKLT_EN

2
5
1
7

SDVO_INTN
SDVO_INTP

BF45
BH45

R143
1K_0402_0.5%

+5VS
U25

17,29,30 DGPU_SELECT#
29 IGPU_SELECT#

Y53
Y51

DAC_IREF
CRT_IRTN

BJ48
BG48

IBEXPEAK-M_FCBGA107
R134
100K_0402_5%

23 DGPU_BKL_EN

CRT_DDC_CLK
CRT_DDC_DATA

UMA Only

SDVO_STALLN
SDVO_STALLP

DDPD_CTRLCLK
DDPD_CTRLDATA

V51
V53

CRT_IREF AD48
AB51

IGPU_BKLT_EN

BJ46
BG46

SDVO_CTRLDATA strap Pull High at Level Shift Page

AV53
AV51

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

30 PCH_CRT_B
30 PCH_CRT_G
30 PCH_CRT_R

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK
SDVO_CTRLDATA

PCH_TXCLKPCH_TXCLK+

30 PCH_CRT_HSYNC
30 PCH_CRT_VSYNC

L_BKLTCTL

AB48
Y45

LVDS_IBG

29 PCH_TXOUT029 PCH_TXOUT129 PCH_TXOUT2-

R130 1

Y48
PCH_LCD_CLK
PCH_LCD_DATA

R166 1 UMA@ 2
2.37K_0402_1%

29 PCH_TXCLK29 PCH_TXCLK+

+3VS

L_BKLTEN
L_VDD_EN

Digital Display Interface

PCH_ENVDD

CRT

29

T48
T47

LVDS

IGPU_BKLT_EN

VCC
1B
2B
GND

8
3
6
4

2/3 Change to 1K_0402_0.5% from Intel


Suggestion. (EDS 1.0 is incorrect)

C472
SG@
0.1U_0402_16V4Z
1
2
ENBKL

ENBKL

23,37

SN74CBTD3306CPW R_TSSOP8
SG@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCH (4/9) LVDS, CRT, DPI


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

16

of

59

Rev
1.0

R577
R574
R572
R153

R568
R570
R565
R566

1
1
1
1

2
2
2
2

1
1
1
1

2
2
2
2

1
1
1
1

2
2
2
2

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

PCI_REQ0#
PCI_PIRQB#
PCI_PIRQF#
PCI_REQ3#

PCI_IRDY#
PCI_PIRQD#
DGPU_SELECT#
PCI_DEVSEL#

PCI_FRAME#
PCI_REQ1#
PCI_PIRQH#
PCI_TRDY#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3#
has a weak internal pull-up

PCI_REQ0#
PCI_REQ1#
DGPU_SELECT#
PCI_REQ3#

16,29,30 DGPU_SELECT#

PCI_GNT2# ESI Strap (Server Only)


this signal should not be pulled low

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
@

TP_PCI_RST#
PCI_SERR#
PCI_PERR#

5,21,33,37 PLT_RST#

1
1

PIRQA#
PIRQB#
PIRQC#
PIRQD#

F51
A46
B45
M53

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

2 22_0402_5%
2 22_0402_5%

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

B41
K53
A36
A48

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K6

PCIRST#
SERR#
PERR#

PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

IRDY#
PAR
DEVSEL#
FRAME#

PCI_PLOCK#

D49

PLOCK#

PCI_STOP#
PCI_TRDY#

D41
C48

STOP#
TRDY#

M7

PME#

PLT_RST#

2008/1/6 2009MOW01 change to 22 ohm


R561
R142

G38
H51
B37
A44

CLK_PCI_LPC_R
CLK_PCI_FB_R

AV7

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

@
0.1U_0402_16V7K

18,21 DGPU_HOLD_RST#

R621
100K_0402_5%

R742
0_0402_5%
@
1
2

R741
0_0402_5%
1 DIS@
2

U43

MC74VHC1G08DFT2G_SC70-5
DIS@

R619 1 DIS@
100_0402_5%

NV_ALE
NV_CLE
NV_RCOMP

R660 1

+1.8VS

2 32.4_0402_1%
NV_ALE

R233 1

2 1K_0402_5%

NV_CLE

R225 1

2 1K_0402_5%

AV11
BF5

Intel Anti-Theft Techonlogy

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USBRBIAS#

B25

USB_BIAS

USBRBIAS

D25

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

N16
J16
F16
L16
E14
G16
F12
T15

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

36
36
36
36
36
36

NV_ALE

USB/B (Right Side)


USB Port (Left Side)

DMI Termination Voltage

USB/B (Right Side)

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

NV_ALE
Enable Intel Anti-Theft
Technology 8.2K PU to +3VS

2/10 USB6, USB7 not


support on HM55
USB20_N8 29
USB20_P8 29
USB20_N9 36
USB20_P9 36
USB20_N10 35
USB20_P10 35
USB20_N11 36
USB20_P11 36
USB20_N12 35
USB20_P12 35
USB20_N13 35
USB20_P13 35

EHCI 1

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13

High=Endabled
Low=Disable(floating)

Disable Intel Anti-Theft


Technology floating(internal PD)

CMOS Camera (LVDS)


Card Reader

NV_CLE

Mini Card(SIM Card)

DMI termination voltage.


weak internal PU, don't PD

EHCI 2

Bluetooth
Mini Card(WLAN)
Mini Card(WWAN)

D5

USB_OC#0_R

USB_OC#0_R 21

USB_OC#2_R

PLTRST#

N52
P53
P46
P51
P48

1
2
R191
22.6_0402_1%

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB_OC#0_R
USB_OC#1_R
USB_OC#2_R
USB_OC#3_R
USB_OC#4_R
USB_OC#5_R
USB_OC#6_R
USB_OC#7_R

R216 1

2 0_0402_5%

R210 1

2 0_0402_5%

USB_OC#2_R 21

(For USB Port0, 2)

USB_OC#0 36
USB_OC#1_R 21
USB_OC#2 36
USB_OC#3_R 21
USB_OC#4_R 21
USB_OC#5_R 21
USB_OC#6_R 21
USB_OC#7_R 21

(For USB Port1)

RP1
USB_OC#3_R
USB_OC#5_R
USB_OC#6_R
USB_OC#7_R

1
2
3
4

8
7
6
5

+3V

10K_1206_8P4R_5%

Boot BIOS Location

LPC

Reserved (NAND)

PCI

SPI

PCI_GNT0#

R137 1

2 1K_0402_5%

2 1K_0402_5%

2 1K_0402_5%

Have internal PU
PCI_GNT1#

R159 1

USB_OC#1_R

R601 1

2 10K_0402_5%

USB_OC#4_R

R603 1

2 10K_0402_5%

Have internal PU
PCI_GNT3#

R558 1

Have internal PU

A16 swap overide Strap/Top-Block


Swap Override jumper

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *
5

PLTRST_VGA# 22

NV_ALE,NV_CLE
has a weak internal pull-down

OC[0..3] use for EHCI 1


OC[4..7] use for EHCI 2

PCI_GNT#1

R622
100K_0402_5%
DIS@

IBEXPEAK-M_FCBGA107

PLT_RST_BUF# 35

2
+3VS

Boot BIOS Strap


PCI_GNT#0

4
1

AU2

NV_RB#

NV_RCOMP

BD3
AY6

NV_ALE
NV_CLE

C443

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

U42
PLT_RST#

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_WE#_CK0
NV_WE#_CK1

E44
E50

PCI_IRDY#

37 CLK_PCI_LPC
14
CLK_PCI_FB

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PCI_GNT0#
F48
PCI_GNT1#
K45
DGPU_PW MSEL# F36
PCI_GNT3#
H53

29 DGPU_PW MSEL#

T12 PAD

J50
G42
H47
G34

NV_DQS0
NV_DQS1

AV9
BG8

+3VS
MC74VHC1G08DFT2G_SC70-5

PCI_PLOCK#
PCI_PERR#
PCI_PIRQE#
PCI_STOP#

AY9
BD1
AP15
BD8

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

2
2
2
2

PCI_PIRQA#
PCI_PIRQG#
PCI_PIRQC#
PCI_SERR#

NVRAM

1
1
1
1

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

REV1.0

R556
R557
R559
R560

2
2
2
2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

USB

R554
R555
R581
R579

1
1
1
1

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

PCI

U41E

+3VS

R160
R588
R585
R158

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

PCH (5/9) PCI, USB, VRAM


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

W ednesday, January 06, 2010

Sheet
1

17

of

59

Rev
1.0

+3VS

+3VS

2 10K_0402_5% DGPU_EDIDSEL#
2 10K_0402_5% DGPU_HPD_INT#

EC_GA20

37

DGPU_PWR_EN Pull Low at Page 43

37

2 10K_0402_5% DGPU_PW R_EN

R236 1
R658 1
R155 1

2 10K_0402_5% PCH_GPIO48
2 10K_0402_5% PCH_TEMP_ALERT#
2 10K_0402_5% VGA_PW ROK

17,21 DGPU_HOLD_RST#
R161 1
0_0402_5%

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 10K_0402_5% VGA_PRSNT_L#
2 10K_0402_5% DGPU_HOLD_RST#

R154 1 @

2 10K_0402_5% DGPU_PW ROK_1

R263 1 @

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AM3

CLK_CPU_BCLK# 5

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

AM1

CLK_CPU_BCLK 5

AB12

GPIO27

V13

GPIO28

PCH_GPIO34

M11

STP_PCI# / GPIO34

PCH_GPIO35

V6

2 10K_0402_5% PCH_GPIO27

+3VS

R656
10K_0402_5%

CRT_DET
B

2
G
2N7002E-T1-GE3_SOT23-3

BE10

THRMTRIP#

BD10

BA22

TP2

AW22

VGA_PRSNT_R#

V3

SLOAD / GPIO38

TP3

BB22

PCH_GPIO39

P3

SDATAOUT0 / GPIO39

TP4

AY45

PCH_GPIO45

H3

PCIECLKRQ6# / GPIO45

TP5

AY46

RST_GATE

F1

PCIECLKRQ7# / GPIO46

TP6

AV43

SDATAOUT1 / GPIO48

TP7

AV45

SATA5GP / GPIO49

TP8

AF13

AB6

GPIO19

GPIO37

PCH_GPIO19

VGA_PRSNT_L#

0
0
1

0
1
0

Q20
@
S

GPIO27

On-Die
voltage regulator enable
On-Die PLL Voltage Regulator disable

Note: the internal pull-up is disabled


after RSMRST# de-asserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the
On-Die PLL Voltage Regulator is disabled.

EC_KBRST# 37
H_CPUPW RGD

THRMTRIP_PCH#

2
R221

1
56_0402_5%

H_THERMTRIP#

H_THERMTRIP# 5

1
56_0402_5%

+1.05VS_PCH

2009/08/23
Series resistor of 565%
Pull-up of 565% to VTT
(both these should be close to PCH)

SATACLKREQ# / GPIO35
TP1

PCH_TEMP_ALERT# AA4

H_PECI 5
EC_KBRST#

2
R220

SATA3GP / GPIO37

On-Die PLL Voltage Regulator


This signal has a weak internal pull up

PROCPWRGD

SATA2GP / GPIO36

This signal has a weak internal pull up


can't Pull low

T1

AB7

GPIO8

H
L

RCIN#

BG10

AB13

CRT_DET#

30

PECI

VGA_PRSNT_L#

High: CRT Plugged

dGPU
iGPU
* SG

SCLOCK / GPIO22

DGPU_PW R_EN

PCH_GPIO57

GPIO27 (Have internal Pull-High)


High: VCCVRM VR Enable
Low: VCCVRM VR Disable

EC_GA20 37

TACH0 / GPIO17

PCH_GPIO48

2 10K_0402_5% PCH_GPIO35

EC_GA20

SATA4GP / GPIO16

PCH_GPIO28

21,37 PCH_TEMP_ALERT#

U2

F38

(GPIO27 Have Internal Pull High) PCH_GPIO27

RST_GATE

A20GATE

AA2

GPIO24

10

DGPU_PW ROK_1

H10

21 VGA_PRSNT_L#

R659 1

AF48
AF47

DGPU_HOLD_RST#

PCH_GPIO24

14,21,39,43 DGPU_PW R_EN

R262 1 DIS@

LAN_PHY_PWR_CTRL / GPIO12

Y7

21 PCH_GPIO28

PCH_GPIO28
PCH_GPIO57
PCH_GPIO45
RST_GATE

R229 1

2 10K_0402_5%

GPIO8

PCH_GPIO22

2 10K_0402_5% PCH_GPIO24

1
1
1
1

CLKOUT_PCIE7N
CLKOUT_PCIE7P

GPIO15

10/7 Not Use PCH_GPIO15 PU 1K to +3V


R642
R640
R633
R630

F10

T7

2 1K_0402_5% PCH_GPIO15

R242 1

TACH3 / GPIO7

EC_SMI#

(GPIO15 Have Internal Pull Down) PCH_GPIO15

2 10K_0402_5% PCH_GPIO12
2 10K_0402_5% EC_SMI#

R239 1

J32

(GPIO8 Have Internal Pull High,Should not be Pull-Low)

2009/09/07 GPIO24 pull high +3V

R245 1
R246 1

TACH2 / GPIO6

EC_SCI#

K9

2 10K_0402_5% PCH_GPIO34
2 10K_0402_5% EC_SCI#

+3V

TACH1 / GPIO1

D37

AH45
AH46

PCH_GPIO12

51 VGA_PW ROK
R243 1
R178 1

EC_SMI#

C38

DGPU_HPD_INT#

CLKOUT_PCIE6N
CLKOUT_PCIE6P

MAINPW ON 45,46,48

+1.05VS_PCH

R224
@ 330_0402_5%
1
2

2
B
E

R264 1 @

EC_SCI#

DGPU_EDIDSEL#

CPU

2 10K_0402_5% PCH_GPIO39

BMBUSY# / GPIO0

F8

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

GPIO57

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

RSVD

R651 1

31 DGPU_HPD_INT#

Y3

GPIO

2 10K_0402_5% PCH_GPIO22

2 10K_0402_5%

CRT_DET

CRT_DET

MISC

21

29 DGPU_EDIDSEL#
R238 1

R654 1

EC_KBRST# R653 1

U41F

R655 1
2 10K_0402_5% VGA_PRSNT_R#
R261 1 UMAO@ 2 10K_0402_5% VGA_PRSNT_L#

NCTF

R582 1
R583 1

TP9

M18

TP10

N18

TP11

AJ24

TP12

AK41

TP13

AK42

TP14

M32

TP15

N32

TP16

M30

TP17

N30

TP18

H12

TP19

AA23

NC_1

AB45

NC_2

AB38

NC_3

AB42

NC_4

AB41

NC_5

T39

INIT3_3V#

REV1.0

TP24

Q14
2SC2411K_SOT23-3
@

H_THERMTRIP#

INIT3_3V

P6

2009/08/23
(Have internal PH,Do not pull down)

C10

TP24_SST

This signal has weak internal


PH, can't pull low

PAD T21

IBEXPEAK-M_FCBGA107

GPIO15
L Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

H Intel ME Crypto Transport


Layer Security(TLS) chiper suite
with confidentiality

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CRB has a 1-k pull-up on this signal


to +3.3VA rail.
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

PCH (6/9) GPIO, CPU, MISC


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

18

of

59

Rev
1.0

Need Modify
180 ohm @
100MHz Bead
+1.05VS_VTT
+1.05VS_PCH

+3VS

Near AB24
Top Side

Near AB24

Intel suggest follow CRB 8/21

All Ibex Peak-M Power rails with netnames +1.1VS and


+1.1V rails are actually +1.05VS and +1.05V rails

DG 1.6 (Page 329)


Have Internal VRM

+1.05VS_PCH

10U_0805_10V4Z
1
C719

Near AN20
1
C321

Top Side

1U_0402_6.3V4Z
1
C342

C345

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1

C348

1U_0402_6.3V4Z

Follow Intel suggestion 8/21

+3VS

Near AN35
0.1U_0402_16V4Z
C329 2
1

+VCCVRM

10mil

DG 1.6 (Page 329) T9 PAD


Have Internal VRM

+VCCAPLL_FDI

+1.05VS_PCH

VSSA_DAC[2]

AF51

300mA

42mA

VCCALVDS

AH38

VSSA_LVDS

AH39

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

AP43
AP45
AT46
AT45

VCC3_3[2]

AB34

VCC3_3[3]

AB35

VCC3_3[4]

AD35

VCCAPLLEXP

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

AN30
AN31

VCCIO[54]
VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

LVDS

BJ24

VCCIO[24]

VCCIO[1]

C331

VCCVRM[2]

3208mA

61mA

C291
10U_0805_10V4Z
2

0.1U_0402_16V4Z
2

+VCCA_LVDS

1
2
L19
MBK1608221YZF_2P

Near AE50

VCCDMI[2]

AU16

220 ohm bead,350mA

+3VS

CRB 0.9 is 180 ohm @ 100MHz


DG0.8 is 600 ohm FB (Page 290)

R138 1 UMA@ 2 0_0805_5%

+1.8VS

Near AP43

15mil

+VCCTX_LVDS
C300
C316 1
UMA@ 1
1
0.01U_0402_16V7K
22U_0805_6.3V6M
C304
UMA@
0.01U_0402_16V7K
2
2
UMA@ 2

L20 UMA@
2
1
0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA


1 DISO@ 2
R145
0_0402_5%

+3VS

Near AB34
R186 1 @

2 0_0805_5%

+1.05VS_PCH

R192 1

2 0_0805_5%

+1.8VS

+VCCVRM

AT24

VCCDMI[1]

156mA

C298

R172
0_0402_5%
DISO@

40mil

AT16

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

0.01U_0402_16V7K
1
C296

R136
0_0402_5%
@

0.1U_0402_16V4Z
2

35mA

6mA

+VCCADAC

AF53

HVCMOS

@ +VCCAPLL_EXP

VSSA_DAC[1]

59mA
AK24

T20 PAD

AE52

20mil

+1.05VS_PCH

10mil

AE50

VCCADAC[2]

DMI

Short J4 for PCH VCCCORE

VCCADAC[1]

69mA

C344

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]1524mA
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

60mA

C718

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

15mil

1U_0402_6.3V4Z
1

CRT

10U_0805_10V4Z
1

NAND / SPI

PCI E*

@ JUMP_43X118

FDI

2
D

POWER

U41G

VCC CORE

J1

+1.05VS_PCH

10mil
+VCC_DMI

R204 1

2 0_0805_5%

1
C368
1U_0402_6.3V4Z
2

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

Near AT16

+1.8VS

C372

0.1U_0402_16V4Z
2

85mA
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AM8
AM9
AP11
AP9

Near AK13
+3VS

C387

REV1.0
IBEXPEAK-M_FCBGA107

0.1U_0402_16V4Z
2

Near AM8

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCH (7/9) PWR


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

19

of

59

Rev
1.0

C367

Near AF23

0.1U_0402_16V4Z
2

Near Y20

DG2.0 Table162 Note2 (C295 unpop)


+1.05VS_PCH

1
C293

22U_0805_6.3V6M
1

22U_0805_6.3V6M

VCCME[1]
VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

Near AD38

@
C295
C324
22U_0805_6.3V6M 1U_0402_6.3V4Z
2
2

C341

1U_0402_6.3V4Z

Near V39

All Ibex Peak-M Power rails with netnames +1.1VS and


+1.1V rails are actually +1.05VS and +1.05V rails
C390
10mil
0.1U_0402_16V4Z
+VCCRTCEXT
1
2

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

AU24

+VCCVRM

20mil
+VCCADPLLA

20mil
+VCCADPLLB

+1.05VS_PCH

Near AH23
1
C330
1U_0402_6.3V4Z

Near AF32

C351

+PCH_VCCIO
2
0_0603_5%
2
1
C336
1U_0402_6.3V4Z

1
R139

1U_0402_6.3V4Z

Near AH35
10mil
10mil

+3V

V12

+VCCSUS
1
2
C353
Near
0.1U_0402_16V4Z

Y22

0.1U_0402_16V4Z

BB51
BB53

VCCME[12]

DCPRTC

VCCVRM[3]

72mA
VCCADPLLA[1]
VCCADPLLA[2]

73mA

BD51
BD53

VCCADPLLB[1]
VCCADPLLB[2]

AH23
AJ35
AH35

VCCIO[21]
VCCIO[22]
VCCIO[23]

AF34

VCCIO[2]

AH34

+VCCSST
1
2
C375
Near
0.1U_0402_16V4Z

C369

V9

AF32

VCCIO[4]

V12

DCPSST

Y22

4.7U_0805_10V4Z

C359

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
Near

V5REF

357mA
VCC3_3[8]

J38

VCC3_3[9]

L38

AU18

AT18

20mil

A12

VCC3_3[7]

> 1mA
V_CPU_IO[1]
V_CPU_IO[2]

2mA
VCCRTC

+3V

C386

C377

IBEXPEAK-M_FCBGA107

+1.05VS_PCH

+VCC5REFSUS

10mil

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

Near A12

10mil

+5V

R189
2 100_0402_5%

C349
1U_0402_6.3V6K

+VCC5REF

C692
1U_0402_6.3V4Z

Near BD51

D4
CH751H-40PT_SOD323-2
R141
100_0402_5%
1
2

Near F24
Change to 1U for power
sequence issue on ICH9

2/12 Follow EDS1.11


Change to 100 ohm

+5VS

C299
1U_0402_6.3V6K

Near K49
+3VS

N36
P36

C337

VCC3_3[13]

U35

0.1U_0402_16V4Z
2

VCC3_3[14]

AD13

Near J38
+3VS

Near AD13
10mil
+VCCSATAPLL @

2 C376
0.1U_0402_16V4Z

PAD T23

DG 1.6 (Page 329)


Have Internal VRM
B

VCCIO[9]

AH22

VCCVRM[4]

AT20

VCCIO[10]

AH19

VCCIO[11]

AD20

VCCIO[12]

AF22

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

AD19
AF20
AF19
AH20

C371
1U_0402_6.3V4Z
2

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

AB19
AB20
AB22
AD22

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

AA34
Y34
Y35
AA35

+VCCVRM
+1.05VS_PCH

+5VALW

Near AB19

43

SBPW R_EN#

PCH_VCCME13
PCH_VCCME14
PCH_VCCME15
PCH_VCCME16

R179
R164
R165
R173

1
1
1
1

2
2
2
2

L30

R176
0_0402_5%
2 @
1
C343
@
0.1U_0402_16V4Z

+1.05VS_PCH

15mil

Q8

R169
0_0402_5%

@
D
AO3413L_SOT23-3

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

+5V

+3V
C357 1

2 1U_0402_6.3V4Z

Near L30

C373
1U_0402_6.3V4Z

+VCCADPLLB

+3VS

2/12 Follow EDS1.11


Change to 100 ohm

VCC3_3[12]

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

D5
CH751H-40PT_SOD323-2

+RTCVCC

Near U23

C689
220U_B2_2.5VM_R35

M36

6mA

R562
0_0402_5%
@

2
1U_0402_6.3V4Z

VCC3_3[11]

VCCSUSHDA

C691
@

L61
1
2
10UH_LB2012T100MR_20%

VCC3_3[10]

AK3
AK1

C688
220U_B2_2.5VM_R35

10uH inductor, 120mA 1

10mil
K49

0.1U_0402_16V4Z
2

Near A26

>1mA

DCPSUS

VCCSUS3_3[29]

C360

F24

32mA

P18

Near V15

V5REF_SUS

>1mA

VCCSATAPLL[1]
VCCSATAPLL[2]

U19

AT18
C364

VCCIO[56]

V23

0.1U_0402_16V4Z
2

RTC

+1.05VS_PCH

U23

C347

VCCIO[3]

+3VS

0.1U_0402_16V4Z

VCCSUS3_3[28]

C350

+1.05VS_PCH

Near P18

C370

163mA

VCCME[5]

AF42

Y42

Near V9

1998mA

AD39

AF41
1

DCPSUSBYP

AD38

Follow Intel suggestion

C294

Y20

Near BB51

L60
1
2
10UH_LB2012T100MR_20%

10uH inductor, 120mA 1

+PCH_VCCD6W

+3V

Near V24

10mil

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

09/09/14 WW37 remove


+VCCADPLLA
+VCCADPLLA,+VCCADPLLB external 1U

C352
1U_0402_6.3V4Z
2
@

HDA

R199
0_0402_5%

USB

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

+1.05VS_PCH

C340
1U_0402_6.3V4Z
2

VCCLAN[2]

+1.05VS_PCH

AF24

+VCCLAN

344mA

SATA

V24
V26
Y24
Y26

VCCLAN[1]

PCI/GPIO/LPC

R187 1
0_0603_5%

15mil

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

AF23

+1.05VS_PCH

VCCACLK[2]

AP53

VCCACLK[1]

Clock and Miscellaneous

DG 1.6 (Page 329)


Have Internal VRM

REV1.0

52mA

AP51

PCI/GPIO/LPC

10mil

+1.1VS_VCCACLK

POWER

U41J
@

T17 PAD

CPU

Title

PCH (8/9) PWR


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

20

of

59

Rev
1.0

U41H

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AB16

VSS[0]

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

PCH XDP Port

REV1.0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

17 USB_OC#0_R

R314 1 @

2 33_0402_5%

XDP_FN0

17 USB_OC#2_R

R311 1 @

2 33_0402_5%

XDP_FN2

17 USB_OC#4_R

R306 1 @

2 33_0402_5%

XDP_FN4

R312
R310
R309
R307
R305
R304
R300
R297

2
2
2
2
2
2
2
2

14 PCH_GPIO20
14 PCH_GPIO18
13 PCH_GPIO21
13 PCH_GPIO19
14,18,39,43 DGPU_PW R_EN
18 VGA_PRSNT_L#
17,18 DGPU_HOLD_RST#
18,37 PCH_TEMP_ALERT#
18

CRT_DET

13 PCH_JTAG_TCK
13 PCH_JTAG_TMS
13 PCH_JTAG_TDI
13 PCH_JTAG_TDO

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15

R313 1 @

2 33_0402_5%

XDP_FN17

R287
R284
R286
R293

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
2
0_0402_5%
2 0_0402_5%

1
1
1
1
1
1
1
1

@
@
@
@
@
@
@
@

1
1
1
1

R289 1 @

13 PCH_JTAG_RST#

PCH_JTAG_RST#_R

JP3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

XDP_FN0

(XDP_FN1) 17 USB_OC#1_R
XDP_FN2

(XDP_FN3) 17 USB_OC#3_R

XDP_FN4

(XDP_FN5) 17 USB_OC#5_R
(XDP_FN6) 17 USB_OC#6_R
(XDP_FN7) 17 USB_OC#7_R
15 SYS_PW ROK
5,15,37 PBTN_OUT#
+3VS

1
R296

2
0_0402_5%

5 SMB_DATA_S3
5 SMB_CLK_S3
PCH_JTAG_TCK_R

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
CONN@

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

(XDP_FN16)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

PCH_GPIO28 18

XDP_FN17
XDP_FN8
XDP_FN9

XDP_FN10
XDP_FN11

XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
+3VS

2
1
R295
1K_0402_5%
PCH_JTAG_TDO_R
PCH_JTAG_RST#_R
PCH_JTAG_TDI_R
PCH_JTAG_TMS_R

PLT_RST# 5,17,33,37
XDP_DBRESET# 5,15

SAMTE_BSH-030-01-L-D-A
B

+3VS

12,14,35 PCH_SMBDATA

IBEXPEAK-M_FCBGA107

R294
@
4.7K_0402_5%
1
2

+3VS

SMB_DATA_S3

Q21A
DMN66D0LDW -7_SOT363-6
@
+3VS
R290
@
4.7K_0402_5%
1
2

12,14,35 PCH_SMBCLK

+3VS

SMB_CLK_S3

Q21B
DMN66D0LDW -7_SOT363-6
@

REV1.0

Compal Electronics, Inc.

Compal Secret Data

Security Classification

IBEXPEAK-M_FCBGA107

2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PCH_JTAG_TCK_R
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R

U41I

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

Title

PCH (9/9) VSS & PCH XDP Port


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Thursday, January 07, 2010

Sheet
1

21

of

59

Rev
1.0

4 PEG_GTX_HRX_N[0..15]
4 PEG_GTX_HRX_P[0..15]
4 PEG_HTX_C_GRX_N[0..15]
4 PEG_HTX_C_GRX_P[0..15]

add for VB support.


R73
10K_0402_5%
1 VGA@ 2

U34G

LVDS CONTROL

GFX PCIE LANE REVERSAL

VARY_BL
DIGON

AK27
AJ27

VGA_PNL_PWM 29
ENVDD
29

R76
1 VGA@ 2
10K_0402_5%

U34A

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

T35
R36

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33
W32

PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PEG_GTX_HRX_P2
PEG_GTX_HRX_N2

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30
U29

PEG_GTX_HRX_P3
PEG_GTX_HRX_N3

PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

R38
P37

PCIE_RX6P
PCIE_RX6N

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

P35
N36

PCIE_RX7P
PCIE_RX7N

PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8

N38
M37

PCIE_RX8P
PCIE_RX8N

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9

M35
L36

PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10

L38
K37

PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11

K35
J36

PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12

J38
H37

PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13

H35
G36

PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14

G38
F37

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

F35
E37

PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

U38
T37

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_TX4P
PCIE_TX4N

PCIE_TX6P
PCIE_TX6N

P33
P32

PEG_GTX_HRX_P6
PEG_GTX_HRX_N6

PCIE_TX7P
PCIE_TX7N

P30
P29

PEG_GTX_HRX_P7
PEG_GTX_HRX_N7

PCIE_TX8P
PCIE_TX8N

N33
N32

PEG_GTX_HRX_P8
PEG_GTX_HRX_N8

N30
N29

PEG_GTX_HRX_P9
PEG_GTX_HRX_N9

L33
L32

PEG_GTX_HRX_P10
PEG_GTX_HRX_N10

L30
L29

PEG_GTX_HRX_P11
PEG_GTX_HRX_N11

K33
K32

PEG_GTX_HRX_P12
PEG_GTX_HRX_N12

J33
J32

PEG_GTX_HRX_P13
PEG_GTX_HRX_N13

K30
K29

PEG_GTX_HRX_P14
PEG_GTX_HRX_N14

H33
H32

PEG_GTX_HRX_P15
PEG_GTX_HRX_N15

PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N

AG38
AH37
AF35
AG36

AP34
AR34

VGA_TXCLK+
VGA_TXCLK-

AW37
AU35

VGA_TXOUT0+
VGA_TXOUT0-

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

VGA_TXOUT1+
VGA_TXOUT1-

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

VGA_TXOUT2+
VGA_TXOUT2-

TXOUT_L3P
TXOUT_L3N

AN36
AP37

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

PEG_GTX_HRX_P4
PEG_GTX_HRX_N4

T33
T32

PEG_GTX_HRX_P5
PEG_GTX_HRX_N5

PCIE_TX9P
PCIE_TX9N

AK35
AL36

LVTMDP

T30
T29

PCIE_TX5P
PCIE_TX5N

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

VGA_TXCLK+ 29
VGA_TXCLK- 29
VGA_TXOUT0+ 29
VGA_TXOUT0- 29
VGA_TXOUT1+ 29
VGA_TXOUT1- 29
C

VGA_TXOUT2+ 29
VGA_TXOUT2- 29

216-0729002 A12 M96_BGA962


MADI@

CLOCK
AB35
AA36

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

For M96, AH16 is NC


2 VGA@ 1
R498
10K_0402_5%
17 PLTRST_VGA#

AJ21
AK21
AH16
AA30

NC#1
NC#2
NC_PWRGOOD

PCIE_CALRP
PCIE_CALRN

Y30

R55

1 VGA@ 2

1.27K_0402_1%

Y29

R52

1 VGA@ 2

2K_0402_1%

+1.0VSDGPU

PERSTB
216-0729002 A12 M96_BGA962
MADI@

Park XT P/N : SA00003M500 (S IC 216-0774009 A11 PARK XT S3 631P C38)


Madision Pro P/N : SA00003M300 ( S IC 216-0772000 MADISON PRO FCBGA 0FA)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

2010/08/01

Deciphered Date

Title

M96_ PCIE / LVDS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

22

of

59

Rev
1.0

U34B

Pin Straps description <all internal PD>

+3VSDGPU

BIOS_ROM_EN

b) If BIOS_ROM_EN = 0, then Config[2:0] defines


the primary memory aperture size.

GPIO22

001

Enable external BIOS ROM device


0: Diable, 1: Enable

00: No audio function;


10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

AUD[1]
AUD(0)

HSYNC
VSYNC

BIF_GEN2_EN

GPIO2

RESERVED

H2SYNC
GPIO8
GPIO21

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

11

Internal use only. THIS PAD HAS AN INTERNAL PULL-DOWN AND MUST
BE 0 V AT RESET. The pad may be left unconnected

NC on Park
+3VSDGPU

16,37

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2

R71

2 10K_0402_5%

VGA_AC_DET

R95

2 10K_0402_5%

SOUT_GPIO8

R93

2 10K_0402_5%

SIN_GPIO9

R113
R112
R110
R96
R109

1 VGA@
@
1
@
1
@
1
@
1

2
2
2
2
2

DGPU_BKL_EN
1 DISO@ 2
R103
0_0402_5% DISCRETE

ENBKL

1 VGA@
1 VGA@

2 4.7K_0402_5%
2 4.7K_0402_5%

VGA_LCD_CLK
VGA_LCD_DATA

29 VGA_LCD_CLK
29 VGA_LCD_DATA

15,37

@
CH751H-40PT_SOD323-2
1
2
D3

EC_ACIN

VGA_AC_DET
DGPU_BKL_EN
SOUT_GPIO8
SIN_GPIO9
CLK_GPIO10
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

VRAM_ID0

R104

10K_0402_5%

0
T1

@
THM_ALERT#
GPU_VID1

GPU_VID1

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

1 VGA@

2 499_0402_1%

R101

1 VGA@

2 249_0402_1%

2 C244
0.1U_0402_16V4Z

20mil
1

TESTEN

@
2
0_0402_5%

VGA_CLK_27M_R
1

External 27MHZ 3.3V CLK

L11
BLM18AG121SN1D_0603
2
1
VGA@

SM010030010
200ma 120ohm@100mhz DCR 0.2

C802
12P_0402_50V8J
@
+1.8VSDGPU

XTALOUT

24

+DPLL_VDDC
1
1
VGA@
VGA@
2

TXCDP_DPD3P
TXCDM_DPD3N

TX4P_DPD1P
TX4M_DPD1N
TX5P_DPD0P
TX5M_DPD0N

SCL
SDA
R
RB

HSYNC
VSYNC
RSET

70mA
45mA

VGA_SMB_CK2

AU16
AV15
AT17
AR16

VGA_SMB_DA2

G2
G2B
B2
B2B
C
Y
COMP
H2SYNC
V2SYNC

HPD1

50mA

VDD2DI
VSS2DI

20mA

A2VDD
A2VDDQ

VREFG

DDC/AUX

20mil

AN31

DPLL_PVDD
DPLL_PVSS

27MCLK
XTALOUT

AV33
AU34

DPLL_VDDC

120mA

DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N

AK32
AJ32
AJ33

VGA@

DDC1CLK
DDC1DATA
AUX1P
AUX1N

150mA

XTALIN
XTALOUT

DPLUS
DMINUS

THERMAL

DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
TSVDD
TSVSS

EC_SMB_DA2

+3VSDGPU

14,37

EC_SMB_DA2

14,37

R120
@
0_0603_5%

NC on Park

AU22
AV21

+3VS

+3VSDGPU

AO3413L_SOT23-3
Q6
100mA
3
1

AT23
AR22

AD39
AD37

VGA_CRT_R

30

AE36
AD35

VGA_CRT_G

30

AF37
AE38

VGA_CRT_B

AC36
AC38

VGA_CRT_HSYNC
VGA_CRT_VSYNC
R53

VGA@
1

AD34
AE34

+AVDD

AC33
AC34

+VDD1DI

R128
100K_0402_5%
VGA@

30

VGA@
1
1
C609
C279
VGA@
VGA@
0.1U_0402_16V7K
10U_0805_6.3V6M
2
2
R739
1 VGA@ 2
Q4
24K_0402_1%
VGA@

R129

30
30

39,43,51,52

499_0402_1%

10mil

2
1
0_0402_5%
VGA@
C289
0.1U_0402_16V4Z
VGA@

VGA_ON

L3
BLM18AG121SN1D_0603
1
+1.8VSDGPU
VGA@

R106
470_0603_5%
VGA@

2VGA_ON#
G
S
2N7002E-T1-GE3_SOT23-3

D
Q7
VGA@

2
G
S

2N7002E-T1-GE3_SOT23-3
43,51,52

VGA_ON#

1 VGA@ 1 VGA@ 1 VGA@

10mil

AC30
AC31
AD30
AD31

L8
BLM18AG121SN1D_0603
1
+1.8VSDGPU
VGA@

1 VGA@ 1 VGA@ 1 VGA@

AF30
AF31

AC32
AD32
AF32
AD29
AC29

H2SYNC
V2SYNC

AG31
AG32

+VDD1DI

AG33

+A2VDD

AD33

+A2VDDQ

SM010030010
200ma 120ohm@100mhz DCR 0.2

+3VSDGPU

10mil
+3VSDGPU

10mil

10mil

AF33

R56
715_0402_1%
1 VGA@ 2

AA29

20mA

DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

AM26
AN26

VGA_HDMI_SCLK
VGA_HDMI_SDATA

@
1

VGA_HDMI_SCLK 31
VGA_HDMI_SDATA 31

AM27
AL27

V2SYNC
H2SYNC

R107 1
R114 1

VGA_CRT_VSYNC
VGA_CRT_HSYNC

R447 1 VGA@
R460 1 VGA@

Strap

2 10K_0402_5%
2 10K_0402_5%

VGA_HDMI_SCLK
VGA_HDMI_SDATA
VGA_DDC_CLK
VGA_DDC_DATA

R506
R511
R118
R119

2
2
2
2

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

HDMI

VGA@

AN20
AM20
AL30
AM30
AL29
AM29
AN21
AM21

VGA@

2 10K_0402_5%
2 10K_0402_5%

VGA@
VGA@
VGA@
VGA@

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 150_0402_1%
2 150_0402_1%
2 150_0402_1%

VGA@

FLASH ROM
U8

NC on Park
VGA_DDC_CLK
VGA_DDC_DATA

VGA_DDC_CLK 30
VGA_DDC_DATA 30

CRT

AK30
AK29

SIN_GPIO9

CLK_GPIO10

ROMSE_GPIO22

1
7

+3VSDGPU

AJ30
AJ31

2
R94
2
R86

NC on Park

@
@

1
0_0402_5%
1
0_0402_5%
2
@

2009/08/01

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

3
8

SOUT_GPIO8

C
S

TYPE 1

HOLD

W
VCC

VSS

M25P10-AVMN6P
C227
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1
1
1
1

R462 1 VGA@
R463 1 VGA@
R465 1 VGA@

1
216-0729002 A12 M96_BGA962
MADI@

@
@

@
1

+1.8VSDGPU
1

AM19
AL19

Issued Date

EC_SMB_CK2

DAC2

PLL/CLOCK
AM32
AN32

EC_SMB_CK2

Q5A DMN66D0LDW-7_SOT363-6
VGA@

AT21
AR20

AB34

+3VSDGPU

Q5B DMN66D0LDW-7_SOT363-6
VGA@

AU20
AT19

R2SET

10mil

VDD1DI
VSS1DI

A2VSSQ

AF29
AG29

AVDD
AVSSQ

R2
R2B

130mA

GPU_THERM_D+
GPU_THERM_D-

VGA@

B
BB

DAC1

VGA@

+TSVDD
1

G
GB

20mil
AH13

1 VGA@ 2
R102
4.7K_0402_5%

Not share via for other GND

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG

THM_ALERT#

R115
4.7K_0402_5%
VGA@

Title

M96_Strape/DP/HDMI//CRT
Size
C
Date:

VGA_SMB_DA2

GND

VGA@

C180
0.1U_0402_16V4Z

27MHZ_16PF_X5H027000FG1H
VGA@
C647
VGA@
18P_0402_50V8J

C221
1U_0402_6.3V4Z

2
2

L7
BLM18AG121SN1D_0603
2
1
VGA@
1
VGA@

Y1

C635
VGA@
18P_0402_50V8J

C220
10U_0603_6.3V6M

2
1 27MCLK
R500
1M_0402_5%
VGA@

VGA_SMB_CK2

C218
10U_0603_6.3V6M

2
10K_0402_5%

AT15
AR14

C216
0.1U_0402_16V4Z

ALERT#

+3VSDGPU

C215
1U_0402_6.3V4Z

1
R720

TX2P_DPC0P
TX2M_DPC0N

+DPLL_PVDD

C197
1U_0402_6.3V4Z

+3VSDGPU

+1.0VSDGPU

VGA@

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AK24

+VGA_VREF

C236
1U_0402_6.3V4Z

L15
BLM18AG121SN1D_0603
2
1
VGA@
1
C249
VGA@
10U_0603_6.3V6M

C196
0.1U_0402_16V4Z

JTAG_TMS
2
10K_0402_5%

DTHERM#

C600
10U_0603_6.3V6M

R100

C243
10U_0603_6.3V6M

JTAG_TRSTB
2
10K_0402_5%

1
R509

VGA_HDMI_DET

12 VGA_CLK_27M

GENERICC

C189
0.1U_0402_16V4Z

2009/09/18 For AMD roger


FIX intermittent system boot up hangs issue

SDATA

R108
4.7K_0402_5%
VGA@

C172
0.1U_0402_16V4Z

+1.8VSDGPU

AU14
AV13

C599
1U_0402_6.3V4Z

T5

1
VGA@

X76@

1
R718

AT33
AU32

C219
10U_0603_6.3V6M

+1.8VSDGPU

PD-Reset

1
R717

SCLK

D+

+3VSDGPU

C154
0.1U_0402_16V4Z

T6
VGA_CLK_27M_R
JTAG_TMS

31 VGA_HDMI_DET

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

+3VSDGPU

VDD

ADM1032ARMZ-2REEL_MSOP8
VGA@

AR32
AT31

C156
1U_0402_6.3V4Z

X76@

JTAG_TRSTB

Park NC pins

R478
10K_0402_5%

X76@

R477
10K_0402_5%

R474
10K_0402_5%

R483
10K_0402_5%

R492
10K_0402_5%

X76@

R473
10K_0402_5%

R482
10K_0402_5%

R491
10K_0402_5%

ROMSE_GPIO22

Boot-up Hangs,R717,R718,VGA_CLK_27M_R

X76@

U9
1

AV31
AU30

C188
22U_0805_6.3V6M

GPU_VID0

GPU_VID0

0
51

X76@

AR30
AT29

C182
0.1U_0402_16V4Z

51

Location VRAM_ID3 VRAM_ID2 VRAM_ID1


VRAM_ID0
2009/08/27
VRAM
remove BB_EN
64Mx16
64Mx16
14 PEG_CLKREQ#
Samsung
0
0
0
0
<8PCS>
HYNIX
1
0
0
0
<8PCS>
AMD
1
0
1
0
<8PCS>
2009/09/18 For AMD roger
ID3: VRAM Vender
ID2: VRAM Size ID1: VRAM Vender Ass Option Circuit for Solve Intermittent System
X76@

TX1P_DPC1P
TX1M_DPC1N

GPU_THERM_D+
2200P_0402_50V7K
VGA@
1
2
C247
GPU_THERM_D-

C181
1U_0402_6.3V4Z

Madison(Pro)

X76@

TX0P_DPC2P
TX0M_DPC2N
DPC

GENERAL PURPOSE I/O

2 VGA@

+1.8VSDGPU

TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N

I2C
AK26
AJ26

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2

16 DGPU_BKL_EN

Location VRAM_ID3 VRAM_ID2 VRAM_ID1


VRAM
64Mx16
64Mx16
Samsung
0
1
0
<4PCS>
HYNIX
1
1
0
<4PCS>
AMD
1
1
1
<4PCS>

TX4P_DPB1P
TX4M_DPB1N

DPD

R117
R116

ONLY

Park(XT)

DPB

TX3P_DPD2P
TX3M_DPD2N
+3VSDGPU

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
ROMSE_GPIO22
GENERICC

10K_0402_5%
10K_0402_5%
10K_0402_5%
3K_0402_5%
10K_0402_5%

TX3P_DPB2P
TX3M_DPB2N

VGA_HDMI_TXD2+ 31
VGA_HDMI_TXD2- 31

R74 1 VGA@
R111 1 VGA@
R487 1
@

TXCBP_DPB3P
TXCBM_DPB3N

VGA_HDMI_TXD1+ 31
VGA_HDMI_TXD1- 31

AT27
AR26

GPIO13
GPIO12
GPIO11

CONFIG[2]
CONFIG[1]
CONFIG[0]

memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010

NC on Park

AU26
AV25

GPIO13,12,11 (config 2,1,0) :


a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.

TX2P_DPA0P
TX2M_DPA0N

GPIO1

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable


0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

TX1P_DPA1P
TX1M_DPA1N
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

1
VGA@

1 1

VGA_HDMI_TXD0+ 31
VGA_HDMI_TXD0- 31

Transmitter Power Saving Enable


0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

AT25
AR24

GPIO0

DPA

TX_PWRS_ENB

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

VGA Disable determines


0: VGA Controller capacity enabled
1: The device will not be recognized as the systems VGA controller

VGA_HDMI_TXC+ 31
VGA_HDMI_TXC- 31

GPIO9

AU24
AV23

VGA_DIS

TXCAP_DPA3P
TXCAM_DPA3N

VIP Device Strap Enable indicates to the software driver


0: Driver would ignore the value sampled on VHAD_0 during reset
1: VHAD_0 to determine whether or not a VIP slave device

V2SYNC

C263
0.1U_0402_16V4Z

VIP_DEVICE_EN

External VGA Thermal Sensor

Setting

Strap Name

Document Number

Rev
1.0

NEW70 M/B LA-5891P Schematic


Thursday, January 07, 2010

Sheet
1

23

of

59

Park is single channel for


memory (channel B only)
U34C

U34D

R33
R40
R65

R34

20mil

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2

WEA0B
WEA1B

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

RSVD#1
RSVD#2
RSVD#3

AF28
AG28
AL31

RSVD#5
RSVD#6

H23
J19

RSVD#9
RSVD#11

VGA@

CLKA0
CLKA0#

27
27

R47
VGA@
40.2_0402_1%

CLKA1
CLKA1#

27
27

RASA0#
RASA1#

27
27

CASA0#
CASA1#

27
27

CSA0#_0

27

CSA1#_0

27

CKEA0
CKEA1

27
27

WEA0#
WEA1#

27
27

R54
VGA@
40.2_0402_1%

MAB13

27
28

VGA@

+1.5VSDGPU

GCORE_SEN 51

MAA13

R44
100_0402_1%
VGA@

2009/08/20 del AG28 VDDCI_SEN

T8
W8

20mil
MVREFDB

In M97, Medison and Park, AF28 is


FB_VDDC, AG28 is FB_VDDCI, AH29 is
FB_GND. GCORE_SEN and FB_GND
should route as differential pair Same
as VDDCI_SEN and FB_GND

2009/09/18
change R64 PD change
to +3VSDGPU
23

R57
VGA@
100_0402_1%

R64
10K_0402_5%
TESTEN
1
2
VGA@
TEST_MCLK
TEST_YCLK

MVREFSB
1
VGA@

MVREFDB Y12
MVREFSB AA12

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
QSB_0B/WDQSB_0
QSB_1B/WDQSB_1
QSB_2B/WDQSB_2
QSB_3B/WDQSB_3
QSB_4B/WDQSB_4
QSB_5B/WDQSB_5
QSB_6B/WDQSB_6
QSB_7B/WDQSB_7
ODTB0
ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

WEB0B
WEB1B

TESTEN

20mil

M96 no support

216-0729002 A12 M96_BGA962


MADI@

If use M96 upper resistor will


change to 100ohm for
MVREFDA/B and MVREFSA/B

GCORE_SEN

CLKA1
CLKA1B

27
27

CLKA0
CLKA0B

+1.5VSDGPU
ODTA0
ODTA1

H27
G27

QSA#[0..7] 27

ODTA0
ODTA1

QSA#[0..7]

27

VGA@
1

If use M96 upper resistor will


change to 100ohm for
MVREFDA/B and MVREFSA/B VGA@ R72

51.1_0402_1%

AD28
AK10
AL10

C193
0.1U_0402_16V4Z

J21
G19

QSA[0..7]

C184
0.1U_0402_16V4Z

R35
VGA@
100_0402_1%

C80
0.1U_0402_16V4Z

1 VGA@ 2
L27
1 VGA@ 2 240_0402_1% N12
1 VGA@ 2 240_0402_1% AG12
240_0402_1%
1 VGA@ 2
M12
1 VGA@ 2 240_0402_1% M27
1 VGA@ 2 240_0402_1% AH12
240_0402_1%

ODTA0
ODTA1

QSA[0..7]

C147
0.1U_0402_16V4Z

R38
R39
R70

MVREFSA

40.2_0402_1%
VGA@

L18
L20

A34
E30
E26
C20
C16
C12
J11
F8

DQMA#[0..7] 27

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

VGA@

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

MAB[0..12] 28

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

DRAM_RST

B_BA[0..2]

DQMB#[0..7] 28

QSB[0..7]

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

QSB#[0..7] 28

ODTB0
ODTB1

28
28

CLKB0
CLKB0#

28
28

CLKB1
CLKB1#

28
28

RASB0#
RASB1#

28
28

CASB0#
CASB1#

28
28

CSB0#_0

28

CSB1#_0

28

CKEB0
CKEB1

28
28

WEB0#
WEB1#

28
28

R63
4.7K_0402_5%
@
1
2

R66
680_0402_5%
1
2
VGA@

AH11

R68

+1.5VSDGPU
VRAM_RST# 27,28

1 C168

VGA@
10K_0402_5%

VGA@
68P_0402_50V8J

R75
VGA@
51.1_0402_1%
M96

M96 use 4.7K to


PD directly.

R159
R159
C659

Issued Date

2009/08/01

10k Ohm
SD028100280
680 Ohm
SD028680080

2010/08/01

Deciphered Date

68 pF
SE071680J80

Title

Memory

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

DNI

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Broadway

4.7k Ohm
SD028470180
0 Ohm
SD028000080
4.7k Ohm
SD028470180
1000 pF
SE074102K80

R228
A

28

QSB#[0..7]

T7
W7

216-0729002 A12 M96_BGA962


MADI@

B_BA[0..2] 28

QSB[0..7]

TESTEN
CLKTESTA
CLKTESTB

DQMB#[0..7]

+1.5VSDGPU

MVREFDA
MVREFSA

QSA_0B/WDQSA_0
QSA_1B/WDQSA_1
QSA_2B/WDQSA_2
QSA_3B/WDQSA_3
QSA_4B/WDQSA_4
QSA_5B/WDQSA_5
QSA_6B/WDQSA_6
QSA_7B/WDQSA_7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

DQMA#[0..7]

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

+1.5VSDGPU

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

A_BA[0..2] 27

C34
D29
D25
E20
E16
E12
J10
D7

QSA_0/RDQSA_0
QSA_1/RDQSA_1
QSA_2/RDQSA_2
QSA_3/RDQSA_3
QSA_4/RDQSA_4
QSA_5/RDQSA_5
QSA_6/RDQSA_6
QSA_7/RDQSA_7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

VGA@

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

A_BA[0..2]

MDB[0..63]

A32
C32
D23
E22
C14
A14
E10
D9

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

MAB[0..12]
28

C78
0.1U_0402_16V4Z

R37
VGA@
100_0402_1%

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

20mil
MVREFDA

R36
VGA@
40.2_0402_1%

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1

+1.5VSDGPU

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

MDB[0..63]

C112
0.1U_0402_16V4Z

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[0..63]

MEMORY INTERFACE A

27

MAA[0..12] 27

MEMORY INTERFACE B

MAA[0..12]
MDA[0..63]

Tuesday, December 29, 2009

Sheet
1

24

of

59

Rev
1.0

2009/09/14
update P/N SM010005500 500ma 600ohm@100MHZ DCR 0.38

U34E

VGA@

C143
1U_0402_6.3V4Z

C116
1U_0402_6.3V4Z

C130
1U_0402_6.3V4Z

VGA@ 2

VGA@

C104
1U_0402_6.3V4Z

VGA@
2

VGA@ 2

C117
1U_0402_6.3V4Z

VGA@ + C1

VGA@ + C2

330U_D2_2V_Y
2

330U_D2_2V_Y

2009/09/17
ADD BIF_VDDCI N27,T27
R716 1 VGA@ 2 0_0603_5%

+VGA_CORE

M97 and Mahattan VDDC and


VDDCI ball assignments are
different from M96, If M96 is
populated on this
design,VDDC and VDDCI
shoudl be shorted.
1 VGA@

1 VGA@

1 VGA@

1 VGA@

1 VGA@

+VDDCI_R
VGA@ 1 VGA@

1 VGA@ 1

2
1
L35
VGA@
FBMA-L11-201209-221LMA30T_0805

C94
1U_0402_6.3V4Z

1 VGA@

C103
1U_0402_6.3V4Z

4A

1 VGA@

C88
1U_0402_6.3V4Z

160mil

1 VGA@

C93
1U_0402_6.3V4Z

VGA@ 1 VGA@

C162
1U_0402_6.3V4Z

2009/08/01

C145
1U_0402_6.3V4Z

VGA@
2

VGA@

C6
10U_0805_6.3V6M

VGA@ 2

C131
1U_0402_6.3V4Z

VGA@
2

C114
1U_0402_6.3V4Z

VGA@
2

VGA@

C7
10U_0805_6.3V6M

VGA@
2

C148
1U_0402_6.3V4Z

VGA@

VGA@ 2

+VGA_CORE

2
1
L34
VGA@
FBMA-L11-201209-221LMA30T_0805

SM010014520 3000ma 220ohm@100mhz DCR 0.04

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VGA@

VGA@ 2

C118
1U_0402_6.3V4Z

2009/08/27
short BBP

VGA@

VGA@ 2

2009/08/27
RemoveBack Biasing

2
216-0729002 A12 M96_BGA962
MADI@

VGA@
2

C514
10U_0805_6.3V6M

M15
N13
R12
T12

C515
10U_0805_6.3V6M

Back Bias is not supported on


M97,Broadway,Madison and Park
Connect to VDDCI directly

ISOLATED VDDCI#1
CORE I/O VDDCI#2
VDDCI#3
VDDCI#4

VGA@
2

C513
10U_0805_6.3V6M

C107
0.1U_0402_16V4Z

C120
1U_0402_6.3V4Z

BBP#1
BBP#2

C56
10U_0805_6.3V6M

AA13
Y13

VGA@ 2

C100
1U_0402_6.3V4Z

32mA

VGA@ 1 VGA@ 1

SPVSS

BACK BIAS

10mil

2009/08/27
remove +VGA_CORE power

SPV10

C589
10U_0805_6.3V6M

AN10

NC_SPV18

VGA@

C102
1U_0402_6.3V4Z

AN9

VGA@

VGA@ 2

C101
1U_0402_6.3V4Z

For M96 SPV10=+GPU_CORE


For M97,Nahattan SPV10=+1.0VS

AM10

136mA

VGA@ 1

VGA@ 2

C137
1U_0402_6.3V4Z

+SPV10

NC_MPV18#1
NC_MPV18#2

VGA@ 2

C92
1U_0402_6.3V4Z

C649
0.1U_0402_16V4Z

1 VGA@ 1 VGA@ 1
C646
1U_0402_6.3V4Z

VGA@

SPV18 For
Mahattan only

VGA@
C655
10U_0603_6.3V6M

2
1
BLM18AG121SN1D_0603
VGA@

+SPV_18

C198
0.1U_0402_16V4Z

+1.8VSDGPU

1 VGA@ 1 VGA@ 1
C206
1U_0402_6.3V4Z

L58

C662
10U_0603_6.3V6M

1
VGA@
BLM18AG121SN1D_0603

20mil

50mA

PCIE_PVDD

+1.0VSDGPU

+VGA_CORE
1

C8
10U_0805_6.3V6M

L59
+1.0VSDGPU

150mA

H7
H8

+1.8VSDGPU

34.6A

C146
1U_0402_6.3V4Z

+MPV_18

PLL
AB37

C133
1U_0402_6.3V4Z

20mil

68mA

C55
1U_0402_6.3V4Z

+PCIE_PVDD

C587
1U_0402_6.3V4Z

10mil

10mil
SM010030010
200ma 120ohm@100mhz DCR 0.2

VDDRHB
VSSRHB

For M96 only,


Manhattan are NC pin

C9
10U_0805_6.3V6M

V12
U12

C176
1U_0402_6.3V4Z

C132
1U_0402_6.3V4Z

VDDRHA
VSSRHA

C70
1U_0402_6.3V4Z

M20
M21

C588
1U_0402_6.3V4Z

VGA@
C522
0.1U_0402_16V4Z

C521
1U_0402_6.3V4Z

C517
0.1U_0402_16V4Z

C518
1U_0402_6.3V4Z

MPV18 For
Mahattan only

C520
10U_0603_6.3V6M

L36
2
1
BLM18AG121SN1D_0603
VGA@
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1
VGA@

C564
0.1U_0402_16V4Z

VGA@
BLM18AG121SN1D_0603 1 VGA@ 1 VGA@ 1
C565
1U_0402_6.3V4Z

+1.8VSDGPU

1
C566
10U_0603_6.3V6M

+1.8VSDGPU

C74
1U_0402_6.3V4Z

MEM CLK

2009/08/27
remove VDDRHA,VDDRHB

L37

SM010030010
200ma 120ohm@100mhz DCR 0.2

C109
1U_0402_6.3V4Z

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4

C3
10U_0805_6.3V6M

AD12
AF11
AF12
AG11

C89
1U_0402_6.3V4Z

170mA

C177
1U_0402_6.3V4Z

VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4

C77
1U_0402_6.3V4Z

AF13
AF15
AG13
AG15

C139
1U_0402_6.3V4Z

170mA

+VDDR4_5

1
L42
BLM18AG601SN1D_2P

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C4
10U_0805_6.3V6M

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

C185
1U_0402_6.3V4Z

AF23
AF24
AG23
AG24

2A

C144
1U_0402_6.3V4Z

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

C85
1U_0402_6.3V4Z

LEVEL
TRANSLATION

I/O

60mA

10mil
20mil

AF26
AF27
AG26
AG27

AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C5
10U_0805_6.3V6M

C170
0.1U_0402_16V4Z

C169
1U_0402_6.3V4Z

C259
10U_0603_6.3V6M

136mA

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74

+PCIE_VDDR

C135
1U_0402_6.3V4Z

+VDDR3

1 VGA@ 1 VGA@ 1 VGA@

20mil
+VDD_CT

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

CORE

POWER

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VGA@

40mil

400mA

C152
1U_0402_6.3V4Z

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

C90
1U_0402_6.3V4Z

C183
0.1U_0402_16V4Z

2
1
L14
BLM18AG601SN1D_2P
VGA@

VGA@

C163
0.1U_0402_16V4Z

2009/09/14
update P/N SM010005500 500ma 600ohm@100MHZ DCR 0.38

C166
1U_0402_6.3V4Z

VGA@

VGA@
C175
1U_0402_6.3V4Z

C186
10U_0603_6.3V6M

VGA@

VGA@

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

C122
1U_0402_6.3V4Z

C64
1U_0402_6.3V4Z

2
1
L5
BLM18AG121SN1D_0603
VGA@

+3VSDGPU

+1.8VSDGPU

C209
1U_0402_6.3V4Z

VGA@

SM010030010
200ma 120ohm@100mhz DCR 0.2

+1.8VSDGPU

C591
10U_0603_6.3V6M

1
L43
BLM18AG121SN1D_0603
VGA@

C201
1U_0402_6.3V4Z

C530
1U_0402_6.3V4Z

C482
10U_0805_6.3V6M

C483
10U_0805_6.3V6M

C484
10U_0805_6.3V6M

C498
10U_0805_6.3V6M

C501
10U_0805_6.3V6M

VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

PCIE
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C108
1U_0402_6.3V4Z

C608
1U_0402_6.3V4Z

C602
1U_0402_6.3V4Z

C531
1U_0402_6.3V4Z

C82
1U_0402_6.3V4Z

C68
1U_0402_6.3V4Z

C83
1U_0402_6.3V4Z

C79
1U_0402_6.3V4Z

C91
1U_0402_6.3V4Z

VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C124
0.1U_0402_16V4Z

2900mA
TBD AC7

MEM I/O

C150
0.1U_0402_16V4Z

C158
1U_0402_6.3V4Z

C159
1U_0402_6.3V4Z

C179
1U_0402_6.3V4Z

C65
1U_0402_6.3V4Z

C138
1U_0402_6.3V4Z

C199
1U_0402_6.3V4Z

330U_2.5V_M_R15

C192
1U_0402_6.3V4Z

VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

C492
VGA@

C127
1U_0402_6.3V4Z

+1.5VSDGPU

2010/08/01

Deciphered Date

Title

M96_Power/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

25

of

59

Rev
1.0

L18
BLM18AG121SN1D_0603
2
1
VGA@

U34F
+1.8VSDGPU

VGA@

1
2

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

DPCD_CALR

DPAB_CALR

+DPB_VDD10

AN29
AP29
AP30
AW30
AW32

AW28

AU28
AV27

+DPA_PVDD

+DPB_PVDD

@
1
R484

2
0_0402_5%

20mil

+DPE_VDD18

DPD_PVDD
DPD_PVSS

DPE_PVDD
DPE_PVSS

+DPD_PVDD

+DPE_PVDD

10mil

10mil

10mil
2

10mil

10mil

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

SM010030010
200ma 120ohm@100mhz DCR 0.2

L50
BLM18AG121SN1D_0603
2
1
VGA@

L46
BLM18AG121SN1D_0603
2
1
VGA@

+1.8VSDGPU

For M96 are NC pins

C606
10U_0603_6.3V6M

C605
1U_0402_6.3V4Z

C604
0.1U_0402_16V4Z

1 VGA@ 1 VGA@ 1

2010/08/01

Deciphered Date

Title

M96_Power/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

216-0729002 A12 M96_BGA962


MADI@

+1.8VSDGPU

Compal Electronics, Inc.

Compal Secret Data


2009/08/01

C621
10U_0603_6.3V6M

DPEF_CALR

Security Classification
Issued Date

VGA@ 1 VGA@ 1 VGA@ 1

216-0729002 A12 M96_BGA962


MADI@

A39
AW1
AW39

C639
10U_0603_6.3V6M

+DPF_PVDD

C620
1U_0402_6.3V4Z

VGA@
150_0402_1%

VGA@ 1 VGA@ 1 VGA@ 1

C619
0.1U_0402_16V4Z

1 AM39

+1.8VSDGPU

R479
2

C623
1U_0402_6.3V4Z

AL38
AM35

+1.8VSDGPU

SM010030010
200ma 120ohm@100mhz DCR 0.2

+1.8VSDGPU

20mA

DPF_VDD10#1
DPF_VDD10#2
NC_DPF_PVDD
NC_DPF_PVSS

AF39
AH39
AK39
AL34
AM34

AM37
AN38

10mil

C631
0.1U_0402_16V4Z

+DPE_VDD10

+DPE_VDD10

AK33
AK34

AV19
AR18

L54
BLM18AG121SN1D_0603
2
1
+1.8VSDGPU
VGA@

VGA@ 1 VGA@ 1 VGA@ 1

20mA

DPF_VDD18#1
DPF_VDD18#2

20mil 120mA

2
0_0402_5%

+DPC_PVDD

20mA

200mA
AF34
AG34

AU18
AV17

SM010030010
200ma 120ohm@100mhz DCR 0.2

C638
10U_0603_6.3V6M

DPC_PVDD
DPC_PVSS

VGA@ 1 VGA@ 1 VGA@ 1

20mA
AN34
AP39
AR39
AU37
AW35

C622
1U_0402_6.3V4Z

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

AV29
AR28

R494
150_0402_1%
2
VGA@

C630
0.1U_0402_16V4Z

DPB_PVDD
DPB_PVSS

VGA@ 1 VGA@ 1 VGA@ 1

20mA
DPE_VDD10#1
DPE_VDD10#2

C644
10U_0603_6.3V6M

DP PLL POWER
DPA_PVDD
DPA_PVSS

20mil 120mA
AL33
AM33

20mil

20mA
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2

+1.0VSDGPU
VGA@ 1 VGA@ 1 VGA@ 1

C637
1U_0402_6.3V4Z

DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5

AN33
AP33

For M96 are NC pins

20mil
+DPB_VDD18

C628
0.1U_0402_16V4Z

AH34
AJ34

+DPE_VDD10

C226
1U_0402_6.3V4Z

AW18

DPB_VDD10#1
DPB_VDD10#2

C645
10U_0603_6.3V6M

R486
150_0402_1%
2
1
VGA@

VGA@
1

C627
1U_0402_6.3V4Z

AN19
AP18
AP19
AW20
AW22

AN27
AP27
AP28
AW24
AW26

200mA
DPD_VDD10#1
DPD_VDD10#2

VGA@
1

AP25
AP26

NEW70 M/B LA-5891P Schematic

Date:

+1.8VSDGPU
VGA@

C632
10U_0603_6.3V6M

NC_DPB_VDD18#1
NC_DPB_VDD18#2

20mil

+DPA_VDD10

130mA
NC_DPD_VDD18#1
NC_DPD_VDD18#2

C629
1U_0402_6.3V4Z

AP14
AP15

AP31
AP32

C636
0.1U_0402_16V4Z

C596
1U_0402_6.3V4Z

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

20mil 200mA

C191
0.1U_0402_16V4Z

DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5

20mil 200mA

+DPE_VDD18
1
R490

AP22
AP23

+DPD_VDD10

+DPE_VDD10
L9
BLM18AG121SN1D_0603
2
1
VGA@
VGA@ 1 VGA@ 1 VGA@ 1

Ball AW34 and AW35


are GND ball in M96,
but have another ball
name in Broadway,
that is XO_IN and
X0_IN2.

DPA_VDD10#1
DPA_VDD10#2

20mil

+DPA_VDD18

200mA
DPC_VDD10#1
DPC_VDD10#2

20mil 130mA
+DPD_VDD18

+DPE_VDD18

C225
10U_0603_6.3V6M

R77
0_0402_5%
@

C595
0.1U_0402_16V4Z

PX_EN:
AL21should be leave NC since
SBIOS will control VGA power on/off.

C597
10U_0603_6.3V6M

+1.0VSDGPU

AN17
AP16
AP17
AW14
AW16

+DPE_VDD18
L44
BLM18AG121SN1D_0603
2
1
VGA@
VGA@ 1 VGA@ 1 VGA@ 1

R69
0_0402_5%
@

PX_EN

AP13
AT13

130mA
AN24
AP24

C200
0.1U_0402_16V4Z

FB_GND

200mA

+DPC_VDD10

C626
1U_0402_6.3V4Z

+1.8VSDGPU

C634
0.1U_0402_16V4Z

2009/09/04
remove offpage

NC_DPA_VDD18#1
NC_DPA_VDD18#2

L12
BLM18AG121SN1D_0603
1
+1.0VSDGPU
VGA@

C252
10U_0603_6.3V6M

VGA@ 1 VGA@ 1 VGA@ 1

SM010030010
200ma 120ohm@100mhz DCR 0.2

20mil

NC_DPC_VDD18#1
NC_DPC_VDD18#2

C240
1U_0402_6.3V4Z

VGA@

AP20
AP21

DP A/B POWER

C205
0.1U_0402_16V4Z

+1.0VSDGPU

C245
1U_0402_6.3V4Z

VGA@

C238
0.1U_0402_16V4Z

VGA@

130mA

DP C/D POWER

SM010030010
200ma 120ohm@100mhz DCR 0.2

C248
10U_0603_6.3V6M

20mil

+DPC_VDD18

+1.8VSDGPU

For M96 are NC pins

VGA@ 1 VGA@ 1 VGA@ 1

U34H

C207
1U_0402_6.3V4Z

C237
0.1U_0402_16V4Z

C633
1U_0402_6.3V4Z

C625
0.1U_0402_16V4Z

VGA@ 1 VGA@ 1 VGA@ 1

+1.8VSDGPU

For M96 are NC pins

+1.0VSDGPU

VGA@

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

VGA@

C265
1U_0402_6.3V4Z

C264
0.1U_0402_16V4Z

VGA@

C266
10U_0603_6.3V6M

VGA@

C239
1U_0402_6.3V4Z

For M96 are NC pins


SM010030010
200ma 120ohm@100mhz DCR 0.2

C246
0.1U_0402_16V4Z

1 VGA@ 1 VGA@ 1

C641
10U_0603_6.3V6M

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AH29
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C254
10U_0603_6.3V6M

GND
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#152
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#162
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#176

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
GND#100

C640
10U_0603_6.3V6M

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

C255
10U_0603_6.3V6M

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

Tuesday, December 29, 2009

Sheet
1

26

of

59

Rev
1.0

C46
MADI@
2

+1.5VSDGPU

C485

MADI@
2

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA6
QSA7

F3
C7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

DQSL
DQSU

QSA#6
QSA#7

G3
B7

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R376
243_0402_1%
MADI@

R4
4.99K_0402_1%
MADI@

15mil

C486

R13
4.99K_0402_1%
MADI@

15mil

MADI@
2

+1.5VSDGPU

C17

MADI@
2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

R367
4.99K_0402_1%
MADI@

15mil

VREFCA_A3
R6
4.99K_0402_1%
MADI@

J1
L1
J9
L9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

+1.5VSDGPU

R377
4.99K_0402_1%
MADI@

15mil

VREFDA_Q3
1
R12
C45
4.99K_0402_1%
MADI@ MADI@
2

DML
DMU

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

15mil

DQSL
DQSU

VREFDA_Q2

R372
4.99K_0402_1%
MADI@

ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

15mil

A1
A8
C1
C9
D2
E9
F1
H2
H9

D7
C3
C8
C2
A7
A2
B8
A3

R9
243_0402_1%
MADI@

VREFCA_A2
R370
4.99K_0402_1%
MADI@

J1
L1
J9
L9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

L8

CK
CK
CKE/CKE0

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A4
R368
4.99K_0402_1%
MADI@

C481

VREFDA_Q4

MADI@
2

1
R378
C493
4.99K_0402_1%
MADI@ MADI@
2

0.1U_0402_16V4Z

G3
B7

R369
4.99K_0402_1%
MADI@

VREFDA_Q1
R10
4.99K_0402_1%
MADI@

QSA#4
QSA#5

J7
K7
K9

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

15mil

E7
D3

VRAM_RST# T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQMA#4
DQMA#5

CLKA1
CLKA1#
CKEA1
+1.5VSDGPU

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

F3
C7

BA0
BA1
BA2

E3
F7
F2
F8
H3
H8
G2
H7

0.1U_0402_16V4Z

ZQ/ZQ0

QSA4
QSA5

M2
N8
M3

0.1U_0402_16V4Z

RESET

R371
4.99K_0402_1%
MADI@

VREFCA_A1
1

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

CSA1#_0
RASA1#
CASA1#
WEA1#

A_BA0
A_BA1
A_BA2

+1.5VSDGPU

0.1U_0402_16V4Z

ODTA1_1

15mil

ODT/ODT0
CS/CS0
RAS
CAS
WE

0.1U_0402_16V4Z

MADI@

R14
4.99K_0402_1%
MADI@

R8
C18
4.99K_0402_1%
MADI@
MADI@

DML
DMU

0.1U_0402_16V4Z

MADI@

DQSL
DQSU

24
24
24
24

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

R7
4.99K_0402_1%
MADI@

R3
56_0402_1%
2

0_0402_5%
1
1

J1
L1
J9
L9

R381
243_0402_1%
MADI@

R16
MADI@
56_0402_1%
ODTA0 2
1
1
2
R17
0_0402_5% MADI@
R5
ODTA1 2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U_0402_16V4Z

ODTA1

L8

0.1U_0402_16V4Z

24

VRAM_RST# T2

ODTA0_1

ODTA0

G3
B7

K1
L2
J3
K3
L3

ODTA1_1

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

Pull high for Madison and Park...

24

QSA#3
QSA#1

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

E7
D3

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R11
243_0402_1%
MADI@

ZQ/ZQ0

DQMA#3
DQMA#1

J7
K7
K9

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

VREFCA
VREFDQ

J1
L1
J9
L9

RESET

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CLKA1
CLKA1#
CKEA1

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

L8

DQSL
DQSU

F3
C7

+1.5VSDGPU 24

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A4
VREFDA_Q4

T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

QSA3
QSA1

BA0
BA1
BA2

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

VRAM_RST#

24,28 VRAM_RST#

DML
DMU

K1
L2
J3
K3
L3

M2
N8
M3

E3
F7
F2
F8
H3
H8
G2
H7

G3
B7

DQSL
DQSU

ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#

A_BA0
A_BA1
A_BA2

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

QSA#2
QSA#0

ODT/ODT0
CS/CS0
RAS
CAS
WE

A1
A8
C1
C9
D2
E9
F1
H2
H9

B2
D9
G7
K2
K8
N1
N9
R1
R9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

QSA#[7..0]

CK
CK
CKE/CKE0

MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

24

J7
K7
K9

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

E7
D3

CLKA0
CLKA0#
CKEA0
+1.5VSDGPU

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A3
VREFDA_Q3

DQMA#2
DQMA#0

BA0
BA1
BA2

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

QSA[7..0]

M2
N8
M3

E3
F7
F2
F8
H3
H8
G2
H7

U28

24

F3
C7

A_BA0
A_BA1
A_BA2

+1.5VSDGPU

DQMA#[7..0]
QSA2
QSA0

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

ODT/ODT0
CS/CS0
RAS
CAS
WE

B2
D9
G7
K2
K8
N1
N9
R1
R9

24

CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

24
24
24
24

CK
CK
CKE/CKE0

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

M8
H1

ODTA0_1

MAA[13..0]

J7
K7
K9

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

CLKA0
CLKA0#

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A2
VREFDA_Q2

CKEA0

BA0
BA1
BA2

MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17

24

M2
N8
M3

MDA[0..63]

MDA[0..63]

24

A_BA0
A_BA1
A_BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

24

24
24
24

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

U2

VREFCA_A1 M8
VREFDA_Q1 H1

U29

U1

+1.5VSDGPU
+1.5VSDGPU

2009/08/01

C495
1U_0402_6.3V6K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C509
1U_0402_6.3V6K

C507
1U_0402_6.3V6K

1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@


C503
1U_0402_6.3V6K

C11
10U_0603_6.3V6M

C500
0.01U_0402_16V7K
MADI@

C12
10U_0603_6.3V6M

2
56_0402_1%
1

1 MADI@1 MADI@1 MADI@1 MADI@


C476
10U_0603_6.3V6M

MADI@

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

C478
10U_0603_6.3V6M

1
R380

C15
10U_0603_6.3V6M

CLKA1#

C480
10U_0603_6.3V6M

24

2
56_0402_1%

C10
10U_0603_6.3V6M

1
R384

1 MADI@1 MADI@1 MADI@1 MADI@


C477
10U_0603_6.3V6M

CLKA1

+1.5VSDGPU

+1.5VSDGPU
C494
0.01U_0402_16V7K
MADI@

MADI@
24

C479
1U_0402_6.3V6K

2
A

C51
1U_0402_6.3V6K

C14
1U_0402_6.3V6K

2
56_0402_1%

C49
1U_0402_6.3V6K

1
R379

C47
1U_0402_6.3V6K

CLKA0#

C13
1U_0402_6.3V6K

MADI@
24

C504
1U_0402_6.3V6K

C508
1U_0402_6.3V6K

C510
1U_0402_6.3V6K

C502
1U_0402_6.3V6K

1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@

C499
1U_0402_6.3V6K

1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@

C53
1U_0402_6.3V6K

1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@


C50
1U_0402_6.3V6K

2
56_0402_1%

C52
1U_0402_6.3V6K

1
R383

C48
1U_0402_6.3V6K

CLKA0

C16
1U_0402_6.3V6K

MADI@
24

2010/08/01

Deciphered Date

Title

VRAM_DDR3 / Channel A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

27

of

59

Rev
1.0

U33
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

B_BA0
B_BA1
B_BA2

24

CKEB0

CLKB0
CLKB0#

MAB[13..0]

24

ODTB0_1
24
24
24
24

DQMB#[7..0]

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

M2
N8
M3

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CSB0#_0
RASB0#
CASB0#
WEB0#

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

+1.5VSDGPU
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#

A1
A8
C1
C9
D2
E9
F1
H2
H9

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

J7
K7
K9

QSB3
QSB1

VREFCB_A2 M8
VREFDB_Q2 H1

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

24

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

CKEB1
ODTB1_1

A1
A8
C1
C9
D2
E9
F1
H2
H9

24
24
24
24

CSB1#_0
RASB1#
CASB1#
WEB1#
QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

+1.5VSDGPU

U6

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB6
QSB7

F3
C7

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1.5VSDGPU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R469
243_0402_1%
VGA@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

T2

J1
L1
J9
L9

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VRAM_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

VGA@

+1.5VSDGPU

1
VREFCB_A3

C617
VGA@

+1.5VSDGPU

R432
4.99K_0402_1%
VGA@

C545
VGA@

VREFCB_A4
R45
4.99K_0402_1%
VGA@

+1.5VSDGPU

C119
VGA@

VREFDB_Q4

R82
4.99K_0402_1%
VGA@

C214
VGA@

+1.5VSDGPU

R414

C611
1U_0402_6.3V6K

C615
1U_0402_6.3V6K

+1.5VSDGPU

C613
1U_0402_6.3V6K

C616
1U_0402_6.3V6K

C612
1U_0402_6.3V6K

C125
1U_0402_6.3V6K

C213
1U_0402_6.3V6K

C210
1U_0402_6.3V6K

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C212
1U_0402_6.3V6K

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

2009/08/01

C601
10U_0603_6.3V6M

C594
10U_0603_6.3V6M

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

C187
10U_0603_6.3V6M

C195
10U_0603_6.3V6M

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@


C217
1U_0402_6.3V6K

C525
1U_0402_6.3V6K

C526
1U_0402_6.3V6K

1 VGA@

C527
1U_0402_6.3V6K

C614
0.01U_0402_16V7K
VGA@

1 VGA@ 1 VGA@ 1 VGA@

C528
1U_0402_6.3V6K

+1.5VSDGPU

C67
10U_0603_6.3V6M

C529
1U_0402_6.3V6K

C535
10U_0603_6.3V6M

CLKB1#

C73
10U_0603_6.3V6M

24

R471
56_0402_1%
1 VGA@ 2

C540
10U_0603_6.3V6M

CLKB1

C60
1U_0402_6.3V6K

24

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C61
1U_0402_6.3V6K

2
R470
56_0402_1%
1 VGA@ 2

C532
0.01U_0402_16V7K
VGA@

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@


C58
1U_0402_6.3V6K

C57
1U_0402_6.3V6K

CLKB0#

C59
1U_0402_6.3V6K

24

56_0402_1%
2
VGA@
1

R80
4.99K_0402_1%
VGA@

VREFDB_Q3
1

R468
4.99K_0402_1%
VGA@

VGA@

C544

1
VGA@

R434
4.99K_0402_1%
VGA@
2

C62

R51
4.99K_0402_1%
VGA@
2

R430
4.99K_0402_1%
VGA@
2

2
VREFDB_Q2

1
2

R25
4.99K_0402_1%
VGA@
2

1
2

2
VGA@
2

C523

R467
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

R415 56_0402_1%
2
VGA@

VREFCB_A2

VREFDB_Q1

R411
4.99K_0402_1%
VGA@

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU

0.1U_0402_16V4Z

VGA@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSDGPU

0.1U_0402_16V4Z

C543

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

0.1U_0402_16V4Z

R428
4.99K_0402_1%
VGA@

ODTB1_1

CLKB0

VREFCB_A1
R49
56_0402_1%
2
VGA@

ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

+1.5VSDGPU

0.1U_0402_16V4Z

RESET

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

R431
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

ODTB1 R50
VGA@
0_0402_5%

R43
56_0402_1%
2
VGA@

R28
4.99K_0402_1%
VGA@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

ODTB1

ODTB0 R42
VGA@
0_0402_5%

ODTB0

R417
4.99K_0402_1%
VGA@

R433
4.99K_0402_1%
VGA@

T2

R46
243_0402_1%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

L8

+1.5VSDGPU
ODTB0_1

DML
DMU

VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VRAM_RST#

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

R27
243_0402_1%

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

Pull high for Madison and Park...

J1
L1
J9
L9

ZQ/ZQ0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

RESET

DML
DMU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

L8

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VRAM_RST# T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VGA@

ZQ/ZQ0

R429
243_0402_1%

J1
L1
J9
L9

RESET

DML
DMU

L8

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VRAM_RST#

24,27 VRAM_RST#

24

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

QSB#[7..0]

DML
DMU

24

24

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

+1.5VSDGPU

24

VREFCB_A4 M8
VREFDB_Q4 H1

QSB[7..0]

24

E3
F7
F2
F8
H3
H8
G2
H7

MDB[0..63]

MDB[0..63]

24

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

U36

24

24
24
24

U4

2010/08/01

Deciphered Date

Title

VRAM_DDR3 / Channel B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

28

of

59

Rev
1.0

LCD POWER CIRCUIT

+LCDVDD

+3VS C475
SG@
0.1U_0402_16V4Z
1
2

+3VS

+3V

AO3413L_SOT23-3
+LCDVDD

P
DGPU_SELECT#

16,17,30 DGPU_SELECT#

INVTPWM

C462

C459

SG@ 2 DGPU_EDIDSEL_R#
1
R366
0_0402_5%

18 DGPU_EDIDSEL#

0.1U_0402_16V4Z
30 DGPU_EDIDSEL_R#

1
@
1
R364
74AHC1G14GW_SOT3535

DPST_PWM_1

VGA_PNL_PWM 1 @
R360

SWITCHABLE

USB20_CMOS_P8

CH4

CH1

41
42
43
44
45
46

G1
G2
G3
G4
G5
G6

W=60mils

R729
@

1 0_0402_5%
+LCDVDD

INVTPWM
DISPOFF#
I2CC_SCL
I2CC_SDA

+3VS
+LCDVDD
1

W=60mils

+3VS
2

C464
0.1U_0402_16V4Z

DAC_BRIG

TXOUT1TXOUT1+

INVTPWM
DISPOFF#

TXOUT2TXOUT2+
TXCLKTXCLK+

R731 2

DISPOFF#

@
@

C461
10U_0805_10V4Z

C458
0.1U_0402_16V4Z

48
47
43
42
37
36
32
31
22
23

1 0_0402_5%

1
C467
1
C468
1
C473

2
220P_0402_50V7K
2
220P_0402_50V7K
2
220P_0402_50V7K

0_0402_5% 2

1 R363

10K_0402_5% 2

1 R362

BKOFF#

37

PCH_TXCLK+
PCH_TXCLKPCH_TXOUT2PCH_TXOUT2+
PCH_TXOUT1+
PCH_TXOUT1PCH_TXOUT0PCH_TXOUT0+
PCH_LCD_CLK
PCH_LCD_DATA

46
45
41
40
35
34
30
29
25
26

DGPU_EDIDSEL_R#

54

LOCAL_DIM 37

52
5
51

1208 Add Panel new feature

1 0_0402_5%

COLOR_ENG_EN 37

57

+3VS

R1
R2
1

C805
22P_0402_50V8J
@ 2

2
2

1 0_0402_5%
1 0_0402_5%

R15
0_0603_5%
SG@

UMA
U3

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
SEL2
NC
NC
NC
Thermal_GND

VCC
VCC
VCC
VCC
VCC
VCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

4
10
18
27
38
50
56

+3VS_SWITCH
1

SG@ SG@ SG@


2
2
2

2
3
7
8
11
12
14
15
19
20

C63 C54
C66
TXCLK+
TXCLKTXOUT2TXOUT2+
TXOUT1+
TXOUT1TXOUT0TXOUT0+
I2CC_SCL
I2CC_SDA

17

DGPU_SELECT#

0_0402_5% 2 UMAO@1
UMAO@ R416
0_0402_5% 2 UMAO@1 R412

PCH_TXOUT0+
PCH_TXOUT0-

TXOUT1+
TXOUT1-

0_0402_5% 2 UMAO@1 R405


0_0402_5% 2 UMAO@1 R410

PCH_TXOUT1+
PCH_TXOUT1-

TXOUT2+
TXOUT2-

0_0402_5% 2 UMAO@1 R401


0_0402_5% 2 UMAO@1 R399

PCH_TXOUT2+
PCH_TXOUT2-

TXCLK+
TXCLK-

0_0402_5% 2 UMAO@1 R393


0_0402_5% 2 UMAO@
UMAO@1 R396

PCH_TXCLK+
PCH_TXCLK-

I2CC_SCL
I2CC_SDA

0_0402_5% 2 UMAO@1 R418


0_0402_5% 2 UMAO@1 R420

+3VS

1
6
9
13
16
21
24
28
33
39
44
49
53
55

UMA ONLY

TXOUT0+
TXOUT0-

PCH_TXOUT1+ 16
PCH_TXOUT1- 16
PCH_TXOUT2+ 16
PCH_TXOUT2- 16

PCH_LCD_CLK 16
PCH_LCD_DATA 16

5/4 PCH_LCD_CLK& PCH_LCD_DATA


Pull high 2.2K change to 4.7K
1 UMA@ 2 4.7K_0402_5% PCH_LCD_CLK

R32

1 UMA@ 2 4.7K_0402_5% PCH_LCD_DATA

Discrete ONLY

TXOUT0+
TXOUT0-

0_0402_5% 2 DISO@ 1 R26


0_0402_5% 2 DISO@ 1 R24

VGA_TXOUT0+
VGA_TXOUT0-

TXOUT1+
TXOUT1-

0_0402_5% 2 DISO@ 1 R22


0_0402_5% 2 DISO@ 1 R23

VGA_TXOUT1+
VGA_TXOUT1-

TXOUT2+
TXOUT2-

0_0402_5% 2 DISO@ 1 R21


0_0402_5% 2 DISO@ 1 R20

VGA_TXOUT2+
VGA_TXOUT2-

TXCLK+
TXCLK-

0_0402_5% 2 DISO@ 1 R18


0_0402_5% 2 DISO@ 1 R19

VGA_TXCLK+
VGA_TXCLK-

I2CC_SCL
I2CC_SDA

0_0402_5% 2 DISO@ 1 R419


0_0402_5% 2 DISO@ 1 R421

VGA_TXOUT0+ 22
VGA_TXOUT0- 22
VGA_TXOUT1+ 22
VGA_TXOUT1- 22
VGA_TXOUT2+ 22
VGA_TXOUT2- 22
VGA_TXCLK+ 22
VGA_TXCLK- 22
A

VGA_LCD_CLK
VGA_LCD_DATA

VGA_LCD_CLK 23
VGA_LCD_DATA 23

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/08/01

2010/08/01

Deciphered Date

Title

LVDS Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

PCH_TXCLK+ 16
PCH_TXCLK- 16

PCH_LCD_CLK
PCH_LCD_DATA

R29

Date:

PCH_TXOUT0+ 16
PCH_TXOUT0- 16

PI3LVD400ZFE with 2 SEL pin


USB20_N8 17
USB20_P8 17

Issued Date

C806
22P_0402_50V8J
@

+3VS

DIS

PI3LVD400ZFEX_TQFN56_11X5
SG@

1109 RF request
USB20_CMOS_N8
USB20_CMOS_P8

IPEX_20143-040E-20F
CONN@

B2

DAC_BRIG 37

TXOUT0TXOUT0+

R730 2

VGA_TXCLK+
VGA_TXCLKVGA_TXOUT2VGA_TXOUT2+
VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT0VGA_TXOUT0+
VGA_LCD_CLK
VGA_LCD_DATA

Place closed to JLVDS1

+LCDVDD

+INVPWR_B+
+LCDVDD_R

B1

TS3DV520ERHUR with 1 SEL pin

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

SEL1
SEL2

LCD/LED PANEL Conn.


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

2009/8/27 ADD SWITCHABLE

0.1U_0402_16V4Z

Vn

C470
68P_0402_50V8J

4.7U_0603_6.3V6K

Vp

USB20_CMOS_N8

CH2

+3VS

CH3

0.1U_0402_16V4Z

CM1293-04SO_SOT23-6
@

R355
10K_0402_5%

B+

5
2
0_0402_5%

D1

IGPU_PWM_SELECT#

U22
SG@

1 DISO@ 2
R356
0_0402_5%

+INVPWR_B+

L30 2
1
FBMA-L11-201209-221LMA30T_0805

SM010014520 3000ma 220ohm@100mhz DCR 0.04

Reserved for UMA Only

INVT_PWM

INVT_PWM

22 VGA_PNL_PWM

INVTPWM
1 UMAO@ 2
R358
0_0402_5%

U24
74AHCT1G125GW_SOT353-5
UMA@

37

C471
680P_0402_50V7K

2
100K_0402_5%

74AHC1G14GW_SOT3535
Y

VBIOS PWM SETTING


CHANGE TO NORMAL

L31 2
1
FBMA-L11-201209-221LMA30T_0805

IGPU_EDIDSEL#

2009/12/15
change P/N to SA00000U500

W=60mils

PWMSEL_1#
SG@ 2
1
R361
0_0402_5%

2
P
2

DPST_PWM

16

100K_0402_5%
1
17 DGPU_PWMSEL#

Q16,Q17
NEED ADD OPTION COMPONENT

Y
U26
@

NC

R734
2

1
R735
0_0402_5%

R736
0_0402_5%
@

Q31
2N7002E-T1-GE3_SOT23-3
DIS@

+3VS C469
SG@
0.1U_0402_16V4Z
1
2

091211 ADD R734 Fix CPT 4sec shut down flash issue

OE#

2
G

Pull Low at GPU side

+3VS

1
3

ENVDD

ENVDD

IGPU_SELECT# 16

SG@ 2
1
R365
100K_0402_5%
74AHC1G14GW_SOT3535

+3VS C474
@
0.1U_0402_16V4Z
1
2

SN74CBTD3306CPWR_TSSOP8
SG@

+5VS

22

IGPU_SELECT#

U27
SG@

4.7U_0805_10V4Z

W=60mils

0.047U_0402_16V7K
2

R351
100K_0402_5%

8
3
6
4

Q29
UMA@
S 2N7002E-T1-GE3_SOT23-3

VCC
1B
2B
GND

2
G

Q30

1A
2A
1OE#
2OE#

NC

1
PCH_ENVDD

PCH_ENVDD

C466

16

S
2N7002E-T1-GE3_SOT23-3

2
5
1
7

2
2
G

INVT_PWM
DPST_PWM_1
PWMSEL_1#
IGPU_PWM_SELECT#

4.7U_0805_10V4Z

2
1

R353
1K_0402_5%
2
1

D
Q28
D

+5VS

C463
U23

R357
100K_0402_5%

NC

W=60mils

R349
300_0603_5%

Wednesday, January 06, 2010

Sheet
1

29

of

59

Rev
1.0

CRT Connector

D17

D16

W=40mils

D14

+5VS

+R_CRT_VCC

+CRT_VCC

D2

BAV99_SOT-23 BAV99_SOT-23 BAV99_SOT-23


F1

SM010005220 600ma 80ohm@100mhz DCR 0.25

1.1A_6V_SMD1812P110TF
1
C171
0.1U_0402_16V4Z

CH491DPT_SOT23-3

W=40mils

+3VS

2
1

Change to 0 ohm for Discrete


CRT_R

CRT_R_1
2
FCM2012CF-800T06_2P

L48 1

UMAO@

CRT_G_1
2
FCM2012CF-800T06_2P

L41 1

2 FCM2012CF-800T06_2P

CRT_G_2

UMAO@

L39 1

2 FCM2012CF-800T06_2P

CRT_B_2

UMAO@

CRT_B_1
2
FCM2012CF-800T06_2P

L47 1

1
C607

R446

C592

C567

C618

UMAO@
UMAO@
UMAO@
2
2
2
10P_0402_50V8J
10P_0402_50V8J

150_0402_1%

150_0402_1%

C598

C590

UMAO@
2

UMAO@
UMAO@
2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J

10P_0402_50V8J

C603
10P_0402_50V8J
UMAO@ 2

P
A

1 10K_0402_5%

1
L2

2
MBC1608121YZF_0603

CRT_HSYNC_2

1
L1

2
MBC1608121YZF_0603

CRT_VSYNC_2
1
1

U7
Y

C178
10P_0402_50V8J
CRT_HSYNC_1

R41
100K_0402_5%
@

C164
10P_0402_50V8J

16
17

C-H_13-12201513CP
CONN@
CRT_DET# 18

100P_0402_50V8J

DSUB_12

G
G

C110

DSUB_15

C208 2
68P_0402_50V8J 1

R67

OE#

CRT_HSYNC

Change to 12pf for Discrete

+CRT_VCC
2 0.1U_0402_16V4Z

C569
10P_0402_50V8J
2 UMAO@

SM010012010 300ma 120ohm@100mhz DCR 0.4

Change to 15pf for Discrete

C194 1

C593
10P_0402_50V8J
UMAO@ 2

R464

150_0402_1%

74AHCT1G125GW_SOT353-5

R466

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

L38 1
1

L40 1

CRT_B
1

CRT_G

CRT_R_2

2 FCM2012CF-800T06_2P

C126
+CRT_VCC
68P_0402_50V8J

+CRT_VCC

2 0.1U_0402_16V4Z

U5
Y

CRT_VSYNC_1

3
2
2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

R48
4.7K_0402_5%
C280
SG@
0.1U_0402_16V4Z

UMA only
CRT_DDC_DATA

4
16
23
29
32
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA

27
25
22
20
18
12
14

PCH_CRT_R
PCH_CRT_G
PCH_CRT_B
PCH_CRT_HSYNC
PCH_CRT_VSYNC
PCH_CRT_CLK
PCH_CRT_DATA

26
24
21
19
17
13
15

VDD
VDD
VDD
VDD
VDD
0B1
1B1
2B1
3B1
4B1
5B1
6B1
0B2
1B2
2B2
3B2
4B2
5B2
6B2

A0
A1
A2
A3
A4
SEL1
A5
A6
SEL2

GND
GND
GND
GND
GPAD

1
2
5
6
7

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

9
10

CRT_HSYNC

16 PCH_CRT_VSYNC

PCH_CRT_VSYNC R528 2 UMAO@1


UMAO@
0_0402_5%

CRT_VSYNC

16 PCH_CRT_CLK

PCH_CRT_CLK

R544 2 UMAO@ 1 0_0402_5% CRT_DDC_CLK

PCH_CRT_DATA

R543 2 UMAO@ 1 0_0402_5% CRT_DDC_DATA

Discrete only

3
11
28
31
33

23 VGA_CRT_R
23 VGA_CRT_G
23 VGA_CRT_B

DIS

23 VGA_DDC_CLK

UMA

23 VGA_DDC_DATA

VGA_CRT_R

R537 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R535 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R533 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC R531 2 DISO@ 1 0_0402_5% CRT_HSYNC


VGA_CRT_VSYNC
VGA_DDC_CLK

R529 2 DISO@ 1 0_0402_5% CRT_VSYNC


R527 2 DISO@ 1 0_0402_5% CRT_DDC_CLK
4

VGA_DDC_DATA R526 2 DISO@ 1 0_0402_5% CRT_DDC_DATA

2009/08/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DSUB_15

1
Q2
2N7002E-T1-GE3_SOT23-3

DGPU_EDIDSEL_R# 29

B2

CRT_DDC_CLK
CRT_DDC_DATA

30

23 VGA_CRT_VSYNC

CRT_DDC_CLK

PCH DDC PU 2.2K on Page 17

23 VGA_CRT_HSYNC

B1

CRT_B

PCH_CRT_HSYNC R530 2 UMAO@ 1 0_0402_5%

DGPU_SELECT# 16,17,29

PI3V712-AZLEX_TQFN32_6X3~D
SG@

CRT_G

16 PCH_CRT_HSYNC

16 PCH_CRT_DATA

R532 2 UMAO@ 1 0_0402_5%

U10

R534 2 UMAO@ 1 0_0402_5%

PCH_CRT_B

DSUB_12

Q3
2N7002E-T1-GE3_SOT23-3
D

PCH_CRT_G

16 PCH_CRT_B

CRT_R
G

16 PCH_CRT_G
+3VS

R536 2 UMAO@ 1 0_0402_5%

16 PCH_CRT_R

PCH_CRT_R

R78
4.7K_0402_5%
2

0.1U_0402_16V4Z
1
1
C290
C271
SG@
SG@

C273
SG@

2009/08/27

+3VS

+3VS

SWITCHABLE

+CRT_VCC
74AHCT1G125GW_SOT353-5
1

CRT_VSYNC

OE#

C111 1

CRT Connector
Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
E

30

of

59

Rev
1.0

+3VS
+3VS

C730

C731

C720

C721

C409

2 0_0603_5%
HDMI@

D21
UMAHD@
2

UMAHD@
2

UMAHD@
2

0.1U_0402_16V4Z

UMAHD@
2

UMAHD@
2

0.1U_0402_16V4Z

+5VS

R616
10K_0402_5%
UMAHD@

W=40mils
+HDMI_5V_OUT
F2

1 +HDMI_5V

OE#

1
2
HDMI@
1
1.1A_6V_SMD1812P110TF
C707
HDMI@
0.1U_0402_16V4Z 2

@
CH491DPT_SOT23-3

0.1U_0402_16V4Z

Q43
UMAHD@

HDMI_HPD

2
G
S

VGAHD@
X

VGA

R269
R253
R273
R252

HDMI_R_CK+
HDMI_R_D0-

+3VS

HDMI_R_D0+
HDMI_R_D1-

2
11
15
21
26
33
40
46

@
1
2 2.2K_0402_5%
@
1
2 2.2K_0402_5%
1 UMAHD@2 2.2K_0402_5%
1 UMAHD@2 2.2K_0402_5%

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

CG_0
CG_1

3
4

CG_0
CG_1

REXT

REXT

OE#

25

OE#

@
1
R618

SCL_SINK

28

HDMI_SCLK

D23
R625 1 HDMI@ 2 2.2K_0402_5%1

SDA_SINK

29

HDMI_SDATA

R627 1 HDMI@ 2 2.2K_0402_5%1

2
0_0402_5%

D24

HPD_SINK

30

DDC_EN

32

EQ_0
EQ_1

34
35

HDMI_HPD
R629 1 UMAHD@
2 2.2K_0402_5% +3VS
R637
1 UMAHD@2
R638
1 UMAHD@2
EQ_S0
R635
@
1
2
EQ_S1
R666
@
1
2

HDMI@
CH751H-40PT_SOD323-2
2
+HDMI_5V_OUT

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

R235 UMAHD@1

+3VS
16 SDVO_SDATA

2 3.3K_0402_5%

R223 UMAHD@1

2 2.2K_0402_5%

R219 UMAHD@1

2 2.2K_0402_5%

SDVO_SCLK
R211
R209

+3VS

CG0

CG1

CG2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

+3VS

Swing Pre-amp Slew-rate


0
0
0
0
0
2db
2db
0

R228 1

0
-3db
-3db (default)
-4db
0
0
0
0

HPD#

SDA

SDVO_SCLK

SCL

CG_2

EQ0

EQ1

0
0
1
1

0
1
0
1

+3VS

SM070001310 400ma 90ohm@100mhz DCR 0.3

12dB
9dB
6dB
3dB (default)

CG_2

HDMI_TX2+
HDMI_TX2-

13
14

OUT_D4+
OUT_D4-

IN_D4+
IN_D4-

48
47

PCH_TMDS_D2 16
PCH_TMDS_D2# 16

HDMI_TX1+
HDMI_TX1-

16
17

OUT_D3+
OUT_D3-

IN_D3+
IN_D3-

45
44

PCH_TMDS_D1 16
PCH_TMDS_D1# 16

HDMI_CLK+
HDMI_CLK-

19
20

OUT_D2+
OUT_D2-

IN_D2+
IN_D2-

42
41

PCH_TMDS_CK 16
PCH_TMDS_CK# 16

HDMI_TX0+
HDMI_TX0-

22
23

OUT_D1+
OUT_D1-

IN_D1+
IN_D1-

39
38

PCH_TMDS_D0 16
PCH_TMDS_D0# 16

1
5
12
18
24
27
31
36
37
43

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

49

HPD_SOURCE

2
10K_0402_5%

2 2.2K_0402_5%

PCH_TMDS_CK#

R738 1

2 2.2K_0402_5%

PCH_TMDS_CK

23 VGA_HDMI_TXD123 VGA_HDMI_TXD1+
23 VGA_HDMI_TXD023 VGA_HDMI_TXD0+

+3VSDGPU
+3VSDGPU

HDMI_TX1+

R183 1 HDMI@ 2

L25
W CM-2012-900T_0805
@
4
HDMI_TX1-

R182

HDMI_TX2+

R190

1 HDMI@ 2
1 HDMI@ 2
1
4

HDMI_R_CK-

0_0402_5%

HDMI_R_D0+

2
3
0_0402_5%

HDMI_R_D0-

0_0402_5%

HDMI_R_D1+

2
3
0_0402_5%

HDMI_R_D1-

0_0402_5%

HDMI_R_D2+

R188 1 HDMI@ 2

0_0402_5%

HDMI_R_D2-

C379
C378

VGAHD@ 2
VGAHD@ 2

1 0.1U_0402_16V7K HDMI_TX21 0.1U_0402_16V7K HDMI_TX2+

R613 1 VGAHD@2 499_0402_1%


R614 1 VGAHD@2 499_0402_1%

C381
C380

VGAHD@ 2
VGAHD@ 2

1 0.1U_0402_16V7K HDMI_TX11 0.1U_0402_16V7K HDMI_TX1+

R611 1 VGAHD@2 499_0402_1%


R612 1 VGAHD@2 499_0402_1%

C385
C384

VGAHD@ 2
VGAHD@ 2

1 0.1U_0402_16V7K HDMI_TX01 0.1U_0402_16V7K HDMI_TX0+

R607 1 VGAHD@2 499_0402_1%


R608 1 VGAHD@2 499_0402_1%

C383
C382

VGAHD@ 2
VGAHD@ 2

1 0.1U_0402_16V7K HDMI_CLK- R609 1 VGAHD@2 499_0402_1%


1 0.1U_0402_16V7K HDMI_CLK+ R610 1 VGAHD@2 499_0402_1%

HDMI_SDATA

VGAHD@
2N7002E-T1-GE3_SOT23-3

Place closed to JHDMI1

C804
12P_0402_50V8J
2 @

C803
12P_0402_50V8J
2 @

18 DGPU_HPD_INT#

Q42
VGAHD@

S
A

2N7002E-T1-GE3_SOT23-3

Compal Electronics, Inc.

Compal Secret Data


2009/08/01

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2
G

+3VSDGPU

Q44
2N7002E-T1-GE3_SOT23-3
SG@

Security Classification

DDC to HDMI CONN

2
G

R715
10K_0402_5%
VGAHD@

HDMI_HPD

1
D

23 VGA_HDMI_DET

1 VGAHD@2
R634
150K_0402_5%

2
B
E

Q13

Q12

HDMI_SCLK
VGAHD@
2N7002E-T1-GE3_SOT23-3

Q52
MMBT3904_G_SOT23-3
VGAHD@
1
2
R714
0_0402_5%
VGAHD@

1109 RF request

23 VGA_HDMI_SCLK
A

R168 1 HDMI@ 2

3
0_0402_5%

Pull high at VGA side

23 VGA_HDMI_SDATA

HDMI_R_CK+

23 VGA_HDMI_TXC23 VGA_HDMI_TXC+

HDMI_TX0-

UMAHD@

23 VGA_HDMI_TXD223 VGA_HDMI_TXD2+

R174 1 HDMI@ 2

1
L26
W CM-2012-900T_0805
@
4

ASMEIDA BUG

HDMI_TX0+

HDMI_TX2R737 1

R177 1 HDMI@ 2

1
L23
W CM-2012-900T_0805
@
4

0_0402_5%

HDMI_CLK-

ASM1442 PN: SA00003GT00


ASM1442T_QFN48_7X7

R180 1 HDMI@ 2

1
L24
W CM-2012-900T_0805
@
4

Equalization

10

2 10K_0402_5%

1 UMAHD@2
R230
0_0402_5%
R234

SDVO_SDATA

@
1
2 2.2K_0402_5%
1 UMAHD@2 2.2K_0402_5%

450
420
450
460
340
400
400
420

16 PCH_DPB_HPD

HPD_SOURCE

20
21
22
23

SUYIN_100042MR019S153ZL
CONN@

CH751H-40PT_SOD323-2
HDMI@

HDMI_CLK+

Connection to 3.4K
external resistor.

16

HDMI_R_CK-

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

+3VS

C410
HDMI@
0.1U_0402_16V4Z

SG@

SG

UMA

NO HDMI

HDMI@

1
R256
UMAHD@
100K_0402_5% 2

U45

UMAHD@

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_SDATA
HDMI_SCLK

2N7002E-T1-GE3_SOT23-3

Option

JHDMI1
HDMI_HPD
+HDMI_5V_OUT

UMAHD@
UMAHD@
2
2
0.1U_0402_16V4Z

HDMI connector

0.1U_0402_16V4Z

C725

C727

0.1U_0402_16V4Z

R590 1

0.1U_0402_16V4Z

Title

HDMI Level Shift & Conn


Size
Document Number
Custom

Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

31

of

59

SATA HDD1 Conn.


CL 4.0 mm
JHDD1
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

C753 1
C751 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0

C749 1
C747 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_PRX_N0
SATA_DTX_PRX_P0

13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0
13 SATA_DTX_C_PRX_N0
13 SATA_DTX_C_PRX_P0

1
2
3
4
5
6
7

+3VS
1

2
+5VS

R669 1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

C745

0.1U_0402_16V4Z
+5VS_HDD1

2 0_0805_5%

100mils
10U_0805_10V4Z
C735

0.1U_0402_16V4Z
1

C734

C733

C732

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

24
23

GND
GND

1U_0402_6.3V4Z

SANTA_192301-1
CONN@

1000P_0402_50V7K

SATA ODD Conn.


JODD1

13 SATA_PTX_DRX_P1
13 SATA_PTX_DRX_N1

13 SATA_DTX_C_PRX_N1
13 SATA_DTX_C_PRX_P1

C687 1
C685 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C680 1
C678 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_PRX_N1
SATA_DTX_PRX_P1

R516 1
+5VS

R105 1

2 1K_0402_1%

8
9
10
11
12
13

+5VS_ODD

2 0_0805_5%

80mils
10U_0805_10V4Z
C642

Place caps. near ODD CONN.

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND

GND
GND
GND
GND

17
16
15
14

0.1U_0402_16V4Z
C654

C653

C643

1U_0402_6.3V4Z

OCTEK_SLS-13SB1G_RV
CONN@

2
1000P_0402_50V7K

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

HDD & ODD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

32

of

59

Rev
1.0

+3V_LAN
+3VALW

R599

60mil

0_1206_5%
1

U39

2
2
0.1U_0402_16V4Z

2
2
2
0.1U_0402_16V4Z
1000P_0402_50V7K
+LAN_AVDDL

VDDC
VDDC
VDDC

XTALVDDH

14

AVDDH

30

AVDDH

36

27
33
39

AVDDL
AVDDL
AVDDL

37
38

LAN_MIDI3+

35

LAN_MIDI2-

34

LAN_MIDI2+

TRD1_N

31

LAN_MIDI1-

TRD1_P

32

LAN_MIDI1+

29

LAN_MIDI0-

28

LAN_MIDI0+

TRD3_N

TRD2_N
24

+LAN_PCIEPLLVDD 18
21

+LAN_AVDDH

LAN_MIDI3-

TRD3_P

+LAN_GPHYPLLVDDL

+LAN_XTALVDDH

TRD2_P

LAN_MIDI3- 34
LAN_MIDI3+ 34
LAN_MIDI2- 34

PCIE_PLLVDDL
TRD0_N
PCIE_PLLVDDL

0.1U_0402_16V7K
14 PCIE_PTX_C_DRX_P1
14 PCIE_PTX_C_DRX_N1
15,35 PCH_PCIE_WAKE#
37
EC_PME#
+3V_LAN

R592 1
R589 1
R587 1

LAN_MIDI2+ 34

C322 1

LAN_MIDI1- 34

R195
1K_0402_1%
@

LAN_MIDI1+ 34
LAN_MIDI0- 34
LAN_MIDI0+ 34

SPD100LED#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
REST#
PCIE_REFCLK_P
PCIE_REFCLK_N

SPD1000LED#
TRAFFICLED#

2
1
R595
0_0402_5%

47

LAN_LINK# 34

2
1
R594
0_0402_5%

U12 @

SPROM_CLK
SPROM_DOUT

VCC
WP
SCL
SDA

A0
A1
NC
GND

1
2
3
4

AT24C02_SO8

R196
1K_0402_1%

46
45

R193
1K_0402_1%
8
7
6
5

48

2 0.1U_0402_16V4Z
@

R194
1K_0402_1%
@

LAN_ACTIVITY# 34

SM010005500 500ma 600ohm@100mhz DCR 0.38

20mil

L22

+LAN_XTALVDDH
C301

1
2
BLM18AG601SN1D_2P

+3V_LAN

0.1U_0402_16V4Z
R597 1

5,17,21,37 PLT_RST#

17
16
22
23
LAN_PME#
4
LAN_RESET# 2
20
2 0_0402_5%
19
2 0_0402_5%
2 4.7K_0402_5%

AT24C02

LINKLED#
PCIE_DTX_PRX_P1
PCIE_DTX_PRX_N1

+3V_LAN

0.1U_0402_16V7K
1
2 C699
1
2 C700

SPROM_DOUT
(EEDATA)

GPHY_PLLVDDL

TRD0_P

14 PCIE_DTX_C_PRX_P1
14 PCIE_DTX_C_PRX_N1

SPROM_CLK
(EECLK)
On chip

4.7U_0603_6.3V6K 2

BIASVDDH

6
15
41

+LAN_BIASVDDH

VDDC

25

C697

C715

0.1U_0402_16V4Z
1000P_0402_50V7K
1
1
1
1
1
C701
C333
C705
C808
C807

+1.2V_LAN

42

+3V_LAN

091211 EMI add 1000P

C716

4.7U_0603_6.3V6K
2
2
0.1U_0402_16V4Z

2 0_0402_5%
MODE

20mil

L64

+LAN_BIASVDDH

14 CLK_PCIE_LAN
14 CLK_PCIE_LAN#

C703

1
2
BLM18AG601SN1D_2P

0.1U_0402_16V4Z
EEDATA
+3VS

R175 1

2 1K_0402_5%

40

R596 1

2 10K_0402_5%

EECLK

LAN_XTALI

12

SPROM_CLK

20mil

L66

LOW_PWR

40mil

XTALO

SR_VFB

11

0.1U_0402_16V4Z

L65

+1.2V_LAN_OUT
1
2
4.7UH_PG031B-4R7MS_1.1A_20%

8
C708

XTALI

0.1U_0402_16V4Z

LAN_RDAC

26

SR_VDDP

C710
10U_0805_10V4Z

SR_VDD
14 LAN_CLKREQ#

10
C318

L63
1
2
BLM18AG601SN1D_2P

+LAN_PCIEPLLVDD
1

+1.2V_LAN

C695
4.7U_0603_6.3V6K

20mil

L62
1
2
BLM18AG601SN1D_2P

+LAN_GPHYPLLVDDL

PAD

C698
0.1U_0402_16V4Z

+1.2V_LAN

C696
4.7U_0603_6.3V6K

49

BCM57780A0KMLG_QFN48_7X7

0.1U_0402_16V4Z

C311

2
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z

CLKREQ#
NC

+3V_LAN
1

1
2
BLM18AG601SN1D_2P

SM010005500 500ma 600ohm@100mhz DCR 0.38

0.1U_0402_16V4Z

RDAC

C706

20mil

C302

1.24K_0402_1%

+1.2V_LAN

R575
1

+LAN_AVDDH
C712

SR_LX
13

SPROM_DOUT

44

VMAIN_PRSINT

LAN_XTALO_R

43

20mil

L21
1
2
BLM18AG601SN1D_2P

+LAN_AVDDL
LAN_XTALI

C709

LAN_XTALO_R

0.1U_0402_16V4Z

+1.2V_LAN

C312
4.7U_0603_6.3V6K

R571
200_0402_1%
Y3
1
1

2 LAN_XTALO

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1
25MHZ_20PF_7A25000012
C704
C702
27P_0402_50V8J
27P_0402_50V8J
2

2010/08/01

Deciphered Date

Title

Broadcom BCM57780

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

33

of

59

Rev
1.0

LAN Connector
D

T16
RJ45_MIDI0+
RJ45_MIDI0-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MIDI1+
RJ45_MIDI1-

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI2+
RJ45_MIDI2-

LAN_MIDI3+
LAN_MIDI3-

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MIDI3+
RJ45_MIDI3-

350UH_IH-037-2

C671

C681

0.1U_0402_16V4Z
2
2

R549
75_0402_1%

C690

0.1U_0402_16V4Z
2

R525
75_0402_1%

0.1U_0402_16V4Z

C656 68P_0402_50V8J
@
2
1
LAN_LINK#

33 LAN_LINK#
D22
PJDLC05C_SOT23-3
@

R541
75_0402_1%

R522
75_0402_1%

0.1U_0402_16V4Z

C686

LAN_MIDI3+
LAN_MIDI3-

33
33

220P_0402_50V7K
C663

LAN_ACTIVITY#
LAN_LINK#

LAN_MIDI2+
LAN_MIDI2-

1
1K_0402_5%

33
33

LAN_MIDI2+
LAN_MIDI2-

2
R518

+3V_LAN

24
23
22

MCT1
MX1+
MX1-

TCT1
TD1+
TD1-

LAN_MIDI1+
LAN_MIDI1-

33
33

LAN_MIDI0+
LAN_MIDI0-

LAN_MIDI1+
LAN_MIDI1-

4
5
6

33
33

LAN_MIDI0+
LAN_MIDI0-

1
2
3

RJ45_GND

Place close to TCT pin

+3V_LAN

2
R140

40mil

1
1K_0402_5%

220P_0402_50V7K
C297

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00


TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

Green LED+

10

Green LED-

RJ45_MIDI0+

PR1+

RJ45_MIDI0-

PR1-

RJ45_MIDI1+

PR2+

RJ45_MIDI2+

PR3+

RJ45_MIDI2-

PR3-

RJ45_MIDI1-

PR2-

RJ45_MIDI3+

PR4+

RJ45_MIDI3-

PR4-

LAN_ACTIVITY#

33 LAN_ACTIVITY#

JRJ45

2
@

11

Yellow LED+

12

Yellow LED-

68P_0402_50V8J

14
13

SHLD1
SHLD2

SANTA_130451-K
CONN@

1
C292

RJ45_GND

LANGND
1

C661
1000P_1206_2KV7K

1
C660

40mil

C659
4.7U_0603_6.3V6K

0.1U_0402_16V4Z
B

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LAN Magnetic & RJ45


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

34

of

59

Rev
1.0

2
R302

+3VS

1
0_1206_5%

For Wireless LAN

+3VS_W LAN

60mil
+3VS_W LAN

+1.5VS

C440
4.7U_0805_10V4Z

C423
0.1U_0402_16V4Z

+3VS_W LAN

C452
4.7U_0805_10V4Z

C441
0.1U_0402_16V4Z

C434
0.1U_0402_16V4Z

C442

Mini Card Power Rating

0.1U_0402_16V4Z

Power

JMINI1
R323 1

@
2 0_0402_5%
(WLAN_BT_DATA)
(WLAN_BT_CLK)

14 MINI1_CLKREQ#
14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

14 PCIE_DTX_C_PRX_N2
14 PCIE_DTX_C_PRX_P2

14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2
+3VS_W LAN
2

R280 1

E51TXD_P80DATA1_R
E51RXD_P80CLK

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42 (WWAN_LED#)
44 (WLAN_LED#)
46
48
50
52

+3VS_W LAN
+1.5VS

W L_OFF#
PLT_RST_BUF#
R303 1
R299 1
@

Auxiliary Power (mA)

Normal

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

W L_OFF# 37
PLT_RST_BUF# 17
+3VS
+3V

2 0_0603_5%
2 0_0603_5%
0_0402_5%
MINI1_SMBCLK
R292 1
@
2
MINI1_SMBDATA
@
1
2
R288 0_0402_5%

PCH_SMBCLK 12,14,21
PCH_SMBDATA 12,14,21

USB20_N12 17
USB20_P12 17
R291 1

2 0_0402_5%
MINI1_LED# 37

(9~16mA)
R285
100K_0402_5%

53
54
55
56

G1
G2
G3
G3

37 E51TXD_P80DATA
37 E51RXD_P80CLK

0_0402_5%
2

1
3
5
7
9
11
13
15

PCH_PCIE_W AKE#

15,33 PCH_PCIE_W AKE#

Primary Power (mA)

ACES_88910-5204
CONN@

+3VS_W LAN

4 mm High

+3VS_W W AN

C460
3G@
0.1U_0402_16V4Z

For 3G / GPS

+3VS_W W AN

(Port 9)

+3VS_W W AN

Peak: 2.75A
Normal: 1.1A
1 3G@
R352

1
2
3
4
5
6
7
8
9
10
GND
GND

2
0_1206_5%
1

C465
@
150U_B2_6.3VM_R35M

1
C801
3G@

C173
3G@
10U_0603_6.3V6M

47P_0402_50V8J

Close to WWAN CONN

+3VS_W W AN

R350
100K_0402_5%

JP4

1
2
3
4
5
6
7
8
9
10
11
12

+3VS

To 3G Module Connect
W W AN_OFF#

W W AN_OFF# 37
W W AN_LED# 37
USB20_N13 17
USB20_P13 17
USB20_N10 17
USB20_P10 17

ACES_87036-1001-CP
CONN@

1109 RF request

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

MINI CARD (WLAN & TV-Tuner)


Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Monday, January 04, 2010

Sheet
E

35

of

59

Rev
1.0

+3V
+5VALW

+USB_VCCB
U46

U17

C424

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

R250
100K_0402_5%

8
7
6
5

1
2
3
4

1
2
R251
10K_0402_5%

RT9715BGS_SO8
4.7U_0805_10V4Z
2

SYSON#

C736

USB_OC#2 17

2
43

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

R681
100K_0402_5%

8
7
6
5

+USB_VCCA

+5VALW

+3V

1
2
R680
10K_0402_5%

RT9715BGS_SO8

USB_OC#0 17

4.7U_0805_10V4Z
2

C408

0.1U_0402_16V4Z

C744
1

0.1U_0402_16V4Z

SYSON#

SYSON#

2009/08/14 CHANGE cap


D26

CH3

CH2

+USB_VCCA

USB20_N1_1

W=100mils

USB/B Conn.

+USB_VCCA

Vp

Vn

C726

220U_6.3V_M_R17
USB20_P1_1

CH4

CH1

(Port 0,2)

+USB_VCCA

C728

2009/08/25 Update Footprint(follow NAL00)


2
470P_0402_50V7K

CM1293-04SO_SOT23-6
R667 1

2 0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12

USB Conn.
(Port 1)
JUSB1

17

USB20_N1

USB20_N1
L68

USB20_N1_1
USB20_P1_1

17

USB20_P1

USB20_P1

OCE2012120YZF_0805
@
1
2
R668
0_0402_5%

1
2
3
4
5
6
7
8

+USB_VCCB

JUSB2

VBUS
DD+
GND
GND
GND
GND
GND

13
14

GND
GND

W=100mils

1
2
3
4
5
6
7
8
9
10
11
12

USB20_N0
USB20_P0
USB20_N2
USB20_P2

USB20_N0 17
USB20_P0 17
USB20_N2 17
USB20_P2 17

ACES_85201-1205N
CONN@

SUYIN_020133GB004M51PZR
CONN@

09/12/28 ADD USB common mode choke


S COM FI_ SUPERWORLD OCE2012120YZF

+3VALW

10

2
Q51
BT@
AO3413L_SOT23-3

W=40mils
+BT_VCC

1
C796
BT@
4.7U_0805_10V4Z

5IN1_LED# 38
USB20_N9
USB20_P9

C445
4.7U_0805_10V4Z
1
2

(Port 11)

C795
BT@

2
0.1U_0402_16V4Z

USB20_N9 17
USB20_P9 17

R713
300_0603_5%
BT@

2
G

JCR1
ACES_85201-08051
CONN@

2008/08/10

Issued Date

Deciphered Date

8
7
6
5
4
3
2
1

USB20_P11 17
USB20_N11 17

(WLAN_BT_DATA)
(WLAN_BT_CLK)

BT Wire Cable Note:


Pin 3, Pin 4 NC

Q50
2N7002E-T1-GE3_SOT23-3
BT@

Compal Electronics, Inc.


2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

GND 8
7
6
5
4
3
2
GND 1

ACES_87213-0800G
CONN@

Compal Secret Data

Security Classification

+BT_VCC

JBT1

GND
GND
8
7
6
5
4
3
2
1

1 BT@
2
R706
10K_0402_5%

C788
BT@
0.1U_0402_16V4Z

+3VS

10
9
8
7
6
5
4
3
2
1

BT_ON#

BT Conn.
C790
BT@
1U_0603_10V4Z

Card Reader Conn.

BT_ON#

37

C789
BT@
0.1U_0402_16V4Z

2009/08/24 CHANGE Conn to FFC Type

+3VS

Title

USB / BT / USBB
Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
E

36

of

59

Rev
1.0

SM010015410 300ma 80ohm@100mhz DCR 0.3

1000P_0402_50V7K

0.1U_0402_16V4Z

18
EC_SCI#
15 PM_CLKRUN#

+3VALW

1
R392
1
R395
1
R422

2 LID_SW #
100K_0402_5%

1
R374
1
R373

2 KSO1
47K_0402_5%
2 KSO2
47K_0402_5%

1
R426

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
EC_ACIN
MINI1_LED#
LOCAL_DIM
COLOR_ENG_EN
INVT_PW M
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PW R_SUSP_LED
W LAN_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_CRY1
EC_CRY2

122
123

2 EC_PME#
10K_0402_5%

HIGH

EC_PROJECTID

LOW
45
45
14,23
14,23

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

R400 2

R402 1

2
100K_0402_5%

2
100K_0402_5%
2
100K_0402_5%

EC_SMB_CK2
1
2.2K_0402_5%
EC_SMB_DA2
1
2.2K_0402_5%

2 GFX_CORE_PW RGD
10K_0402_5%

1 E51TXD_P80DATA
R508

(NUM_LED#)

15

SUSCLK

39
ON/OFF
38 PW R_SUSP_LED
38 W LAN_LED#

1
R740

2
0_0402_5%

AVCC
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
GFX_CORE_PW RGD
W W AN_LED#

AD_BID0

DAC_BRIG 29
EN_DFAN1 42
IREF
47
CALIBRATE# 47

R382
18K_0402_5%

Rb

EC_MUTE# 41
GFX_CORE_PW RGD 53
W W AN_LED# 35

TP_CLK
TP_DATA

C496

2
0.1U_0402_16V4Z

TP_CLK

2
R404
TP_DATA
2
R408

TP_CLK 38
TP_DATA 38

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

3S/4S#
65W /90W #
SBPW R_EN
LID_SW #

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

W W AN_OFF#
PCH_TEMP_ALERT#
FSTCHG
BATT_GRN_LED#
3G_LED#
BATT_AMB_LED#
PW R_LED
SYSON
VR_ON
ACIN

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SW I#
EC_PW ROK
BKOFF#
W L_OFF#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

3S/4S# 47
65W /90W # 47
SBPW R_EN 43
LID_SW # 38

SPI Device Interface


SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

XCLK1
XCLK0

1 LOCAL_DIM
R732
1 COLOR_ENG_EN
R733

Board ID definition,
Please see page 3.

R389
100K_0402_5%

Ra

BATT_TEMP 45

BATT_OVP 47
ADP_I
47

3S/4S#

11
24
35
94
113

R398 2

BATT_TEMP
BATT_OVP
ADP_I
AD_BID0
EC_PROJECTID

PS2 Interface

GND
GND
GND
GND
GND

+3VS

63
64
65
66
75
76

+3VALW

+5VS

15 PM_SLP_S3#
15 PM_SLP_S5#
18
EC_SMI#
15,23 EC_ACIN
35 MINI1_LED#
29 LOCAL_DIM
29 COLOR_ENG_EN
29
INVT_PW M
42 FAN_SPEED1
36
BT_ON#

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

2 EC_SMB_CK1
2.2K_0402_5%
2 EC_SMB_DA1
2.2K_0402_5%

ACOFF

65W /90W #

2
R423
2
R424

+3VALW

1
100K_0402_5%
1
100K_0402_5%

PCH_TEMP_ALERT# Pull high at Page 18 (PCH side)


EC_SI_SPI_SO 38
EC_SO_SPI_SI 38
EC_SPICLK 38
EC_SPICS#/FSEL# 38

+3VALW

W W AN_OFF# 35
PCH_TEMP_ALERT# 18,21
FSTCHG 47
BATT_GRN_LED# 38
3G_LED# 38
BATT_AMB_LED# 38
PW R_LED 38
SYSON
43,50
VR_ON
39,54
ACIN
38,43,44

R394
100K_0402_5%
@

Ra
(CAPS_LED#)

EC_PROJECTID

Rb

EC_RSMRST# 15
EC_LID_OUT# 14
EC_ON
39
EC_SW I# 15
EC_PW ROK 15,39
BKOFF# 29
W L_OFF# 35

C511
0.1U_0402_16V4Z
@

Project ID definition,
Please see page 3.
EC_CRY1

15P_0402_50V8J

PM_SLP_S4# 15
ENBKL
16,23
EAPD
40
SUS_PW R_DN_ACK 15
SUSP#
39,43,47,49
PBTN_OUT# 5,15,21
EC_PME# 33

ENBKL
EAPD
SUS_PW R_DN_ACK
SUSP#
PBTN_OUT#
EC_PME#

R397
0_0402_5%

C536

KB926QFD3_LQFP128_14X14

1
4.7K_0402_5%
1
4.7K_0402_5%

EC_CRY2

X1

ACOFF

BEEP#
40
ME_OVERRIDE 13
47,48
ECAGND
2
1
C491
0.01U_0402_16V7K

AD

ACES_85205-0400
@
BEEP#

OSC

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

PWM Output

21
23
26
27

OSC

12
13
37
20
38

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

C537
15P_0402_50V8J

32.768KHZ_12.5PF_Q13MC14610002

C539
4.7U_0805_10V4Z

C490
BATT_TEMP
2
C489
BATT_OVP
2
C534
ACIN
2

20mil

L33
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

ENBKL

1
R425

2
100K_0402_5%

100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1

SM010015410 300ma 80ohm@100mhz DCR 0.3

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

E51RXD_P80CLK
E51TXD_P80DATA

NC

C487

5,17,21,33 PLT_RST#

1 47K_0402_5%

1
2
3
4

NC

R375 2

Place on MiniCard

+3VALW

1
2
3
4

EC_RST#
EC_SCI#

17 CLK_PCI_LPC
+3VALW

E51RXD_P80CLK 35
E51TXD_P80DATA 35

JP5

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

Place on RAM door

E51RXD_P80CLK
E51TXD_P80DATA

ACES_85205-0400
@

AGND

1 47_0402_5%

1
2
3
4
5
7
8
10

69

C516
22P_0402_50V8J
R403 2
2
1

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

0.1U_0402_16V4Z

67

9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC

1109 RF request

18
EC_GA20
18 EC_KBRST#
13
SERIRQ
13 LPC_FRAME#
13
LPC_AD3
13
LPC_AD2
13
LPC_AD1
13
LPC_AD0

1
2
3
4

1
2
3
4

C505

U32

+3VALW
JP6

KSO[0..17] 38

1
1
1000P_0402_50V7K

KSO[0..17]

2
2
0.1U_0402_16V4Z

C488

2
2
0.1U_0402_16V4Z

+3VALW _EC

38

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
C519
C533
C538
C524

C512

KSI[0..7]

For EC Tools
KSI[0..7]

20mil

L32
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

ECAGND

1
R385
0_0805_5%

40mil

+3VALW

Title

EC ENE KB926
Size
B
Date:

Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet
1

37

of

59

Rev
1.0

1
R391

C506 1

2
0_0603_5%

20mil
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#

R406 1
R390 1

+3VALW

+5VS
U30

37 EC_SPICS#/FSEL#

1
3
7
4

To TP/B Conn.

2 0.1U_0402_16V4Z

+SPI_VCC

220mils

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

JTP1
8
6
5
2

EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

R387 1
R388 1
R407 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

EC_SPICLK 37
EC_SO_SPI_SI 37
EC_SI_SPI_SO 37

MX25L8005M2C-15G_SOP8
7
8

(Right)

C682
@
2
2
100P_0402_50V8J 100P_0402_50V8J

VDD
SCK
SI
SO

+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

8
6
5
2

KSI[0..7]

KSI[0..7]

KSO[0..17]

37

Reserved for BIOS simulator.


Footprint SO8

KSO[0..17] 37

MX25L1005AMC-12G_SOP8
@
R386

0_0402_5%

+5VS
1

@
C497
33P_0402_50V8K

TP_CLK

LEFT_BTN#

TP_DATA

RIGHT_BTN#

D19
PJDLC05C_SOT23-3

CE#
WP#
HOLD#
VSS

D18
PJDLC05C_SOT23-3

C684
0.1U_0402_16V4Z

SW2
SMT1-05-A_4P
1

RIGHT_BTN#

SW3
SMT1-05-A_4P
1

2
5
6

LEFT_BTN#

1
3
7
4

EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#

INT_KBD Conn.

28
27

G2
G1

5
6

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1
C683
@

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

U31

(Left)
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK 37
TP_DATA 37

LEFT_BTN#
RIGHT_BTN#

ACES_85201-0605N
CONN@

150mils
JKB1

1
2
3
4
5
6

1
2
3
4
5
6
GND
GND

+3VALW

ACES_88747-2601
CONN@
100P_0402_50V8J

100P_0402_50V8J

KSO15

C34

100P_0402_50V8J

LED/B RIGHT
KSO7

C26

100P_0402_50V8J

JLED1
1
2
3
4
5
6
7
8
9
10
GND
GND

KSO14

C33

100P_0402_50V8J

KSO6

C25

100P_0402_50V8J

KSO13

C32

100P_0402_50V8J

KSO5

C24

100P_0402_50V8J

KSO12

C31

100P_0402_50V8J

KSO4

C23

100P_0402_50V8J

KSI0

C37

100P_0402_50V8J

KSO3

C22

100P_0402_50V8J

KSO11

C30

100P_0402_50V8J

KSI4

C41

100P_0402_50V8J

KSO10

C29

100P_0402_50V8J

KSO2

C21

100P_0402_50V8J

KSI1

C38

100P_0402_50V8J

KSO1

C20

100P_0402_50V8J

KSI2

C39

100P_0402_50V8J

KSO0

C19

100P_0402_50V8J

KSO9

C28

100P_0402_50V8J

KSI5

C42

100P_0402_50V8J

KSI3

C40

100P_0402_50V8J

KSI6

C43

100P_0402_50V8J

KSO8

C27

100P_0402_50V8J

KSI7

C44

100P_0402_50V8J

LED/B LEFT

+3VS

JLED2
1
2
3
4
5
6
7
8
9
10
11
12

LID_SW#
ACIN_LED#
3G_LED#
WLAN_LED#
MEDIA_LED#
PWR_LED#
ON/OFFBTN#

+3VALW
LID_SW# 37

1
2
3
4
5
6
7
8
9
10
GND
GND

3G_LED# 37
WLAN_LED# 37
+3VS
ON/OFFBTN# 39

ACES_85201-1005N
CONN@

1
2
3
4
5
6
7
8
9
10
11
12

LID_SW#
ACIN_LED#
3G_LED#
WLAN_LED#
MEDIA_LED#
PWR_LED#
ON/OFFBTN#

+3VALW

+3VS

Q54A

R272
@
100K_0402_5%
1

C36

C35

KSO17

+3VS

MEDIA_LED#

5IN1_LED# 36

DMN66D0LDW-7_SOT363-6
3

Q54B

PCH_SATALED# 13

DMN66D0LDW-7_SOT363-6

ACES_85201-1005N
CONN@

KSO16

+3VS

LED Status

Power/SUS
ON

SUS

NEW70/80/90 Blue Amber

Battery

3G/WLAN

Full Charge

3G

Blue Amber

Blue Amber

BlueTooth

ACIN

WLAN

ACIN_LED#

PWR_LED#
37,43,44

LED1
1 7080@ 2
2
R344
3.9K_0402_5%

Q53
@

2
G

ACIN

HT-191NB5_BLUE

+3VALW

1 7080@ 2
2
R343
2.2K_0402_5%

LED3
+3VS

2N7002E-T1-GE3_SOT23-3

PWR_SUSP_LED#

HT-191UD5_AMBER

PWR_SUSP_LED#

PWR_LED#
LED4
Q26A
BATT_GRN_LED# 37

37

PWR_LED

DMN66D0LDW-7_SOT363-6

HT-191NB5_BLUE

R340
100K_0402_5%

Q26B
DMN66D0LDW-7_SOT363-6

37 PWR_SUSP_LED
R335
100K_0402_5%

BATT_GRN_LED#

1 7080@ 2
2
R341
2.2K_0402_5%

1 7080@ 2
2
R342
3.9K_0402_5%

BATT_AMB_LED#

LED2
1

+3VALW

BATT_AMB_LED# 37

HT-191UD5_AMBER

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BIOS, I/O Port & K/B Connector


Document Number

NEW70 M/B LA-5891P Schematic


Thursday, January 07, 2010

Sheet

38

of

59

Rev
1.0

Power Button
ON/OFF switch

+3VALW

R409

38 ON/OFFBTN#

100K_0402_5%
1

TOP Side
SW1
SMT1-05-A_4P
1
3
4

37

51ON#

44

D12
CHN202UPT_SC70-3
EC_ON

EC_ON

Q32
2N7002E-T1-GE3_SOT23-3

R413

Bottom Side

2
G

37

6
5

51ON#

10K_0402_5%
1

SW4
SMT1-05-A_4P
1
3
4

6
5

ON/OFF

2
ON/OFFBTN#

Test Only

Power ON Circuit
+3VS
+3VALW

+3VALW

CH751H-40PT_SOD323-2
@
C455
1U_0603_10V6K
@

14
P

For South Bridge

SYS_PWROK_1 1
R332

U21B
SN74LVC14APWLE_TSSOP14
@

2
0_0402_5%

EC_PWROK 15,37

VR_ON

U21A
SN74LVC14APWLE_TSSOP14

37,54

14

R331
180K_0402_5%
D7

+3VS
+3VALW

+3VALW

2N7002E-T1-GE3_SOT23-3

14
P

14
P

1
R320

O
G

U21D
SN74LVC14APWLE_TSSOP14
2
0_0402_5%

VS_ON

52

VGA_ON

23,43,51,52

For VTT

Q25
C456
0.1U_0402_16V7K

U21C
SN74LVC14APWLE_TSSOP14

1
SUSP

5
2

2
G
3

SUSP

R334
249K_0402_1%
SUSP# 1
2

37,43,47,49 SUSP#
43,49

R333
10K_0402_1%
@

SUSP#
1
R321

2
0_0402_5%

+3VS
1

+3VALW

2N7002E-T1-GE3_SOT23-3

C447
DIS@
1U_0603_10V6K
1

14

U21F
SN74LVC14APWLE_TSSOP14

P
I

O
G

13

10

12

1
R317

DIS@ 2
0_0402_5%

Q23
DIS@

2
G

43 DGPU_PWR_EN#

U21E
SN74LVC14APWLE_TSSOP14

11
D

2 0.1U_0402_16V4Z

14,18,21,43 DGPU_PWR_EN
4

14

R319
31.6K_0402_1%
@

R318
10K_0402_1%
1 DIS@ 2

+3VALW

C448
1

DGPU_PWR_EN
1
R316

2
0_0402_5%

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Power OK
Document Number

NEW70 M/B LA-5891P Schematic


Sheet

Tuesday, December 29, 2009


E

39

of

59

Rev
1.0

2
0_0805_5%

D32
CH751H-40PT_SOD323-2

4.75V

+VDDA

R704

BYP

1
2
C439
0.01U_0402_16V7K
@

(output = 300 mA)

37

C780 1

BEEP#

1U_0402_6.3V4Z
13

C785 1

PCH_SPKR

1U_0402_6.3V4Z

R699

2
B

R701

Q49

1
R694

2SC2411K_SOT23-3

560_0402_5%

INT_MIC_R

External MIC

R702 2

1K_0402_1%
1

INT_MIC

C775 1

C776 1

AVDD1

Place near Codec

41

MIC1_L

41

MIC1_R

MIC1_L

C777 1

MIC1_R

C778 1

35

AMP_LEFT

36

AMP_RIGHT

MIC2_L

LOUT2_L

39

MIC2_R

LOUT2_R

LINE1_L

SPDIFO2

LINE1_R

DMIC_CLK1/2

MIC1_C_L
21
4.7U_0603_6.3V6K
MIC1_C_R
2
22
4.7U_0603_6.3V6K
MONO_IN
12

LINE1_VREFO

NC

LINE2_VREFO

DMIC_CLK3/4

MIC2_VREFO

10

13 HDA_SYNC_AUDIO

13 HDA_SDOUT_AUDIO

R695 2
R685 2

41 MIC_PLUG#
41 HP_PLUG#
37

EAPD

SENSE_A
SENSE_B

1 20K_0402_1%
1 5.11K_0402_1%
1
R672

2
0_0402_5%

BITCLK
MIC1_R
PCBEEP_IN

SDATA_IN
MONO_OUT
CBP

RESET#
CPVEE
SYNC
MIC1_VREFO
SDATA_OUT
HPOUT_R

2
3
13
34

GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B

47

EAPD

48
4
7

GNDA

+3VS

C746
10U_0805_10V4Z

AMP_LEFT 41

272@amp

AMP_RIGHT 41

41
45
46
43
44

1
R686

2 C752
22P_0402_50V8J

2
1
0_0402_5%

For EMI

HDA_BITCLK_AUDIO 13

MIC1_L

11

2
0_0805_5%

0.1U_0402_16V4Z

LOUT_R

1
R707

LOUT1_L

19

13 HDA_RST_AUDIO#

LINE2_R

20
MIC2_VREFO

L71 1
2
MBK1608121YZF_0603
1

C748

LINE2_L

18

Internal MIC REF


272@

C760

15

24

2
0_0805_5%

SM010032020 600ma 120ohm@100mhz DCR 0.25

+3VS_DVDD

14

MIC2_C_L
16
4.7U_0603_6.3V6K
MIC2_C_R
17
4.7U_0603_6.3V6K
23

1
R308

U48

2
0.1U_0402_16V4Z

DVDD

DVDD_IO

38

0.1U_0402_16V4Z

C772

25

C738
10U_0805_10V4Z

AVDD2

+VDDA

2
0_0805_5%

GND

Place near Codec

10mil

1
R670

2
+AVDD_HDA

40mil
0.1U_0402_16V4Z
1
1
C739

GNDA

2
2.4K_0402_1%

HD Audio Codec

L70 1
2
FBMA-L11-160808-800LMT_0603

2
0_0805_5%

GND

D31
CH751H-40PT_SOD323-2

SM010015410 300ma 80ohm@100mhz DCR 0.3

1
R283

MONO_IN

560_0402_5%
1

C773
1
1U_0402_6.3V4Z

C
2

2
0_0805_5%

SPDIFO1

CBN

HDA_SDIN0_AUDIO

HDA_SDIN0 13

2.2U_0402_6.3VM
31
28
32

C754 1

10mil
MIC1_VREFO
HP_RIGHT

External MIC REF


272@

HP_RIGHT 41

1
C758
2

MIC2_VREFO

2.2U_0402_6.3VM

30

VREF

27

CODEC_VREF

40

R673 1

HPOUT_L

33

AVSS1
AVSS2

2
33_0402_5%

29

JDREF

DVSS1
DVSS2

1
R687

37

HP_LEFT

10mil

C764 1
C765 1

2 0.1U_0402_16V4Z
2 10U_0805_10V4Z

Int. MIC

2 20K_0402_1%

Place next pin27


HP_LEFT 41

26
42

1
2

For EMI

15mil

JP1
1
2

SHDN

1
R329
2
1U_0402_6.3V4Z

C783
R696
10K_0402_5%

10K_0402_5%

G9191-475T1U_SOT23-5
@

2
0_0805_5%

R703
2.2K_0402_5%

15mil

INT_MIC_L

1
L29

INT_MIC_R
2
FBMA-L11-160808-700LMT_2P

ALC272X-GR_LQFP48_7X7

ACES_88266-02001
CONN@

C786
220P_0402_50V7K

AGND

3
4

DGND

G1
G2

0.1U_0402_16V4Z

OUT
GND

IN

3
2

2
C438

40mil

C444

U19

60mil

0.1U_0402_16V4Z

L28 1
2
FBMA-L11-201209-221LMA30T_0805
@
L27 1
2
FBMA-L11-201209-221LMA30T_0805

+5VAMP
+5VS

SM010014520 3000ma 220ohm@100mhz DCR 0.04

1
R339
R698
10K_0402_5%

+3VS

1
R298

+5VAMP

D10
PJDLC05C_SOT23-3
@

SM010004010 300ma 70ohm@100mhz DCR 0.3

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

HD Audio Codec ALC272X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

40

of

59

Rev
1.0

Ri
90k
70k
45k
25k

0.1U_0402_16V4Z
1

10 dB

C457
2

+5VAMP

16
15
6

R710
100K_0402_5%

VDD
PVDD1
PVDD2
AMP_RIGHT

C779

C793 1

2 0.47U_0603_10V7K

GAIN1

ROUT+

18

SPKR+

14

SPKR-

SPKL+

SPKL-

RIN-

ROUT-

AMP_LEFT

1
C791

2
1
0.47U_0603_10V7K R712

AMP_C_LEFT
2
0_0603_5%

EC_MUTE#

19

LINLOUT-

NC
EC_MUTE#

BYPASS
SHUTDOWN

R708
100K_0402_5%

12

Keep 10 mil width

10
2

GND5
GND1
GND2
GND3
GND4

37

@ R711
100K_0402_5%

LIN+
LOUT+

40

GAIN0

AMP_C_RIGHT 17
2
0_0603_5%

GAIN1

GAIN0

2
1
0.47U_0603_10V7K R697

RIN+

40

2 0.47U_0603_10V7K

@ R709
100K_0402_5%

C453
10U_0805_10V4Z
U50

C792 1

+5VAMP

GAIN0 GAIN1 AV(inv)


0
0
6dB
0
1
10dB
1
0
15.6dB
1
1
21.6dB

C794
0.47U_0603_10V7K

21
20
13
11
1

TPA6017A2PWPR_TSSOP20

C787
330P_0402_50V7K

40

HP_LEFT

R705 1

2 56.2_0603_1%

HPOUT_L_1

40

HP_RIGHT

R700 1

2 56.2_0603_1%

HPOUT_R_1

1
L78
1
L77

(Use NAL00 PCB Footprint)


C784

330P_0402_50V7K
1

Headphone Out
JHP1
1
2

2 HPOUT_L_2
FBMA-L11-160808-700LMT_2P
2 HPOUT_R_2
FBMA-L11-160808-700LMT_2P

3
4

SM010004010 300ma 70ohm@100mhz DCR 0.3


40

HP_PLUG#

HP_PLUG#

MIC1_VREFO

SINGA_2SJ-0960-C01
CONN@

1
1

Headphone Out

D29
CH751H-40PT_SOD323-2

D27
CH751H-40PT_SOD323-2

Int. Speaker Conn.

HP_PLUG#

MIC_PLUG#

D30
PJDLC05C_SOT23-3

Left Side

1
2

R676
4.7K_0402_5%

R688

D11
PJDLC05C_SOT23-3

G1
G2
ACES_88266-02001
CONN@

40

MIC1_L

R689 1

40

MIC1_R

R674 1

MIC1_L_1
2
1K_0603_1%
MIC1_R_1
2
1K_0603_1%

L73 1
2
FBMA-L11-160808-700LMT_2P
L72 1
2
FBMA-L11-160808-700LMT_2P

SM010004010 300ma 70ohm@100mhz DCR 0.3

C743
220P_0402_50V7K

Right Side

MIC JACK

4.7K_0402_5%

JMIC1

MIC1_L_R

1
2

MIC1_R_R

3
2

3
4

20mil

1
2

SPK_L+
SPK_L-

2 0_0603_5%
2 0_0603_5%

R354 1
R359 1

JSPK2
SPKL+
SPKL-

D28
C759
PJDLC05C_SOT23-3
220P_0402_50V7K

4
40

MIC_PLUG#

MIC_PLUG#

JSPK1
SPK_R+
SPK_R-

1
2

1
2

SINGA_2SJ-A960-C01
CONN@

2 0_0603_5%
2 0_0603_5%
2

SPKR+ R348 1
SPKR- R347 1

D9
PJDLC05C_SOT23-3

3
4

G1
G2
ACES_88266-02001
CONN@

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

Amplifier & Audio Jack

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
E

41

of

59

Rev
1.0

H16
H_3P0
@

H22
H_3P0
@

H3
H_3P0

H5
H_3P0

H1
H_3P0

H2
H_3P0

H20
H_3P0

H21
H_3P0

H17
H_3P0

H6
H_3P0

H15
H_3P0

H10
H_3P0

GNDA

H11
H_3P0
H14
H_4P2

H13
H_4P2

H8
H_4P2
@

+5VS

10U_0805_10V4Z
2

C542
1

+5VS

FAN1 Conn

H9
H_4P2

H12
H_4P0

C562
1000P_0402_50V7K

JFAN1
1
2
3

FD4

ACES_85205-03001
CONN@

FD2
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD3
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD1

FAN_SPEED1

H7
H_3P0N

+VCC_FAN1

40mil
37

R445
10K_0402_5%

H19
H_3P0X3P5N

H18
H_3P4

C563
1000P_0402_50V7K
1
2

+3VS

2
@
BAS16_SOT23-3
C568
10U_0805_10V4Z
1
2

C570
0.1U_0402_16V4Z

H4
H_4P0

D15
1

APL5607KI-TRG_SO8

D13
1SS355_SOD323-2
@

8
7
6
5

EN_DFAN1

+VCC_FAN1
1
300_0402_5%

GND
GND
GND
GND

37

2
R461

EN
VIN
VOUT
VSET

U35
1
2
3
4

2008/08/10

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

FAN & Screw Hole


Document Number

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet

42

of

59

Rev
1.0

+5VALW

C407

10U_0805_10V4Z
5VS_GATE

2
1
6

R226
@
470_0603_5%

10U_0805_10V4Z
2
2
1U_0603_10V4Z

DMN66D0LDW-7_SOT363-6

R345
100K_0402_5%

DMN66D0LDW-7_SOT363-6

C756

20mil

0.1U_0603_25V7K

+VSB

+5VALW

10mil
R255 2

200K_0402_5%
1

1
Q16A

SBPWR_EN#

Q16B
DMN66D0LDW-7_SOT363-6

R346
100K_0402_5%

C421
@
0.1U_0603_25V7K
39,49

SUSP

SUSP

SBPWR_EN#

3V_GATE

DMN66D0LDW-7_SOT363-6

C392

SUSP

C393

1
Q47A

SUSP

SYSON

SYSON

Q27A
37,50

10mil

2
1
R684
200K_0402_5%

+VSB

SYSON#

SYSON#

40mil

Q47B

20mil

36

+3V

10U_0805_10V4Z
2
2
1U_0603_10V4Z

R692
470_0603_5%

10U_0805_10V4Z
2
2
10U_0805_10V4Z

C767

JUMP_43X79
U14
@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

2
C761

C766

J5
1
1

R337
100K_0402_5%

Short J5 for PCH VCCSUS3.3

+3VALW

U49
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
4

C763
1

+3VALW TO +3V(PCH AUX Power)

+5VS

3 1

+5VALW TO +5VS
+5VALW

DMN66D0LDW-7_SOT363-6

+3VALW TO +3VS
+3VALW

2
1

DIS@
2
10U_0805_10V4Z

330U_2.5V_M_R15

2
20

R502
470_0603_5%
DIS@

SBPWR_EN#

SBPWR_EN#

DIS@

2N7002E-T1-GE3_SOT23-3

Q37
@

2
G

SYSON#

2
1
1
3

1
2

2N7002E-T1-GE3_SOT23-3

3
2

C711
DIS@
0.1U_0603_25V7K

VGA_ON#

2009/08/17 add VGA_ON#

R232
100K_0402_5%
DIS@
1

1
R584

VGA_ON#

23,51,52 VGA_ON#

510K_0402_5%

2
G

Q38
@
S 2N7002E-T1-GE3_SOT23-3

Q15
DIS@

2
G

23,39,51,52 VGA_ON
D
R231
DIS@
22K_0402_5%

2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge

2008/08/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Q24
DIS@

+5VALW

SUSP

Q40A
DIS@

2N7002E-T1-GE3_SOT23-3

2
G
S

2N7002E-T1-GE3_SOT23-3

Q36

R593
470_0603_5%
DIS@

1
1

SUSP

2
G
S

Q40B
DMN66D0LDW-7_SOT363-6
DIS@

1.5VSDGPU_GATE

DMN66D0LDW-7_SOT363-6
ACIN

1
1

Q33

10mil
2
1
R586
510K_0402_5%
DIS@
VGA_ON#

C713
DIS@

2
2
1U_0603_10V4Z
10U_0805_10V4Z

@
R569
470_0603_5%
@

R524
470_0603_5%

+1.5V

+1.8VS

SUSP

C717
DIS@

2
10U_0805_10V4Z

2
G

1
2
3

R325
100K_0402_5%
DIS@

8
7
6
5

2
G

1
2
G

R427
470_0603_5%

DGPU_PWR_EN#

14,18,21,39 DGPU_PWR_EN

+1.5VSDGPU

DIS@

Q10
@
S 2N7002E-T1-GE3_SOT23-3

Q11

R326
100K_0402_5%
DIS@

Q34
@
2N7002E-T1-GE3_SOT23-3

U40
AO4430L_SO8

C714
D

+1.05VS_VTT

+1.5V

0.1U_0603_25V7K

2
G

+1.5V to +1.5VSDGPU for GPU

+VSB

R200
22_0603_5%

SUSP

20mil

+0.75VS

+5VALW

C346

ACIN

ACIN

37,38,44

510K_0402_5%

6
2

Q9A
DMN66D0LDW-7_SOT363-6

Q9B
DMN66D0LDW-7_SOT363-6

1.5VS_GATE

R185 @
SUSP

C650
DIS@
0.1U_0603_25V7K

39 DGPU_PWR_EN#

10mil

2
1
R184
510K_0402_5%

+VSB

0.1U_0402_16V4Z 0.1U_0402_16V4Z

20mil

ACIN

10U_0805_10V4Z
2
2
1U_0603_10V4Z

VGA_ON#

Q1
@
S
2N7002E-T1-GE3_SOT23-3

DMN66D0LDW-7_SOT363-6
510K_0402_5%

R181
470_0603_5%

C338

2
10U_0805_10V4Z

C810

C328

R30
100K_0402_5%
@

C809

Q35A @
DIS@

VGA_ON#

C389

1
R472

C374

Q35B
DMN66D0LDW-7_SOT363-6
DIS@

1.8VSDGPU_GATE

U13
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

10U_0805_10V4Z

10mil
2
1
R505
510K_0402_5%
DIS@

+VSB
+1.5VS

2
G

37 SBPWR_EN

20mil

+1.5V to +1.5VS
+1.5V

1211 EMI ADD 0.1U close PJ5

C664
DIS@

2
2
1U_0603_10V4Z
10U_0805_10V4Z

DMN66D0LDW-7_SOT363-6

C648
DIS@

C624
DIS@

C670

0.1U_0603_25V7K

R31
100K_0402_5%
@
1

U37
DIS@
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

Q22A
SUSP

C450

SUSP

Q22B
DMN66D0LDW-7_SOT363-6

+1.8VSDGPU

3VS_GATE
1

1
2

+1.8VS

10mil

+5VALW

+1.8VS to +1.8VSDGPU for GPU

2
1
R322
200K_0402_5%

R338
10K_0402_5%
R315
470_0603_5%

+VSB

20mil

C446

10U_0805_10V4Z
2
2
1U_0603_10V4Z

3 1

C451

10U_0805_10V4Z
2
2
10U_0805_10V4Z

Q27B
DMN66D0LDW-7_SOT363-6

37,39,47,49 SUSP#

C449

C454

+3VS

U20
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

DC Interface
Document Number

NEW70 M/B LA-5891P Schematic


Thursday, January 07, 2010

Sheet
E

43

of

59

Rev
1.0

VIN

VIN

VIN

VS

PR296
10K_0402_5%

PR297
84.5K_0402_1%

1
2

PC210
0.1U_0603_25V7K
2
1

PR303
10K_0402_1%
1
2

PR298
22K_0402_5%
1
2

8
+

PU18A
LM393DG_SO8
PD1
GLZ4.3B_LL34-2

PR302
10K_0402_1%

P
1

37,38,43 ACIN

PC209
1000P_0402_50V7K

PR299
10K_0402_5%
1
2

47,48 PACIN

PC207
100P_0402_50V8J

1
PC206
1000P_0402_50V7K

PC208
100P_0402_50V8J

ACES_50305-00441-001

2DC_IN_S2

DC_IN_S1

1
2
3
4
GND
GND

PL24
SMB3025500YA_2P
1

PJP1

PR295
1M_0402_1%
1
2

PR301
20K_0402_1%

PC211
1000P_0402_50V7K

RTCVREF

Vin Dectector

Min.
H-->L 16.976V
L-->H 17.430V

Typ
17.525V
17.901V

Max.
17.728V
18.384V

PJ23

+1.0VSPDGPU

+1.0VSDGPU

JUMP_43X118

VIN
2

PJ6

+3VALWP

PD2
LL4148_LL34-2

+3VALW

PJ2

+VGFX_COREP

PR304
68_1206_5%

39

51ON#

+5VALW

+1.5VP

VS
1

PJ11

+VSBP

PC213
0.1U_0603_25V7K

+VSB

JUMP_43X39

+1.8VSP

+1.5V

1
GND

PC214
10U_0805_10V4Z

+1.8VS

+1.05VS_VTT

JUMP_43X118
PJ15
PJ17

+0.75VSP

+VGA_COREP

N2

IN

JUMP_43X118
PJ10
2 2
1 1

JUMP_43X118

PBJ1

ML1220T13RE
<BOM Structure>

+VGA_CORE

JUMP_43X118
PJ16
2 2
1 1

+0.75VS

JUMP_43X39
PC215
1U_0805_25V4Z

JUMP_43X118

+RTCBATT

OUT

PR309
200_0603_5%

PU14
G920AT24U_SOT89-3

3.3V

PJ9

RTCVREF

+CHGRTC

JUMP_43X118

+1.05VS_VTTP

PR311
560_0603_5%
1
2

JUMP_43X118
PJ7
2 2
1 1

PJ14

PR310
560_0603_5%
1
2

+VGFX_CORE

PR308
22K_0402_1%
1
2

PJ5

PC212
0.22U_0603_25V7K

PR307
100K_0402_1%

JUMP_43X118

+5VALWP

JUMP_43X118
2

N1

PJ8
PR305
68_1206_5%

JUMP_43X118
PJ4
2 2
1 1

1
PQ42
TP0610K-T1-E3_SOT23-3

PR306
200_0603_5%
CHGRTCP 1
2

BATT+

JUMP_43X118

PD3
LL4148_LL34-2
2
1

+RTCBATT

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DCIN & DETECTOR


Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009


D

Sheet

44

of

59

10
9
8
7
6
5
4
3
2
1

EC_SMCA
TH
PI

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C

EC_SMDA

PR542
100_0402_1%

GND
GND
8
7
6
5
4
3
2
1

PJP2
SUYIN_200275GR008G13GZR

PR543
100_0402_1%

VL

EC_SMB_DA1 37
1

<40,41>
VMB

VL

GND RHYST1

OT1 TMSNS2

OT2 RHYST2

PR549
9.53K_0402_1%

G718TM1U_SOT23-8

@ PR551
47K_0402_1%
1

VCC TMSNS1

PR550
1K_0402_1%

@ PR547
100K_0402_1%

PU30

+3VALW P

PR546
21K_0402_1%

PH1
100K_0402_1%_NCP15W F104F03RC

PC380
0.01U_0402_25V7K
1

PC379
1000P_0402_50V7K

PR545
10K_0402_1%
1

PC381
0.1U_0603_25V7K
PR548
6.49K_0402_1%
2
1

1
2

PR544
1K_0402_5%

EC_SMB_CK1 37
2

BATT_S1

<40,41>
BATT+

PL44
SMB3025500YA_2P
1
2

CONN@

BATT_TEMP 37

MAINPW ON 18,46,48
2

@ PH2
100K_0402_1%_NCP15W F104F03RC

PQ44
TP0610K-T1-E3_SOT23-3

1
2

PC222
0.1U_0603_25V7K

PR327
22K_0402_1%
1
2

VL

+VSBP

1
PR325
100K_0402_1%

PC221
0.22U_0603_25V7K

B+

PQ45
2
G

2N7002W -T/R7_SOT323-3

PC224
1U_0402_6.3V6K

SPOK

PR330
1K_0402_5%
2
1

46

PR329
100K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2010/08/01

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009


D

Sheet

45

of

59

ISL6237_B+

ISL6237_B+

B+

VBST1

17

DRVL2

30

VOUT2

FB3

32

VL

LL1

16

DRVL1

18

LG5

PGND

22

VOUT1

10

FB1

11

VSW

VREF2

LDOREFIN

28

EN_LDO

PGOOD1

13

TRIP1

12

ILM1

TRIP2

31

ILIM2

14

EN1

27

EN2

2
1
PR340
@ 0_0402_5%
1
2
PR341
0_0402_5%

PC237
220U_6.3VM_R15

SPOK

RT8206BGQW QFN 32P

45
For +5VALWP
Power Budget=8.8A, Ipeak=7A, I max=4.9A
Fsw=300KHz by RT8206 setting.
I=2.61A, 1/2I=1.306A
5uA*PR344=10*Iocpmin*18m*1.3
=>PR344=397K~402K

PR344
402K_0402_1%
2
1
2

VL

PR345
267K_0402_1%

5uA*402K=10*ILIMTmin*18m*1.3
ILIMTmin=8.589A
5uA*402K=10*ILIMTmax*15m*1.1
ILMIT=12.181A
Iocp=9.89A~13.48A

13/5V_TON

PR347
0_0402_5%

21

2
1

PC241
1U_0603_10V6K
2
13/5V_NC

For +3VALWP
Power Budget=4.72A, Ipeak=4.72A, Imax=4A
Iocpmin=4.72*1.2=5.664~5.7A
Fsw=375KHz, I=1.547A, 1/2I=0.773A
5uA*PR345=10*Iocpmin*Rdsonmax*1.3
5uA*PR345=10*5.7A*18m*1.3
PR345=266.76K~267K

PR350
0_0402_5%

2VREF_ISL6237

PC243
@ 0.047U_0402_16V7K
2
1

GND

PGOOD2

TONSE

NC

TP0610K-T1-E3_SOT23-3

@
2

PQ50

080414:PQ23 ,Del @

5V_SKIP

29

PR349
47K_0402_5%

18,45,48 MAINPWON

PR348
0_0402_5%
2
1

@ PR346
0_0402_5%

PD8
1SS355_SOD323-2

PR561
806K_0603_1%

PC242
0.047U_0402_16V7K

VS

3/5V_EN1

PC240
0.22U_0603_25V7K

2VREF_ISL6237

VL

EN_LDO

PC238
680P_0603_50V7K

FB5

SKIPSEL

VREF3

20

PR342
100K_0402_1%
2

PC236
0.1U_0603_25V7K

REFIN2

PR343
200K_0402_5%
1
2

EN_LDO-1

LL2

23

25

LG3

SW 5

SW 3

PC239
0.22U_0603_25V7K

PD7
RLZ5.1B_LL34
1
2

PR336
4.7_1206_5%

2BST5A-1
PR334
4

PC234
0.1U_0603_25V7K

1
2
3

PC235
680P_0603_50V7K

BST5A1
2.2_0603_5%

VBST2

PQ49
AO4712_SO8

HG5

15

PL27
4.7UH_SIL104R-4R7PF_5.7A_30%
2
1

5
6
7
8

DRVH1

PC232
1U_0603_10V6K
1
2

+5VALWP

PQ47
AO4466_SO8

DRVH2

2VREF_ISL6237

VS

3
2
1

PC231
4.7U_0603_6.3V6K
2
1

PC230
1U_0603_10V6K
3/5V_VCC
1
2
3

19

V5DRV

PR339
0_0402_5%
1
2

2
1

LDO

24

V5FILT

BST3A-1 1
PQ48
2 BST3A
2.2_0603_5% PR333
AO4712_SO8

PR338
@ 10K_0402_1%

3/5V_VIN

26

VIN

UG3

8
7
6
5

TP

33

3
2
1

13V_SNB
2

PU16

PR332
4.7_1206_5%

PR335
0_0402_5%

1
2
3

PL28
4.7UH_SIL104R-4R7PF_5.7A_30%
1
2

+3VALWP

PC229
0.1U_0603_25V7K

PQ46
AO4466_SO8
4

VL

@ PR337
61.9K_0402_1%
1
2

8
7
6
5

5
6
7
8

PC226
2200P_0402_50V7K
2
1

PC225
10U_1206_25V6M
2
1

HCB4532KF-800T90_1812
D

PC228
2200P_0402_50V7K
2
1

PC227
10U_1206_25V6M
2
1

PR331
0_0805_5%
1
2

PL26
1

PC233
220U_6.3VM_R15

5uA*267K=10*ILIMTmin*18m*1.3
ILIMTmin=5.705A
5uA*267K=10*ILIMTmax*15m*1.1
ILIMTmax=8.09A
Iocp=6.47A~8.86A

Compal Secret Data

Security Classification
2009/02/04

Issued Date

2010/08/01

Deciphered Date

Title

Compal Electronics, Inc.


3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, December 29, 2009
Date:

Rev
1.0

NEW70 M/B LA-5891P Schematic

Sheet
1

46

of

59

Iada=0~4.74A(90W/19V=4.736A)
Iada=0~3.42A(90W/19V=3.421A)

P2

B+

P3

PQ52 AO4407A_SO8

CHG_B+

B+

PR351 0.02_2512_1%

PQ53 AO4407A_SO8

PJ18

EN

CSON

22

CELLS

CSOP

21

ICOMP

CSIN

20

VCOMP

CSIP

19

ICM

PHASE

18

2 10K_0402_1%

VREF

UGATE

17

DH_CHG

CHLIM

BOOT

16

ACLIM

VDDP

15

LGATE

12

GND

PGND

13

2
1

4
0.02_1206_1%
3

PR376
4.7_0603_5%
PC265
4.7U_0603_6.3V6K

ISL6251AHAZ-T_QSOP24

VMB

<40,41>

PR379
15.4K_0402_1%
1
2

PR380
340K_0402_1%

PR383
10K_0402_1%
1
2

2
PU13B
LM358DT_SO8
7 0

PC267
0.01U_0402_25V7K

PR384
105K_0402_1%

CV mode

37 BATT_OVP

PR382
499K_0402_1%
2

Per cell=4.5V

BATT-OVP=0.1112*VMB

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451

VS

LI-3S :13.5V----BATT-OVP=1.5012V
PC266
0.01U_0402_25V7K

PR381
31.6K_0402_1%

Ki
Vchlim=Iref*(PR374/(PR372+PR374))
=Iref*(100K/(80.6K+100K))
=Iref*0.5537
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)
=(165m/20m)*(1/3.3V)*Iref*0.5537
=1.3842*Iref
Iref=0.7224*Ichanrge =>Ki=0.7224

12600mV

RB751V-40_SOD323-2
1
26251VDD

Normal 3S LI-ON Cells

2N7002W -T/R7_SOT323-3
3

PQ66
2
G

6251VDDP
DL_CHG

CHG

PQ64
AO4466_SO8

BATT+

PR369

PC260
0.1U_0603_25V7K
2 BST_CHGA 2
1
PD13

VADJ

14

<40,41>

TCR=50ppm / C
PL29
10UH_PCMB104T-100MS_6A_20%
1
2

11

2 PACIN
2N7002W
-T/R7_SOT323-3
G
S

3
2
1

10

PQ61D

6251ACLIM
20K_0402_1%
PR378

12.1K_0402_1%

6251VREF 1

37 CALIBRATE#

Charging Voltage
(0x15)

PR373
0_0603_5%
BST_CHG 1

PQ62
AO4466_SO8

PR375

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.502V, Iinput=4.07A

BATT Type

CSOP

5
6
7
8

0.1U_0402_16V7K

37 65W/90W#

CC=0.6~4.48A
Iref=0.7224*Ichanrge
kI=0.7224
IREF=0.43V~3.24V

CSON

PR374
100K_0402_1%

6251VREF

PC259
1
2

IREF

ADP_I

PR368
100_0402_1%
1
2

2
PC258
@ 100P_0402_50V8J

PR372
80.6K_0402_1%
2
1

PR363
20_0402_5%
1
2
PC254
0.047U_0402_16V7K
1
2
PR364
20_0402_5%
2
1
PR365
PC257
20_0402_5%
0.1U_0603_25V7K
1
2
PR367
2_0402_5%
LX_CHG

PC264
10U_1206_25V6M
2
1

PC263
10U_1206_25V6M
2
1

23

ACSET ACPRN

VIN

PD12

PR370
4.7_1206_5%

DCIN

ACOFF

1SS355_SOD323-2
PR357
200K_0402_1%
1
2

1SS355_SOD323-2

3
2
1

24

PD9
1

5
6
7
8

DCIN

VIN

PC262
680P_0402_50V7K

3
VDD

wrong Value
PC252
0.1U_0603_25V7K
2
1

1 PR366

6800P_0402_25V7K
2

PR377
2.55K_0402_1%

ACOFF

37

ACOFF

37

PR371
22K_0402_5%
1
2

PQ65
PDTC115EU_SOT323

PC256
0.01U_0402_25V7K

ACON

PACIN

PQ57
PDTC115EU_SOT323

PR352
47K_0402_1%
1
2

1 1

1
2
1

PC250
2.2U_0603_6.3V6K
2
1
6251_EN

PC255
1

2
1
PC261
0.01U_0402_25V7K
2
1

PACIN

D
2N7002W -T/R7_SOT323-3

3
ACON

37,48

PU17

SUSP# 37,39,43,49

BAS40CW _SOT323-3

3S/4S#

SUSP#

100K_0402_1%

37

PQ63
2
G

44,48

2 1

8
7
6
5

PR356
10K_0402_1%

FSTCHG

2
1

PQ60
PDTC115EU_SOT323

48

PR358
2

D
2N7002W -T/R7_SOT323-3

PQ59
2
G

PR361
150K_0402_1%

1
2
PC251
0.1U_0402_16V7K

PR360 47K_0402_5%
2

100K_0402_1%

FSTCHG

6251VDD

PR362
2

37

PQ55
PDTC115EU_SOT323
PD10

PR359
10K_0402_5%
2
1

FSTCHG

DCIN

PD11 1SS355_SOD323-2
6251VDD
1
2

47K

PQ58
PDTC115EU_SOT323

P3

PR355
100K_0402_1%
2
1

1
1
2
3

PC249
0.1U_0603_25V7K
2

PR354
200K_0402_1%

PQ54 TP0610K-T1-E3_SOT23-3

PQ56
PDTA144EU_SOT323-3

47K
2

CSIP

PC248
5600P_0402_25V7K
1
2

4
1
PR353
47K_0402_1%

CSIN

JUMP_43X118

1
2
3

PC253
0.1U_0603_25V7K
2
1

PC247
2200P_0402_25V7K
2
1

PC246
0.1U_0603_25V7K
2
1

8
7
6
5

PC245
10U_1206_25V6M
2
1

1
2
3

1
2
3

8
7
6
5

PC244
10U_1206_25V6M
2
1

VIN

CP = 85%*Iada ; CP = 4.07A
CP = 85%*Iada ; CP = 2.91A

ADP_I = 19.9*Iadapter*Rsense

PQ51 AO4407A_SO8

12.60V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/09/20

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHARGER
Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009


D

Sheet

47

of

59

B+

PR385
2.2M_0402_5%
1

PR386
1K_1206_5%
1
2

PR393

PR396
100K_0402_5%

1
2

PQ68
PDTC115EU_SOT323
PR398
47K_0402_5%
2
2
1
2N7002W
-T/R7_SOT323-3
G

37,47

ACOFF

PQ70
PDTC115EU_SOT323

PACIN 44,47

PQ69D

B+

1 2

PR397
34K_0402_1%
2
1

PRG++ 2

PR395
499K_0402_1%

PC270
0.01U_0402_25V7K

1
PR394
191K_0402_1%

2
32.4

PC268
0.1U_0603_25V7K

RTCVREF

PR391
1K_1206_5%
1
2

BAS40CW _SOT323-3

PR390
1K_1206_5%
1
2

PU18B
LM393DG_SO8
5

ACON

PC269
1000P_0402_50V7K

47

PD15

1
LL4148_LL34-2

18,45,46 MAINPWON

TP0610K-T1-E3_SOT23-3
PQ67

PR388
1K_1206_5%
1
2

PD14
2

100K_0402_5%

VS

PR389
100K_0402_1%

VIN

PR387
499K_0402_1%

100K_0402_5%

PR392
1

VL

PQ71
PDTC115EU_SOT323

@ PR399
66.5K_0402_1%

+5VALW

ACIN

Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/08/01

Title

PRECHARGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

48

of

59

PL30
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

+1.8VSP

LX_1.8V

FB

GND

SW

IN

BS

EN/SYNC

10

1
PC279
22U_0805_6.3V6M

PC278
22U_0805_6.3V6M

1.8V_EN

PC281
1

0.01U_0402_16V7K

SW

IN

POK

PC382
680P_0402_50V7K

+5VALW

GND

PR563
4.7_1206_5%

PU20
MP2121DQ-LF-Z_QFN10_3X3

PR407
402K_0402_1%
1
2

PR405
309K_0402_1%

VFB=0.8V

PC283
10U_0805_10V4Z

PR566
0_0402_5%

@ PD16

11

+1.5VS

B340A_SMA2

+1.5V

TP

1
1

PJ20
JUMP_43X39

PU21
6

NC

REFEN

NC

VOUT

NC

GND

+3VALW

PC285
1U_0402_6.3V6K

2007/09/20

Deciphered Date

1
PC288
10U_0805_6.3V6M

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

+0.75VSP
2

PR410
1K_0402_1%

PC286
0.1U_0402_16V7K
2
1

1
D

S PQ72
2N7002W -T/R7_SOT323-3

OP1@ PQ102
2N7002W -T/R7_SOT323-3
SUSP
2
G

2
G

OP1@ PC287
1U_0402_6.3V6K

OP1@ PR409
24.9K_0402_1%
1
2

39,43 SUSP

PC274
0.47U_0603_16V7K

VCNTL

GND

APL5336KAI-TRL SO8

1.8V_EN

VIN

OP2@
PR409
0_0402_5%
2

37,39,43,47 SUSP#

PR408
1K_0402_1%

PC284
4.7U_0603_6.3V6K
PR401
22K_0402_5%
1
2

PJ24
JUMP_43X39

OP1 Short
OP2 Short

1
2

PC282
10U_0805_10V4Z

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8VSP/+0.75VSP
Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

49

of

59

PL31
FBMA-L18-453215-900LMA90T_1812

RT8209BGQW _W QFN14_3P5X3P5

2
2

2
PC295
4.7U_0805_10V6K

PC293
330U_6.3V_M

PC294
680P_0603_50V7K

Rds=4.5m(Typ)
5.6m(Max)

VFB=0.75V

VFB=0.75V
Vo=VFB*(1+PR418/PR419)=1.52V
Freq=282KHz(min) , 300KHz(typ)

PR418
5.9K_0402_1%
1
2

PR415
4.7_1206_5%

4
1

LG_1.5V

LGATE

PQ74
AO4456_SO8

VDDP

10

+5VALW

+1.5VP

LX_1.5V

11

5
6
7
8

12

CS

3
2
1

14

NC
PGND

PHASE

PL32
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

PC292
1

0.1U_0603_25V7K

@ PC297
47P_0402_50V8J
1
2

PC296
4.7U_0603_6.3V6K

15

6
open-drain PGOOD

GND

FB

UG_1.5V

VDD

UGATE

13

PR417
11K_0402_1%

PR414
0_0603_5%
1
2BST_1.5V-1

BOOT

VOUT

EN/DEM

TON

PR416
100_0603_1%
1
2

+5VALW

3
2
1

BST_1.5V
PU22

1.5V_EN
@ PC291
0.1U_0402_16V7K

@ PR413
47K_0402_5%

PR412
0_0402_5%
1
2

37,43 SYSON

PR411
280K_0402_1%
1
2

B+

PC290
4.7U_0805_25V6-K

PQ73
AO4466_SO8

Because +1.5VSP has 17.74A power budget, it includes


DDR3, VGA chip, VRAM, so must use molding choke.
1

5
6
7
8

EN_PSV
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode
3. HIGH=>Auto_skip mode

PC289
4.7U_0805_25V6-K

51117_1.5V_B+

PR419
5.76K_0402_1%
2

Cesr=15m ohm
Ipeak=15.82A
Iocpmin=18.98A
I=((19-1.5)*(1.5/19))/(L*Freq)=4.899A
1/2I=2.449A
Iocp=18.09A~29.13A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.5VP
Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009


D

Sheet

50

of

59

VGA_CORE
F=1/(75*e-12*44.2)=300K
Ipeak=33A Imax=23.1A Iocp=39.6A
Iocpmin=(5.11K*26uA)/((5.6mohm/2)*1.2)=39.54A
Iocpmin=39.54A

B+_CORE

7138_VCORE

LX_VCORE

1
VGA@ PC165
10U_1206_25V6M

DH_VCORE
VGA@
1
2
PR184 0_0603_5%
BST_VCORE

@ PR182
10K_0402_1%

18 VGA_PWROK

VGA@ PC166
0.1U_0603_25V7K

+5VS

VGA@ PQ38
SI7686DP-T1-E3_SO8
VGA@ PR186
4.7_0603_5%
1
2 7138_VCORE
VGA@ PC167
2.2U_0603_6.3V6K
1
2

VIN

VCC

BOOT

UG

PHASE

PVCC

14

LG

13

PGND

12

ISEN

11

3
2
1
4

VGA@ PR552
0_0402_5%

VGA@ PC169
390U_2.5V_M

ESR=10mohm
VGA@ PC171
680P_0603_50V7K

VGA@ PR553
10_0402_5%
2
1 GCORE_SEN

GCORE_SEN 24

MAD@ PR197
68.1K_0402_1%

Rds=4.5m/5.6mOHM

+3VS

1 1
2
G

VGA@ PC175
4700P_0402_25V7K

@ PR200
10K_0402_5%

2
MAD@ PR198
9.53K_0402_1%

VGA@ PR199
10K_0402_5%
1
2

PAK@ PR198
8.87K_0402_1%

PR195/PC172/PC174 must pop and modify in PVT.

VGA@ PR211
10K_0402_5%

VGA@ PQ76
2N7002W-T/R7_SOT323-3

VGA@ PC174
6800P_0402_25V7K

PAK@ PR197
43.2K_0402_1%

@ PC998
0.01U_0402_25V7K

PR196
36.5K_0402_1%
2
1

VGA@ PR193
4.99K_0402_1%

1
VGA@ PR195
49.9K_0402_1%

VGA@ PC172
22P_0402_50V8J

2
G

23,43,52 VGA_ON#

VGA@ PQ98
2N7002W-T/R7_SOT323-3

VGA@

3
2
1

10

VGA@ PQ78
AO4456_SO8

+VGA_COREP

5
6
7
8

VGA@ PQ75
AO4456_SO8

1 2

VGA@ PR190
5.11K_0402_1%
1
2

VGA@ PR191
4.7_1206_5%

VO

NC
6

VGA@ PC170
0.1U_0402_16V7K

FSET

EN
FB

VGA@ PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

5
6
7
8

VGA@ PR189
10K_0402_1%
1
2

VFB=0.6V

VGA_ON

DL_VCORE

VGA@ PU998
APW7138NITRL_SSOP16

9,43,52 VGA_ON

VGA@ PC168
2.2U_0603_6.3V6K

7138_VCORE

@ PR187
10K_0402_5%

@ PQ79
SI7686DP-T1-E3_SO8

3
2
1

+3VS

PGOOD

GND

15

16

VGA@ PR185
0_0603_5%

3
2
1

VGA@ PC164
10U_1206_25V6M

VGA@ PL13
FBMA-L11-322513-201LMA40T_1210
1
2

B+

MAD@ PR201
31.6K_0402_1%

+3VS

PAK@ PR201
25.5K_0402_1%

+3VS

@ PR555
10K_0402_5%

0.95 V

1.00 V

1.00 V
1.05 V

@ PR204
10K_0402_5%

@ PR558
10K_0402_5%

1.12 V
D
VGA@ PQ100
2N7002W-T/R7_SOT323-3

VGA@ PR559
10K_0402_5%
2 2
1
G

1.05 V

VGA@ PR557
10K_0402_5%

+3VS

VGA@ PC177
4700P_0402_25V7K

GPU_VID1 23

2
G

0.93 V

VGA@ PR556
10K_0402_5%
2 2
1
G

0.90 V

VGA@ PQ99 D
2N7002W-T/R7_SOT323-3

VGA@ PR202
10K_0402_5%
1
2

VGA@ PQ77 D
2N7002W-T/R7_SOT323-3

VGA@ PR210
10K_0402_5%

2
2

Core Voltage Level


PARK XT

GPU_VID1 GPU_VID0

Core Voltage Level


MADISON PRO

GPU_VID0 23

VGA@ PR560
10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2007/12/18

2010/08/01

Deciphered Date

Title

Compal Electronics, Inc.


VGA_COREP/+1.1VSDGPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

51

of

59

PL37
FBMA-L18-453215-900LMA90T_1812

DH_1.05VS_VTT
PR461
BST_1.05VS_VTT
1
2
0_0603_5%

2
4

VO

PR467
4.99K_0402_1%

1
2

2
1
PR470
57.6K_0402_1%

PR469
90.9K_0402_1%

2
1

@ PC999
0.01U_0402_25V7K

PR472
5.11K_0402_1%
1
2

1
+

PC332
680P_0603_50V7K

PC333
390U_2.5V_M

Material Note:
330uF/9 m, number
are 3, Power 1, HW 2

Pin15
+1.05VS_VTTP

@ PR473
10_0402_5%
1
2

VTT_SENSE 7

VFB=0.6V
PR564
0_0402_5%
1
2

+5VS

+1.05VS_VTT
B

PR465
4.7_1206_5%

Rdson=2.3m/3.2m

Layout Note:
Close IC

@ PR471
0_0402_5%
1
2

PC336
6800P_0402_25V7K

1
2

PC334

22P_0402_50V8J

Fsw=1/(PR470*K)=231KHz,
K=75*10^-12
+1.05VSP_VTT
Ipeak=25A
Imax=17.5A
Rsen(PR467)=2.2K
Iocp=31.19A~56.41A
Vref=(Rb/(Rtop+Rbot))*Vo
=>0.6=(6.65/(5.11+6.65))*Vo
Vo=1.061V

+1.05VS_VTTP

1 2

5
1

ISEN

11

10

FB

NC

1
PC331
0.1U_0402_16V7K

FSET

EN

12

PGND

3
2
1

1
2

PC330
2.2U_0603_6.3V6K

DCR=2.7m(Typ)
3.0m(Max)
PL38
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

PU999
APW7138NITRL_SSOP16

@ PR468
10K_0402_5%

13

PC329
2.2U_0603_6.3V6K
DL_1.05VS_VTT

PQ95
TPCA8028-H_SOP-ADVANCE8-5

VS_ON

LG

Layout Note:
Close IC

PQ83
TPCA8028-H_SOP-ADVANCE8-5

39

14

PQ82
SI7686DP-T1-E3_SO8

1
2
6268_VCORE_1.05VS_VTT
4 VCC

PR464
4.7_0603_5%
1
2 6268_VCORE_1.05VS_VTT

BOOT
PVCC

PR463
0_0603_5%

15

16
UG

PHASE

PGOOD

VIN

3
2
1

8
GND
3

PR466
57.6K_0402_1%
1
2

PC328
0.1U_0603_25V7K

+5VS

3
2
1

@ PR462
1K_0402_1%
1
2

LX_1.05VS_VTT

H_VTTPWRGD 5

PGOOD=1V

+3VS

PR459
2K_0402_1%

+5VS

PR458
0_0402_5%
1
2

PR460
2K_0402_1%

1
2

1
2
D

PC327
10U_1206_25V6M

6268_B+

PC326
10U_1206_25V6M

B+

+1.5V

1
1

@ PJ22
JUMP_43X118

1
VGA@ PR528
1.54K_0402_1%

+1.0VSPDGPU
VGA@ PC366
22U_0805_6.3V6M

VGA@
PC365
0.022U_0402_25V7K

VGA@ PU28
APL5913-KAC-TRL_SO8

@ PR562
22K_0402_5%

FB=0.8V

VGA@ PR529
6.04K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

2010/08/01

Deciphered Date

Title

VGA@ PQ101
2N7002W-T/R7_SOT323-3
2
23,43,51 VGA_ON#
G

VGA@ PC369
1U_0402_6.3V6K

FB

VGA@ PC367
4.7U_0603_6.3V6K

EN
POK

3
4

8
7

VOUT
VOUT

VCNTL
VIN
VIN
GND

6
5
9

23,39,43,51 VGA_ON

VGA@ PR530
27K_0402_1%
1
2

PR476
6.65K_0402_1%
VGA@ PC320
1U_0402_6.3V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05VS_VTTP
Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Sheet

Tuesday, December 29, 2009


1

52

of

59

Intel Auburndale CPU(Integrate Graphics) Ipeak=22A Imax=15A


OCP calculation : Assume DCR=1.1m ohm
G1=Rn/(Rn+Rsum)=0.617
where Rn=PR277 // (PR274+PH3)=5.875k ohm
Rsum=PR269=3.65k ohm
LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A
where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm
Iocp=OCP Threshold*Rdroop/LL=24.89A

UMA@ PL23
FBMA-L18-453215-900LMA90T_1812
GFX_B+
2
1

UMA@ PC191
0.22U_0402_6.3V6K

GFXVR_IMON

ISUMBST_GFX 1
1

14

3
2
1
15 DH_GFX

2
UMA@ PC199
680P_0603_50V7K

22

UMA@ PC198
2.2U_0603_6.3V6K

Rds=4.5mOHM(typ)
Rds=5.6mOHM(max)

UMA@
PR270
0_0402_5%

UMA@ PC130
330U_X_2VM_R6M

10K +-5% TSM0A103J4302RE 0402

1
2
UMA@ PR277
11K_0402_1%

Layout Note:
Place near Choke

Material Note:
330uF/6 m, number are 3, PW
1, HW 1, 1 of HW is backup

UMA@ PC202
0.1U_0402_16V7K
B

UMA@ PC204
0.01U_0402_16V7K

8
ISUM+

+1.05VS_VTT

2
@ PR284
100_0402_1%
1

UMA@ PC203
0.1U_0402_16V7K
UMA@ PR283
1.69K_0402_1%
UMA@ PR288
82.5_0402_1%
1
2
1
2

GFXVR_VID_0 8
GFXVR_VID_1 8
GFXVR_VID_2 8
GFXVR_VID_3 8
GFXVR_VID_4 8
GFXVR_VID_5 8
GFXVR_VID_6 8
GFXVR_EN 8
GFXVR_DPRSLPVR

UMA@
2
1 PR280
UMA@
2
1 PR281
UMA@
2
1 PR282
UMA@
2
1 PR285
UMA@
2
1 PR286
UMA@
2
1 PR287
UMA@
2
1 PR289
UMA@
2
1 PR290
@ 1 PR291
2
UMA@ PR567
0_0402_5%
2
1

1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

37 GFX_CORE_PWRGD

UMA@ PR274
2.61K_0402_1%
UMA@ PH3
1
2 1
2

+5VALW

@ PR279
10K_0402_1%

UMA@ PR269
3.65K_0805_1%
2

UMA@ PR273
1
2
0_0603_5%

UMA@ PR268
4.7_1206_5%
UMA@
PQ41
AO4456_SO8
2

4
21

1
UMA@ PQ40
AO4456_SO8

19

VID2

5
6
7
8

5
6
7
8
18 DL_GFX

VID1

17

20

+VGFX_COREP

UMA@ PL10
0.45UH_PCMB104T-R45MN_25A_20%
4
1

16 LX_GFX

3
2
1

13

12

11

10

UMA@ PQ39
SI7686DP-T1-E3_SO8

BOOT

IMON

VIN

VDD

RTN

CLK_EN#

UMA@ PC200
150P_0402_50V8J

ISUM

VID0

VID3

UMA@ PR276
8.06K_0402_1%
2
1

PGOOD

VID4

UMA@ PC201
22P_0402_50V8J
1
2

VCCP

23

UMA@ PR275
17.8K_0402_1%
1 2
1

1
+VGFX_COREP

RBIAS

24

147K for CPU


47K for GPU

UMA@ PC196
100P_0402_50V8J

LGATE

VID5

UMA@ PC197
1000P_0402_50V7K
2
1

VSSP

VW

25

UMA@ PR272
825K_0402_1%
1
2 1

PHASE

COMP

28

UMA@ PR271
8.66K_0402_1%
2
1

VID6

UMA@ PC193
0.22U_0603_25V7K

DCR=1.1 mOHM

UGATE
UMA@ PU12
ISL62881HRZ-T_QFN28_4X4

FB

VR_ON

5
UMA@ PR294
2
1
47K_0402_1%

VSEN

DPRSLPVR

26

27

UMA@ PR293
10_0402_1%

ISUM+

AGND

UMA@ PC195
330P_0402_50V7K

29

+VGFX_COREP

UMA@ PR266
0_0603_5%

UMA@ PC194
330P_0402_50V7K

8 VSS_AXG_SENSE
8 VCC_AXG_SENSE

8
5

ISUM+
UMA@ PC192
1000P_0402_50V7K
1
2

UMA@ PR265
22.6K_0402_1%

3
2
1

UMA@ PR292
2
1
10_0402_1%

VSS_AXG_SENSE

UMA@ PC189
1U_0402_6.3V6K

1 1

UMA@ PR263
0_0603_5%

UMA@ PR264
1_0603_5%
2
1

+5VALW

@ PC188
0.1U_0402_25V6

UMA@ PC190
0.22U_0603_25V7K

UMA@ PC126
10U_1206_25V6M
2
1

UMA@ PC125
10U_1206_25V6M
2
1

UMA@ PC187
2200P_0402_50V7K

B+

@ PC205
180P 50V J NPO 0402

ISUM-

2009-1214 common circiut modify.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

GFX_COREP
Size
C
Date:

Document Number

Rev
1.0

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009
1

Sheet

53

of

59

+5VS

HFM_VID

PH0

7 H_DPRSLPVR

PR565
0_0805_5%

H_PSI#
2

CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

HFM_Icc

LL

Icc_Dyn

Icc_TDC

# of PH

Auburndale 45W

1.075

50

1.9m

37

35

29

27

Auburndale 35W

0.975

38

1.9m

Clarksfield SV

0.95

51

1.9m

38

39

Clarksfield XE

0.95

65

TBD

48

TBD

+5VS_3212

+5VS_3212

7
7
7
7
7
7
7

PH1

+CPU_B+

PL39
FBMA-L18-453215-900LMA90T_1812

PR481
10_0603_5%

VR_ON

B+

9
3212_VRTT

10

TTSENSE

11

VARFR

SWFB2

VRTT

SW2

28

3212_DRVH2

3212_DRVH2

PR515
69.8K_0402_1%

3212_SW2

3
2
1

3
2
1
1

PC343
220U_25V_M

1
2

PC341
10U_1206_25V6M

1
2

2
CSREF

3212_CS_PH1

PC359
680P_0603_50V7K
@

PQ92
TPCA8028-H_SOP-ADVANCE8-5

PR522
73.2K_0402_1%
2
1

PR523
165K_0402_1%
1
2

PH6
100K_0402_1%_NCP15WF104F03RC

CSREF

PC363
1200P_0402_50V7K
1
2

PC361
1000P_0402_50V7K

PC362
680P_0402_50V7K
2
1

PR513
10_0402_5%

1
1

2 PR520
1K_0402_1%

+CPU_B+

Place PH1 close to


PHASE 1 inductor on
the same layer

TTSense

PC360
0.01U_0402_50V7K

3
1

3212_DRVL2

VGA@ PQ93
TPCA8028-H_SOP-ADVANCE8-5

PR519
2.05K_0402_1%

Connect to input caps

1 2

PWM3

SWFB3

3212_DRVL2

2.05K

PR517
649K_0402_1%

PL41
0.36UH +-20% ETQP4LR36WFC 24A

PR512
4.7_1206_5%
@

24

OD3

23

22

ILIM
21

3212_CSCOMP

3212_CSCOMP

PR514
80.6K_0402_1%

PR521
0_0402_5%

@ PQ91
TPCA8030-H_SOP-ADV8-5
PC358
0.1U_0603_25V7K
2
1

CSCOMP
20

CSSUM
19

CSREF
18

17

LLINE

RAMP

15

2
1
PR516
162K_0402_1%
1

16

14
1
2

RT

RPM

IREF

3212_VRTT

2
G
S

PC339
10U_1206_25V6M

13

25

PR518
7.32K_0402_1%

BST2

+5VS_3212

PQ94

2
2N7002W-T/R7_SOT323-3

5 H_PROCHOT#

AGND

49

GND

PR511 0_0402_5%
D

PR510
@ 499_0402_1%

3212_DRVH2
PR509
0_0603_5%
2
1

@ PC356
0.1U_0603_25V7K

3
2
1

26

PC355
10U_1206_25V6M

DRVH2

1
1 2
2
1

3212_SW2

27

PQ90
TPCA8030-H_SOP-ADV8-5

3212_CS_PH2

3
2
1

TTSNS

PC342
2200P_0402_50V7K
2
1

5
3
2
1

3212_DRVL2
PR506
100_0402_1%
1
2

29

2
1

12

Avoid high dV/dt

+CPU_B+

30

DRVL2

+3VS
PR508
0_0402_5%

VGA@ PQ89
TPCA8028-H_SOP-ADVANCE8-5

PC350
4.7U_0603_6.3V6K

PGND

1
8
5.11K_0402_1% TRDET

+5VS_3212

PR507
0_0402_5%

COMP

3212_DRVL1

PR503
1.65K_0402_1%
1
2

31

PQ88
TPCA8028-H_SOP-ADVANCE8-5

ADP3212MNR2G_QFN48_7X7

DRVL1

+5VS

FB

32

PC347
680P_0603_50V7K
@

CSREF

PC353
150P_0402_50V8J
PR504
39.2K_0402_1%
1
2 1
2
2
PR505

3212_CS_PH1

PVCC

FBRTN

33

3212_DRVL1

+CPU_CORE

3
F

3212_CS_PH2

12P_0402_50V8J
3212_FB PC352
1

PC351 150P_0402_50V8J
1
2

SWFB1

PR502
100_0402_1%
1
2

3212_FBRTN

CLKEN

PR500
10_0402_5%

PL40
0.36UH +-20% ETQP4LR36WFC 24A
1
4

DCR=1.1m OHM

PC354
10U_1206_25V6M

1
1

PC349
1000P_0402_50V7K

CLK_EN#

5
3212_DRVL1
3212_SW1

34

PR499
4.7_1206_5%
@

3212_DRVH1

PC348
0.068U_0402_16V7K

PR501
5.49K_0402_1%

VCC
SW1

35

3
2
1

37

38
PH1

39
PH0

40

IMON

36

PC346
0.1U_0603_25V7K
2
1

499_0402_1%
1
2

0_0402_5%
1
2
PSI

41

PR490

0_0402_5%
1
2
VID6

42

PR489

0_0402_5%
1
2
VID5

43

PR488

0_0402_5%
1
2
VID4

44

PR487

0_0402_5%
1
2
VID3

45

PR486

0_0402_5%
1
2
VID2

46

PR485

0_0402_5%
1
VID1

47

PR483
48

DRVH1

PR498
0_0603_5%
2
1

4
@ PQ86
TPCA8030-H_SOP-ADV8-5

3212_SW1

AGND

BST1

PWRGD

3212_DRVH1

PGND

3
2
1

IMVP_IMON

EN

IMVP_IMON

PQ87
TPCA8030-H_SOP-ADV8-5

3
2
1

PR496
0_0402_5%

PR491
0_0603_5%
2
1

VGATE

PC344
1U_0603_16V6K

3212_DRVH1

DPRSLP

12,15

VID0

+1.05VS_VTT

CLK_EN#
PR497 0_0402_5%

PU27

PR494

12 CLK_ENABLE#

0_0402_5%
1

1
2
PR493
3K_0402_5%

PR495 0_0402_5%
1

PR482

+3VS
PR492
3K_0402_5%

+3VS

PR484

0_0402_5%
1

PC345
0.1U_0603_25V7K
2
1

37,39

PC364
1U_0603_16V6K

PH7
100K_0402_1%_NCP15WF104F03RC

PR524
2

PR525
@ PR526
100_0402_1%
2
1
VCCSENSE
VSSSENSE

130K_0603_1%
1

3212_CS_PH1
3212_CS_PH2

130K_0603_1%

+CPU_CORE
VCCSENSE

VSSSENSE

PR527 100_0402_1%
@

Compal Secret Data

Security Classification
2009/02/04

Issued Date

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_CORE
Size
C
Date:

Compal Electronics, Inc.


Document Number

Rev
1.0

NEW70 M/B LA-5891P Schematic


Tuesday, December 29, 2009

Sheet

54
1

of

59

Version change list (P.I.R. List)


Item

Page 1 of 3
for PWR

Fixed Issue
For BOM unique.

Reason for change

Rev.

For BOM unique.

0.1

1
For BOM unique.

2
3
4

For UMA Arrandale CPU


commond design.

PG#
46

54

0.1

52

0.1

54

Change PR500 from SD028100A00(S RES 1/16W 10 +-5% 0402)


2009-1021 to DVT
to SD028100A80(S RES 1/16W 10 +-5% 0402)

0.1

47

Chnage PC265 from SE107475M80(S CER CAP 4.7U 6.3V M X5R


0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603)

2009-1021 to DVT

0.1

49

Chnage PC284 from SE107475M80(S CER CAP 4.7U 6.3V M X5R


0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603)

2009-1021 to DVT

CIS link error.

2009-1021 to DVT

BOM unique.

0.1

54

Chnage PC350 from SE107475M80(S CER CAP 4.7U 6.3V M X5R


0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603)

2009-1021 to DVT

BOM unique.(For Madison/Park SKU)

0.1

52

Chnage PC367 from SE107475M80(S CER CAP 4.7U 6.3V M X5R


0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603)

2009-1021 to DVT

BOM unique.

BOM unique.

0.1

46

BOM unique.

BOM unique.

0.1

54

+1.05VS_VTTP Cost down 1 LS MOS.


Because +1.05VS_VTT has voltage drop issue,
HW request, remote sense to close to PCH.

0.2

52

Because we remove a LS MOS, so OCP must adjust.

0.2

52

Change PR467 from SD000004O80(S RES 1/16W 2.2K +-1% 0402)


to SD034499180(S RES 1/16W 4.99K 0402 1%)

2009-1029 to DVT

0.2

49

Delete PU19 SA00001NC00 (S IC APL5913-KAC-TRL SO 8P)

2009-1029 to DVT

+1.05VS_VTTP Cost down 1 LS MOS.


HW request.

Adjust +1.05VS_VTTP OCP.


+1.8VSP2, Using MP2121 for 1.8V
only.
+1.8VSP2, Using MP2121 for 1.8V
only.

No need to
Delete all
No need to
Delete all

+1.8VSP2, Using MP2121 for 1.8V


only.

No need to use LDO for +1.8V.


Delete all PU19 circiut.

+VGA_COREP, efficiency issue.


+VGA_COREP, OVP issue.

19

Change PC225/PC227 from SE153106K80(S CER CAP 10U 25V K


X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R 1206)
Change PC339/PC341 from SE153106K80(S CER CAP 10U
X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R
Change PC354/PC355 from SE153106K80(S CER CAP 10U
X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R
Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP )
Delete PR471 SD028000080(S RES 0 0402 5%)
Delete PR473 from SD034100A80(S RES 10 0402 5%)

25V K
1206)
25V K
1206)

2009-1021 to DVT

2009-1021 to DVT

2009-1029 to DVT

Add PR564 SD028000080(S RES 1/16W 0 0402 5%)

use LDO for +1.8V.


PU19 circiut.
use LDO for +1.8V.
PU19 circiut.

0.2

0.2

49
49

Increase Freq, decrease choke, to improve efficiency.

0.2

51

Becasue if PR199/PR202 pop 0ohm, it will cause OVP


when VID change from 00 to 11)

0.2

51

Delete PR402 SD034150280, PR404 SD034120280.


Delete PC273 SE075103K80

PC275 SE000000I10

2009-1029 to DVT

Delete PC272 SE107475K80, PC271 SE107105M80


Delete PR401 and PR403 SD028220280, PC274 SE026474K80
Change PR196 from SD034442280 to SD034365280.

2009-1029 to DVT
2009-1029 to DVT

Change PL14 from SL200000V00 to SH000005680


Change PR199/PR202 from SD028000080 to SD028100280
(S RES 1/16W 10K 0402 5%)

2009-1029 to DVT

+VGA_COREP, cost issue.

Cost down.

0.2

51

Change PQ75/PQ78 from SB00000GL00(S TR TPCA8028-H 1N SOP)


2009-1029 to DVT
to SB000009F80(S TR AO4456 1N SO8)

+VGA_COREP, satndard design.

+VGA_COREP, satndard design, pop 1HS MOS and 2LS MOS,


so remove one HS MOS PQ79.

0.2

51

Delete PQ79 SB000008L80 (S TR SI7686DP-T1-E3 1N


POWERPAK SO8 )

+GFX_COREP, spike issue.

Because +GFX_COREP has spike voltage issue, add


schottky diode across GFXVR_EN and VS_ON to solve it.

0.2

51

0.2

51

20
21
22
23

Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP)

BOM unique.

18

2009-1021 to DVT

BOM unique.

13

17

Delete PQ89/PQ93 SB00000GL00(S TR TPCA8028-H 1N SOP)

BOM unique.

10

16

2009-1021 to DVT

BOM unique.

15

Add PQ87/PQ90 SB00000HL00(S TR TPCA8030-H 1N SOP).

BOM unique.

BOM unique.(For Madison/Park SKU)

Delete PQ86/PQ91 SB00000HL00(S TR TPCA8030-H 1N SOP).

0.1

14

2009-1021 to DVT

For UMA Arrandale CPU, we just only pop 1 HS MOS


and 1 LS MOS.

12

Phase

54

11

Date

0.1

Modify List
Change PD8 from SC1SS355003(S DIO 1SS355)
to SC100001K00( DIO 1SS355 SOD323 T/R-5K)

For BOM unique.

For VTT Power rail commond design, we pop 1 HS MOS


For VTT Power rail commond design. and 1LS MOS.
CIS link error.

+VGA_COREP, OCP caaculation erroe


issue.

Because VGA_CORE has 2 LS MOS, APW7138 detect LS Rdson,


so when caculate OCP, Rdson must reduce 1/2.

Issued Date

Add PD17 SCS00000Z00 (S SCH DIO RB751V-40 SOD-323 )


Change PR190 from SD034649180 to SD034511180
(S RES 1/16W 5.11K 0402 1%)

2007/09/20

Deciphered Date

2009-1029 to DVT
2009-1029 to DVT

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009-1029 to DVT

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

55

of

59

Rev
1.0

Version change list (P.I.R. List)


Item
D

Page 2 of 3 for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

Phase

CPU choke TOHO quality issue.

Because TOHO has quality issue before, change to


Panasonic choke.

0.2

54

Change PL40/PL41 from SHSH00000F000 S COIL 0.36UH +-20%


to DVT
SF-I104-R36 23A to SH000005680 S COIL 0.36UH +-20%
2009-1029
PCMC104T-R36MN1R17

+VGA_COREP, voltage change.

ATI updated Park output voltage.

0.2

51

Change PR197 from SD034649280 to SD034432280.

2009-1029

+VGA_COREP, voltage change.

ATI updated Park output voltage.

0.2

51

Chnage PR198 from SD034953180 to SD034887180.

2009-1029 to DVT

+VGA_COREP, voltage change.

ATI updated Park output voltage.

0.2

51

CHange PR201 from SD034316280 to SD034255280.

2009-1029 to DVT

0.2

51

Add PR557/PR560 SD028100280( S RES 1/16W 10K 0402 5%)

Because HW request that adjust power sequence,


+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW.

0.2

52

Change PC369 from SE076104K80 to SE000000K80


(S CER CAP 1U 0402 X7R)

Because HW request that adjust power sequence,


+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW.

0.2

52

Change PR530 from SD028150380 to SD034270280


(S RES 1/16W 27K 0402 1%)

2009-1029 to DVT

Because HW request that adjust power sequence,


+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW.

0.2

52

Delete PR562 SD028220280 (S RES 1/16W 22K +-5% 0402)

2009-1029 to DVT

+0.75VSP,adjust power sequence.

Because HW request that adjust power sequence,


we will follow the value which given by HW.

0.2

49

=1.8VSP, voltage too small.

Because +1.8VSP drop in HW side, increase +1.8VSP.

0.2

49

Because GFX_COREP has spike voltage issue, originally


we add a schottcky diode to solve it, but Intel's
0.3
command is that do not add it, because of overdriving,
so delete it now.

53

EMI request to add snubber.

53

1
2

to DVT

3
4
5
6
7
C

When VGA_CORE start up, but VBIOS doesn't ready,


+VGA_COREP, initial state unknow. the VID is unknow, add pull down R.

9
10
+GFX_COREP, spike voltage issue.

11
12

+GFX_COREP, EMI request.

0.3

2009-1029

+1.05VS_VTTP, EMI request.

EMI request to add snubber.

14

+VGA_COREP, EMI request.

EMI request to add snubber.

0.3

52

0.3

51

0.3

50

0.3

47

15

Change PC287 from SE076104K80 to SE000000K80

EMI request to add snubber.

Charger, EMI request.

EMI request to add snubber.

CPU_COREP, transient, load line


modify.

CPU_COREP, transient, load line


modify.

16
17
18

0.3

54

to DVT

2009-1029

to DVT

Change PR405 from SD034316380(S RES 1/16W 316K +-1% 0402)


to DVT
2009-1029
to SD034309380(S RES 1/16W 309K 0402 1%)
Delete PD17 SCS00000Z00( S SCH DIO RB751V-40 SOD-323)

Add PR268 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PR465 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
Add PC332 SE025681K80(S CER CAP 680P 50V K X7R 0603)
Add PR191 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
Add PC171 SE025681K80(S CER CAP 680P 50V K X7R 0603)
Add PR415 SD001470B80(S RES 1/4W 4.7 +-5% 1206)

+1.5VP, EMI request.

to DVT

Change PR409 SD028000080 to SD034249280( 24.9K 0402 1%)

Add PC199 SE025681K80(S CER CAP 680P 50V K X7R 0603)

13

2009-1029

2009-1104 to DVT

2009-1104 to DVT
2009-1104 to DVT

2009-1104 to DVT
B

Add PC294 SE025681K80(S CER CAP 680P 50V K X7R 0603)


Add PR370 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
Add PC262 SE074681K80 (S CER CAP 680P 50V K X7R 0402)

2009-1104 to DVT
2009-1104 to DVT

Change PR524/PR525 from SD014120380 to SD014130380.


Change PR501 from SD034536180 to SD034549180

2009-1104 to DVT

Change PC362 from SE074391K80 to SE074681K80


Change PL40/PL41 from SH000005680 to SH12036BM00.
+VSBP, EMI request.

EMI request to add cap to reduce EMI noise on B+

0.3

45

+1.8VSP BOM error.

Loss +1.8VSP enable circiut.

0.3

49

19
20
21

Because ATI change Park output voltage, we saperate


+VGA_COREP, output voltage change. Park and Madison by PAK@ and MAD@. And Change Madison
X63 BOM.

22

+CPU_COREP, power measure.

0.4

51

Add PC221 SE000005Z80 S CER CAP .22U 25V K X7R 0603.


Add PC222 SE042104K80 S CER CAP .1U 25V K X7R 0603
Add PR401 SD014220280 S RES 1/16W 22K 0402 5%
Add PC274 SE026474K80 S CER CAP 0.47U 16V K X7R 0603

2009-1104 to DVT
2009-1104 to DVT

Change PR197 from SD034432280 to SD034681280.


Chnage PR198 from SD034887180 to SD034953180.

2009-1113 to DVT

Change PR201 SD034255280 to SD034316280.

Because HW want to measure CPU_CORE IC power loss,


Add 0805 R to saperate +5VS.

0.4

Add PR565 SD002000080 S RES 1/8W 0 +-5% 0805

2007/09/20

Deciphered Date

2009-1113 to DVT

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

54

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

56

of

59

Rev
1.0

Version change list (P.I.R. List)


Item

Page 3 of 3 for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

Phase

+CPU_COREP, IMON design change.

Intel release IMON RC time constant new request,


change PC348 to 0.068u to meet spec.

0.4

54

+CPU_COREP, cost issue.

SF000000G80 will cost up, change to SF22004M210.

0.4

54

+3V/+5V cost issue.

Because Nippon cost up thier OS-CON cap, so we change


Nippon cap to Sanyo cap by sourcer request.

0.5

46

+1.05VS_VTTP issue.

+1.05VS_VTTP choke unique to +1.5VP.

0.5

52

0.6

51

0.6

51

Change location PU23 to PU998.

2009-1208 to PVT

0.6

52

Change PU26 from SA00001HT80 S IC ISL6268CAZ-T SSOP 16P


to PU999 SA00002O600 S IC APW7138NITRL SSOP 16P

2009-1208 to PVT

0.6

52

Delete PC335 SE075103K80 S CER CAP .01U 25V K X7R 0402


and change location to PC999.

2009-1208 to PVT

0.6

45

Add PC224 SE000000K80 S CER CAP 1U 6.3V K X5R 0402

2009-1208 to PVT

If add PC224, must change PR330 from 0 to 1K to avoid


SPOK pin fail. that is add a current limit R on SPOK pin. 0.6

45

Chnage PR330 from SD028000080 to SD028100180.

2009-1208 to PVT

49

Change PL30 from SH000006I80 S COIL 2.2UH +-20% PCMC063T


2009-1208 to PVT
-2R2MN 8A to SH000009Q00 S COIL 2.2UH 20% MSCDRI-74A2R2M-E 6.5A

3
4
+VGA_COREP 2nd source issue.

5
6

+VGA_COREP 2nd source issue.

+1.05VS_VTTP 2nd source issue.

+1.05VS_VTTP 2nd source issue.

HDD LED flash issue.

10

HDD LED flash issue.

11

BOM error.

In order to phase in 2nd source of APW7138, must add


Pin6 components to meet ISL6268 reqirement.
In order to phase in 2nd source of APW7138, must add
Pin6 components to meet ISL6268 reqirement.
In order to phase in 2nd source, change ISL6268 to
APW7138.
APW7138 needn't pop PC335.

Change PC348 from SE076103K80 S CER CAP .01U 16V K X7R 0402
2009-1113 to DVT
to SE000003J80 S CER CAP 0.068U 16V K X7R 0402
Change PC343 from SF000000G80 to SF22004M210.

2009-1113 to DVT

Change PC233/PC237 from SF22001M300 S ELE CAP 220U 6.3V M


F60(6.3X5.7) PXC to SF22001M200 S ELE CAP 220U 6.3V M B 2009-1118 to DVT
C6 SVPC ESR15
Change PL38 from SH000008V80 S COIL 1UH +-20% PCMB103E-1R0MS2009-1118 to DVT
20A to SH000009U00 S COIL 1UH +-20% FDUE1040D-1R0M=P3 21.3A
Add PC172 SE071220J80 S CER CAP 22P 50V J NPO 0402
2009-1208 to PVT
Add PC174 SE075682K80 S CER CAP 6800P 25V K X7R 0402
Add PR195 SD034909280 S RES 1/16W 90.9K 0402 1%

HDD LED will flash when plug in adapter, because


+3VS rise a little. HW request add PC224 to solve it.

+1.8VSP choke use wrong material.

0.6

12
13
14
B

15
16
17

18
19
20
A

21

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2010/08/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR)

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
1

57

of

59

Rev
1.0

A --> B Change List

1012:--------------------------Page 29,30 Update F1,F2 symbol to SP04301P120(F_SMD1812P110TF)


Page 36,38 C789,C788,C684 symbol update (have pin define)
Page 31, U3 P/N change from SA00001RM00 to SA00003O900
1102:--------------------------Page 7,8 C97,C675,C134,C136,C251,C268,C541,C667 symbol update from SGA00002380 to SGA00002U00
Page 23. Add C609 0.1u_0402(SE076104K80) R739 24K_0402(SD034240280) fix +3VSDGPU Ramp up issue
Page 17,35 Add 1 more USB trace to 3G/B connector from PCH USB20_P10 & USB20_N10
1103:--------------------------Page 43 R200 change symbol from 22_0402_5% to 22_0603_5%
Page 39 SW1,SW4 BOM structure change to @
Page 36 C789.2 power source +3VS change to +3VALW
1104:--------------------------Page 8, Add C797,C798,C799,C800 0.1u_0402 at between +1.5V&+1.5V_1(Intel suggest)
Page 15,37 U41.F3 modify net from GPIO62 to susclk
Page 37 Add R740(@) close U32.123
1105:--------------------------Page 8 R98 change from 4.7K_0402_5% to 330ohm_0402_5% (Intel feekback VGFX_CORE issue solution)
1109:--------------------------Page 23 Change R717,R718,R720,R509 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2)
Page 24 Change R64 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2)
Page 23 Remove and short R729 (A2VDD)
Page 23 Change C600,C172,C599 BOM structure from VGA@ to @ (+A2VDD)
Page 23 Remove and short L6 (+A2VDDQ)
Page 26 Remove and short R730,R731,R732,R733,R734,R735,R736,R737,R738, (DPB,DPC,DPD power source)
Page 37 Add R508 100K_0402 Pull down to GND(EC E51TXD_P80DATA)(fix Intel WLAN Card reset issue)
RF request:--------------------------Page 35 Add C801 (SE071470J80 47P_0402) and C173(SE000005T80 10U_0603)(+3VS_WWAN)
Page 23 Remove R508 (100_0402) change to C802(@) (12P_0402_50V8J)(SE071120J80) (VGA_CLK_27M)
Page 29 Add two shunt C804,C803 12P_0402_50V8J(SE071120J80)(P31.DDC to HDMI conn)
Page 29 Add two shunt C805,C806 22P_0402_50V8J(SE071220J80)(P29.LCD Conn)
pop R403(47_0402) and C516 (22P_0402)(CLK_PCI_LPC)
pop R163 (10_0402)and C319 (10P_0402) (CLK_BUF_ICH_14M)
EMI request:--------------------------Page 36 POP D26, CM1293-04SO(SC300000O00)
Page 38,40,41 POP D18,D19,D10,D9,D11,D28,D30 PJDLC05C(SCA00001100)
1110:--------------------------Page 38 Add Q53(ACIN_LED#)
1111:--------------------------Page 40 C775,C776,C777,C778 change Symbol from SE093475K80(4.7U_0805) to SE107475M80(4.7U_0603)
Page 38 R341,R343 100_0402_5% change to 680_0402_5%(BLUE LED Bright)
Page 38 R342,R344 300_0402_5% change to 3.9K_0402_5%(Orange LED Bright)
1113:--------------------------Page 8 R98 change from 330_0402_5% to 470_0402_5%(SD028470080)
Page 23 Change back R717,R718,R720,R509 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2)
Page 24 Change back R64 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2)
1116:--------------------------Page 13 U41 change P/N from SA00003N700 to SA00003N7B0
Page 34 T16 change P/N from SP050006C00 to SP050006B00
1117:--------------------------Page 58 Add HW PIR

1211:--------------------------ADD C807,C808 1000P_0402(SE074102K80) LAN EMI


ADD C610 0.1U_0402 Y5V(SE070104Z80) VGFX_CORE EMI
ADD C809 C810 0.1U_0402 Y5V(SE070104Z80) +1.5V EMI
1211B:--------------------------Add U32.36 WLAN_LED# (output)
Add U32.91 3G_LED# (output)
Add U32.85 WWAN_LED# (input)
1214:--------------------------ADD R735 For U24 power source +3VS (POP)
ADD R736 For U24 power source +5VS (@)
1215:--------------------------ADD R737 asmedia CLKADD R738 asmedia CLK+
U24 PN change to SA00000U500 (74AHC1G125GW_SOT353-5)
1216:--------------------------C465 change BOM structure to @(3G 150U)
R41 change BOM structure to @(CRT DET)
Q20 change BOM structure to @(CRT DET)
R343,R341 change to 2.2K_0402_5%(SD028220180) (LED)
R334 change to 249K_0402_1%(SD034249380)
1217:--------------------------R253 2.2K_0402_5% change to @
R252 2.2K_0402_5% change to UMAHD@
R343 change to 2.2K_0402_5%(7080@) 680_0402_5%(90@)
R344 change to 3.9K_0402_5%(7080@) 680_0402_5%(90@)
R341 change to 2.2K_0402_5%(7080@) 680_0402_5%(90@)
R342 change to 3.9K_0402_5%(7080@) 680_0402_5%(90@)
1219:
R382 change to 18K_0402(SD028180280)(Board ID)
R389 ADD 100K_0402_5%(SD028100380) PH +3VALW(Board ID)
1223:
R157 change to R167 10K_0402_5% (GPIO66: L:6L H:8L)
GPIO21 define to Project ID (L:NEW50/70/80/90 H:NEW71/91)

1228:
MB PCB P/N (DA80000H700)change to (DAZ0C900100)
Q5,Q9,Q16,Q19,Q21,Q22,Q26,Q27,Q35,Q40,Q47,Q54 change SB00000AR10 to SB00000D900
DEL D10 (Int. MIC ESD Diode PASS Can remove)
R382 change to 18K_0402_5%(SD028180280 Board ID rev0.3)
DEL R667,R668(SD028000080) USb common mode choke
DEL R167,(SD028100280)(GPIO66 PH 8L,PD 6L) 10K_0402_5%
ADD R157 (SD028100280)(GPIO66 PH 8L,PD 6L) 10K_0402_5%
ADD R389 (SD028100380)(Board ID)100K_0402_5%
ADD L68(SM070001600 12ohm bead) USB common mode choke
Modify U24 Symbol

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

0104:
ADD R350 100K_0402_5%(SD028100380)(3G PH +3VS_WWAN)
0107:
Q5,Q9,Q16,Q19,Q21,Q22,Q26,Q27,Q35,Q40,Q47,Q54 change SB00000D900 to SB00000DH00

1209:--------------------------R679 change BOM structure to @


D13,D15 change BOM structure to @
Change R717,R718,R720,R509 BOM structure from VGA@ to @ (Madison&Park prodution remove JTAG option2)
Change R64 BOM structure from @ to VGA@ (Madison&Park prodution remove JTAG option2)
Add R729 0_0402(SD028000080,@)
Add R730 0_0402(SD028000080,@) LOCAL_DIM for Panel new feature
Add R731 0_0402(SD028000080,@) COLOR_ENG_EN for Panel new feature
Add R732 100K_0402(SD028100380)LOCAL_DIM PD to GND
Add R733 100K_0402(SD028100380)COLOR_ENG_EN PD to GND
Q53 change BOM structure to @
ADD Q54 2N7002DWH_SOT363-6(SB00000AR10) for AC PLUG HDD LED flash issue
DEL U16 for AC PLUG HDD LED flash issue
C97,C134,C136,C251,C541,C268,C675,C667 symbol update from SGA00002U00 to SGA00001Q80
C775,C776,C777,C778 change P/N SE107475M80 to SE107475K80(4.7U_0603_6.3V6K)
Security Classification
Compal Secret Data
R272(100K PU +3VS) change BOM structure to @
2007/09/20
2010/08/01
Issued Date
Deciphered Date
Add U32.85 WWAN_LED# (input)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Add U32.17 MINI1_LED# (input)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ADD R734 PD to GND (fix CPT Panel Flash issue)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5

C --> MP Change List

B --> C Change List

Compal Electronics, Inc.


Title

PIR (HW)
Size Document Number
Custom

Rev
1.0

NEW70 M/B LA-5891P Schematic

Date:

Friday, January 08, 2010

Sheet
1

58

of

59

CRT Option Components

NEW90 LED Option


2 5090@1
R343
680_0402_5%

C607

C592
1

C567
1

2 5090@1
R344
680_0402_5%

DIS@2
DIS@2
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J

2 5090@1
R341
680_0402_5%

C603

2 5090@1
R342
680_0402_5%

DIS@2

C593
1

C569
1

DIS@2

DIS@2
DIS@2
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J

15P_0402_50V8J: SE071150J80
12P_0402_50V8J: SE071120J80

VGA
U34

L47

2
DIS@

1
0_0805_5%

L40

2
DIS@

1
0_0805_5%

L38

2
DIS@

1
0_0805_5%

PARK XT M2 A11: SA00003MC10


PARK@
216-0774007 A11 PARK XT M2

PCH SKU Option

0_0805_5%: SD002000080

2
1
R259
10K_0402_5%
UMAO@

GPIO19

PCB
ZZZ

LA-5891P MB Rev0: DA80000H700


LA-5891P MB Rev1: DA80000H710
LA-5891P MB with Small Board Rev1: DAZ0C900100

LA-5891P REV1 M/B

X76
ZZZ
X761@

X76198BOL01 VRAM 512M SAM NEW70


Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)

X76198BOL01
3

ZZZ
X762@

X76198BOL02 VRAM 512M HYN NEW70


Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

X76198BOL02
ZZZ
X763@

X76198BOL03 VRAM 1G SAM NEW70


Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)

X76198BOL03
ZZZ
X764@

X76198BOL04 VRAM 1G HYN NEW70


Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

X76198BOL04
ZZZ
X765@
4

X76198BOL05

X76198BOL05 VRAM 512M AMD NEW70


AMD :SA00003PF10
(S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

ZZZ
X766@
X76198BOL06

AMD :SA00003PF10
(S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

Compal Electronics, Inc.

Compal Secret Data

Security Classification

X76198BOL06 VRAM 1G AMD NEW70

2008/08/10

Issued Date

Deciphered Date

2010/08/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

Option Component
Size
Document Number
Custom

NEW70 M/B LA-5891P Schematic

Date:

Tuesday, December 29, 2009

Sheet
E

59

of

59

Rev
1.0