VHDL Code For Carry Save Adder

Done By
Atchyuth Sonti

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outcarry:out std_logic). architecture Behavioral of main is signal c0.cin :in std_logic.sum1:std_logic_vector(3 downto 0).ALL. end main.cout: out std_logic). component fulladder is port(a. use IEEE. carry1<=not carry.c1. use IEEE.b(0).b. outsum:out std_logic_vector(3 downto 0).carry0.carry1:std_logic.library IEEE.NUMERIC_STD. b:in std_logic_vector(3 downto 0).c0(0)). end component. carry:in std_logic.STD_LOGIC_1164. entity main is port( a:in std_logic_vector(3 downto 0). . sum. begin carry0<=carry.ALL. signal carry0.sum0.sum0(0). fa01:fulladder port map(a(0).

b(2).fa02:fulladder port map(a(1).c1(1).c1(3)). outsum<=sum1.c0(1).c0(2)).carry1.c1(2). fa11:fulladder port map(a(0). fa04:fulladder port map(a(3).sum1(3).b(3).sum0(3).sum0(1).c1(2)).c0(0). fa12:fulladder port map(a(1). outsum<=sum0.c0(3)).sum1(1). .c1(1)). end Behavioral.b(2).sum0(2). end if. fa13:fulladder port map(a(2). process(carry) begin if(carry='0') then outcarry<=c0(3).c1(0)). else outcarry<=c1(3).sum1(0).b(0).sum1(2). end process.b(1). fa14:fulladder port map(a(3).c0(2).c1(0).c0(1)).b(1).b(3). fa03:fulladder port map(a(2).

-.any Xilinx primitives in this code.all.VComponents. b : in STD_LOGIC. sum : out STD_LOGIC.NUMERIC_STD. --library UNISIM. -.arithmetic functions with Signed or Unsigned values --use IEEE. cout : out STD_LOGIC).Uncomment the following library declaration if using -. entity fulladder is Port ( a : in STD_LOGIC.ALL.STD_LOGIC_1164. cin : in STD_LOGIC. end fulladder.ALL. --use UNISIM. architecture Behavioral of fulladder is . use IEEE.Sub Program For Full Adder library IEEE.Uncomment the following library declaration if instantiating -.

begin sum<= a xor b xor cin. end Behavioral. cout<=(a and b)or(b and cin)or(cin and a). .

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