© 2009 Microchip Technology Inc.

DS40044G
PIC16F627A/628A/648A
Data Sheet
Flash-Based, 8-Bit CMOS
Microcontrollers with nanoWatt Technology
DS40044G-page 2 © 2009 Microchip Technology Inc.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC
32
logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, KEELOQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc. DS40044G-page 3
PIC16F627A/628A/648A
High-Performance RISC CPU:
• Operating speeds from DC – 20 MHz
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• 35 single-word instructions:
- All instructions single cycle except branches
Special Microcontroller Features:
• Internal and external oscillator options:
- Precision internal 4 MHz oscillator factory
calibrated to ±1%
- Low-power internal 48 kHz oscillator
- External Oscillator support for crystals and
resonators
• Power-saving Sleep mode
• Programmable weak pull-ups on PORTB
• Multiplexed Master Clear/Input-pin
• Watchdog Timer with independent oscillator for
reliable operation
• Low-voltage programming
• In-Circuit Serial Programming™ (via two pins)
• Programmable code protection
• Brown-out Reset
• Power-on Reset
• Power-up Timer and Oscillator Start-up Timer
• Wide operating voltage range (2.0-5.5V)
• Industrial and extended temperature range
• High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- 40 year data retention
Low-Power Features:
• Standby Current:
- 100 nA @ 2.0V, typical
• Operating Current:
- 12 μA @ 32 kHz, 2.0V, typical
- 120 μA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 μA @ 2.0V, typical
• Timer1 Oscillator Current:
- 1.2 μA @ 32 kHz, 2.0V, typical
• Dual-speed Internal Oscillator:
- Run-time selectable between 4 MHz and
48 kHz
- 4 μs wake-up from Sleep, 3.0V, typical
Peripheral Features:
• 16 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Selectable internal or external reference
- Comparator outputs are externally accessible
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Timer1: 16-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module:
- 16-bit Capture/Compare
- 10-bit PWM
• Addressable Universal Synchronous/Asynchronous
Receiver/Transmitter USART/SCI
Device
Program
Memory
Data Memory
I/O
CCP
(PWM)
USART Comparators
Timers
8/16-bit
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F627A 1024 224 128 16 1 Y 2 2/1
PIC16F628A 2048 224 128 16 1 Y 2 2/1
PIC16F648A 4096 256 256 16 1 Y 2 2/1
18-pin Flash-Based, 8-Bit CMOS Microcontrollers
with nanoWatt Technology
PIC16F627A/628A/648A
DS40044G-page 4 © 2009 Microchip Technology Inc.
Pin Diagrams
1
9
1
8
1
6
1
5
1
4
1
3
1
2
1
1
1
7
2
0
PDIP, SOIC
SSOP
2
7
A
/
6
2
8
A
/
6
4
8
A
R
A
6
/
O
S
C
2
/
C
L
K
O
U
T
R
A
7
/
O
S
C
1
/
C
L
K
I
N
V
S
S
V
S
S
V
D
D
V
D
D
R
A
1
/
A
N
1
R
A
0
/
A
N
0
R
B
6
/
T
1
O
S
O
/
T
1
C
K
I
/
P
G
C
R
B
7
/
T
1
O
S
I
/
P
G
D
R
B
1
/
R
X
/
D
T
R
B
2
/
T
X
/
C
K
R
B
3
/
C
C
P
1
R
B
4
/
P
G
M
R
B
5
R
A
3
/
A
N
3
/
C
M
P
1
R
A
4
/
T
0
C
K
I
/
C
M
P
2
R
A
5
/
M
C
L
R
/
V
P
P
R
B
0
/
I
N
T
R
A
2
/
A
N
2
/
V
R
E
F
VSS
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
RB0/INT
RA2/AN2/VREF
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VDD
RA1/AN1
RA0/AN0
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
RB4/PGM
RB5
PIC16F627A/628A/648A
N
C
N
C
2
8
2
7
2
6
2
5
2
4
2
3
1
2
3
4
5
6
7
8 9
1
0
1
1
2
2
21
20
19
18
17
16
15
1
4
1
3
1
2
R
A
2
/
A
N
2
/
V
R
E
F
R
A
3
/
A
N
3
/
C
M
P
1
R
A
4
/
T
0
C
K
I
/
C
M
P
2
RA5/MCLR/VPP
VSS
RB0/INT
R
B
1
/
R
X
/
D
T
R
B
2
/
T
X
/
C
K
R
B
3
/
C
C
P
1
R
A
1
/
A
N
1
R
A
0
/
A
N
0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
R
B
5
VDD
R
B
4
/
P
G
M
VSS
N
C
N
C
NC
NC
NC
NC
VDD
PIC16F627A/628A
PIC16F648A
28-Pin QFN
2
3
4
5
6
7
8
9
1 18
17
15
14
13
12
11
10
16

2

3

4

5

6

7

8

9
1
0

1
P
I
C
1
6
F
6
2
7
A
/
6
2
8
A
/
6
4
8
A
© 2009 Microchip Technology Inc. DS40044G-page 5
PIC16F627A/628A/648A
Table of Contents
1.0 General Description ........................................................................................................................................................................ 7
2.0 PIC16F627A/628A/648A Device Varieties...................................................................................................................................... 9
3.0 Architectural Overview.................................................................................................................................................................. 11
4.0 Memory Organization .................................................................................................................................................................... 17
5.0 I/O Ports........................................................................................................................................................................................ 33
6.0 Timer0 Module .............................................................................................................................................................................. 47
7.0 Timer1 Module .............................................................................................................................................................................. 50
8.0 Timer2 Module .............................................................................................................................................................................. 54
9.0 Capture/Compare/PWM (CCP) Module........................................................................................................................................ 57
10.0 Comparator Module .................................................................................................................................................................... 63
11.0 Voltage Reference Module ......................................................................................................................................................... 69
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module......................................................................... 73
13.0 Data EEPROM Memory .............................................................................................................................................................. 91
14.0 Special Features of the CPU ...................................................................................................................................................... 97
15.0 Instruction Set Summary........................................................................................................................................................... 117
16.0 Development Support ............................................................................................................................................................... 131
17.0 Electrical Specifications ............................................................................................................................................................ 135
18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 151
19.0 Packaging Information .............................................................................................................................................................. 163
Appendix A: Data Sheet Revision History......................................................................................................................................... 171
Appendix B: Device Differences ....................................................................................................................................................... 171
Appendix C: Device Migrations......................................................................................................................................................... 172
Appendix D: Migrating from other PIC
®
Devices .............................................................................................................................. 172
The Microchip Web Site .................................................................................................................................................................... 173
Customer Change Notification Service ............................................................................................................................................. 173
Customer Support ............................................................................................................................................................................. 173
Reader Response............................................................................................................................................................................. 174
Product Identification System ........................................................................................................................................................... 179
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PIC16F627A/628A/648A
DS40044G-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 7
PIC16F627A/628A/648A
1.0 GENERAL DESCRIPTION
The PIC16F627A/628A/648A are 18-pin Flash-based
members of the versatile PIC16F627A/628A/648A
family of low-cost, high-performance, CMOS, fully-
static, 8-bit microcontrollers.
All PIC
®
microcontrollers employ an advanced RISC
architecture. The PIC16F627A/628A/648A have
enhanced core features, an eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single-
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available, complemented by a large register
set.
PIC16F627A/628A/648A microcontrollers typically
achieve a 2:1 code compression and a 4:1 speed
improvement over other 8-bit microcontrollers in their
class.
PIC16F627A/628A/648A devices have integrated
features to reduce external components, thus reducing
system cost, enhancing system reliability and reducing
power consumption.
The PIC16F627A/628A/648A has 8 oscillator
configurations. The single-pin RC oscillator provides a
low-cost solution. The LP oscillator minimizes power
consumption, XT is a standard crystal, and INTOSC is
a self-contained precision two-speed internal oscillator.
The HS mode is for High-Speed crystals. The EC mode
is for an external clock source.
The Sleep (Power-down) mode offers power savings.
Users can wake-up the chip from Sleep through several
external interrupts, internal interrupts and Resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
Table 1-1 shows the features of the PIC16F627A/628A/
648A mid-range microcontroller family.
A simplified block diagram of the PIC16F627A/628A/
648A is shown in Figure 3-1.
The PIC16F627A/628A/648A series fits in applications
ranging from battery chargers to low power remote
sensors. The Flash technology makes customizing
application programs (detection levels, pulse genera-
tion, timers, etc.) extremely fast and convenient. The
small footprint packages makes this microcontroller
series ideal for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16F627A/628A/648A
very versatile.
1.1 Development Support
The PIC16F627A/628A/648A family is supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a low cost in-circuit debugger, a low
cost development programmer and a full-featured
programmer. A Third Party “C” compiler support tool is
also available.
TABLE 1-1: PIC16F627A/628A/648A FAMILY OF DEVICES
PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A
Clock Maximum Frequency
of Operation (MHz)
20 20 20 20 20 20
Flash Program
Memory (words)
1024 2048 4096 1024 2048 4096
Memory RAM Data Memory
(bytes)
224 224 256 224 224 256
EEPROM Data
Memory (bytes)
128 128 256 128 128 256
Timer module(s) TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
Comparator(s) 2 2 2 2 2 2
Peripherals Capture/Compare/
PWM modules
1 1 1 1 1 1
Serial Communications USART USART USART USART USART USART
Internal Voltage
Reference
Yes Yes Yes Yes Yes Yes
Interrupt Sources 10 10 10 10 10 10
I/O Pins 16 16 16 16 16 16
Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5 2.0-5.5
Brown-out Reset Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
All PIC
®
family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability.
All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7.
PIC16F627A/628A/648A
DS40044G-page 8 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 9
PIC16F627A/628A/648A
2.0 PIC16F627A/628A/648A
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F627A/628A/648A
Product Identification System, at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1 Flash Devices
Flash devices can be erased and re-programmed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically erasable Flash is
that it can be erased and reprogrammed in-circuit, or by
device programmers, such as Microchip’s PICSTART
®
Plus or PRO MATE
®
II programmers.
2.2 Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard Flash devices, but
with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more
details.
2.3 Serialized Quick-Turnaround-
Production (SQTP
SM
) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
PIC16F627A/628A/648A
DS40044G-page 10 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 11
PIC16F627A/628A/648A
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F627A/628A/648A
family can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC16F627A/628A/648A uses a
Harvard architecture in which program and data are
accessed from separate memories using separate
busses. This improves bandwidth over traditional Von
Neumann architecture where program and data are
fetched from the same memory. Separating program
and data memory further allows instructions to be sized
differently than 8-bit wide data word. Instruction
opcodes are 14-bits wide making it possible to have all
single-word instructions. A 14-bit wide program mem-
ory access bus fetches a 14-bit instruction in a single
cycle. A two-stage pipeline overlaps fetch and execu-
tion of instructions. Consequently, all instructions (35)
execute in a single-cycle (200 ns @ 20 MHz) except for
program branches.
Table 3-1 lists device memory sizes (Flash, Data and
EEPROM).
TABLE 3-1: DEVICE MEMORY LIST
The PIC16F627A/628A/648A can directly or indirectly
address its register files or data memory. All Special
Function Registers (SFR), including the program
counter, are mapped in the data memory. The
PIC16F627A/628A/648A have an orthogonal (symmet-
rical) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ makes programming with the
PIC16F627A/628A/648A simple yet efficient. In
addition, the learning curve is reduced significantly.
The PIC16F627A/628A/648A devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions,
typically one operand is the working register
(Wregister). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the Status Register. The C and DC bits
operate as Borrow and Digit Borrow out bits,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, and
a description of the device pins in Table 3-2.
Two types of data memory are provided on the
PIC16F627A/628A/648A devices. Nonvolatile
EEPROM data memory is provided for long term
storage of data, such as calibration values, look-up
table data, and any other data which may require
periodic updating in the field. These data types are not
lost when power is removed. The other data memory
provided is regular RAM data memory. Regular RAM
data memory is provided for temporary storage of data
during normal operation. Data is lost when power is
removed.
Device
Memory
Flash
Program
RAM
Data
EEPROM
Data
PIC16F627A 1024 x 14 224 x 8 128 x 8
PIC16F628A 2048 x 14 224 x 8 128 x 8
PIC16F648A 4096 x 14 256 x 8 256 x 8
PIC16LF627A 1024 x 14 224 x 8 128 x 8
PIC16LF628A 2048 x 14 224 x 8 128 x 8
PIC16LF648A 4096 x 14 256 x 8 256 x 8
PIC16F627A/628A/648A
DS40044G-page 12 © 2009 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM
Note 1: Higher order bits are from the Status register.
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR Reg
Status Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RB0/INT
8
8
Brown-out
Reset
USART CCP1
Timer0 Timer1 Timer2
RA3/AN3/CMP1
RA2/AN2/VREF
RA1/AN1
RA0/AN0
8
3
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Low-Voltage
Programming
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VREF
Comparator
Data EEPROM
© 2009 Microchip Technology Inc. DS40044G-page 13
PIC16F627A/628A/648A
TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/AN0 RA0 ST CMOS Bidirectional I/O port
AN0 AN — Analog comparator input
RA1/AN1 RA1 ST CMOS Bidirectional I/O port
AN1 AN — Analog comparator input
RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port
AN2 AN — Analog comparator input
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port
AN3 AN — Analog comparator input
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port
T0CKI ST — Timer0 clock input
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port
MCLR ST — Master clear. When configured as MCLR, this
pin is an active low Reset to the device.
Voltage on MCLR/VPP must not exceed VDD
during normal device operation.
VPP — — Programming voltage input
RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port
OSC2 — XTAL Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT — CMOS In RC/INTOSC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1.
RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port
OSC1 XTAL — Oscillator crystal input
CLKIN ST — External clock source input. RC biasing pin.
RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
INT ST — External interrupt
RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
RX ST — USART receive pin
DT ST CMOS Synchronous data I/O
RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
TX — CMOS USART transmit pin
CK ST CMOS Synchronous clock I/O
RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
CCP1 ST CMOS Capture/Compare/PWM I/O
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
PIC16F627A/628A/648A
DS40044G-page 14 © 2009 Microchip Technology Inc.
RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
PGM ST — Low-voltage programming input pin. When
low-voltage programming is enabled, the
interrupt-on-pin change and weak pull-up
resistor are disabled.
RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS
Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
T1OSO — XTAL Timer1 oscillator output
T1CKI ST — Timer1 clock input
PGC ST — ICSP™ programming clock
RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
T1OSI XTAL — Timer1 oscillator input
PGD ST CMOS ICSP data I/O
VSS VSS Power — Ground reference for logic and I/O pins
VDD VDD Power — Positive supply for logic and I/O pins
TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
© 2009 Microchip Technology Inc. DS40044G-page 15
PIC16F627A/628A/648A
3.1 Clocking Scheme/Instruction
Cycle
The clock input (RA7/OSC1/CLKIN pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the Program Counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
CLKOUT
PC PC + 1 PC + 2
Fetch INST (PC)
Execute INST (PC - 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
phase
clock
Note: All instructions are single cycle except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, 3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16F627A/628A/648A
DS40044G-page 16 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 17
PIC16F627A/628A/648A
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16F627A/628A/648A has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC16F627A, 2K x 14 (0000h-07FFh) for the
PIC16F628A and 4K x 14 (0000h-0FFFh) for the
PIC16F648A are physically implemented. Accessing a
location above these boundaries will cause a wrap-
around within the first 1K x 14 space (PIC16F627A),
2K x 14 space (PIC16F628A) or 4K x 14 space
(PIC16F648A). The Reset vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-1).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK
4.2 Data Memory Organization
The data memory (Figure 4-2 and Figure 4-3) is
partitioned into four banks, which contain the General
Purpose Registers (GPRs) and the Special Function
Registers (SFRs). The SFRs are located in the first 32
locations of each bank. There are General Purpose
Registers implemented as static RAM in each bank.
Table 4-1 lists the General Purpose Register available
in each of the four banks.
TABLE 4-1: GENERAL PURPOSE STATIC
RAM REGISTERS
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
Table 4-2 lists how to access the four banks of registers
via the Status register bits RP1 and RP0.
TABLE 4-2: ACCESS TO BANKS OF
REGISTERS
4.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F627A/628A and 256 x 8 in the PIC16F648A.
Each is accessed either directly or indirectly through
the File Select Register (FSR), See Section 4.4
“Indirect Addressing, INDF and FSR Registers”.
PC<12:0>
13
000h
0004
0005
03FFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
07FFh

PIC16F627A,
PIC16F628A and
PIC16F648A
On-chip Program
Memory
PIC16F628A and
PIC16F648A
On-chip Program
Memory
PIC16F648A only
0FFFh
PIC16F627A/628A PIC16F648A
Bank0 20-7Fh 20-7Fh
Bank1 A0h-FF A0h-FF
Bank2 120h-14Fh, 170h-17Fh 120h-17Fh
Bank3 1F0h-1FFh 1F0h-1FFh
Bank RP1 RP0
0 0 0
1 0 1
2 1 0
3 1 1
PIC16F627A/628A/648A
DS40044G-page 18 © 2009 Microchip Technology Inc.
FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
Indirect addr.
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
File
Address
Indirect addr.
(1)
Indirect addr.
(1)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.
(1)
TMR0 OPTION
RCSTA
TXREG
RCREG
CMCON
TXSTA
SPBRG
VRCON
General
Purpose
Register
1EFh
1F0h
accesses
70h-7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
80 Bytes
EEDATA
EEADR
EECON1
EECON2
(1)
General
Purpose
Register
80 Bytes
General
Purpose
Register
48 Bytes
11Fh
120h
14Fh
150h
6Fh
70h
16 Bytes
PORTB TRISB
1Ch
1Dh
1Eh
© 2009 Microchip Technology Inc. DS40044G-page 19
PIC16F627A/628A/648A
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A
Indirect addr.
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
PR2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
File
Address
Indirect addr.
(1)
Indirect addr.
(1)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.
(1)
TMR0 OPTION
RCSTA
TXREG
RCREG
CMCON
TXSTA
SPBRG
VRCON
General
Purpose
Register
1EFh
1F0h
accesses
70h-7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
80 Bytes
EEDATA
EEADR
EECON1
EECON2
(1)
General
Purpose
Register
80 Bytes
11Fh
120h
6Fh
70h
16 Bytes
PORTB TRISB
1Ch
1Dh
1Eh
General
Purpose
Register
80 Bytes
PIC16F627A/628A/648A
DS40044G-page 20 © 2009 Microchip Technology Inc.
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
01h TMR0 Timer0 Module’s Register xxxx xxxx 47
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 33
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 28
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 50
11h TMR2 TMR2 Module’s Register 0000 0000 54
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54
13h — Unimplemented — —
14h — Unimplemented — —
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 57
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 57
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 74
19h TXREG USART Transmit Data Register 0000 0000 79
1Ah RCREG USART Receive Data Register 0000 0000 82
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh — Unimplemented — —
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 63
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
© 2009 Microchip Technology Inc. DS40044G-page 21
PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx 30
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 33
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 27
8Dh — Unimplemented — —
8Eh PCON — — — — OSCF — POR BOR ---- 1-0x 29
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 54
93h — Unimplemented — —
94h — Unimplemented — —
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 73
99h SPBRG Baud Rate Generator Register 0000 0000 75
9Ah EEDATA EEPROM Data Register xxxx xxxx 91
9Bh EEADR EEPROM Address Register xxxx xxxx 92
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 92
9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 92
9Eh — Unimplemented — —
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 69
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
PIC16F627A/628A/648A
DS40044G-page 22 © 2009 Microchip Technology Inc.
TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
101h TMR0
Timer0 Module’s Register xxxx xxxx
47
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
105h — Unimplemented — —
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
10Ch — Unimplemented — —
10Dh — Unimplemented — —
10Eh — Unimplemented — —
10Fh — Unimplemented — —
110h — Unimplemented — —
111h — Unimplemented — —
112h — Unimplemented — —
113h — Unimplemented — —
114h — Unimplemented — —
115h — Unimplemented — —
116h — Unimplemented — —
117h — Unimplemented — —
118h — Unimplemented — —
119h — Unimplemented — —
11Ah — Unimplemented — —
11Bh — Unimplemented — —
11Ch — Unimplemented — —
11Dh — Unimplemented — —
11Eh — Unimplemented — —
11Fh — Unimplemented — —
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
© 2009 Microchip Technology Inc. DS40044G-page 23
PIC16F627A/628A/648A
TABLE 4-6: SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
185h — Unimplemented — —
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
18Ch — Unimplemented — —
18Dh — Unimplemented — —
18Eh — Unimplemented — —
18Fh — Unimplemented — —
190h — Unimplemented — —
191h — Unimplemented — —
192h — Unimplemented — —
193h — Unimplemented — —
194h — Unimplemented — —
195h — Unimplemented — —
196h — Unimplemented — —
197h — Unimplemented — —
198h — Unimplemented — —
199h — Unimplemented — —
19Ah — Unimplemented — —
19Bh — Unimplemented — —
19Ch — Unimplemented — —
19Dh — Unimplemented — —
19Eh — Unimplemented — —
19Fh — Unimplemented — —
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
PIC16F627A/628A/648A
DS40044G-page 24 © 2009 Microchip Technology Inc.
4.2.2.1 Status Register
The Status register, shown in Register 4-1, contains the
arithmetic status of the ALU; the Reset status and the
bank select bits for data memory (SRAM).
The Status register can be the destination for any
instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are non-
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the Status register
as “000uu1uu” (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
any Status bit. For other instructions, not affecting any
Status bits, see the “Instruction Set Summary”.
REGISTER 4-1: STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for Borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 25
PIC16F627A/628A/648A
4.2.2.2 OPTION Register
The Option register is a readable and writable register,
which contains various control bits to configure the
TMR0/WDT prescaler, the external RB0/INT interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1 “Switching
Prescaler Assignment”.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI/CMP2 pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI/CMP2 pin
0 = Increment on low-to-high transition on RA4/T0CKI/CMP2 pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F627A/628A/648A
DS40044G-page 26 © 2009 Microchip Technology Inc.
4.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 “PIE1 Register” and
Section 4.2.2.5 “PIR1 Register” for a description of
the comparator enable and flag bits.

REGISTER 4-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB<7:4> pins changes state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 27
PIC16F627A/628A/648A
4.2.2.4 PIE1 Register
This register contains interrupt enable bits.
REGISTER 4-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 28 © 2009 Microchip Technology Inc.
4.2.2.5 PIR1 Register
This register contains interrupt flag bits.
REGISTER 4-5: PIR1 – PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 29
PIC16F627A/628A/648A
4.2.2.6 PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.

REGISTER 4-6: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent Resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR Status bit is a “don’t
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BOREN bit in the
Configuration Word).
U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-0 R/W-x
— — — — OSCF — POR BOR
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OSCF: INTOSC Oscillator Frequency bit
1 = 4 MHz typical
0 = 48 kHz typical
bit 2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 30 © 2009 Microchip Technology Inc.
4.3 PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 4-4 shows the
two situations for loading the PC. The upper example
in Figure 4-4 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
Figure 4-4 shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-4: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556 “Implementing a Table Read”
(DS00556).
4.3.2 STACK
The PIC16F627A/628A/648A family has an 8-level
deep x 13-bit wide hardware stack (Figure 4-1). The
stack space is not part of either program or data space
and the Stack Pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
4.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no-operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-5.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: INDIRECT ADDRESSING
PC
12 8 7 0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12 11 10 0
11 PCLATH<4:3>
PCH PCL
8 7
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
;yes continue
© 2009 Microchip Technology Inc. DS40044G-page 31
PIC16F627A/628A/648A
FIGURE 4-5: DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A
Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.
RAM
Indirect Addressing Direct Addressing
bank select location select
RP1 RP0 6 0 from opcode IRP FSR Register 7 0
bank select location select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
File
Registers
Status
Register
Status
Register
PIC16F627A/628A/648A
DS40044G-page 32 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 33
PIC16F627A/628A/648A
5.0 I/O PORTS
The PIC16F627A/628A/648A have two ports, PORTA
and PORTB. Some pins for these I/O ports are
multiplexed with alternate functions for the peripheral
features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5
(1)
is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
A ‘1’ in the TRISA register puts the corresponding
output driver in a High-impedance mode. A ‘0’ in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control register) register and the VRCON
(Voltage Reference Control register) register. When
selected as a comparator input, these pins will read
as ‘0’s.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high-impedance output. The user must configure
TRISA<2> bit as an input and use high-impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1: INITIALIZING PORTA
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
Note 1: RA5 shares function with VPP. When VPP
voltage levels are applied to RA5, the
device will enter Programming mode.
2: On Reset, the TRISA register is set to all
inputs. The digital inputs (RA<3:0>) are
disabled and the comparator inputs are
forced to ground to reduce current
consumption.
3: TRISA<6:7> is overridden by oscillator
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
TRISA<6:7> bits are ignored.
CLRF PORTA ;Initialize PORTA by
;setting
;output data latches
MOVLW 0x07 ;Turn comparators off and
MOVWF CMCON ;enable pins for I/O
;functions
BCF STATUS, RP1
BSF STATUS, RP0;Select Bank1
MOVLW 0x1F ;Value used to initialize
;data direction
MOVWF TRISA ;Set RA<4:0> as inputs
;TRISA<5> always
;read as ‘1’.
;TRISA<7:6>
;depend on oscillator
;mode
Data
Bus
Q D
Q CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
I/O Pin
Q D
Q CK
Input Mode
D Q
EN
To Comparator
Schmitt Trigger
Input Buffer
VDD
VSS
TRISA
(CMCON Reg.)
PIC16F627A/628A/648A
DS40044G-page 34 © 2009 Microchip Technology Inc.
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/AN2/VREF PIN
FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN
Data
Bus
Q D
Q CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA2 Pin
Q D
Q CK
Input Mode
D Q
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
VREF
VDD
VSS
TRISA
(CMCON Reg.)
Data
Bus
Q D
Q CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA3 Pin
Q D
Q CK
D Q
EN
To Comparator
Schmitt Trigger
Input Buffer
Input Mode
Comparator Output
Comparator Mode = 110
VDD
VSS
TRISA
(CMCON Reg.)
(CMCON Reg.)
1
0
© 2009 Microchip Technology Inc. DS40044G-page 35
PIC16F627A/628A/648A
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN
FIGURE 5-5: BLOCK DIAGRAM OF THE
RA5/MCLR/VPP PIN
FIGURE 5-6: BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
Data
Bus
Q D
Q CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Vss
RA4 Pin
Q D
Q CK
D Q
EN
TMR0 Clock Input
Schmitt Trigger
Input Buffer
Comparator Output
Comparator Mode = 110
Vss
1
0
(CMCON Reg.)
D Q
EN
HV Detect
MCLR Filter
RA5/MCLR/VPP
MCLR
Program
MCLRE
RD
VSS
Data
Bus
VSS
PORTA
RD
circuit
mode
Schmitt Trigger
Input Buffer
TRISA
(Configuration Bit)
WR
D
CK
Q
Q
PORTA
WR
TRISA
VDD
VSS
CLKOUT(FOSC/4)
FOSC =
101, 111
(2)
Q D
RD
EN
RD PORTA
FOSC =
D
CK
Q
Q
011, 100, 110
(1)
TRISA
From OSC1
OSC
Circuit
Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with
RA6 = CLKOUT.
Schmitt
Trigger
Input Buffer
Data Latch
TRIS Latch
1
0
PIC16F627A/628A/648A
DS40044G-page 36 © 2009 Microchip Technology Inc.
FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
Data Bus
Q D
Q CK
WR PORTA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
RA7/OSC1/CLKIN Pin
Q
D
Q CK
D Q
EN
To Clock Circuits
FOSC = 100, 101
(1)
VDD
VSS
Note 1: INTOSC with CLKOUT and INTOSC with I/O.

Schmitt Trigger
Input Buffer
© 2009 Microchip Technology Inc. DS40044G-page 37
PIC16F627A/628A/648A
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Function
Input
Type
Output
Type
Description
RA0/AN0 RA0 ST CMOS Bidirectional I/O port
AN0 AN — Analog comparator input
RA1/AN1 RA1 ST CMOS Bidirectional I/O port
AN1 AN — Analog comparator input
RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port
AN2 AN — Analog comparator input
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port
AN3 AN — Analog comparator input
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port. Output is open drain type.
T0CKI ST — External clock input for TMR0 or comparator output
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port
MCLR ST — Master clear. When configured as MCLR, this pin is an
active low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation.
VPP HV —
Programming voltage input
RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port
OSC2 — XTAL Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
CLKOUT — CMOS In RC or INTOSC mode. OSC2 pin can output CLKOUT,
which has 1/4 the frequency of OSC1.
RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port
OSC1 XTAL — Oscillator crystal input. Connects to crystal resonator in
Crystal Oscillator mode.
CLKIN ST — External clock source input. RC biasing pin.
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
All Other
Resets
05h PORTA RA7 RA6
RA5
(1)
RA4 RA3 RA2 RA1 RA0 xxxx 0000 qqqu 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition. Shaded cells
are not used for PORTA.
Note 1: MCLRE configuration bit sets RA5 functionality.
PIC16F627A/628A/648A
DS40044G-page 38 © 2009 Microchip Technology Inc.
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. A ‘1’ in
the TRISB register puts the corresponding output driver
in a High-impedance mode. A ‘0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output.
The standard port functions and the alternate port
functions are shown in Table 5-3. Alternate port
functions may override the TRIS setting when enabled.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 μA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (See Application Note
AN552 “Implementing Wake-up on Key Strokes”
(DS00552).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-8: BLOCK DIAGRAM OF
RB0/INT PIN
Note: If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
Data Bus
WR PORTB
WR TRISB
RD PORTB
Data Latch
TRIS Latch
RB0/INT
INT
Q D
CK
EN
Q D
EN
RD TRISB
RBPU
P
VDD
VDD
VSS
Q
Q D
CK Q
Weak Pull-up
Schmitt
TTL
Input
Buffer
Trigger
© 2009 Microchip Technology Inc. DS40044G-page 39
PIC16F627A/628A/648A
FIGURE 5-9: BLOCK DIAGRAM OF
RB1/RX/DT PIN
FIGURE 5-10: BLOCK DIAGRAM OF
RB2/TX/CK PIN
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
1
0
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(1)
Data Bus
SPEN
USART Data Output
USART Receive Input
RBPU
VDD
P
EN
Q D
VDD
VSS
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
RD PORTB
RX/DT
RB1/
TTL
Input
Buffer
Weak
Pull-up
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
1
0
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(1)
Data Bus
SPEN
USART TX/CK Output
USART Slave Clock In
RBPU
VDD
P
EN
Q D
VDD
VSS
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
RD PORTB
TTL
Input
Buffer
RB2/
TX/CK
Weak
Pull-up
PIC16F627A/628A/648A
DS40044G-page 40 © 2009 Microchip Technology Inc.
FIGURE 5-11: BLOCK DIAGRAM OF
RB3/CCP1 PIN
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
0
1
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(2)
Data Bus
CCP1CON
CCP output
CCP In
RBPU
VDD
P
EN
Q D
VDD
VSS
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
RD PORTB
TTL
Input
Buffer
RB3/
CCP1
Weak
Pull-up
© 2009 Microchip Technology Inc. DS40044G-page 41
PIC16F627A/628A/648A
FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
RD PORTB
WR PORTB
WR TRISB
Schmitt
Trigger
PGM input
LVP
Data Bus
RB4/PGM
VDD
weak pull-up
P
From other Q D
EN
Q D
EN
Set RBIF
RB<7:4> pins
TTL
input
buffer
VDD
VSS
Note: The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.
RBPU
Q1
Q3
(Configuration Bit)
PIC16F627A/628A/648A
DS40044G-page 42 © 2009 Microchip Technology Inc.
FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
Data Bus
WR PORTB
WR TRISB
RD PORTB
Data Latch
TRIS Latch
RB5 pin
TTL
input
buffer
RD TRISB
RBPU
P
VDD
weak
pull-up
From other Q D
EN
Q D
EN
Set RBIF
RB<7:4> pins
VDD
VSS
Q D
Q CK
Q D
Q CK
Q1
Q3
© 2009 Microchip Technology Inc. DS40044G-page 43
PIC16F627A/628A/648A
FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
RD PORTB
WR PORTB
WR TRISB
Schmitt
Trigger
T1OSCEN
Data Bus
RB6/
TMR1 Clock
RBPU
VDD
weak pull-up P
From RB7
T1OSO/
T1CKI/
PGC
From other Q D
EN
Set RBIF
RB<7:4> pins
Serial Programming Clock
TTL
input
buffer
TMR1 oscillator
Q D
EN
VDD
VSS
Q3
Q1
pin
PIC16F627A/628A/648A
DS40044G-page 44 © 2009 Microchip Technology Inc.
FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN
Data Latch
TRIS Latch
RD TRISB
Q D
Q CK
Q D
Q CK
RD PORTB
WR PORTB
WR TRISB
T10SCEN
Data Bus
RB7/T1OSI/
To RB6
RBPU
VDD
weak pull-up
P
PGD pin
TTL
input
buffer
From other Q D
EN
Q D
EN
Set RBIF
RB<7:4> pins
Serial Programming Input
Schmitt
Trigger
TMR1 oscillator
VDD
VSS
Q3
Q1
© 2009 Microchip Technology Inc. DS40044G-page 45
PIC16F627A/628A/648A
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Function Input Type
Output
Type
Description
RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
INT ST — External interrupt
RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
RX ST — USART Receive Pin
DT ST CMOS Synchronous data I/O
RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port
TX — CMOS USART Transmit Pin
CK ST CMOS Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
CCP1 ST CMOS Capture/Compare/PWM/I/O
RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM ST — Low-voltage programming input pin. When low-voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T1OSO/T1CKI/
PGC
RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSO — XTAL Timer1 Oscillator Output
T1CKI ST — Timer1 Clock Input
PGC ST — ICSP

Programming Clock
RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSI XTAL — Timer1 Oscillator Input
PGD ST CMOS ICSP Data I/O
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
All Other
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4
(1)
RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: u = unchanged, x = unknown. Shaded cells are not used for PORTB.
Note 1: LVP configuration bit sets RB4 functionality.
PIC16F627A/628A/648A
DS40044G-page 46 © 2009 Microchip Technology Inc.
5.3 I/O Programming Considerations
5.3.1 BIDIRECTIONAL I/O PORTS
Any instruction that writes operates internally as a read
followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit 5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit 5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit 0) and is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the Input mode, no problem occurs. However,
if bit 0 is switched into Output mode later on, the
content of the data latch may now be unknown.
Reading a port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential read-
modify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-OR”, “wired-
AND”). The resulting high output currents may damage
the chip.
EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.3.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-16). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction, which causes
that file to be read into the CPU, is executed. Other-
wise, the previous state of that pin may be read into
the CPU rather than the new state. When in doubt, it
is better to separate these instructions with a NOP or
another instruction not accessing this I/O port.
FIGURE 5-16: SUCCESSIVE I/O OPERATION
;Initial PORT settings:PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-up and are
;not connected to other circuitry
;
; PORT latchPORT Pins
---------- ----------
BCF STATUS, RP0 ;
BCF PORTB, 7 ;01pp pppp 11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ;10pp pppp 11pp pppp
BCF TRISB, 6 ;10pp pppp 10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(High).
Q1 Q2 Q3 Q4
PC
Instruction
fetched
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC + 1 PC PC + 2 PC + 3
MOVWF PORTB
Write to PORTB
MOVF PORTB, W
Read to PORTB
NOP NOP
TPD
Execute
MOVWF
PORTB
Execute
MOVF
PORTB, W
Port pin
sampled here
Execute
NOP
Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle
to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
© 2009 Microchip Technology Inc. DS40044G-page 47
PIC16F627A/628A/648A
6.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Read/write capabilities
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module. Additional information is available in the “PIC
®
Mid-Range MCU Family Reference Manual” (DS33023).
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the TMR0 register value
will increment every instruction cycle (without
prescaler). If the TMR0 register is written to, the
increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
this mode the TMR0 register value will increment either
on every rising or falling edge of pin RA4/T0CKI/CMP2.
The incrementing edge is determined by the source
edge (T0SE) control bit (OPTION<4>). Clearing the
T0SE bit selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.2 “Using Timer0 with External Clock”.
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 “Timer0 Prescaler” details
the operation of the prescaler.
6.1 Timer0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut
off during Sleep.
6.2 Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1 EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-1). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device. See Table 17-8.
PIC16F627A/628A/648A
DS40044G-page 48 © 2009 Microchip Technology Inc.
6.3 Timer0 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT
T0CKI
T0SE
pin
FOSC/4
SYNC
2
Cycles
TMR0 Reg
8-to-1MUX
Watchdog
Timer
PSA
WDT
Time-out
PS<2:0>
8
.
PSA
WDT Enable bit
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the Option Register.
T0CS
WDT Postscaler/
TMR0 Prescaler
1
0
1
0
1
0
1
0
TMR1 Clock Source
© 2009 Microchip Technology Inc. DS40044G-page 49
PIC16F627A/628A/648A
6.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). Use the instruction sequences
shown in Example 6-1 when changing the prescaler
assignment from Timer0 to WDT, to avoid an
unintended device Reset.
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0 →WDT)
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT →TIMER0)
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
BCF STATUS, RP0 ;Skip if already in
;Bank 0
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;Prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW '00101111’b ;These 3 lines
;(5, 6, 7)
MOVWF OPTION_REG ;are required only
;if desired PS<2:0>
;are
CLRWDT ;000 or 001
MOVLW '00101xxx’b ;Set Postscaler to
MOVWF OPTION_REG ;desired WDT rate
BCF STATUS, RP0 ;Return to Bank 0
CLRWDT ;Clear WDT and
;prescaler
BSF STATUS, RP0
MOVLW b'xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
MOVWF OPTION_REG
BCF STATUS, RP0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
All Other
Resets
01h, 101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h, 181h
OPTION
(2)
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used for Timer0.
Note 1: Option is referred by OPTION_REG in MPLAB
®
IDE Software.
PIC16F627A/628A/648A
DS40044G-page 50 © 2009 Microchip Technology Inc.
7.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The Timer1 Interrupt, if
enabled, is generated on overflow of the TMR1 register
pair which latches the interrupt flag bit TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing the Timer1 interrupt enable bit TMR1IE
(PIE1<0>).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, the TMR1 register pair value
increments every instruction cycle. In Counter mode, it
increments on every rising edge of the external clock
input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 9.0
“Capture/Compare/PWM (CCP) Module”).
Register 7-1 shows the Timer1 control register.
For the PIC16F627A/628A/648A, when the Timer1
oscillator is enabled (T1OSCEN is set), the RB7/
T1OSI/PGD and RB6/T1OSO/T1CKI/PGC pins
become inputs. That is, the TRISB<7:6> value is
ignored.
REGISTER 7-1: T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 51
PIC16F627A/628A/648A
7.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
7.2 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the TMR1 register pair value increments on
every rising edge of clock input on pin RB7/T1OSI/PGD
when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/
PGC when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during Sleep mode, the TMR1
register pair value will not increment even if the
external clock is present, since the synchronization
circuit is shut off. The prescaler however will continue
to increment.
7.2.1 EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
When an external clock input is used for Timer1 in
Synchronized Counter mode, it must meet certain
requirements. The external clock requirement is due to
internal phase clock (TOSC) synchronization. Also,
there is a delay in the actual incrementing of the TMR1
register pair value after synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to Table 17-8 in
the Electrical Specifications Section, timing parameters
45, 46 and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-counter
type prescaler so that the prescaler output is symmetri-
cal. In order for the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T1CKI to have a
period of at least 4 TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement on
T1CKI high and low time is that they do not violate the
minimum pulse width requirements of 10 ns). Refer to
the appropriate electrical specifications in Table 17-8,
parameters 45, 46 and 47.
FIGURE 7-1: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR1ON
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow
TMR1
PIC16F627A/628A/648A
DS40044G-page 52 © 2009 Microchip Technology Inc.
7.3 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up the
processor. However, special precautions in software are
needed to read/write the timer (Section 7.3.2 “Reading
and Writing Timer1 in Asynchronous Counter
Mode”).
7.3.1 EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high and low time requirements. Refer
to Table 17-8 in the Electrical Specifications Section,
timing parameters 45, 46 and 47.
7.3.2 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading the TMR1H or TMR1L register, while the timer
is running from an external asynchronous clock, will
produce a valid read (taken care of in hardware).
However, the user should keep in mind that reading the
16-bit timer in two 8-bit values itself poses certain
problems since the timer may overflow between the
reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
EXAMPLE 7-1: READING A 16-BIT FREE-
RUNNING TIMER
Note: In Asynchronous Counter mode, Timer1
cannot be used as a time base for capture
or compare operations.
; All interrupts are disabled
MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
MOVF TMR1H, W ;Read high byte
SUBWF TMPH, W ;Sub 1st read with
;2nd read
BTFSC STATUS,Z ;Is result = 0
GOTO CONTINUE ;Good 16-bit read
;
; TMR1L may have rolled over between the
; read of the high and low bytes. Reading
; the high and low bytes now will read a good
; value.
;
MOVF TMR1H, W ;Read high byte
MOVWF TMPH ;
MOVF TMR1L, W ;Read low byte
MOVWF TMPL ;
; Re-enable the Interrupts (if required)
CONTINUE ;Continue with your
;code
© 2009 Microchip Technology Inc. DS40044G-page 53
PIC16F627A/628A/648A
7.4 Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). It will
continue to run during Sleep. It is primarily intended for
a 32.768 kHz watch crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.5 Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M<3:0> =
1011), this signal will reset Timer1.
Timer1 must be configured for either timer or
Synchronized Counter mode to take advantage of this
feature. If Timer1 is running in Asynchronous Counter
mode, this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPRxH:CCPRxL
register pair effectively becomes the period register for
Timer1.
7.6 Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on
a POR or any other Reset except by the CCP1 special
event triggers (see Section 9.2.4 “Special Event
Trigger”).
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Freq C1 C2
32.768 kHz 15 pF 15 pF
Note: These values are for design guidance only.
Consult Application Note AN826 “Crystal
Oscillator Basics and Crystal Selection for
rfPIC
®
and PIC
®
Devices” (DS00826) for
further information on Crystal/Capacitor
Selection.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
PIC16F627A/628A/648A
DS40044G-page 54 © 2009 Microchip Technology Inc.
8.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
The TMR2 register value increments from 00h until it
matches the PR2 register value and then resets to 00h
on the next increment cycle. The PR2 register is a
readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of Timer2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a Timer2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Register 8-1 shows the Timer2 control register.
8.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
The TMR2 register is not cleared when T2CON is
written.
8.2 TMR2 Output
The TMR2 output (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
Comparator
TMR2
Sets flag
TMR2 Reg
output
Reset
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
to
T2CKPS<1:0>
TOUTPS<3:0>
© 2009 Microchip Technology Inc. DS40044G-page 55
PIC16F627A/628A/648A
REGISTER 8-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)
TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale Value
0001 = 1:2 Postscale Value



1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = 1:1 Prescaler Value
01 = 1:4 Prescaler Value
1x = 1:16 Prescaler Value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
0000 -000 0000 -000
11h TMR2 Timer2 Module’s Register
0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
92h PR2 Timer2 Period Register
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.
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DS40044G-page 56 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 57
PIC16F627A/628A/648A
9.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
master/slave Duty Cycle register. Table 9-1 shows the
timer resources of the CCP module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
Additional information on the CCP module is available
in the “PIC
®
Mid-Range MCU Family Reference Man-
ual” (DS33023).
TABLE 9-1: CCP MODE – TIMER
RESOURCE
REGISTER 9-1: CCP1CON – CCP OPERATION REGISTER (ADDRESS: 17h)
CCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCP1M<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 58 © 2009 Microchip Technology Inc.
9.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1<2>) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
9.1.1 CCP PIN CONFIGURATION
In Capture mode, the RB3/CCP1 pin should be config-
ured as an input by setting the TRISB<3> bit.
FIGURE 9-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
9.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
9.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned
off, or the CCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will not
be cleared, therefore the first capture may be from a
non-zero prescaler. Example 9-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1: CHANGING BETWEEN
CAPTURE PRESCALERS
9.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 9-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
Note: If the RB3/CCP1 is configured as an
output, a write to the port can cause a
capture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RB3/CCP1
Prescaler
³ 1, 4, 16
and
edge detect
pin
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
Q S
R
Output
Logic
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1
TRISB<3>
CCP1CON<3:0>
Mode Select
Output Enable
pin
Note: Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).
© 2009 Microchip Technology Inc. DS40044G-page 59
PIC16F627A/628A/648A
9.2.1 CCP PIN CONFIGURATION
The user must configure the RB3/CCP1 pin as an
output by clearing the TRISB<3> bit.
9.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
9.2.4 SPECIAL EVENT TRIGGER
In this mode (CCP1M<3:0>=1011), an internal hard-
ware trigger is generated, which may be used to initiate
an action. See Register 9-1.
The special event trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and CCPR1H, CCPR1L register
pair. The TMR1H, TMR1L register pair is not reset until
the next rising edge of the TMR1 clock. This allows the
CCPR1 register pair to effectively be a 16-bit program-
mable period register for Timer1. The special event
trigger output also starts an A/D conversion provided
that the A/D module is enabled.
TABLE 9-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to
the default low level. This is not the data
latch.
Note: Removing the match condition by chang-
ing the contents of the CCPR1H, CCPR1L
register pair between the clock edge that
generates the special event trigger and
the clock edge that generates the TMR1
Reset will preclude the Reset from
occuring.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
0000 -000 0000 -000
8Ch PIE1
EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
0000 -000 0000 -000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
PIC16F627A/628A/648A
DS40044G-page 60 © 2009 Microchip Technology Inc.
9.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “Set-
Up for PWM Operation”.
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(frequency = 1/period).
FIGURE 9-4: PWM OUTPUT
9.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
R Q
S
Duty cycle registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISB<3>
RB3/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
Note: The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM period PR2 ( ) 1 + [ ] 4 ⋅ ⋅ = Tosc TMR2 prescale ⋅
value
© 2009 Microchip Technology Inc. DS40044G-page 61
PIC16F627A/628A/648A
9.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:

For an example PWM period and duty cycle
calculation, see the PIC
®
Mid-Range Reference Man-
ual (DS33023).
9.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISB<3> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
(CCPR1L:CCP1CON<5:4>) Tosc TMR2 prescale ⋅ ⋅
value
PWM duty cycle =
Note: If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
Resolution
log
Fosc
FPWM TMR2 Prescaler ×
-------------------------------------------------------------
⎝ ⎠
⎛ ⎞
log(2)
--------------------------------------------------------------------------- bits =
PWM
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.
PIC16F627A/628A/648A
DS40044G-page 62 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 63
PIC16F627A/628A/648A
10.0 COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The on-chip
Voltage Reference (Section 11.0 “Voltage Reference
Module”) can also be an input to the comparators.
The CMCON register, shown in Register 10-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 10-1.
REGISTER 10-1: CMCON – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 01Fh)
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 Output inverted
0 = C2 Output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM<2:0>: = 001
Then:
1 = C1 VIN- connects to RA3
0 = C1 VIN- connects to RA0
When CM<2:0> = 010
Then:
1 = C1 VIN- connects to RA3
C2 VIN- connects to RA2
0 = C1 VIN- connects to RA0
C2 VIN- connects to RA1
bit 2-0 CM<2:0>: Comparator Mode bits
Figure 10-1 shows the comparator modes and CM<2:0> bit settings
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 64 © 2009 Microchip Technology Inc.
10.1 Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 10-1 shows the eight possible
modes. The TRISA register controls the data direction
of the comparator pins for each mode.
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Table 17-2.
FIGURE 10-1: COMPARATOR I/O OPERATING MODES
Note 1: Comparator interrupts should be disabled
during a Comparator mode change,
otherwise a false interrupt may occur.
2: Comparators can have an inverted
output. See Figure 10-1.
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Comparators Reset (POR Default Value)
A
A
CM<2:0> = 000
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Two Independent Comparators
A
A
CM<2:0> = 100
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Two Common Reference Comparators
A
D
CM<2:0> = 011
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Off (Read as ‘0’)
One Independent Comparator
D
D
CM<2:0> = 101
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
C1
VIN-
VIN+
Off (Read as ‘0’)
Comparators Off
D
D
CM<2:0> = 111
C2
VIN-
VIN+
Off (Read as ‘0’)
D
D
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Four Inputs Multiplexed to Two Comparators
A
A
CM<2:0> = 010
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
From VREF
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Two Common Reference Comparators with Outputs
A
D
CM<2:0> = 110
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
Open Drain
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
RA4/T0CKI/CMP2
C1
RA0/AN0
VIN-
VIN+
RA3/AN3/CMP1
Three Inputs Multiplexed to Two Comparators
A
A
CM<2:0> = 001
C2
RA1/AN1
VIN-
VIN+
RA2/AN2/VREF
A
A
CIS = 0
CIS = 1
VSS
VSS
RA0/AN0
RA3/AN3/CMP1
RA1/AN1
RA2/AN2/VREF
Module
C1VOUT
C2VOUT
C1VOUT
C2VOUT
Off (Read as ‘0’)
Off (Read as ‘0’)
C2VOUT
C1VOUT
C2VOUT
C1VOUT
C2VOUT
C1VOUT
C2VOUT
© 2009 Microchip Technology Inc. DS40044G-page 65
PIC16F627A/628A/648A
The code example in Example 10-1 depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 10-1: INITIALIZING
COMPARATOR MODULE
10.2 Comparator Operation
A single comparator is shown in Figure 10-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 10-2 represent
the uncertainty due to input offsets and response time.
See Table 17-2 for Common Mode voltage.
10.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 10-2).
FIGURE 10-2: SINGLE COMPARATOR
10.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
Comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
10.3.2 INTERNAL REFERENCE SIGNAL
The Comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 11.0 “Voltage Reference
Module”, contains a detailed description of the Voltage
Reference module that provides this signal. The
internal reference signal is used when the comparators
are in mode CM<2:0> = 010 (Figure 10-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
10.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the internal
reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Table 17-2, page 142).
FLAG_REG EQU 0X20
CLRF FLAG_REG ;Init flag register
CLRF PORTA ;Init PORTA
MOVF CMCON, W ;Load comparator bits
ANDLW 0xC0 ;Mask comparator bits
IORWF FLAG_REG,F ;Store bits in flag register
MOVLW 0x03 ;Init comparator mode
MOVWF CMCON ;CM<2:0> = 011
BSF STATUS,RP0 ;Select Bank1
MOVLW 0x07 ;Initialize data direction
MOVWF TRISA ;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
BCF STATUS,RP0 ;Select Bank 0
CALL DELAY10 ;10Μs delay
MOVF CMCON,F ;Read CMCONto end change
;condition
BCF PIR1,CMIF ;Clear pending interrupts
BSF STATUS,RP0 ;Select Bank 1
BSF PIE1,CMIE ;Enable comparator interrupts
BCF STATUS,RP0 ;Select Bank 0
BSF INTCON,PEIE ;Enable peripheral interrupts
BSF INTCON,GIE ;Global interrupt enable

+
VIN+
VIN-
Result
Result
VIN-
VIN+
PIC16F627A/628A/648A
DS40044G-page 66 © 2009 Microchip Technology Inc.
10.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110 or 001, multiplexors
in the output path of the RA3 and RA4/T0CK1/CMP2
pins will switch and the output of each pin will be the
unsynchronized output of the comparator. The
uncertainty of each of the comparators is related to the
input offset voltage and the response time given in the
specifications. Figure 10-3 shows the comparator output
block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3/AN3/CMP1 and RA4/T0CK1/
CMP2 pins while in this mode.
FIGURE 10-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
D Q
EN
To RA3/AN3/CMP1 or
Set CMIF bit D Q
EN
CL
Reset
From other Comparator
To Data Bus
CnVOUT
CnINV
Q1
RD CMCON
CMCON<7:6>
Q3
RA4/T0CK1/CMP2 pin
© 2009 Microchip Technology Inc. DS40044G-page 67
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10.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any write or read of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
10.7 Comparator Operation During
Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered-up, higher Sleep
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in Sleep mode, turn off the
comparators, CM<2:0> = 111, before entering Sleep. If
the device wakes up from Sleep, the contents of the
CMCON register are not affected.
10.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state. This forces the Comparator module to be in the
comparator Reset mode, CM<2:0> = 000. This ensures
that all potential inputs are analog inputs. Device current
is minimized when analog inputs are present at Reset
time. The comparators will be powered-down during the
Reset interval.
10.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 10-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
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DS40044G-page 68 © 2009 Microchip Technology Inc.
FIGURE 10-4: ANALOG INPUT MODE
TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
All Other
Resets
1Fh CMCON C2OUT C1OUT C2INV C1NV CIS CM2 CM1 CM0 0000 0000 0000 0000
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’
VA
RS < 10 K
AIN
CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the Pin
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
© 2009 Microchip Technology Inc. DS40044G-page 69
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11.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference module consists of a 16-tap
resistor ladder network that provides a selectable volt-
age reference. The resistor ladder is segmented to pro-
vide two ranges of VREF values and has a power-down
function to conserve power when the reference is not
being used. The VRCON register controls the opera-
tion of the reference as shown in Figure 11-1. The
block diagram is given in Figure 11-1.
11.1 Voltage Reference Configuration
The Voltage Reference module can output 16 distinct
voltage levels for each range.
The equations used to calculate the output of the
Voltage Reference module are as follows:
if VRR = 1:
if VRR = 0:
The setting time of the Voltage Reference module must
be considered when changing the VREF output
(Table 17-3). Example 11-1 demonstrates how voltage
reference is configured for an output voltage of 1.25V
with VDD = 5.0V.
REGISTER 11-1: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Fh)
VREF
VR<3:0>
24
----------------------- VDD × =
VREF VDD
1
4
--- ×
⎝ ⎠
⎛ ⎞
VR<3:0>
32
----------------------- + VDD × =
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR — VR3 VR2 VR1 VR0
bit 7 bit 0
bit 7 VREN: VREF Enable bit
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6 VROE: VREF Output Enable bit
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5 VRR: VREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0’
bit 3-0 VR<3:0>: VREF Value Selection bits 0 ≤ VR <3:0> ≤ 15
When VRR = 1: VREF = (VR<3:0>/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 70 © 2009 Microchip Technology Inc.
FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM
EXAMPLE 11-1: VOLTAGE REFERENCE
CONFIGURATION
11.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 11-1) keep VREF from approaching VSS or VDD.
The Voltage Reference module is VDD derived and
therefore, the VREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Voltage Ref-
erence module can be found in Table 17-3.
11.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time out, the contents of
the VRCON register are not affected. To minimize
current consumption in Sleep mode, the Voltage
Reference module should be disabled.
11.4 Effects of a Reset
A device Reset disables the Voltage Reference module
by clearing bit VREN (VRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
11.5 Connection Considerations
The Voltage Reference module operates independently
of the Comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and the VROE bit, VRCON<6>, is
set. Enabling the Voltage Reference module output onto
the RA2 pin with an input signal present will increase
current consumption. Connecting RA2 as a digital output
with VREF enabled will also increase current consump-
tion.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference module output for external connec-
tions to VREF. Figure 11-2 shows an example buffering
technique.
Note: R is defined in Table 17-3.
VRR 8R
VR3
VR0
(From VRCON<3:0>) 16-1 Analog Mux
8R R R R R
VREN
VREF
16 Stages VDD
VSS VSS
MOVLW 0x02 ;4 Inputs Muxed
MOVWF CMCON ;to 2 comps.
BSF STATUS,RP0 ;go to Bank 1
MOVLW 0x07 ;RA3-RA0 are
MOVWF TRISA ;outputs
MOVLW 0xA6 ;enable VREF
MOVWF VRCON ;low range set VR<3:0>=6
BCF STATUS,RP0 ;go to Bank 0
CALL DELAY10 ;10μs delay
© 2009 Microchip Technology Inc. DS40044G-page 71
PIC16F627A/628A/648A
FIGURE 11-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value On
POR
Value On
All Other
Resets
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: - = Unimplemented, read as ‘0’.
Note 1: R is dependent upon the voltage reference configuration VRCON<3:0> and VRCON<5>.
VREF
Module
R
(1)
Voltage
Reference
Output
Impedance
RA2
VREF Output
+
Op Amp
PIC16F627A/628A/648A
DS40044G-page 72 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 73
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12.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) is also known as a Serial
Communications Interface (SCI). The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be
set in order to configure pins RB2/TX/CK and RB1/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
Register 12-1 shows the Transmit Status and Control
Register (TXSTA) and Register 12-2 shows the
Receive Status and Control Register (RCSTA).
REGISTER 12-1: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be parity bit.
Note 1: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 74 © 2009 Microchip Technology Inc.
REGISTER 12-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2 FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of received data (Can be parity bit)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 75
PIC16F627A/628A/648A
12.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit baud rate generator. The SPBRG register
controls the period of a free running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 12-1 shows the formula for
computation of the baud rate for different USART
modes, which only apply in Master mode (internal
clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
EQUATION 12-1: CALCULATING BAUD
RATE ERROR
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared) and ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 12-1: BAUD RATE FORMULA
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Desired Baud Rate
Fosc
64 x 1 + ( )
----------------------- =
9600
16000000
64 x 1 + ( )
------------------------ =
x 25.042 =
Calculated Baud Rate
16000000
64 25 1 + ( )
--------------------------- 9615 = =
Error
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
----------------------------------------------------------------------------------------------------------- =
=
9615 9600 –
9600
------------------------------ 0.16% =
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1))
1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA
Legend: X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on all
other Resets
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the BRG.
PIC16F627A/628A/648A
DS40044G-page 76 © 2009 Microchip Technology Inc.
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE

BAUD
RATE (K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 NA — — NA — — 9.766 +1.73% 255
19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129
76.8 76.92 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32
96 96.15 +0.16% 51 95.24 -0.79% 41 96.15 +0.16% 25
300 294.1 -1.96 16 307.69 +2.56% 12 312.5 +4.17% 7
500 500 0 9 500 0 7 500 0 4
HIGH 5000 — 0 4000 — 0 2500 — 0
LOW 19.53 — 255 15.625 — 255 9.766 — 255
BAUD
RATE (K)
FOSC = 7.15909 MHz SPBRG
value
(decimal)
5.0688 MHz SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 9.622 +0.23% 185 9.6 0 131 9.615 +0.16% 103
19.2 19.24 +0.23% 92 19.2 0 65 19.231 +0.16% 51
76.8 77.82 +1.32 22 79.2 +3.13% 15 75.923 +0.16% 12
96 94.20 -1.88 18 97.48 +1.54% 12 1000 +4.17% 9
300 298.3 -0.57 5 316.8 5.60% 3 NA


500 NA — — NA

— NA — —
HIGH 1789.8 — 0 1267 — 0 100 — 0
LOW 6.991 — 255 4.950 — 255 3.906 — 255
BAUD
RATE (K)
FOSC = 3.579545 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 NA — — NA — — 0.303 +1.14% 26
1.2 NA — — 1.202 +0.16% 207 1.170 -2.48% 6
2.4 NA — — 2.404 +0.16% 103 NA
— —
9.6 9.622 +0.23% 92 9.615 +0.16% 25 NA — —
19.2 19.04 -0.83% 46 19.24 +0.16% 12 NA — —
76.8 74.57 -2.90% 11 83.34 +8.51% 2 NA —

96 99.43 +3.57% 8 NA
— —
NA


300 298.3 0.57% 2 NA — — NA — —
500 NA

— NA — — NA — —
HIGH 894.9 — 0 250 — 0 8.192 — 0
LOW 3.496 — 255 0.9766 — 255 0.032 — 255
© 2009 Microchip Technology Inc. DS40044G-page 77
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TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD
RATE (K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 NA — — NA — — NA — —
1.2 1.221 +1.73% 255 1.202 +0.16% 207 1.202 +0.16% 129
2.4 2.404 +0.16% 129 2.404 +0.16% 103 2.404 +0.16% 64
9.6 9.469 -1.36% 32 9.615 +0.16% 25 9.766 +1.73% 15
19.2 19.53 +1.73% 15 19.23 +0.16% 12 19.53 +1.73V 7
76.8 78.13 +1.73% 3 83.33 +8.51% 2 78.13 +1.73% 1
96 104.2 +8.51% 2 NA — — NA — —
300 312.5 +4.17% 0 NA — — NA — —
500 NA — — NA — — NA — —
HIGH 312.5 — 0 250 — 0 156.3 — 0
LOW 1.221 — 255 0.977 — 255 0.6104 — 255
BAUD
RATE (K)
FOSC = 7.15909 MHz SPBRG
value
(decimal)
5.0688 MHz SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 NA — — 0.31 +3.13% 255 0.3005 -0.17% 207
1.2 1.203 +0.23% 92 1.2 0 65 1.202 +1.67% 51
2.4 2.380 -0.83% 46 2.4 0 32 2.404 +1.67% 25
9.6 9.322 -2.90% 11 9.9 +3.13% 7 NA — —
19.2 18.64 -2.90% 5 19.8 +3.13% 3 NA — —
76.8 NA — — 79.2 +3.13% 0 NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 111.9 — 0 79.2 — 0 62.500 — 0
LOW 0.437 — 255 0.3094 — 255 3.906 — 255
BAUD
RATE (K)
FOSC = 3.579545 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
0.3 0.301 +0.23% 185 0.300 +0.16% 51 0.256 -14.67% 1
1.2 1.190 -0.83% 46 1.202 +0.16% 12 NA — —
2.4 2.432 +1.32% 22 2.232 -6.99% 6 NA — —
9.6 9.322 -2.90% 5 NA — — NA — —
19.2 18.64 -2.90% 2 NA — — NA — —
76.8 NA — — NA — — NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 55.93 — 0 15.63 — 0 0.512 — 0
LOW 0.2185 — 255 0.0610 — 255 0.0020 — 255
PIC16F627A/628A/648A
DS40044G-page 78 © 2009 Microchip Technology Inc.
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD
RATE (K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
9600 9.615 +0.16% 129 9.615 +0.16% 103 9.615 +0.16% 64
19200 19.230 +0.16% 64 19.230 +0.16% 51 18.939 -1.36% 32
38400 37.878 -1.36% 32 38.461 +0.16% 25 39.062 +1.7% 15
57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10
115200 113.636 -1.36% 10 111.111 -3.55% 8 125 +8.51% 4
250000 250 0 4 250 0 3 NA — —
625000 625 0 1 NA — — 625 0 0
1250000 1250 0 0 NA — — NA — —
BAUD
RATE (K)
FOSC = 7.16 MHz SPBRG
value
(decimal)
5.068 MHz SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
9600 9.520 -0.83% 46 9598.485 0.016% 32 9615.385 0.160% 25
19200 19.454 +1.32% 22 18632.35 -2.956% 16 19230.77 0.160% 12
38400 37.286 -2.90% 11 39593.75 3.109% 7 35714.29 -6.994% 6
57600 55.930 -2.90% 7 52791.67 -8.348% 5 62500 8.507% 3
115200 111.860 -2.90% 3 105583.3 -8.348% 2 125000 8.507% 1
250000 NA — — 316750 26.700% 0 250000 0.000% 0
625000 NA — — NA — — NA — —
1250000 NA — — NA — — NA — —
BAUD
RATE (K)
FOSC = 3.579 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)
KBAUD ERROR KBAUD ERROR KBAUD ERROR
9600 9725.543 1.308% 22 8.928 -6.994% 6 NA NA NA
19200 18640.63 -2.913% 11 20833.3 8.507% 2 NA NA NA
38400 37281.25 -2.913% 5 31250 -18.620% 1 NA NA NA
57600 55921.88 -2.913% 3 62500 +8.507 0 NA NA NA
115200 111243.8 -2.913% 1 NA — — NA NA NA
250000 223687.5 -10.525% 0 NA — — NA NA NA
625000 NA — — NA — — NA NA NA
1250000 NA — — NA — — NA NA NA
© 2009 Microchip Technology Inc. DS40044G-page 79
PIC16F627A/628A/648A
12.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8-bit. A dedicated 8-bit baud rate generator is used to
derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The baud rate generator produces a clock either
x16 or x64 of the bit shift rate, depending on bit BRGH
(TXSTA<2>). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
12.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register (occurs
in one TCY), the TXREG register is empty and flag bit
TXIF (PIR1<4>) is set. This interrupt can be enabled/
disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicated the
status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register.
Status bit TRMT is a read-only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 12-1). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate
transfer to TSR resulting in an empty TXREG. A back-
to-back transfer is thus possible (Figure 12-3). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will reset the
transmitter. As a result the RB2/TX/CK pin will revert to
high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
PIC16F627A/628A/648A
DS40044G-page 80 © 2009 Microchip Technology Inc.
FIGURE 12-1: USART TRANSMIT BLOCK DIAGRAM
Follow these steps when setting up an Asynchronous
Transmission:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
3. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set transmit
bit TX9.
6. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Load data to the TXREG register (starts
transmission).
FIGURE 12-2: ASYNCHRONOUS TRANSMISSION
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator
TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RB2/TX/CK pin
Pin Buffer
and Control
8
² ² ²
Word 1
Stop bit
Word 1
Transmit Shift Reg.
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
© 2009 Microchip Technology Inc. DS40044G-page 81
PIC16F627A/628A/648A
FIGURE 12-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’.
Shaded cells are not used for Asynchronous Transmission.
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RB2/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1 Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
.
Note: This timing diagram shows two consecutive transmissions.
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DS40044G-page 82 © 2009 Microchip Technology Inc.
12.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 12-4.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate or at FOSC.
When Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR register. On the detection of the
Stop bit of the third byte, if the RCREG register is still
full, then overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a Stop bit
is detected as clear. Bit FERR and the 9th receive bit
are buffered the same way as the receive data. Read-
ing the RCREG, will load bits RX9D and FERR with
new values, therefore it is essential for the user to read
the RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 12-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RB1/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR register MSb LSb
RX9D RCREG register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop Start (8) 7 1 0
RX9
• • •
RX9
ADEN
RX9
ADEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
RCREG register RX9D
© 2009 Microchip Technology Inc. DS40044G-page 83
PIC16F627A/628A/648A
FIGURE 12-5: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 12-6: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
FIGURE 12-7: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
Start
bit bit 1 bit 0 bit 8 bit 0 Stop
bit
Start
bit bit 8 Stop
bit
RB1/RX/DT (Pin)
RCV Buffer Reg
RCV Shift Reg
Read RCV
Buffer Reg
RCREG
RCIF
(interrupt flag)
Word 1
RCREG
bit 8 = 0, Data Byte bit 8 = 1, Address Byte

ADEN = 1
(Address Match
Enable)
‘1’ ‘1’
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
Start
bit bit 1 bit 0 bit 8 bit 0 Stop
bit
Start
bit bit 8 Stop
bit
RB1/RX/DT (pin)
RCV Buffer Reg
RCV Shift Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
Word 1
RCREG
bit 8 = 1, Address Byte bit 8 = 0, Data Byte
ADEN = 1
(Address Match
Enable)
‘1’ ‘1’
Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
Start
bit bit 1 bit 0 bit 8 bit 0 Stop
bit
Start
bit bit 8 Stop
bit
RB1/RX/DT (pin)
Reg
RCV Buffer Reg
RCV Shift
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
Word 2
RCREG
bit 8 = 1, Address Byte bit 8 = 0, Data Byte
ADEN
(Address Match
Enable)
Word 1
RCREG
Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.
PIC16F627A/628A/648A
DS40044G-page 84 © 2009 Microchip Technology Inc.
Follow these steps when setting up an Asynchronous
Reception:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
3. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an OERR error occurred, clear the error by
clearing enable bit CREN.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
© 2009 Microchip Technology Inc. DS40044G-page 85
PIC16F627A/628A/648A
12.3 USART Address Detect Function
12.3.1 USART 9-BIT RECEIVER WITH
ADDRESS DETECT
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The
port is now programmed such that when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the
receive interrupt is set if and only if RSR<8> = 1. This
feature can be used in a multiprocessor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a ‘1’
(instead of a ‘0’ for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling
multiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (= 1), all data bytes are
ignored. Following the Stop bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = 1). When ADEN is
disabled (= 0), all data bytes are received and the 9th
bit can be used as the parity bit.
The receive block diagram is shown in Figure 12-4.
Reception is enabled by setting bit CREN
(RCSTA<4>).
12.3.1.1 Setting up 9-bit mode with Address
Detect
Follow these steps when setting up Asynchronous
Reception with Address Detect Enabled:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
3. Enable asynchronous communication by setting
or clearing bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. Set bit RX9 to enable 9-bit reception.
6. Set ADEN to enable address detect.
7. Enable the reception by setting enable bit CREN
or SREN.
8. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
10. If an OERR error occurred, clear the error by
clearing enable bit CREN if it was already set.
11. If the device has been addressed (RSR<8> = 1
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
all other
Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous
reception.
PIC16F627A/628A/648A
DS40044G-page 86 © 2009 Microchip Technology Inc.
12.4 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RB2/TX/CK and RB1/RX/DT I/O pins to
CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
12.4.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and
interrupt bit, TXIF (PIR1<4>) is set. The interrupt can
be enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory so it is not available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 12-8). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 12-9). This is advantageous when slow
baud rates are selected, since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to high-
impedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from high-imped-
ance Receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Follow these steps when setting up a Synchronous
Master Transmission:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate (Section 12.1 “USART Baud Rate
Generator (BRG)”).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set bit TX9.
6. Enable the transmission by setting bit TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start each transmission by loading data to the
TXREG register.
© 2009 Microchip Technology Inc. DS40044G-page 87
PIC16F627A/628A/648A
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 12-8: SYNCHRONOUS TRANSMISSION
FIGURE 12-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on all
other Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
bit 0 bit 1 bit 7
Word 1
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 2 bit 0 bit 1 bit 7 RB1/RX/DT pin
RB2/TX/CK pin
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TRMT
TXEN bit
‘1’
‘1’
Word 2
TRMT bit
Write Word 1
Write Word 2
Note: Sync Master Mode; SPBRG = 0. Continuous transmission of two 8-bit words.
RB1/RX/DT pin
RB2/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
PIC16F627A/628A/648A
DS40044G-page 88 © 2009 Microchip Technology Inc.
12.4.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Follow these steps when setting up a Synchronous
Master Reception:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1 “USART Baud Rate
Generator (BRG)”).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, then set enable bit
RCIE.
6. If 9-bit reception is desired, then set bit RX9.
7. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
8. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an OERR error occurred, clear the error by
clearing bit CREN.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR
Value on all
other Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EPIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 0000 -000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
© 2009 Microchip Technology Inc. DS40044G-page 89
PIC16F627A/628A/648A
FIGURE 12-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
12.5 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.5.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
Follow these steps when setting up a Synchronous
Slave Transmission:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
3. Clear bits CREN and SREN.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set bit TX9.
6. Enable the transmission by setting enable bit
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start transmission by loading data to the TXREG
register.
CREN bit
RB1/RX/DT pin
RB2/TX/CK pin
WRITE to
Bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q2 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Q1Q2Q3Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
PIC16F627A/628A/648A
DS40044G-page 90 © 2009 Microchip Technology Inc.
12.5.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of the Sleep
mode. Also, bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Follow these steps when setting up a Synchronous
Slave Reception:
1. TRISB<1> and TRISB<2> should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. To enable reception, set enable bit CREN.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If an OERR error occurred, clear the error by
clearing bit CREN.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on all
other Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on all
other Resets
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
© 2009 Microchip Technology Inc. DS40044G-page 91
PIC16F627A/628A/648A
13.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers (SFRs). There are four SFRs used to read
and write this memory. These registers are:
• EECON1
• EECON2 (Not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write and EEADR
holds the address of the EEPROM location being
accessed. PIC16F627A/628A devices have 128 bytes
of data EEPROM with an address range from 0h to
7Fh. The PIC16F648A device has 256 bytes of data
EEPROM with an address range from 0h to FFh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip-to-chip. Please refer to AC specifications for
exact limits.
When the device is code-protected, the CPU can
continue to read and write the data EEPROM memory. A
device programmer can no longer access this memory.
Additional information on the data EEPROM is
available in the PIC
®
Mid-Range Reference Manual
(DS33023).
REGISTER 13-1: EEDATA – EEPROM DATA REGISTER (ADDRESS: 9Ah)
REGISTER 13-2: EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
bit 7-0 EEDATn: Byte value to Write to or Read from data EEPROM memory location.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EADR7 EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit 7 bit 0
bit 7 PIC16F627A/628A
Unimplemented Address: Must be set to ‘0’
PIC16F648A
EEADR: Set to ‘1’ specifies top 128 locations (128-255) of EEPROM Read/Write Operation
bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F627A/628A/648A
DS40044G-page 92 © 2009 Microchip Technology Inc.
13.1 EEADR
The PIC16F648A EEADR register addresses 256
bytes of data EEPROM. All eight bits in the register
(EEADR<7:0>) are required.
The PIC16F627A/628A EEADR register addresses
only the first 128 bytes of data EEPROM so only seven
of the eight bits in the register (EEADR<6:0>) are
required. The upper bit is address decoded. This
means that this bit should always be ‘0’ to ensure that
the address is in the 128 byte memory space.
13.2 EECON1 and EECON2 Registers
EECON1 is the control register with four low order bits
physically implemented. The upper-four bits are non-
existent and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit and rewrite the location. The
data and address will be unchanged in the EEDATA
and EEADR registers.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 13-3: EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 9Ch)
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
— — — — WRERR WREN WR RD
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 93
PIC16F627A/628A/648A
13.3 Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1: DATA EEPROM READ
13.4 Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 13-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-3: WRITE VERIFY
13.6 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also
when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
BSF STATUS, RP0 ;Bank 1
MOVLW CONFIG_ADDR ;
MOVWF EEADR ;Address to read
BSF EECON1, RD ;EE Read
MOVF EEDATA, W ;W = EEDATA
BCF STATUS, RP0 ;Bank 0
R
e
q
u
i
r
e
d
S
e
q
u
e
n
c
e
BSF STATUS, RP0 ;Bank 1
BSF EECON1, WREN ;Enable write
BCF INTCON, GIE ;Disable INTs.
BTFSC INTCON,GIE ;See AN576
GOTO $-2
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1,WR ;Set WR bit
;begin write
BSF INTCON, GIE ;Enable INTs.
BSF STATUS, RP0;Bank 1
MOVF EEDATA, W
BSF EECON1, RD ;Read the
;value written
;
;Is the value written (in W reg) and
;read (in EEDATA) the same?
;
SUBWF EEDATA, W ;
BTFSS STATUS, Z ;Is difference 0?
GOTO WRITE_ERR ;NO, Write error
: ;YES, Good write
: ;Continue program
PIC16F627A/628A/648A
DS40044G-page 94 © 2009 Microchip Technology Inc.
13.7 Using the Data EEPROM
The data EEPROM is a high endurance, byte
addressable array that has been optimized for the storage
of frequently changing information (e.g., program
variables or other data that are updated often). When
variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the EEPROM
(specification D124) without exceeding the total number
of write cycles to a single byte (specifications D120 and
D120A). If this is the case, then an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 13-4.
EXAMPLE 13-4: DATA EEPROM REFRESH ROUTINE
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
BANKSEL 0X80 ;select Bank1
CLRF EEADR ;start at address 0
BCF INTCON, GIE ;disable interrupts
BTFSC INTCON, GIE ;see AN576
GOTO $ - 2
BSF EECON1, WREN ;enable EE writes
Loop
BSF EECON1, RD ;retrieve data into EEDATA
MOVLW 0x55 ;first step of ...
MOVWF EECON2 ;... required sequence
MOVLW 0xAA ;second step of ...
MOVWF EECON2 ;... required sequence
BSF EECON1, WR ;start write sequence
BTFSC EECON1, WR ;wait for write complete
GOTO $ - 1
#IFDEF __16F648A ;256 bytes in 16F648A
INCFSZ EEADR, f ;test for end of memory
#ELSE ;128 bytes in 16F627A/628A
INCF EEADR, f ;next address
BTFSS EEADR, 7 ;test for end of memory
#ENDIF ;end of conditional assembly
GOTO Loop ;repeat for all locations
BCF EECON1, WREN ;disable EE writes
BSF INTCON, GIE ;enable interrupts (optional)
© 2009 Microchip Technology Inc. DS40044G-page 95
PIC16F627A/628A/648A
13.8 Data EEPROM Operation During
Code-Protect
When the device is code-protected, the CPU is able to
read and write data to the data EEPROM.
TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on all
other
Resets
9Ah EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu
9Bh EEADR EEPROM Address Register xxxx xxxx uuuu uuuu
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000
9Dh EECON2
(1)
EEPROM Control Register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register.
PIC16F627A/628A/648A
DS40044G-page 96 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 97
PIC16F627A/628A/648A
14.0 SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC16F627A/628A/648A family
has a host of such features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection.
These are:
1. OSC selection
2. Reset
3. Power-on Reset (POR)
4. Power-up Timer (PWRT)
5. Oscillator Start-Up Timer (OST)
6. Brown-out Reset (BOR)
7. Interrupts
8. Watchdog Timer (WDT)
9. Sleep
10. Code protection
11. ID Locations
12. In-Circuit Serial Programming™ (ICSP™)
The PIC16F627A/628A/648A has a Watchdog Timer
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in Reset while the
power supply stabilizes. There is also circuitry to reset
the device if a brown-out occurs. With these three
functions on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
14.1 Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special configuration memory space (2000h-3FFFh),
which can be accessed only during programming. See
“PIC16F627A/628A/648A EEPROM Memory
Programming Specification” (DS41196) for additional
information.
PIC16F627A/628A/648A
DS40044G-page 98 © 2009 Microchip Technology Inc.
REGISTER 14-1: CONFIG – CONFIGURATION WORD REGISTER
CP — — — — CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0
bit 13: CP: Flash Program Memory Code Protection bit
(2)
(PIC16F648A)
1 = Code protection off
0 = 0000h to 0FFFh code-protected
(PIC16F628A)
1 = Code protection off
0 = 0000h to 07FFh code-protected
(PIC16F627A)
1 = Code protection off
0 = 0000h to 03FFh code-protected
bit 12-9: Unimplemented: Read as ‘0’
bit 8: CPD: Data Code Protection bit
(3)
1 = Data memory code protection off
0 = Data memory code-protected
bit 7: LVP: Low-Voltage Programming Enable bit
1 = RB4/PGM pin has PGM function, low-voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6: BOREN: Brown-out Reset Enable bit
(1)
1 = BOR Reset enabled
0 = BOR Reset disabled
bit 5: MCLRE: RA5/MCLR/VPP Pin Function Select bit
1 = RA5/MCLR/VPP pin function is MCLR
0 = RA5/MCLR/VPP pin function is digital Input, MCLR internally tied to VDD
bit 3: PWRTE: Power-up Timer Enable bit
(1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0: FOSC<2:0>: Oscillator Selection bits
(4)
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it does on the
PIC16F627/628 devices.
2: The code protection scheme has changed from the code protection scheme used on the PIC16F627/628 devices. The
entire Flash program memory needs to be bulk erased to set the CP bit, turning the code protection off. See
“PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196) for details.
3: The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See “PIC16F627A/
628A/648A EEPROM Memory Programming Specification” (DS41196) for details.
4: When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown
© 2009 Microchip Technology Inc. DS40044G-page 99
PIC16F627A/628A/648A
14.2 Oscillator Configurations
14.2.1 OSCILLATOR TYPES
The PIC16F627A/628A/648A can be operated in eight
different oscillator options. The user can program three
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC External Resistor/Capacitor (2 modes)
• INTOSC Internal Precision Oscillator (2 modes)
• EC External Clock In
14.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 14-1). The PIC16F627A/628A/648A
oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturers specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1 pin (Figure 14-4).
FIGURE 14-1: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
TABLE 14-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 14-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Note 1: A series resistor may be required for AT strip cut
crystals.
2: See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
C1
(2)
C2
(2)
XTAL
OSC2
RS
(1)

OSC1
RF
Sleep
PIC16F627A/628A/648A
FOSC
Mode Freq OSC1(C1) OSC2(C2)
XT 455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
HS 8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external compo-
nents.
Mode Freq OSC1(C1) OSC2(C2)
LP 32 kHz
200 kHz
15-30 pF
0-15 pF
15-30 pF
0-15 pF
XT 100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
HS 8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
Note: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. A series resistor (RS) may
be required in HS mode, as well as XT
mode, to avoid overdriving crystals with
low drive level specification. Since each
crystal has its own characteristics, the
user should consult the crystal manufac-
turer for appropriate values of external
components.
PIC16F627A/628A/648A
DS40044G-page 100 © 2009 Microchip Technology Inc.
14.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
Figure 14-2 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180° phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The
10 kΩ potentiometers bias the 74AS04 in the linear
region. This could be used for external oscillator
designs.
FIGURE 14-2: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 14-3 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 14-3: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
14.2.4 PRECISION INTERNAL 4 MHZ
OSCILLATOR
The internal precision oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5V and 25°C. See
Section 17.0 “Electrical Specifications”, for informa-
tion on variation over voltage and temperature.
14.2.5 EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the PIC16F627A/
628A/648A provided that this external clock source meets
the AC/DC timing requirements listed in Section 17.6
“Timing Diagrams and Specifications”. Figure 14-4
below shows how an external clock circuit should be
configured.
FIGURE 14-4: EXTERNAL CLOCK INPUT
OPERATION (EC, HS, XT
OR LP OSC
CONFIGURATION)
+5V
10K
4.7K
10K
74AS04
XTAL
10K
74AS04
PIC16F627A/628A/648A
CLKIN
To other
Devices
C1 C2
330 KΩ
74AS04 74AS04
PIC16F627A/
CLKIN
To other
Devices
XTAL
330 KΩ
74AS04
0.1 pF
628A/648A
Clock from
ext. system
PIC16F627A/628A/648A
RA6
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
© 2009 Microchip Technology Inc. DS40044G-page 101
PIC16F627A/628A/648A
14.2.6 RC OSCILLATOR
For applications where precise timing is not a
requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC oscillator
frequency is a function of:
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature
The oscillator frequency will vary from unit-to-unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 14-5 shows how the R/C combination is
connected.
FIGURE 14-5: RC OSCILLATOR MODE
The RC Oscillator mode has two options that control
the unused OSC2 pin. The first allows it to be used as
a general purpose I/O port. The other configures the
pin as an output providing the FOSC signal (internal
clock divided by 4) for test or external synchronization
purposes.
14.2.7 CLKOUT
The PIC16F627A/628A/648A can be configured to
provide a clock out signal by programming the
Configuration Word. The oscillator frequency, divided
by 4 can be used for test purposes or to synchronize
other logic.
14.2.8 SPECIAL FEATURE: DUAL-SPEED
OSCILLATOR MODES
A software programmable dual-speed oscillator mode
is provided when the PIC16F627A/628A/648A is
configured in the INTOSC oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 48 kHz nominal in the INTOSC
mode. Applications that require low-current power
savings, but cannot tolerate putting the part into Sleep,
may use this mode.
There is a time delay associated with the transition
between fast and slow oscillator speeds. This oscillator
speed transition delay consists of two existing clock
pulses and eight new speed clock pulses. During this
clock speed transition delay, the System Clock is halted
causing the processor to be frozen in time. During this
delay, the program counter and the CLKOUT stop.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 4.2.2.6 “PCON
Register”, Register 4-6.
14.3 Reset
The PIC16F627A/628A/648A differentiates between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) WDT Reset (normal operation)
e) WDT wake-up (Sleep)
f) Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset, Brown-out Reset, MCLR
Reset, WDT Reset and MCLR Reset during Sleep.
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 14-4. These bits are
used in software to determine the nature of the Reset.
See Table 14-7 for a full description of Reset states of
all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.
CEXT
VDD
REXT
VSS
PIC16F627A/628A/648A
FOSC/4
Internal
Clock
CLKIN
RA7/OSC1/
RA6/OSC2/CLKOUT
Recommended Values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)
CEXT > 20 pF
PIC16F627A/628A/648A
DS40044G-page 102 © 2009 Microchip Technology Inc.
FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R Q
External
Reset
MCLR/
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple-counter
Reset
Enable OST
Enable PWRT
Sleep
See Table 14-3 for time out situations.
Note 1: This is a separate oscillator from the INTOSC/RC oscillator.
Brown-out
Reset
BOREN
CLKIN
Pin
VPP Pin
10-bit Ripple-counter
Q
Schmitt Trigger Input
On-chip
(1)

OSC
© 2009 Microchip Technology Inc. DS40044G-page 103
PIC16F627A/628A/648A
14.4 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
14.4.1 POWER-ON RESET (POR)
The on-chip POR holds the part in Reset until a VDD
rise is detected (in the range of 1.2-1.7V). A maxi-
mum rise time for VDD is required. See Section 17.0
“Electrical Specifications” for details.
The POR circuit does not produce an internal Reset
when VDD declines.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset via MCLR, BOR
or PWRT until the operating conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting” (DS00607).
14.4.2 POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) time out
on power-up (POR) or if enabled from a Brown-out
Reset. The PWRT operates on an internal RC oscilla-
tor. The chip is kept in Reset as long as PWRT is active.
The PWRT delay allows the VDD to rise to an accept-
able level. A configuration bit, PWRTE can disable (if
set) or enable (if cleared or programmed) the PWRT. It
is recommended that the PWRT be enabled when
Brown-out Reset is enabled.
The power-up time delay will vary from chip-to-chip and
due to VDD, temperature and process variation. See
DC parameters Table 17-7 for details.
14.4.3 OSCILLATOR START-UP TIMER
(OST)
The OST provides a 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. Program
execution will not start until the OST time out is
complete. This ensures that the crystal oscillator or
resonator has started and stabilized.
The OST time out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep. See Table 17-7.
14.4.4 BROWN-OUT RESET (BOR)
The PIC16F627A/628A/648A have on-chip BOR
circuitry. A configuration bit, BOREN, can disable (if
clear/programmed) or enable (if set) the BOR circuitry.
If VDD falls below VBOR for longer than TBOR, the
brown-out situation will reset the chip. A Reset is not
assured if VDD falls below VBOR for shorter than TBOR.
VBOR and TBOR are defined in Table 17-2 and
Table 17-7, respectively.
On any Reset (Power-on, Brown-out, Watchdog, etc.),
the chip will remain in Reset until VDD rises above
VBOR (see Figure 14-7). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 72 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms Reset. Figure 14-7 shows typical brown-out
situations.
FIGURE 14-7: BROWN-OUT SITUATIONS WITH PWRT ENABLED
72 ms
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset
72 ms
<72 ms
72 ms
VBOR
VDD
Internal
Reset
≥ TBOR
Note: 72 ms delay only if PWRTE bit is programmed to ‘0’.
PIC16F627A/628A/648A
DS40044G-page 104 © 2009 Microchip Technology Inc.
14.4.5 TIME OUT SEQUENCE
On power-up, the time out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time out will vary based on
oscillator configuration and PWRTE bit Status. For
example, in RC mode with PWRTE bit set (PWRT
disabled), there will be no time out at all. Figure 14-8,
Figure 14-11 and Figure 14-12 depict time out
sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-11). This is useful for testing purposes
or to synchronize more than one PIC16F627A/628A/
648A device operating in parallel.
Table 14-6 shows the Reset conditions for some
special registers, while Table 14-7 shows the Reset
conditions for all the registers.
14.4.6 POWER CONTROL (PCON) STATUS
REGISTER
The PCON/Status register, PCON (address 8Eh), has
two bits.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BOREN bit = 0 in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (VDD may have
gone too low).
TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS
TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
Oscillator Configuration
Power-up Timer Brown-out Reset
Wake-up from
Sleep
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms +
1024•TOSC
1024•TOSC 72 ms +
1024•TOSC
1024•TOSC 1024•TOSC
RC, EC 72 ms — 72 ms — —
INTOSC 72 ms — 72 ms — 6 μs
POR BOR TO PD Condition
0 X 1 1 Power-on Reset
0 X 0 X Illegal, TO is set on POR
0 X X 0 Illegal, PD is set on POR
1 0 X X Brown-out Reset
1 1 0 u WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
© 2009 Microchip Technology Inc. DS40044G-page 105
PIC16F627A/628A/648A
TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR Reset
Value on all
other
Resets
(1)
03h, 83h,
103h, 183h
STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu
8Eh PCON — — — — OSCF — POR BOR ---- 1-0x ---- u-uq
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by Brown-out Reset.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
Condition
Program
Counter
Status
Register
PCON
Register
Power-on Reset 000h 0001 1xxx ---- 1-0x
MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu
MCLR Reset during Sleep 000h 0001 0uuu ---- 1-uu
WDT Reset 000h 0000 uuuu ---- 1-uu
WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu
Brown-out Reset 000h 000x xuuu ---- 1-u0
Interrupt Wake-up from Sleep PC + 1
(1)
uuu1 0uuu ---- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC + 1.
PIC16F627A/628A/648A
DS40044G-page 106 © 2009 Microchip Technology Inc.
TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on Reset
• MCLR Reset during normal
operation
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset
(1)
• Wake-up from Sleep
(7)
through
interrupt
• Wake-up from Sleep
(7)
through
WDT time out
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h, 80h,
100h, 180h
— — —
TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h, 82h,
102h, 182h
0000 0000 0000 0000 PC + 1
(3)
STATUS 03h, 83h,
103h, 183h
0001 1xxx 000q quuu
(4)
uuuq 0uuu
(4)
FSR 04h, 84h,
104h, 184h
xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h xxxx 0000 xxxx 0000 uuuu uuuu
PORTB 06h, 106h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah, 8Ah,
10Ah, 18Ah
---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh, 8Bh,
10Bh,18Bh
0000 000x 0000 000u uuuu uqqq
(2)
PIR1 0Ch 0000 -000 0000 -000 qqqq -qqq
(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h --00 0000 --uu uuuu
(6)
--uu uuuu
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 17h --00 0000 --00 0000 --uu uuuu
RCSTA 18h 0000 000x 0000 000x uuuu uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
CMCON 1Fh 0000 0000 0000 0000 uu-- uuuu
OPTION 81h,181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h 1111 1111 1111 1111 uuuu uuuu
TRISB 86h, 186h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 -000 0000 -000 uuuu -uuu
PCON 8Eh ---- 1-0x ---- 1-uq
(1,5)
---- u-uu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
EEDATA 9Ah xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 9Bh xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
EECON2 9Dh — — —
VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-6 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: Reset to ‘--00 0000’ on a Brown-out Reset (BOR).
7: Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers.
© 2009 Microchip Technology Inc. DS40044G-page 107
PIC16F627A/628A/648A
FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE
FIGURE 14-9: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time Out
OST Time Out
Internal Reset
PIC16F627A/628A/648A
DS40044G-page 108 © 2009 Microchip Technology Inc.
FIGURE 14-11: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 14-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 14-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge (ESD)
or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16F627A/628A/648A
VDD
Note 1: This circuit will activate Reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.
VDD
33k
10k
40k
VDD
MCLR
PIC16F627A/628A/648A
x
R1
R1 + R2
= 0.7 V
VDD
R2
40k
VDD
MCLR
PIC16F627A/628A/648A
R1
Q1
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
2: Internal Brown-out Reset should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
VDD x
R1
R1 + R2
= 0.7 V
© 2009 Microchip Technology Inc. DS40044G-page 109
PIC16F627A/628A/648A
14.5 Interrupts
The PIC16F627A/628A/648A has 10 sources of
interrupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PORTB Change Interrupts (pins RB<7:4>)
• Comparator Interrupt
• USART Interrupt TX
• USART Interrupt RX
• CCP Interrupt
• TMR1 Overflow Interrupt
• TMR2 Match Interrupt
• Data EEPROM Interrupt
The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on Reset.
The “return-from-interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which re-
enables RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid RB0/
INT recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-15).
The latency is the same for one or two-cycle instructions.
Once in the interrupt service routine, the source(s) of the
interrupt can be determined by polling the interrupt flag
bits. The interrupt flag bit(s) must be cleared in software
before re-enabling interrupts to avoid multiple interrupt
requests.
FIGURE 14-14: INTERRUPT LOGIC
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
TMR2IF
TMR2IE
CCP1IF
CCP1IE
CMIF
CMIE
TXIF
TXIE
RCIF
RCIE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (if in Sleep mode)
(1)
Interrupt to CPU
EEIE
EEIF
TMR1IF
TMR1IE
Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is
suspended during Sleep, only those peripherals which do not depend upon the system
clock will wake the part from Sleep. See Section 14.8.1 “Wake-up from Sleep”.
PIC16F627A/628A/648A
DS40044G-page 110 © 2009 Microchip Technology Inc.
14.5.1 RB0/INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from Sleep, if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.8 “Power-Down Mode (Sleep)” for details
on Sleep, and Figure 14-17 for timing of wake-up from
Sleep through RB0/INT interrupt.
14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set the
T0IF (INTCON<2>) bit. The interrupt can be enabled/
disabled by setting/clearing T0IE (INTCON<5>) bit. For
operation of the Timer0 module, see Section 6.0
“Timer0 Module”.
14.5.3 PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/disabled
by setting/clearing the RBIE (INTCON<3>) bit. For
operation of PORTB (Section 5.2 “PORTB and TRISB
Registers”).
14.5.4 COMPARATOR INTERRUPT
See Section 10.6 “Comparator Interrupts” for
complete description of comparator interrupts.
FIGURE 14-15: INT PIN INTERRUPT TIMING
Note: If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC + 1)
Inst (PC - 1)
Inst (0004h)
Dummy Cycle Inst (PC)

Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
3: CLKOUT is available in RC and INTOSC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
(1)
(1)
(4)
(5)
(2)
(3)
© 2009 Microchip Technology Inc. DS40044G-page 111
PIC16F627A/628A/648A
TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS
14.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
Status register). This must be implemented in software.
Example 14-1 stores and restores the Status and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x170 and 0x1F0). The Example 14-1:
• Stores the W register
• Stores the Status register
• Executes the ISR code
• Restores the Status (and bank select bit register)
• Restores the W register
EXAMPLE 14-1: SAVING THE STATUS
AND W REGISTERS IN
RAM
14.7 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the CLKIN pin. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped, for example, by
execution of a SLEEP instruction. During normal
operation, a WDT time out generates a device Reset. If
the device is in Sleep mode, a WDT time out causes
the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 14.1 “Configuration Bits”).
14.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC Specifications, Table 17-7). If longer time-
out periods are desired, a postscaler with a division ratio
of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register. Thus,
time-out periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the Status register will be cleared upon a
Watchdog Timer time out.
14.7.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time out occurs.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR Reset
Value on all
other
Resets
(1)
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
MOVWF W_TEMP ;copy W to temp register,
;could be in any bank
SWAPF STATUS,W ;swap status to be saved
;into W
BCF STATUS,RP0 ;change to bank 0
;regardless of current
;bank
MOVWF STATUS_TEMP;save status to bank 0
;register
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP
register
;into W, sets bank to
original
;state
MOVWF STATUS ;move W into STATUS
;register
SWAPF W_TEMP,F ;swap W_TEMP
SWAPF W_TEMP,W ;swap W_TEMP into W
PIC16F627A/628A/648A
DS40044G-page 112 © 2009 Microchip Technology Inc.
FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
14.8 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the Status register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low or high-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS with no external
circuitry drawing current from the I/O pin and the
comparators, and VREF should be disabled. I/O pins
that are high-impedance inputs should be pulled high
or low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (VIHMC).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR Reset
Value on
all other
Resets
2007h CONFIG LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 uuuu uuuu uuuu uuuu
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Note: Shaded cells are not used by the Watchdog Timer.
(Figure 6-1)
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
From TMR0 Clock Source
Watchdog
Timer
WDT
Enable Bit
0
1
8
8 to 1 MUX
PS<2:0>
To TMR0
(Figure 6-1)
0 1
PSA
WDT
Time-out
PSA
M
U
X
MUX
3
WDT Postscaler/
TMR0 Prescaler
Note: It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
© 2009 Microchip Technology Inc. DS40044G-page 113
PIC16F627A/628A/648A
14.8.1 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin
2. Watchdog Timer wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB port change, or
any peripheral interrupt, which is active in Sleep.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT wake-up occurred.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have an NOP after the SLEEP
instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
14.9 Code Protection
With the Code-Protect bit is cleared (Code-Protect
enabled), the contents of the program memory
locations are read out as ‘0’. See “PIC16F627A/628A/
648A EEPROM Memory Programming Specification”
(DS41196) for details.
14.10 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during Program/Verify.
Only the Least Significant 4 bits of the user ID locations
are used for checksum calculations although each
location has 14 bits.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will not enter
Sleep. The SLEEP instruction is executed as
a NOP instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h
(3)
0005h
Dummy cycle
TOST
(1,2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). Approximately 1 μs delay will be there for RC Oscillator mode.
3: GIE = 1 assumed. In this case, after wake-up the processor jumps to the interrupt routine. If GIE = 0, execution will continue
in-line.
4: CLKOUT is not available in these Oscillator modes, but shown here for timing reference.
Note: Only a Bulk Erase function can set the CP
and CPD bits by turning off the code
protection. The entire data EEPROM and
Flash program memory will be erased to
turn the code protection off.
PIC16F627A/628A/648A
DS40044G-page 114 © 2009 Microchip Technology Inc.
14.11 In-Circuit Serial Programming™
(ICSP™)
The PIC16F627A/628A/648A microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH. See “PIC16F627A/
628A/648A EEPROM Memory Programming
Specification” (DS41196) for details. RB6 becomes the
programming clock and RB7 becomes the programming
data. Both RB6 and RB7 are Schmitt Trigger inputs in
this mode.
After Reset, to place the device into Programming/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depending
on the command, 14 bits of program data are then
supplied to or from the device, depending if the command
was a load or a read. For complete details of serial
programming, please refer to “PIC16F627A/628A/648A
EEPROM Memory Programming Specification”
(DS41196).
A typical In-Circuit Serial Programming connection is
shown in Figure 14-18.
FIGURE 14-18: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
14.12 Low-Voltage Programming
The LVP bit of the Configuration Word, enables the low-
voltage programming. This mode allows the
microcontroller to be programmed via ICSP using only
a 5V source. This mode removes the requirement of
VIHH to be placed on the MCLR pin. The LVP bit is
normally erased to ‘1’ which enables the low-voltage
programming. In this mode, the RB4/PGM pin is
dedicated to the programming function and ceases to
be a general purpose I/O pin. The device will enter
Programming mode when a ‘1’ is placed on the RB4/
PGM pin. The High-Voltage Programming mode is still
available by placing VIHH on the MCLR pin.
If Low-Voltage Programming mode is not used, the
LVP bit should be programmed to a ‘0’ so that RB4/
PGM becomes a digital I/O pin. To program the device,
VIHH must be placed onto MCLR during programming.
The LVP bit may only be programmed when program-
ming is entered with VIHH on MCLR. The LVP bit
cannot be programmed when programming is entered
with RB4/PGM.
It should be noted, that once the LVP bit is programmed
to ‘0’, only High-Voltage Programming mode can be
used to program the device.
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F627A/628A/648A
VDD
VSS
RA5/MCLR/VPP
RB6/PGC
RB7/PGD
+5V
0V
VPP
CLK
Data I/O
VDD
Note 1: While in this mode, the RB4 pin can no
longer be used as a general purpose I/O
pin.
2: VDD must be 5.0V +10% during erase
operations.
© 2009 Microchip Technology Inc. DS40044G-page 115
PIC16F627A/628A/648A
14.13 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB
®
ICD 2 development with
an 18-pin device is not practical. A special 28-pin
PIC16F648A-ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user. Debugging of all
three versions of the PIC16F627A/628A/648A is
supported by the PIC16F648A-ICD.
This special ICD device is mounted on the top of a
header and its signals are routed to the MPLAB ICD 2
connector. On the bottom of the header is an 18-pin
socket that plugs into the user’s target via an 18-pin
stand-off connector.
When the ICD pin on the PIC16F648A-ICD device is
held low, the In-Circuit Debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB ICD 2. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 14-19
shows which features are consumed by the background
debugger.
TABLE 14-19: DEBUGGER RESOURCES
The PIC16F648A-ICD device with header is supplied
as an assembly. See Microchip Part Number
AC162053.
I/O pins ICDCLK, ICDDATA
Stack 1 level
Program Memory Address 0h must be NOP
300h-3FEh
PIC16F627A/628A/648A
DS40044G-page 116 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 117
PIC16F627A/628A/648A
15.0 INSTRUCTION SET SUMMARY
Each PIC16F627A/628A/648A instruction is a 14-bit
word divided into an OPCODE which specifies the
instruction type and one or more operands which
further specify the operation of the instruction. The
PIC16F627A/628A/648A instruction set summary in
Table 15-2 lists byte-oriented, bit-oriented, and
literal and control operations. Table 15-1 shows the
opcode field descriptions.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven bit constant or literal value.
15.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a “clrf PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended result that the condition that sets the RBIF flag
would be cleared for pins configured as inputs and
using the PORTB interrupt-on-change feature.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 μs. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 μs.
Table 15-2 lists the instructions recognized by the
MPASM™ assembler.
Figure 15-1 shows the three general formats that the
instructions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
TO Time-out bit
PD Power-down bit
Note 1: Any unused opcode is reserved. Use of
any reserved opcode may cause unex-
pected operation.
2: To maintain upward compatibility with
future PIC

MCU

products, do not use the
OPTION and TRIS instructions.
Byte-oriented file register operations
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
OPCODE k (literal)
k = 8-bit immediate value
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
13 8 7 6 0
13 10 9 7 0 6
13 8 7 0
13 11 10 0
PIC16F627A/628A/648A
DS40044G-page 118 © 2009 Microchip Technology Inc.
TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET
Mnemonic,
Operands
Description Cycles
14-Bit Opcode
Status
Affected
Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f

f, d
f, d
f, d
f, d
f, d
f, d
f, d
f

f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
(2)
1
1
(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
(2)
1
(2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k

k
k
k

k


k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data
will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.
© 2009 Microchip Technology Inc. DS40044G-page 119
PIC16F627A/628A/648A
15.2 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Encoding: 11 111x kkkk kkkk
Description: The contents of the W register
are added to the eight bit literal
‘k’ and the result is placed in the
W register.
Words: 1
Cycles: 1
Example ADDLW 0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (dest)
Status Affected: C, DC, Z
Encoding: 00 0111 dfff ffff
Description: Add the contents of the W
register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example ADDWF REG1, 0
Before Instruction
W = 0x17
REG1 = 0xC2
After Instruction
W = 0xD9
REG1 = 0xC2
Z = 0
C = 0
DC = 0
ANDLW AND Literal with W
Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Encoding: 11 1001 kkkk kkkk
Description: The contents of W register are
AND’ed with the eight bit literal
‘k’. The result is placed in the W
register.
Words: 1
Cycles: 1
Example ANDLW 0x5F
Before Instruction
W = 0xA3
After Instruction
W = 0x03
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (dest)
Status Affected: Z
Encoding: 00 0101 dfff ffff
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored
in the W register. If ‘d’ is ‘1’, the
result is stored back in register
‘f’.
Words: 1
Cycles: 1
Example ANDWF REG1, 1
Before Instruction
W = 0x17
REG1 = 0xC2
After Instruction
W = 0x17
REG1 = 0x02
PIC16F627A/628A/648A
DS40044G-page 120 © 2009 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Encoding: 01 00bb bfff ffff
Description: Bit ‘b’ in register ‘f’ is cleared.
Words: 1
Cycles: 1
Example BCF REG1, 7
Before Instruction
REG1 = 0xC7
After Instruction
REG1 = 0x47
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit ‘b’ in register ‘f’ is set.
Words: 1
Cycles: 1
Example BSF REG1, 7
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 01 10bb bfff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next
instruction fetched during the
current instruction execution is
discarded, and a NOP is executed
instead, making this a two-cycle
instruction.
Words: 1
Cycles: 1(2)
Example HERE
FALSE
TRUE
BTFSC
GOTO



REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if REG<1> = 0,
PC = address TRUE
if REG<1> =1,
PC = address FALSE
© 2009 Microchip Technology Inc. DS40044G-page 121
PIC16F627A/628A/648A
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 01 11bb bfff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then
the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next
instruction fetched during the
current instruction execution, is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
Words: 1
Cycles: 1(2)
Example HERE
FALSE
TRUE
BTFSS
GOTO



REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Encoding: 10 0kkk kkkk kkkk
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven bit imme-
diate address is loaded into PC
bits <10:0>. The upper bits of
the PC are loaded from
PCLATH. CALL is a two-cycle
instruction.
Words: 1
Cycles: 2
Example HERE CALL THERE
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
Words: 1
Cycles: 1
Example CLRF REG1
Before Instruction
REG1 = 0x5A
After Instruction
REG1 = 0x00
Z = 1
PIC16F627A/628A/648A
DS40044G-page 122 © 2009 Microchip Technology Inc.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Encoding: 00 0001 0000 0011
Description: W register is cleared. Zero bit
(Z) is set.
Words: 1
Cycles: 1
Example CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z = 1
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Words: 1
Cycles: 1
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler = 0
TO = 1
PD = 1
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Encoding: 00 1001 dfff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Words: 1
Cycles: 1
Example COMF REG1, 0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W = 0xEC
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (dest)
Status Affected: Z
Encoding: 00 0011 dfff ffff
Description: Decrement register ‘f’. If ‘d’ is
‘0’. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example DECF CNT, 1
Before Instruction
CNT = 0x01
Z = 0
After Instruction
CNT = 0x00
Z = 1
© 2009 Microchip Technology Inc. DS40044G-page 123
PIC16F627A/628A/648A
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (dest); skip if result =
0
Status Affected: None
Encoding: 00 1011 dfff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
If the result is ‘0’, the next
instruction, which is already
fetched, is discarded. A NOP is
executed instead making it a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Example HERE DECFSZ REG1, 1
GOTO LOOP
CONTINUE •


Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 - 1
if REG1 = 0,
PC = address CONTINUE
if REG1 ≠ 0,
PC = address HERE+1
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Description: GOTO is an unconditional
branch. The eleven-bit immedi-
ate value is loaded into PC bits
<10:0>. The upper bits of PC
are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
Words: 1
Cycles: 2
Example GOTO THERE
After Instruction
PC = Address THERE
PIC16F627A/628A/648A
DS40044G-page 124 © 2009 Microchip Technology Inc.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (dest)
Status Affected: Z
Encoding: 00 1010 dfff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Words: 1
Cycles: 1
Example INCF REG1, 1
Before Instruction
REG1 = 0xFF
Z = 0
After Instruction
REG1 = 0x00
Z = 1
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (dest), skip if result = 0
Status Affected: None
Encoding: 00 1111 dfff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
If the result is ‘0’, the next
instruction, which is already
fetched, is discarded. A NOP is
executed instead making it a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Example HERE INCFSZ REG1, 1
GOTO LOOP
CONTINUE •


Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1≠ 0,
PC = address HERE +1
© 2009 Microchip Technology Inc. DS40044G-page 125
PIC16F627A/628A/648A
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Status Affected: Z
Encoding: 11 1000 kkkk kkkk
Description: The contents of the W register is
OR’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Words: 1
Cycles: 1
Example IORLW 0x35
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (dest)
Status Affected: Z
Encoding: 00 0100 dfff ffff
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’
is ‘1’, the result is placed back in
register ‘f’.
Words: 1
Cycles: 1
Example IORWF REG1, 0
Before Instruction
REG1 = 0x13
W = 0x91
After Instruction
REG1 = 0x13
W = 0x93
Z = 1
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Encoding: 11 00xx kkkk kkkk
Description: The eight bit literal ‘k’ is loaded
into W register. The “don’t
cares” will assemble as ‘0’s.
Words: 1
Cycles: 1
Example MOVLW 0x5A
After Instruction
W = 0x5A
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Encoding: 00 1000 dfff ffff
Description: The contents of register ‘f’ is
moved to a destination
dependent upon the status of
‘d’. If d = 0, destination is W
register. If d = 1, the destination
is file register f itself. d = 1 is
useful to test a file register since
status flag Z is affected.
Words: 1
Cycles: 1
Example MOVF REG1, 0
After Instruction
W= value in REG1 register
Z = 1
PIC16F627A/628A/648A
DS40044G-page 126 © 2009 Microchip Technology Inc.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Encoding: 00 0000 1fff ffff
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example MOVWF REG1
Before Instruction
REG1 = 0xFF
W = 0x4F
After Instruction
REG1 = 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 00 0000 0xx0 0000
Description: No operation.
Words: 1
Cycles: 1
Example NOP
OPTION Load Option Register
Syntax: [ label ] OPTION
Operands: None
Operation: (W) → OPTION
Status Affected: None
Encoding: 00 0000 0110 0010
Description: The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
products. Since OPTION is a
readable/writable register, the
user can directly address it. Using
only register instruction such as
MOVWF.
Words: 1
Cycles: 1
Example
To maintain upward compatibil-
ity with future PIC
®
MCU
products, do not use this
instruction.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
Encoding: 00 0000 0000 1001
Description: Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS)
is loaded in the PC. Interrupts
are enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-
cycle instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
© 2009 Microchip Technology Inc. DS40044G-page 127
PIC16F627A/628A/648A
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Encoding: 11 01xx kkkk kkkk
Description: The W register is loaded with
the eight-bit literal ‘k’. The
program counter is loaded from
the top of the stack (the return
address). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example
TABLE
CALL TABLE;W contains table
;offset value
• ;W now has table value


ADDWF PC;W = offset
RETLW k1;Begin table
RETLW k2;



RETLW kn; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
two-cycle instruction.
Words: 1
Cycles: 2
Example RETURN
After Interrupt
PC = TOS
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1101 dfff ffff
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example RLF REG1, 0
Before Instruction
REG1=1110 0110
C = 0
After Instruction
REG1=1110 0110
W = 1100 1100
C = 1
REGISTER F C
PIC16F627A/628A/648A
DS40044G-page 128 © 2009 Microchip Technology Inc.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1100 dfff ffff
Description: The contents of register ‘f’ are
rotated one bit to the right
through the Carry Flag. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Words: 1
Cycles: 1
Example RRF REG1, 0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 0111 0011
C = 0
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down Status bit, PD
is cleared. Time out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator
stopped. See Section 14.8
“Power-Down Mode (Sleep)”
for more details.
Words: 1
Cycles: 1
Example: SLEEP
REGISTER F C
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status
Affected:
C, DC, Z
Encoding: 11 110x kkkk kkkk
Description: The W register is subtracted (2’s
complement method) from the eight-
bit literal ‘k’. The result is placed in
the W register.
Words: 1
Cycles: 1
Example 1: SUBLW 0x02
Before Instruction
W = 1
C = ?
After Instruction
W = 1
C = 1; result is positive
Example 2: Before Instruction
W = 2
C = ?
After Instruction
W = 0
C = 1; result is zero
Example 3: Before Instruction
W = 3
C = ?
After Instruction
W = 0xFF
C = 0; result is negative
© 2009 Microchip Technology Inc. DS40044G-page 129
PIC16F627A/628A/648A
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (dest)
Status
Affected:
C, DC, Z
Encoding: 00 0010 dfff ffff
Description: Subtract (2’s complement method)
Wregister from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example 1: SUBWF REG1, 1
Before Instruction
REG1 = 3
W = 2
C = ?
After Instruction
REG1 = 1
W = 2
C = 1; result is positive
DC = 1
Z = 0
Example 2: Before Instruction
REG1 = 2
W = 2
C = ?
After Instruction
REG1 = 0
W = 2
C = 1; result is zero
Z = DC = 1
Example 3: Before Instruction
REG1 = 1
W = 2
C = ?
After Instruction
REG1 = 0xFF
W = 2
C = 0; result is negative
Z = DC = 0
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status Affected: None
Encoding: 00 1110 dfff ffff
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
Words: 1
Cycles: 1
Example SWAPF REG1, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
W = 0x5A
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operands: 5 ≤ f ≤ 7
Operation: (W) → TRIS register f;
Status Affected: None
Encoding: 00 0000 0110 0fff
Description: The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and
writable, the user can directly
address them.
Words: 1
Cycles: 1
Example
To maintain upward compatibil-
ity with future PIC
®
MCU
products, do not use this
instruction.
PIC16F627A/628A/648A
DS40044G-page 130 © 2009 Microchip Technology Inc.
XORLW Exclusive OR Literal with W
Syntax: [ label ] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Encoding: 11 1010 kkkk kkkk
Description: The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the Wregister.
Words: 1
Cycles: 1
Example: XORLW 0xAF
Before Instruction
W = 0xB5
After Instruction
W = 0x1A
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (dest)
Status Affected: Z
Encoding: 00 0110 dfff ffff
Description: Exclusive OR the contents of the
Wregister with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example XORWF REG1, 1
Before Instruction
REG1 = 0xAF
W = 0xB5
After Instruction
REG1 = 0x1A
W = 0xB5
© 2009 Microchip Technology Inc. DS40044G-page 131
PIC16F627A/628A/648A
16.0 DEVELOPMENT SUPPORT
The PIC
®
microcontrollers and dsPIC
®
digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB
®
IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASM
TM
Assembler
- MPLINK
TM
Object Linker/
MPLIB
TM
Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
16.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows
®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC16F627A/628A/648A
DS40044G-page 132 © 2009 Microchip Technology Inc.
16.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
16.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
16.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel
®
standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
16.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
16.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
© 2009 Microchip Technology Inc. DS40044G-page 133
PIC16F627A/628A/648A
16.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC
®
DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
16.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC
®
Flash MCUs and dsPIC
®
Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
16.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC
®
Flash microcon-
trollers and dsPIC
®
DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
16.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC
®
and dsPIC
®
Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC16F627A/628A/648A
DS40044G-page 134 © 2009 Microchip Technology Inc.
16.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows
®
programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC
®
microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
16.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
16.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ
®
security ICs, CAN,
IrDA
®
, PowerSmart battery management, SEEVAL
®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2009 Microchip Technology Inc. DS40044G-page 135
PIC16F627A/628A/648A
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias................................................................................................................. -40 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +14V
Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V
Total power dissipation
(1)
..................................................................................................................................... 800 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin .............................................................................................................................. 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)............................................................................................................... ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin .................................................................................................... 25 mA
Maximum current sunk by PORTA and PORTB (Combined)................................................................................ 200 mA
Maximum current sourced by PORTA and PORTB (Combined)........................................................................... 200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.
PIC16F627A/628A/648A
DS40044G-page 136 © 2009 Microchip Technology Inc.
FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
4 10
FREQUENCY (MHz)
VDD
20
(VOLTS)
25
Note: The shaded region indicates the permissible combinations of voltage and frequency.
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
4 10
FREQUENCY (MHz)
VDD
20
(VOLTS)
25
2.0
Note: The shaded region indicates the permissible combinations of voltage and frequency.
© 2009 Microchip Technology Inc. DS40044G-page 137
PIC16F627A/628A/648A
17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
PIC16LF627A/628A/648A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial
PIC16F627A/628A/648A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and
-40°C ≤ Ta ≤ +125°C for extended
Param
No.
Sym Characteristic/Device Min Typ† Max Units Conditions
VDD Supply Voltage
D001 PIC16LF627A/628A/648A 2.0 — 5.5 V
PIC16F627A/628A/648A 3.0 — 5.5 V
D002 VDR RAM Data Retention
Voltage
(1)
— 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage
to ensure Power-on Reset
— VSS — V See Section 14.4 “Power-
on Reset (POR), Power-up
Timer (PWRT), Oscillator
Start-up Timer (OST) and
Brown-out Reset
(BOR)”on Power-on Reset
for details
D004 SVDD VDD Rise Rate
to ensure Power-on Reset
0.05* — — V/ms See Section 14.4 “Power-
on Reset (POR), Power-up
Timer (PWRT), Oscillator
Start-up Timer (OST) and
Brown-out Reset (BOR)”
on Power-on Reset for
details
D005 VBOR Brown-out Reset Voltage 3.65
3.65
4.0
4.0
4.35
4.4
V
V
BOREN configuration bit is
set
BOREN configuration bit is
set, Extended
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
PIC16F627A/628A/648A
DS40044G-page 138 © 2009 Microchip Technology Inc.
17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial)
PIC16LF627A/628A/648A (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial
Param
No.
LF and F Device
Characteristics
Min† Typ Max Units
Conditions
VDD Note
Supply Voltage (VDD)
D001
LF 2.0 — 5.5 V —
LF/F 3.0 — 5.5 V —
Power-down Base Current (IPD)
D020
LF — 0.01 0.80 μA 2.0 WDT, BOR, Comparators, VREF and
T1OSC: disabled
LF/F — 0.01 0.85 μA 3.0
— 0.02 2.7 μA 5.0
Peripheral Module Current (ΔIMOD)
(1)
D021
LF — 1 2.0 μA 2.0 WDT Current
LF/F — 2 3.4 μA 3.0
— 9 17.0 μA 5.0
D022
LF/F — 29 52 μA 4.5 BOR Current
— 30 55 μA 5.0
D023
LF — 15 22 μA 2.0 Comparator Current
(Both comparators enabled)
LF/F — 22 37 μA 3.0
— 44 68 μA 5.0
D024
LF — 34 55 μA 2.0 VREF Current
LF/F — 50 75 μA 3.0
— 80 110 μA 5.0
D025
LF — 1.2 2.0 μA 2.0 T1OSC Current
LF/F — 1.3 2.2 μA 3.0
— 1.8 2.9 μA 5.0
Supply Current (IDD)
D010
LF — 10 15 μA 2.0 FOSC = 32 kHz
LP Oscillator Mode
LF/F — 15 25 μA 3.0
— 28 48 μA 5.0
D011
LF — 125 190 μA 2.0 FOSC = 1 MHz
XT Oscillator Mode
LF/F — 175 340 μA 3.0
— 320 520 μA 5.0
D012
LF — 250 350 μA 2.0 FOSC = 4 MHz
XT Oscillator Mode
LF/F — 450 600 μA 3.0
— 710 995 μA 5.0
D012A
LF — 395 465 μA 2.0 FOSC = 4 MHz
INTOSC
LF/F — 565 785 μA 3.0
— 0.895 1.3 mA 5.0
D013
LF/F — 2.5 2.9 mA 4.5 FOSC = 20 MHz
HS Oscillator Mode
— 2.75 3.3 mA 5.0
Note 1: The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
© 2009 Microchip Technology Inc. DS40044G-page 139
PIC16F627A/628A/648A
17.3 DC Characteristics: PIC16F627A/628A/648A (Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +125°C for extended
Param
No.
Device Characteristics Min† Typ Max Units
Conditions
VDD Note
Supply Voltage (VDD)
D001 — 3.0 — 5.5 V —
Power-down Base Current (IPD)
D020E
— — 0.01 4 μA 3.0 WDT, BOR, Comparators, VREF and
T1OSC: disabled
— 0.02 8 μA 5.0
Peripheral Module Current (ΔIMOD)
(1)
D021E
— — 2 9 μA 3.0 WDT Current
— 9 20 μA 5.0
D022E
— — 29 52 μA 4.5 BOR Current
— 30 55 μA 5.0
D023E
— — 22 37 μA 3.0 Comparator Current
(Both comparators enabled)
— 44 68 μA 5.0
D024E
— — 50 75 μA 3.0 VREF Current
— 83 110 μA 5.0
D025E
— — 1.3 4 μA 3.0 T1OSC Current
— 1.8 6 μA 5.0
Supply Current (IDD)
D010E
— — 15 28 μA 3.0 FOSC = 32 kHz
LP Oscillator Mode
— 28 54 μA 5.0
D011E
— — 175 340 μA 3.0 FOSC = 1 MHz
XT Oscillator Mode
— 320 520 μA 5.0
D012E
— — 450 650 μA 3.0 FOSC = 4 MHz
XT Oscillator Mode
— 0.710 1.1 mA 5.0
D012AE
— — 565 785 μA 3.0 FOSC = 4 MHz
INTOSC
— 0.895 1.3 mA 5.0
D013E
— — 2.5 2.9 mA 4.5 FOSC = 20 MHz
HS Oscillator Mode
— 2.75 3.5 mA 5.0
Note 1: The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
PIC16F627A/628A/648A
DS40044G-page 140 © 2009 Microchip Technology Inc.
17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC specification Table 17-2 and
Table 17-3
Param.
No.
Sym Characteristic/Device Min Typ† Max Unit Conditions
VIL Input Low Voltage
D030
D031
D032
D033
I/O ports
with TTL buffer
with Schmitt Trigger input
(4)
MCLR, RA4/T0CKI,OSC1
(in RC mode)
OSC1 (in HS)
OSC1 (in LP and XT)
VSS
VSS
VSS
VSS
VSS
VSS






0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.6
V
V
V
V
V
V
VDD = 4.5V to 5.5V
otherwise
(Note1)
VIH Input High Voltage
D040
D041
D042
D043
D043A
D043B
I/O ports
with TTL buffer
with Schmitt Trigger input
(4)
MCLR RA4/T0CKI
OSC1 (XT and LP)
OSC1 (in RC mode)
OSC1 (in HS mode)
2.0V
.25 VDD + 0.8V
0.8 VDD
0.8 VDD
1.3
0.9 VDD
0.7 VDD






VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
VDD = 4.5V to 5.5V
otherwise
(Note1)
D070 IPURB PORTB weak pull-up
current
50 200 400 μA VDD = 5.0V, VPIN = VSS
IIL Input Leakage Current
(2), (3)
D060
D061
D063
I/O ports (Except PORTA)
PORTA
(4)
RA4/T0CKI
OSC1, MCLR








±1.0
±0.5
±1.0
±5.0
μA
μA
μA
μA
VSS ≤ VPIN ≤ VDD, pin at high-impedance
VSS ≤ VPIN ≤ VDD, pin at high-impedance
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD, XT, HS and LP
oscillator configuration
VOL Output Low Voltage
D080
I/O ports
(4)




0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5 V, -40° to +85°C
IOL = 7.0 mA, VDD = 4.5 V, +85° to
+125°C
VOH Output High Voltage
(3)
D090 I/O ports (Except RA4
(4)
) VDD – 0.7
VDD – 0.7




V
V
IOH = -3.0 mA, VDD = 4.5 V, -40° to +85°C
IOH = -2.5 mA, VDD = 4.5 V, +85° to
+125°C
D150 VOD Open-Drain High Voltage — — 8.5* V RA4 pin PIC16F627A/628A/648A,
PIC16LF627A/628A/648A
Capacitive Loading Specs on Output Pins
D100*
D101*
COSC2
CIO
OSC2 pin
All I/O pins/OSC2 (in RC mode)




15
50
pF
pF
In XT, HS and LP modes when external
clock used to drive OSC1.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F627A/628A/648A
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal
operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Includes OSC1 and OSC2 when configured as I/O pins, CLKIN or CLKOUT.
© 2009 Microchip Technology Inc. DS40044G-page 141
PIC16F627A/628A/648A
TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC specification
Table 17-2 and Table 17-3
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
Data EEPROM Memory
D120
D120A
D121
D122
D123
D124
ED
ED
VDRW
TDEW
TRETD
TREF
Endurance
Endurance
VDD for read/write
Erase/Write cycle time
Characteristic Retention
Number of Total Erase/Write
Cycles before Refresh
(1)
100K
10K
VMIN

40
1M
1M
100K

4

10M

5.5
8*


E/W
E/W
V
ms
Year
E/W
-40°C ≤ TA ≤ 85°C
85°C ≤ TA ≤ 125°C
VMIN = Minimum operating
voltage
Provided no other
specifications are violated
-40°C to +85°C
Program Flash Memory
D130
D130A
D131
D132
D132A
D133
D133A
D134
EP
EP
VPR
VIE
VPEW
TIE
TPEW
TRETP
Endurance
Endurance
VDD for read
VDD for Block erase
VDD for write
Block Erase cycle time
Write cycle time
Characteristic Retention
10K
1000
VMIN
4.5
VMIN


40
100K
10K



4
2



5.5
5.5
5.5
8*
4*

E/W
E/W
V
V
V
ms
ms
year
-40°C ≤ TA ≤ 85°C
85°C ≤ TA ≤ 125°C
VMIN = Minimum operating
voltage
VMIN = Minimum operating
voltage
VDD > 4.5V
Provided no other
specifications are violated
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Refer to Section 13.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
PIC16F627A/628A/648A
DS40044G-page 142 © 2009 Microchip Technology Inc.
TABLE 17-2: COMPARATOR SPECIFICATIONS
TABLE 17-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Characteristics Sym Min Typ Max Units Comments
D300 Input Offset Voltage VIOFF — ±5.0 ±10 mV
D301 Input Common Mode Voltage VICM 0 — VDD – 1.5* V
D302 Common Mode Rejection Ratio CMRR 55* — — db
D303 Response Time
(1)
TRESP —


300
400
400
400*
600*
600*
ns
ns
ns
VDD = 3.0V to 5.5V
-40° to +85°C
VDD = 3.0V to 5.5V
-85° to +125°C
VDD = 2.0V to 3.0V
-40° to +85°C
D304 Comparator Mode Change to
Output Valid
TMC2OV — 300 10* μs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD.
Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Spec
No.
Characteristics Sym Min Typ Max Units Comments
D310 Resolution VRES — — VDD/24
VDD/32
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
D311 Absolute Accuracy VRAA —



1/4
(2)
*
1/2
(2)
*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
D312 Unit Resistor Value (R) VRUR — 2k* — Ω
D313 Settling Time
(1)
TSET — — 10* μs
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
2: When VDD is between 2.0V and 3.0V, the VREF output voltage levels on RA2 described by the
equation:[VDD/2 ± (3 – VDD)/2] may cause the Absolute Accuracy (VRAA) of the VREF output signal on RA2
to be greater than the stated max.
© 2009 Microchip Technology Inc. DS40044G-page 143
PIC16F627A/628A/648A
17.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
FIGURE 17-3: LOAD CONDITIONS
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT osc OSC1
io I/O port t0 T0CKI
mc MCLR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-Impedance
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Condition 1 Load Condition 2
PIC16F627A/628A/648A
DS40044G-page 144 © 2009 Microchip Technology Inc.
17.6 Timing Diagrams and Specifications
FIGURE 17-4: EXTERNAL CLOCK TIMING
TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
FOSC External CLKIN Frequency
(1)
DC — 4 MHz XT and RC Osc mode,
VDD = 5.0 V
DC — 20 MHz HS, EC Osc mode
DC — 200 kHz LP Osc mode
Oscillator Frequency
(1)
— — 4 MHz RC Osc mode, VDD = 5.0V
0.1 — 4 MHz XT Osc mode
1



20
200
MHz
kHz
HS Osc mode
LP Osc mode
— 4 — MHz INTOSC mode (fast)
— 48 — kHz INTOSC mode (slow)
1 TOSC External CLKIN Period
(1)
250 — — ns XT and RC Osc mode
50 — — ns HS, EC Osc mode
5 — — μs LP Osc mode
Oscillator Period
(1)
250 — — ns RC Osc mode
250 — 10,000 ns XT Osc mode
50 — 1,000 ns HS Osc mode
5 — — μs LP Osc mode
— 250 — ns INTOSC mode (fast)
— 21 — μs INTOSC mode (slow)
2 TCY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH
External CLKIN (OSC1) High
External CLKIN Low
100* — — ns XT oscillator, TOSC L/H duty
cycle
4 RC External Biased RC
Frequency
10 kHz* — 4 MHz — VDD = 5.0V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max” cycle time
limit is “DC” (no clock) for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1 3 3
4 4
2
© 2009 Microchip Technology Inc. DS40044G-page 145
PIC16F627A/628A/648A
TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS
Legend: TBD = To Be Determined.
* Characterized but not tested.
FIGURE 17-5: CLKOUT AND I/O TIMING
Parameter
No.
Sym Characteristic Min Typ Max Units Conditions
F10 FIOSC Oscillator Center frequency
— 4 — MHz
F13 ΔIOSC Oscillator Accuracy
3.96 4 4.04 MHz VDD = 3.5 V, 25°C
3.92 4 4.08 MHz 2.0V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
3.80 4 4.20 MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (IND)
-40°C ≤ TA ≤ +125°C (EXT)
F14
*
TIOSCST Oscillator Wake-up from Sleep
start-up time
— 6 8 μs VDD = 2.0V, -40°C to +85°C
— 4 6 μs VDD = 3.0V, -40°C to +85°C
— 3 5 μs VDD = 5.0V, -40°C to +85°C
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
22
23
19
18
15
11
12
16
Old Value New Value
PIC16F627A/628A/648A
DS40044G-page 146 © 2009 Microchip Technology Inc.
TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS
FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
Parameter
No.
Sym Characteristic Min Typ† Max Units
10 TOSH2CKL OSC1↑ to CLKOUT↓
PIC16F62XA
— 75 200* ns
10A PIC16LF62XA — — 400* ns
11 TOSH2CKH OSC1↑ to CLKOUT↑ PIC16F62XA — 75 200* ns
11A PIC16LF62XA — — 400* ns
12 TCKR CLKOUT rise time PIC16F62XA — 35 100* ns
12A PIC16LF62XA — — 200* ns
13 TCKF CLKOUT fall time PIC16F62XA — 35 100* ns
13A PIC16LF62XA — — 200* ns
14 TCKL2IOV CLKOUT ↓ to Port out valid — — 20* ns
15 TIOV2CKH Port in valid before CLKOUT ↑ PIC16F62XA TOSC+200 ns* — — ns
PIC16LF62XA TOSC+400 ns* — — ns
16 TCKH2IOI Port in hold after CLKOUT ↑ 0 — — ns
17 TOSH2IOV OSC1↑ (Q1 cycle) to PIC16F62XA — 50 150* ns
Port out valid PIC16LF62XA — — 300* ns
18 TOSH2IOI OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
100*
200*
— — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time out
OST
Time out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
© 2009 Microchip Technology Inc. DS40044G-page 147
PIC16F627A/628A/648A
FIGURE 17-7: BROWN-OUT RESET TIMING
TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
30 TMCL MCLR Pulse Width (low) 2000 — — ns VDD = 5V, -40°C to +85°C
31 TWDT Watchdog Timer Time out Period
(No Prescaler)
7* 18 33* ms VDD = 5V, -40°C to +85°C
32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33 TPWRT Power-up Timer Period 28* 72 132* ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O High-impedance from MCLR
Low or Watchdog Timer Reset
— — 2.0* μs
35 TBOR Brown-out Reset pulse width 100* — — μs VDD ≤ VBOR (D005)
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
VDD
VBOR
35
46
47
45
48
41
42
40
RA4/T0CKI/CMP2
RB6/T1OSO/T1CKI/PGC
TMR0 OR
TMR1
PIC16F627A/628A/648A
DS40044G-page 148 © 2009 Microchip Technology Inc.
TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
40 TT0H T0CKI High Pulse Width
No Prescaler
0.5TCY + 20* — — ns
With Prescaler 10* — — ns
41 TT0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns
With Prescaler 10* — — ns
42 TT0P T0CKI Period
20 or
Greater of:
TCY + 40*
N
— — ns N = prescale
value (2, 4,
..., 256)
45 TT1H T1CKI High
Time
Synchronous, No Prescaler 0.5TCY + 20* — — ns
Synchronous,
with Prescaler
PIC16F62XA 15* — — ns
PIC16LF62XA 25* — — ns
Asynchronous PIC16F62XA 30* — — ns
PIC16LF62XA 50* — — ns
46 TT1L T1CKI Low
Time
Synchronous, No Prescaler 0.5TCY + 20* — — ns
Synchronous,
with Prescaler
PIC16F62XA 15* — — ns
PIC16LF62XA 25* — — ns
Asynchronous PIC16F62XA 30* — — ns
PIC16LF62XA 50* — — ns
47 TT1P T1CKI input
period
Synchronous PIC16F62XA
20 or
Greater of:
TCY + 40*
N
— — ns N = prescale
value (1, 2,
4, 8)
PIC16LF62XA
20 or
Greater of:
TCY + 40*
N
— — —
Asynchronous PIC16F62XA 60* — — ns
PIC16LF62XA 100* — — ns
FT1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit
T1OSCEN)
— 32.7
(1)
— kHz
48 TCKEZTMR1 Delay from external clock edge to timer
increment
2TOSC — 7TOSC —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This oscillator is intended to work only with 32.768 kHz watch crystals and their manufactured tolerances.
Higher value crystal frequencies may not be compatible with this crystal driver.
© 2009 Microchip Technology Inc. DS40044G-page 149
PIC16F627A/628A/648A
FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS
TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
50 TCCL CCP
input low time
No Prescaler 0.5TCY +
20*
— — ns
With Prescaler
PIC16F62XA 10* — — ns
PIC16LF62XA 20* — — ns
51 TCCH CCP
input high time
No Prescaler 0.5TCY +
20*
— — ns
With Prescaler
PIC16F62XA 10* — — ns
PIC16LF62XA 20* — — ns
52 TCCP CCP input period 3TCY + 40*
N
— — ns N = prescale
value (1,4 or 16)
53 TCCR CCP output rise time PIC16F62XA 10 25* ns
PIC16LF62XA 25 45* ns
54 TCCF CCP output fall time PIC16F62XA 10 25* ns
PIC16LF62XA 25 45* ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

(CAPTURE MODE)
50 51
52
53 54
RB3/CCP1

(COMPARE OR PWM MODE)
RB3/CCP1
PIC16F627A/628A/648A
DS40044G-page 150 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 151
PIC16F627A/628A/648A
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ‘Typical’ represents the mean of the distribution at 25°C. ‘Max’ or ‘Min’ represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.
FIGURE 18-1: TYPICAL BASELINE IPD vs. VDD (-40°C TO 25°C)
0
20
40
60
80
100
120
140
160
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
I
P
D

(
n
A
)
-40°C 0°C
+25°C
PIC16F627A/628A/648A
DS40044G-page 152 © 2009 Microchip Technology Inc.
FIGURE 18-2: TYPICAL BASELINE IPD vs. VDD (85°C)
FIGURE 18-3: TYPICAL BASELINE CURRENT IPD vs. VDD (125°C)
100
120
140
160
180
200
220
240
260
280
300
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
I
P
D

(
n
A
)
+85°C
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
+125°C
I
P
D

(
μ
A
)
© 2009 Microchip Technology Inc. DS40044G-page 153
PIC16F627A/628A/648A
FIGURE 18-4: TYPICAL BOR IPD vs. VDD
FIGURE 18-5: TYPICAL SINGLE COMPARATOR IPD vs. VDD
20
22
24
26
28
30
32
34
36
38
40
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C

I
P
D

(
μ
A
)
0
5
10
15
20
25
30
2 2.5 3 3.5 4 4.5 5 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C

I
P
D

(
μ
A
)
PIC16F627A/628A/648A
DS40044G-page 154 © 2009 Microchip Technology Inc.
FIGURE 18-6: TYPICAL VREF IPD vs. VDD
FIGURE 18-7: TYPICAL WDT IPD vs. VDD
20
30
40
50
60
70
80
90
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C

I
P
D

(
μ
A
)
0
2
4
6
8
10
12
14
16
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C
I
P
D

(
μ
A
)
© 2009 Microchip Technology Inc. DS40044G-page 155
PIC16F627A/628A/648A
FIGURE 18-8: AVERAGE IPD_TIMER1
FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
VDD = 5 VOLTS
0
1
2
3
4
5
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D


(
u
A
)
-40C
0C
25C
85C
125
-5.0%
-4.0%
-3.0%
-2.0%
-1.0%
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
-40 25 85 125
Temperature (ºC)
C
h
a
n
g
e

f
r
o
m

C
a
l
i
b
r
a
t
i
o
n

T
a
r
g
e
t

(
%
)
PIC16F627A/628A/648A
DS40044G-page 156 © 2009 Microchip Technology Inc.
FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
VDD = 3 VOLTS
FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
VDD = 2 VOLTS
-5.0%
-4.0%
-3.0%
-2.0%
-1.0%
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
-40 25 85 125
Temperature (ºC)
C
h
a
n
g
e

f
r
o
m

C
a
l
i
b
r
a
t
i
o
n

T
a
r
g
e
t

(
%
)
-5.0%
-4.0%
-3.0%
-2.0%
-1.0%
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
-40 25 85 125
Temperature (ºC)
C
h
a
n
g
e

f
r
o
m

C
a
l
i
b
r
a
t
i
o
n

T
a
r
g
e
t

(
%
)
© 2009 Microchip Technology Inc. DS40044G-page 157
PIC16F627A/628A/648A
FIGURE 18-12: TYPICAL INTERNAL OSCILLATOR DEVIATION vs. VDD AT 25°C – 4 MHz MODE
FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD TEMPERATURE =
-40°C TO 85°C
-5.0%
-4.0%
-3.0%
-2.0%
-1.0%
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
C
h
a
n
g
e

f
r
o
m

C
a
l
i
b
r
a
t
i
o
n

T
a
r
g
e
t

(
%
)
-5.0%
-4.0%
-3.0%
-2.0%
-1.0%
0.0%
1.0%
2.0%
3.0%
4.0%
5.0%
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
C
h
a
n
g
e

f
r
o
m

C
a
l
i
b
r
a
t
i
o
n

T
a
r
g
e
t

(
%
)
PIC16F627A/628A/648A
DS40044G-page 158 © 2009 Microchip Technology Inc.
FIGURE 18-14: INTERNAL OSCILLATOR IDD vs. VDD – 4 MHz MODE
FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD AT 25°C – SLOW
MODE
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
D
D

(
m
A
)
85 C 25 C Avg -40 C
30
35
40
45
50
55
60
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
O
s
c
i
l
l
a
t
o
r

F
r
e
q
u
e
n
c
y

(
k
H
z
)
© 2009 Microchip Technology Inc. DS40044G-page 159
PIC16F627A/628A/648A
FIGURE 18-16: INTERNAL OSCILLATOR IDD vs. VDD – SLOW MODE
FIGURE 18-17: SUPPLY CURRENT (IDD vs. VDD, FOSC = 1 MHz (XT OSCILLATOR MODE)
0
20
40
60
80
100
120
140
160
180
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
85 C 25 C Avg -40 C
I
P
D

(
μ
A
)
100
150
200
250
300
350
400
450
500
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C
I
P
D

(
μ
A
)
PIC16F627A/628A/648A
DS40044G-page 160 © 2009 Microchip Technology Inc.
FIGURE 18-18: SUPPLY CURRENT (IDD vs. VDD, FOSC = 4 MHz (XT OSCILLATOR MODE)
FIGURE 18-19: SUPPLY CURRENT (IDD) vs. VDD, FOSC = 20 MHz (HS OSCILLATOR MODE)
200
300
400
500
600
700
800
900
1000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD

(Volts)
125°C
85°C
25°C
0°C
-40°C
I
P
D

(
μ
A
)
2.0
2.5
3.0
3.5
4.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VDD

(Volts)
I
D
D

(
m
A
)
125°C
85°C
25°C
0°C
-40°C
© 2009 Microchip Technology Inc. DS40044G-page 161
PIC16F627A/628A/648A
FIGURE 18-20: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)
WDT Time-out
0
5
10
15
20
25
30
35
40
45
50
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
T
i
m
e

(
m
S
)
-40
0
25
85
125
PIC16F627A/628A/648A
DS40044G-page 162 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 163
PIC16F627A/628A/648A
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F627A
0410017
18-Lead SOIC (.300”)
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC16F628A
-E/SO
0410017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC16F648A
-I/SS
0410017
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
16F628A
-I/ML
0410017
3 e
3 e
3 e
3 e
-I/P
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
PIC16F627A/628A/648A
DS40044G-page 164 © 2009 Microchip Technology Inc.
18-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units ÌNCHES
Dimension Limits MÌN NOM MAX
Number of Pins N 18
Pitch e .100 BSC
Top to Seating Plane A ÷ ÷ .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 ÷ ÷
Shoulder to Shoulder Width E .300 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .880 .900 .920
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .014
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB ÷ ÷ .430
NOTE 1
N
E1
D
1 2 3
A
A1
A2
L
E
eB
c
e
b1
b
Microchip Technology Drawing C04-007B
© 2009 Microchip Technology Inc. DS40044G-page 165
PIC16F627A/628A/648A
18-Lead PIastic SmaII OutIine (SO) - Wide, 7.50 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MÌLLÌMETERS
Dimension Limits MÌN NOM MAX
Number of Pins N 18
Pitch e 1.27 BSC
Overall Height A ÷ ÷ 2.65
Molded Package Thickness A2 2.05 ÷ ÷
Standoff § A1 0.10 ÷ 0.30
Overall Width E 10.30 BSC
Molded Package Width E1 7.50 BSC
Overall Length D 11.55 BSC
Chamfer (optional) h 0.25 ÷ 0.75
Foot Length L 0.40 ÷ 1.27
Footprint L1 1.40 REF
Foot Angle I 0° ÷ 8°
Lead Thickness c 0.20 ÷ 0.33
Lead Width b 0.31 ÷ 0.51
Mold Draft Angle Top D 5° ÷ 15°
Mold Draft Angle Bottom E 5° ÷ 15°
NOTE 1
D
N
E
E1
e
b
1 2 3
A
A1
A2
L
L1
h
h
c
β
φ
α
Microchip Technology Drawing C04-051B
PIC16F627A/628A/648A
DS40044G-page 166 © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. DS40044G-page 167
PIC16F627A/628A/648A
20-Lead PIastic Shrink SmaII OutIine (SS) - 5.30 mm Body [SSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MÌLLÌMETERS
Dimension Limits MÌN NOM MAX
Number of Pins N 20
Pitch e 0.65 BSC
Overall Height A ÷ ÷ 2.00
Molded Package Thickness A2 1.65 1.75 1.85
Standoff A1 0.05 ÷ ÷
Overall Width E 7.40 7.80 8.20
Molded Package Width E1 5.00 5.30 5.60
Overall Length D 6.90 7.20 7.50
Foot Length L 0.55 0.75 0.95
Footprint L1 1.25 REF
Lead Thickness c 0.09 ÷ 0.25
Foot Angle I 0° 4° 8°
Lead Width b 0.22 ÷ 0.38
φ
L L1
A2
c
e
b
A1
A
1 2
NOTE 1
E1
E
D
N
Microchip Technology Drawing C04-072B
PIC16F627A/628A/648A
DS40044G-page 168 © 2009 Microchip Technology Inc.
28-Lead PIastic Quad FIat, No Lead Package (ML) - 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MÌLLÌMETERS
Dimension Limits MÌN NOM MAX
Number of Pins N 28
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Width E 6.00 BSC
Exposed Pad Width E2 3.65 3.70 4.20
Overall Length D 6.00 BSC
Exposed Pad Length D2 3.65 3.70 4.20
Contact Width b 0.23 0.30 0.35
Contact Length L 0.50 0.55 0.70
Contact-to-Exposed Pad K 0.20 ÷ ÷
D
EXPOSED
D2
e
b
K
E2
E
L
N
NOTE 1
1
2
2
1
N
A
A1
A3
TOP VIEW BOTTOM VIEW
PAD
Microchip Technology Drawing C04-105B
© 2009 Microchip Technology Inc. DS40044G-page 169
PIC16F627A/628A/648A
28-Lead PIastic Quad FIat, No Lead Package (ML) - 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F627A/628A/648A
DS40044G-page 170 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS40044G-page 171
PIC16F627A/628A/648A
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
Revision B
Revised 28-Pin QFN Pin Diagram
Revised Figure 5-4 Block Diagram
Revised Register 7-1 TMR1ON
Revised Example 13-4 Data EEPROM Refresh Routine
Revised Instruction Set SUBWF, Example 1
Revised DC Characteristics 17-2 and 17-3
Revised Tables 17-4 and 17-6
Corrected Table and Figure numbering in Section 17.0
Revision C
General revisions throughout. Revisions to Section
14.0 – Special Features of the CPU. Section 18,
modified graphs.
Revision D
Revise Example 13-2, Data EEPROM Write
Revise Sections 17.2, Param No. D020 and 17.3,
Param No. D020E
Revise Section 18.0 graphs
Revision E
Section 19.0 Packaging Information: Replaced
package drawings and added note.
Revision F (03/2007)
Replaced Package Drawings (Rev. AM); Replaced
Development Support Section; Revised Product ID
System.
Revision G (10/2009)
Corrected 28-lead QFN Package in Section 19.1.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC16F627A/628A/648A
devices listed in this data sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Device
Memory
Flash
Program
RAM
Data
EEPROM
Data
PIC16F627A 1024 x 14 224 x 8 128 x 8
PIC16F628A 2048 x 14 224 x 8 128 x 8
PIC16F648A 4096 x 14 256 x 8 256 x 8
PIC16F627A/628A/648A
DS40044G-page 172 © 2009 Microchip Technology Inc.
APPENDIX C: DEVICE MIGRATIONS
This section describes the functional and electrical
specification differences when migrating between
functionally similar devices. (such as from a
PIC16F627 to a PIC16F627A).
C.1 PIC16F627/628 to a PIC16F627A/
628A
1. ER mode is now RC mode.
2. Code protection for the program memory has
changed from code-protect sections of memory
to code-protect of the whole memory. The
configuration bits CP0 and CP1 in the
PIC16F627/628 do not exist in the PIC16F627A/
628A. They have been replaced with one
configuration bit<13> CP.
3. “Brown-out Detect (BOD)” terminology has
changed to “Brown-out Reset (BOR)” to better
represent the function of the Brown-out circuitry.
4. Enabling Brown-out Reset (BOR) does not
automatically enable the Power-up Timer
(PWRT) the way it did in the PIC16F627/628.
5. INTRC is now called INTOSC.
6. Timer1 Oscillator is now designed for
32.768 kHz operation. In the PIC16F627/628,
the Timer1 oscillator was designed to run up to
200 kHz.
7. The Dual-Speed Oscillator mode only works in
the INTOSC oscillator mode. In the PIC16F627/
628, the Dual-Speed Oscillator mode worked in
both the INTRC and ER oscillator modes.
APPENDIX D: MIGRATING FROM
OTHER PIC
®

DEVICES
This discusses some of the issues in migrating from
other PIC MCU devices to the PIC16F627A/628A/
648A family of devices.
D.1 PIC16C62X/CE62X to PIC16F627A/
628A/648A Migration
See Microchip web site for availability
(www.microchip.com).
D.2 PIC16C622A to PIC16F627A/628A/
648A Migration
See Microchip web site for availability
(www.microchip.com).
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
© 2009 Microchip Technology Inc. DS40044G-page 173
PIC16F627A/628A/648A
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
PIC16F627A/628A/648A
DS40044G-page 174 © 2009 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS40044G PIC16F627A/628A/648A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2009 Microchip Technology Inc. DS40044G-page 175
PIC16F627A/628A/648A
INDEX
A
A/D
Special Event Trigger (CCP)....................................... 59
Absolute Maximum Ratings .............................................. 135
ADDLW Instruction ........................................................... 119
ADDWF Instruction ........................................................... 119
ANDLW Instruction ........................................................... 119
ANDWF Instruction ........................................................... 119
Architectural Overview........................................................ 11
Assembler
MPASM Assembler................................................... 132
B
Baud Rate Error .................................................................. 75
Baud Rate Formula............................................................. 75
BCF Instruction ................................................................. 120
Block Diagrams
Comparator
I/O Operating Modes .......................................... 64
Modified Comparator Output .............................. 66
I/O Ports
RB0/INT Pin........................................................ 38
RB1/RX/DT Pin................................................... 39
RB2/TX/CK Pin ................................................... 39
RB3/CCP1 Pin .................................................... 40
RB4/PGM Pin ..................................................... 41
RB5 Pin............................................................... 42
RB6/T1OSO/T1CKI Pin ...................................... 43
RB7/T1OSI Pin ................................................... 44
RC Oscillator Mode................................................... 101
USART Receive.......................................................... 82
USART Transmit ......................................................... 80
BRGH bit ............................................................................. 75
Brown-Out Reset (BOR) ................................................... 103
BSF Instruction ................................................................. 120
BTFSC Instruction............................................................. 120
BTFSS Instruction............................................................. 121
C
C Compilers
MPLAB C18 .............................................................. 132
CALL Instruction ............................................................... 121
Capture (CCP Module) ....................................................... 58
Block Diagram............................................................. 58
CCP Pin Configuration................................................ 58
CCPR1H:CCPR1L Registers...................................... 58
Changing Between Capture Prescalers...................... 58
Prescaler..................................................................... 58
Software Interrupt ....................................................... 58
Timer1 Mode Selection............................................... 58
Capture/Compare/PWM (CCP)........................................... 57
Capture Mode. See Capture
CCP1 .......................................................................... 57
CCPR1H Register............................................... 57
CCPR1L Register ............................................... 57
CCP2 .......................................................................... 57
Compare Mode. See Compare
PWM Mode. See PWM
Timer Resources......................................................... 57
CCP1CON Register ............................................................ 57
CCP1M Bits ................................................................ 57
CCP1X:CCP1Y Bits.................................................... 57
CCP2CON Register
CCP2M<3:2> Bits ....................................................... 57
CCP2X:CCP2Y Bits.................................................... 57
Clocking Scheme/Instruction Cycle .................................... 15
CLRF Instruction............................................................... 121
CLRW Instruction.............................................................. 122
CLRWDT Instruction......................................................... 122
CMCON Register................................................................ 63
Code Examples
Data EEPROM Refresh Routine ................................ 94
Code Protection................................................................ 113
COMF Instruction.............................................................. 122
Comparator
Block Diagrams
I/O Operating Modes .......................................... 64
Modified Comparator Output .............................. 66
Comparator Module.................................................... 63
Configuration .............................................................. 64
Interrupts .................................................................... 67
Operation.................................................................... 65
Reference................................................................... 65
Compare (CCP Module) ..................................................... 58
Block Diagram............................................................ 58
CCP Pin Configuration ............................................... 59
CCPR1H:CCPR1L Registers ..................................... 58
Software Interrupt ....................................................... 59
Special Event Trigger ................................................. 59
Timer1 Mode Selection............................................... 59
CONFIG Register ............................................................... 98
Configuration Bits ............................................................... 97
Crystal Operation................................................................ 99
Customer Change Notification Service............................. 173
Customer Notification Service .......................................... 173
Customer Support............................................................. 173
D
Data EEPROM Memory...................................................... 91
EECON1 Register ...................................................... 91
EECON2 Register ...................................................... 91
Operation During Code Protection ............................. 95
Reading ...................................................................... 93
Spurious Write Protection........................................... 93
Using .......................................................................... 94
Write Verify ................................................................. 93
Writing to .................................................................... 93
Data Memory Organization................................................. 17
DECF Instruction .............................................................. 122
DECFSZ Instruction.......................................................... 123
Development Support ....................................................... 131
Device Differences............................................................ 171
Device Migrations ............................................................. 172
Dual-speed Oscillator Modes............................................ 101
E
EECON1 Register............................................................... 92
EECON1 register ................................................................ 92
EECON2 register ................................................................ 92
Errata.................................................................................... 5
External Crystal Oscillator Circuit ..................................... 100
F
Fuses. See Configuration Bits
G
General-Purpose Register File ........................................... 17
GOTO Instruction.............................................................. 123
PIC16F627A/628A/648A
DS40044G-page 176 © 2009 Microchip Technology Inc.
I
I/O Ports.............................................................................. 33
Bidirectional ................................................................ 46
Block Diagrams
RB0/INT Pin........................................................ 38
RB1/RX/DT Pin................................................... 39
RB2/TX/CK Pin ................................................... 39
RB3/CCP1 Pin .................................................... 40
RB4/PGM Pin...................................................... 41
RB5 Pin............................................................... 42
RB6/T1OSO/T1CKI Pin ...................................... 43
RB7/T1OSI Pin ................................................... 44
PORTA........................................................................ 33
PORTB........................................................................ 38
Programming Considerations ..................................... 46
Successive Operations ............................................... 46
TRISA ......................................................................... 33
TRISB ......................................................................... 38
ID Locations ...................................................................... 113
INCF Instruction ................................................................ 124
INCFSZ Instruction............................................................ 124
In-Circuit Serial Programming™....................................... 114
Indirect Addressing, INDF and FSR Registers.................... 30
Instruction Flow/Pipelining .................................................. 15
Instruction Set
ADDLW..................................................................... 119
ADDWF..................................................................... 119
ANDLW..................................................................... 119
ANDWF..................................................................... 119
BCF........................................................................... 120
BSF........................................................................... 120
BTFSC ...................................................................... 120
BTFSS ...................................................................... 121
CALL ......................................................................... 121
CLRF......................................................................... 121
CLRW ....................................................................... 122
CLRWDT................................................................... 122
COMF ....................................................................... 122
DECF ........................................................................ 122
DECFSZ.................................................................... 123
GOTO ....................................................................... 123
INCF.......................................................................... 124
INCFSZ..................................................................... 124
IORLW...................................................................... 125
IORWF...................................................................... 125
MOVF........................................................................ 125
MOVLW .................................................................... 125
MOVWF .................................................................... 126
NOP .......................................................................... 126
OPTION .................................................................... 126
RETFIE ..................................................................... 126
RETLW ..................................................................... 127
RETURN................................................................... 127
RLF ........................................................................... 127
RRF........................................................................... 128
SLEEP ...................................................................... 128
SUBLW..................................................................... 128
SUBWF..................................................................... 129
SWAPF ..................................................................... 129
TRIS.......................................................................... 129
XORLW..................................................................... 130
XORWF..................................................................... 130
Instruction Set Summary................................................... 117
INT Interrupt ...................................................................... 110
INTCON Register ................................................................ 26
Internet Address ............................................................... 173
Interrupt Sources
Capture Complete (CCP)............................................ 58
Compare Complete (CCP).......................................... 59
TMR2 to PR2 Match (PWM) ....................................... 60
Interrupts........................................................................... 109
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ........................................ 58
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit)............................................. 58
IORLW Instruction ............................................................ 125
IORWF Instruction ............................................................ 125
M
Memory Organization
Data EEPROM Memory.................................. 91, 93, 95
Microchip Internet Web Site.............................................. 173
Migrating from other PICmicro Devices ............................ 172
MOVF Instruction.............................................................. 125
MOVLW Instruction........................................................... 125
MOVWF Instruction .......................................................... 126
MPLAB ASM30 Assembler, Linker, Librarian................... 132
MPLAB Integrated Development Environment Software.. 131
MPLAB PM3 Device Programmer .................................... 134
MPLAB REAL ICE In-Circuit Emulator System ................ 133
MPLINK Object Linker/MPLIB Object Librarian................ 132
N
NOP Instruction ................................................................ 126
O
OPTION Instruction .......................................................... 126
OPTION Register................................................................ 25
OPTION_REG Register...................................................... 25
Oscillator Configurations..................................................... 99
Oscillator Start-up Timer (OST) ........................................ 103
P
Package Marking Information........................................... 163
Packaging Information...................................................... 163
PCL and PCLATH............................................................... 30
Stack........................................................................... 30
PCON Register ................................................................... 29
PIE1 Register...................................................................... 27
Pin Functions
RC6/TX/CK........................................................... 73–89
RC7/RX/DT........................................................... 73–89
PIR1 Register ..................................................................... 28
PORTA ............................................................................... 33
PORTB ............................................................................... 38
PORTB Interrupt ............................................................... 110
Power Control/Status Register (PCON)............................ 104
Power-Down Mode (Sleep)............................................... 112
Power-On Reset (POR) .................................................... 103
Power-up Timer (PWRT) .................................................. 103
PR2 Register ................................................................ 54, 60
Program Memory Organization........................................... 17
PWM (CCP Module) ........................................................... 60
Block Diagram............................................................ 60
Simplified PWM.................................................. 60
CCPR1H:CCPR1L Registers...................................... 60
Duty Cycle .................................................................. 61
Example Frequencies/Resolutions ............................. 61
Period ......................................................................... 60
Set-Up for PWM Operation......................................... 61
TMR2 to PR2 Match ................................................... 60
© 2009 Microchip Technology Inc. DS40044G-page 177
PIC16F627A/628A/648A
Q
Q-Clock ............................................................................... 61
Quick-Turnaround-Production (QTP) Devices ...................... 9
R
RC Oscillator ..................................................................... 101
RC Oscillator Mode
Block Diagram........................................................... 101
Reader Response............................................................. 174
Registers
CCP1CON (CCP Operation)....................................... 57
CMCON (Comparator Configuration).......................... 63
CONFIG (Configuration Word).................................... 98
EECON1 (EEPROM Control Register 1) .................... 92
INTCON (Interrupt Control)......................................... 26
Maps
PIC16F627A ................................................. 18, 19
PIC16F628A ................................................. 18, 19
OPTION_REG (Option) .............................................. 25
PCON (Power Control) ............................................... 29
PIE1 (Peripheral Interrupt Enable 1)........................... 27
PIR1 (Peripheral Interrupt Register 1) ........................ 28
Status.......................................................................... 24
T1CON Timer1 Control).............................................. 50
T2CON Timer2 Control).............................................. 55
Reset................................................................................. 101
RETFIE Instruction............................................................ 126
RETLW Instruction............................................................ 127
RETURN Instruction ......................................................... 127
Revision History ................................................................ 171
RLF Instruction.................................................................. 127
RRF Instruction................................................................. 128
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Production (SQTP) Devices... 9
SLEEP Instruction............................................................. 128
Software Simulator (MPLAB SIM)..................................... 133
Special Event Trigger. See Compare
Special Features of the CPU .............................................. 97
Special Function Registers ................................................. 20
Status Register ................................................................... 24
SUBLW Instruction............................................................ 128
SUBWF Instruction ........................................................... 129
SWAPF Instruction............................................................ 129
T
T1CKPS0 bit ....................................................................... 50
T1CKPS1 bit ....................................................................... 50
T1CON Register ................................................................. 50
T1OSCEN bit ...................................................................... 50
T2CKPS0 bit ....................................................................... 55
T2CKPS1 bit ....................................................................... 55
T2CON Register ................................................................. 55
Timer0
Block Diagrams
Timer0/WDT ....................................................... 48
External Clock Input .................................................... 47
Interrupt....................................................................... 47
Prescaler..................................................................... 48
Switching Prescaler Assignment................................. 49
Timer0 Module............................................................ 47
Timer1
Asynchronous Counter Mode ..................................... 52
Capacitor Selection..................................................... 53
External Clock Input ................................................... 51
External Clock Input Timing........................................ 52
Oscillator..................................................................... 53
Prescaler .............................................................. 51, 53
Resetting Timer1 ........................................................ 53
Resetting Timer1 Registers ........................................ 53
Special Event Trigger (CCP) ...................................... 59
Synchronized Counter Mode...................................... 51
Timer Mode ................................................................ 51
TMR1H....................................................................... 52
TMR1L........................................................................ 52
Timer2
Block Diagram............................................................ 54
Postscaler................................................................... 54
PR2 register................................................................ 54
Prescaler .............................................................. 54, 61
Timer2 Module............................................................ 54
TMR2 output ............................................................... 54
TMR2 to PR2 Match Interrupt..................................... 60
Timing Diagrams
Timer0 ...................................................................... 147
Timer1 ...................................................................... 147
USART
Asynchronous Receiver...................................... 83
USART Asynchronous Master Transmission ............. 80
USART Asynchronous Reception .............................. 83
USART Synchronous Reception ................................ 89
USART Synchronous Transmission........................... 87
Timing Diagrams and Specifications ................................ 144
TMR0 Interrupt.................................................................. 110
TMR1CS bit ........................................................................ 50
TMR1ON bit........................................................................ 50
TMR2ON bit........................................................................ 55
TOUTPS0 bit ...................................................................... 55
TOUTPS1 bit ...................................................................... 55
TOUTPS2 bit ...................................................................... 55
TOUTPS3 bit ...................................................................... 55
TRIS Instruction................................................................ 129
TRISA................................................................................. 33
TRISB................................................................................. 38
U
Universal Synchronous Asynchronous Receiver Transmitter
(USART) ..................................................................... 73
Asynchronous Receiver
Setting Up Reception.......................................... 85
Asynchronous Receiver Mode
Address Detect ................................................... 85
Block Diagram.................................................... 85
USART
Asynchronous Mode................................................... 79
Asynchronous Receiver.............................................. 82
Asynchronous Reception............................................ 84
Asynchronous Transmission ...................................... 80
Asynchronous Transmitter.......................................... 79
Baud Rate Generator (BRG) ...................................... 75
Block Diagrams
Transmit.............................................................. 80
USART Receive ................................................. 82
BRGH bit .................................................................... 75
Sampling......................................................... 76, 77, 78
Synchronous Master Mode......................................... 86
Synchronous Master Reception ................................. 88
Synchronous Master Transmission ............................ 86
Synchronous Slave Mode........................................... 89
Synchronous Slave Reception ................................... 90
PIC16F627A/628A/648A
DS40044G-page 178 © 2009 Microchip Technology Inc.
Synchronous Slave Transmit ...................................... 89
V
Voltage Reference
Configuration............................................................... 69
Voltage Reference Module ......................................... 69
W
Watchdog Timer (WDT) .................................................... 111
WWW Address.................................................................. 173
WWW, On-Line Support........................................................ 5
X
XORLW Instruction ........................................................... 130
XORWF Instruction ........................................................... 130
© 2009 Microchip Technology Inc. DS40044G-page 179
PIC16F627A/628A/648A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Pattern Package Temperature
Range
Device

Device: PIC16F627A/628A/648A:Standard VDD range 3.0V to
5.5V
PIC16F627A/628A/648AT:VDD range 3.0V to 5.5V
(Tape and Reel)
PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V
PIC16LF627A/628A/648AT:VDD range 2.0V to 5.5V
(Tape and Reel)
Temperature
Range:
I = -40°C to +85°C
E = -40°C to+125°C
Package: P = PDIP
SO = SOIC (Gull Wing, 7.50 mm body)
SS = SSOP (5.30 mm
ML = QFN (28 Lead)
Examples:
a) PIC16F627A - E/P 301 = Extended
Temp.,
PDIP package, 20 MHz, normal VDD lim-
its, QTP pattern #301.
b) PIC16LF627A - I/SO = Industrial Temp.,
SOIC package, 20 MHz, extended VDD
limits.
DS40044G-page 180 © 2009 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
03/26/09

Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

• •

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS40044G-page 2

© 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
18-pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
• • • • • Operating speeds from DC – 20 MHz Interrupt capability 8-level deep hardware stack Direct, Indirect and Relative Addressing modes 35 single-word instructions: - All instructions single cycle except branches

Low-Power Features:
• Standby Current: - 100 nA @ 2.0V, typical • Operating Current: - 12 μA @ 32 kHz, 2.0V, typical - 120 μA @ 1 MHz, 2.0V, typical • Watchdog Timer Current: - 1 μA @ 2.0V, typical • Timer1 Oscillator Current: - 1.2 μA @ 32 kHz, 2.0V, typical • Dual-speed Internal Oscillator: - Run-time selectable between 4 MHz and 48 kHz - 4 μs wake-up from Sleep, 3.0V, typical

Special Microcontroller Features:
• Internal and external oscillator options: - Precision internal 4 MHz oscillator factory calibrated to ±1% - Low-power internal 48 kHz oscillator - External Oscillator support for crystals and resonators • Power-saving Sleep mode • Programmable weak pull-ups on PORTB • Multiplexed Master Clear/Input-pin • Watchdog Timer with independent oscillator for reliable operation • Low-voltage programming • In-Circuit Serial Programming™ (via two pins) • Programmable code protection • Brown-out Reset • Power-on Reset • Power-up Timer and Oscillator Start-up Timer • Wide operating voltage range (2.0-5.5V) • Industrial and extended temperature range • High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - 40 year data retention

Peripheral Features:
• 16 I/O pins with individual direction control • High current sink/source for direct LED drive • Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Selectable internal or external reference - Comparator outputs are externally accessible • Timer0: 8-bit timer/counter with 8-bit programmable prescaler • Timer1: 16-bit timer/counter with external crystal/ clock capability • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM module: - 16-bit Capture/Compare - 10-bit PWM • Addressable Universal Synchronous/Asynchronous Receiver/Transmitter USART/SCI

Device

Program Memory Flash (words) 1024 2048 4096

Data Memory SRAM (bytes) 224 224 256 EEPROM (bytes) 128 128 256 I/O

CCP (PWM) 1 1 1

USART Comparators

Timers 8/16-bit 2/1 2/1 2/1

PIC16F627A PIC16F628A PIC16F648A

16 16 16

Y Y Y

2 2 2

© 2009 Microchip Technology Inc.

DS40044G-page 3

PIC16F627A/628A/648A Pin Diagrams PDIP. . SOIC RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP VSS RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 1 PIC16F627A/628A/648A 2 3 4 5 6 7 8 9 27A/628A/648A 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC RB5 RB4/PGM RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC RB5 RB4/PGM SSOP 28-Pin QFN RA4/T0CKI/CMP2 RA3/AN3/CMP1 RA2/AN2/VREF RA5/MCLR/VPP PIC16F627A/628A/648A RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP VSS VSS RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB1/RX/DT RB2/TX/CK RB3/CCP1 8 9 10 NC 11 12 RB4/PGM 13 RB5 NC 14 1 21 NC 2 20 VSS 3 19 NC 4 PIC16F627A/628A 18 NC PIC16F648A VSS 17 5 NC 6 16 RB0/INT 7 15 28 27 26 25 NC 24 23 22 NC 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC 1 2 3 4 5 6 7 8 9 10 DS40044G-page 4 © 2009 Microchip Technology Inc.

............................................................................................................................................................................0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module................................................................................. 97 15................................. Our publications will be refined and enhanced as new volumes and updates are introduced................... DS40044G-page 5 . please register at our Worldwide Web site at: http://www.................. 172 The Microchip Web Site ............................................................................. please contact the Marketing Communications Department via E-mail at docerrors@microchip.................microchip...................................... 50 8. please check with one of the following: • Microchip’s Worldwide Web site............ 11 4......................................0 Instruction Set Summary.. http://www............................................................................................................................................................................................... revision of silicon and data sheet (include literature number) you are using...........................microchip................... 173 Customer Change Notification Service .......... describing minor operational differences from the data sheet and recommended workarounds.......................................PIC16F627A/628A/648A Table of Contents 1................................. 171 Appendix C: Device Migrations ........................................................................................................................................................0 Memory Organization ............................................. 91 14........... To determine if an errata sheet exists for a particular device........................................................................................... Errata An errata sheet...........................................................................................................................................................com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150...................... Most Current Data Sheet To obtain the most up-to-date version of this data sheet.............. 179 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products..........................................................................................................................................................................................................................0 Packaging Information ........................................................................0 DC and AC Characteristics Graphs and Tables ...................................................0 Special Features of the CPU ................................................................................. 163 Appendix A: Data Sheet Revision History.............. 57 10........................................... If you have any questions or comments regarding this publication..........................0 PIC16F627A/628A/648A Device Varieties...................0 Voltage Reference Module ..............................0 I/O Ports .....................................................................................................0 Timer0 Module .......... 171 Appendix B: Device Differences .........................................................................................................................................0 Capture/Compare/PWM (CCP) Module ............................................................ As device/documentation issues become known to us....................................microchip......................................................................... 69 12......................................................................................................................................................................................................................................................................................0 Data EEPROM Memory ......................................0 Timer1 Module ............................................................................................................................ To this end.................................................................................... © 2009 Microchip Technology Inc................................... 173 Reader Response ..................................... 47 7....................................................................com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page........................ 33 6............... We welcome your feedback.................................................................................................................. 17 5....................................... DS30000A is version A of document DS30000)............0 General Description ............. 7 2............ 117 16..................................................com • Your local Microchip sales office (see last page) When contacting a sales office................0 Electrical Specifications ................................... please specify which device................................................................ 9 3.........0 Architectural Overview .........................0 Timer2 Module .................................................0 Development Support ........................... may exist for current devices.................................................................................................0 Comparator Module .............. 54 9............... 135 18............................................................................ 63 11.................................................. (e...................................... 151 19......... The last character of the literature number is the version number.................................................................................................................................................................................................g..................................... 173 Customer Support ............................................................................................................... 73 13.................. 172 Appendix D: Migrating from other PIC® Devices ............... 131 17.............................................. Customer Notification System Register on our web site at www................................................ we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies............................... we will continue to improve our publications to better suit your needs.................................... 174 Product Identification System ...........com to receive the most current information on all of our products.......................................

.PIC16F627A/628A/648A NOTES: DS40044G-page 6 © 2009 Microchip Technology Inc.

complemented by a large register set. TMR1. SOIC. © 2009 Microchip Technology Inc. The HS mode is for High-Speed crystals. SOIC. except for program branches (which require two cycles). internal interrupts and Resets. etc.5 Yes 18-pin DIP. The PIC16F627A/628A/648A has 8 oscillator configurations.5 Yes 18-pin DIP. a low cost development programmer and a full-featured programmer. Low cost. The single-pin RC oscillator provides a low-cost solution. fullystatic. TMR2 2 1 USART Yes 10 16 2. TMR1. A total of 35 instructions (reduced instruction set) are available. 28-pin QFN PIC16LF648A 20 4096 256 256 TMR0. The PIC16F627A/628A/648A series fits in applications ranging from battery chargers to low power remote sensors. A Third Party “C” compiler support tool is also available. TABLE 1-1: Clock PIC16F627A/628A/648A FAMILY OF DEVICES PIC16F627A PIC16F628A 20 2048 224 128 TMR0.) extremely fast and convenient. All PIC® microcontrollers employ an advanced RISC architecture. TMR2 2 1 USART Yes 10 16 3. The EC mode is for an external clock source. TMR1. timers. and INTOSC is a self-contained precision two-speed internal oscillator.0 GENERAL DESCRIPTION The PIC16F627A/628A/648A are 18-pin Flash-based members of the versatile PIC16F627A/628A/648A family of low-cost. 20-pin SSOP. low power. an in-circuit emulator. 20-pin SSOP. and multiple internal and external interrupt sources. an eight-level deep stack. 20-pin SSOP. high performance. TMR2 2 1 USART Yes 10 16 3. 28-pin QFN PIC16F648A 20 4096 256 256 TMR0. XT is a standard crystal. TMR1. pulse generation. 28-pin QFN Maximum Frequency of Operation (MHz) Flash Program Memory (words) Memory RAM Data Memory (bytes) EEPROM Data Memory (bytes) Timer module(s) Comparator(s) Peripherals Capture/Compare/ PWM modules Serial Communications Internal Voltage Reference Interrupt Sources I/O Pins Features Voltage Range (Volts) Brown-out Reset Packages All PIC® family devices have Power-on Reset. a software simulator.0-5. TMR1.0-5. SOIC. The small footprint packages makes this microcontroller series ideal for all applications with space limitations. 28-pin QFN PIC16LF628A 20 2048 224 128 TMR0. selectable code-protect and high I/O current capability. enhancing system reliability and reducing power consumption. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a singlecycle. The Sleep (Power-down) mode offers power savings. A simplified block diagram of the PIC16F627A/628A/ 648A is shown in Figure 3-1. All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7. thus reducing system cost. 28-pin QFN PIC16LF627A 20 1024 224 128 TMR0.0-5. SOIC. TMR2 2 1 USART Yes 10 16 3. The Flash technology makes customizing application programs (detection levels.PIC16F627A/628A/648A 1. SOIC. 28-pin QFN 20 1024 224 128 TMR0. PIC16F627A/628A/648A devices have integrated features to reduce external components. Users can wake-up the chip from Sleep through several external interrupts.1 Development Support The PIC16F627A/628A/648A family is supported by a full-featured macro assembler. 20-pin SSOP. 20-pin SSOP.0-5.0-5. The PIC16F627A/628A/648A have enhanced core features.5 Yes 18-pin DIP. 8-bit microcontrollers. selectable Watchdog Timer. TMR2 2 1 USART Yes 10 16 2. PIC16F627A/628A/648A microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. TMR2 2 1 USART Yes 10 16 2.5 Yes 18-pin DIP.0-5.5 Yes 18-pin DIP. TMR1. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. DS40044G-page 7 . 1. The LP oscillator minimizes power consumption. 20-pin SSOP. a low cost in-circuit debugger. CMOS. Table 1-1 shows the features of the PIC16F627A/628A/ 648A mid-range microcontroller family.5 Yes 18-pin DIP. ease of use and I/O flexibility make the PIC16F627A/628A/648A very versatile. SOIC. high-performance.

PIC16F627A/628A/648A NOTES: DS40044G-page 8 © 2009 Microchip Technology Inc. .

the proper device option can be selected using the information in the PIC16F627A/628A/648A Product Identification System. The devices are standard Flash devices. such as Microchip’s PICSTART® Plus or PRO MATE® II programmers. Serial programming allows each device to have a unique number.PIC16F627A/628A/648A 2. pilot programs and production. This allows the same device to be used for prototype development. DS40044G-page 9 . or by device programmers. When placing orders. This service is made available for users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. but with all program locations and configuration options already programmed by the factory. © 2009 Microchip Technology Inc.0 PIC16F627A/628A/648A DEVICE VARIETIES A variety of frequency ranges and packaging options are available. 2. which can serve as an entry-code. Certain code and prototype verification procedures apply before production shipments are available. The serial numbers may be random. A further advantage of the electrically erasable Flash is that it can be erased and reprogrammed in-circuit.3 Serialized Quick-TurnaroundProduction (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. 2. Depending on application and production requirements. at the end of this data sheet. password or ID number.1 Flash Devices Flash devices can be erased and re-programmed electrically. Please contact your Microchip Technology sales office for more details. please use this page of the data sheet to specify the correct part number. 2.2 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. pseudo-random or sequential.

PIC16F627A/628A/648A NOTES: DS40044G-page 10 © 2009 Microchip Technology Inc. .

Two types of data memory are provided on the PIC16F627A/628A/648A devices. Nonvolatile EEPROM data memory is provided for long term storage of data. and a description of the device pins in Table 3-2. Table 3-1 lists device memory sizes (Flash. shift and logical operations. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. The ALU is 8-bits wide and capable of addition. In single operand instructions. The PIC16F627A/628A/648A devices contain an 8-bit ALU and working register. See the SUBLW and SUBWF instructions for examples. These data types are not lost when power is removed. respectively. look-up table data. the operand is either the W register or a file register. Digit Carry (DC). This symmetrical nature and lack of ‘special optimal situations’ makes programming with the PIC16F627A/628A/648A simple yet efficient. TABLE 3-1: Device PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A DEVICE MEMORY LIST Memory Flash Program 1024 x 14 2048 x 14 4096 x 14 1024 x 14 2048 x 14 4096 x 14 RAM Data 224 x 8 224 x 8 256 x 8 224 x 8 224 x 8 256 x 8 EEPROM Data 128 x 8 128 x 8 256 x 8 128 x 8 128 x 8 256 x 8 © 2009 Microchip Technology Inc. To begin with. Regular RAM data memory is provided for temporary storage of data during normal operation. DS40044G-page 11 . the ALU may affect the values of the Carry (C). and Zero (Z) bits in the Status Register.PIC16F627A/628A/648A 3. subtraction. Consequently. A simplified block diagram is shown in Figure 3-1. typically one operand is the working register (W register). using any addressing mode. In two-operand instructions. It is not an addressable register. and any other data which may require periodic updating in the field. including the program counter. all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program branches. Data is lost when power is removed. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. The other operand is a file register or an immediate constant. Data and EEPROM). Depending on the instruction executed. In addition. The W register is an 8-bit working register used for ALU operations. The ALU is a general purpose arithmetic unit. The PIC16F627A/628A/648A have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation. such as calibration values. The PIC16F627A/628A/648A can directly or indirectly address its register files or data memory. the learning curve is reduced significantly. The C and DC bits operate as Borrow and Digit Borrow out bits. The other data memory provided is regular RAM data memory. on any register. Instruction opcodes are 14-bits wide making it possible to have all single-word instructions. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory. are mapped in the data memory. All Special Function Registers (SFR). A two-stage pipeline overlaps fetch and execution of instructions. the PIC16F627A/628A/648A uses a Harvard architecture in which program and data are accessed from separate memories using separate busses.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F627A/628A/648A family can be attributed to a number of architectural features commonly found in RISC microprocessors. Unless otherwise mentioned. in subtraction. arithmetic operations are two’s complement in nature. It performs arithmetic and Boolean functions between data in the working register and any register file.

VSS Comparator Timer0 Timer1 Timer2 VREF CCP1 USART Data EEPROM Note 1: Higher order bits are from the Status register. . DS40044G-page 12 © 2009 Microchip Technology Inc.PIC16F627A/628A/648A FIGURE 3-1: BLOCK DIAGRAM 13 Flash Program Memory Program Counter Data Bus 8 8-Level Stack (13-bit) Program Bus 14 Instruction Reg Direct Addr 7 RAM File Registers RAM Addr (1) 9 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PORTB RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD Addr MUX 8 Indirect Addr FSR Reg 8 3 Status Reg Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Low-Voltage Programming 8 MUX ALU W Reg MCLR VDD.

Can be software programmed for internal weak pull-up. OSC2 pin can output CLKOUT. When configured as MCLR. DS40044G-page 13 . Voltage on MCLR/VPP must not exceed VDD during normal device operation. Bidirectional I/O port Oscillator crystal input External clock source input. this pin is an active low Reset to the device. Can be software programmed for internal weak pull-up. Can be software programmed for internal weak pull-up. Programming voltage input Bidirectional I/O port Oscillator crystal output. USART receive pin Synchronous data I/O Bidirectional I/O port.PIC16F627A/628A/648A TABLE 3-2: Name RA0/AN0 RA1/AN1 RA2/AN2/VREF PIC16F627A/628A/648A PINOUT DESCRIPTION Function RA0 AN0 RA1 AN1 RA2 AN2 VREF Input Type Output Type ST AN ST AN ST AN — ST AN — ST ST — ST ST CMOS — CMOS — CMOS — AN CMOS — CMOS OD — OD — — Description Bidirectional I/O port Analog comparator input Bidirectional I/O port Analog comparator input Bidirectional I/O port Analog comparator input VREF output Bidirectional I/O port Analog comparator input Comparator 1 output Bidirectional I/O port Timer0 clock input Comparator 2 output Input port Master clear. which has 1/4 the frequency of OSC1. In RC/INTOSC mode. Bidirectional I/O port. Can be software programmed for internal weak pull-up. RC biasing pin. External interrupt Bidirectional I/O port. Connects to crystal or resonator in Crystal Oscillator mode. Capture/Compare/PWM I/O P = Power ST = Schmitt Trigger Input AN = Analog RA3/AN3/CMP1 RA3 AN3 CMP1 RA4/T0CKI/CMP2 RA4 T0CKI CMP2 RA5/MCLR/VPP RA5 MCLR VPP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT — ST — — — CMOS XTAL CMOS RA7/OSC1/CLKIN RA7 OSC1 CLKIN ST XTAL ST TTL ST TTL ST ST TTL — ST TTL ST CMOS — — CMOS — CMOS — CMOS CMOS CMOS CMOS CMOS CMOS RB0/INT RB0 INT RB1/RX/DT RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 Legend: O = Output — = Not used TTL = TTL Input CMOS = CMOS Output I = Input OD = Open Drain Output © 2009 Microchip Technology Inc. USART transmit pin Synchronous clock I/O Bidirectional I/O port.

Timer1 oscillator input ICSP data I/O Ground reference for logic and I/O pins Positive supply for logic and I/O pins P = Power ST = Schmitt Trigger Input AN = Analog PGM ST — RB5 RB5 TTL CMOS RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS T1OSO T1CKI PGC RB7/T1OSI/PGD RB7 — ST ST TTL XTAL — — CMOS T1OSI PGD VSS VDD Legend: O = Output — = Not used TTL = TTL Input VSS VDD XTAL ST Power Power — CMOS — — CMOS = CMOS Output I = Input OD = Open Drain Output DS40044G-page 14 © 2009 Microchip Technology Inc. Timer1 oscillator output Timer1 clock input ICSP™ programming clock Bidirectional I/O port. Can be software programmed for internal weak pull-up. Can be software programmed for internal weak pull-up. Bidirectional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. the interrupt-on-pin change and weak pull-up resistor are disabled. Interrupt-on-pin change. Interrupt-on-pin change. Interrupt-on-pin change. Low-voltage programming input pin.PIC16F627A/628A/648A TABLE 3-2: Name RB4/PGM PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED) Function RB4 Input Type Output Type TTL CMOS Description Bidirectional I/O port. . Bidirectional I/O port. When low-voltage programming is enabled. Can be software programmed for internal weak pull-up.

PIC16F627A/628A/648A
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

The clock input (RA7/OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2.

FIGURE 3-2:
Q1 OSC1 Q1 Q2 Q3 Q4 PC CLKOUT

CLOCK/INSTRUCTION CYCLE
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Internal phase clock PC PC + 1 PC + 2

Fetch INST (PC) Execute INST (PC - 1)

Fetch INST (PC + 1) Execute INST (PC)

Fetch INST (PC + 2) Execute INST (PC + 1)

EXAMPLE 3-1:
1. MOVLW 55h 2. MOVWF PORTB 3. CALL 4. BSF SUB_1

INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1

PORTA, 3

Note:

All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

© 2009 Microchip Technology Inc.

DS40044G-page 15

PIC16F627A/628A/648A
NOTES:

DS40044G-page 16

© 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
4.0
4.1

MEMORY ORGANIZATION
Program Memory Organization

4.2

Data Memory Organization

The PIC16F627A/628A/648A has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC16F627A, 2K x 14 (0000h-07FFh) for the PIC16F628A and 4K x 14 (0000h-0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F627A), 2K x 14 space (PIC16F628A) or 4K x 14 space (PIC16F648A). The Reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1).

The data memory (Figure 4-2 and Figure 4-3) is partitioned into four banks, which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). The SFRs are located in the first 32 locations of each bank. There are General Purpose Registers implemented as static RAM in each bank. Table 4-1 lists the General Purpose Register available in each of the four banks.

TABLE 4-1:

GENERAL PURPOSE STATIC RAM REGISTERS
PIC16F627A/628A PIC16F648A 20-7Fh A0h-FF 120h-17Fh 1F0h-1FFh 20-7Fh A0h-FF

Bank0 Bank1 Bank2 Bank3

FIGURE 4-1:

PROGRAM MEMORY MAP AND STACK
PC<12:0> 13

120h-14Fh, 170h-17Fh 1F0h-1FFh

CALL, RETURN RETFIE, RETLW

Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h

Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are implemented as common RAM and mapped back to addresses 70h-7Fh. Table 4-2 lists how to access the four banks of registers via the Status register bits RP1 and RP0.

TABLE 4-2:
Bank 0 1 0004 0005 2 3

ACCESS TO BANKS OF REGISTERS
RP1 0 0 1 1 RP0 0 1 0 1

Interrupt Vector On-chip Program Memory PIC16F627A, PIC16F628A and PIC16F648A

4.2.1
03FFh

GENERAL PURPOSE REGISTER FILE

On-chip Program Memory PIC16F628A and PIC16F648A 07FFh On-chip Program Memory PIC16F648A only 0FFFh

The register file is organized as 224 x 8 in the PIC16F627A/628A and 256 x 8 in the PIC16F648A. Each is accessed either directly or indirectly through the File Select Register (FSR), See Section 4.4 “Indirect Addressing, INDF and FSR Registers”.

1FFFh

© 2009 Microchip Technology Inc.

DS40044G-page 17

Note 1: Not a physical register.(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 48 Bytes 11Fh 120h 14Fh 150h 16Fh 170h 17Fh Bank 2 1EFh 1F0h PCLATH INTCON PORTB Indirect addr. read as ‘0’. .(1) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh PCLATH INTCON TRISB Indirect addr.PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A File Address Indirect addr.(1) OPTION PCL STATUS FSR 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh accesses 70h-7Fh Bank 1 accesses 70h-7Fh accesses 70h-7Fh Bank 3 FFh 1FFh Unimplemented data memory locations. DS40044G-page 18 © 2009 Microchip Technology Inc.(1) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh CMCON General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 1Fh 20h General Purpose Register 80 Bytes EFh F0h VRCON TXSTA SPBRG EEDATA EEADR EECON1 EECON2(1) PR2 PCON PCLATH INTCON PIE1 Indirect addr.

© 2009 Microchip Technology Inc.(1) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes 16Fh 170h 17Fh Bank 2 1EFh 1F0h 11Fh 120h PCLATH INTCON PORTB Indirect addr. DS40044G-page 19 .PIC16F627A/628A/648A FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A File Address Indirect addr.(1) TMR0 PCL STATUS FSR 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh PCLATH INTCON TRISB Indirect addr. Note 1: Not a physical register.(1) OPTION PCL STATUS FSR 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh accesses 70h-7Fh Bank 1 accesses 70h-7Fh accesses 70h-7Fh Bank 3 FFh 1FFh Unimplemented data memory locations. read as ‘0’.(1) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh CMCON General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 1Fh 20h General Purpose Register 80 Bytes EFh F0h VRCON TXSTA SPBRG EEDATA EEADR EECON1 EECON2(1) PR2 PCON PCLATH INTCON PIE1 Indirect addr.

2. These registers are static RAM. q = value depends on condition.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-3). The special registers can be classified into two sets (core and peripheral). x = unknown. u = unchanged. The SFRs associated with the “core” functions are described in this section. DS40044G-page 20 © 2009 Microchip Technology Inc. . refer to Table 14-6 and Table 14-7.= Unimplemented locations read as ‘0’.PIC16F627A/628A/648A 4. shaded = unimplemented For the initialization condition for registers tables. Those related to the operation of the peripheral features are described in the section of that peripheral feature. TABLE 4-3: Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: INDF TMR0 PCL STATUS FSR PORTA PORTB — — — PCLATH INTCON PIR1 — TMR1L TMR1H T1CON TMR2 T2CON — — CCPR1L Name SPECIAL REGISTERS SUMMARY BANK0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module’s Register Program Counter’s (PC) Least Significant Byte IRP RA7 RB7 RP1 RA6 RB6 RP0 RA5 RB5 TO RA4 RB4 PD RA3 RB3 Z RA2 RB2 DC RA1 RB1 C RA0 RB0 Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx 0000 xxxx xxxx — — — 30 47 30 24 30 33 38 — — — 30 26 28 — 50 50 50 54 54 — — 57 57 57 74 79 82 — — — — 63 Unimplemented Unimplemented Unimplemented — GIE EEIF — PEIE CMIF — T0IE RCIF Write Buffer for upper 5 bits of Program Counter INTE TXIF RBIE — T0IF CCP1IF INTF TMR2IF RBIF TMR1IF ---0 0000 0000 000x 0000 -000 — xxxx xxxx xxxx xxxx Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — — TOUTPS3 T1CKPS1 T1CKPS0 T1OSCEN TOUTPS0 T1SYNC TMR2ON TMR1CS T2CKPS1 TMR1ON T2CKPS0 TMR2 Module’s Register TOUTPS2 TOUTPS1 Unimplemented Unimplemented Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) — SPEN — RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D --00 0000 0000 0000 -000 0000 — — xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 — — — — CCPR1H CCP1CON RCSTA TXREG RCREG — — — — CMCON USART Transmit Data Register USART Receive Data Register Unimplemented Unimplemented Unimplemented Unimplemented C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 .

u = unchanged. refer to Table 14-6 and Table 14-7.x000 ---. q = value depends on condition.---— VRR — VR3 VR2 VR1 VR0 000. shaded = unimplemented For the initialization condition for registers tables.1-0x — — — 1111 1111 — — — — — TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 0000 xxxx xxxx xxxx xxxx — — WRERR WREN WR RD ---. x = unknown.PIC16F627A/628A/648A TABLE 4-4: Address Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: PR2 — — — — — TXSTA SPBRG EEDATA EEADR EECON1 EECON2 — VRCON INDF OPTION PCL STATUS FSR TRISA TRISB — — — PCLATH INTCON PIE1 — PCON — — — Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP TRISA7 TRISB7 INTEDG RP1 TRISA6 TRISB6 T0CS RP0 TRISA5 TRISB5 T0SE TO TRISA4 TRISB4 PSA PD TRISA3 TRISB3 PS2 Z TRISA2 TRISB2 PS1 DC TRISA1 TRISB1 PS0 C TRISA0 TRISB0 Program Counter’s (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 — — — — PEIE CMIE — — T0IE RCIE — Write Buffer for upper 5 bits of Program Counter INTE TXIE — RBIE — OSCF T0IF CCP1IE — INTF TMR2IE POR RBIF TMR1IE BOR ---0 0000 0000 000x 0000 -000 — ---. © 2009 Microchip Technology Inc.= Unimplemented locations read as ‘0’. DS40044G-page 21 .0000 30 25 30 24 30 33 38 — — — 30 26 27 — 29 — — — 54 — — — — — 73 75 91 92 92 92 — 69 SPECIAL FUNCTION REGISTERS SUMMARY BANK1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Unimplemented Unimplemented Unimplemented — GIE EEIE — Unimplemented Unimplemented Unimplemented Timer2 Period Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CSRC TX9 Baud Rate Generator Register EEPROM Data Register EEPROM Address Register — Unimplemented VREN VROE — EEPROM Control Register 2 (not a physical register) Unimplemented .

x = unknown. q = value depends on condition. refer to Table 14-6 and Table 14-7. . DS40044G-page 22 © 2009 Microchip Technology Inc.PIC16F627A/628A/648A TABLE 4-5: Address Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: INDF TMR0 PCL STATUS FSR — PORTB — — — PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx Timer0 Module’s Register Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Unimplemented Unimplemented Unimplemented — GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented — PEIE — T0IE Write Buffer for upper 5 bits of Program Counter INTE RBIE T0IF INTF RBIF xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx — xxxx xxxx — — — ---0 0000 0000 000x — — — — — — — — — — — — — — — — — — — — 30 47 30 24 30 — 38 — — — 30 26 — — — — — — — — — — — — — — — — — — — — SPECIAL FUNCTION REGISTERS SUMMARY BANK2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page . u = unchanged.= Unimplemented locations read as ‘0’. shaded = unimplemented. For the initialization condition for registers tables.

shaded = unimplemented For the initialization condition for registers tables. u = unchanged.PIC16F627A/628A/648A TABLE 4-6: Address Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: INDF OPTION PCL STATUS FSR — TRISB — — — PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C 1111 1111 0000 0000 0001 1xxx xxxx xxxx — TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 — — — — PEIE — T0IE Write Buffer for upper 5 bits of Program Counter INTE RBIE T0IF INTF RBIF ---0 0000 0000 000x — — — — — — — — — — — — — — — — — — — — Program Counter’s (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented TRISB7 TRISB6 Unimplemented Unimplemented Unimplemented — GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 30 25 30 24 30 — 38 — — — 30 26 — — — — — — — — — — — — — — — — — — — — SPECIAL FUNCTION REGISTERS SUMMARY BANK3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page . © 2009 Microchip Technology Inc. DS40044G-page 23 . q = value depends on condition. refer to Table 14-6 and Table 14-7.= Unimplemented locations read as ‘0’. x = unknown.

REGISTER 4-1: STATUS – STATUS REGISTER (ADDRESS: 03h. 3 (100h-1FFh) 0 = Bank 0. the polarity is reversed. respectively. It is recommended. BSF.PIC16F627A/628A/648A 4. Note: The C and DC bits operate as a Borrow and Digit Borrow out bit. Therefore.1 Status Register The Status register. in subtraction.SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For Borrow. not affecting any Status bits. contains the arithmetic status of the ALU. 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time Out bit 1 = After power-up. shown in Register 4-1. this bit is loaded with either the high or low order bit of the source register.2. CLRF STATUS will clear the upper-three bits and set the Z bit.2. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DS40044G-page 24 © 2009 Microchip Technology Inc. ADDLW. This leaves the Status register as “000uu1uu” (where u = unchanged). For example. ADDLW.SUBLW. These bits are set or cleared according to the device logic. SWAPF and MOVWF instructions are used to alter the Status register because these instructions do not affect any Status bit. A subtraction is executed by adding the two’s complement of the second operand. therefore. 183h) R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2. the result of an instruction with the Status register as destination may be different than intended.SUBLW. the Reset status and the bank select bits for data memory (SRAM). If the Status register is the destination for an instruction that affects the Z. bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.SUBWF instructions) (for Borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/Borrow bit (ADDWF. For other instructions. that only BCF. like any other register. then the write to these three bits is disabled. RLF) instructions. CLRWDT instruction or SLEEP instruction 0 = A WDT time out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF. the TO and PD bits are nonwritable. 103h. 83h. The Status register can be the destination for any instruction. DC or C bits. see the “Instruction Set Summary”. See the SUBLW and SUBWF instructions for examples. . Furthermore. For rotate (RRF.

2.2. The Option register is a readable and writable register. REGISTER 4-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h. which contains various control bits to configure the TMR0/WDT prescaler. TMR0 and the weak pull-ups on PORTB.3. See Section 6. assign the prescaler to the WDT (PSA = 1). 181h) R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI/CMP2 pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI/CMP2 pin 0 = Increment on low-to-high transition on RA4/T0CKI/CMP2 pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. DS40044G-page 25 .1 “Switching Prescaler Assignment”.PIC16F627A/628A/648A 4. the external RB0/INT interrupt.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for TMR0. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
4.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 “PIE1 Register” and Section 4.2.2.5 “PIR1 Register” for a description of the comparator enable and flag bits.

REGISTER 4-3:

INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit 0

bit 7

GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB<7:4> pins changes state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DS40044G-page 26

© 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
4.2.2.4 PIE1 Register
This register contains interrupt enable bits.

REGISTER 4-4:

PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 EEIE bit 7 R/W-0 CMIE R/W-0 RCIE R/W-0 TXIE U-0 — R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0

bit 7

EEIE: EE Write Complete Interrupt Enable Bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt Unimplemented: Read as ‘0’ CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown

bit 6

bit 5

bit 4

bit 3 bit 2

bit 1

bit 0

© 2009 Microchip Technology Inc.

DS40044G-page 27

PIC16F627A/628A/648A
4.2.2.5 PIR1 Register
This register contains interrupt flag bits. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

REGISTER 4-5:

PIR1 – PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0 EEIF bit 7 R/W-0 CMIF R-0 RCIF R-0 TXIF U-0 — R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0

bit 7

EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started CMIF: Comparator Interrupt Flag bit 1 = Comparator output has changed 0 = Comparator output has not changed RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full Unimplemented: Read as ‘0’ CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown

bit 6

bit 5

bit 4

bit 3 bit 2

bit 1

bit 0

DS40044G-page 28

© 2009 Microchip Technology Inc.

It must then be set by the user and checked on subsequent Resets to see if BOR is cleared.6 PCON Register Note: BOR is unknown on Power-on Reset. WDT Reset or a Brown-out Reset.PIC16F627A/628A/648A 4. indicating a brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BOREN bit in the Configuration Word). DS40044G-page 29 .2.2. an external MCLR Reset. The PCON register contains flag bits to differentiate between a Power-on Reset. REGISTER 4-6: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 — bit 7 U-0 — U-0 — U-0 — R/W-1 OSCF U-0 — R/W-0 POR R/W-x BOR bit 0 bit 7-4 bit 3 Unimplemented: Read as ‘0’ OSCF: INTOSC Oscillator Frequency bit 1 = 4 MHz typical 0 = 48 kHz typical Unimplemented: Read as ‘0’ POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 2 bit 1 bit 0 © 2009 Microchip Technology Inc.

The stack is POPed in the event of a RETURN. PCLATH is not affected by a PUSH or POP operation. This means that after the stack has been PUSHed eight times. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.2 STACK The PIC16F627A/628A/648A family has an 8-level deep x 13-bit wide hardware stack (Figure 4-1). Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected). CALL EXAMPLE 4-1: 4. Figure 4-4 shows the two situations for loading the PC. DS40044G-page 30 © 2009 Microchip Technology Inc. INDF and FSR Registers The INDF register is not a physical register. The lower example in Figure 4-4 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH). The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. or the vectoring to an interrupt address. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Addressing the INDF register will cause indirect addressing. These are actions that occur from the execution of the CALL. care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). the PC is cleared.3. Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions.3 PCL and PCLATH The Program Counter (PC) is 13-bits wide. FIGURE 4-4: LOADING OF PC IN DIFFERENT SITUATIONS 4.all done? . The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH.no clear next . 2: There are no instructions/mnemonics called PUSH or POP. . On any Reset.to RAM . Indirect addressing is possible by using the INDF register. The low byte comes from the PCL register. RETURN. An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>).1 COMPUTED GOTO NEXT INDIRECT ADDRESSING 0x20 FSR INDF FSR FSR. Refer to the Application Note AN556 “Implementing a Table Read” (DS00556). MOVLW MOVWF CLRF INCF BTFSS GOTO 4. Reading INDF itself indirectly will produce 00h.4 NEXT .3.inc pointer .yes continue A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO. as shown in Figure 4-5. which is a readable and writable register. The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. the ninth PUSH overwrites the value that was stored from the first PUSH.clear INDF register . RETLW and RETFIE instructions. The upper example in Figure 4-4 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).PIC16F627A/628A/648A 4. The tenth PUSH overwrites the second PUSH (and so on). The stack operates as a circular buffer. RETLW or a RETFIE instruction execution.4 PCH 12 PC 5 PCLATH<4:0> 8 8 7 PCL 0 Instruction with PCL as Destination ALU result Indirect Addressing. When doing a table read using a computed GOTO method.initialize pointer .

PIC16F627A/628A/648A FIGURE 4-5: Status Register RP1 RP0 DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A Direct Addressing 6 from opcode 0 Status Register IRP Indirect Addressing 7 FSR Register 0 bank select location select 00 00h bank select 01 10 11 180h location select RAM File Registers 7Fh Bank 0 Note: Bank 1 Bank 2 Bank 3 1FFh For memory map detail see Figure 4-3. © 2009 Microchip Technology Inc. Figure 4-2 and Figure 4-1. DS40044G-page 31 .

PIC16F627A/628A/648A NOTES: DS40044G-page 32 © 2009 Microchip Technology Inc. .

PIC16F627A/628A/648A
5.0 I/O PORTS
The PIC16F627A/628A/648A have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.

EXAMPLE 5-1:
CLRF PORTA

INITIALIZING PORTA
;Initialize PORTA by ;setting ;output data latches ;Turn comparators off and ;enable pins for I/O ;functions

5.1

PORTA and TRISA Registers

PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input. RA5(1) is a Schmitt Trigger input only and has no output drivers. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. A ‘1’ in the TRISA register puts the corresponding output driver in a High-impedance mode. A ‘0’ in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (Comparator Control register) register and the VRCON (Voltage Reference Control register) register. When selected as a comparator input, these pins will read as ‘0’s. Note 1: RA5 shares function with VPP. When VPP voltage levels are applied to RA5, the device will enter Programming mode. 2: On Reset, the TRISA register is set to all inputs. The digital inputs (RA<3:0>) are disabled and the comparator inputs are forced to ground to reduce current consumption. 3: TRISA<6:7> is overridden by oscillator configuration. When PORTA<6:7> is overridden, the data reads ‘0’ and the TRISA<6:7> bits are ignored. TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs when using them as comparator inputs. The RA2 pin will also function as the output for the voltage reference. When in this mode, the VREF pin is a very high-impedance output. The user must configure TRISA<2> bit as an input and use high-impedance loads.

MOVLW MOVWF BCF BSF MOVLW MOVWF

0x07 CMCON

STATUS, RP1 STATUS, RP0 ;Select Bank1 0x1F ;Value used to initialize ;data direction TRISA ;Set RA<4:0> as inputs ;TRISA<5> always ;read as ‘1’. ;TRISA<7:6> ;depend on oscillator ;mode

FIGURE 5-1:

BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS

Data Bus WR PORTA

D CK D

Q Q Q CK Q Analog Input Mode (CMCON Reg.) Schmitt Trigger Input Buffer

VDD

Data Latch I/O Pin

WR TRISA

TRIS Latch

VSS

RD TRISA

Q EN RD PORTA To Comparator

D

© 2009 Microchip Technology Inc.

DS40044G-page 33

PIC16F627A/628A/648A
FIGURE 5-2:
Data Bus WR PORTA

BLOCK DIAGRAM OF RA2/AN2/VREF PIN
Q VDD

D CK D

Q Q

Data Latch WR TRISA RA2 Pin Analog Input Mode (CMCON Reg.) VSS

CK

Q

TRIS Latch RD TRISA

Schmitt Trigger Input Buffer Q EN D

RD PORTA

To Comparator VROE VREF

FIGURE 5-3:
Data Bus WR PORTA D CK D WR TRISA CK

BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN
Comparator Mode = 110 (CMCON Reg.) Q Comparator Output
1

VDD

Q
0

Data Latch Q Q

RA3 Pin Analog Input Mode (CMCON Reg.) VSS

TRIS Latch RD TRISA

Schmitt Trigger Input Buffer Q EN D

RD PORTA

To Comparator

DS40044G-page 34

© 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
FIGURE 5-4:
Data Bus WR PORTA D CK D WR TRISA CK

BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN
Comparator Mode = 110 Q Comparator Output
1

(CMCON Reg.)

Q
0

Data Latch Q

N

RA4 Pin

Q Vss Vss

TRIS Latch

RD TRISA Q EN RD PORTA

Schmitt Trigger Input Buffer D

TMR0 Clock Input

FIGURE 5-5:

BLOCK DIAGRAM OF THE RA5/MCLR/VPP PIN

FIGURE 5-6:
From OSC1

BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
OSC Circuit
1

VDD

MCLR circuit

MCLRE (Configuration Bit)

CLKOUT(FOSC/4)

MCLR Filter Program mode Schmitt Trigger Input Buffer
RA5/MCLR/VPP

HV Detect

CK Q FOSC = (2) Data Latch 101, 111 D Q

WR PORTA

D

Q

0

VSS

Data Bus

VSS

WR TRISA RD TRISA

CK Q TRIS Latch Schmitt Trigger Input Buffer

RD TRISA

VSS Q D EN

FOSC = 011, 100, 110 (1) Q D EN RD PORTA

RD PORTA

Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O. 2: INTOSC with RA6 = CLKOUT or RC with RA6 = CLKOUT.

© 2009 Microchip Technology Inc.

DS40044G-page 35

DS40044G-page 36 © 2009 Microchip Technology Inc. . 101(1) Q EN RD PORTA D Schmitt Trigger Input Buffer Note 1: INTOSC with CLKOUT and INTOSC with I/O.PIC16F627A/628A/648A FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits VDD Data Bus WR PORTA D CK D Q RA7/OSC1/CLKIN Pin Q Q Q VSS Data Latch WR TRISA CK TRIS Latch RD TRISA FOSC = 100.

PIC16F627A/628A/648A TABLE 5-1: Name RA0/AN0 RA1/AN1 RA2/AN2/VREF PORTA FUNCTIONS Function RA0 AN0 RA1 AN1 RA2 AN2 VREF Input Type ST AN ST AN ST AN — ST AN — ST ST — ST ST Output Type CMOS — CMOS — CMOS — AN CMOS — CMOS OD — OD — — Bidirectional I/O port Analog comparator input Bidirectional I/O port Analog comparator input Bidirectional I/O port Analog comparator input VREF output Bidirectional I/O port Analog comparator input Comparator 1 output Bidirectional I/O port. P = Power ST = Schmitt Trigger Input AN = Analog Description RA3/AN3/CMP1 RA3 AN3 CMP1 RA4/T0CKI/CMP2 RA4 T0CKI CMP2 RA5/MCLR/VPP RA5 MCLR VPP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT RA7/OSC1/CLKIN RA7 OSC1 CLKIN Legend: O = Output — = Not used TTL = TTL Input HV ST — — ST XTAL ST — CMOS XTAL CMOS CMOS — — CMOS = CMOS Output I = Input OD = Open Drain Output TABLE 5-2: Address 05h 85h 1Fh 9Fh Legend: Note 1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 RA7 C2OUT VREN Bit 6 RA6 C1OUT VROE Bit 5 RA5(1) C2INV VRR Bit 4 RA4 C1INV — Bit 3 RA3 CIS VR3 Bit 2 RA2 CM2 VR2 Bit 1 RA1 CM1 VR1 Bit 0 RA0 CM0 VR0 Value on POR xxxx 0000 1111 1111 0000 0000 000. In RC or INTOSC mode. When configured as MCLR. External clock input for TMR0 or comparator output Comparator 2 output Input port Master clear. © 2009 Microchip Technology Inc. Connects to crystal resonator in Crystal Oscillator mode. Shaded cells are not used for PORTA. u = unchanged. Voltage on MCLR/VPP must not exceed VDD during normal device operation. x = unknown. Bidirectional I/O port Oscillator crystal input. q = value depends on condition.0000 Name PORTA TRISA CMCON VRCON TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 . External clock source input. Output is open drain type.= Unimplemented locations read as ‘0’. Connects to crystal resonator in Crystal Oscillator mode. MCLRE configuration bit sets RA5 functionality. which has 1/4 the frequency of OSC1. this pin is an active low Reset to the device. RC biasing pin. DS40044G-page 37 .0000 Value on All Other Resets qqqu 0000 1111 1111 0000 0000 000. OSC2 pin can output CLKOUT. Programming voltage input Bidirectional I/O port Oscillator crystal output.

Only pins configured as inputs can cause this interrupt to occur (i. The standard port functions and the alternate port functions are shown in Table 5-3. A ‘1’ in the TRISB register puts the corresponding output driver in a High-impedance mode. DS40044G-page 38 © 2009 Microchip Technology Inc. Reading PORTB register reads the status of the pins. The weak pull-up is automatically turned off when the port pin is configured as an output. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This will end the mismatch condition. RB<7:4>. in the interrupt service routine. then the RBIF interrupt flag may not get set. whereas writing to it will write to the port latch. Alternate port functions may override the TRIS setting when enabled. together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression (See Application Note AN552 “Implementing Wake-up on Key Strokes” (DS00552).2 PORTB and TRISB Registers PORTB is an 8-bit wide bidirectional port. A single control bit can turn on all the pull-ups. then this value is modified and written to the port data latch.e.. The user. USART. PORTB is multiplexed with the external interrupt. can clear the interrupt in the following manner: a) b) Any read or write of PORTB. So a write to a port implies that the port pins are first read. . This is done by clearing the RBPU (OPTION<7>) bit. The “mismatch” outputs of RB<7:4> are OR’ed together to generate the RBIF interrupt (flag latched in INTCON<0>). Each of the PORTB pins has a weak internal pull-up (≈200 μA typical). This interrupt can wake the device from Sleep. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.PIC16F627A/628A/648A 5. FIGURE 5-8: RBPU BLOCK DIAGRAM OF RB0/INT PIN VDD P Weak Pull-up VDD Data Bus WR PORTB D CK Q RB0/INT Q Data Latch VSS D Q Q WR TRISB CK TRIS Latch RD TRISB Q D EN EN TTL Input Buffer RD PORTB INT Schmitt Trigger A mismatch condition will continue to set flag bit RBIF. The corresponding data direction register is TRISB. Clear flag bit RBIF. Note: If a change on the I/O pin should occur when a read operation is being executed (start of the Q2 cycle). CCP module and the TMR1 clock input/output. have an interrupt-onchange feature. The input pins (of RB<7:4>) are compared with the old value latched on the last read of PORTB. any RB<7:4> pin configured as an output is excluded from the interrupton-change comparison). Four of PORTB’s pins. All write operations are read-modify-write operations. This interrupt on mismatch feature. The pull-ups are disabled on Power-on Reset. A ‘0’ in the TRISB register puts the contents of the output latch on the selected pin(s).

Note 1: RD PORTB D Peripheral OE(1) TRIS Latch RD TRISB RD TRISB Q EN D TTL Input Buffer USART Slave Clock In Schmitt Trigger Peripheral OE (output enable) is only active if peripheral select is active. © 2009 Microchip Technology Inc.PIC16F627A/628A/648A FIGURE 5-9: RBPU SPEN BLOCK DIAGRAM OF RB1/RX/DT PIN VDD Weak P Pull-up VDD FIGURE 5-10: RBPU SPEN BLOCK DIAGRAM OF RB2/TX/CK PIN VDD Weak P Pull-up VDD USART Data Output Data Bus WR PORTB 1 D CK Q Q VSS 0 RB1/ RX/DT USART TX/CK Output Data Bus WR PORTB 1 D CK Q Q VSS 0 RB2/ TX/CK Data Latch D WR TRISB CK Q Q Data Latch D WR TRISB CK Q Q TRIS Latch Peripheral OE(1) TTL Input Buffer Q EN RD PORTB USART Receive Input Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. DS40044G-page 39 .

D RD TRISB DS40044G-page 40 © 2009 Microchip Technology Inc.PIC16F627A/628A/648A FIGURE 5-11: RBPU CCP1CON BLOCK DIAGRAM OF RB3/CCP1 PIN VDD Weak P Pull-up VDD CCP output Data Bus WR PORTB 0 D CK Q Q VSS 1 RB3/ CCP1 Data Latch D WR TRISB CK Q Q TRIS Latch Peripheral OE(2) TTL Input Buffer Q EN RD PORTB CCP In Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. .

DS40044G-page 41 .PIC16F627A/628A/648A FIGURE 5-12: RBPU BLOCK DIAGRAM OF RB4/PGM PIN VDD P weak pull-up Data Bus D CK Q Q VDD WR PORTB Data Latch D WR TRISB CK Q Q VSS TRIS Latch RD TRISB RB4/PGM LVP (Configuration Bit) RD PORTB PGM input Schmitt Trigger Q D EN Set RBIF From other RB<7:4> pins Q D EN Q3 Q1 TTL input buffer Note: The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. © 2009 Microchip Technology Inc.

PIC16F627A/628A/648A FIGURE 5-13: RBPU BLOCK DIAGRAM OF RB5 PIN VDD weak VDD P pull-up Data Bus WR PORTB D CK Q RB5 pin Q Data Latch VSS D WR TRISB CK Q Q TTL input buffer TRIS Latch RD TRISB Q RD PORTB D EN Q1 Set RBIF From other RB<7:4> pins Q D EN Q3 DS40044G-page 42 © 2009 Microchip Technology Inc. .

DS40044G-page 43 .PIC16F627A/628A/648A FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN VDD P weak pull-up RBPU Data Bus WR PORTB D CK Q Q VDD Data Latch D WR TRISB CK Q Q VSS RB6/ T1OSO/ T1CKI/ PGC pin TRIS Latch RD TRISB T1OSCEN TTL input buffer RD PORTB TMR1 Clock From RB7 Serial Programming Clock Schmitt Trigger TMR1 oscillator Q D EN Q1 Set RBIF From other RB<7:4> pins Q D EN Q3 © 2009 Microchip Technology Inc.

.PIC16F627A/628A/648A FIGURE 5-15: RBPU BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN VDD P weak pull-up To RB6 TMR1 oscillator VDD Data Bus WR PORTB D CK Q Q RB7/T1OSI/ PGD pin Data Latch D WR TRISB CK Q Q VSS TRIS Latch RD TRISB T10SCEN RD PORTB Serial Programming Input Schmitt Trigger Q D EN Set RBIF From other RB<7:4> pins Q D TTL input buffer Q1 EN Q3 DS40044G-page 44 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. 181h Legend: Note 1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 T0CS Bit 4 RB4(1) T0SE Bit 3 RB3 PSA Bit 2 RB2 PS2 Bit 1 RB1 PS1 Bit 0 RB0 PS0 Value on POR xxxx xxxx Value on All Other Resets uuuu uuuu 1111 1111 1111 1111 Name PORTB TRISB OPTION TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 u = unchanged. Shaded cells are not used for PORTB. Bidirectional I/O port. Interrupt-on-pin change. Low-voltage programming input pin. External interrupt Bidirectional I/O port. Bidirectional I/O port. DS40044G-page 45 . Capture/Compare/PWM/I/O Bidirectional I/O port. LVP configuration bit sets RB4 functionality. Can be software programmed for internal weak pull-up. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. 186h 81h. Can be software programmed for internal weak pull-up.PIC16F627A/628A/648A TABLE 5-3: Name RB0/INT PORTB FUNCTIONS Function Input Type RB0 INT TTL ST TTL ST ST TTL — ST TTL ST TTL ST Output Type CMOS — CMOS — CMOS CMOS CMOS CMOS CMOS CMOS CMOS — Description Bidirectional I/O port. Can be software programmed for internal weak pull-up. Interrupt-on-pin change. x = unknown. Interrupt-on-pin change. 106h 86h. USART Receive Pin Synchronous data I/O Bidirectional I/O port USART Transmit Pin Synchronous Clock I/O. Timer1 Oscillator Input ICSP Data I/O P = Power ST = Schmitt Trigger Input AN = Analog RB1/RX/DT RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 RB4/PGM RB4 PGM RB5 RB6/T1OSO/T1CKI/ PGC RB5 RB6 T1OSO T1CKI PGC TTL TTL — ST ST TTL XTAL ST CMOS CMOS XTAL — — CMOS — CMOS RB7/T1OSI/PGD RB7 T1OSI PGD Legend: O = Output — = Not used TTL = TTL Input CMOS = CMOS Output I = Input OD = Open Drain Output TABLE 5-4: Address 06h. Can be software programmed for internal weak pull-up. When low-voltage programming is enabled. Can be software programmed for internal weak pull-up. Bidirectional I/O port. Timer1 Oscillator Output Timer1 Clock Input ICSP™ Programming Clock Bidirectional I/O port. Can be software programmed for internal weak pull-up. the interrupt-on-pin change and weak pull-up resistor are disabled. Can be software programmed for internal weak pull-up.

Then the BSF operation takes place on bit 5 and PORTB is written to the output latches. DS40044G-page 46 © 2009 Microchip Technology Inc.Note that the user may have expected the . As long as the pin stays in the Input mode. and this value is then written to the port latch.. no problem occurs. etc. it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. The BCF and BSF instructions.01pp pppp 11pp pppp BSF STATUS. etc. the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin. PORT latchPORT Pins ---------. When using read-modify-write instructions (ex. BCF TRISB. which causes that file to be read into the CPU. The resulting high output currents may damage the chip. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. execute the bit operation and write the result back to the register. whereas for reading.caused RB7 to be latched as the pin value . W Execute NOP This example shows write to PORTB followed by a read from PORTB. the desired operation is done to this value. . Example 5-2 shows the effect of two sequential readmodify-write instructions (ex. BSF.3. 6 .PIC16F627A/628A/648A 5. the value of the port pins is read. Therefore. RP0 .(High).pin values to be 00pp pppp.TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid. PORTB<3:0> Outputs . If another bit of PORTB is used as a bidirectional I/O pin (e.g. bit 0) and is defined as an input at this time. BCF. 7 . .) on an I/O port.1 I/O Programming Considerations BIDIRECTIONAL I/O PORTS EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT Any instruction that writes operates internally as a read followed by a write operation. Reading a port register reads the values of the port pins.Initial PORT settings:PORTB<7:4> Inputs . A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-OR”. The 2nd BCF .25 TCY . the previous state of that pin may be read into the CPU rather than the new state. for example. a BSF operation on bit 5 of PORTB will cause all eight bits of PORTB to be read into the CPU. BCF.) on a port.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle.10pp pppp 11pp pppp BCF TRISB.3 5.. . Writing to the port register writes the value to the port latch. Otherwise. BSF. 7 . a write followed by a read may be problematic. is executed.not connected to other circuitry . Therefore. RP0 . FIGURE 5-16: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 PC + 2 NOP Q2 Q3 Q4 PC + 3 NOP PC Instruction fetched PC MOVWF PORTB Write to PORTB PC + 1 MOVF PORTB.---------BCF STATUS. “wiredAND”).3. care must be exercised if a write followed by a read operation is carried out on the same I/O port. the content of the data latch may now be unknown. BCF PORTB. For example.PORTB<7:6> have external pull-up and are .10pp pppp 10pp pppp . the data must be valid at the beginning of the instruction cycle (Figure 5-16). overwriting the previous content. at higher clock frequencies. When in doubt. However. W Read to PORTB Port pin sampled here TPD Execute MOVWF PORTB Note 1: 2: Execute MOVF PORTB. Data setup time = (0. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction. if bit 0 is switched into Output mode later on. . read the register into the CPU. 5.

The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). In this mode the TMR0 register value will increment either on every rising or falling edge of pin RA4/T0CKI/CMP2. Timer mode is selected by clearing the T0CS bit (OPTION<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before reenabling this interrupt.3 “Timer0 Prescaler” details the operation of the prescaler..2 Using Timer0 with External Clock The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Read/write capabilities 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock When an external clock input is used for Timer0. Also. 1:4. The user can work around this by writing an adjusted value to the TMR0 register.. Counter mode is selected by setting the T0CS bit. Refer to parameters 40. the TMR0 register value will increment every instruction cycle (without prescaler).2 “Using Timer0 with External Clock”. it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. prescale value of 1:2. When the prescaler is assigned to the Timer0 module. The external clock requirement is due to internal phase clock (TOSC) synchronization. The prescaler is not readable or writable.0 TIMER0 MODULE 6. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION<4>). the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. Clearing the PSA bit will assign the prescaler to Timer0. the increment is inhibited for the following two cycles. In Timer mode.PIC16F627A/628A/648A 6. 41 and 42 in the electrical specification of the desired device. When no prescaler is used. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). Additional information is available in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023). 6. See Table 17-8. the ripple-counter must be taken into account. it must meet certain requirements. The prescaler is shared between the Timer0 module and the Watchdog Timer. it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-1). Section 6. the external clock input is the same as the prescaler output.2. Therefore. Therefore.1 Timer0 Interrupt Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. 6. Clearing the T0SE bit selects the rising edge. DS40044G-page 47 . If the TMR0 register is written to.1 EXTERNAL CLOCK SYNCHRONIZATION Figure 6-1 is a simplified block diagram of the Timer0 module. Restrictions on the external clock input are discussed in detail in Section 6. 1:256 are selectable.. there is a delay in the actual incrementing of Timer0 after synchronization. © 2009 Microchip Technology Inc.. When a prescaler is used. Refer to the electrical specification of the desired device. For the external clock to meet the sampling requirement. This overflow sets the T0IF bit. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns.

and vice-versa. x.g.. ... . PS<2:0> are bits in the Option Register. all instructions writing to the TMR0 register (e.3 Timer0 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. FIGURE 6-1: FOSC/4 BLOCK DIAGRAM OF THE TIMER0/WDT Data Bus 8 1 0 0 T0CKI pin 1 SYNC 2 Cycles TMR0 Reg T0SE T0CS TMR1 Clock Source PSA Set flag bit T0IF on Overflow 0 Watchdog Timer 1 WDT Postscaler/ TMR0 Prescaler 8 PSA 8-to-1MUX WDT Enable bit 1 0 PS<2:0> WDT Time-out PSA Note: T0SE. MOVWF 1. The prescaler is not readable or writable. When assigned to WDT.etc.PIC16F627A/628A/648A 6.. or as a postscaler for the Watchdog Timer. The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. T0CS. PSA. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer.) will clear the prescaler. DS40044G-page 48 © 2009 Microchip Technology Inc. CLRF 1. a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. BSF 1. When assigned to the Timer0 module.

Use the instruction sequences shown in Example 6-1 when changing the prescaler assignment from Timer0 to WDT.These 3 lines .are . 6. EXAMPLE 6-2: CLRWDT BSF MOVLW CHANGING PRESCALER (WDT → TIMER0) .1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.Prescaler . Shaded cells are not used for Timer0. to avoid an unintended device Reset.e.(5. 7) .if desired PS<2:0> .Bank 0 . read as ‘0’.clock source STATUS.Return to Bank 0 STATUS.prescale value and . INTCON 10Bh. RP0 TABLE 6-1: Address 01h. use the sequence shown in Example 6-2. RP0 MOVWF BCF OPTION_REG STATUS.are required only .Bank 1 .prescaler EXAMPLE 6-1: BCF CHANGING PRESCALER (TIMER0 → WDT) . 8Bh.Select TMR0.desired WDT rate .000 or 001 . RP0 '00101111’b OPTION_REG CLRWDT MOVLW '00101xxx’b MOVWF OPTION_REG BCF STATUS. RP0 CLRWDT CLRF TMR0 BSF MOVLW MOVWF STATUS.3.Clear WDT and . To change prescaler from the WDT to the Timer0 module. Option is referred by OPTION_REG in MPLAB® IDE Software. © 2009 Microchip Technology Inc.Set Postscaler to . 101h REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other Resets TMR0 Timer0 Module Register GIE RBPU PEIE INTEDG T0IE T0CS INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 xxxx xxxx uuuu uuuu 0000 000x 0000 000u 1111 1111 1111 1111 0Bh..PIC16F627A/628A/648A 6. u = unchanged.Clear WDT . x = unknown. RP0 b'xxxx0xxx’ .Clear TMR0 and .= Unimplemented locations. new .Skip if already in . it can be changed “on-the-fly” during program execution). 18Bh 81h. DS40044G-page 49 . 181h 85h Legend: Note 1: OPTION(2) TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 . This precaution must be taken even if the WDT is disabled.

. That is.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain. the RB7/ T1OSI/PGD and RB6/T1OSO/T1CKI/PGC pins become inputs. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. For the PIC16F627A/628A/648A. Timer1 also has an internal “Reset input”. if enabled. In Counter mode. TMR1CS (T1CON<1>).PIC16F627A/628A/648A 7. REGISTER 7-1: T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 — bit 7 U-0 — R/W-0 R/W-0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 bit 0 T1CKPS1 T1CKPS0 T1SYNC TMR1CS TMR1ON bit 7-6 bit 5-4 Unimplemented: Read as ‘0’ T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off(1) T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Register 7-1 shows the Timer1 control register. This interrupt can be enabled/disabled by setting/clearing the Timer1 interrupt enable bit TMR1IE (PIE1<0>). This Reset can be generated by the CCP module (Section 9. The Timer1 Interrupt. it increments on every rising edge of the external clock input. when the Timer1 oscillator is enabled (T1OSCEN is set). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).0 “Capture/Compare/PWM (CCP) Module”). Timer1 uses the internal clock when TMR1CS = 0. the TRISB<7:6> value is ignored. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 3 bit 2 bit 1 bit 0 DS40044G-page 50 © 2009 Microchip Technology Inc. is generated on overflow of the TMR1 register pair which latches the interrupt flag bit TMR1IF (PIR1<0>). Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Timer1 can operate in one of two modes: • As a timer • As a counter The Operating mode is determined by the clock select bit. the TMR1 register pair value increments every instruction cycle. In Timer mode.

The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore. In this configuration. Refer to the appropriate electrical specifications in Table 17-8. the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. FIGURE 7-1: Set flag bit TMR1IF on Overflow TIMER1 BLOCK DIAGRAM TMR1 TMR1H TMR1L 0 Synchronized Clock Input 1 TMR1ON T1OSC RB6/T1OSO/T1CKI/PGC T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock 1 Prescaler 1. In order for the external clock to meet the sampling requirement.PIC16F627A/628A/648A 7. 46 and 47. In this mode. Therefore. Also. If T1SYNC is cleared.2. since the synchronization circuit is shut off. When the prescaler is 1:1. it must meet certain requirements. it is necessary for T1CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). the TMR1 register pair value increments on every rising edge of clock input on pin RB7/T1OSI/PGD when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/ PGC when bit T1OSCEN is cleared. The synchronization is done after the prescaler stage. 4.1 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. This eliminates power drain. Refer to Table 17-8 in the Electrical Specifications Section.1 Timer1 Operation in Timer Mode 7. there is a delay in the actual incrementing of the TMR1 register pair value after synchronization. the external clock input is the same as the prescaler output. the input clock to the timer is FOSC/4. 2. 8 0 2 T1CKPS<1:0> TMR1CS Sleep Input T1SYNC Synchronize det RB7/T1OSI/PGD Note 1: When the T1OSCEN bit is cleared. it is necessary for T1CKI to have a period of at least 4 TOSC (and a small RC delay of 40 ns) divided by the prescaler value. the inverter and feedback resistor are turned off.2 Timer1 Operation in Synchronized Counter Mode When an external clock input is used for Timer1 in Synchronized Counter mode. timing parameters 45. The only requirement on T1CKI high and low time is that they do not violate the minimum pulse width requirements of 10 ns). EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE 7. DS40044G-page 51 . In this mode. parameters 45. The prescaler however will continue to increment. The prescaler stage is an asynchronous ripple-counter. The external clock requirement is due to internal phase clock (TOSC) synchronization. then the external clock input is synchronized with internal phase clocks. When a prescaler other than 1:1 is used. © 2009 Microchip Technology Inc. during Sleep mode. 46 and 47. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. the ripple-counter must be taken into account. the TMR1 register pair value will not increment even if the external clock is present. Counter mode is selected by setting bit TMR1CS.

W . . the high and low bytes now will read a good . MOVF TMR1H.Is result = 0 GOTO CONTINUE . Example 7-1 is an example routine to read the 16-bit timer value. Refer to Table 17-8 in the Electrical Specifications Section. the timer will increment completely asynchronously. .3.Read high byte MOVWF TMPH . timing parameters 45.code If control bit T1SYNC (T1CON<2>) is set. W .3. MOVF TMR1L. W . For writes. value. the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may overflow between the reads. TMR1L may have rolled over between the . Note: In Asynchronous Counter mode.1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK If control bit T1SYNC is set. DS40044G-page 52 © 2009 Microchip Technology Inc. the external clock input is not synchronized. 7. 7. Reading .3 Timer1 Operation in Asynchronous Counter Mode EXAMPLE 7-1: READING A 16-BIT FREERUNNING TIMER . MOVF TMR1H. However. The timer continues to increment asynchronous to the internal phase clocks. will produce a valid read (taken care of in hardware).Read low byte MOVWF TMPL . W . This is useful if the timer cannot be stopped.PIC16F627A/628A/648A 7. Timer1 cannot be used as a time base for capture or compare operations.3.Read high byte MOVWF TMPH .Read low byte MOVWF TMPL . However. which will wake-up the processor. W . A write contention may occur by writing to the timer registers while the register is incrementing. it is recommended that the user simply stop the timer and write the desired values.2nd read BTFSC STATUS.Read high byte SUBWF TMPH. All interrupts are disabled MOVF TMR1H. This may produce an unpredictable value in the timer register. while the timer is running from an external asynchronous clock.2 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading the TMR1H or TMR1L register.Continue with your . The input clock must meet certain minimum high and low time requirements. .Good 16-bit read . MOVF TMR1L. special precautions in software are needed to read/write the timer (Section 7.2 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Re-enable the Interrupts (if required) CONTINUE . Reading the 16-bit value requires some care. W . 46 and 47.Z . The timer will continue to run during Sleep and can generate an interrupt on overflow. . read of the high and low bytes.Sub 1st read with .

7.4 Timer1 Oscillator 7. In the event that a write to Timer1 coincides with a special event trigger from CCP1. which shuts off the timer and leaves a 1:1 prescale. DS40044G-page 53 . In this mode of operation. the register is unaffected.768 kHz Note: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR C1 15 pF C2 15 pF Timer1 must be configured for either timer or Synchronized Counter mode to take advantage of this feature. the write will take precedence.5 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR or any other Reset except by the CCP1 special event triggers (see Section 9. this signal will reset Timer1. © 2009 Microchip Technology Inc. It will continue to run during Sleep.2.768 kHz watch crystal. this Reset operation may not work. 10Bh. 18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 GIE EEIF EEIE Bit 6 PEIE CMIF CMIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE — — Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR 0000 000x 0000 -000 0000 -000 xxxx xxxx xxxx xxxx TMR1ON --00 0000 Value on all other Resets 0000 000u 0000 -000 0000 -000 uuuu uuuu uuuu uuuu --uu uuuu INTCON PIR1 PIE1 TMR1L TMR1H T1CON Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS x = unknown. Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011). Table 7-1 shows the capacitor selection for the Timer1 oscillator. Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). TABLE 7-2: Address 0Bh. . Shaded cells are not used by the Timer1 module. the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.= unimplemented read as ‘0’. 7. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset. It is enabled by setting control bit T1OSCEN (T1CON<3>). These values are for design guidance only. 8Bh.6 Resetting Timer1 Register Pair (TMR1H. u = unchanged. It is primarily intended for a 32. The user must provide a software time delay to ensure proper oscillator start-up.PIC16F627A/628A/648A 7.4 “Special Event Trigger”). TABLE 7-1: Freq 32.7 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. In all other Resets. Consult Application Note AN826 “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) for further information on Crystal/Capacitor Selection. If Timer1 is running in Asynchronous Counter mode.

Watchdog Timer Reset or Brown-out Reset) The TMR2 register is not cleared when T2CON is written. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. selected by control bits T2CKPS<1:0> (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2. The PR2 register is initialized to FFh upon Reset.1 Timer2 Prescaler and Postscaler Timer2 is an 8-bit timer with a prescaler and a postscaler. and is cleared on any device Reset. It can be used as the PWM time base for PWM mode of the CCP module. The PR2 register is a readable and writable register. 1:16 2 T2CKPS<1:0> FOSC/4 DS40044G-page 54 © 2009 Microchip Technology Inc.0 TIMER2 MODULE 8. MCLR Reset. (PIR1<1>)). .PIC16F627A/628A/648A 8. Postscaler 1:1 to 1:16 4 TOUTPS<3:0> EQ The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device Reset (Power-on Reset. The input clock (FOSC/4) has a prescale option of 1:1. The match output of Timer2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a Timer2 interrupt (latched in flag bit TMR2IF. The TMR2 register is readable and writable.2 TMR2 Output The TMR2 output (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. 1:4 or 1:16. FIGURE 8-1: Sets flag bit TMR2IF TMR2 output Reset TIMER2 BLOCK DIAGRAM TMR2 Reg Comparator PR2 Reg Prescaler 1:1. 1:4. 8. Register 8-1 shows the Timer2 control register. The TMR2 register value increments from 00h until it matches the PR2 register value and then resets to 00h on the next increment cycle.

© 2009 Microchip Technology Inc. 18Bh 0Ch 8Ch 11h 12h 92h Legend: PIR1 PIE1 TMR2 T2CON PR2 0000 000x 0000 000u 0000 -000 0000 -000 0000 -000 0000 -000 0000 0000 0000 0000 Timer2 Module’s Register — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Timer2 Period Register x = unknown. DS40044G-page 55 .PIC16F627A/628A/648A REGISTER 8-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h) U-0 — bit 7 bit 7 bit 6-3 Unimplemented: Read as ‘0’ TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale Value 0001 = 1:2 Postscale Value • • • 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = 1:1 Prescaler Value 01 = 1:4 Prescaler Value 1x = 1:16 Prescaler Value Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Shaded cells are not used by the Timer2 module.= unimplemented read as ‘0’. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TMR2ON T2CKPS1 T2CKPS0 bit 2 bit 1-0 TABLE 8-1: Address Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 GIE EEIF EEIE Bit 6 PEIE CMIF CMIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE — — Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR Value on all other Resets 0Bh. u = unchanged. 8Bh. . INTCON 10Bh.

PIC16F627A/628A/648A NOTES: DS40044G-page 56 © 2009 Microchip Technology Inc. .

generate software interrupt on match (CCP1IF bit is set. clear output on match (CCP1IF bit is set) 1010 = Compare mode. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 3-0 © 2009 Microchip Technology Inc. set output on match (CCP1IF bit is set) 1001 = Compare mode. Additional information on the CCP module is available in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023). every rising edge 0110 = Capture mode. The eight MSbs are found in CCPRxL. CCP1M<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode. every 16th rising edge 1000 = Compare mode. DS40044G-page 57 . as a 16-bit Compare register or as a PWM master/slave Duty Cycle register. every 4th rising edge 0111 = Capture mode. CCP1 resets TMR1 11xx = PWM mode Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. every falling edge 0101 = Capture mode. All are readable and writable.PIC16F627A/628A/648A 9. REGISTER 9-1: CCP1CON – CCP OPERATION REGISTER (ADDRESS: 17h) U-0 — bit 7 U-0 — R/W-0 CCP1X R/W-0 CCP1Y R/W-0 CCP1M3 R/W-0 R/W-0 R/W-0 bit 0 CCP1M2 CCP1M1 CCP1M0 bit 7-6 bit 5-4 Unimplemented: Read as ‘0’ CCP1X:CCP1Y: PWM Least Significant bits Capture Mode Unused Compare Mode Unused PWM Mode These bits are the two LSbs of the PWM duty cycle. CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). Table 9-1 shows the timer resources of the CCP module modes. The CCP1CON register controls the operation of CCP1. CCP1 pin is unaffected) 1011 = Compare mode.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 9-1: CCP MODE – TIMER RESOURCE Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit Capture register. trigger special event (CCP1IF bit is set.

the old captured value will be lost. but not set interrupt flag bit TMR1IF (PIR1<0>). a false capture interrupt may be generated. This example also clears the prescaler counter and will not generate the “false” interrupt. Q S Output Logic match RB3/CCP1 R pin TRISB<3> Output Enable CCP1CON<3:0> Mode Select Note: Comparator TMR1H TMR1L Special event trigger will reset Timer1. the prescaler counter will not be cleared. the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. the RB3/CCP1 pin should be configured as an input by setting the TRISB<3> bit.Turn CCP module off NEW_CAPT_PS .1.1. DS40044G-page 58 © 2009 Microchip Technology Inc.Load CCP1CON with this .1 Capture Mode 9. An event is selected by control bits CCP1M<3:0> (CCP1CON<3:0>). This means that any Reset will clear the prescaler counter. a write to the port can cause a capture condition. therefore the first capture may be from a non-zero prescaler. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in Operating mode. At the same time. interrupt flag bit CCP1IF is set. or the CCP module is not in Capture mode. 16 RB3/CCP1 pin and edge detect Capture Enable TMR1H TMR1L CCP1CON<3:0> Q’s FIGURE 9-2: 9. CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1.1 CCP PIN CONFIGURATION CHANGING BETWEEN CAPTURE PRESCALERS In Capture mode. mode value and CCP ON CCP1CON . the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. EXAMPLE 9-1: CLRF MOVLW 9. Example 9-1 shows the recommended method for switching between capture prescalers. Switching from one capture prescaler to another may generate an interrupt.3 SOFTWARE INTERRUPT When the Capture mode is changed. the RB3/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). the new prescaler . MOVWF CCP1CON . 9. the capture operation may not work.2 TIMER1 MODE SELECTION COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. specified by bits CCP1M<3:0>. Whenever the CCP module is turned off. 4. When a capture is made. Note: If the RB3/CCP1 is configured as an output. . If another capture occurs before the value in register CCPR1 is read. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge There are four prescaler settings.1. the prescaler counter is cleared.2 Compare Mode In Compare mode.4 CCP PRESCALER In Capture mode. When a match occurs. Also.Load the W reg with .1. Prescaler ³ 1.PIC16F627A/628A/648A 9. In Asynchronous Counter mode. value FIGURE 9-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L 9.

2. AND TIMER1 Name Bit 7 Bit 6 GIE PEIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE — — Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR Value on all other Resets 0Bh. The TMR1H.2. The special event trigger output of the CCP occurs immediately upon a match between the TMR1H. Only a CCP interrupt is generated (if enabled).2. The special event trigger output also starts an A/D conversion provided that the A/D module is enabled. CCPR1L register pair between the clock edge that generates the special event trigger and the clock edge that generates the TMR1 Reset will preclude the Reset from occuring. Note: Removing the match condition by changing the contents of the CCPR1H. 9. 8Bh. TABLE 9-2: Address REGISTERS ASSOCIATED WITH CAPTURE. 186h 0Eh 0Fh 10h 15h 16h 17h Legend: PIR1 PIE1 TRISB TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON 0000 000x 0000 000u EEIF CMIF EEIE CMIE TMR1IF 0000 -000 0000 -000 TMR1IE 0000 -000 0000 -000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTB Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 x = unknown. an internal hardware trigger is generated. © 2009 Microchip Technology Inc. See Register 9-1. the compare operation may not work. TMR1L register pair and CCPR1H. DS40044G-page 59 . This allows the CCPR1 register pair to effectively be a 16-bit programmable period register for Timer1. Note: Clearing the CCP1CON register will force the RB3/CCP1 compare output latch to the default low level.1 CCP PIN CONFIGURATION 9.2. 18Bh 0Ch 8Ch 86h.4 SPECIAL EVENT TRIGGER The user must configure the RB3/CCP1 pin as an output by clearing the TRISB<3> bit.PIC16F627A/628A/648A 9. CCPR1L register pair. In Asynchronous Counter mode. u = unchanged.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. COMPARE. 9.= unimplemented read as ‘0’. This is not the data latch. In this mode (CCP1M<3:0>=1011). INTCON 10Bh. TMR1L register pair is not reset until the next rising edge of the TMR1 clock. Shaded cells are not used by Capture and Timer1. which may be used to initiate an action.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. .

3.PIC16F627A/628A/648A 9. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. R Comparator When TMR2 is equal to PR2. the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%. This is not the PORTB I/O data latch.1 PWM PERIOD Duty cycle registers CCPR1L The PWM period is specified by writing to the PR2 register. Since the CCP1 pin is multiplexed with the PORTB data latch. the TRISB<3> bit must be cleared to make the CCP1 pin an output. the CCP1 pin produces up to a 10-bit resolution PWM output. PWM frequency is defined as 1/[PWM period].C. A PWM output (Figure 9-4) has a time base (period) and a time that the output stays high (duty cycle).3 “SetUp for PWM Operation”. CCP1 pin and latch D.3 PWM Mode In Pulse Width Modulation (PWM) mode. 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base. The PWM period can be calculated using the following formula: PWM period = [ ( PR2 ) + 1 ] ⋅ 4 ⋅ Tosc ⋅ TMR2 prescale value CCPR1H (Slave) Q RB3/CCP1 TMR2 (1) S TRISB<3> Clear Timer. . see Section 9. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.0 “Timer2 Module”) is not used in the determination of the PWM frequency. FIGURE 9-4: Period PWM OUTPUT Figure 9-3 shows a simplified block diagram of the CCP module in PWM mode.3. The frequency of the PWM is the inverse of the period (frequency = 1/period). the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 8. Comparator PR2 Note 1: DS40044G-page 60 © 2009 Microchip Technology Inc. Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 FIGURE 9-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> 9. For a step by step procedure on how to set up the CCP module for PWM operation.

88 kHz 19. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.e. 8Bh. the period is complete). TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1. Maximum PWM resolution (bits) for a given PWM frequency: Fosc log ⎛ -------------------------------------------------------------⎞ PWM ⎝ F PWM × TMR2 Prescaler⎠ Resolution = -------------------------------------------------------------------------. Make the CCP1 pin an output by clearing the TRISB<3> bit. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) ⋅ Tosc ⋅ TMR2 prescale value CCPR1L and CCP1CON<5:4> can be written to at any time. 4.= unimplemented read as ‘0’. .3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. see the PIC® Mid-Range Reference Manual (DS33023). DS40044G-page 61 .53 kHz 78. Set the PWM period by writing to the PR2 register.PIC16F627A/628A/648A 9. For an example PWM period and duty cycle calculation.3. 2. 186h 11h 92h 12h 15h 16h 17h Legend: PIR1 PIE1 TRISB TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON Timer2 Module’s Register Timer2 Module’s Period Register — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) — — CCP1X CCP1Y x = unknown. the CCP1 pin is cleared. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. This double buffering is essential for glitchless PWM operation. INTCON 10Bh. but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i. © 2009 Microchip Technology Inc. 3. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. u = unchanged.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits.12 kHz 156.22 kHz 4.bits log(2) Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared.. 16) PR2 Value Maximum Resolution (bits) TABLE 9-4: Address Name REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 GIE EEIF EEIE TRISB7 Bit 6 PEIE CMIF CMIE TRISB6 Bit 5 T0IE RCIF RCIE TRISB5 Bit 4 INTE TXIF TXIE TRISB4 Bit 3 RBIE — — TRISB3 Bit 2 T0IF CCP1IF CCP1IE TRISB2 Bit 1 INTF TMR2IF TMR2IE TRISB1 Bit 0 RBIF TMR1IF TMR1IE TRISB0 Value on POR 0000 000x 0000 -000 0000 -000 1111 1111 0000 0000 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx xxxx xxxx CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 Value on all other Resets 0000 000u 0000 -000 0000 -000 1111 1111 0000 0000 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu --00 0000 0Bh. 9. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. CCPR1H is a read-only register.3. 18Bh 0Ch 8Ch 86h. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. Shaded cells are not used by PWM and Timer2. 4.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 6.5 Timer Prescaler (1. In PWM mode.3 kHz 208.

.PIC16F627A/628A/648A NOTES: DS40044G-page 62 © 2009 Microchip Technology Inc.

0 “Voltage Reference Module”) can also be an input to the comparators.connects to RA1 bit 4 bit 3 bit 2-0 CM<2:0>: Comparator Mode bits Figure 10-1 shows the comparator modes and CM<2:0> bit settings Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. DS40044G-page 63 . A block diagram of the comparator is shown in Figure 10-1.connects to RA0 When CM<2:0> = 010 Then: 1 = C1 VIN.connects to RA3 0 = C1 VIN.PIC16F627A/628A/648A 10. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. The CMCON register. REGISTER 10-1: CMCON – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 01Fh) R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 Output inverted 0 = C2 Output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM<2:0>: = 001 Then: 1 = C1 VIN. The on-chip Voltage Reference (Section 11. shown in Register 10-1.0 COMPARATOR MODULE The comparator module contains two analog comparators. controls the comparator input and output multiplexers.connects to RA2 0 = C1 VIN.connects to RA3 C2 VIN.connects to RA0 C2 VIN.

The CMCON register is used to select the mode. See Figure 10-1. . FIGURE 10-1: COMPARATOR I/O OPERATING MODES Comparators Off CM<2:0> = 111 RA0/AN0 C1 Off (Read as ‘0’) RA3/AN3/CMP1 D D VINVIN+ C1 Off (Read as ‘0’) Comparators Reset (POR Default Value) CM<2:0> = 000 RA0/AN0 RA3/AN3/CMP1 A A VINVIN+ RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 Off (Read as ‘0’) RA1/AN1 RA2/AN2/VREF D D VINVIN+ VSS C2 Off (Read as ‘0’) Two Independent Comparators CM<2:0> = 100 RA0/AN0 RA3/AN3/CMP1 A A VINVIN+ C1 C1VOUT Four Inputs Multiplexed to Two Comparators CM<2:0> = 010 RA0/AN0 A CIS = 0 CIS = 1 VINVIN+ VINVIN+ C2 C2VOUT C1 C1VOUT RA3/AN3/CMP1 A RA1/AN1 A A RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 C2VOUT RA2/AN2/VREF CIS = 0 CIS = 1 From VREF Module Two Common Reference Comparators CM<2:0> = 011 RA0/AN0 RA3/AN3/CMP1 A D VINVIN+ C1 C1VOUT Two Common Reference Comparators with Outputs CM<2:0> = 110 RA0/AN0 RA3/AN3/CMP1 A D VINVIN+ C1 C1VOUT RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 C2VOUT RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 C2VOUT RA4/T0CKI/CMP2 Open Drain One Independent Comparator CM<2:0> = 101 RA0/AN0 D VINVIN+ VSS RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 C2VOUT RA1/AN1 RA2/AN2/VREF A A VINVIN+ C2 C2VOUT C1 Off (Read as ‘0’) Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 RA0/AN0 A CIS = 0 CIS = 1 VINVIN+ C1 C1VOUT RA3/AN3/CMP1 D RA3/AN3/CMP1 A A = Analog Input. Note 1: Comparator interrupts should be disabled during a Comparator mode change. Figure 10-1 shows the eight possible modes. port reads zeros always. If the Comparator mode is changed. The TRISA register controls the data direction of the comparator pins for each mode.PIC16F627A/628A/648A 10. DS40044G-page 64 © 2009 Microchip Technology Inc. the comparator output level may not be valid for the specified mode change delay shown in Table 17-2. otherwise a false interrupt may occur. 2: Comparators can have an inverted output. CIS (CMCON<3>) is the Comparator Input Switch. D = Digital Input.1 Comparator Configuration There are eight modes of operation for the comparators.

10. before the comparator output is to have a valid level. the output of the comparator is a digital high level. and the digital output of the comparator is adjusted accordingly (Figure 10-2). the internal voltage reference is applied to the VIN+ pin of both comparators. and can be applied to either pin of the comparator(s). the maximum delay of the internal voltage reference must be considered when using the comparator outputs. 10.PIC16F627A/628A/648A The code example in Example 10-1 depicts the steps required to configure the Comparator module.condition PIR1.10Μs delay CMCON.4 Comparator Response Time An external or internal reference signal may be used depending on the comparator Operating mode.inputs and RA2 as the V+ input to both comparators.Load comparator bits .Init flag register .Global interrupt enable Result 10. the output of the comparator is a digital low level. after selecting a new reference voltage or input source. 10. The shaded areas of the output of the comparator in Figure 10-2 represent the uncertainty due to input offsets and response time.Enable peripheral interrupts INTCON.RP0 MOVLW 0x07 MOVWF TRISA INITIALIZING COMPARATOR MODULE VINVIN+ BCF CALL MOVF BCF BSF BSF BCF BSF BSF 0X20 .RP0 .Mask comparator bits .is compared to the signal at VIN+.Init comparator mode .Store bits in flag register .Select Bank 0 INTCON.CM<2:0> = 011 .Select Bank1 .Set RA<2:0> as inputs .GIE . Otherwise.Select Bank 0 DELAY10 .RP0 . In this mode. contains a detailed description of the Voltage Reference module that provides this signal.Enable comparator interrupts STATUS.CMIE . The internal reference signal is used when the comparators are in mode CM<2:0> = 010 (Figure 10-1).0 “Voltage Reference Module”. RA0 and RA1 are configured as the V.PEIE . DS40044G-page 65 . If the internal reference is changed. the maximum delay of the comparators should be used (Table 17-2.Clear pending interrupts STATUS. FIGURE 10-2: VIN+ VIN- SINGLE COMPARATOR + – Result EXAMPLE 10-1: FLAG_REG EQU CLRF FLAG_REG CLRF PORTA MOVF CMCON. See Table 17-2 for Common Mode voltage.2 Comparator Operation A single comparator is shown in Figure 10-2 along with the relationship between the analog input levels and the digital output.TRISA<7:5> always read ‘0’ STATUS.Init PORTA .F MOVLW 0x03 MOVWF CMCON BSF STATUS.Select Bank 1 PIE1. RA3 and RA4 are configured as digital output.RP0 .RA<4:3> as outputs . When the analog input at VIN+ is less than the analog input VIN-. Section 11.2 INTERNAL REFERENCE SIGNAL The Comparator module also allows the selection of an internally generated voltage reference for the comparators. The reference signal must be between VSS and VDD. page 142).1 EXTERNAL REFERENCE SIGNAL When external voltage references are used.3.Read CMCON to end change . W ANDLW 0xC0 IORWF FLAG_REG. threshold detector applications may require the same reference.3.3 Comparator Reference 10. However. The analog signal that is present at VIN.CMIF .F . Response time is the minimum time. the Comparator module can be configured to have the comparators operate from the same or different reference sources. When the analog input at VIN+ is greater than the analog input VIN-.Initialize data direction . © 2009 Microchip Technology Inc.

Pins configured as digital inputs will convert an analog input. all pins configured as analog inputs will read as a ‘0’. according to the Schmitt Trigger input specification. Figure 10-3 shows the comparator output block diagram. FIGURE 10-3: CnINV To RA3/AN3/CMP1 or RA4/T0CK1/CMP2 pin To Data Bus CMCON<7:6> MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM CnVOUT Q D Q3 EN RD CMCON Set CMIF bit Q D EN CL From other Comparator Reset Q1 DS40044G-page 66 © 2009 Microchip Technology Inc. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. The TRISA bits will still function as an output enable/ disable for the RA3/AN3/CMP1 and RA4/T0CK1/ CMP2 pins while in this mode. When the CM<2:0> = 110 or 001.PIC16F627A/628A/648A 10. . Note 1: When reading the PORT register. These bits are read-only. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. multiplexors in the output path of the RA3 and RA4/T0CK1/CMP2 pins will switch and the output of each pin will be the unsynchronized output of the comparator.5 Comparator Outputs The comparator outputs are read through the CMCON register.

PIR1<6>. If the device wakes up from Sleep. higher Sleep currents than shown in the power-down current specification will occur. Software will need to maintain information about the status of the output bits. 10. © 2009 Microchip Technology Inc. The comparators will be powered-down during the Reset interval. must be between VSS and VDD. A maximum source impedance of 10 kΩ is recommended for the analog sources. such as a capacitor or a Zener diode. This interrupt will wake-up the device from Sleep mode when enabled. is the comparator interrupt flag. The CMIF bit must be reset by clearing ‘0’. If the input voltage deviates from this range by more than 0. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt.PIC16F627A/628A/648A 10. Since the analog pins are connected to a digital output. then the CMIF (PIR1<6>) interrupt flag may not get set. Each comparator that is operational will consume additional current as shown in the comparator specifications. 10. one of the diodes is forward biased and a latch-up may occur. the GIE bit must also be set. This will end the mismatch condition.7 The comparator interrupt flag is set whenever there is a change in the output value of either comparator. a simulated interrupt may be initiated. though the CMIF bit will still be set if an interrupt condition occurs. in the interrupt service routine. In addition.6V in either direction. To minimize power consumption while in Sleep mode. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle). should have very little leakage current.9 A mismatch condition will continue to set flag bit CMIF. If any of these bits are clear. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 10-4.8 Effects of a Reset The user. as read from CMCON<7:6>. This forces the Comparator module to be in the comparator Reset mode. to determine the actual change that has occurred. Device current is minimized when analog inputs are present at Reset time. A device Reset forces the CMCON register to its Reset state. the interrupt is not enabled. turn off the comparators. The analog input therefore. CM<2:0> = 000. the contents of the CMCON register are not affected. CM<2:0> = 111. Clear flag bit CMIF. DS40044G-page 67 . Since it is also possible to write a ‘1’ to this register. Any external component connected to an analog input pin. While the comparator is powered-up. can clear the interrupt in the following manner: a) b) Any write or read of CMCON. the comparator remains active and the interrupt is functional if enabled. they have reverse biased diodes to VDD and VSS. before entering Sleep.6 Comparator Interrupts 10. Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode. This ensures that all potential inputs are analog inputs. The CMIF bit.

= Unimplemented. . 8Bh. 18Bh 0Ch 8Ch 85h Legend: PIR1 PIE1 TRISA CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 x = Unknown.6V VT = 0. read as ‘0’ DS40044G-page 68 © 2009 Microchip Technology Inc. u = Unchanged. INTCON 10Bh.6V RIC ILEAKAGE ±500 nA VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the Pin Interconnect Resistance Source Impedance Analog Voltage TABLE 10-1: Address 1Fh REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 C2OUT GIE EEIF EEIE Bit 6 C1OUT PEIE CMIF CMIE Bit 5 C2INV T0IE RCIF RCIE Bit 4 C1NV INTE TXIF TXIE Bit 3 CIS RBIE — — Bit 2 CM2 T0IF Bit 1 CM1 INTF Bit 0 CM0 RBIF Value on POR Value on All Other Resets Name CMCON 0000 0000 0000 0000 0000 000x 0000 000u 0Bh. .PIC16F627A/628A/648A FIGURE 10-4: ANALOG INPUT MODE VDD RS < 10 K AIN VA CPIN 5 pF VT = 0.

1 Voltage Reference Configuration The Voltage Reference module can output 16 distinct voltage levels for each range. no IDD drain VROE: VREF Output Enable bit 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin VRR: VREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as ‘0’ VR<3:0>: VREF Value Selection bits 0 ≤ VR <3:0> ≤ 15 When VRR = 1: VREF = (VR<3:0>/ 24) * VDD When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.× VDD 24 if VRR = 0: VR <3:0> 1 VREF = ⎛ VDD × --⎞ + ---------------------. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 11-1. The block diagram is given in Figure 11-1.0V.25V with VDD = 5. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3-0 © 2009 Microchip Technology Inc. DS40044G-page 69 . The Voltage Reference module consists of a 16-tap resistor ladder network that provides a selectable voltage reference.PIC16F627A/628A/648A 11. Example 11-1 demonstrates how voltage reference is configured for an output voltage of 1. REGISTER 11-1: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Fh) R/W-0 VREN bit 7 R/W-0 VROE R/W-0 VRR U-0 — R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0 bit 7 VREN: VREF Enable bit 1 = VREF circuit powered on 0 = VREF circuit powered down.0 VOLTAGE REFERENCE MODULE The equations used to calculate the output of the Voltage Reference module are as follows: if VRR = 1: VR <3:0> VREF = ---------------------.× VDD ⎝ 4⎠ 32 The setting time of the Voltage Reference module must be considered when changing the VREF output (Table 17-3). 11.

This Reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). DS40044G-page 70 © 2009 Microchip Technology Inc. is set. To minimize current consumption in Sleep mode. 11.enable VREF . . Figure 11-2 shows an example buffering technique. The tested absolute accuracy of the Voltage Reference module can be found in Table 17-3.4 Effects of a Reset A device Reset disables the Voltage Reference module by clearing bit VREN (VRCON<7>). the contents of the VRCON register are not affected. Due to the limited drive capability.RP0 DELAY10 VOLTAGE REFERENCE CONFIGURATION .2 Voltage Reference Accuracy/Error The full range of VSS to VDD cannot be realized due to the construction of the module. 11.10μs delay 11. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit. 11. are also cleared. VRCON<3:0>. . The transistors on the top and bottom of the resistor ladder network (Figure 11-1) keep VREF from approaching VSS or VDD. Connecting RA2 as a digital output with VREF enabled will also increase current consumption. a buffer must be used in conjunction with the Voltage Reference module output for external connections to VREF.to 2 comps. VRCON<6>.4 Inputs Muxed . The Voltage Reference module is VDD derived and therefore.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time out. the VREF output changes with fluctuations in VDD.go to Bank 1 .5 Connection Considerations The Voltage Reference module operates independently of the Comparator module.outputs . The RA2 pin can be used as a simple D/A output with limited drive capability. The VREF value select bits.go to Bank 0 .RA3-RA0 are . Enabling the Voltage Reference module output onto the RA2 pin with an input signal present will increase current consumption. EXAMPLE 11-1: MOVLW MOVWF BSF MOVLW MOVWF MOVLW MOVWF BCF CALL 0x02 CMCON STATUS. the Voltage Reference module should be disabled.PIC16F627A/628A/648A FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREN 8R R R 16 Stages R R 8R VSS VREF 16-1 Analog Mux VSS VRR VR3 (From VRCON<3:0>) VR0 Note: R is defined in Table 17-3.RP0 0x07 TRISA 0xA6 VRCON STATUS.low range set VR<3:0>=6 .

PIC16F627A/628A/648A FIGURE 11-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE Module VREF R(1) RA2 Op Amp + VREF Output Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration VRCON<3:0> and VRCON<5>.0000 000. read as ‘0’. DS40044G-page 71 .0000 0000 0000 0000 0000 TRISA7 TRISA6 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 . © 2009 Microchip Technology Inc.= Unimplemented. TABLE 11-1: Address 9Fh 1Fh 85h Legend: Name REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Bit 7 VREN C2OUT Bit 6 VROE C1OUT Bit 5 VRR C2INV TRISA5 Bit 4 — C1INV TRISA4 Bit 3 VR3 CIS TRISA3 Bit 2 VR2 CM2 Bit 1 VR1 CM1 Bit 0 VR0 CM0 Value On POR Value On All Other Resets VRCON CMCON TRISA 000.

.PIC16F627A/628A/648A NOTES: DS40044G-page 72 © 2009 Microchip Technology Inc.

Serial EEPROMs. etc. Register 12-1 shows the Transmit Status and Control Register (TXSTA) and Register 12-2 shows the Receive Status and Control Register (RCSTA). REGISTER 12-1: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h) R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as ‘0’ BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of transmit data.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be set in order to configure pins RB2/TX/CK and RB1/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.PIC16F627A/628A/648A 12. The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers. Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as a Serial Communications Interface (SCI). DS40044G-page 73 . read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 © 2009 Microchip Technology Inc. Note 1: SREN/CREN overrides TXEN in SYNC mode. or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits. Can be parity bit.

slave: Unused in this mode CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection. enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection. Synchronous mode . .master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Unused in this mode Synchronous mode Unused in this mode FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of received data (Can be parity bit) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS40044G-page 74 © 2009 Microchip Technology Inc. all bytes are received.PIC16F627A/628A/648A REGISTER 12-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 SPEN bit 7 bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADEN R-0 FERR R-0 OERR R-x RX9D bit 0 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set) 1 = Serial port enabled 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode .

the error in baud rate can be determined.= unimplemented read as ‘0’.PIC16F627A/628A/648A 12. Shaded cells are not used for the BRG. From this. It is a dedicated 8-bit baud rate generator. In Synchronous mode. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared) and ensures the BRG does not wait for a timer overflow before outputting the new baud rate. The data on the RB1/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. Table 12-1 shows the formula for computation of the baud rate for different USART modes.= 0. Example 12-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 Fosc Desired Baud Rate = ----------------------64 ( x + 1 ) 16000000 9600 = ----------------------64 ( x + 1 ) x = 25.1 USART Baud Rate Generator (BRG) EQUATION 12-1: CALCULATING BAUD RATE ERROR The BRG supports both the Asynchronous and Synchronous modes of the USART. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. bit BRGH is ignored. DS40044G-page 75 . bit BRGH (TXSTA<2>) also controls the baud rate. TABLE 12-1: SYNC 0 1 Legend: BAUD RATE FORMULA BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) NA X = value in SPBRG (0 to 255) TABLE 12-2: Address 98h 18h 99h Legend: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 — ADEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR 0000 -010 0000 000x 0000 0000 Value on all other Resets 0000 -010 0000 000x 0000 0000 Name TXSTA RCSTA SPBRG Baud Rate Generator Register x = unknown.16% 9600 It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. which only apply in Master mode (internal clock).= 9615 64 ( 25 + 1 ) (Calculated Baud Rate . © 2009 Microchip Technology Inc. the nearest integer value for the SPBRG register can be calculated using the formula in Table 12-1. .Desired Baud Rate) Error = ---------------------------------------------------------------------------------------------------------Desired Baud Rate 9615 – 9600 = ----------------------------.042 16000000 Calculated Baud Rate = -------------------------. In Asynchronous mode. Given the desired baud rate and FOSC. The SPBRG register controls the period of a free running 8-bit timer.

15 294.4 9.3 1.8 96 300 500 HIGH LOW FOSC = 3.23 76.04 74.1 500 5000 19.991 ERROR — — — +0.24 307.48 316.3 NA 1789.57% — — — SPBRG value (decimal) — — — 92 46 11 8 2 — 0 255 1 MHz KBAUD NA 1.2 76.3 NA 894.15909 MHz KBAUD NA NA NA 9.16% -1.34 NA NA NA 250 0.9 3.57 — — — SPBRG value (decimal) — — — 185 92 22 18 5 — 0 255 5.404 9.906 ERROR — — — +0.73% +0.92 95.96 0 — — BAUD RATE (K) 0.303 1.88 -0.202 2.43 298.2 97.6 19.23% -0.PIC16F627A/628A/648A TABLE 12-3: BAUD RATE (K) 0.579545 MHz KBAUD NA NA NA 9.768 kHz KBAUD 0.16% +0.192 0.16% +0.16% -0.170 NA NA NA NA NA NA NA 8.2 2.2 76.17% 0 — — SPBRG value (decimal) — — — 255 129 32 25 7 4 0 255 FOSC = 20 MHz KBAUD NA NA NA NA 19.90% +3.16% +0.53 ERROR — — — — +1.24 83.8 6.20 298.16% +0.766 ERROR — — — +1.16% +4.3 1.23% +1.69 500 4000 15. .496 ERROR — — — +0.60% — — — SPBRG value (decimal) — — — 131 65 15 12 3 — 0 255 4 MHz KBAUD NA NA NA 9.2 2.82 94.51% — — — — — SPBRG value (decimal) — 207 103 25 12 2 — — — 0 255 32.16% +4.23% +0.2 2.16% -1.57% 0.13% +1.56% 0 — — SPBRG value (decimal) — — — — 207 51 41 12 7 0 255 10 MHz KBAUD NA NA NA 9.57 99.923 1000 NA NA 100 3.4 9.36% +0.3 1.8 NA 1267 4.6 19.0688 MHz KBAUD NA NA NA 9.32 -1.615 19.231 75.17% — — — — SPBRG value (decimal) — — — 103 51 12 9 — — 0 255 BAUD RATE (K) 0.48% — — — — — — — — — SPBRG value (decimal) 26 6 — — — — — — — 0 255 DS40044G-page 76 © 2009 Microchip Technology Inc.14% -2.2 76.4 9.9766 ERROR — +0.16% +0.5 500 2500 9.766 19.73% +0.92 96.615 19.622 19.54% 5.625 ERROR — — — — +0.16% +0.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE SPBRG value (decimal) — — — — 255 64 51 16 9 0 255 16 MHz KBAUD NA NA NA NA 19.2 79.8 96 300 500 HIGH LOW FOSC = 7.24 77.76 96.622 19.6 19.15 312.950 ERROR — — — 0 0 +3.79% +2.16% +0.16% +8.83% -2.032 ERROR +1.53 76.6 19.23 75.

3 1.190 2.2 76.16% +0.232 NA NA NA NA NA NA 15.67% +1.16% +0.93 0.23 83.977 ERROR — +0.13 104.6 19.301 1.63 0.322 18.73V +1.2 2.300 1.16% +0.23% -0.3 1.16% +0.53 78.8 96 300 500 HIGH LOW FOSC = 3.15909 MHz KBAUD NA 1.33 NA NA NA 250 0.2 2.4 9.256 NA NA NA NA NA NA NA NA 0.2 2.17% +1.13% — — — — — SPBRG value (decimal) 255 65 32 7 3 0 — — — 0 255 4 MHz KBAUD 0.202 2.73% — — — — — SPBRG value (decimal) — 129 64 15 7 1 — — — 0 255 FOSC = 20 MHz KBAUD NA 1.8 96 300 500 HIGH LOW FOSC = 7.2 NA NA NA 79.13% 0 0 +3.2 76.221 ERROR — +1.500 3.53 78.16% -6.8 79.32% -2.202 2.4 9.579545 MHz KBAUD 0.221 2.31 1.3 0.23% -0.73% +0.512 0.906 ERROR -0.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) SPBRG value (decimal) — 255 129 32 15 3 2 0 — 0 255 16 MHz KBAUD NA 1.0688 MHz KBAUD 0.437 ERROR — +0.2 2.51% +4.432 9.6 19.766 19.469 19.404 9.3 1.83% +1.2 0.67% — — — — — — — — — — SPBRG value (decimal) 1 — — — — — — — — 0 255 © 2009 Microchip Technology Inc.73% +1.203 2.13 NA NA NA 156.17% — — — BAUD RATE (K) 0.16% +8.2185 ERROR +0.5 NA 312.322 18.6104 ERROR — +0.99% — — — — — — — — SPBRG value (decimal) 51 12 6 — — — — — — 0 255 32.73% +8.16% +0.0020 ERROR -14. DS40044G-page 77 .13% +3.16% -1.16% +1.51% — — — — — SPBRG value (decimal) — 207 103 25 12 2 — — — 0 255 10 MHz KBAUD NA 1.64 NA NA NA NA 111.83% -2.3005 1.PIC16F627A/628A/648A TABLE 12-4: BAUD RATE (K) 0.5 1.4 9.90% -2.0610 ERROR +0.4 9.90% — — — — — — SPBRG value (decimal) — 92 46 11 5 — — — — 0 255 5.36% +1.380 9.404 9.3094 ERROR +3.90% — — — — — — SPBRG value (decimal) 185 46 22 5 2 — — — — 0 255 1 MHz KBAUD 0.9 0.202 2.13% +3.768 kHz KBAUD 0.67% — — — — — — — — SPBRG value (decimal) 207 51 25 — — — — — — 0 255 BAUD RATE (K) 0.9 19.64 NA NA NA NA 55.6 19.2 312.404 9.202 2.404 NA NA NA NA NA NA 62.90% -2.73% +1.615 19.

36% 0 0 0 BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 FOSC = 7.994% 8.36% -1.109% -8.636 250 625 1250 ERROR +0.286 55.36% +1.507% -18.8 223687.525% — — SPBRG value (decimal) 22 11 5 3 1 0 — — 1 MHz KBAUD 8.90% — — — SPBRG value (decimal) 46 22 11 7 3 — — — 5.16% -1.507 — — — — SPBRG value (decimal) 6 2 1 0 — — — — 32.160% -6.385 19230.7% -1.348% -8.068 MHz KBAUD 9598.454 37.77 35714.860 NA NA NA ERROR -0.36% +8.32% -2.913% -2.994% 8.615 19.818 125 NA 625 NA ERROR +0.930 111.308% -2.16% +0.520 19. .29 62500 125000 250000 NA NA ERROR 0.111 250 NA NA ERROR +0.3 31250 62500 NA NA NA NA ERROR -6.25 55921.230 38.913% -2.160% 0.485 18632.16% +2.5 NA NA ERROR 1.878 56.543 18640.75 52791.620% +8.16 MHz KBAUD 9.615 19.768 kHz KBAUD NA NA NA NA NA NA NA NA ERROR NA NA NA NA NA NA NA NA SPBRG value (decimal) NA NA NA NA NA NA NA NA DS40044G-page 78 © 2009 Microchip Technology Inc.35 39593.16% -1.507% 0.615 18.36% -1.348% 26.90% -2.16% +0.818 113.000% — — SPBRG value (decimal) 25 12 6 3 1 0 — — BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 FOSC = 3.51% — 0 — SPBRG value (decimal) 64 32 15 10 4 — 0 — FOSC = 20 MHz KBAUD 9.83% +1.67 105583.939 39.016% -2.63 37281.956% 3.16% +0.461 58.PIC16F627A/628A/648A TABLE 12-5: BAUD RATE (K) 9600 19200 38400 57600 115200 250000 625000 1250000 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) SPBRG value (decimal) 129 64 32 21 10 4 1 0 16 MHz KBAUD 9.90% -2.928 20833.913% -10.062 56.823 111.12% -3.700% — — SPBRG value (decimal) 32 16 7 5 2 0 — — 4 MHz KBAUD 9615.88 111243.3 316750 NA NA ERROR 0.507% 8.579 MHz KBAUD 9725.55% 0 — — SPBRG value (decimal) 103 51 25 16 8 3 — — 10 MHz KBAUD 9.230 37.913% -2.

It will reset only when new data is loaded into the TXREG register. the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. While flag bit TXIF indicated the status of the TXREG register. Asynchronous mode is stopped during Sleep. the TXREG register is empty and flag bit TXIF (PIR1<4>) is set.2.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 12-1. The most common data format is 8-bit. so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. so the user has to poll this bit in order to determine if the TSR register is empty. The TXREG register is loaded with data in software.2 USART Asynchronous Mode In this mode. © 2009 Microchip Technology Inc. The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN.PIC16F627A/628A/648A 12. The USART transmits and receives the LSb first. A dedicated 8-bit baud rate generator is used to derive baud rate frequencies from the oscillator. As a result the RB2/TX/CK pin will revert to high-impedance. Once the TXREG register transfers the data to the TSR register (occurs in one TCY). another bit TRMT (TXSTA<1>) shows the status of the TSR register. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). but can be implemented in software (and stored as the ninth data bit). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The actual transmission will not occur until the TXREG register has been loaded with data and the Baud Rate Generator (BRG) has produced a shift clock (Figure 12-1). The ninth bit must be written before writing the 8-bit data to the TXREG register. The shift register obtains its data from the read/write transmit buffer. The baud rate generator produces a clock either x16 or x64 of the bit shift rate. TXREG. Normally when transmission is first started. 2: Flag bit TXIF is set when enable bit TXEN is set. depending on bit BRGH (TXSTA<2>). No interrupt logic is tied to this bit. the TSR is loaded with new data from the TXREG register (if available). As soon as the Stop bit is transmitted. The USART Asynchronous module consists of the following important elements: • • • • Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Transmission is enabled by setting enable bit TXEN (TXSTA<5>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. DS40044G-page 79 . In such a case. the USART uses standard non-return-tozero (NRZ) format (one Start bit. In order to select 9-bit transmission. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). but use the same data format and baud rate. A backto-back transfer is thus possible (Figure 12-3). transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The TSR register is not loaded until the Stop bit has been transmitted from the previous load. eight or nine data bits and one Stop bit). The heart of the transmitter is the Transmit (serial) Shift Register (TSR). an incorrect ninth data bit may be loaded in the TSR register. 12. Status bit TRMT is a read-only bit which is set when the TSR register is empty. This interrupt can be enabled/ disabled by setting/clearing enable bit TXIE ( PIE1<4>). The USART’s transmitter and receiver are functionally independent. Parity is not supported by the hardware.

3. DS40044G-page 80 © 2009 Microchip Technology Inc. . when required. If 9-bit transmission is selected.1 “USART Baud Rate Generator (BRG)”). Output drive. 2. 4. then set transmit bit TX9. set bit BRGH. If a high-speed baud rate is desired. (Section 12. 5. which will also set bit TXIF. If 9-bit transmission is desired. Initialize the SPBRG register for the appropriate baud rate. 6. Load data to the TXREG register (starts transmission). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. empty flag) ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit TRMT bit (Transmit shift reg. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. FIGURE 12-2: Write to TXREG BRG output (shift clock) RB2/TX/CK (pin) TXIF bit (Transmit buffer reg. is controlled by the peripheral circuitry.PIC16F627A/628A/648A FIGURE 12-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN TXREG register 8 ² ² ² TSR register LSb 0 Pin Buffer and Control RB2/TX/CK pin Follow these steps when setting up an Asynchronous Transmission: 1. empty flag) Word 1 Transmit Shift Reg. 7. the ninth bit should be loaded in bit TX9D. then set enable bit TXIE. 8. If interrupts are desired. Enable the transmission by setting bit TXEN.

empty flag) . DS40044G-page 81 . TABLE 12-6: Address 0Ch 18h 19h 8Ch 98h 99h Legend: Name PIR1 RCSTA PIE1 TXSTA REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF SREN RCIE TXEN Bit 4 TXIF CREN TXIE SYNC Bit 3 — ADEN — — Bit 2 CCP1IF FERR CCP1IE BRGH Bit 1 TMR2IF OERR TMR2IE TRMT Bit 0 TMR1IF RX9D TMR1IE TX9D Value on POR 0000 -000 0000 000x 0000 0000 0000 -000 0000 -010 0000 0000 Value on all other Resets 0000 -000 0000 000x 0000 0000 0000 -000 0000 -010 0000 0000 TXREG USART Transmit Data Register SPBRG Baud Rate Generator Register x = unknown. flag) Word 1 Word 2 ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 TRMT bit (Transmit shift reg. Note: This timing diagram shows two consecutive transmissions. Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. .PIC16F627A/628A/648A FIGURE 12-3: Write to TXREG BRG output (shift clock) RB2/TX/CK (pin) TXIF bit (interrupt reg.= unimplemented locations read as ‘0’. Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.

whereas the main receive serial shifter operates at the bit rate or at FOSC. This is done by resetting the receive logic (CREN is cleared and then set). Flag bit RCIF is a read-only bit. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. flag bit RCIF (PIR1<5>) is set. therefore it is essential for the user to read the RCSTA register before reading RCREG register in order not to lose the old FERR and RX9D information.. FIGURE 12-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN SPBRG Baud Rate Generator ÷ 64 or ÷ 16 MSb Stop (8) 7 FERR OERR RSR register • • • 1 LSb 0 Start RB1/RX/DT Pin Buffer and Control Data Recovery RX9 8 SPEN RX9 ADEN RX9 ADEN RSR<8> Enable Load of Receive Buffer 8 RX9D RX9D RCREG register RCREG register 8 FIFO Interrupt RCIF RCIE Data Bus DS40044G-page 82 © 2009 Microchip Technology Inc. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>).2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 12-4. The RCREG is a double buffered register (i. If the transfer is complete.e. the received data in the RSR is transferred to the RCREG register (if it is empty). On the detection of the Stop bit of the third byte. . When Asynchronous mode is selected. it is a two-deep FIFO). The data is received on the RB1/RX/DT pin and drives the data recovery block. if the RCREG register is still full. transfers from the RSR register to the RCREG register are inhibited. After sampling the Stop bit. reception is enabled by setting bit CREN (RCSTA<4>). Bit FERR and the 9th receive bit are buffered the same way as the receive data. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate. then overrun error bit OERR (RCSTA<1>) will be set.2. will load bits RX9D and FERR with new values. It is cleared when the RCREG register has been read and is empty. Reading the RCREG.PIC16F627A/628A/648A 12. The heart of the receiver is the Receive (serial) Shift Register (RSR). so it is essential to clear error bit OERR if it is set. which is cleared by the hardware. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. The word in the RSR will be lost. Framing error bit FERR (RCSTA<2>) is set if a Stop bit is detected as clear. If bit OERR is set.

Address Byte Word 1 RCREG bit 8 = 0. DS40044G-page 83 . The data byte is not read into the RCREG (receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0. and was cleared to a ‘0’. © 2009 Microchip Technology Inc. The data byte is read into the RCREG (Receive Buffer) because ADEN was updated after an address match. Data Byte bit 8 = 1. The data byte is not read into the RCREG (Receive Buffer) because ADEN = 1 and bit 8 = 0. Address Byte Word 1 RCREG bit 8 = 0. FIGURE 12-6: RB1/RX/DT (pin) RCV Shift Reg RCV Buffer Reg Read RCV Buffer Reg RCREG RCIF (Interrupt Flag) ADEN = 1 (Address Match Enable) ‘1’ ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit bit 8 = 1. Data Byte Word 2 RCREG Note: This timing diagram shows an address byte followed by an data byte. Address Byte Word 1 RCREG ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit Note: This timing diagram shows a data byte followed by an address byte. so the contents of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.PIC16F627A/628A/648A FIGURE 12-5: RB1/RX/DT (Pin) RCV Shift Reg RCV Buffer Reg Read RCV Buffer Reg RCREG RCIF (interrupt flag) ADEN = 1 (Address Match Enable) ‘1’ ‘1’ bit 8 = 0. FIGURE 12-7: RB1/RX/DT (pin) RCV Shift Reg RCV Buffer Reg Read RCV Buffer Reg RCREG RCIF (Interrupt Flag) ADEN (Address Match Enable) ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY VALID DATA BYTE Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit bit 8 = 1. Data Byte ‘1’ Note: This timing diagram shows an address byte followed by an data byte.

6. . 4. clear the error by clearing enable bit CREN. (Section 12. 10. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. If a high-speed baud rate is desired.1 “USART Baud Rate Generator (BRG)”). Shaded cells are not used for asynchronous reception. If interrupts are desired. when required. DS40044G-page 84 © 2009 Microchip Technology Inc.= unimplemented locations read as ‘0’. Enable the reception by setting bit CREN. If 9-bit reception is desired. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. 9. 3. then set enable bit RCIE. Initialize the SPBRG register for the appropriate baud rate. 2. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.PIC16F627A/628A/648A Follow these steps when setting up an Asynchronous Reception: 1. Read the 8-bit received data by reading the RCREG register. . 5. then set bit RX9. is controlled by the peripheral circuitry. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. TABLE 12-7: Address 0Ch 18h 1Ah 8Ch 98h 99h Legend: Name PIR1 RCSTA PIE1 TXSTA REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF SREN RCIE TXEN Bit 4 TXIF CREN TXIE SYNC Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 RCREG USART Receive Data Register SPBRG Baud Rate Generator Register x = unknown. 7. 8. set bit BRGH. Output drive. If an OERR error occurred.

all data bytes are ignored. Multiprocessor communication is enabled by setting the ADEN bit (RCSTA<3>) along with the RX9 bit. Set bit RX9 to enable 9-bit reception. when required.3 12. Reception is (RCSTA<4>). When ADEN is enabled (= 1). If a high-speed baud rate is desired. . 2. 9. so that the slave can examine the received byte to see if it is being addressed. the slave will be interrupted and the contents of the RSR register will be transferred into the receive buffer. enabling multiprocessor communication. Enable the reception by setting enable bit CREN or SREN. indicating that the received byte is an address. When ADEN is disabled (= 0). This feature can be used in a multiprocessor system as follows: A master processor intends to transmit a block of data to one of many slaves.1 USART Address Detect Function USART 9-BIT RECEIVER WITH ADDRESS DETECT The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = 1). The USART module has a special provision for multiprocessor communication. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. 10. then set enable bit RCIE. 11. 8. It must first send out an address byte that identifies the target slave. and no interrupt will occur. clear the ADEN and RCIF bits to allow data bytes and address bytes to be read into the receive buffer and interrupt the CPU. is controlled by the peripheral circuitry. The addressed slave will then clear its ADEN bit and prepare to receive data bytes from the master. Set ADEN to enable address detect. TABLE 12-8: Address 0Ch 18h 1Ah 8Ch 98h 99h Name PIR1 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF SREN RCIE TXEN Bit 4 TXIF CREN TXIE SYNC Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 RCSTA PIE1 TXSTA RCREG USART Receive Data Register SPBRG Baud Rate Generator Register Legend: x = unknown. An address byte is identified by setting the ninth bit (RSR<8>) to a ‘1’ (instead of a ‘0’ for a data byte). the previous data byte will be lost. if the ninth received bit is equal to a ‘1’. DS40044G-page 85 . Read the 8-bit received data by reading the RCREG register to determine if the device is being addressed.3. the data will not be loaded into the receive buffer. If interrupts are desired.1 Setting up 9-bit mode with Address Detect Follow these steps when setting up Asynchronous Reception with Address Detect Enabled: 1.PIC16F627A/628A/648A 12. Initialize the SPBRG register for the appropriate baud rate. 6. However. Following the Stop bit. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. all data bytes are received and the 9th bit can be used as the parity bit. The receive block diagram is shown in Figure 12-4. enabled by setting bit CREN When the RX9 bit is set in the RCSTA register. If another byte is shifted into the RSR register. and the receive interrupt is set if and only if RSR<8> = 1. the ninth bit of the RSR (RSR<8>) is transferred to RX9D. 5. 3. Output drive. The port is now programmed such that when the last bit is received. This allows the slave to be interrupted only by addresses. set bit BRGH. Enable asynchronous communication by setting or clearing bit SYNC and setting bit SPEN. 9 bits are received and the ninth bit is placed in the RX9D bit of the RCSTA register. clear the error by clearing enable bit CREN if it was already set. 4. 7.1. If the ADEN and RX9 bits are set in the slave’s RCSTA register. If the device has been addressed (RSR<8> = 1 with address match enabled). all data bytes will be ignored. 12. the contents of the Receive Shift Register (RSR) are transferred to the receive buffer. If an OERR error occurred.= unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.3. © 2009 Microchip Technology Inc.

In Synchronous Master mode. The shift register obtains its data from the read/write transmit buffer register. when transmission is first started. Data out is stable around the falling edge of the synchronous clock (Figure 12-8). the transmission is aborted and the DT pin reverts to a high-impedance state (for a reception). Setting enable bit TXEN will start the BRG. Back-to-back transfers are possible. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. DS40044G-page 86 © 2009 Microchip Technology Inc. Follow these steps when setting up a Synchronous Master Transmission: 1. The ninth bit must be written before writing the 8-bit data to the TXREG register. then after the single word is received. bit TXEN should be cleared. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). CREN and SREN are clear. If 9-bit transmission is desired. since the BRG is kept in Reset when bits TXEN. 7. the TSR is loaded with new data from the TXREG (if available). so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. The TSR is not mapped in data memory so it is not available to the user. the reception is inhibited and vice versa. When transmitting data. The transmitter logic however is not reset although it is disconnected from the pins. The TSR register is not loaded until the last bit has been transmitted from the previous load. so the user has to poll this bit in order to determine if the TSR register is empty. 5. Initialize the SPBRG register for the appropriate baud rate (Section 12. It will reset only when new data is loaded into the TXREG register. Start each transmission by loading data to the TXREG register. The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 12-9). creating a shift clock immediately. 6. then set bit TX9. If interrupts are desired. While flag bit TXIF indicates the status of the TXREG register.PIC16F627A/628A/648A 12. 8. If the TSR was empty and the TXREG was written before writing the “new” TX9D. 2. In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RB2/TX/CK and RB1/RX/DT I/O pins to CK (clock) and DT (data) lines.4 USART Synchronous Master Mode Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. respectively. If either bit CREN or bit SREN is set during a transmission. SPEN and CSRC. This is advantageous when slow baud rates are selected. transmission and reception do not occur at the same time). the data is transmitted in a half-duplex manner (i.4. 4. The heart of the transmitter is the Transmit (serial) Shift Register (TSR).e. TRMT is a read-only bit which is set when the TSR is empty. bit SREN will be cleared and the serial port will revert back to transmitting since bit TXEN is still set. the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The DT and CK pins will revert to highimpedance. Normally. Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle). is controlled by the peripheral circuitry. If 9-bit transmission is selected. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). As soon as the last bit is transmitted. The Master mode indicates that the processor transmits the master clock on the CK line.1 “USART Baud Rate Generator (BRG)”). then set enable bit TXIE. No interrupt logic is tied to this bit. The DT line will immediately switch from high-impedance Receive mode to transmit and start driving. another bit TRMT (TXSTA<1>) shows the status of the TSR register.1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 12-1. To avoid this. The CK pin will remain an output if bit CSRC is set (internal clock). TXIF (PIR1<4>) is set. TXREG. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. The Master mode is entered by setting bit CSRC (TXSTA<7>). In order to reset the transmitter. The actual transmission will not occur until the TXREG register has been loaded with data. 3. the “present” value of bit TX9D is loaded. . Enable the transmission by setting bit TXEN. the TSR register is empty. when required. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Output drive. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). Enable the synchronous master serial port by setting bits SYNC. The TXREG register is loaded with data in software. 12. the user has to clear bit TXEN. In order to select 9-bit transmission. If bit SREN is set (to interrupt an on-going transmission and receive a single word). the ninth bit should be loaded in bit TX9D.. Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. the TXREG is empty and interrupt bit.

read as ‘0’. Continuous transmission of two 8-bit words.= unimplemented. . FIGURE 12-8: SYNCHRONOUS TRANSMISSION Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 bit 7 bit 0 bit 1 Word 2 bit 7 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RB1/RX/DT pin RB2/TX/CK pin Write to TXREG Reg Write Word 1 TXIF bit (Interrupt Flag) TRMT TRMT bit Write Word 2 bit 0 bit 1 Word 1 bit 2 ‘1’ TXEN bit ‘1’ Note: Sync Master Mode. SPBRG = 0. FIGURE 12-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit 0 bit 1 bit 2 bit 6 bit 7 RB1/RX/DT pin RB2/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit © 2009 Microchip Technology Inc.PIC16F627A/628A/648A TABLE 12-9: Address 0Ch 18h 19h 8Ch 98h 99h Legend: Name PIR1 RCSTA PIE1 TXSTA REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF Bit 4 TXIF Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 0000 -000 0000 000x 0000 0000 0000 -000 0000 -010 0000 0000 CCP1IF TMR2IF TMR1IF 0000 -000 FERR OERR RX9D 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 -000 BRGH TRMT TX9D 0000 -010 0000 0000 SREN CREN RCIE TXIE TXREG USART Transmit Data Register TXEN SYNC SPBRG Baud Rate Generator Register x = unknown. Shaded cells are not used for synchronous master transmission. DS40044G-page 87 .

interrupt flag bit RCIF (PIR1<5>) is set.= unimplemented read as ‘0’. then overrun error bit OERR (RCSTA<1>) is set.1 “USART Baud Rate Generator (BRG)”). will load bit RX9D with a new value. . The 9th receive bit is buffered the same way as the receive data. Ensure bits CREN and SREN are clear. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. when required. Output drive. When the transfer is complete. In this case. Reading the RCREG register.e. the reception is continuous until CREN is cleared. therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. Enable the synchronous master serial port by setting bits SYNC. If an OERR error occurred. 10. so it is essential to clear bit OERR if it is set. Once Synchronous mode is selected. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). 6. The RCREG is a double buffered register (i. transfers from the RSR to the RCREG are inhibited. Shaded cells are not used for synchronous master reception. is controlled by the peripheral circuitry.4. If enable bit SREN is set.2 USART SYNCHRONOUS MASTER RECEPTION Follow these steps when setting up a Synchronous Master Reception: 1. Bit OERR has to be cleared in software (by clearing bit CREN). Initialize the SPBRG register for the appropriate baud rate. set bit SREN. 3.. 9. it is reset when the RCREG register has been read and is empty. TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Address 0Ch 18h 1Ah 8Ch 98h 99h Legend: Name PIR1 RCSTA PIE1 TXSTA Bit 7 EEIF SPEN EPIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF Bit 4 TXIF Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on: POR Value on all other Resets 0000 -000 0000 000x 0000 0000 -000 -000 0000 -010 0000 0000 CCP1IF TMR2IF TMR1IF 0000 -000 FERR OERR RX9D 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE -000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 SREN CREN RCIE TXIE RCREG USART Receive Data Register TXEN SYNC SPBRG Baud Rate Generator Register x = unknown. SPEN and CSRC. . If interrupts are desired. 2. (Section 12. For continuous reception. the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). If bit OERR is set. 5. The RCREG register can be read twice to retrieve the two bytes in the FIFO. 4. If both bits are set. If enable bit CREN is set. it is a twodeep FIFO). then only a single word is received. After clocking the last bit. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. If a single reception is required. 8. then set bit RX9. If 9-bit reception is desired. set bit CREN. then CREN takes precedence. Read the 8-bit received data by reading the RCREG register. clear the error by clearing bit CREN. then set enable bit RCIE. The word in the RSR will be lost. Data is sampled on the RB1/RX/DT pin on the falling edge of the clock. 7. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. Flag bit RCIF is a read-only bit which is reset by the hardware. On the clocking of the last bit of the third byte. reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>).PIC16F627A/628A/648A 12. 11. if the RCREG register is still full. DS40044G-page 88 © 2009 Microchip Technology Inc.

then set enable bit TXIE. the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. If enable bit TXIE is set. DS40044G-page 89 . the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. 8. If interrupts are desired. 7. This allows the device to transfer or receive data while in Sleep mode. is controlled by the peripheral circuitry.PIC16F627A/628A/648A FIGURE 12-10: SYNCHRONOUS RECEPTION (MASTER MODE. 2. Flag bit TXIF will not be set. If 9-bit transmission is selected. the interrupt will wake the chip from Sleep and if the global interrupt is enabled. Start transmission by loading data to the TXREG register. If 9-bit transmission is desired. Clear bits CREN and SREN. SREN) Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 RB1/RX/DT pin RB2/TX/CK pin WRITE to Bit SREN bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SREN bit CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 12. when required. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. Enable the transmission by setting enable bit TXEN. 3. If two words are written to the TXREG and then the SLEEP instruction is executed. 4. Slave mode is entered by clearing bit CSRC (TXSTA<7>).1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical except in the case of the Sleep mode. the ninth bit should be loaded in bit TX9D.5 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RB2/TX/CK pin (instead of being supplied internally in Master mode). Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. 5. 6. the program will branch to the interrupt vector (0004h). e) © 2009 Microchip Technology Inc. Follow these steps when setting up a Synchronous Slave Transmission: 1.5. When the first word has been shifted out of TSR. ‘0’ ‘0’ 12. The second word will remain in TXREG register. then set bit TX9. Output drive.

= unimplemented read as ‘0’. On completely receiving the word. clear the error by clearing bit CREN.2 USART SYNCHRONOUS SLAVE RECEPTION Follow these steps when setting up a Synchronous Slave Reception: 1. Shaded cells are not used for synchronous slave transmission. 2. If interrupts are desired. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. 6. 8. when required. then a word may be received during Sleep. If receive is enabled by setting bit CREN prior to the SLEEP instruction. If 9-bit reception is desired. 3.5. 4. the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set. is controlled by the peripheral circuitry. the interrupt generated will wake the chip from Sleep. set enable bit CREN. If an OERR error occurred. Flag bit RCIF will be set when reception is complete and an interrupt will be generated. TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Address 0Ch 18h 1Ah 8Ch 98h 99h Name PIR1 RCSTA PIE1 TXSTA Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF Bit 4 TXIF Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 0000 -000 0000 000x 0000 0000 0000 -000 0000 -010 0000 0000 CCP1IF TMR2IF TMR1IF 0000 -000 FERR OERR RX9D 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 -000 BRGH TRMT TX9D 0000 -010 0000 0000 SREN CREN RCIE TXIE RCREG USART Receive Data Register TXEN SYNC SPBRG Baud Rate Generator Register Legend: x = unknown. Output drive. . then set enable bit RCIE.= unimplemented read as ‘0’. then set bit RX9. Shaded cells are not used for synchronous slave reception. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. DS40044G-page 90 © 2009 Microchip Technology Inc. if enable bit RCIE was set. TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address 0Ch 18h 19h 8Ch 98h 99h Legend: Name PIR1 RCSTA PIE1 TXSTA Bit 7 EEIF SPEN EEIE CSRC Bit 6 CMIF RX9 CMIE TX9 Bit 5 RCIF Bit 4 TXIF Bit 3 — ADEN — — Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 0000 -000 0000 000x 0000 0000 0000 -000 0000 -010 0000 0000 CCP1IF TMR2IF TMR1IF 0000 -000 FERR OERR RX9D 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 -000 BRGH TRMT TX9D 0000 -010 0000 0000 SREN CREN RCIE TXIE TXREG USART Transmit Data Register TXEN SYNC SPBRG Baud Rate Generator Register x = unknown. 9. 5. To enable reception. bit SREN is a “don’t care” in Slave mode.PIC16F627A/628A/648A 12. Also. the program will branch to the interrupt vector (0004h). TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. . 7. If the global interrupt is enabled. . The operation of the Synchronous Master and Slave modes is identical except in the case of the Sleep mode.

This memory is not directly mapped in the register file space. When the device is code-protected. PIC16F627A/628A devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. A byte write automatically erases the location and writes the new data (erase before write). DS40044G-page 91 . as well as from chip-to-chip. The PIC16F648A device has 256 bytes of data EEPROM with an address range from 0h to FFh. Instead it is indirectly addressed through the Special Function Registers (SFRs).PIC16F627A/628A/648A 13.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). Please refer to AC specifications for exact limits. The EEPROM data memory is rated for high erase/write cycles. Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. There are four SFRs used to read and write this memory. These registers are: • • • • EECON1 EECON2 (Not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. the CPU can continue to read and write the data EEPROM memory. The write time will vary with voltage and temperature. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown REGISTER 13-2: EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh) R/W-x EADR7 bit 7 R/W-x EADR6 R/W-x EADR5 R/W-x EADR4 R/W-x EADR3 R/W-x EADR2 R/W-x EADR1 R/W-x EADR0 bit 0 bit 7 PIC16F627A/628A Unimplemented Address: Must be set to ‘0’ PIC16F648A EEADR: Set to ‘1’ specifies top 128 locations (128-255) of EEPROM Read/Write Operation bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The write time is controlled by an on-chip timer. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. REGISTER 13-1: EEDATA – EEPROM DATA REGISTER (ADDRESS: 9Ah) R/W-x EEDAT7 bit 7 R/W-x EEDAT6 R/W-x EEDAT5 R/W-x EEDAT4 R/W-x EEDAT3 R/W-x R/W-x R/W-x EEDAT0 bit 0 EEDAT2 EEDAT1 bit 7-0 EEDATn: Byte value to Write to or Read from data EEPROM memory location. A device programmer can no longer access this memory. Additional information on the data EEPROM is available in the PIC® Mid-Range Reference Manual (DS33023).

This means that this bit should always be ‘0’ to ensure that the address is in the 128 byte memory space. The inability to clear the WR bit in software prevents the accidental. (The bit is cleared by hardware once write is complete. premature termination of a write operation. On power-up. following Reset. All eight bits in the register (EEADR<7:0>) are required. They are cleared in hardware at completion of the read or write operation. The WREN bit. only set. The RD bit can only be set (not cleared) in software).2 EECON1 and EECON2 Registers The PIC16F648A EEADR register addresses 256 bytes of data EEPROM. REGISTER 13-3: EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 9Ch) U-0 — bit 7 U-0 — U-0 — U-0 — R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 bit 7-4 bit 3 Unimplemented: Read as ‘0’ WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset. This bit must be cleared in software. . The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation.1 EEADR 13. in software. the user can check the WRERR bit and rewrite the location. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 2 bit 1 bit 0 DS40044G-page 92 © 2009 Microchip Technology Inc.PIC16F627A/628A/648A 13. Control bits RD and WR initiate read and write. The upper bit is address decoded. respectively. EECON2 is not a physical register. The EECON2 register is used exclusively in the data EEPROM write sequence. RD is cleared in hardware. EECON1 is the control register with four low order bits physically implemented. In these situations. The upper-four bits are nonexistent and read as ‘0’s. when set. 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. The PIC16F627A/628A EEADR register addresses only the first 128 bytes of data EEPROM so only seven of the eight bits in the register (EEADR<6:0>) are required. The data and address will be unchanged in the EEDATA and EEADR registers. Reading EECON2 will read all ‘0’s. any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = initiates a write cycle. Interrupt flag bit EEIF in the PIR1 register is set when write is complete. will allow a write operation. These bits cannot be cleared. 0 = Does not initiate an EEPROM read Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The WR bit can only be set (not cleared) in software. the WREN bit is clear.

To read a data memory location. Any number that is not equal to the required cycles to execute the required sequence will cause the data not to be written into the EEPROM.EE Read . EEDATA will hold this value until another read or until it is written to by the user (during a write operation). power glitch or software malfunction. Also when enabled.PIC16F627A/628A/648A 13. EXAMPLE 13-2: BSF BSF BCF BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF DATA EEPROM WRITE . the user must write the address to the EEADR register and then set control bit RD (EECON1<0>).6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. Write error . the WREN bit in EECON1 must be set to enable write.4 Writing to the EEPROM Data Memory STATUS. the user must first write the address to the EEADR register and the data to the EEDATA register.Set WR bit . The user should keep the WREN bit clear at all times. DS40044G-page 93 . W STATUS. Z GOTO WRITE_ERR : : STATUS. RP0 Depending on the application.WR 13. WREN is cleared. EXAMPLE 13-3: BSF MOVF BSF WRITE VERIFY 13.Address to read . On power-up. 13. Then the user must follow a specific sequence to initiate the write for each byte. The WR bit will be inhibited from being set unless the WREN bit is set.5 Write Verify EXAMPLE 13-1: BSF MOVLW MOVWF BSF MOVF BCF DATA EEPROM READ .Disable INTs.Write 55h . The EEIF bit in the PIR1 registers must be cleared by software. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out. We strongly recommend that interrupts be disabled during this code segment.Read the . RP0 CONFIG_ADDR EEADR EECON1.Is the value written . The WREN bit is not cleared by hardware. . RD . the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. Additionally.begin write . GIE The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2.Enable INTs. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i. After a write sequence has been initiated.e. To protect against spurious EEPROM writes..See AN576 . the Power-up Timer (72 ms duration) prevents EEPROM write. GIE INTCON. RP0 . write AAh to EECON2. The data is available.Bank 1 EEDATA.Write AAh . good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 13-3) to the desired value to be written. various mechanisms have been built-in. except when updating EEPROM. . The user can either enable this interrupt or poll this bit. then set WR bit) for each byte. .read (in EEDATA) the .Bank 1 .3 Reading the EEPROM Data Memory At the completion of the write cycle. . in the EEDATA register. in the very next cycle.Enable write . SUBWF EEDATA.value written (in W reg) and same? . © 2009 Microchip Technology Inc. W BTFSS STATUS. RP0 EECON1. .Bank 0 STATUS. This should be used in applications where an EEPROM bit will be stressed near the specification limit.YES. . therefore it can be read in the next instruction.Is difference 0? .NO. lost programs). W EECON1.W = EEDATA . . Good write . RD EEDATA.Continue program To write an EEPROM data location. WREN INTCON.GIE $-2 55h EECON2 AAh EECON2 EECON1. A cycle count is executed during the required sequence.Bank 1 . Required Sequence BSF INTCON. clearing the WREN bit will not affect this write cycle.

Note: If data EEPROM is only used to store constants and/or data that changes rarely. For this reason. it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A).retrieve data into EEDATA . EXAMPLE 13-4: BANKSEL CLRF BCF BTFSC GOTO BSF Loop BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC GOTO DATA EEPROM REFRESH ROUTINE 0X80 EEADR INTCON. byte addressable array that has been optimized for the storage of frequently changing information (e.. See specification D124. an array refresh is likely not required. 7 . If this is the case.7 Using the Data EEPROM The data EEPROM is a high endurance.128 bytes in 16F627A/628A .2 EECON1.enable EE writes .. etc.test for end of memory . A simple data EEPROM refresh routine is shown in Example 13-4..PIC16F627A/628A/648A 13.end of conditional assembly .1 ...disable EE writes .. required sequence . WR EECON1. variables that change infrequently (such as constants. IDs.wait for write complete #IFDEF __16F648A INCFSZ #ELSE INCF BTFSS #ENDIF GOTO BCF BSF EEADR.repeat for all locations . WR $ . . required sequence .see AN576 .next address . GIE INTCON. calibration.first step of .second step of . WREN INTCON... RD 0x55 EECON2 0xAA EECON2 EECON1..enable interrupts (optional) Loop EECON1. f EEADR..256 bytes in 16F648A . . program variables or other data that are updated often).. When variables in one section change frequently. while variables in another section do not change.g.select Bank1 . then an array refresh must be performed. GIE $ . f EEADR.start write sequence . WREN EECON1.) should be stored in Flash program memory.test for end of memory . GIE DS40044G-page 94 © 2009 Microchip Technology Inc.disable interrupts .start at address 0 . .

Shaded cells are not used by data EEPROM. TABLE 13-1: Address 9Ah 9Bh 9Ch REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset xxxx xxxx xxxx xxxx ---. u = unchanged.PIC16F627A/628A/648A 13. q = value depends upon condition.x000 Value on all other Resets uuuu uuuu uuuu uuuu ---.q000 ---.8 Data EEPROM Operation During Code-Protect When the device is code-protected. Note 1: EECON2 is not a physical register. . the CPU is able to read and write data to the data EEPROM. © 2009 Microchip Technology Inc.---- Name EEDATA EEADR EECON1 EEPROM Data Register EEPROM Address Register — — — — WRERR WREN WR RD ---. DS40044G-page 95 .---9Dh EECON2(1) EEPROM Control Register 2 Legend: x = unknown.= unimplemented read as ‘0’.

.PIC16F627A/628A/648A NOTES: DS40044G-page 96 © 2009 Microchip Technology Inc.

6. 4. OSC selection Reset Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Brown-out Reset (BOR) Interrupts Watchdog Timer (WDT) Sleep Code protection ID Locations In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A has a Watchdog Timer which is controlled by configuration bits. Several oscillator options are also made available to allow the part to fit the application. The user can wake-up from Sleep through external Reset. There is also circuitry to reset the device if a brown-out occurs. It runs off its own RC oscillator for added reliability. One is the Oscillator Start-up Timer (OST). These bits are mapped in program memory location 2007h. The PIC16F627A/628A/648A family has a host of such features intended to maximize system reliability. The Sleep mode is designed to offer a very low current Power-down mode. 7. 11. © 2009 Microchip Technology Inc. The user will note that address 2007h is beyond the user program memory space. There are two timers that offer necessary delays on power-up. which provides a fixed delay of 72 ms (nominal) on power-up only. 8. 12. 5. A set of configuration bits are used to select various options. most applications need no external Reset circuitry. The RC oscillator option saves system cost while the LP crystal option saves power. Watchdog Timer wake-up or through an interrupt.0 SPECIAL FEATURES OF THE CPU 14. Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. DS40044G-page 97 . which can be accessed only during programming. 3. These are: 1. designed to keep the part in Reset while the power supply stabilizes. 9. The other is the Power-up Timer (PWRT). See “PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196) for additional information. 2. minimize cost through elimination of external components. In fact. With these three functions on-chip. 10. provide power-saving operating modes and offer code protection. intended to keep the chip in Reset until the crystal oscillator is stable.PIC16F627A/628A/648A 14. it belongs to the special configuration memory space (2000h-3FFFh).1 Configuration Bits The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations.

HV on MCLR must be used for programming BOREN: Brown-out Reset Enable bit (1) 1 = BOR Reset enabled 0 = BOR Reset disabled MCLRE: RA5/MCLR/VPP Pin Function Select bit 1 = RA5/MCLR/VPP pin function is MCLR 0 = RA5/MCLR/VPP pin function is digital Input. read as ‘0’ ‘0’ = bit is cleared x = bit is unknown DS40044G-page 98 © 2009 Microchip Technology Inc. MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits(4) 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin. turning the code protection off. . CLKIN on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN Note 1: 2: bit 0 bit 12-9: bit 8: bit 7: bit 6: bit 5: bit 3: bit 2: bit 4. I/O function on RA7/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin. low-voltage programming enabled 0 = RB4/PGM is digital I/O. I/O function on RA7/OSC1/CLKIN 011 = EC: I/O function on RA6/OSC2/CLKOUT pin. R = Readable bit -n = Value at POR W = Writable bit ‘1’ = bit is set U = Unimplemented bit. See “PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196) for details. Resistor and Capacitor on RA7/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin. 1-0: 3: 4: Legend: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it does on the PIC16F627/628 devices. The entire Flash program memory needs to be bulk erased to set the CP bit. turning the code protection off.PIC16F627A/628A/648A REGISTER 14-1: CP — — CONFIG – CONFIGURATION WORD REGISTER — — CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0 bit 13 bit 13: CP: Flash Program Memory Code Protection bit(2) (PIC16F648A) 1 = Code protection off 0 = 0000h to 0FFFh code-protected (PIC16F628A) 1 = Code protection off 0 = 0000h to 07FFh code-protected (PIC16F627A) 1 = Code protection off 0 = 0000h to 03FFh code-protected Unimplemented: Read as ‘0’ CPD: Data Code Protection bit(3) 1 = Data memory code protection off 0 = Data memory code-protected LVP: Low-Voltage Programming Enable bit 1 = RB4/PGM pin has PGM function. The entire data EEPROM needs to be bulk erased to set the CPD bit. See “PIC16F627A/ 628A/648A EEPROM Memory Programming Specification” (DS41196) for details. The code protection scheme has changed from the code protection scheme used on the PIC16F627/628 devices. When MCLR is asserted in INTOSC mode. Resistor and Capacitor on RA7/OSC1/CLKIN 110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin. the internal clock oscillator is disabled.

These values are for design guidance only. but also increases the start-up time.0 MHz 4.2. to avoid overdriving crystals with low drive level specification.2. Since each resonator has its own characteristics. The PIC16F627A/628A/648A oscillator design requires the use of a parallel cut crystal. © 2009 Microchip Technology Inc.1 Oscillator Configurations OSCILLATOR TYPES TABLE 14-1: Mode XT CAPACITOR SELECTION FOR CERAMIC RESONATORS OSC1(C1) 22-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF OSC2(C2) 22-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF The PIC16F627A/628A/648A can be operated in eight different oscillator options. LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 14-1). Higher capacitance increases the stability of the oscillator. DS40044G-page 99 . XT OR LP OSC CONFIGURATION) OSC1 HS Note: C1(2) XTAL OSC2 RS(1) C2(2) Note 1: 2: FOSC RF Sleep PIC16F627A/628A/648A A series resistor may be required for AT strip cut crystals.PIC16F627A/628A/648A 14. but also increases the start-up time. the device can have an external clock source to drive the OSC1 pin (Figure 14-4). the user should consult the crystal manufacturer for appropriate values of external components.0 MHz 16. as well as XT mode. the user should consult the resonator manufacturer for appropriate values of external components.0 MHz 8. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • • • • • • LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Precision Oscillator (2 modes) EC External Clock In Freq 455 kHz 2. When in XT. LP or HS modes. TABLE 14-2: Mode LP XT CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR OSC1(C1) 15-30 pF 0-15 pF 68-150 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF OSC2(C2) 15-30 pF 0-15 pF 150-200 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF Freq 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz FIGURE 14-1: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS Higher capacitance increases the stability of the oscillator. A series resistor (RS) may be required in HS mode. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. These values are for design guidance only. Since each crystal has its own characteristics. In XT. See Table 14-1 and Table 14-2 for recommended values of C1 and C2.0 MHz HS Note: 14.2 14.

This could be used for external oscillator designs. Prepackaged oscillators provide a wide operating range and better stability.PIC16F627A/628A/648A 14.2. Figure 14-4 below shows how an external clock circuit should be configured. Two types of crystal oscillator circuits can be used. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.4 PRECISION INTERNAL 4 MHZ OSCILLATOR FIGURE 14-2: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT To other Devices The internal precision oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C. EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To other Devices 74AS04 CLKIN 330 KΩ 74AS04 0. A well-designed crystal oscillator will provide good performance with TTL gates. XT OR LP OSC CONFIGURATION) RA7/OSC1/CLKIN PIC16F627A/628A/648A Clock from ext.7 kΩ resistor provides the negative feedback for stability. . Figure 14-2 shows implementation of a parallel resonant oscillator circuit.6 “Timing Diagrams and Specifications”.2. RA6 RA6/OSC2/CLKOUT DS40044G-page 100 © 2009 Microchip Technology Inc. 14. for information on variation over voltage and temperature.0 “Electrical Specifications”. HS. or one with parallel resonance. users may directly drive the PIC16F627A/ 628A/648A provided that this external clock source meets the AC/DC timing requirements listed in Section 17.5 EXTERNAL CLOCK IN +5V 10K 4. one with series resonance. The inverter performs a 180° phase shift in a series resonant oscillator circuit.1 pF 330 KΩ 74AS04 PIC16F627A/ 628A/648A XTAL 14. See Section 17. This circuit is also designed to use the fundamental frequency of the crystal.7K 74AS04 74AS04 PIC16F627A/628A/648A CLKIN For applications where a clock is already available elsewhere. The 4. system Figure 14-3 shows a series resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 14-3: Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. The 74AS04 inverter performs the 180° phase shift that a parallel oscillator requires. 10K XTAL 10K C1 C2 FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (EC. The 10 kΩ potentiometers bias the 74AS04 in the linear region.2.

divided by 4 can be used for test purposes or to synchronize other logic. This oscillator speed transition delay consists of two existing clock pulses and eight new speed clock pulses.3 Reset The PIC16F627A/628A/648A differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset (normal operation) WDT wake-up (Sleep) Brown-out Reset (BOR) CEXT VSS FOSC/4 RA6/OSC2/CLKOUT Recommended Values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3. DS40044G-page 101 .6 “PCON Register”. The oscillator frequency. During this delay. The user also needs to account for the tolerance of the external R and C components.0V) 10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3. © 2009 Microchip Technology Inc. WDT Reset and MCLR Reset during Sleep. their status is unknown on POR and unchanged in any other Reset. See Table 14-7 for a full description of Reset states of all registers. MCLR Reset. Most other registers are reset to a “Reset state” on Power-on Reset. but cannot tolerate putting the part into Sleep. since this is viewed as the resumption of normal operation.2. Brown-out Reset.6 RC OSCILLATOR 14. During this clock speed transition delay.2. especially for low CEXT values. See Table 17-7 for pulse width specification. may use this mode. The OSCF bit in the PCON register is used to control Dual Speed mode.2. The other configures the pin as an output providing the FOSC signal (internal clock divided by 4) for test or external synchronization purposes. TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 14-4. FIGURE 14-5: VDD REXT RC OSCILLATOR MODE PIC16F627A/628A/648A RA7/OSC1/ CLKIN Internal Clock 14. See Section 4.8 For applications where precise timing is not a requirement. the System Clock is halted causing the processor to be frozen in time. The first allows it to be used as a general purpose I/O port. A simplified block diagram of the on-chip Reset circuit is shown in Figure 14-6. The difference in lead frame capacitance between package types will also affect the oscillation frequency.7 CLKOUT Some registers are not affected in any Reset condition. They are not affected by a WDT wake-up. The MCLR Reset path has a noise filter to detect and ignore small pulses. The RC oscillator frequency is a function of: • Supply voltage • Resistor (REXT) and capacitor (CEXT) values • Operating temperature The oscillator frequency will vary from unit-to-unit due to normal process parameter variation. SPECIAL FEATURE: DUAL-SPEED OSCILLATOR MODES A software programmable dual-speed oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC oscillator mode. the RC oscillator option is available. Register 4-6. There is a time delay associated with the transition between fast and slow oscillator speeds.0V) CEXT > 20 pF The RC Oscillator mode has two options that control the unused OSC2 pin.PIC16F627A/628A/648A 14. The operation and functionality of the RC oscillator is dependent upon a number of variables.2. Applications that require low-current power savings. These bits are used in software to determine the nature of the Reset. the program counter and the CLKOUT stop. This feature allows users to dynamically toggle the oscillator speed between 4 MHz and 48 kHz nominal in the INTOSC mode. The PIC16F627A/628A/648A can be configured to provide a clock out signal by programming the Configuration Word. Figure 14-5 shows how the R/C combination is connected. 14.2.

PIC16F627A/628A/648A FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset Schmitt Trigger Input MCLR/ VPP Pin WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin On-chip(1) OSC Chip_Reset R Q S BOREN Q Sleep WDT Time-out Reset Power-on Reset PWRT 10-bit Ripple-counter Enable PWRT See Table 14-3 for time out situations. . DS40044G-page 102 © 2009 Microchip Technology Inc. Enable OST Note 1: This is a separate oscillator from the INTOSC/RC oscillator.

2-1. This ensures that the crystal oscillator or resonator has started and stabilized. On any Reset (Power-on. respectively.7V).4. The power-up time delay will vary from chip-to-chip and due to VDD. the Power-Up Timer will execute a 72 ms Reset.1 The on-chip POR holds the part in Reset until a VDD rise is detected (in the range of 1. 14. 14. If these conditions are not met. The POR circuit does not produce an internal Reset when VDD declines. the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. See DC parameters Table 17-7 for details.3 OSCILLATOR START-UP TIMER (OST) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. BOREN. if enabled. the brown-out situation will reset the chip. Program execution will not start until the OST time out is complete. Figure 14-7 shows typical brown-out situations. The Power-up Timer will now be invoked.0 “Electrical Specifications” for details. If VDD falls below VBOR for longer than TBOR. can disable (if clear/programmed) or enable (if set) the BOR circuitry. etc. PWRTE can disable (if set) or enable (if cleared or programmed) the PWRT. A Reset is not assured if VDD falls below VBOR for shorter than TBOR. When the device starts normal operation (exits the Reset condition). the device must be held in Reset via MCLR.2 POWER-UP TIMER (PWRT) The PWRT provides a fixed 72 ms (nominal) time out on power-up (POR) or if enabled from a Brown-out Reset.4. The PWRT delay allows the VDD to rise to an acceptable level. If VDD drops below VBOR while the Power-up Timer is running. refer to Application Note AN607 “Power-up Trouble Shooting” (DS00607).). VBOR and TBOR are defined in Table 17-2 and Table 17-7. Once VDD rises above VBOR. Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) POWER-ON RESET (POR) 14.4 BROWN-OUT RESET (BOR) The PIC16F627A/628A/648A have on-chip BOR circuitry. FIGURE 14-7: VDD BROWN-OUT SITUATIONS WITH PWRT ENABLED VBOR ≥ TBOR Internal Reset VDD 72 ms VBOR <72 ms Internal Reset 72 ms VDD VBOR Internal Reset Note: 72 ms 72 ms delay only if PWRTE bit is programmed to ‘0’. LP and HS modes and only on Power-on Reset or wake-up from Sleep. The PWRT operates on an internal RC oscillator. Watchdog. It is recommended that the PWRT be enabled when Brown-out Reset is enabled. See Section 17. 14. See Table 17-7.PIC16F627A/628A/648A 14. For additional information. Brown-out. frequency. Power-up Timer (PWRT). and will keep the chip in Reset an additional 72 ms. DS40044G-page 103 . © 2009 Microchip Technology Inc. the chip will remain in Reset until VDD rises above VBOR (see Figure 14-7).4. A configuration bit. temperature and process variation.) must be met to ensure proper operation. temperature. BOR or PWRT until the operating conditions are met. The OST time out is invoked only for XT.4 Power-on Reset (POR). A configuration bit. etc.4. device operating parameters (voltage. A maximum rise time for VDD is required. The chip is kept in Reset as long as PWRT is active.

Bit 1 is POR (Power-on Reset). On a subsequent Reset if POR is ‘0’. It must then be set by the user and checked on subsequent Resets to see if BOR = 0 indicating that a brown-out has occurred. there will be no time out at all. the time outs will expire. while Table 14-7 shows the Reset conditions for all the registers.4.6 On power-up.5 TIME OUT SEQUENCE 14. . Then bringing MCLR high will begin execution immediately (see Figure 14-11). it will indicate that a Power-on Reset must have occurred (VDD may have gone too low). This is useful for testing purposes or to synchronize more than one PIC16F627A/628A/ 648A device operating in parallel. TO is set on POR Illegal. x = unknown DS40044G-page 104 © 2009 Microchip Technology Inc. PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition BOR X X X 0 1 1 1 1 u = unchanged. BOR is unknown on Power-on Reset. HS. has two bits. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (by setting BOREN bit = 0 in the Configuration Word). Figure 14-8. if MCLR is kept low long enough. Bit 0 is BOR (Brown-out Reset). POWER CONTROL (PCON) STATUS REGISTER The PCON/Status register. the time out sequence is as follows: First PWRT time-out is invoked after POR has expired. in RC mode with PWRTE bit set (PWRT disabled). EC INTOSC 72 ms + 1024•TOSC 72 ms 72 ms PWRTE = 1 1024•TOSC — — TABLE 14-4: POR 0 0 0 1 1 1 1 1 Legend: STATUS/PCON BITS AND THEIR SIGNIFICANCE TO 1 0 X X 0 0 u 1 PD 1 X 0 X u 0 u 0 Power-on Reset Illegal. TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS Power-up Timer Brown-out Reset PWRTE = 0 72 ms + 1024•TOSC 72 ms 72 ms PWRTE = 1 1024•TOSC — — Wake-up from Sleep 1024•TOSC — 6 μs Oscillator Configuration PWRTE = 0 XT. The total time out will vary based on oscillator configuration and PWRTE bit Status. Then OST is activated. Table 14-6 shows the Reset conditions for some special registers. The user must write a ‘1’ to this bit following a Power-on Reset. PCON (address 8Eh). For example. It is a ‘0’ on Power-on Reset and unaffected otherwise. Figure 14-11 and Figure 14-12 depict time out sequences.PIC16F627A/628A/648A 14. LP RC. Since the time outs occur from the POR pulse.4.

83h. . Brown-out Reset and Watchdog Timer Reset during normal operation.1-uu ---. GIE is set.u-uq Name STATUS PCON x = unknown. reads as ‘0’.= unimplemented read as ‘0’. © 2009 Microchip Technology Inc. Note 1: When the wake-up is due to an interrupt and global enable bit.1-uu ---. . u = unchanged. 103h. DS40044G-page 105 . Shaded cells are not used by Brown-out Reset.1-0x Value on all other Resets(1) 000q quuu ---. x = unknown. q = value depends upon condition.PIC16F627A/628A/648A TABLE 14-5: Address 03h. Other (non Power-up) Resets include MCLR Reset.1-uu ---.u-uu ---.1-u0 ---. the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.= unimplemented bit.u-uu Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Legend: u = unchanged.1-0x ---. TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1 (1) Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 000x xuuu uuu1 0uuu PCON Register ---. 183h 8Eh Legend: Note 1: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Bit 7 IRP — Bit 6 RP1 — Bit 5 RPO — Bit 4 TO — Bit 3 PD OSCF Bit 2 Z — Bit 1 DC POR Bit 0 C BOR Value on POR Reset 0001 1xxx ---.

10Bh. 83h. 80h. 10Ah. 106h 0Ah. 182h 03h.PIC16F627A/628A/648A TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS • MCLR Reset during normal operation • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (1) uuuu uuuu — uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu xxxx 0000 uuuu uuuu ---0 0000 0000 000u 0000 -000 uuuu uuuu uuuu uuuu --uu uuuu(6) 0000 0000 -000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 000x 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 -000 ---. 82h. the PC is loaded with the interrupt vector (0004h). then bit 0 = 0.= unimplemented bit. 183h 04h. 8Bh. Power-on Reset will be activated and registers will be affected differently. See Table 14-6 for Reset value for specific condition.5) 1111 1111 0000 -010 0000 0000 uuuu uuuu uuuu uuuu ---. When the wake-up is due to an interrupt and the GIE bit is set. 101h 02h. 180h 01h. x = unknown. If VDD goes too low. 102h. Reset to ‘--00 0000’ on a Brown-out Reset (BOR). .q000 — 000. 104h.x000 — 000.0000 u = unchanged. One or more bits in INTCON and PIR1 will be affected (to cause wake-up). 184h 05h 06h. q = value depends on condition. . 103h.1-0x 1111 1111 0000 -010 0000 0000 xxxx xxxx xxxx xxxx ---. Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers. 8Ah.uuuu — uuu. If Reset was due to brown-out.18Bh 0Ch 0Eh 0Fh 10h 11h 12h 15h 16h 17h 18h 19h 1Ah 1Fh 81h.u-uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu ---. reads as ‘0’. DS40044G-page 106 © 2009 Microchip Technology Inc. 18Ah 0Bh. 186h 8Ch 8Eh 92h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Fh xxxx xxxx — xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx 0000 xxxx xxxx ---0 0000 0000 000x 0000 -000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 -000 ---.0000 • Wake-up from Sleep(7) through interrupt • Wake-up from Sleep(7) through WDT time out uuuu uuuu — uuuu uuuu PC + 1(3) uuuq 0uuu(4) uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uqqq(2) qqqq -qqq(2) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-.uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu ---. 100h. 84h.181h 85h 86h.uuuu Register Address Power-on Reset W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CMCON OPTION TRISA TRISB PIE1 PCON PR2 TXSTA SPBRG EEDATA EEADR EECON1 EECON2 VRCON Legend: Note 1: 2: 3: 4: 5: 6: 7: — 00h.1-uq(1. All other Resets will cause bit 0 = u.

DS40044G-page 107 .PIC16F627A/628A/648A FIGURE 14-8: VDD MCLR Internal POR TPWRT PWRT Time Out OST Time Out Internal Reset TOST TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE FIGURE 14-9: VDD MCLR Internal POR TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT PWRT Time Out OST Time Out Internal Reset TOST FIGURE 14-10: VDD MCLR Internal POR TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) TPWRT PWRT Time Out OST Time Out Internal Reset TOST © 2009 Microchip Technology Inc.

R1 = 100Ω to 1 kΩ will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. albeit less accurate.7 V EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD VDD D PIC16F627A/628A/648A R2 40k MCLR PIC16F627A/628A/648A Note 1: 2: 3: External Power-on Reset circuit is required only if VDD power-up slope is too slow. . The diode D helps discharge the capacitor quickly when VDD powers down. FIGURE 14-12: VDD 33k 10k EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD MCLR 40k PIC16F627A/628A/648A Note 1: This circuit will activate Reset when VDD goes below (Vz + 0. R < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.PIC16F627A/628A/648A FIGURE 14-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-13: VDD R1 Q1 R R1 MCLR C Note 1: This brown-out circuit is less expensive.7 V 2: Internal Brown-out Reset should be x R1 + R2 disabled when using this circuit. DS40044G-page 108 © 2009 Microchip Technology Inc.7V) where Vz = Zener voltage. R1 = 0. 3: Resistors should be adjusted for the characteristics of the transistor. Transistor Q1 turns off when VDD is below a certain level such that: VDD x R1 R1 + R2 = 0.

The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/ INT recursive interrupts. which reenables RB0/INT interrupts. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. It also has individual and global interrupt enable bits. The corresponding interrupt enable bit is contained in special registers PIE1. FIGURE 14-14: INTERRUPT LOGIC TMR1IF TMR1IE TMR2IF TMR2IE CCP1IF CCP1IE CMIF CMIE TXIF TXIE RCIF RCIE EEIF EEIE T0IF T0IE INTF INTE RBIF RBIE PEIE Wake-up (if in Sleep mode)(1) Interrupt to CPU GIE Note 1: Some peripherals depend upon the system clock for operation. the source(s) of the interrupt can be determined by polling the interrupt flag bits.PIC16F627A/628A/648A 14. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. Since the system clock is suspended during Sleep. Once in the interrupt service routine.8. See Section 14.5 Interrupts The PIC16F627A/628A/648A has 10 sources of interrupt: • • • • • • • • • • External Interrupt RB0/INT TMR0 Overflow Interrupt PORTB Change Interrupts (pins RB<7:4>) Comparator Interrupt USART Interrupt TX USART Interrupt RX CCP Interrupt TMR1 Overflow Interrupt TMR2 Match Interrupt Data EEPROM Interrupt When an interrupt is responded to. the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. RETFIE. the GIE is cleared to disable any further interrupt. The exact latency depends when the interrupt event occurs (Figure 14-15). GIE is cleared on Reset. The latency is the same for one or two-cycle instructions. The peripheral interrupt flag is contained in the special register PIR1. such as the INT pin or PORTB change interrupt. © 2009 Microchip Technology Inc. any interrupts that were pending for execution in the next cycle are ignored. The “return-from-interrupt” instruction. A Global Interrupt Enable bit. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. the return address is pushed into the stack and the PC is loaded with 0004h. For external interrupt events. the interrupt latency will be three or four instruction cycles. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. The INT pin interrupt. Once in the interrupt service routine.1 “Wake-up from Sleep”. GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. 2: When an instruction that clears the GIE bit is executed. DS40044G-page 109 . only those peripherals which do not depend upon the system clock will wake the part from Sleep. the source(s) of the interrupt can be determined by polling the interrupt flag bits. exits interrupt routine as well as sets the GIE bit.

1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). if the INTE bit was set prior to going into Sleep.6 “Comparator Interrupts” complete description of comparator interrupts.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. FIGURE 14-15: Q1 OSC1 CLKOUT INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5: (3) INT PIN INTERRUPT TIMING Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (4) (1) (1) (5) Interrupt Latency (2) PC Inst (PC) Inst (PC .4 COMPARATOR INTERRUPT for See Section 10. DS40044G-page 110 © 2009 Microchip Technology Inc.5. Asynchronous interrupt latency = 3-4 TCY. See Section 14.3 PORTB INTERRUPT External interrupt on the RB0/INT pin is edge triggered.5. either rising if INTEDG bit (OPTION<6>) is set. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<3>) bit.8 “Power-Down Mode (Sleep)” for details on Sleep.0 “Timer0 Module”.PIC16F627A/628A/648A 14. . where TCY = instruction cycle time. For minimum width of INT pulse. When a valid edge appears on the RB0/INT pin. or falling.5. if INTEDG bit is clear. Synchronous latency = 3 TCY. The RB0/INT interrupt can wake-up the processor from Sleep. CLKOUT is available in RC and INTOSC oscillator mode.1 RB0/INT INTERRUPT 14. For operation of PORTB (Section 5. refer to AC specs. then the RBIF interrupt flag may not get set. An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing T0IE (INTCON<5>) bit. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>).5. the INTF bit (INTCON<1>) is set. 14.2 “PORTB and TRISB Registers”). Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction. and Figure 14-17 for timing of wake-up from Sleep through RB0/INT interrupt. 14. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. INTF is enabled to be set anytime during the Q4-Q1 cycles. The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. For operation of the Timer0 module. Note: If a change on the I/O pin should occur when the read operation is being executed (starts during the Q2 cycle and ends before the start of the Q3 cycle). see Section 6.

Temperature = Max. DS40044G-page 111 .W . If the device is in Sleep mode. © 2009 Microchip Technology Inc.RP0 .state MOVWF STATUS . VDD and process variations from part to part (see DC Specifications. sets bank to original .swap status to be saved . W register and Status register).6 Context Saving During Interrupts 14. W_TEMP. time-out periods up to 2.. 0x170 and 0x1F0).copy W to temp register. 14. Brown-out Reset and Watchdog Timer Reset during normal operation.could be in any bank STATUS.1 “Configuration Bits”). The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 14. WDT prescaler) it may take several seconds before a WDT time out occurs. 8Bh.swap W_TEMP SWAPF W_TEMP.register W_TEMP The WDT has a nominal time-out period of 18 ms (with no prescaler).7. accessible at 0xF0.into W.change to bank 0 .into W STATUS. INTCON 10Bh. and prevent it from timing out and generating a device Reset.. 14. if assigned to the WDT. max.3 seconds can be realized.swap STATUS_TEMP register .e. . This RC oscillator is separate from the RC oscillator of the CLKIN pin. Typically.. Example 14-1 stores and restores the Status and W registers.7 Watchdog Timer (WDT) During an interrupt. a WDT time out causes the device to wake-up and continue with normal operation. If longer timeout periods are desired. Table 17-7). The CLRWDT and SLEEP instructions clear the WDT and the postscaler. a WDT time out generates a device Reset.regardless of current . by execution of a SLEEP instruction. W_TEMP is defined at 0x70 in Bank 0 and is therefore..register SWAPF W_TEMP.move W into STATUS .save status to bank 0 . only the return PC value is saved on the stack. must be defined in a common memory location (i.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case conditions (VDD = Min. 18Bh 0Ch 8Ch PIR1 PIE1 CCP1IF TMR2IF TMR1IF CCP1IE TMR2IE TMR1IE Note 1: Other (non Power-up) Resets include MCLR Reset. The user register.PIC16F627A/628A/648A TABLE 14-8: Address SUMMARY OF INTERRUPT REGISTERS Bit 7 GIE EEIF EEIE Bit 6 PEIE CMIF CMIE Bit 5 T0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE — — Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on POR Reset 0000 000x 0000 -000 0000 -000 Value on all other Resets(1) 0000 000u 0000 -000 0000 -000 Name 0Bh. This must be implemented in software.swap W_TEMP into W 14. The TO bit in the Status register will be cleared upon a Watchdog Timer time out. During normal operation. The Example 14-1: • • • • • Stores the W register Stores the Status register Executes the ISR code Restores the Status (and bank select bit register) Restores the W register The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. The time-out periods vary with temperature. : :(ISR) : SWAPF STATUS_TEMP.W . even if the clock on the OSC1 and OSC2 pins of the device has been stopped.F . for example.W.7.1 WDT PERIOD EXAMPLE 14-1: SAVING THE STATUS AND W REGISTERS IN RAM MOVWF SWAPF BCF MOVWF . users may wish to save key registers during an interrupt (e.g. Thus. That means that the WDT will run. a postscaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register.bank STATUS_TEMP .

T0CS. PS0-PS2 are bits in the OPTION register. and VREF should be disabled. DS40044G-page 112 © 2009 Microchip Technology Inc. . PSA. For lowest current consumption in this mode. low or highimpedance). the TO bit is set. TABLE 14-9: Address 2007h 81h.8 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. the Watchdog Timer will be cleared but keeps running.= unimplemented read as ‘0’.PIC16F627A/628A/648A FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-1) 0 Watchdog Timer M U 1X WDT Postscaler/ TMR0 Prescaler 8 8 to 1 MUX PS<2:0> PSA WDT Enable Bit 3 To TMR0 (Figure 6-1) 0 MUX 1 PSA WDT Time-out Note: T0SE. the PD bit in the Status register is cleared. u = unchanged. all I/O pins should be either at VDD or VSS with no external circuitry drawing current from the I/O pin and the comparators. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The MCLR pin must be at a logic high level (VIHMC). Shaded cells are not used by the Watchdog Timer. The I/O ports maintain the status they had. before SLEEP was executed (driving high. and the oscillator driver is turned off. 14. The contribution from on chip pull-ups on PORTB should be considered. q = value depends upon condition. 181h Note: SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 LVP Bit 6 Bit 5 Bit 4 Bit 3 PWRTE PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 Value on POR Reset Value on all other Resets Name CONFIG OPTION BOREN MCLRE FOSC2 T0CS T0SE uuuu uuuu uuuu uuuu 1111 1111 1111 1111 RBPU INTEDG Legend: x = unknown. . If enabled. The T0CKI input should also be at VDD or VSS for lowest current consumption.

In this case. The first event will cause a device Reset. PD bit. or any peripheral interrupt. RB port change. If GIE = 0. TO bit is cleared if WDT wake-up occurred. Note: Only a Bulk Erase function can set the CP and CPD bits by turning off the code protection.10 User ID Locations Four memory locations (2000h-2003h) are designated as user ID locations where the user can store checksum or other code-identification numbers. 2. the next instruction (PC + 1) is pre-fetched. The TO and PD bits in the Status register can be used to determine the cause of device Reset.9 Code Protection 14. HS or LP Oscillator mode assumed. Approximately 1 μs delay will be there for RC Oscillator mode. the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). the user should have an NOP after the SLEEP instruction. With the Code-Protect bit is cleared (Code-Protect enabled). GIE = 1 assumed. Wake-up is regardless of the state of the GIE bit. the device continues execution at the instruction after the SLEEP instruction. but shown here for timing reference. regardless of the source of wake-up. TOST = 1024 TOSC (drawing not to scale). The two latter events are considered a continuation of program execution. is cleared when Sleep is invoked. The SLEEP instruction is executed as a NOP instruction. These locations are not accessible during normal execution but are readable and writable during Program/Verify.PIC16F627A/628A/648A 14. When the SLEEP instruction is being executed. execution will continue in-line. but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set. after wake-up the processor jumps to the interrupt routine. For the device to wake-up through an interrupt event. the device will not enter Sleep. 14. the contents of the program memory locations are read out as ‘0’. Note: If the global interrupts are disabled (GIE is cleared). The entire data EEPROM and Flash program memory will be erased to turn the code protection off. which is active in Sleep.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. CLKOUT is not available in these Oscillator modes. If the GIE bit is clear (disabled). which is set on power-up.2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Interrupt Latency (Note 2) Processor in Sleep 0004h(3) Inst(0004h) Dummy cycle Dummy cycle PC + 1 Inst(PC + 1) Sleep PC + 2 PC + 2 Inst(PC + 2) Inst(PC + 1) PC + 2 0005h Inst(0005h) Inst(0004h) Inst(PC) = Sleep Inst(PC .8. The WDT is cleared when the device wakes up from Sleep. DS40044G-page 113 . © 2009 Microchip Technology Inc.1) Note 1: 2: 3: 4: XT. In cases where the execution of the instruction following SLEEP is not desirable. If the GIE bit is set (enabled). External Reset input on MCLR pin Watchdog Timer wake-up (if WDT was enabled) Interrupt from RB0/INT pin. the corresponding interrupt enable bit must be set (enabled). 3. Only the Least Significant 4 bits of the user ID locations are used for checksum calculations although each location has 14 bits. FIGURE 14-17: OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed PC WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(1. See “PIC16F627A/628A/ 648A EEPROM Memory Programming Specification” (DS41196) for details.

The LVP bit may only be programmed when programming is entered with VIHH on MCLR. This also allows the most recent firmware or custom firmware to be programmed. the RB4/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. This mode allows the microcontroller to be programmed via ICSP using only a 5V source. It should be noted. After Reset. Note 1: While in this mode. 2: VDD must be 5. that once the LVP bit is programmed to ‘0’. and three other lines for power. the LVP bit should be programmed to a ‘0’ so that RB4/ PGM becomes a digital I/O pin. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. For complete details of serial programming. RB6 becomes the programming clock and RB7 becomes the programming data. the RB4 pin can no longer be used as a general purpose I/O pin. FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC16F627A/628A/648A VDD VSS RA5/MCLR/VPP RB6/PGC RB7/PGD External Connector Signals +5V 0V VPP CLK Data I/O VDD To Normal Connections DS40044G-page 114 © 2009 Microchip Technology Inc. The LVP bit is normally erased to ‘1’ which enables the low-voltage programming. A typical In-Circuit Serial Programming connection is shown in Figure 14-18. The device will enter Programming mode when a ‘1’ is placed on the RB4/ PGM pin.12 Low-Voltage Programming The LVP bit of the Configuration Word. please refer to “PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196). 14. The device is placed into a Program/Verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH. 14 bits of program data are then supplied to or from the device. to place the device into Programming/Verify mode. This mode removes the requirement of VIHH to be placed on the MCLR pin. only High-Voltage Programming mode can be used to program the device. ground and the programming voltage. VIHH must be placed onto MCLR during programming. The High-Voltage Programming mode is still available by placing VIHH on the MCLR pin. A 6-bit command is then supplied to the device. This is simply done with two lines for clock and data. enables the lowvoltage programming. depending if the command was a load or a read. If Low-Voltage Programming mode is not used. . To program the device. The LVP bit cannot be programmed when programming is entered with RB4/PGM. the Program Counter (PC) is at location 00h. In this mode.0V +10% during erase operations.11 In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A microcontrollers can be serially programmed while in the end application circuit.PIC16F627A/628A/648A 14. Depending on the command. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. See “PIC16F627A/ 628A/648A EEPROM Memory Programming Specification” (DS41196) for details.

data and MCLR pins. This special ICD device is mounted on the top of a header and its signals are routed to the MPLAB ICD 2 connector.PIC16F627A/628A/648A 14. ICDDATA 1 level Address 0h must be NOP 300h-3FEh The PIC16F648A-ICD device with header is supplied as an assembly.13 In-Circuit Debugger Since in-circuit debugging requires the loss of clock. Debugging of all three versions of the PIC16F627A/628A/648A is supported by the PIC16F648A-ICD. When the microcontroller has this feature enabled. DS40044G-page 115 . See Microchip Part Number AC162053. When the ICD pin on the PIC16F648A-ICD device is held low. MPLAB® ICD 2 development with an 18-pin device is not practical. © 2009 Microchip Technology Inc. A special 28-pin PIC16F648A-ICD device is used with MPLAB ICD 2 to provide separate clock. Table 14-19 shows which features are consumed by the background debugger. TABLE 14-19: DEBUGGER RESOURCES I/O pins Stack Program Memory ICDCLK. some of the resources are not available for general use. the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. On the bottom of the header is an 18-pin socket that plugs into the user’s target via an 18-pin stand-off connector. data and MCLR pins and frees all normally available pins to the user.

PIC16F627A/628A/648A NOTES: DS40044G-page 116 © 2009 Microchip Technology Inc. .

constant data or label Don’t care location (= 0 or 1) The assembler will generate code with x = 0. and the result is stored according to either the instruction.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. Use of any reserved opcode may cause unexpected operation. It is the recommended form of use for compatibility with all Microchip software tools. or the destination designator ‘d’. All examples use the following format to represent a hexadecimal number: 0xhh where ‘h’ signifies a hexadecimal digit. If ‘d’ is one. The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations All instructions are executed within one single instruction cycle. If a conditional test is true or the program counter is changed as a result of an instruction. One instruction cycle consists of four oscillator periods. 2: To maintain upward compatibility with future PIC MCU products. FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS 0 f (FILE #) Byte-oriented file register operations 13 8 7 6 OPCODE d TABLE 15-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) 0 Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field. the result is placed in the file register specified in the instruction. then write the result back to PORTB. ‘f’ represents a file register designator and ‘d’ represents a destination designator. do not use the OPTION and TRIS instructions. clear all the data bits. For literal and control operations. A read operation is performed on a register even if the instruction writes to that register. unless a conditional test is true or the program counter is changed as a result of an instruction. For example. for an oscillator frequency of 4 MHz. ‘k’ represents an eight or eleven bit constant or literal value. The file register designator specifies which file register is to be used by the instruction. bit-oriented. the instruction execution time is 2 μs. the data is modified. Default is d = 1 Time-out bit Power-down bit b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k (literal) k = 11-bit immediate value 0 8 7 k (literal) 0 d TO PD © 2009 Microchip Technology Inc. while ‘f’ represents the number of the file in which the bit is located. For bit-oriented instructions. 15. The register is read. ‘b’ represents a bit field designator which selects the number of the bit affected by the operation. the result is placed in the W register. Figure 15-1 shows the three general formats that the instructions can have. d = 1: store result in file register f. Thus.PIC16F627A/628A/648A 15. The PIC16F627A/628A/648A instruction set summary in Table 15-2 lists byte-oriented. and literal and control operations. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero.0 INSTRUCTION SET SUMMARY Each PIC16F627A/628A/648A instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. This example would have the unintended result that the condition that sets the RBIF flag would be cleared for pins configured as inputs and using the PORTB interrupt-on-change feature. a “clrf PORTB” instruction will read PORTB. DS40044G-page 117 . d = 0: store result in W. Destination select. Table 15-2 lists the instructions recognized by the MPASM™ assembler. In this case. the execution takes two instruction cycles with the second cycle executed as a NOP. Note 1: Any unused opcode is reserved. For byte-oriented instructions. the normal instruction execution time is 1 μs. Table 15-1 shows the opcode field descriptions.

2 1. 2 1. 3 1.Z Z TO. b f. 2 1. the instruction requires two cycles. d f..PD Z LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk TO. 1). 2 1. d f. d f. 2. DS40044G-page 118 © 2009 Microchip Technology Inc. d f. Skip if Clear Bit Test f.PIC16F627A/628A/648A TABLE 15-2: Mnemonic. b k k k — k k k — k — — k k Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f.PD C. d f — f. if the data latch is ‘1’ for a pin configured as input and is driven low by an external device. d f. d = 1). d f. the prescaler will be cleared if assigned to the Timer0 Module. the value used will be that value present on the pins themselves.Z Z 1. b f. Skip if 0 Increment f Increment f. 2. MOVF PORTB.Z Z Z Z Z Z Z Z Z 1.DC. For example. Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f. Operands PIC16F627A/628A/648A INSTRUCTION SET 14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f. the data will be written back with a ‘0’.DC. d f. d f. 2 1. where applicable.DC. d f. d f — f. Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1(2) 1(2) 1 1 2 1 2 1 1 2 2 2 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C. 3 1. 2 1. If Program Counter (PC) is modified or a conditional test is true.DC. d f. 2 1.g.Z Z 2: 3: When an I/O register is modified as a function of itself (e. 2 1. 2 1. 2 3 3 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C. 2 C C C. 2 1. d f. d f. 2 2 1. The second cycle is executed as a NOP. b f. . If this instruction is executed on the TMR0 register (and. 2 1.

1 1 ANDLW 0x5F Words: Cycles: Example Before Instruction W = 0x10 After Instruction W = 0x25 Before Instruction W = 0xA3 After Instruction W = 0x03 ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Add W and f [ label ] ADDWF 0 ≤ f ≤ 127 d ∈ [0. 1 1 ADDLW 0x15 Words: Cycles: Example The contents of W register are AND’ed with the eight bit literal ‘k’.AND. DC. If ‘d’ is ‘0’. The result is placed in the W register. If ‘d’ is ‘1’. If ‘d’ is ‘1’. 1 1 ADDWF REG1. DC.1] (W) + (f) → (dest) C. 1 1 ANDWF REG1.2 Syntax: Operands: Operation: Status Affected: Encoding: Description: Instruction Descriptions Add Literal and W [ label ] ADDLW 0 ≤ k ≤ 255 (W) + k → (W) C. Z 11 111x kkkk kkkk ADDLW ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description: AND Literal with W [ label ] ANDLW 0 ≤ k ≤ 255 (W) . the result is stored in the W register.1] (W) . If ‘d’ is ‘0’.d Add the contents of the W register with register ‘f’. (f) → (dest) Z 00 0101 dfff ffff f. (k) → (W) Z 11 1001 kkkk kkkk k The contents of the W register are added to the eight bit literal ‘k’ and the result is placed in the W register. the result is stored back in register ‘f’. 0 AND the W register with register ‘f’. DS40044G-page 119 .PIC16F627A/628A/648A 15. the result is stored back in register ‘f’.d Syntax: Operands: Operation: Status Affected: Encoding: Description: AND W with f [ label ] ANDWF 0 ≤ f ≤ 127 d ∈ [0. 1 Words: Cycles: Example Words: Cycles: Example Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2 Z = 0 C = 0 DC = 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0x17 REG1 = 0x02 © 2009 Microchip Technology Inc. Z 00 0111 dfff ffff ANDWF f. the result is stored in the W register.AND.

7 Before Instruction PC = address HERE After Instruction if REG<1> = 0. . Skip if Clear [ label ] BTFSC f. 1 1 BSF REG1. PC = address FALSE Before Instruction REG1 = 0x0A After Instruction REG1 = 0x8A DS40044G-page 120 © 2009 Microchip Technology Inc. PC = address TRUE if REG<1> =1. then the next instruction fetched during the current instruction execution is discarded. 1 1 BCF REG1. and a NOP is executed instead. then the next instruction is skipped. If bit ‘b’ is ‘0’. 7 Before Instruction REG1 = 0xC7 After Instruction REG1 = 0x47 If bit ‘b’ in register ‘f’ is ‘0’. 1 1(2) HERE FALSE TRUE BTFSC GOTO • • • REG1 PROCESS_CODE Words: Cycles: Example BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Bit Set f [ label ] BSF 0 ≤ f ≤ 127 0≤b≤7 1 → (f<b>) None 01 01bb bfff ffff f.b 0 ≤ f ≤ 127 0≤b≤7 skip if (f<b>) = 0 None 01 10bb bfff ffff Bit ‘b’ in register ‘f’ is cleared.b Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f.PIC16F627A/628A/648A BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Bit Clear f [ label ] BCF 0 ≤ f ≤ 127 0≤b≤7 0 → (f<b>) None 01 00bb bfff ffff BTFSC f.b Bit ‘b’ in register ‘f’ is set. making this a two-cycle instruction.

CALL is a two-cycle instruction. 1 1 CLRF REG1 Before Instruction REG1 = 0x5A After Instruction REG1 = 0x00 Z = 1 © 2009 Microchip Technology Inc. is discarded and a NOP is executed instead.b 0 ≤ f ≤ 127 0≤b<7 skip if (f<b>) = 1 None 01 11bb bfff ffff CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 ≤ k ≤ 2047 (PC)+ 1→ TOS.PIC16F627A/628A/648A BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f. PC = address TRUE Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Clear f [ label ] CLRF 0 ≤ f ≤ 127 00h → (f) 1→Z Z 00 0001 1fff ffff f The contents of register ‘f’ are cleared and the Z bit is set. 1 1(2) HERE FALSE TRUE BTFSS GOTO • • • REG1 PROCESS_CODE Words: Cycles: Example Call Subroutine. making this a two-cycle instruction. (PCLATH<4:3>) → PC<12:11> None 10 0kkk kkkk kkkk Status Affected: Encoding: Description: If bit ‘b’ in register ‘f’ is ‘1’. k → PC<10:0>. First. then the next instruction is skipped. Skip if Set [ label ] BTFSS f. If bit ‘b’ is ‘1’. The eleven bit immediate address is loaded into PC bits <10:0>. then the next instruction fetched during the current instruction execution. DS40044G-page 121 . PC = address FALSE if FLAG<1> = 1. 1 2 HERE CALL THERE Words: Cycles: Example Before Instruction PC = address HERE After Instruction if FLAG<1> = 0. The upper bits of the PC are loaded from PCLATH. return address (PC + 1) is pushed onto the stack.

Status bits TO and PD are set. 1 → TO 1 → PD TO.PIC16F627A/628A/648A CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Clear W [ label ] CLRW None 00h → (W) 1→Z Z 00 0001 0000 0011 COMF Syntax: Operands: Operation: Status Affected: Encoding: Description: Complement f [ label ] COMF 0 ≤ f ≤ 127 d ∈ [0.1 → (dest) Z 00 0011 dfff ffff Status Affected: Encoding: Description: CLRWDT instruction resets the Watchdog Timer. Zero bit (Z) is set. . If ‘d’ is ‘1’.d W register is cleared. the result is stored back in register ‘f’. It also resets the prescaler of the WDT. the result is stored in the W register. 1 1 DECF CNT. If ‘d’ is ‘0’.1] (f) . 1 1 CLRW The contents of register ‘f’ are complemented. 0 Words: Cycles: Example Before Instruction W = 0x5A After Instruction W = 0x00 Z = 1 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W = 0xEC CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h → WDT 0 → WDT prescaler. the result is stored in W. 1 1 CLRWDT Decrement register ‘f’. the result is stored back in register ‘f’. 1 Words: Cycles: Example Words: Cycles: Example Before Instruction WDT counter = ? After Instruction WDT counter = WDT prescaler = = TO = PD 0x00 0 1 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 DS40044G-page 122 © 2009 Microchip Technology Inc. 1 1 COMF REG1.1] (f) → (dest) Z 00 1001 dfff ffff f. PD 00 0000 0110 0100 DECF Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f [ label ] DECF f.d 0 ≤ f ≤ 127 d ∈ [0. If ‘d’ is ‘1’. If ‘d’ is ‘0’.

0 None 00 1011 dfff ffff GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 ≤ k ≤ 2047 k → PC<10:0> PCLATH<4:3> → PC<12:11> None 10 1kkk kkkk kkkk skip if result = The contents of register ‘f’ are decremented.1] (f) . is discarded. If ‘d’ is ‘1’. which is already fetched.d 0 ≤ f ≤ 127 d ∈ [0. 1 2 GOTO THERE Words: Cycles: Example Words: Cycles: Example After Instruction PC = Address THERE Before Instruction PC = address HERE After Instruction REG1 = REG1 . If ‘d’ is ‘0’. 1 LOOP GOTO is an unconditional branch. 1 1(2) HERE DECFSZ GOTO CONTINUE • • • REG1. the result is placed back in register ‘f’. DS40044G-page 123 . A NOP is executed instead making it a two-cycle instruction. PC = address CONTINUE if REG1 ≠ 0. GOTO is a two-cycle instruction.PIC16F627A/628A/648A DECFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Decrement f.1 → (dest). PC = address HERE+1 © 2009 Microchip Technology Inc. If the result is ‘0’. The upper bits of PC are loaded from PCLATH<4:3>. the result is placed in the W register.1 if REG1 = 0. the next instruction. Skip if 0 [ label ] DECFSZ f. The eleven-bit immediate value is loaded into PC bits <10:0>.

1 1(2) HERE INCFSZ GOTO CONTINUE • • • REG1. the result is placed in the W register. If ‘d’ is ‘0’.d 0 ≤ f ≤ 127 d ∈ [0. If ‘d’ is ‘1’. the result is placed back in register ‘f’. the result is placed back in register ‘f’. If the result is ‘0’. PC = address HERE +1 DS40044G-page 124 © 2009 Microchip Technology Inc.d 0 ≤ f ≤ 127 d ∈ [0. 1 LOOP Words: Cycles: Example Before Instruction PC = address HERE After Instruction REG1 = REG1 + 1 if CNT = 0.PIC16F627A/628A/648A INCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f [ label ] INCF f. 1 1 INCF REG1. If ‘d’ is ‘0’. the next instruction. is discarded.1] (f) + 1 → (dest) Z 00 1010 dfff ffff INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f. If ‘d’ is ‘1’. which is already fetched.1] (f) + 1 → (dest). Skip if 0 [ label ] INCFSZ f. the result is placed in the W register. . A NOP is executed instead making it a two-cycle instruction. 1 Words: Cycles: Example Before Instruction REG1 = 0xFF Z = 0 After Instruction REG1 = 0x00 Z = 1 The contents of register ‘f’ are incremented. PC = address CONTINUE if REG1≠ 0. skip if result = 0 None 00 1111 dfff ffff The contents of register ‘f’ are incremented.

d = 1 is useful to test a file register since status flag Z is affected.d 0 ≤ f ≤ 127 d ∈ [0.PIC16F627A/628A/648A IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR Literal with W [ label ] IORLW k 0 ≤ k ≤ 255 (W) . The result is placed in the W register.1] (W) .OR.OR. If ‘d’ is ‘1’. destination is W register. (f) → (dest) Z 00 0100 dfff ffff MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f. 1 1 MOVLW 0x5A Words: Cycles: Example Words: Cycles: Example Before Instruction W = 0x9A After Instruction W = 0xBF Z = 0 After Instruction W = 0x5A IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR W with f [ label ] IORWF f. 1 1 IORLW 0x35 The eight bit literal ‘k’ is loaded into W register. If d = 0. 1 1 MOVF REG1. DS40044G-page 125 . the destination is file register f itself.1] (f) → (dest) Z 00 1000 dfff ffff Inclusive OR the W register with register ‘f’.d 0 ≤ f ≤ 127 d ∈ [0. the result is placed back in register ‘f’. 1 1 IORWF REG1. The “don’t cares” will assemble as ‘0’s. the result is placed in the W register. If ‘d’ is ‘0’. k → (W) Z 11 1000 kkkk kkkk MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Move Literal to W [ label ] k → (W) None 11 00xx kkkk kkkk MOVLW k 0 ≤ k ≤ 255 The contents of the W register is OR’ed with the eight-bit literal ‘k’. 0 Words: Cycles: Example Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93 Z = 1 After Instruction W= value in REG1 register Z = 1 © 2009 Microchip Technology Inc. 0 Words: Cycles: Example The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 1.

Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. GIE (INTCON<7>). This is a twocycle instruction. 1 → GIE None 00 0000 0000 1001 NOP RETFIE No operation. the user can directly address it. do not use this instruction. Interrupts are enabled by setting Global Interrupt Enable bit.PIC16F627A/628A/648A MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Move W to f [ label ] (W) → (f) None 00 0000 1fff ffff OPTION f Syntax: Operands: Operation: Status Affected: Encoding: Description: Load Option Register [ label ] None (W) → OPTION None 00 0000 0110 0010 MOVWF OPTION 0 ≤ f ≤ 127 Move data from W register to register ‘f’. This instruction is supported for code compatibility with PIC16C5X products. Words: Cycles: Example NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example No Operation [ label ] None No operation None 00 0000 0xx0 0000 RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Interrupt [ label ] None TOS → PC. 1 1 NOP Return from Interrupt. 1 1 To maintain upward compatibility with future PIC® MCU products. 1 1 MOVWF REG1 Before Instruction REG1 = 0xFF W = 0x4F After Instruction REG1 = 0x4F W = 0x4F The contents of the W register are loaded in the OPTION register. Using only register instruction such as MOVWF. . Since OPTION is a readable/writable register. 1 2 RETFIE Words: Cycles: Example After Interrupt PC = TOS GIE = 1 DS40044G-page 126 © 2009 Microchip Technology Inc.

This is a two-cycle instruction. • • • RETLW kn. the result is placed in the W register. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. the result is stored back in register ‘f’.1] See description below C 00 1101 dfff ffff The W register is loaded with the eight-bit literal ‘k’.Begin table RETLW k2. End of table The contents of register ‘f’ are rotated one bit to the left through the Carry Flag.W now has table value • • ADDWF PC.offset value • . DS40044G-page 127 .W contains table . C REGISTER F Words: Cycles: Example Words: Cycles: Example 1 1 RLF REG1.PIC16F627A/628A/648A RETLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Return with Literal in W [ label ] RETLW k 0 ≤ k ≤ 255 k → (W). 1 2 RETURN Words: Cycles: Example After Interrupt PC = TOS © 2009 Microchip Technology Inc. 1 2 CALL TABLE.d 0 ≤ f ≤ 127 d ∈ [0.W = offset RETLW k1. 0 REG1=1110 0110 C = 0 TABLE Before Instruction After Instruction REG1=1110 0110 W = 1100 1100 C = 1 Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Subroutine [ label ] None TOS → PC None 00 0000 0000 1000 RETURN Return from subroutine. The program counter is loaded from the top of the stack (the return address). TOS → PC None 11 01xx kkkk kkkk RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] RLF f. This is a two-cycle instruction. If ‘d’ is ‘0’. If ‘d’ is ‘1’.

PD is cleared.PIC16F627A/628A/648A RRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Right f through Carry [ label ] RRF f. result is positive Example 2: Before Instruction W = 2 C = ? After Instruction W = 0 C = 1. 1 1 SLEEP Words: Cycles: Example: DS40044G-page 128 © 2009 Microchip Technology Inc. See Section 14. If ‘d’ is ‘0’. Z 11 110x kkkk kkkk SUBLW k The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. 1 1 SUBLW 0x02 Words: Cycles: Example 1: Words: Cycles: Example 1 1 RRF REG1. 0 → PD TO. The result is placed in the W register.(W) → (W) C. PD 00 0000 0110 0011 SLEEP Example 3: Before Instruction W = C = W = C = 3 ? 0xFF 0.1] See description below C 00 1100 dfff ffff SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] 0 ≤ k ≤ 255 k . result is negative After Instruction Status Affected: Encoding: Description: The power-down Status bit.8 “Power-Down Mode (Sleep)” for more details. . 0 Before Instruction W = 1 C = ? After Instruction W = 1 C = 1. 1 → TO. result is zero Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 SLEEP Syntax: Operands: Operation: [ label ] None 00h → WDT. 0 → WDT prescaler.d 0 ≤ f ≤ 127 d ∈ [0. If ‘d’ is ‘1’. Time out Status bit. Watchdog Timer and its prescaler are cleared. TO is set. The processor is put into Sleep mode with the oscillator stopped. DC. the result is placed back in register ‘f’. the result is placed in the W register. C REGISTER F The W register is subtracted (2’s complement method) from the eightbit literal ‘k’.

the result is stored in the W register. If ‘d’ is ‘0’. result is positive 1 0 Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0x5A TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Load TRIS Register [ label ] TRIS 5≤f≤7 (W) → TRIS register f. 0 Words: Cycles: Example 1: Words: Cycles: Example Before Instruction REG1 = 3 W = 2 C = ? After Instruction REG1 W C DC Z Example 2: = = = = = 1 2 1. (f<7:4>) → (dest<3:0>) None 00 1110 dfff ffff SUBWF f. the result is placed in register ‘f’. DC. result is zero DC = 1 The instruction is supported for code compatibility with the PIC16C5X products. Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 W C Z = = = = 0xFF 2 0. If ‘d’ is ‘1’.(W) → (dest) C. 1 The upper and lower nibbles of register ‘f’ are exchanged.d 0 ≤ f ≤ 127 d ∈ [0. do not use this instruction.d Encoding: Description: Subtract (2’s complement method) W register from register ‘f’. the user can directly address them. 1 1 SUBWF REG1. 1 1 SWAPF REG1. DS40044G-page 129 . If ‘d’ is ‘1’. the result is placed in W register. None 00 0000 0110 0fff f Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 W C Z = = = = 0 2 1.PIC16F627A/628A/648A SUBWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from f [ label ] 0 ≤ f ≤ 127 d ∈ [0. result is negative DC = 0 Words: Cycles: Example © 2009 Microchip Technology Inc. 1 1 To maintain upward compatibility with future PIC® MCU products. the result is stored back in register ‘f’.1] (f) .1] (f<3:0>) → (dest<7:4>). Z Status Affected: 00 0010 dfff ffff SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f. Since TRIS registers are readable and writable. If ‘d’ is ‘0’.

. the result is stored in the W register.d The contents of the W register are XOR’ed with the eight-bit literal ‘k’. 1 Words: Cycles: Example Before Instruction W = 0xB5 After Instruction W = 0x1A Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5 DS40044G-page 130 © 2009 Microchip Technology Inc. 1 1 XORLW 0xAF Words: Cycles: Example: Exclusive OR the contents of the W register with register ‘f’.XOR. the result is stored back in register ‘f’. k → (W) Z 11 1010 kkkk kkkk XORWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR W with f [ label ] 0 ≤ f ≤ 127 d ∈ [0. The result is placed in the W register. (f) → (dest) Z 00 0110 dfff ffff XORWF f.1] (W) . If ‘d’ is ‘0’. 1 1 XORWF REG1.PIC16F627A/628A/648A XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR Literal with W [ label ] XORLW k 0 ≤ k ≤ 255 (W) .XOR. If ‘d’ is ‘1’.

Evaluation Kits.PICkit™ 3 Debug Express • Device Programmers . to full-featured emulators.MPLINKTM Object Linker/ MPLIBTM Object Librarian .Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm.MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers .Programmer (sold separately) . DS40044G-page 131 . through low-cost in-circuit debuggers.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment . from the cost-effective simulators.Mixed C and assembly .PIC16F627A/628A/648A 16.MPASMTM Assembler . and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market.In-Circuit Emulator (sold separately) .0 DEVELOPMENT SUPPORT 16.MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards. This eliminates the learning curve when upgrading to tools with increased flexibility and power.HI-TECH C for Various Device Families .MPLAB ICD 3 .MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators . and download to emulator and simulator tools (automatically updates all project information) • Debug using: . © 2009 Microchip Technology Inc.MPLAB® IDE Software • Compilers/Assemblers/Linkers .Source files (C or assembly) . such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools .PICkit™ 2 Programmer .MPLAB C Compiler for Various Device Families .Simulator .MPLAB SIM Software Simulator • Emulators .In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools.

. For easy source level debugging. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. For easy source level debugging.PIC16F627A/628A/648A 16.6 MPLAB Assembler.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. replacement. PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. universal macro assembler for PIC10/12/16/18 MCUs. omniscient code generation and ease of use. MAP files to detail memory usage and symbol reference.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18. Linker and Librarian for Various Device Families 16. the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. superior code optimization and ease of use. preprocessor. absolute LST files that contain source lines and generated machine code and COFF files for debugging. and one-step driver.4 MPASM Assembler The MPASM Assembler is a full-featured. The compilers include a macro assembler. 16. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. MPLAB C Compiler uses the assembler to produce its object file. When a routine from a library is called from a source file. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker. only the modules that contain that routine will be linked in with the application. the compilers provide symbol information that is optimized to the MPLAB IDE debugger. Intel® standard HEX files.2 MPLAB C Compilers for Various Device Families 16. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS40044G-page 132 © 2009 Microchip Technology Inc. These compilers provide powerful integration capabilities. using directives from a linker script. This allows large libraries to be used efficiently in many different applications. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24. and can run on multiple platforms. deletion and extraction 16. It can link relocatable objects from precompiled libraries. linker. PIC32 and dsPIC devices. These compilers provide powerful integration capabilities.

yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers. The emulator is field upgradable through future firmware downloads in MPLAB IDE.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). lessons. tutorial. new devices will be supported. and new features will be added. The PICkit 3 Debug Express include the PICkit 3. run-time variable watches. Registers can be logged to files for further run-time analysis. MPLAB ICD 3 supports all MPLAB ICD 2 headers. most peripherals and internal registers. noise tolerant.PIC16F627A/628A/648A 16. © 2009 Microchip Technology Inc. On any given instruction. The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful. The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). actions on I/O. demo board and microcontroller. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. and the MPASM and MPLAB Assemblers. a ruggedized probe interface and long (up to three meters) interconnection cables. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed. the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. compiler and MPLAB IDE software. included with each kit. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. Low-Voltage Differential Signal (LVDS) interconnection (CAT5).10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). making it an excellent. DS40044G-page 133 . MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost.7 MPLAB SIM Software Simulator 16. powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). full-speed emulation. The emulator is connected to the design engineer’s PC using a high-speed USB 2. complex breakpoints. economical software development tool. 16. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution. In upcoming releases of MPLAB IDE.8 MPLAB REAL ICE In-Circuit Emulator System 16. hookup cables and CDROM with user’s guide. trace analysis.

Check the Microchip web page (www. halts and single steps the program while the PIC microcontroller is embedded in the application. hookup cables and CDROM with user’s guide. PIC16F5xx). Sigma-Delta ADC. and 32-bit microcontrollers. DS40044G-page 134 © 2009 Microchip Technology Inc.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The PICkit 2 Debug Express include the PICkit 2. PIC12F5xx. In-Circuit-Debugging runs. The boards support a variety of features. . It can also set code protection in this mode. Microchip has a line of evaluation kits and demonstration software for analog filter design. and PIC32 families of 8-bit. It features a large LCD display (128 x 64) for menus and error messages and a modular. Also available are starter kits that contain everything needed to experience the specified device. CAN. 16. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 16. development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. Evaluation Kits. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits. compiler and MPLAB IDE software. LCD displays. PIC18F. 16-bit. The demonstration and development boards can be used in teaching environments. the MPLAB PM3 Device Programmer can read. speakers. for prototyping custom circuits and for learning about various microcontroller applications. In Stand-Alone mode.PIC16F627A/628A/648A 16. dsPIC30. The full featured Windows® programming interface supports baseline (PIC10F.13 Demonstration/Development Boards.com) for the complete list of demonstration. PIC24. PowerSmart battery management. development and evaluation kits. switches. temperature sensors. and many Microchip Serial EEPROM products. When halted at a breakpoint. plus many more. including LEDs. and Starter Kits A wide variety of demonstration. CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. demo board and microcontroller. RS-232 interfaces. detachable socket assembly to support various package types. SEEVAL® evaluation system. verify and program PIC devices without a PC connection. This usually includes a single application and debug capability. dsPIC33. midrange (PIC12F6xx. flow rate sensing. KEELOQ® security ICs. the file registers can be examined and modified. The ICSP™ cable assembly is included as a standard item. IrDA®. tutorial.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal. potentiometers and additional EEPROM memory. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. lessons. all on one board.microchip. PIC16F).

...................................................................... IIK (VI < 0 or VI > VDD)..................................................................300 mA Maximum current into VDD pin ..........200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.................................-0....................................................................................................................................... DS40044G-page 135 ...........................................................0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.............................25 mA Maximum current sunk by PORTA and PORTB (Combined)... Note: Voltage spikes below VSS at the MCLR pin...................................... IOK (Vo < 0 or Vo >VDD).........................................................-0................................................................ © 2009 Microchip Technology Inc.................................................. -40 to +125°C Storage temperature ............................................................................3V to VDD + 0.............200 mA Maximum current sourced by PORTA and PORTB (Combined)..................................... ± 20 mA Output clamp current....................3 to +14V Voltage on all other pins with respect to VSS ........................................................................................................800 mW Maximum current out of VSS pin ............................................................... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied......................................................................................................... may cause latch-up............ -0........ Exposure to maximum rating conditions for extended periods may affect device reliability..........................................250 mA Input clamp current................ a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS..... ± 20 mA Maximum output current sunk by any I/O pin..PIC16F627A/628A/648A 17.............25 mA Maximum output current sourced by any I/O pin ...................................... -65°C to +150°C Voltage on VDD with respect to VSS .................................. inducing currents greater than 80 mA............................................3V Total power dissipation(1) .................................................................................................................................................3 to +6................. Thus.............5V Voltage on MCLR and RA4 with respect to VSS ...........................................................................................

-40°C ≤ TA ≤ +85°C 4 10 FREQUENCY (MHz) 20 25 Note: The shaded region indicates the permissible combinations of voltage and frequency.0 3.0 4.PIC16F627A/628A/648A FIGURE 17-1: 6.5 2. FIGURE 17-2: 6.0 2.5 0 4 10 FREQUENCY (MHz) 20 25 PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH. -40°C ≤ TA ≤ +125°C Note: The shaded region indicates the permissible combinations of voltage and frequency.5 4.0 2.0 VDD (VOLTS) 4.5 5. DS40044G-page 136 © 2009 Microchip Technology Inc.5 VDD (VOLTS) 4.5 5.0 5.0 5.0 3.5 3. .0 0 PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH.5 3.

PIC16F627A/628A/648A
17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and -40°C ≤ Ta ≤ +125°C for extended Min Typ† Max Units Conditions

PIC16LF627A/628A/648A (Industrial) PIC16F627A/628A/648A (Industrial, Extended) Param No. D001 D002 D003 VDR Sym VDD Characteristic/Device Supply Voltage PIC16LF627A/628A/648A PIC16F627A/628A/648A RAM Data Retention Voltage(1)

2.0 3.0 — —

— — 1.5* VSS

5.5 5.5 — —

V V V V Device in Sleep mode See Section 14.4 “Poweron Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR)”on Power-on Reset for details See Section 14.4 “Poweron Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR)” on Power-on Reset for details BOREN configuration bit is set BOREN configuration bit is set, Extended

VPOR VDD Start Voltage to ensure Power-on Reset

D004

SVDD VDD Rise Rate to ensure Power-on Reset

0.05*

V/ms

D005

VBOR Brown-out Reset Voltage

3.65 3.65

4.0 4.0

4.35 4.4

V V

Legend: * † Note 1:

Rows with standard voltage device data only are shaded for improved readability. These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

© 2009 Microchip Technology Inc.

DS40044G-page 137

PIC16F627A/628A/648A
17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial Conditions Min† Typ Max Units VDD 2.0 3.0 — — — Peripheral Module Current (ΔIMOD)(1) LF D021 LF/F LF/F LF D023 LF/F LF D024 LF/F LF D025 LF/F — — — D022 — — — — — — — — — — — Supply Current (IDD) LF D010 LF/F LF D011 LF/F LF D012 LF/F LF D012A LF/F LF/F — — — — — — — — — — — — D013 Note 1: — — 10 15 28 125 175 320 250 450 710 395 565 0.895 2.5 2.75 15 25 48 190 340 520 350 600 995 465 785 1.3 2.9 3.3 μA μA μA μA μA μA μA μA μA μA μA mA mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator Mode FOSC = 4 MHz INTOSC FOSC = 4 MHz XT Oscillator Mode FOSC = 1 MHz XT Oscillator Mode FOSC = 32 kHz LP Oscillator Mode 1 2 9 29 30 15 22 44 34 50 80 1.2 1.3 1.8 2.0 3.4 17.0 52 55 22 37 68 55 75 110 2.0 2.2 2.9 μA μA μA μA μA μA μA μA μA μA μA μA μA μA 2.0 3.0 5.0 4.5 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 T1OSC Current VREF Current Comparator Current (Both comparators enabled) BOR Current WDT Current — — 0.01 0.01 0.02 5.5 5.5 0.80 0.85 2.7 V V μA μA μA — — 2.0 3.0 5.0 WDT, BOR, Comparators, VREF and T1OSC: disabled Note

DC CHARACTERISTICS

Param No.

LF and F Device Characteristics

Supply Voltage (VDD) D001 LF LF/F LF D020 LF/F

Power-down Base Current (IPD)

The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. Max values should be used when calculating total current consumption.

DS40044G-page 138

© 2009 Microchip Technology Inc.

PIC16F627A/628A/648A
17.3 DC Characteristics: PIC16F627A/628A/648A (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +125°C for extended Conditions Device Characteristics Min† Typ Max Units VDD — — 3.0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.01 0.02 2 9 29 30 22 44 50 83 1.3 1.8 15 28 175 320 450 0.710 565 0.895 2.5 2.75 5.5 4 8 9 20 52 55 37 68 75 110 4 6 28 54 340 520 650 1.1 785 1.3 2.9 3.5 V μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA mA μA mA mA mA — 3.0 5.0 3.0 5.0 4.5 5.0 3.0 5.0 3.0 5.0 3.0 5.0 3.0 5.0 3.0 5.0 3.0 5.0 3.0 5.0 4.5 5.0 FOSC = 32 kHz LP Oscillator Mode FOSC = 1 MHz XT Oscillator Mode FOSC = 4 MHz XT Oscillator Mode FOSC = 4 MHz INTOSC FOSC = 20 MHz HS Oscillator Mode T1OSC Current Comparator Current (Both comparators enabled) VREF Current BOR Current WDT, BOR, Comparators, VREF and T1OSC: disabled WDT Current Note
DC CHARACTERISTICS

Param No.

Supply Voltage (VDD) D001 Power-down Base Current (IPD) D020E

Peripheral Module Current (ΔIMOD)(1) D021E D022E D023E D024E D025E Supply Current (IDD) D010E D011E D012E D012AE D013E Note 1:

The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. Max values should be used when calculating total current consumption.

© 2009 Microchip Technology Inc.

DS40044G-page 139

0V. VDD = 4. VDD = 4.0V.6 V V V V V V VDD = 4.2 VDD 0. PIC16LF627A/628A/648A In XT.0V . +85° to +125°C RA4 pin PIC16F627A/628A/648A.5* V V V D150 VOD Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100* D101* COSC2 OSC2 pin CIO All I/O pins/OSC2 (in RC mode) — — — — 15 50 pF pF Note * These parameters are characterized but not tested.8V 0. the OSC1 pin is a Schmitt Trigger input.25 VDD + 0.0 mA. Sym VIL Characteristic/Device Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger input(4) MCLR.7 VDD – 0.8 0. VPIN = VSS VOH D090 Output High Voltage(3) I/O ports (Except RA4(4) ) VDD – 0.5 V. (3) I/O ports (Except PORTA) PORTA(4) RA4/T0CKI OSC1. RA4/T0CKI.5 mA.5V to 5.PIC16F627A/628A/648A 17. It is not recommended that the PIC16F627A/628A/648A be driven with external clock in RC mode.0 mA.5 V.0 μA μA μA μA VSS ≤ VPIN ≤ VDD.5 V. +85° to +125°C IOH = -3. pin at high-impedance VSS ≤ VPIN ≤ VDD.9 VDD 0. HS and LP modes when external clock used to drive OSC1. VDD = 4. 3: Negative current is defined as coming out of the pin. Higher leakage current may be measured at different input voltages. DS40044G-page 140 © 2009 Microchip Technology Inc.6 0. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. pin at high-impedance VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD. -40° to +85°C IOH = -2. These parameters are for design guidance only and are not tested.15 VDD 0. VDD = 4. 1: In RC oscillator configuration. 4: Includes OSC1 and OSC2 when configured as I/O pins.7 VDD 50 — — — — — — 200 VDD VDD VDD VDD VDD VDD VDD 400 V V V V V V V μA VDD = 4.5 ±1.8 VDD 1. .0 ±0.5V otherwise (Note1) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger input(4) MCLR RA4/T0CKI OSC1 (XT and LP) OSC1 (in RC mode) OSC1 (in HS mode) PORTB weak pull-up current Input Leakage Current(2). XT.OSC1 (in RC mode) OSC1 (in HS) OSC1 (in LP and XT) D030 D031 D032 D033 VIH D040 D041 D042 D043 D043A D043B D070 IPURB IIL D060 D061 D063 VOL D080 VSS VSS VSS VSS VSS VSS — — — — — — 0. † Data in “Typ” column is at 5.5 V. MCLR Output Low Voltage I/O ports(4) — — — — 0. Extended) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC specification Table 17-2 and Table 17-3 Min Typ† Max Unit Conditions DC CHARACTERISTICS Param.3 0.3 VDD 0.5V otherwise (Note1) VDD = 5. HS and LP oscillator configuration 2. 25°C unless otherwise stated.5 mA.8 VDD 0. — — — — — — — — ±1.2 VDD 0.0 ±5. -40° to +85°C IOL = 7. CLKIN or CLKOUT.6 V V IOL = 8. No. The specified levels represent normal operating conditions.4 DC Characteristics: PIC16F627A/628A/648A (Industrial.5V to 5.7 — — — — — — 8.

0V.5 8* — — E/W E/W V ms Year E/W -40°C ≤ TA ≤ 85°C 85°C ≤ TA ≤ 125°C VMIN = Minimum operating voltage Provided no other specifications are violated -40°C to +85°C Min Typ† Max Units Conditions DC CHARACTERISTICS Parameter No. Sym VDD for Block erase VIE VPEW VDD for write Block Erase cycle time TIE TPEW Write cycle time TRETP Characteristic Retention These parameters are characterized but not tested. Data in “Typ” column is at 5.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. These parameters are for design guidance only and are not tested.5 VMIN — — 40 100K 10K — — — 4 2 — — — 5. © 2009 Microchip Technology Inc. Extended) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC specification Table 17-2 and Table 17-3 Characteristic Data EEPROM Memory D120 D120A D121 D122 D123 D124 Endurance ED ED Endurance VDRW VDD for read/write TDEW Erase/Write cycle time TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory D130 D130A D131 D132 D132A D133 D133A D134 * † Note 1: EP EP VPR Endurance Endurance VDD for read 10K 1000 VMIN 4.PIC16F627A/628A/648A TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial.5 8* 4* — E/W E/W V V V ms ms year -40°C ≤ TA ≤ 85°C 85°C ≤ TA ≤ 125°C VMIN = Minimum operating voltage VMIN = Minimum operating voltage VDD > 4.5 5.5V Provided no other specifications are violated 100K 10K VMIN — 40 1M 1M 100K — 4 — 10M — 5. Refer to Section 13.5 5. DS40044G-page 141 . 25°C unless otherwise stated.

0V to 5. Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time (1) Sym VIOFF VICM CMRR TRESP Min — 0 55* — — — Typ ±5.0V < VDD < 5.0V to 3. Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Sym VRES VRAA VRUR TSET Min — — — — — Typ — — — 2k* — Max VDD/24 VDD/32 1/4(2)* 1/2(2)* — 10* Units LSb LSb LSb LSb Ω μs Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0) * These parameters are characterized but not tested. unless otherwise stated. while the other input transitions from VSS to VDD.PIC16F627A/628A/648A TABLE 17-2: Param No. . the VREF output voltage levels on RA2 described by the equation:[VDD/2 ± (3 – VDD)/2] may cause the Absolute Accuracy (VRAA) of the VREF output signal on RA2 to be greater than the stated max. -40°C < TA < +125°C.5V. TABLE 17-3: Spec No.5V.5V -40° to +85°C VDD = 3. D300 D301 D302 D303 COMPARATOR SPECIFICATIONS Operating Conditions: 2. 2: When VDD is between 2. Note 1: Response time measured with one comparator input at (VDD – 1.0V < VDD <5.5V -85° to +125°C VDD = 2. -40°C < TA < +125°C.5* — 400* 600* 600* 10* Units mV V db ns ns ns μs Comments VDD = 3.0V and 3.5)/2. DS40044G-page 142 © 2009 Microchip Technology Inc.0 — — 300 400 400 300 Max ±10 VDD – 1.0V to 5. D310 D311 D312 D313 VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 2.0V -40° to +85°C D304 Comparator Mode Change to Output Valid TMC2OV — * These parameters are characterized but not tested.0V. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. unless otherwise stated.

TppS2ppS 2.PIC16F627A/628A/648A 17.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS T F pp ck io mc S F H I L Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-Impedance CLKOUT I/O port MCLR osc t0 OSC1 T0CKI Frequency T Time Lowercase subscripts (pp) and their meanings: Uppercase letters and their meanings: FIGURE 17-3: LOAD CONDITIONS Load Condition 1 VDD/2 RL Load Condition 2 Pin VSS RL = 464Ω CL Pin VSS CL CL = 50 pF for all pins except OSC2 15 pF for OSC2 output © 2009 Microchip Technology Inc. DS40044G-page 143 .

25°C unless otherwise stated. All devices are tested to operate at “Min” values with an external clock applied to the OSC1 pin. VDD = 5.1 1 — — — Typ† — — — — — — — 4 48 — — — — — — — 250 21 TCY — — Max 4 20 200 4 4 20 200 — — — — — — 10. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption.6 Timing Diagrams and Specifications EXTERNAL CLOCK TIMING Q4 OSC1 1 2 CLKOUT 3 3 4 4 Q1 Q2 Q3 Q4 Q1 FIGURE 17-4: TABLE 17-4: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC Oscillator Frequency(1) — 0. Data in “Typ” column is at 5.0V MHz XT Osc mode MHz HS Osc mode kHz LP Osc mode MHz INTOSC mode (fast) kHz INTOSC mode (slow) ns ns μs ns ns ns μs ns μs ns ns — XT and RC Osc mode HS. TosH RC Instruction Cycle Time External CLKIN (OSC1) High External CLKIN Low External Biased RC Frequency 200 100* 10 kHz* These parameters are characterized but not tested. EC Osc mode kHz LP Osc mode MHz RC Osc mode. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. the “Max” cycle time limit is “DC” (no clock) for all devices. These parameters are for design guidance only and are not tested.000 — — — DC — 4 MHz Units Conditions MHz XT and RC Osc mode.0V 1 TOSC External CLKIN Period(1) 250 50 5 Oscillator Period(1) 250 250 50 5 — — 2 3 4 * † Note 1: TCY TosL. When an external clock input is used.0 V MHz HS. TOSC L/H duty cycle VDD = 5.000 1. DS40044G-page 144 © 2009 Microchip Technology Inc.0V.PIC16F627A/628A/648A 17. . Instruction cycle period (TCY) equals four times the input oscillator time-based period. EC Osc mode LP Osc mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode INTOSC mode (fast) INTOSC mode (slow) TCY = 4/FOSC XT oscillator. VDD = 5.

96 3.20 Units MHz MHz VDD = 3.04 4.5 V.PIC16F627A/628A/648A TABLE 17-5: Parameter No. -40°C to +85°C VDD = 5. 21 15 19 23 12 18 16 New Value © 2009 Microchip Technology Inc.5V 0°C ≤ TA ≤ +85°C MHz 2.0V.80 Typ 4 4 4 4 Max — 4. -40°C to +85°C VDD = 3.5V -40°C ≤ TA ≤ +85°C (IND) -40°C ≤ TA ≤ +125°C (EXT) μs μs μs VDD = 2. F10 F13 PRECISION INTERNAL OSCILLATOR PARAMETERS Sym Characteristic Oscillator Center frequency Oscillator Accuracy Min — 3.0V. DS40044G-page 145 .0V ≤ VDD ≤ 5. * Characterized but not tested. -40°C to +85°C Conditions FIOSC ΔIOSC F14* TIOSCST Oscillator Wake-up from Sleep — — — 6 4 3 8 6 5 start-up time Legend: TBD = To Be Determined.0V.92 3.0V ≤ VDD ≤ 5.08 4. 25°C MHz 2. FIGURE 17-5: CLKOUT AND I/O TIMING Q4 Q1 Q2 11 22 Q3 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) Old Value 20.

0V. . † Data in “Typ” column is at 5. FIGURE 17-6: RESET. 10 10A 11 11A 12 12A 13 13A 14 15 16 17 18 TCKL2IOV CLKOUT ↓ to Port out valid PIC16F62XA TIOV2CKH Port in valid before CLKOUT ↑ TCKH2IOI TOSH2IOV TOSH2IOI Port in hold after CLKOUT ↑ OSC1↑ (Q1 cycle) to Port out valid PIC16F62XA PIC16LF62XA TCKF CLKOUT fall time TCKR CLKOUT rise time TOSH2CKH OSC1↑ to CLKOUT↑ CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic PIC16F62XA PIC16LF62XA PIC16F62XA PIC16LF62XA PIC16F62XA PIC16LF62XA PIC16F62XA PIC16LF62XA Min — — — — — — — — — TOSC+200 ns* 0 — — 100* 200* PIC16LF62XA TOSC+400 ns* Typ† 75 — 75 — 35 — 35 — — — — — 50 — — Max 200* 400* 200* 400* 100* 200* 100* 200* 20* — — — 150* 300* — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TOSH2CKL OSC1↑ to CLKOUT↓ OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) * These parameters are characterized but not tested. OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR PWRT Time out OST Time out Internal Reset Watchdog Timer Reset 34 I/O Pins 33 32 30 31 34 DS40044G-page 146 © 2009 Microchip Technology Inc.PIC16F627A/628A/648A TABLE 17-6: Parameter No. WATCHDOG TIMER. 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

WATCHDOG TIMER. DS40044G-page 147 .0* — Units ns ms — ms μs μs Conditions VDD = 5V. -40°C to +85°C TOSC = OSC1 period VDD = 5V. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI/CMP2 40 41 42 RB6/T1OSO/T1CKI/PGC 45 46 47 48 TMR0 OR TMR1 © 2009 Microchip Technology Inc. These parameters are characterized but not tested. 25°C unless otherwise stated.0V. -40°C to +85°C VDD ≤ VBOR (D005) TBD = To Be Determined. Data in “Typ” column is at 5. These parameters are for design guidance only and are not tested.PIC16F627A/628A/648A FIGURE 17-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 17-7: Parameter No. -40°C to +85°C VDD = 5V. OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Sym TMCL TWDT TOST TPWRT TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 2000 7* — 28* — 100* Typ† — 18 1024 TOSC 72 — — Max — 33* — 132* 2. 30 31 32 33 34 35 Legend: * † RESET.

5TCY + 20* 10* 0.. No Prescaler Time Synchronous..5TCY + 20* 15* 25* 30* 50* Greater of: 20 or TCY + 40* N 20 or Asynchronous PIC16F62XA PIC16LF62XA Greater of: TCY + 40* N 60* 100* — Typ† — — — — — Max Units Conditions — — — — — ns ns ns ns ns N = prescale value (2. These parameters are for design guidance only and are not tested.PIC16F627A/628A/648A TABLE 17-8: Param No.768 kHz watch crystals and their manufactured tolerances. . 8) — 45 TT1H T1CKI High Synchronous. 4. PIC16F62XA with Prescaler PIC16LF62XA Asynchronous PIC16F62XA PIC16LF62XA — — — — — — — — — — — — — — — — — — — — — — 46 TT1L T1CKI Low Synchronous. 2TOSC — 7TOSC — Data in “Typ” column is at 5V. 40 41 42 Sym TT0H TT0L TT0P TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.. No Prescaler Time Synchronous.5TCY + 20* 10* Greater of: 20 or TCY + 40* N 0. Note 1: DS40044G-page 148 © 2009 Microchip Technology Inc. 25°C unless otherwise stated. . 256) ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1.7(1) — — — ns ns kHz FT1 Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN) 48 TCKEZTMR1 Delay from external clock edge to timer increment * † These parameters are characterized but not tested. 2. Higher value crystal frequencies may not be compatible with this crystal driver. PIC16F62XA with Prescaler PIC16LF62XA Asynchronous PIC16F62XA PIC16LF62XA 47 TT1P T1CKI input Synchronous PIC16F62XA period PIC16LF62XA — — — — 32. 4. This oscillator is intended to work only with 32.5TCY + 20* 15* 25* 30* 50* 0.

5TCY + 20* 10* 20* 3TCY + 40* N PIC16F62XA PIC16LF62XA PIC16F62XA PIC16LF62XA Typ† Max Units — — — — — — — 10 25 10 25 — — — — — — — 25* 45* 25* 45* ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1. 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.PIC16F627A/628A/648A FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS RB3/CCP1 (CAPTURE MODE) 50 52 51 RB3/CCP1 (COMPARE OR PWM MODE) 53 54 TABLE 17-9: Param Sym No.5TCY + 20* 10* 20* 0.4 or 16) Conditions TCCL CCP input low time 51 TCCH CCP input high time No Prescaler PIC16F62XA With Prescaler PIC16LF62XA 52 53 54 * † TCCP CCP input period TCCR CCP output rise time TCCF CCP output fall time These parameters are characterized but not tested. DS40044G-page 149 . Data in “Typ” column is at 5V. 50 CAPTURE/COMPARE/PWM REQUIREMENTS Characteristic No Prescaler PIC16F62XA With Prescaler PIC16LF62XA Min 0. © 2009 Microchip Technology Inc.

.PIC16F627A/628A/648A NOTES: DS40044G-page 150 © 2009 Microchip Technology Inc.

In some graphs or tables. ‘Max’ or ‘Min’ represents (mean + 3σ) or (mean . The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples.3σ) respectively.0 5. DS40044G-page 151 .PIC16F627A/628A/648A 18.e.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. the data presented are outside specified operating range (i.5 3.5 4. outside specified VDD range). VDD (-40°C TO 25°C) IPD (nA) 80 60 -40°C 40 +25°C 20 0 2.0 2.5 0°C VDD (Volts) © 2009 Microchip Technology Inc. over the whole temperature range. where σ is standard deviation. FIGURE 18-1: 160 140 120 100 TYPICAL BASELINE IPD vs. This is for information only and devices are ensured to operate properly only within the specified range. ‘Typical’ represents the mean of the distribution at 25°C.0 3.0 4..5 5.

0 2.0 2.0 3.5 VDD (Volts) FIGURE 18-3: TYPICAL BASELINE CURRENT IPD vs.5 3.5 4.4 1.0 4.5 5. VDD (125°C) 2.2 2.5 VDD (Volts) DS40044G-page 152 © 2009 Microchip Technology Inc.5 4.0 IPD (μA) 1.2 1.PIC16F627A/628A/648A FIGURE 18-2: 300 280 260 240 220 TYPICAL BASELINE IPD vs.0 5.5 3.0 3.8 +125°C 1. VDD (85°C) IPD (nA) 200 +85°C 180 160 140 120 100 2.0 2.0 4. .6 1.0 5.5 5.4 2.

7 4. DS40044G-page 153 .2 5.5 5 5.1 5. VDD 30 25 20 125°C 85°C 25°C 0°C -40°C IPD (μA) 15 10 5 0 2 2.9 5.5 3 3. VDD 40 38 36 34 32 30 28 26 24 22 20 4.8 4.3 5.4 5.5 4.5 VDD (Volts) © 2009 Microchip Technology Inc.5 125°C 85°C 25°C 0°C -40°C IPD (μA) VDD (Volts) FIGURE 18-5: TYPICAL SINGLE COMPARATOR IPD vs.0 5.PIC16F627A/628A/648A FIGURE 18-4: TYPICAL BOR IPD vs.5 4 4.6 4.

VDD 16 14 12 10 8 6 4 2 0 2.0 3.0 4.5 5.5 125°C 85°C 25°C 0°C -40°C IPD (μA) VDD (Volts) FIGURE 18-7: TYPICAL WDT IPD vs.0 5.0 2.PIC16F627A/628A/648A FIGURE 18-6: TYPICAL VREF IPD vs.5 4.0 4. VDD 100 90 80 70 60 50 40 30 20 2.0 3.0 2.5 3.5 4.5 5.5 3. .5 125°C 85°C 25°C 0°C -40°C IPD (μA) VDD (Volts) DS40044G-page 154 © 2009 Microchip Technology Inc.0 5.

0% 3.0% -5.0% -2.0% -4.5 4 4.0% -40 25 Temperature (ºC) 85 125 © 2009 Microchip Technology Inc.5 VDD (V) FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs.0% 4.5 5 5.0% -1. DS40044G-page 155 . TEMPERATURE VDD = 5 VOLTS 5.0% 0.0% Change from Calibration Target (%) 2.0% -3.PIC16F627A/628A/648A FIGURE 18-8: 5 AVERAGE IPD_TIMER1 4 3 -40C 0C 25C 85C 125 IPD (uA) 2 1 0 2 2.0% 1.5 3 3.

0% -3.0% 1.0% -4.0% 4.0% Change from Calibration Target (%) 2.0% -4.0% 0. TEMPERATURE VDD = 2 VOLTS 5.0% -1.0% -3.0% 4.0% Change from Calibration Target (%) 2.0% -1.0% 1.0% 3.0% -2.0% -2. .0% -5.0% 0.PIC16F627A/628A/648A FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs.0% -40 25 Temperature (ºC) 85 125 DS40044G-page 156 © 2009 Microchip Technology Inc.0% -40 25 Temperature (ºC) 85 125 FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs.0% -5.0% 3. TEMPERATURE VDD = 3 VOLTS 5.

0% 0.0% 2 2.0% 0.0% -2.0% -4.0% -4.0% 2 2.5 5 5.PIC16F627A/628A/648A FIGURE 18-12: 5.5 VDD (V) 4 4.0% 1.5 3 3.0% 3.0% -5.0% TYPICAL INTERNAL OSCILLATOR DEVIATION vs.5 VDD (V) 4 4.0% -5.0% Change from Calibration Target (%) 2.0% 3.5 FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs.5 © 2009 Microchip Technology Inc.5 5 5.0% -1.0% 4.0% -3. VDD AT 25°C – 4 MHz MODE Change from Calibration Target (%) 2.0% -3. DS40044G-page 157 .0% 4.0% -2.0% 1.5 3 3.0% -1. VDD TEMPERATURE = -40°C TO 85°C 5.

PIC16F627A/628A/648A FIGURE 18-14: INTERNAL OSCILLATOR IDD vs.80 0. .5 3 3.00 2 2.5 VDD (V) 4 4.5 DS40044G-page 158 © 2009 Microchip Technology Inc.5 VDD (V) 4 4.40 25 C Avg -40 C 1.5 5 5.60 0.5 3 3.5 5 5.20 0.40 0.20 1.5 FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs.00 IDD (mA) 0. VDD AT 25°C – SLOW MODE 60 55 Oscillator Frequency (kHz) 50 45 40 35 30 2 2. VDD – 4 MHz MODE 85 C 1.

5 VDD (Volts) © 2009 Microchip Technology Inc.5 3 3. VDD.5 5 5. FOSC = 1 MHz (XT OSCILLATOR MODE) 500 450 400 350 125°C 85°C 25°C 0°C -40°C IPD (μA) 300 250 200 150 100 2.5 FIGURE 18-17: IPD (μA) SUPPLY CURRENT (IDD vs.5 4.0 5.0 3. VDD – SLOW MODE 85 C 25 C Avg -40 C 180 160 140 120 100 80 60 40 20 0 2 2.0 4.5 3.5 VDD (V) 4 4. DS40044G-page 159 .5 5.PIC16F627A/628A/648A FIGURE 18-16: INTERNAL OSCILLATOR IDD vs.0 2.

5 5.1 5.5 2.0 125°C 85°C 25°C 0°C -40°C IDD (mA) 2.5 3.0 3.8 4.5 4.7 4.2 5.5 VDD (Volts) DS40044G-page 160 © 2009 Microchip Technology Inc.5 4.0 4. FOSC = 4 MHz (XT OSCILLATOR MODE) 1000 900 800 700 600 500 400 300 200 2.5 125°C 85°C 25°C 0°C -40°C IPD (μA) VDD (Volts) FIGURE 18-19: SUPPLY CURRENT (IDD) vs. VDD.0 4.6 4. FOSC = 20 MHz (HS OSCILLATOR MODE) 4.3 5.PIC16F627A/628A/648A FIGURE 18-18: SUPPLY CURRENT (IDD vs.0 5.0 5. VDD.0 3.9 5.4 5. .0 2.5 3.

VDD (-40°C TO +125°C) WDT Time-out 50 45 40 35 30 25 20 15 10 5 0 2 2.5 4 4.5 3 3. DS40044G-page 161 .PIC16F627A/628A/648A FIGURE 18-20: TYPICAL WDT PERIOD vs.5 -40 0 25 85 125 Time (mS) V DD (V) © 2009 Microchip Technology Inc.5 5 5.

.PIC16F627A/628A/648A NOTES: DS40044G-page 162 © 2009 Microchip Technology Inc.

.1 PACKAGING INFORMATION Package Marking Information 18-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F627A -I/P e3 0410017 18-Lead SOIC (.X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. thus limiting the number of available characters for customer-specific information.PIC16F627A/628A/648A 19. In the event the full Microchip part number cannot be marked on one line. it will be carried over to the next line.0 19..300”) XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC16F628A -E/SO e3 0410017 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16F648A -I/SS e3 0410017 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 16F628A -I/ML e3 0410017 Legend: XX. DS40044G-page 163 . The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. © 2009 Microchip Technology Inc.

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.PIC16F627A/628A/648A NOTES: DS40044G-page 170 © 2009 Microchip Technology Inc.

D020E Revise Section 18.2.1. Data EEPROM Write Revise Sections 17. Revisions to Section 14. modified graphs. Replaced Development Support Section. DS40044G-page 171 . DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. Param No. Revision G (10/2009) Corrected 28-lead QFN Package in Section 19. Revision D Revise Example 13-2.PIC16F627A/628A/648A APPENDIX A: Revision A This is a new data sheet.0 TABLE B-1: DEVICE DIFFERENCES Memory Device Flash Program RAM Data EEPROM Data PIC16F627A PIC16F628A PIC16F648A 1024 x 14 2048 x 14 4096 x 14 224 x 8 224 x 8 256 x 8 128 x 8 128 x 8 256 x 8 Revision C General revisions throughout. D020 and 17. Replaced Revision F (03/2007) Replaced Package Drawings (Rev. Param No. © 2009 Microchip Technology Inc. Revised Product ID System.3.0 graphs Revision E Section 19. Example 1 Revised DC Characteristics 17-2 and 17-3 Revised Tables 17-4 and 17-6 Corrected Table and Figure numbering in Section 17. Revision B Revised 28-Pin QFN Pin Diagram Revised Figure 5-4 Block Diagram Revised Register 7-1 TMR1ON Revised Example 13-4 Data EEPROM Refresh Routine Revised Instruction Set SUBWF. AM).0 Packaging Information: package drawings and added note. Section 18.0 – Special Features of the CPU.

. this device may have different performance characteristics than its earlier version. See Microchip web (www. D. the Timer1 oscillator was designed to run up to 200 kHz. 4. 7. Due to process differences in the manufacture of this device. Timer1 Oscillator is now designed for 32.com). In the PIC16F627/ 628. Note: 5. It has been tested to an electrical specification designed to determine its conformance with these parameters. Code protection for the program memory has changed from code-protect sections of memory to code-protect of the whole memory. 6. The Dual-Speed Oscillator mode only works in the INTOSC oscillator mode. These differences may cause this device to perform differently in your application than the earlier version of this device. They have been replaced with one configuration bit<13> CP. In the PIC16F627/628. Enabling Brown-out Reset (BOR) does not automatically enable the Power-up Timer (PWRT) the way it did in the PIC16F627/628. 2.PIC16F627A/628A/648A APPENDIX C: DEVICE MIGRATIONS APPENDIX D: This section describes the functional and electrical specification differences when migrating between functionally similar devices. the Dual-Speed Oscillator mode worked in both the INTRC and ER oscillator modes. PIC16F627/628 to a PIC16F627A/ 628A ER mode is now RC mode. MIGRATING FROM OTHER PIC® DEVICES C. “Brown-out Detect (BOD)” terminology has changed to “Brown-out Reset (BOR)” to better represent the function of the Brown-out circuitry.768 kHz operation.2 PIC16C622A to PIC16F627A/628A/ 648A Migration site for availability 3. This discusses some of the issues in migrating from other PIC MCU devices to the PIC16F627A/628A/ 648A family of devices. This device has been designed to perform to the parameters of its data sheet. The configuration bits CP0 and CP1 in the PIC16F627/628 do not exist in the PIC16F627A/ 628A.microchip.com). DS40044G-page 172 © 2009 Microchip Technology Inc.1 1. INTRC is now called INTOSC.microchip. (such as from a PIC16F627 to a PIC16F627A). D.1 PIC16C62X/CE62X to PIC16F627A/ 628A/648A Migration site for availability See Microchip web (www.

Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides. This web site is used as a means to make files and information easily available to customers. the web site contains the following information: • Product Support – Data sheets and errata. access the Microchip web site at www.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ). online discussion groups. listing of seminars and events. revisions or errata related to a specified product family or development tool of interest.microchip.com. user’s guides and hardware support documents. latest Microchip press releases.microchip. click on Customer Change Notification and follow the registration instructions. design resources. technical support requests. listings of Microchip sales offices. Accessible by using your favorite Internet browser. representative or field application engineer (FAE) for support. Technical support is available through the web site at: http://support.microchip. © 2009 Microchip Technology Inc.com. distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor. updates. A listing of sales offices and locations is included in the back of this document.PIC16F627A/628A/648A THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www. To register. Subscribers will receive e-mail notification whenever there are changes. Local sales offices are also available to help customers. DS40044G-page 173 . application notes and sample programs.

What deletions from the document could be made without affecting the overall usefulness? 6. please FAX your comments to the Technical Publications Manager at (480) 792-4150. clarity. Is there any incorrect or misleading information (what and where)? 7. What are the best features of this document? 2. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ . why? 4._________ Application (optional): Would you like a reply? Y N Literature Number: DS40044G FAX: (______) _________ . and ways in which our documentation can better serve you. Do you find the organization of this document easy to follow? If not. How would you improve this document? DS40044G-page 174 © 2009 Microchip Technology Inc._________ Device: PIC16F627A/628A/648A Questions: 1.PIC16F627A/628A/648A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. subject matter. What additions to the document do you think would enhance the structure and subject? 5. If you wish to provide your comments on organization. Please list the following information. . and use this outline to provide us with your comments about this document. How does this document meet your hardware and software development needs? 3.

................................................... 173 Customer Notification Service .... 91 EECON2 Register .................................. 122 CMCON Register............................................................................................................... 17 DECF Instruction .. 63 Code Examples Data EEPROM Refresh Routine ........................ 63 Configuration .................................................................................................................. See Capture CCP1 ................................................. 132 B Baud Rate Error ............... 58 Block Diagram........................................................................................... 97 Crystal Operation....................................................... 5 External Crystal Oscillator Circuit ................................................................................................................. 57 CCP1X:CCP1Y Bits .............................................................. 123 Development Support .............................................................................................................................................................. 119 ADDWF Instruction ..................................................................................... 103 BSF Instruction ............................................................................................................................................................................................................................................................................. 58 Software Interrupt ................................................................ 57 CCPR1H Register.......................................................................................... 65 Compare (CCP Module) ................................... 58 Capture/Compare/PWM (CCP)..... 171 Device Migrations ...... 92 EECON1 register ........................................................... 58 CCP Pin Configuration...................... 132 CALL Instruction ....... 131 Device Differences............................ See PWM Timer Resources.... 57 Clocking Scheme/Instruction Cycle ............... 57 CCP1CON Register .............................. 113 COMF Instruction............................................................................................. 94 Write Verify .................................................................................................................................... 59 Timer1 Mode Selection................................................................................................................ 58 Software Interrupt ........... 58 Block Diagram .......................... DS40044G-page 175 ......................................... 59 CONFIG Register ................................... 58 Timer1 Mode Selection .................................................................. 93 Spurious Write Protection............. See Compare PWM Mode......................................................... 64 Interrupts .................... 57 Capture Mode.................. 66 Comparator Module............. 39 RB2/TX/CK Pin ...................... 57 CCP2CON Register CCP2M<3:2> Bits .............................. 92 Errata ................................................................................. 80 BRGH bit ..................................... 75 Brown-Out Reset (BOR) ....................... 59 Special Event Trigger ............................................................ 120 BTFSS Instruction ............ 58 CCP Pin Configuration ..................................................... 172 Dual-speed Oscillator Modes................. 122 DECFSZ Instruction.................. 15 CLRF Instruction........... 92 EECON2 register .. 64 Modified Comparator Output ............................................................................................................................................ 43 RB7/T1OSI Pin .. 58 Changing Between Capture Prescalers................................................................................................................................................. 91 Operation During Code Protection .................. 122 Comparator Block Diagrams I/O Operating Modes ......................................................... 120 BTFSC Instruction................................................................ 98 Configuration Bits ........... 99 Customer Change Notification Service.............................................. 57 CCPR1L Register ............................. 119 ANDWF Instruction .................................................................................... 173 D Data EEPROM Memory.. 82 USART Transmit.............................................................................................................. 75 BCF Instruction .......................................................................... 101 C C Compilers MPLAB C18 ............ 57 Compare Mode.......................................................... 121 CCP2X:CCP2Y Bits........ 93 Data Memory Organization.............. 58 CCPR1H:CCPR1L Registers.................................................. 65 Reference ........................ 101 USART Receive........ 100 F Fuses................................................................................................................................................................................................................................................................................................................................................... See Configuration Bits G General-Purpose Register File ......................................................................................................................... 39 RB3/CCP1 Pin ............... 95 Reading ........... 17 GOTO Instruction........................................................................................... 94 Code Protection ................................................................. 66 I/O Ports RB0/INT Pin ....... 121 Capture (CCP Module) .............................................. 57 CCP2 .......... 93 Writing to .......... 58 Prescaler............... 122 CLRWDT Instruction.......................................................................................................................................................................... 91 EECON1 Register ................................... 123 © 2009 Microchip Technology Inc............ 57 E EECON1 Register........................................................ 119 ANDLW Instruction ...................................................................... 119 Architectural Overview ........... 75 Baud Rate Formula . 59 CCPR1H:CCPR1L Registers .......................................... 173 Customer Support............. 64 Modified Comparator Output ...................... 67 Operation.......................... 93 Using ................................................................PIC16F627A/628A/648A INDEX A A/D Special Event Trigger (CCP)........................................................................................................................ 40 RB4/PGM Pin ............................................................................................................................................................................. 44 RC Oscillator Mode......................................... 59 Absolute Maximum Ratings ........................................................................................................ 11 Assembler MPASM Assembler......................................................... 135 ADDLW Instruction ..................... 57 CCP1M Bits ................................ 121 CLRW Instruction........... 41 RB5 Pin.......................................................................................................................................................... 120 Block Diagrams Comparator I/O Operating Modes .. 42 RB6/T1OSO/T1CKI Pin ........ 38 RB1/RX/DT Pin ...................

............... 122 DECF ........................................................................................... 122 DECFSZ.................................................................................................. 60 Set-Up for PWM Operation.......... 61 Period ......................................... 43 RB7/T1OSI Pin ......................................... 125 MOVWF Instruction ............ 125 MOVLW .................................... 123 INCF......................................................................................................................... 61 Example Frequencies/Resolutions ................................................................ 30 Instruction Flow/Pipelining .................................................................................................................... 42 RB6/T1OSO/T1CKI Pin .............................................. 60 Simplified PWM ...................................................................................... 126 RETLW ............................................................................................................... 126 RETFIE ................................ 95 Microchip Internet Web Site...... 28 PORTA ........................ Linker................. 38 RB1/RX/DT Pin ............................................................................. 17 PWM (CCP Module) .................................. 54..................................................................... 103 Power-up Timer (PWRT) ............................................................... 125 IORWF .......... 113 INCF Instruction ........................ 125 M Memory Organization Data EEPROM Memory..................... 120 BTFSS ........PIC16F627A/628A/648A I I/O Ports ............................................ 128 SLEEP ....... 73–89 RC7/RX/DT............................................................................................... 126 MPLAB ASM30 Assembler........ 41 RB5 Pin........................ 26 Internet Address .................. Flag Bits CCP1 Flag (CCP1IF Bit)..................................................................... 60 DS40044G-page 176 © 2009 Microchip Technology Inc........................ 33 PORTB.......................................................................................................... 125 MOVWF ........................ 39 RB3/CCP1 Pin ................................................. 119 ADDWF ..................................................................................................................................... 46 Successive Operations .... 25 OPTION_REG Register........... 33 PORTB .................................. 33 Bidirectional ................................................................................................................................................................. 91.................................... 173 Interrupt Sources Capture Complete (CCP)....................................................... 120 BSF ............................................. 122 COMF ....... 38 Programming Considerations ........ 27 Pin Functions RC6/TX/CK ............................................................................................................ Enable Bits CCP1 Enable (CCP1IE Bit) ..................................................................................... 126 OPTION ................................................................... 109 Interrupts.................................................................................. 134 MPLAB REAL ICE In-Circuit Emulator System .......... 38 ID Locations .............................. 46 Block Diagrams RB0/INT Pin ......................................... 123 GOTO ....................................... 132 N NOP Instruction ................................................................................................ 129 SWAPF ............................................................................................................................................................... 58 Compare Complete (CCP).......................... INDF and FSR Registers....... 39 RB2/TX/CK Pin .. 60 Block Diagram ..................... 126 OPTION Register............................................... 44 PORTA..................... 40 RB4/PGM Pin.................................................................. 93............................................................. 127 RETURN ................... Librarian ...................................................................... 33 TRISB ........... 130 Instruction Set Summary....................... 117 INT Interrupt ............................................................................................................ 121 CLRF..................................................................................................................................................................... 130 XORWF.................. 128 SUBLW ............................................................................... 129 XORLW ................................ 119 ANDWF ........................................................................................................................................ 131 MPLAB PM3 Device Programmer ........................... 15 Instruction Set ADDLW ......................................................................................................................................... 99 Oscillator Start-up Timer (OST) ..................... 60 Duty Cycle ...................................................... 46 TRISA .................................................................... 124 IORLW ............................... 104 Power-Down Mode (Sleep)............. 58 IORLW Instruction ........................................................................ 124 INCFSZ ....................... 120 BTFSC ......................................... 61 TMR2 to PR2 Match ......................................................................................................... 112 Power-On Reset (POR) ................................................................................... ......... 25 Oscillator Configurations.................................. 126 O OPTION Instruction ................................................................................................... 125 IORWF Instruction .............................................................................................. 173 Migrating from other PICmicro Devices ......................... 30 Stack............................................................................................................................................. 110 Power Control/Status Register (PCON)............................................................................................... 124 INCFSZ Instruction.................................................................. 125 MOVLW Instruction.............................. 127 RRF................................................................... 30 PCON Register ............................................................................................. 121 CALL .............. 124 In-Circuit Serial Programming™ .......................... 119 BCF .................... 59 TMR2 to PR2 Match (PWM) ..................................................................................................................................................................... 163 Packaging Information ...................................................................................................... 127 RLF ............. 110 INTCON Register .................................... 163 PCL and PCLATH............................................................................................................................................ 172 MOVF Instruction........................................... 133 MPLINK Object Linker/MPLIB Object Librarian ............................................................................................................ 58 Interrupts................ 126 NOP ..................................................... 73–89 PIR1 Register ..................... 103 PR2 Register ...................... 38 PORTB Interrupt ................................................ 122 CLRWDT................................................................ 129 TRIS ................ 60 Interrupts................................................................................ 114 Indirect Addressing..... 121 CLRW ...... 132 MPLAB Integrated Development Environment Software........................................... 29 PIE1 Register............................... 128 SUBWF ......................................................... 60 Program Memory Organization....................... 125 MOVF................................ 119 ANDLW ........................................... 60 CCPR1H:CCPR1L Registers.................. 103 P Package Marking Information ..................................................................................................................................................................................................................

................................. 50 T1CON Register . 55 TOUTPS1 bit ................................................... 83 USART Synchronous Reception ................................................................................................................... 28 Status. 55 T2CON Register .................................................................. 127 RRF Instruction .................................... 73 Asynchronous Receiver Setting Up Reception............ 101 Reader Response .............. 47 Timer1 Asynchronous Counter Mode ...................... 83 USART Asynchronous Master Transmission . 80 Asynchronous Transmitter............................................................................................................................................................................................................................................. 25 PCON (Power Control) ................ 53 Resetting Timer1 ........... 77................................ 128 Software Simulator (MPLAB SIM)............... 55 TOUTPS0 bit ............................. 50 TMR1ON bit......................................................................................................................................... 18. 54 PR2 register....................... 51 External Clock Input Timing....................... 79 Asynchronous Receiver.......................................................................................................................................................................................................... 53 Special Event Trigger (CCP) ...................... 50 T1CKPS1 bit ................................................................................................................................................................................................................... 84 Asynchronous Transmission ............... 55 TRIS Instruction ........................................................................................................................................................................................................................................................... 9 SLEEP Instruction .............. 52 Oscillator......................................... 97 Special Function Registers ............... 88 Synchronous Master Transmission ................................................ 78 Synchronous Master Mode..................................... 92 INTCON (Interrupt Control)............... 127 Revision History ..... 60 Timing Diagrams Timer0 ........ 47 Interrupt..... 55 T2CKPS1 bit ............................................ 82 Asynchronous Reception....................................................... 59 Synchronized Counter Mode ..................................................... DS40044G-page 177 ........................................... 129 U Universal Synchronous Asynchronous Receiver Transmitter (USART) .......................... 147 USART Asynchronous Receiver.................................................. 20 Status Register .......................... 50 T2CON Timer2 Control).......................... 61 Timer2 Module...................................................... 55 TOUTPS3 bit ....................... 61 Quick-Turnaround-Production (QTP) Devices .. 147 Timer1 .......... 26 Maps PIC16F627A ........... 19 PIC16F628A .......................................... 38 R RC Oscillator .... 27 PIR1 (Peripheral Interrupt Register 1) .............................................. 90 T T1CKPS0 bit ...PIC16F627A/628A/648A Q Q-Clock ... 18. 129 TRISA ..... 53 © 2009 Microchip Technology Inc..................................................................................................................... 174 Registers CCP1CON (CCP Operation)................ 53 Resetting Timer1 Registers ........................................................................ 80 USART Receive ...... 75 Block Diagrams Transmit.................................................................. 47 Prescaler............................................................... 110 TMR1CS bit ............ 24 T1CON Timer1 Control)............. 50 T2CKPS0 bit ............................................. 55 Reset...................................................................................................... 49 Timer0 Module ............................. 50 T1OSCEN bit .................................. 128 S Serial Communication Interface (SCI) Module.................... 54 TMR2 to PR2 Match Interrupt.... 126 RETLW Instruction .................................................... 171 RLF Instruction..................................... 54 TMR2 output ....................................................................................................................................................................................................... 86 Synchronous Master Reception .... 54 Prescaler ............................................... 89 USART Synchronous Transmission ................................................... 76.................................................................................................... 50 TMR2ON bit.................................. 82 BRGH bit . 54............................................................................ 89 Synchronous Slave Reception ............................................................................................... 80 USART Asynchronous Reception ......................................................... 55 Timer0 Block Diagrams Timer0/WDT ................................................. 54 Postscaler....................................................................................................... 53 Prescaler ................................................................................................................................................................... 98 EECON1 (EEPROM Control Register 1) ............................................................................................................. 101 RETFIE Instruction.... 48 Switching Prescaler Assignment............................. 24 SUBLW Instruction........................... 52 Timer2 Block Diagram ..................................................................................... 51........................................................ 57 CMCON (Comparator Configuration)..................................................................................................................................... See Compare Special Features of the CPU ................................ 9 External Clock Input ............................................... 129 SWAPF Instruction............................................................................................ See USART Serialized Quick-Turnaround-Production (SQTP) Devices ........................................................ 48 External Clock Input....................................................................... 51 TMR1H ............................................................................ 63 CONFIG (Configuration Word)....................................................................................................................................................................................................... 52 TMR1L........ 19 OPTION_REG (Option) .......................... 79 Baud Rate Generator (BRG) ...... 33 TRISB ....................................................... 128 SUBWF Instruction ........................ 52 Capacitor Selection...................................................... 51 Timer Mode ..................................................... 86 Synchronous Slave Mode.................................................... 85 USART Asynchronous Mode............................................... 87 Timing Diagrams and Specifications ................................................ 85 Asynchronous Receiver Mode Address Detect ... 101 RC Oscillator Mode Block Diagram...... 29 PIE1 (Peripheral Interrupt Enable 1)..................................... 133 Special Event Trigger..................................................................................... 127 RETURN Instruction ........................ 75 Sampling......................... 55 TOUTPS2 bit .................................................. 144 TMR0 Interrupt............................................................................................... 85 Block Diagram .........

...............................PIC16F627A/628A/648A Synchronous Slave Transmit ......... 130 XORWF Instruction ..................................... 130 DS40044G-page 178 © 2009 Microchip Technology Inc............... 111 WWW Address................................................................. 173 WWW......................................................................................................... 69 W Watchdog Timer (WDT) ....................................... 89 V Voltage Reference Configuration.................................. 69 Voltage Reference Module ...... 5 X XORLW Instruction ............................................... .......................... On-Line Support.......................

5V (Tape and Reel) I E P SO SS ML = -40°C to +85°C = -40°C to+125°C = = = = PDIP SOIC (Gull Wing..50 mm body) SSOP (5.PIC16F627A/628A/648A PRODUCT IDENTIFICATION SYSTEM To order or obtain information. 20 MHz. PIC16LF627A .0V to 5. PART NO. refer to the factory or the listed sales office. PDIP package.g.0V to 5.5V (Tape and Reel) PIC16LF627A/628A/648A:VDD range 2. on pricing or delivery. Device: PIC16F627A/628A/648A:Standard VDD range 3.. normal VDD limits. 7.5V PIC16F627A/628A/648AT:VDD range 3.E/P 301 = Extended Temp. 20 MHz.0V to 5. SOIC package.I/SO = Industrial Temp. QTP pattern #301.30 mm QFN (28 Lead) b) Temperature Range: Package: © 2009 Microchip Technology Inc.5V PIC16LF627A/628A/648AT:VDD range 2..0V to 5. DS40044G-page 179 . Device X Temperature Range /XX Package XXX Pattern Examples: a) PIC16F627A . e. extended VDD limits.

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