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Published by Ashutosh Yadav

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Published by: Ashutosh Yadav on May 02, 2012
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 VHDL codes for a 4 bit parallel to serial converter

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity piso is port(x: in std_logic_vector(3 downto 0); load,res,clk: in std_logic; y: out std_logic); end piso; architecture behavior of piso is begin process (clk) variable q: std_logic_vector(3 downto 0); begin if clk='1'then if res='0' then q:="0000"; elsif load='1' then q:=x; else q:='0' & q(3 downto 1); end if; else null; end if; y<=q(0); end process; end behavior;

 Simulation Result .

clk) variable q:std_logic_vector(3 downto 0). sipo_out<=q. begin if res_sipo='0'then q:="0000". use IEEE. VHDL codes for a 4 bit serial to parallel converter library IEEE. res_sipo. else null. elsif (clk'event and clk='0') then if en_sipo='1' then q := in_bit & q (3 downto 1). end if. . end sipo. end behavior.STD_LOGIC_UNSIGNED. use IEEE. in_bit: in std_logic. end if.STD_LOGIC_ARITH. end process. en_sipo. use IEEE. sipo_out : out std_logic_vector (3 downto 0)).STD_LOGIC_1164. architecture behavior of sipo is begin process (res_sipo.ALL.ALL. entity sipo is port(clk.ALL. else null.

.

q<='0'. begin p1: process (clk. use IEEE.nxt_state: integer range 0 to 3. else nxt_state<=3. q<='0'. signal q: std_logic. p2: process(pr_state. end design. end process p1. end if. VHDL codes for a 1010 sequence detector library IEEE. architecture design of seq_1010 is signal pr_state. end seq_1010. q<='0'.res:in std_logic. q<='1'. when 3 => if x='0' then nxt_state<=2. end if. else nxt_state<=1. end if. y<='0'. q<='0'.STD_LOGIC_UNSIGNED. when 2 => if x='0' then nxt_state<=0.res) begin if res='0' then pr_state<=0. entity seq_1010 is port(x. end if. end case. y: out std_logic). else nxt_state<=1. use IEEE.x) begin case pr_state is when 0 => if x='0' then nxt_state<=0. use IEEE.clk. .STD_LOGIC_1164. y<=q. when 1 => if x='0' then nxt_state<=2. else nxt_state<=1.ALL.ALL. end process p2. end if.ALL. elsif clk'event and clk='1' then pr_state<=nxt_state. else null.STD_LOGIC_ARITH.

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use IEEE.b.ALL.ALL.c1.all. use IEEE. architecture design of alu is signal c1.b. a. use IEEE.mux port map(s(2).b:in std_logic_vector(3 downto 0). VHDL codes for a 2 bit ALU containing 4 arithmetic & 4 logic operations. x2: entity work.  VHDL codes for an arithmetic Unit library IEEE.c1).ALL. entity alu is port ( s:in std_logic_vector(2 downto 0). . begin x0: entity work. c: out std_logic_vector(3 downto 0) ). library IEEE. end alu. use IEEE. use IEEE. x1: entity work. entity arithmetic_unit is port ( s:in std_logic_vector(1 downto 0).logical_unit port map(s(1 downto 0). a.c). use work.STD_LOGIC_ARITH.ALL.c2.STD_LOGIC_UNSIGNED.ALL.c2: std_logic_vector(3 downto 0).a.arithmetic_unit port map(s(1 downto 0).b:in std_logic_vector(3 downto 0).STD_LOGIC_ARITH.ALL.c2). end design.STD_LOGIC_UNSIGNED.STD_LOGIC_1164.a. c: out std_logic_vector(3 downto 0) ). use IEEE.STD_LOGIC_1164.

ALL.s) begin case s is when "00" => c<=a+b. -. end process.ALL. -.decrement a when others => c<="0000". .addition when "01" => c<=a+"0001".increment a when "10" => c<=b+"0001".end arithmetic_unit. -.b.b:in std_logic_vector(3 downto 0). architecture design of arithmetic_unit is begin process (a.s) begin case s is when "00" => c<= not a. end case. end design.STD_LOGIC_UNSIGNED. -.complement a when "01" => c<= a and b. architecture design of logical_unit is begin process (a. use IEEE. use IEEE.  VHDL codes for a logical Unit library IEEE. use IEEE.b.STD_LOGIC_ARITH.and operation when "10" => c<= a or b.STD_LOGIC_1164. a. c: out std_logic_vector(3 downto 0) ).increment b when "11" => c<=a-"0001". end logical_unit.ALL. -.xor operation when others => c<="0000". entity logical_unit is port ( s:in std_logic_vector(1 downto 0). -.or operation when "11" => c<= a xor b. -. -.

end process. end design. .end case.

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