You are on page 1of 20

ACKNOWLEDGEMENTS: I would like to give gratitude to my parents, Mr. & Mrs. Mtunzi firstly for supporting me to make this project a success, secondly my colleagues, Tatenda Muringa, Marvelous Tshuma, Leon Murefu & Ambrose Moyana for working with me during my design. Last but not least my supervisor Mrs. S.A BEBOVA for her guidance and all those who instilled the importance of design to make this world a better place.

1|Page

ABSTRACT: Contents of this report show the algorithm on how to design a digital clock using a pulse generator with asynchronous counters and binary to seven segment decoders. The clock counts up to sixty seconds (1 minute), simulations displayed in the experimental results were done using circuit maker.

2|Page

. Common anode seven segment display……. P a g e | 14 5.. ………...P a g e |7 7490 IC Counter ………………………………P a g e |8 7400 Quad 2 input NAND gate………………....P a g e |12 b) EXPERIMENT 2:Breadboard circuit setup results………. REFERENCES……………………………………….. iii.... P a g e | 11 3... EXPERIMENTAL METHOD & RESULTS a) EXPERIMENT 1: Output waveform……………………. iv.TABLE OF CONTENTS: 1.. THEORY Digital clock block diagram…………………………….P a g e | 6 7447 IC Decoder ……………………………....P a g e | 16 7. P a g e |15 6.P a g e |9 b) DESIGNING THE PULSE GENERATOR…………….....P a g e |5 a) DESCRIPTION OF COMPONENTS i. ii. DISCUSSION………………………………………………….P a g e |13 4. INTRODUCTION………………………………………………P a g e | 4 2......P a g e |10 c) PROGRAMMING THE 7490………………………….... APPENDIX……………………………………………………….. CONCLUSION………………………………………. P a g e |17 3|Page . ……….

INTRODUCTION: This report helps you to understand how to apply the functionality of asynchronous counters and their implementation together with decoders in designing a digital clock. and this was a way of showing my step by step process that I took to come up with the whole digital clock circuit. 4|Page . It gets you to familiarize with circuits that can be used to produce square wave pulses with certain frequencies and voltages.

7490 asynchronous counters .• • THEORY: Required components: I. it’s the heartbeat of the clock.470k resistor. II.Breadboard Figure 1.10uF capacitor.0 shows the general block diagram of the digital clock counting 60 seconds. Seven segment displays -A way to display time V. 7447 IC decoders -these take the binary outputs from the 7490 counters to the seven segment displays VI.0(obtained from www.howstuff works.com) 5|Page . -it ticks at some known and accurate rate. seconds) IV.a way to gear down time base to extract different components of time (hours. An accurate time base (pulse generator). minutes. 7400 Quad two input nand gate IC. variable resistor.LEDs. Fig 1. III.connecting wires. A source of power to run the clock.

2 (7 segment display circuit connection with a 7447 decoder) 6|Page . 1.1 Fig.• DESCRIPTION OF COMPONENTS: a) Common anode seven segment display Figure 1.

1.b) 7447 Decoder pin layout Fig. pin 5 Description -BCD inputs -Ripple blanking input(active low signal) -display test(active low).1 7|Page .pin -also known as lamp test 3 input -blank output(pin 4) -ripple blanking output or blanking input -segment outputs -pin 9 to 15 Table 0.3 Pin names -Input A and D(pin 7 & 6 respectively) -Blank input(active low).

1.4 Output Count 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 0 0 0 0 0 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 QB QA 0 1 0 1 0 1 0 1 0 1 Table 0.c) 7490 Counter Fig.2 Function table of the counter 8|Page .

Fig 1.45 9|Page .

C with this RC network being controlled by the output of the first NAND gate.2R1.2R1C 1=1/2. Voltage across R1C is now reversed and the capacitor begins to discharge through the resistor until it reaches the lower threshold level of the first NAND gate causing the two gates to change state once again. the NAND gate changes state causing the second NAND gate to follow it.5 a) Functionality: The RC network is formed resistor R1 and the capacitor. The output from this R1C network is fed back to the input of the first NAND gate via the resistor. Frequency of Oscillation =1/2. b) Calculations i. R2 and when the charging voltage across the capacitor reaches the upper threshold level of the first NAND gate. thereby change state and producing a change in the output level. 10 | P a g e . Fig.2*10-6F R1=47KΩ R2=10R1 R2=470KΩ ii.*8.• DESIGNING THE PULSE GENERATOR: The square waveform generator that was implemented consists of two NAND gates and an RC network. 1.

2) Connect pin 12 to pin 1and ground pins 2. 4) Use pin 11 to connect next stage. 5) Use pin 8 to connect to next stage. To create a mode 6 counter: Using the same diagram as above 1) Connect pin 5 to +5V and pin 10 to ground to power the IC. 3) You run input clock signal (from pulse generator) in pin 14.PROGRAMMING THE 7490: To create a mode 10 counter: Using fig 1. 3) Connect pin 2 to 9 and pin 3 to pin 8. 4) Run input clock signal into pin 14.4 follow the steps bellow 1) Connect pins 5 to +5V and pin 10 to ground to power the chip. 3. 11 | P a g e . Now connecting the counters to the 7447 decoder you simply have to use the pin layouts shown in the previous section (component description) also same applies to the 7447 to seven segment display connections. 2) Connect pin 12 to 1 and ground pins 6 and 7. and 7. 6.

• EXPERIMENTAL METHOD AND RESULTS The pulse generator circuit was tested first using circuit maker and simulations were very successful using the calculated values. a-b measures the frequency which is shown as 1. The results/output waveforms of the pulse generator that I obtained were as shown below. 5V as required in my testing. Output waveform Figure 1.e.6(experiment 1) c-d shows the pick voltage i.169Hz 12 | P a g e .

7 (Experiment 2 results) 13 | P a g e . 1.Experiment 2: The next step I had to take after being satisfied with the pulse generator frequency output and testing was assembling the whole circuit on breadboard following the steps mentioned in previous chapters (programming the 7490) altogether with the help of the pin layouts (description of equipment section). Fig.7 shows the whole of the digital clock assembled on breadboard Figure 1.

so it could count up to 60 seconds. but with time the circuit running it could start skipping values.• DISCUSSION: During the testing of the pulse generator in experiment 1 it was difficult to obtain a stable 1Hz signal with exact values of resistance. On testing the whole digital clock it could count from 0 to 9 for the mode 10 counter and 0 to 5 for the mode 6. to resolve this I had to connect some conductor to the variable resistor to stabilize the count.Possible errors that i came across with were exceeding the required calculated resistor value in adjusting it during signal stabilization and short circuiting the connecting wires. Short circuiting the wires was the most possible error! 14 | P a g e . so with the help of a variable resistor within the RC network I could control the signal’s frequency which finally made the whole testing successful .

The objective of getting to know the applications of asynchronous counters in the real world devices that are still being used was met and getting to know how much effect capacitors have on clock signals. 15 | P a g e .• CONLUSION: The digital clock designed could properly count sixty seconds but I could not resolve the problem of it leading the standard time with six seconds.

16 | P a g e .devices and applications. John Wiley & sons.Maini.• REFERENCES: 1) Antil K.com 3) http://www.com 5) Landon Johnson “Digital electronics” electronics technology (counter power point notes).datacatalogue.com 4) http://www.”Digital Electronics” Principles .electronics-tutorials. 2007 page 411 2) http://www.howstuffworks.

• APPENDIX: 17 | P a g e .

18 | P a g e .

19 | P a g e .

20 | P a g e .