QUESTION BANK Subject: Digital Logic Circuits PART – B UNIT – I 1.
Using K-map simplify the expression Y (A, B, C, D) = m1+m3+m5+ m7+m8+m9+ m0+m2+m10+m12+m13. Indicate the prime implicants, essential and non-essential prime implicants. Realize the logic circuit using AND-OR-INVERT gates and also by using NAND gates. (16) 2. Obtain the simplified function for the Boolean function Y (A, B, C, D) = m1+m3+m5+ m7 +m8+m9+ m0+m2+m10+m12+m13 using Quine McClusky method. Obtain the NAND and NOR implementation of the simplified expression. (16) 3. Obtain the minimum SOP using Quine McClusky method and verify using K- map F= m0 + m2+m4+m8+m9+m10+m11+m12+m13. (16) 4. Determine the prime implicants of the following function and verify using K-map F(A,B,C,D) = Σ(3,4,5,7,9,13,14,15). (16) 5. Simplify using K-map to obtain a minimum POS expression for the function F = (A’ + B’ + C + D) (A + B’+ C + D) (A + B + C + D’) (A + B + C’ + D’) (A’+ B + C + D’)(A + B + C’ + D). (8) 6. Write short notes on i) alphanumeric codes and ii) Error detection and correction methods (6) 7. i. Simplify F (A,B,C,D) = Σm ( 1,3,5,8,9,11,15) + Σd (2,13).If don’t care conditions are not taken into care what will be the simplified Boolean function? Write your comments on it. Implement both circuits using logic gates. (12) ii. Add 26 and 39 using Excess-3 code. (4) 8. Simplify using five variable mapping F =(8,9,10,11,13,15,16,18,21,24,25,26,27,30,31) (16) 9. State and prove De - Morgan’s theorems using two variables. (6) 10. Realize the functions of NOT, AND, OR and NAND gates only with NOR gates. (8) 11. i. Convert the decimal 65 to BCD, Excess-3 and Gray code (4) ii. Encode data bits 1001 into a seven bit even parity Hamming code. (4) 12. Simplify the following Boolean function in SOP and POS form using K-map F ( A,B,C,D) = Σm( 3,4,9,13,14,15) + Σd ( 2,5,10,12) (8) 13. Simplify the following function using K – map and tabular methods. Compare the methods. F ( A,B,C,D) = Σm(4,5,6,7,8) + Σd (11,12,13,14,15).Implement the result using NAND gates. (16) 14. Obtain the minimum SOP using Quine Mc Clusky’s method for the function Σm(0,1,2,8,9,15,17,21,24,25,27,31) (7) 15. What are codes? Explain the different codes with examples. (16) 16. Prove the following Boolean identities i) x + xyz + yzx’ + wx + w’x + x’y = x + y ii) (X1 + X2) (X1’ X3’ + X3) (X2’ + X1X3)’ = X1’X2 (6) 17. The state of 12 cell register is 010110010111.What is its contents if it represents a) Three decimal digits in BCD b) Three decimal digits in Excess- 3 code. c) Three decimal digits in 2421 code d) Three decimal digits in 84-2-1 code. (8) 18. Implement the following expression with 2 - input NAND – NOT gates. Assume that only true values of the inputs are available = (AB + A’B’) (CD’ + C’D).Also 1 Subject code: EE 2255
(16) 33. Compare ones complement and twos complement representation of signed binary numbers. B.z) = Σm(1.Design a two – bit magnitude Comparator 41.10.30) (16) 20.x.D) = Σm(0.15) using three input NOR gates.C. 188.8.131.52.9. d) = Σm(0.22.14. Find the MSP form of F (w.30) (16) 28.5. 8 . c.7 ii.B.75 to binary.15. 2 (8) (10) (10) (8)
.6. (2) 21. Simplify the following switching function F(A. if so what are they? (8) 23.y. Implement the simplified function using gates.10.Design a 4 bit BCD to Excess. MSB is 1 or any of the other bits are a 0. (16) 32. Explain the term Prime Implicants.D. (16) 30.7. . (16) 19. Obtain the minimum SOP using Quine MC Clusky’s method and using K-map. Simplify the function F(w. (16) 29.z) = Σm(1.8. corrects the error using Hamming code.184.108.40.206.3. D) = (A’B + C) D + EF (8) 25.22.6. (8) 26. (-27) + (+61) and (-27) + (-61).3.11. Determine the Prime Implicants and Essential Prime Implicants of the function F(w. i.25.x.E) = Σm(1.3 code converter. Given F = A’BE + BCDE + BC’D’E+ A’B’DE’ + B’C’DE’. Perform the following: i) (-105)10 + (-120)10 using ones and twos complement. Obtain a four level NAND network for F (A. The circuit produces a one if and only if all of the following conditions hold. x.14.19. Comment on the result. (16) 35.12. BE +B’DE’ is the simplified version of the expression.B.14. b. Perform the following using 12 bit two’s complement arithmetic i.15) using tabulation method.x.5. Convert the decimal number 342. Draw and explain the working of 4 bit adder – subtractor circuit. 220.127.116.11. Are there any don’t care conditions.11.9. Implement the simplified function using gates.15) using tabulation method.15) (16) 18.104.22.168. for 1100010.15) using tabulation method.12 – 14) using the Quine Mc Clusky method.11. Write notes on computer aided minimization procedure.13. Reduce the following using tabulation method. Then convert to NAND – NOT gates. z) = Σm(1 – 3.B.19.C.3.8+7 (6) 22.17. y.12. (8) 24. (6) ii) Generate the parity bits for 8421 BCD code in an odd parity system. Realise F(A.y.A)=Σm(3. ii) Divide 100000110.The inputs to a circuit are the four bits of the binary number D3 D2 D1 D0. iv) Determine whether single error has occurred and if so. C. octal and hexa decimal.Design a 4 bit Binary to gray code converter.8. Simplify the five variable switching function F(E. 40.C.6.10. Using Quine Mc Clusky method find all the prime implicants and the minimum SOP for the function F ( a. (16) 31.24.4.z) = Σm(2. 5-10. (6) 37.11 using ones complement.1 by 101 and perform 100000 – 0.use a multiple level implementations to reduce the number of gates. (10) 27. i) Perform the following arithmetic using two’s complement (+27) + (-61). Simplify the function F(w. F = m2 + m3 + m4 + m6 + m7 +m9 + m11 + m22.214.171.124.4. -8 -7 iii.20.D.y. Hint – Use a two –level AND –OR implementation plus NOT gates on the inputs as needed. iii) (34)10 + (19)10 using excess – 3 code. F = m0+ m2 + m4 + m8 + m9 +m10 + m11 + m12 + m13 (16) 34.12.4.
a MUX or a DEMUX? a) Has more inputs than outputs. 10. 2. (8) 60. (16) 53. Explain with truth table and gate level circuits diagram for a full adder. B. 12. i) Design and implement a full adder circuit using logic gates and also by using half adders. (8) 3
. Implement the following multiple output combinational logic circuit using a 4 – 16 line decoder.8. Any of the 4 bits are 0 Obtain a minimal expression for the output. What is a decoder? How is it different from encoder? (6) ii.Explain how a 4 to 16 line decoder can be built using 2 to 4 line decoder. (8) 47. Implement a 3 to 8 line decoder. 8. 8. 7.4. Implement the logic function Y(A.Explain the working of carry look ahead generator (10) 44. 15) (10) 49. b. 7) using 74151A and 74153 (8) ii. y. 11.7. 3. 7.1. 6. How can you convert a decoder into a de-multiplexer? (4) 51.x. (10) 43. 9. 11) F3 = Σm (10. d) Only one of its outputs can be active at one time. Which of the following statements refer to a decoder. B. 11. 15) using 4:1 MUX (16) 58. 2. 12. C. 13) (8) ii. 8.Using 8 to 1 multiplexer. i. 4. realize the Boolean function T = f (w. x. (4) ii.The output is 0 otherwise. (8) 45. 4.NAND logic (6) ii) Design a four bit gray to binary code converter. Implement the function Y (A.z) = Σ (1. e) Can be used to route an input signal to one of several possible outputs. (8) 54.12.y. 12. 5. D2 is a 1 or any other bits are a 0. 10. 9. (6) 61. 2. 13) using 4:1MUX. 7. 3. (8) 46. C) = A (B + C) by using only NAND gates.3 code converter using Binary Parallel Adder (BPA). i) Construct a BCD to Excess -3 code converter using full adders (8) ii) Design an 8421 to gray code converter. B. 8.5. State the advantages of complex MSI devices over SSI gates. 9. f) Can be used to generate arbitrary logic functions. 4. Design a 4 bit BCD to Excess. Realize the function given in (i) using Decoder and external gates. (12) 48. 7. 2. 1. d) = Σ ( 0. Using 8 to 1 multiplexer. iii. 14) F4 = Σm (2. 0.Design and explain the working of a 4 x 1 MUX. Using a truth table. (8) 59. What is the drawback in BPA and how can it be rectified. z) = Σm (0. (6) 55. A majority gate is a digital circuit whose output is equal to 1 if majority of its inputs are 1’s. i) Design a Half subtractor using NAND. 8. D) = Σm (1. a) Decoder b) Multiplexer (12) ii. F1 = Σm (1. 13. 12. (8) 42. (10) 57. 2. 4. 4.C) = Σm ( 1.13) (16) 50. 5) using the DEMUX 74156. encoder. Simplify the function and implement it with logic gates. realize the following Boolean function T = f (w. b) Can be used in parallel to serial conversion. i. Implement full adder circuit using. 1. B. 9. c) Produces a binary code at its output. 9.B. Implement the function Y (A. C.9. find the Boolean function implemented by a 3-input majority gate. C) = Σm (1. Implement the following function with a Multiplexer f (a. i.ii. i. (8) 52.2. 8) (16) 56. D) = Σm (1. 13) F2 = Σm (2. Design a logic circuit to simulate the function f (A. Implement the switching function F (A. i. 3. c. 4. 5.
5. 1. 4. 7…. Design a synchronous counter using JK flip-flop to count the following sequence 7. Design a MOD – 10 synchronous counter using JK flip-flops. 14) using a multiplexer and a decoder. 001. Design a BCD to seven segment code conversion and representing the system 63. 1. and one output S. (8) Output Present Next State state x=0 x=1 x=0 x=1 a F b 0 0 b D c 0 0 c F e 0 0 d G a 1 0 e D c 0 0 f F b 1 1 g G h 0 1 h G a 1 0 ii. Compare Moore and Mealy circuits.OR of present states of C and D. inputs come serially. (12)
8. i. i. Starting from state a. 110. (16) 4. determine the output sequence for the given and reduced state stable. Construct a timing diagram and determine the duty cycle of the output of the most significant stage. as shown below. Reduce the number of states in the following state table and tabulate the reduced state table. (16) 2. Show that the characteristic equation of Q’ ( t+1) of JK flip flop is Q’ (t+1) = J’Q’ + KQ (4) ii. (16) 10. Using SR flip-flops. C. 101. design a synchronous counter which counts in the sequence 000. (6) ii. The next states of B. For a four bit even parity bit generator. (16) 6. (8) 9. 3. Design a sequential circuit with four flip-flops ABCD. (12) 3. Explain the working of a master – slave JK flip flop. 0. B. (16) 7. State its advantages. 10. Design a mod – 5 synchronous counter using JK flip – flops with separate logic circuitry for each J and K input. 13. 000. Design a synchronous decade counter using D flip flop. Write the excitation table and state table. Draw and explain the block diagram of Mealy circuit. UNIT – II
1. 8. two inputs x and y. 6. Derive the state table and state diagram of the sequential circuit. i. (4) ii. The four bits of the input sequence are to be examined by the circuit and circuit produces a parity bit 4
.62. A sequential circuit has one flip-flop Q. The next state of A is equal to the EX. and the input sequence 01110010011. 5. Design the following function F = Σm (0. i. (16) 5. C respectively. It consists of a full adder circuit connected to a D flip-flop. and D are equal to the present states of A. 111. 010. 3.
The circuit should get ready for receiving another four bits after producing a parity bit for the last sequence. Design a mod. Draw a four state switch tail ring counter. (10) 11. (16) 17. What is the modification to be used to prevent lock out? (16) 18. Draw the logic diagram of the circuit ii. (16)
21. A sequential circuit has four flip-flops ABCD and an input x is describe the following State equations. A (t + 1) = (CD’ + C’D) x + (CD + C’D’) x’ B (t + 1) = A C (t + 1) = B D (t + 1) = C a. What is the use of State reduction? Reduce the state diagram. Design the clocked sequential circuit using JK flip-flops whose state diagram is given below. Write notes on state minimization. Derive the state table Iii. 1… using JK flip-flops. Design a BCD Up / Down counter using S R flip-flops. 0.Derive the state diagram (16) 13. 1. (10) 16.
. (6) 15. Draw the state diagram and write down the state transition table. Obtain the sequence of states when x = 1 starting from ABCD = 0001 b. A sequential circuit with 2 D flip-flops A and B and input X and output Y is specified by the following next state and output equations.7 counter using JK flip-flops.which is to be added in the original sequence. Design a Mod-14 up-down counter using T flip-flops. 3. Design an asynchronous decade counter using JK flip-flops. A (t + 1) = AX + BX B (t + 1) = A’X Y = (A + B) X’ i. (8) 20. Show the count sequence. Design a synchronous counter with states 0. (16) 14. 2. Obtain the sequence of states when x = 0 starting from ABCD = 0000 (16) 12. (16) 19.
Determine its state table. then it is reversible but that the converse is not always true. Explain the working of JK flip. (16) 23. What does the circuit do? (16)
25. Design a 4 – bit up / down counter using JK flip – flops and Explain its working with timing diagrams. state diagram. (16) 28. Distinguish between synchronous and asynchronous sequential circuits. What is race around condition? How is it overcome? Explain these concepts with relevant timing diagrams. Design a four state down counter using type T design procedures. (10) 27. flips flop input and output equations.22. For the given Moore model sequential circuit. find the state table. Design a 4 – bit synchronous 8421 decade counter with ripple carry. (16) 29. (6) 26. Develop the state diagram and primitive flow table for a logic system that has two inputs S and R and a single output Q. Explain the meaning of Mealy and Moore machines. The device is to be an edge triggered SR flip6
. Consider the following synchronous sequential circuit. Design 4 bit synchronous counter using X-OR gate as well as JK Flip-flop to count from 0 to 15. Show that if a sequential machine is strongly connected.flop. (16) 30. 31. (16)
UNIT – III 1. (6) 24.
K. (16) 3. (16) 4. An incorrect input code pattern is to generate a second output. Design an asynchronous binary toggle circuit that changes state with each rising edge of clock input. when x2= 1 and x1 changes from 0 to 1 the output z1 z2 = 10 otherwise output does not change. (5) (ii) Obtain a flow table for the circuit.where each input is a four bit code. iii) critical race.Analyze the Boolean expression. (5) 6. (16) 8. ii) Cycles.flop but without a clock. Assume the initial output as zero. (16) 9. (6) (ii) Derive the transition table and output map. (5) 5. The first change in X2 that occurs while X1 is a 1 will cause a Z to be a 1. If the string of four bit codes is correctly received. Construct a state diagram and flow table. when x1= 1 and x2 changes from 0 to 1 the output z1 z2 = 01. Define the following: i) asynchronous sequential circuits.Unstable state. Static input values are not to have any effect in changing the Q output (16) 2. An asynchronous sequential circuit is described by the excitation and output functions Y = x1x2' +(x1+x2' ) y and Z =y (i) Draw the logic diagram of the circuit with a NOR SR latch. (6) (ii)Derive the transition table and output map (5) (iii)Obtain a two-state flow table. Z is to remain a 1 until X1 returns to 0. An asynchronous sequential circuit has two internal states and one output. Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output Z.Cycles. The device changes state on the rising edges of the two inputs. (8) Stable state. When x1 x2 = 00 output z1 z2 = 00. The output is to remain a 0 as long as X1 is a 0.Map. The excitation and output functions describing the circuit are Y1=x1 +x1y2 ' +x2y1 Y2=x2 +x1y1' y2+x1y1 Z= x2+y1 (i) Draw the logic diagram of the circuit. Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x1 and x2 and two outputs z1 and z2 that satisfies the following conditions. transition and state table and primitive flow table of the following asynchronous sequential circuits.then an output is generated. Construct the state diagram of a Mealey Pattern detector that can detect a serial string of 4 inputs.critical race (8) 7. Determine the output equations. iv) non. (16)
.The second output is to be asserted only after receiving the sequence of four bit codes.Race 10. Write notes on the following giving one example for each.
Explain the concept and implementation of ECL logic family. (i) Using ROM. (16) 11. Illustrate the ROM and PLA design for the following functions W(A. FPGA iii.15) X(A. Draw a PLA circuit to implement the logic functions A’BC + AB’C + AC’ and A’B’C’ + BC (6) 8. (8) ii) Draw the circuit of CMOS NOR gate and explain its operation. 15) (16) 15. B. Name and explain the characteristics of TTL logic family. (8) 21.B. D) = Σm (1.C. (8) 5.C. 7).11. Discuss the concept of working and applications of the following memories: ROM. B. (10) 7. Draw and explain the circuit diagram of an ECL OR / NOR gate.7. (8) 22. 5. 7). ECL and CMOS digital logic families. (8) 14.11. ii. State the restrictions on the pulse width in a pulse mode asynchronous sequential machine. tri-state gates. (12) 17. Compare various digital logic families based on any five suitable parameters (10) 9. Write short notes on TTL. Discuss the working of the following programmable logic devices: (16) i.Explain the characteristics and implementation of the following digital logic families. Discuss about the TTL parameters. Fan-in. (8) 4.9. Define the terms Fan-out. (8) 3. Y3 = A’BC’D + A’BCD’ + A’BCD + ABC’D Y2 = A’BCD’ + A”BCD + ABCD Y1 = A’BC’ + A’BC + AB’C + ABC’ Y0 = ABCD (16) 18. i. How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine? (12) 12. (i) Explain the operation of TTL NAND gate with a neat circuit diagram. Mention any two points about the advantages of CMOS over the other digital logic families. Draw the circuits of two input NAND and two input NOR gates using CMOS. Explain the working of 3 input totem pole TTL NAND gate. 6. F2 (A. 4. Draw the internal circuits of TTL inverter and AND gate. ECL (16) 24.4. 2.15) Y (A. EPROM. Write notes on ROM and its types.7. Explain EPROM and PLA. (6) 20. (8) 16. 5. Write short notes on memory based design (8) 8
.B.10. Draw the circuit diagram and explain the working of TTL inverter with tristate output (8) 2. Draw the TTL inverter circuit. CMOS. C. (8) (ii) A combinational circuit is defined by the functions F1 (A. C) = ∑m (0. (8) 12. PROM ii. (6) 13. (16) 10.D) = Σm(3. Implement the circuit using PLA. design a combinational circuit which accepts 3 bit number and generates an output binary number equivalent to the square of input number. Draw a neat sketch showing the implementation of Z1 = ab’d’e + a’b’c’d’e’ + bc + de Z2 = a’c’e Z3 = bc + de + c’d’e’ + bd and Z4 = a’c’e + ce using a 5 x 8 x 4 PLA. Generate the following Boolean functions with a PAL with 4 inputs and 4 outputs. C) =∑m (3.D) = Σm(3. 11.14. 7.5. PLD 6. (10) 19. (4) UNIT – IV 1. B.8. PLA (16) 23.
Write HDL behavioral description of JK flipflop using if. (16) 9. G<=A and B. using logic equations. Write a VHDL code for a T flip-flop with a active-low asynchronous clear. State two absorption properties of Boolean algebra. always @ (Posedge CLK) begin E<= A&B. R1R2 R3R3-1 If(T=1) then (R0R1) else if (T2=1) then (R0R2) (16)
2.CLK). 4. Assume that the full subtractor has a 5-ns delay. Write HDL program for full adder and 4 bit comparator (16) 10. input A.C. Write a VHDL code for a full subtractor.B. Write a VHDL code for a serial adder. 2. 3. Why NAND and NOR gates are called as universal gates? 5. What are the different HDL descriptions of a design problem. Draw the circuit represented by the following CHDL statements: (16) F<=E and I. (16) 5. Write a VHDL module that implements a full adder using an array of bit-vectors to represent the truth table. module seqcrt (A. end end module (8) UNIT –I PART – A 1. Distinguish between completely specified function and incompletely specified function.Q. Show a BCD to Gray code converter can be designed using a 16 words X 4 bits ROM. (a) (b) (c)
UNIT V Explain in words the operations specified by the following register transfer notation: R2 R2 +1. 8. Q <= E / C. Show how bubbled AND gate works as NOR gate. (16) 4. 7. Simplify the Boolean function F = (A + (BC)’)’ 9
. State De-Morgan’s laws. (16) 6.CLK. (8) 11.C. I<=G or H. H<=not C and D.E. (16) 7.else statement based on value of present state.B. output Q: reg Q.1. (16) 3. Draw the logic diagram for the following module. Why digital circuits are more frequently constructed with NAND and NOR gates than with AND and OR gates? 6.
What is a multiplexer? Give its applications. Give the circuit of a half adder – subtractor. Implement a NAND gate using 4:1 Multiplexer. Draw the logic diagram for the minimized function. 3. 31. Find the decimal equivalent of (123)9. 35. 21. 23.c) = Σm (2. 39. What is a demultiplexer? Give its applications. 28. Name two canonical forms of Boolean algebra. Design a half subtractor using 2 to 4 decoder. 10.b. Show that the NOR connective is not associative. List out the limitations of SR flip-flop. What is data selector? 42. Plot the expression in K-map F (w. 4) 17. List out the differences between half adder and full adder. What will be the maximum number of outputs for a decoder with a 6 bit data word? 32. 16. Mention the use of decoders. 40. 34. 6) + d (2. 25.6. 38. Express the function f(B. 6.7). 22. 5. 7) using 8 to 1 multiplexer. 18.z) = x + yz as a sum of minterms. Define glitch. 1. 11. Realize the function F (A. 4.3. Draw a 1 to 2 demultiplexer and 2 to1 multiplexer. List out the differences between decoder and encoder. 3. 15. x. Draw the logic diagram of three – bit ring counter. F = C’+ A’D’ + AB’D’. How many inputs and gates are required for the expression W = AB’D + ACD’ + EF 12. Mention the differences between DMUX and MUX. Minimize the expression XY + X’YZ’ + YZ using Boolean theorem.8. find B. Implement half adder circuit using logic gates. 5.A) = A in terms of minterms. 20. Express the function f(x. 30. Write the characteristic equation of JK and D flip-flop. 4. y) = Σ (0. What is a prime implicant? 14. 29. 1. Implement half subtractor circuit using logic gates. Convert an SR flip-flop to D flip-flop. 33. 2. 10
. Simplify: x + x’y 19. 7. For the given function write the Boolean expression in product of maxterms form f( a. 9. Write the excitation tables of JK and D flip-flops.y.What is two state operation? 26. 36. 37. B) = A’B + AB’ using NAND gates only. 13.5. UNIT –II PART – A 1. 41.Write down the truth table of a full adder. If A and B are Boolean variables and if A= 1 and (A+B)’ = 0. 5. Draw the block diagram of SR Flip flop and give its truth table. Implement the function f = Σm (0.What is the value of b if √ 41b = 5? 27.State two significant features of tabular method of minimization of Boolean functions. Minimize the expression using Boolean theorems F= x’y’ + x’yz + xz + xyz’. Show the Karnaugh map with the encircled groups for the Boolean function. What happens when all the gates in a two level AND – OR gate network are replaced by NOR gates? 24.
Define Hazard. 9. How many flip-flops are required to build a counter of modulus 14 and modulus 8? 13. 3. Derive the characteristic equation of T flip-flop. When a sequential machine is said to be trivial? 2. Why CMOS is preferred to TTL? 5. 4. What are races? 10. What are cycles in asynchronous sequential circuits? 9. Define fundamental-mode operation. If the input frequency of a T flip – flop is 1600 KHz. Why critical race is said to be harmful and how it is avoided in asynchronous sequential Circuits? 8. What is the difference between serial and parallel transfer. 16. 7. what will be the output frequency? Give reason for your answer. When a sequential machine is said to be trivial? 25. How can the race conditions be avoided in flip-flops? 15. What is edge triggering? 23. Define Noise margin. What is a Mealy machine? Give an example. 17. Why a serial counter is referred to as asynchronous. 22. What is a race condition? 14. What is a state? 18.8. What is dynamic hazard? 12. What type of register is used in each case? 24. 11. Distinguish between combinational and sequential circuits. 6. UNIT –III PART – A 1. 12. 11. What are shift register counters? List two widely used shift register counters. What are the basic parameters to be noted before selecting an IC? 7. What are state diagrams and state table? 19. What is critical race? UNIT –IV PART – A 1. List out the differences between a flip-flop and a latch. Differentiate between Moore and Mealey type sequential circuits. Describe the behaviour of SR flip-flop by means of a table. Why parallel counter is faster than ripple counter? 5. What is the effect of increasing supply voltage on the propagation delay of the CMOS 11
. 3. Define static Hazard. What is FPGA? 2. Convert a D flip – flop into a T flip – flop. If a serial in serial out shift register has N stages and if the clock frequency is f. Define Fan-in and Fan out? 4. Why is state reduction necessary? 21. Compare PLA and PAL 6. How does the architecture of PLA different from PROM? 8. 20. what will be the time delay between input and output? 10.
17. 10. What is a test bench? 6. 12. State two advantage of CMOS logic. Differentiate PLA. Which is faster TTL or ECL? Which requires more power to operate? 11. 2. ROM and PAL. What is the advantage of Schottky TTL family? 13. Determine the Fan-out given IIH (max) = 40 μA and IOH (max) = 400 μA. 20. Why do CMOS gates require very little power when they are not changing states? Classify the basic families that belong to the bipolar families and to the MOS families.Give the different operators used in VHDL.9. UNIT V 1. 18. What is an ASM? 5. Differentiate EPROM and EEPROM. What is the major difference between TTL and ECL? Why does the propagation delay occur in logic circuits? Draw NAND and NOR gates in CMOS logic. What are the different types of operators? 3.
gates? What is volatile memory? Give example. 21. What are packages and libraries?
16. 15. 19. What is an EPROM? 14. What is an RTL level notation? 4.