6th Semester, B –Tech, VLSI Lab Manual using Tanner Spice © A.

Sarkar, ECE,KGEC

VLSI LAB MANUAL USING TANNER SPICE 6TH SEMESTER ECE
KALYANI GOVT. ENGG. COLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
DESIGNED & DOCUMENTED BY A. SARKAR ECE DEPT, K.G.E.C
List Of Experiments 1. I-V CHARATERISTICS OF NMOSFET WITH SIMPLE MODEL DESCRIPTON, CHANGE VARIOUS PARAMETERS IN THE MODEL OF NMOS AND OBSERVE THE EFFECT TRANSCONDUCTANCE CHARATERISTICS OF NMOSFET WITH SIMPLE MODEL DESCRIPTON, CHANGE VARIOUS PARAMETERS IN THE MODEL OF NMOS AND OBSERVE THE EFFECT Passing logic through cascaded pass transistors Passing logic through cascaded pass transistors driving next transistor gate terminal Design A Inverter With Resistive Pull Up And Find The Transfer Characteristics Design A Inverter With Nmos Depletion Load And Find The Transfer Characteristics Design A Cmos Inverter And Find The Transfer Characteristics Design A Nand Gate Using Cmos Using Pull Up And Pull Down Network Logic. Design A Nor Gate Using Cmos Using Pull Up And Pull Down Network Logic.

2.

3. 4. 5. 6. 7. 8. 9.

10. Design An Xor Gate Using Cmos Using Pull Up And Pull Down Network Logic. 11. Design A Full Adder Using Cmos Using Pull Up And Pull Down Network Logic And Measure The Power Dissipated. 12. Design A Xor Gate And Measure The Power. 13. Design A Mux Using Cmos. 14. using L-edit layout of inveter, NOR,NAND,AND gate Page 1 of 26

6th Semester, B –Tech, VLSI Lab Manual using Tanner Spice © A. Sarkar, ECE,KGEC

Problem 1: I-V CHARATERISTICS OF NMOSFET WITH SIMPLE MODEL DESCRIPTON, CHANGE VARIOUS PARAMETERS IN THE MODEL OF NMOS AND OBSERVE THE EFFECT.

* OUTPUT CHARACTERISTICS OF A NMOSFET .MODEL N1 NMOS VTO=1 KP=200U LAMBDA=0.01 .DC VDS 0 10 0.5 VGS 1 5 1 M1 2 1 0 0 N1 VGS 1 0 VDS 2 0 .PRINT ID(M1) .PROBE .END

T-Spice1
iD(M1)

1.5

Current (mA)

1.0

0.5

0.0 0 1 2 3 4 5 6 7 8 9 10

Voltage (V)

Problem 2: TRANSCONDUCTANCE CHARATERISTICS OF NMOSFET WITH SIMPLE MODEL DESCRIPTON, CHANGE VARIOUS PARAMETERS IN THE MODEL OF NMOS AND OBSERVE THE EFFECT.

* transconductance characteristics OF A NMOSFET .MODEL N1 NMOS VTO=1 KP=200U LAMBDA=0.01 .DC VGS 0 5 0.5 VDS 2 8 2 M1 2 1 0 0 N1 VGS 1 0 VDS 2 0 .PRINT ID(M1) .PROBE .END

Page 2 of 26

5 0 .5 Current (mA) 1 .5 4. ECE.5 3 . VLSI Lab Manual using Tanner Spice © A.5 Voltage (V) 2 .0 3 . B –Tech.5 0 .0 0 .KGEC T-Spice1 i D( M1) 1 .0 C=10pF W=22u Module0 5 .5 1 .0 4 .5 2 .6th Semester.0 0 .0 2.0 v( N3) 4 .5 1 .0 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 Time (ns) Module0 v( N2) 3 .5 0 .5 4 .0 0 .0 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 Time (ns) Page 3 of 26 .0 1 .0 1 .5 5 .0 2 .0 3 .0 0 . Sarkar.5 2 .0 1 .0 2 .5 1.5 3 .0 0 .5 Voltage (V) 3 .0 Voltage (V) Problem 3: passing logic through cascaded pass transistors L=2u W=22u L=2u V=5.

0 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 T im e (ns) Page 4 of 26 .6th Semester.0 W=22u L=2u W=22u L=2u C=10pF Module0 v( N7) 2 .0 0 .5 1 .5 1 .0 1 .5 4 . VLSI Lab Manual using Tanner Spice © A. ECE.0 2 .0 0 .KGEC Problem 4: passing logic through cascaded pass transistors driving gates of next one V=5.5 Voltage (V) 3 .0 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 T im e (ns) Module0 5 .0 Voltage (V) 1 .0 3 .5 0 . Sarkar.5 0 . B –Tech.0 v( N3) 4 .5 2 .

md" .op .0 v4 (V) Page 5 of 26 .0 1 .0 3 .0 2 .0 3 . VLSI Lab Manual using Tanner Spice © A.6th Semester.0.5 5 .end T-Spice1 5 .print v(N3) .0 v(N3 ) 4 .KGEC Problem 5: DESIGN A INVERTER WITH RESISTIVE PULL UP AND NMOS PULL DOWN AND FIND THE TRANSFER CHARACTERISTICS * RESISTIVE LOAD INVERTER C1 N3 Gnd 10pF M2 N3 N1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u R3 Vdd N3 1K TC=0.5 4 .5 Voltage (V) 3 .0 4 .0 0 .1 . 0. B –Tech.5 3.0 2.5 4 .dc v4 0 5.tf v(N3) v4 .5 1 .0 0. Sarkar.0 1 .5 2 .0 Vdd Vdd Gnd 5v .5 1 .0 v4 N1 Gnd 5.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.5 2 . ECE.0 0.

op .include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ. Sarkar.md" .tf v(N2) v4 .5 3. VLSI Lab Manual using Tanner Spice © A.0 1.5 2.KGEC Problem 6: DESIGN A INVERTER WITH NMOS ENHANCEMENT LOAD AND FIND THE TRANSFER CHARACTERISTICS * enhancement load inverter C1 N2 Gnd 10pF M2 Vdd Vdd N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N2 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v4 N5 Gnd 5.5 3.5 1.0 v4 (V) Page 6 of 26 .0 0.5 5.0 2.0 Vdd Vdd Gnd 5v .0 0.6th Semester.end T-Spice1 v(N2) 3.0 4.print v(N2) .dc v4 0 5. B –Tech. ECE.5 0.0 3.5 4.0 Voltage (V) 2.0 1.5 2.1 .

0 3. Sarkar.KGEC Problem 7: DESIGN A CMOS INVERTER AND FIND THE TRANSFER CHARACTERISTICS * cmos inverter C1 N3 Gnd 1pF M2 N3 N2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N3 N2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v4 N2 Gnd 5.0 v(N3) 4. B –Tech.5 4.0 0.0 Vdd Vdd Gnd 5v .include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.5 2.0 3.6th Semester. ECE.0 0.1 .0 0.op . VLSI Lab Manual using Tanner Spice © A.md" .0 2.0 v4 (V) Problem : 8 Page 7 of 26 .5 1.5 1.0 0.0 2.5 3.end T-Spice1 5.0 4.5 0.5 4.5 Voltage (V) 3.5 5.0 1.0 1.5 2.tf v(N3) v4 .print v(N3) .dc v4 0 5.

0 1 . Circuit Diagram: * nand gate cmos design C1 Y Gnd 1pF M2 Y A N15 N5 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N15 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M4 Y A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M5 Y B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u v6 A Gnd bit({0100} pw=100n on=5.KGEC Design a NAND Gate using CMOS using Pull up And Pull Down network logic.0 0 .0 0 5 0 1 00 1 50 2 00 2 50 3 00 3 50 4 00 Ti m (ns ) e T-Spice1 v ( Y) 8 00 Voltage (mV) 7 00 6 00 5 00 4 00 3 00 2 00 1 00 0 0 5 0 1 00 1 50 2 00 2 50 3 00 3 50 4 00 Ti m (ns ) e Page 8 of 26 .tran 1n 400n .0 3 . B –Tech. ECE.0 rt=1n ft=1n delay=0 lt=100n ht=100n) vdd vdd gnd 1v .0 v ( B) 4 .0 off=0.0 1 .5 Voltage (V) 4 .5 3 .5 1 .0 3 .include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.5 2 .END T-Spice1 5 .5 0 .5 2 .5 Voltage (V) 4 .0 off=0.0 2 .0 v ( A) 4 .0 0 .6th Semester.0 2 . VLSI Lab Manual using Tanner Spice © A.0 0 5 0 1 00 1 50 2 00 2 50 3 00 3 50 4 00 Ti m (ns ) e T-Spice1 5 .5 3 .md" .5 0 . Sarkar.5 1 .0 rt=1n ft=1n delay=0 lt=100n ht=100n) v7 B Gnd bit({0111} pw=100n on=5.print v(A) v(B) v(Y) .

Prob : 10 Design an XOR Gate using CMOS using Pull up And Pull Down network logic. ECE. Sarkar. B –Tech. VLSI Lab Manual using Tanner Spice © A.6th Semester.KGEC Problem : 9 Design a NOR Gate using CMOS using Pull up And Pull Down network logic. Circuit Diagram: NETLIST for the Circuit Page 9 of 26 .

0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 Vdd Gnd 1. Page 10 of 26 .0 off=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 Ab A Gnd Vdd NH L=.5 rise=1 targ v(Vout) val=.End of main circuit: Module0 Prob : 11 Design a Full adder using CMOS using Pull up And Pull Down network logic and measure the power dissipated.6th Semester. B –Tech.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Vout Ab N3 Gnd NH L=.include dual.0 off=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M9 Ab A Vdd Vdd PH L=. VLSI Lab Manual using Tanner Spice © A.tran 1n 400n .2u W=5u AD=66p PD=24u AS=66p PS=24u M10 Vout Bb N7 Vdd PH L=.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v14 B Gnd bit({0101} pw=100n on=1.measure tran delay trig v(B) val=.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 Vout B N8 Vdd PH L=.print v(A) v(B) v(Vout) .2u W=5u AD=66p PD=24u AS=66p PS=24u M12 N8 Ab Vdd Vdd PH L=2u W=5u AD=66p PD=24u AS=66p PS=24u v13 A Gnd bit({0011} pw=100n on=1.md .0 . ECE.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 N3 Bb Gnd Gnd NH L=.KGEC * Main circuit: Module0 M1 Vout A N4 Gnd NH L=.5 rise=1 . Sarkar.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 N4 B Gnd Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M8 Bb B Vdd N2 PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M11 N7 A Vdd Vdd PH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 Bb B Gnd N1 NH L=.

2u W=2u AD=66p PD=24u AS=66p PS=24u M5 N33 B Gnd Gnd NH L=. VLSI Lab Manual using Tanner Spice © A.print v(A) v(C) v(Carry) v(Sum) p(vdd) . Sarkar.2u W=5u AD=66p PD=24u AS=66p PS=24u M22 N14 C Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M23 N14 A Vdd Vdd PH L=.07E-09 4.power vdd .0 rt=1n ft=1n delay=0 lt=100n ht=100n) vdd vdd gnd 1v .2u W=5u AD=66p PD=24u AS=66p PS=24u M25 N27 B N22 Vdd PH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 Carry CarryB Gnd Gnd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 CarryB A N2 Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M17 CarryB B N1 Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M16 N11 B Vdd Vdd PH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M15 N11 A Vdd Vdd PH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M13 N55 C Gnd Gnd NH L=.90E-10 Page 11 of 26 .0 off=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 CarryB C N33 Gnd NH L=.60E-10 2.2u W=5u AD=66p PD=24u AS=66p PS=24u M24 N22 A Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M20 Carry CarryB Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M28 N9 C N27 Vdd PH L=.07E-09 3.2u W=2u AD=66p PD=24u AS=66p PS=24u M10 N47 C Gnd Gnd NH L=.KGEC NETLIST for the Circuit * * Main circuit: Module0 M1 N33 A Gnd Gnd NH L=.include dual.23E-10 4.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 C Gnd bit({00001111} pw=100n on=1. B –Tech.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 N2 B Gnd Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M18 N1 A Vdd Vdd PH L=.98E-08 9.2u W=2u AD=66p PD=24u AS=66p PS=24u M14 Sum N9 Gnd Gnd NH L=. ECE.2u W=5u AD=66p PD=24u AS=66p PS=24u M19 CarryB C N11 Vdd PH L=.0 off=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 N9 CarryB N55 Gnd NH L=.81E-09 2.95E-09 A 0 0 0 0 B 0 0 1 1 C 0 1 0 1 Delay 0 6.2u W=2u AD=66p PD=24u AS=66p PS=24u M12 N9 A N51 Gnd NH L=.95E-09 0 2.2u W=2u AD=66p PD=24u AS=66p PS=24u M8 N55 A Gnd Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M21 N14 B Vdd Vdd PH L=.End of main circuit: Module0 Results for Power and Delay for the Circuit FULL_ADDER CIRCUIT for HIGH THRESHOLD Sum Carry Power Delay Power 3.2u W=2u AD=66p PD=24u AS=66p PS=24u M9 N55 B Gnd Gnd NH L=.tran 1n 800n .98E-08 2.81E-09 9.md .6th Semester.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v14 A Gnd bit({00110011} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M11 N51 B N47 Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M26 Sum N9 Vdd Vdd PH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u v13 B Gnd bit({01010101} pw=100n on=1.0 off=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M27 N9 CarryB N14 Vdd PH L=.

tran 1n 400n .2u W=2u AD=66p PD=24u AS=66p PS=24u M4 Ab A Gnd Vdd NH L=.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 Bb B Gnd N3 NH L=.25E-08 3.28E-08 6.6th Semester.md .2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Bb A Vout Gnd NH L=.2u W=5u AD=66p PD=24u AS=66p PS=24u M7 Ab A Vdd Vdd PH L=.81E-09 1.28E-08 6. ECE.measure tran delay trig v(B) val=.5 rise=1 targ v(Vout) val=.power v11 100n . Circuit Diagram: NETLIST for the Circuit * Main circuit: Module0 M1 B Ab Vout Gnd NH L=. B –Tech.12E-09 4.81E-09 0 7. Sarkar.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v11 Vdd Gnd 1.0 off=0.69E-08 1.0 . VLSI Lab Manual using Tanner Spice © A.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 B A Vout Vdd PH L=.69E-08 1.80E-10 1.80E-10 Prob : 12 Design a XOR Gate using CMOS using Transmission Gate logic and measure the Power.2u W=5u AD=66p PD=24u AS=66p PS=24u v9 A Gnd bit({0011} pw=100n on=1.2u W=5u AD=66p PD=24u AS=66p PS=24u M6 Bb B Vdd N2 PH L=.32E-10 8.25E-08 3.KGEC 1 1 1 1 0 0 1 1 0 1 0 1 3.include dual.00E-09 3.2u W=5u AD=66p PD=24u AS=66p PS=24u M8 Bb Ab Vout Vdd PH L=.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v10 B Gnd bit({0101} pw=100n on=1.5 rise=1 * End of main circuit: Module0 Page 12 of 26 .print v(A) v(Vout) p(v11) .

0 rt=1n ft=1n delay=0 lt=100n ht=100n) v4 I3 Gnd bit({01} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M5 I2 A Y1 Gnd NH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M16 Y2 Bb Y Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M14 I3 Ab Y2 Vdd PH L=0.tran 1n 200n .KGEC * BEGIN NON-GRAPHICAL DATA Power Results v11 from time 1e-007 to 1e-030 Average power consumed -> 2.2u W=5u AD=66p PD=24u AS=66p PS=24u M15 Y1 B Y Vdd PH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M12 I1 A Y2 Vdd PH L=0.include "C:\Documents and Settings\Administrator\Desktop\Batch2_Vivita\dual. B –Tech.479105e-006 watts Max power 4.md" .2u W=5u AD=66p PD=24u AS=66p PS=24u M13 I2 Ab Y1 Vdd PH L=0.END Page 13 of 26 .6th Semester.0 off=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M9 Ab A Vdd Vdd PH L=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v5 A Gnd bit({01} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M8 Y2 B Y Gnd NH L=0.0 off=0.2u W=2u AD=66p PD=24u AS=66p PS=24u M4 I1 Ab Y2 Gnd NH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M11 I0 A Y1 Vdd PH L=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v2 I1 Gnd bit({01} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M6 I3 A Y2 Gnd NH L=0. Sarkar.0 off=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v15 Vdd Gnd 1.2u W=5u AD=66p PD=24u AS=66p PS=24u * End of main circuit: Module0 v1 I0 Gnd bit({11} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M7 Y1 Bb Y Gnd NH L=0.2u W=5u AD=66p PD=24u AS=66p PS=24u M10 Bb B Vdd Vdd PH L=0.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v6 B Gnd bit({00} pw=100n on=1.2u W=2u AD=66p PD=24u AS=66p PS=24u M3 I0 Ab Y1 Gnd NH L=0.0 off=0.0 off=0.0 .13097e-007 Prob : 13 Design a MUX using CMOS.2u W=2u AD=66p PD=24u AS=66p PS=24u M2 Bb B Vdd Gnd NH L=0.620846e-009 at time 2.00752e-007 Min power 1.0 off=0. ECE.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v3 I2 Gnd bit({00} pw=100n on=1. NETLIST for the Circuit * Main circuit: Module0 M1 Ab A Vdd Gnd NH L=0. VLSI Lab Manual using Tanner Spice © A.043389e-004 at time 2.print v(I0) v(I1) v(I2) v(I3) v(Y) .

6th Semester. Cell -> New. Draw two 2 x 2 λ Active Contact centered on each Metal 1 box It looks like. Draw two 4 x 4 λ Metal1 box and put on both sides of Active box.KGEC Layout design Lab using L-edit How to build a MOSFET layout using L_edit Inverter Using L-Edit Launch L-Edit Create New File. the TDB file from which to take setup information for the new file. B –Tech. ECE.12\ledit. Layout produces a Tanner Database (TDB) file. by typing the name of the file into the text field. Create new files by choosing File > New . Sarkar. call it inv    Draw 14 x 6λ Active Box where H=14 λ and W=6λ. VLSI Lab Manual using Tanner Spice © A. You will be able to choose the source setup file by selecting one from the list of predefined setup files. which opens the New File dialog: Options include: File type The type of file to create.   Page 14 of 26 . Text creates an ASCII text file for normal text editing Copy TDB setup from file For Layout files.tdb  Under Setup -> Design The chosen technology units should be lambda It should be 1 internal unit for 1/1000 lambda The lambda value should be equal to 1 micron. Under Grid tab -> Grid Display -> Displayed Grid can be chosen 0. C:\L-Edit Student v7.5 locator units  Create a new cell. or by browsing.

 Page 15 of 26 . Draw 18 x 10λ N Select. Sarkar. ECE.6th Semester. B –Tech. VLSI Lab Manual using Tanner Spice © A.KGEC    Draw 2 x10λ poly box centered at the active where W=10 and H=2λ.

VLSI Lab Manual using Tanner Spice © A. it looks like:   Copy the whole block above. Sarkar.6th Semester.KGEC     Draw 10 x 10λ P Select below the Nselect of NMOS. Draw 2 x 2 λ Active Contact inside the Active Extend the Metal1 to Pselect area. B –Tech. change N Select to be P Select. it looks like: Page 16 of 26 . select N Select and click Edit -> Edit Object. ECE. . Draw 6 x 6 λ Active inside the Pselect. With the same method draw a Nselect on the top of PMOS.

Page 17 of 26 . ECE. B –Tech.6th Semester.KGEC  Draw 34x 16λ Nwell at PMOS place. Sarkar. VLSI Lab Manual using Tanner Spice © A.

Page 18 of 26 . ECE.6th Semester. Sarkar.KGEC  Connect following the inverter schematic. VLSI Lab Manual using Tanner Spice © A. B –Tech.

VLSI Lab Manual using Tanner Spice © A. Sarkar. Draw 2 x 2 λ l Poly Contact centered in the Metal1 Page 19 of 26 . B –Tech.KGEC    Draw 6 x5 λ Poly beside the gate of two transistors. ECE. Draw 4 x 4 λ Metal 1 centered in the poly.6th Semester.

write node names.KGEC  Click Port on the Toolbar. For extraction give a name for the spice output file. go to next step. place device labels on layer1. B –Tech. In the output tab click on write nodes as names. Similarly draw VDD. On Layer: Metal1 Port name: OUT. VLSI Lab Manual using Tanner Spice © A.6th Semester. And draw OUT port. The dialog jumps out. Sarkar. Open T-spice from startprograms tanner EdaTspice Prov7. ECE. then add the following lines and run Page 20 of 26 .0Tspice menu and open the extracted file. Extract the file to be SPICE file. IN port. GND.    Run DRC check If No DRC error.

 Polysilicon width =2λ  N well surrounding pMOs by 6λ and avoids nMOS transsitor by 6λ Some other Layout of INVERTER Page 21 of 26 .5 -30 76.include "C:\Tanner\TSpice70\models\ml2_20.5) Vin IN GND PULSE (0 5 0 1n 1n 100n 200n) Vdd VDD GND 5 .6th Semester.END Summary of Design rules  Metal and Diffusion have minimum width and spacing of 4λ. Sarkar. ECE. B –Tech.md" M1 OUT IN VDD VDD PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u * M1 DRAIN GATE SOURCE BULK (-36 107 -30 109) M2 GND IN OUT GND NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u * M2 DRAIN GATE SOURCE BULK (-36 74.KGEC .  Contacts 2λ X 2λ and are surrounded by 1λ.tran/powerup 5n 500n .print tran v(IN) v(OUT) . VLSI Lab Manual using Tanner Spice © A.

VLSI Lab Manual using Tanner Spice © A.KGEC Or another VERSION OF INVERTER as GIVEN BELOW Page 22 of 26 . B –Tech. ECE. Sarkar.6th Semester.

ECE.6th Semester. VLSI Lab Manual using Tanner Spice © A. B –Tech. Sarkar.KGEC Page 23 of 26 .

6th Semester. ECE. B –Tech. Sarkar. VLSI Lab Manual using Tanner Spice © A.KGEC Layout of NOR gate as follows Page 24 of 26 .

VLSI Lab Manual using Tanner Spice © A.6th Semester. ECE. B –Tech.KGEC Layout of NAND gate as given below Page 25 of 26 . Sarkar.

include "C:\Tanner\TSpice70\models\ml2_20.tran 5n 500n .6th Semester.0 off=0.5p PS=107u * M1 DRAIN GATE SOURCE BULK (90 38 92 44) M2 CPL A VDD 9 PMOS L=1u W=3u AD=16.5p PD=107u AS=16.KGEC Layout of AND gate as given below .md" M1 OUT CPL VDD 10 PMOS L=1u W=3u AD=9p PD=12u AS=133.0 rt=1n ft=1n delay=0 lt=100n ht=100n) v7 B Gnd bit({0111} pw=100n on=5.5p PD=17u AS=133.5p PS=17u * M3 DRAIN GATE SOURCE BULK (20 36 22 42) M4 OUT CPL GND GND NMOS L=1u W=3u AD=10.0 rt=1n ft=1n delay=0 lt=100n ht=100n) Vdd VDD GND 5 .END Page 26 of 26 . B –Tech.5p PD=13u AS=108p PS=78u * M6 DRAIN GATE SOURCE BULK (20 15 22 21) v6 A Gnd bit({0100} pw=100n on=5.0 off=0. ECE.print v(B) v(A) v(CPL) v(OUT) .5p PS=107u * M2 DRAIN GATE SOURCE BULK (7 36 9 42) M3 VDD B CPL 9 PMOS L=1u W=3u AD=133. Sarkar.5p PS=63u * M4 DRAIN GATE SOURCE BULK (90 10 92 16) M5 7 A 8 GND NMOS L=1u W=3u AD=108p PD=78u AS=15p PS=16u * M5 DRAIN GATE SOURCE BULK (7 -6 9 0) M6 CPL B 7 GND NMOS L=1u W=3u AD=10. VLSI Lab Manual using Tanner Spice © A.5p PD=13u AS=76.

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