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Code No: NR320404 NR

III B.Tech II Semester Supplementary Examinations, Apr/May 2006
( Common to Electronics & Communication Engineering and Electronics &
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) What are the steps involved in the n MOS fabricationExplain with neat
(b) In what way p MOS fabrication is different from n MOS fabrication? [10+6]
2. (a) Derive the relation ship between drain to source current Ids verses drain to
source voltage Vds in non saturated and saturated region.
(b) Draw graphs of Ids vs Vds for depletion and enhancement mode MOS tran-
sistors. [8+8]
3. Using block schematics, explain the terms
(a) PLDs
(b) CPLDs
(c) FPGAs
(d) PALs [16]
4. Explain about the design approaches for full custom and semi custom Devices [16]
5. Taking 4 bit ALU as an example , give the behavioural synthesis in VHDL. [16]
6. Discuss the following types of simulations
(a) circuit level [4]
(b) logic level [3]
(c) switch level [3]
(d) mixed mode and [3]
(e) timing simulations. [3]
7. (a) How packaging is affects on the cost of VLSI chip?
(b) Explain through hole type packages. [8+8]
8. (a) Explain the use of switched capacitor methodology to design and implement
Analog VLSI filter.
(b) Which technology is predominant for switched capacitor filters in VLSI? Why?


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