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The transmitter consists of three blocks. They are 1. Transmit Data Register 2. Transmit Shift register 3. Transmitter controller The main function of the TDR is to transfer the data serially from data bus to TSR. For the transfer of data from data bus to TSR there is a need of few flags to check and control the TDR. The flag of SCSR namely TDRE (Transmit Data Register Empty) controls the functioning of TDR. When the TDR is free the flag TDRE shows high. Then the data from the data bus flows into TDR bit by bit. If the TDRE flag is low it means that the register TDR is full or containing some information. After the transfer of information from TDR to TSR, the TDRE flag again sets/becomes high which means that the TDR is ready to accept another byte of data. Thus the data from data bus to TDR is transferred. Now the second step is to transfer the data from TDR to TSR. Initially the register TSR contains all ones. All ones implied that the register TSR is empty. So,
hence the SM moves again to the idle state and waits till the register TDR becomes empty. When the TDRE is high it means that the register TDR is empty.the data from the register TDR flows into the register TSR. According to the flag TDRE it follows. All these operations of transmitter are controlled by the transmitter controller by one of the clocks generated by the baud rate generator. The data is synchronized according to the bclk generated by the baud rate generator. Initially the SM will be in idle state. set the TDRE flag. So. When the TDR is loaded. then again the TSR becomes empty and again loads all the register bits to one. . If the register TDR contains some data then the TDRE flag shows zero. Thus the data from TDR to TSR is transferred. When the data from TSR is transferred to UART receiver. Below flow chart clearly shows how the transmitter works. the data from the data bus flows into TDR.
Here a counter is used to count the data bits transferred.e. then transfer the data to TSR. According to the clock raising edges these operations are handled by the transmitter controller. 8 bits from TDR and one zero bit to start the data transfer.When the bclk is high. The TDR contains 8 bits of data where in TSR there will be 9 bits of data i. After all the data is transferred the counter will be cleared and the process is repeated. .