Agenda

Introduction: SystemVerilog Motivation
Vassilios Gerousis, Infineon Technologies Accellera Technical Committee Chair

Session 3: SystemVerilog Assertions Language Tutorial
Bassam Tabbara, Novas Software

Tecnhology and User Experience
Alon Flaisher, Intel

Session 1: SystemVerilog for Design Language Tutorial
Johny Srouji, Intel

Using SystemVerilog Assertions and Testbench Together
Jon Michelson, Verification Central

User Experience
Matt Maidment, Intel

Session 4: SystemVerilog APIs
Doug Warmke, Model Technology

Session 2: SystemVerilog for Verification Language Tutorial
Tom Fitzpatrick, Synopsys

Session 5: SystemVerilog Momentum Verilog2001 to SystemVerilog
Stuart Sutherland, Sutherland HDL

User Experience
Faisal Haque, Verification Central
Lunch: 12:15 – 1:00pm

SystemVerilog Industry Support
Vassilios Gerousis, Infineon
End: 5:00pm

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DAC2003 Accellera SystemVerilog Workshop

SystemVerilog 3.1 Design Subset
Johny Srouji Intel Chair – SV-Basic Committee

30

DAC2003 Accellera SystemVerilog Workshop

Presentation Outline
• • • • • • • Data Types Structures & Unions Literals Enumerated Data Types Constants & Parameters Scope & Lifetime Interfaces

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DAC2003 Accellera SystemVerilog Workshop

// byte b8.1 Data Types reg r. x 0 1 or z as in Verilog 8 bit signed integer 2-state. // int i. 64-bit signed integer Make your own types using typedef Use typedef to get C compatibility typedef typedef typedef typedef 32 shortint longint real shortreal short. 16-bit signed integer 2-state. // shortint s. // bit b.Basic SV3. longlong. double. DAC2003 Accellera SystemVerilog Workshop . 32-bit signed integer 2-state. float. // logic w. // integer i. // 4-state Verilog-2001 single-bit datatype 4-state Verilog-2001 >= 32-bit datatype single bit 0 or 1 4-valued logic.// longint l.

integer i. Verilog reg and integer type bits can contain x and z values Equivalent to these 4-valued SystemVerilog types These SystemVerilog types have two-valued bits (0 and 1) logic a.2 State and 4 State Data Types Verilog SystemVerilog SystemVerilog reg a. If you don't need the X and Z values then If you don't need the X and Z values then use the SystemVerilog bit and int types use the SystemVerilog bit and int types which MAKE EXECUTION FASTER which MAKE EXECUTION FASTER 33 DAC2003 Accellera SystemVerilog Workshop . logic signed [31:0] i. SystemVerilog bit a. int i.

Packed indexes can be sliced bit [15:0] [1023:0] Frame.Packed And Unpacked Arrays unpacked array of bits packed array of bits 1k 16 bit unpacked memory bit a [3:0]. memory[i] [15:8] = 0. unused Don’t get them mixed up a0 a1 a2 a3 bit [3:0] p. always @inv Frame = ~Frame. 1k 16 bit packed memory Can operate on entire memory 34 DAC2003 Accellera SystemVerilog Workshop . memory[i] = ~memory[i]. p3 p2 p1 p0 bit [15:0] memory [1023:0].

IR. bit [23:0] addr. } instruction. opcode. // anonymous structure Like in C but without Like in C but without the optional structure the optional structure tags before the {{ tags before the typedef struct { bit [7:0] opcode.Structures struct { bit [7:0] bit [23:0] } IR. // named structure type instruction IR.opcode = 1. // define variable // set field in IR 35 DAC2003 Accellera SystemVerilog Workshop . addr.

$display("n=%d". like in C again. $finish(0).u.n).f = 3. initial begin u. $display("f=%f". like in C structs and unions can be assigned as a whole int real Can be passed through tasks/functions/ports as a whole can contain fixed size packed or unpacked arrays 36 DAC2003 Accellera SystemVerilog Workshop .n = 27.1415.f). } u_type. u. real f. u_type u.Unions typedef union { int n. end union provide storage for either int or real again. u.

iAddr = Entry.Addr. `define Valid 24 `define Tag 23:16 `define Addr 15:0 iTag = Entry[`Tag].Valid packed struct may packed struct may contain other packed contain other packed structs or packed arrays structs or packed arrays unpacked struct reg [24:0] Entry. } Entry. bit [15:0] Addr. iValid = Entry. iAddr = Entry[`Addr]. byte Tag.Packed Structures Represents bit or part selects of vectors struct packed { bit Valid. iTag = Entry. iValid = Entry[`Valid] 32 2 1 0 24 23 1615 Valid Tag 0 Valid Tag Addr 0 Addr packed struct 37 DAC2003 Accellera SystemVerilog Workshop .Tag.

b.1 Literals • SV literal values are extensions of those for Verilog reg [31:0] a. 'z.. . c = 16'hFFFF This works like in Verilog Adds the ability to specify unsized literal single bit values with a preceding ‘ a b c d = = = = '0... a = 32'hffffffff. reg [15:0] c.d.. 38 DAC2003 Accellera SystemVerilog Workshop . 'x. '1. This fills the packed array with the same bit value These are equivalent logic [31:0] a. a = 32'hf0ab.SV 3. a = '1. .

#1ps $display("%b". You can also specify delays with explicit units Similar to C.1. b).1 Literals This works like in Verilog Adds time literals #10 a <= 1.2}. #5ns b <= !b. but with the replication operator ({{}}) allowed Adds Array literals int n[1:2][1:3] = {{0.SV 3.{3{4}}} 39 DAC2003 Accellera SystemVerilog Workshop .

enum {bronze=4’h3. anonymous int type silver=4. yellow. Colors col. gold=4’h5 enum {bronze=3. b. blue. silver. col = yellow. white. enum {a=0. typedef enum {red. c. gold} medal. light2.Enumerated Data Types enum {red. green. a = blue * 3. a=2*3=6 col=3 b=3+1=4 40 DAC2003 Accellera SystemVerilog Workshop . gold=5 Syntax error silver=4’h4. b=7. silver. integer a. gold} medal. d=8} alphabet. b = col + green. green} light1. black} Colors. yellow.

Unpacked_s A. bit [7:0] f2. } Unpacked_s. … A = Unpacked_s’(B). typedef struct packed { bit [15:0][0:2] f1.0) shortint' {8’hFA.0 * 3. } Packed_s. bit [15:0] f2. B = Packed_s’(A). bit [7:0] f3[0:5]. 41 Objects must have Objects must have identical bit size identical bit size A f1 f2 f30 f31 f32 f33 f34 f35 B f10 f11 f12 f2 DAC2003 Accellera SystemVerilog Workshop . Array ⇔ Structure typedef struct { bit [7:0] f1. 8’hCE} 17 ' (x – 2) A data type can be changed by using a cast (‘) operation • Any aggregate bit-level object can be reshaped – Packed ⇔ Unpacked. Packed_s B.Type Casting int'(2.

TRUE). module top. – No order dependency problems when compiling • specparam is used for specify blocks global constant Can contain an expression with any hierarchical path name const bit TRUE = 1. localparam bit FALSE = 0. // -1 endmodule 42 DAC2003 Accellera SystemVerilog Workshop . const logic option = a.b. • Local constant (localparam) is resolved at the BEGINNING of elaboration. localparam int TRUE = -1. Can’t be overridden with defparam local constant initial $display(“TRUE=%d".Constants • Use like defines or parameters • Global constant (const) is resolved at the END of elaboration.c.

end endmodule module clockgen (output ctype clk). initial clk <= start_value.ctype(int)) c (clk). always @clk $display("t=%t clk=%b". always #delay clk <= !clk.start_value(1'b1). parameter time delay=100. parameter logic start_value=0. logic clk. clk). $finish(0).delay(50). . clockgen #(.Parameters module top. . endmodule 43 DAC2003 Accellera SystemVerilog Workshop Override parameters by name Parameter used before definition Parameters can have explicit type . initial begin repeat(10) @(posedge clk) . $time. parameter type ctype=bit.

e. in $root) – Accessible from any scope – Must be static – Tasks and functions can be global too • Automatic variables – Enable recursive tasks and functions – Reallocated and initialized each time entering a block – May not be used to trigger an event • Local variables – Accessible at the scope where they are defined and below – Default to static.Variable Types • Static variables – Allocated and initialized at time 0 – Exist for the entire simulation • Global variables – Defined outside of any module (i. can made automatic – Accessible from outside the scope with a hierarchical pathname 44 DAC2003 Accellera SystemVerilog Workshop .

local n $root. i<=max. data declared outside of modules is static and global i is automatic and local to that block global n int max = 10. data declared inside n = 1. end endmodule 45 DAC2003 Accellera SystemVerilog Workshop . int n.Scope and Lifetime top inst. for (int i=2.n = n. initial begin automatic int i. module top. i<=max. of a module is static for (i=2. int n. end tasks and functions in initial begin : myblock that module n = 1. i++) n *= i. i++) and available to all n *= i.

// j uses default • Pass by Reference Optional “read-only” qualifier – Declaration: task tk([const] ref int[1000:1] – Usage: tk(my_array). foo(. foo(5). int k=8).Task and Function Arguments • Default Arguments – Definition: task foo(int j=5. • Pass by Name foo(. . – Usage: foo().8). foo(5. // note: no ‘&’ Simplifies Task/Function Usage 46 DAC2003 Accellera SystemVerilog Workshop ar).k(22)).8).

… Blocking Assignments as expressions Auto increment/ decrement operators continue starts next loop iteration works with: for while forever repeat do while break exits the loop if ( (a=b) ) … while ((a = b || c)) x++. f <<= 3.Familiar C Features In SystemVerilog do begin if ( (n%3) == 0 ) continue. a =?= b a !?= b Extra parentheses required to distinguish from if(a==b) Wildcard Comparisons X and Z values act as wildcards 47 Assignment Operators Semantically equivalent to blocking assignment DAC2003 Accellera SystemVerilog Workshop . s &= mask. end while (foo != 0). a += 3. if (--c > 17) c=0. if (foo == 22) break.

Enables efficient transaction modeling .Significant code reduction saves time .Reduces errors. easier to modify .Allows automated block verification 48 DAC2003 Accellera SystemVerilog Workshop .SystemVerilog Interfaces Design On A White Board HDL Design SystemVerilog Design Bus Bus Interface Bus Signal 1 Signal 2 Read() Write() Assert Complex signals Bus protocol repeated in blocks Hard to add signal through hierarchy Bus Communication encapsulated in interface .

49 .What is an Interface? • Provides a new hierarchical structure – – – – – Encapsulates communication Captures Interconnect and Communication Separates Communication from Functionality Eliminates “Wiring” Errors Enables abstraction in the RTL int i. logic [7:0] a. } s_type. At the simplest At the simplest int i. typedef struct { int i. level an interface is to aawire endinterface : intf is to wire what aastruct is what struct is to aavariable to variable DAC2003 Accellera SystemVerilog Workshop interface intf. level an interface wire [7:0] a. logic [7:0] a. int i. wire [7:0] a.

B.F. endinterface intf w.How Interfaces work interface intf. modA m1(w).D. endmodule module modB (intf i1). byte C. bit A. logic E. endmodule modA Instantiate Interface intf modB An interface is similar to a module straddling two other modules An interface can contain An interface can contain anything that could be in a anything that could be in a module except other module except other module definitions or module definitions or instances instances Allows structuring the information flow between blocks 50 DAC2003 Accellera SystemVerilog Workshop . module modA (intf i1). modB m2(w).

logic rdy).clk. output logic req.addr. memMod mem(req.data.Example without Interface logic req.mode). addr. logic gnt.gnt.start.rdy.rdy).data. always @(posedge clk) gnt <= req & avail. logic req.start. bit clk = 0. cpuMod cpu(clk. logic[1:0] mode.data. logic [7:0] addr.rdy.gnt. logic[7:0] addr. module memMod(input module top. endmodule Top clk req start gnt rdy mode[1:0] addr[7:0] data[7:0] CPU Mem endmodule 51 DAC2003 Accellera SystemVerilog Workshop . logic start. logic[1:0] mode). logic [1:0] mode. bit clk. logic[7:0] addr.start. output logic gnt. endmodule module cpuMod(input bit clk. req.mode. inout logic [7:0] data. logic start.gnt. logic rdy. inout logic[7:0] data.

Connect logic [7:0] addr. . instance in interface logic req.data.b(sb_intf). simple_bus sb_intf.Example Using Interfaces interface Bundle signals interface simple_bus. input bit clk). interface logic [1:0] mode. logic avail.gnt. module top. Use interface endmodule keyword in port list module memMod(interface a. endmodule 52 DAC2003 Accellera SystemVerilog Workshop Top clk CPU sb_intf Mem .req & avail. always @(posedge clk) a.rdy. memMod mem(sb_intf. bit clk = 0. logic start.gnt <= a. input bit clk). endinterface: simple_bus cpuMod cpu(. clk). endmodule Refer to intf signals module cpuMod(interface b.clk(clk)).

end endtask task read(output data_type d). for (int i = 0. task write(input data_type d).Encapsulating Communication interface serial(input bit clk). i++) begin if (i==0) data_start <= 1. task write(input data_type d). i++) begin d[i] <= data_wire. @(posedge clk) data_wire = 'x. data_bus <= d. data_valid <= 0. endtask task read(output data_type d). for (int i = 0. while (data_valid !== 1) @(posedge clk). i <= 31. logic data_valid=0. data_wire = d[i]. @(negedge clk) . end endtask endinterface Serial Interface 53 DAC2003 Accellera SystemVerilog Workshop . @(posedge clk) . data_valid <= 1. i <= 31. endtask endinterface logic data_wire. d = data_bus. while (data_start !== 1) @(negedge clk). @(posedge clk) data_bus <= 'z. Parallel Interface interface parallel(input bit clk). logic [31:0] data_bus. logic data_start=0. else data_start <= 0.

serial channel(clk). bit clk. communication i.Using Different Interfaces typedef logic [31:0] data_type. data_type d. method from endmodule interface send receive parallel serial interface 54 DAC2003 Accellera SystemVerilog Workshop . bit clk. receive r(clk.. channel). channel). always #100 clk = !clk. typedef logic [31:0] data_type. send s(clk. channel). interface i). module send(input bit clk. parallel channel(clk). receive r(clk. channel). send s(clk. always #100 clk = !clk.write(d). Module inherits ..

twisted busses) as well as functionality 55 tbS S A B DAC2003 Accellera SystemVerilog Workshop . structure (missing wires.Conventional Verification Strategy • PreIntegration Test Subblocks in isolation tbA tbB • Testbench reuse problems • tbA and tbB separate A B • Complex interconnect • Hard to create tests to check all signals • Slow. runs whole design even if only structure is tested • PostIntegration Need to check interconnect.

SystemVerilog Verification Strategy • PreIntegration Test interface in isolation tbS tbI I tbA I tbB I A B • Post-Integration S A Protocol bugs already flushed out 56 I B • Interfaces provide reusable components • tbA and tbB are ‘linked’ • Interface is an executable spec • Wiring up is simple and not error prone • Interfaces can contain protocol checkers and coverage counters DAC2003 Accellera SystemVerilog Workshop .

SystemVerilog Interfaces: The Key to Design Exploration • Interfaces Encapsulate Data and How Data Move Between Blocks • Design Exploration is All About Looking at Alternatives BlkA BlkB 57 DAC2003 Accellera SystemVerilog Workshop .

SystemVerilog Interfaces: The Key to Design Exploration • Interfaces Encapsulate Data and How Data Move Between Blocks • Design Exploration is All About Looking at Alternatives • Interfaces Should Support Multiple Layers of Abstraction for both “Send” and “Receive” – Shield BlockA from Abstraction Changes in BlockB 58 DAC2003 Accellera SystemVerilog Workshop BlkA BlkB .

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