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Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 1

LECTURE 220 AC ANALYSIS OF THE 741 OP AMP


(READING: GHLM 462-472)
Objective
The objective of this presentation is to:
1.) Identify the devices, circuits, and stages in the 741 operational amplifier
2.) Perform a small-signal analysis
3.) Compare hand calculations of small-signal analyses with PSpice simulations
Outline
Small-signal analysis
Frequency Compensation of 741
PSpice analysis techniques and results
Summary

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 2

741 OPERATIONAL AMPLIFIER


Circuit
VCC
Q9

Q13A

Q8

Q14

Q13B
Q19

Q12
+
R5

Q2

Q1
Q3

39k

VCC

Cc

R10
40k

Q4

Q23B

VCC

Q15
R6
27

Q18

vout

R7
27

Q23A
Q21

Q7

Q16
Q20

Q10

Q11

Q5

Q6

Q17
Q24

Q22
R4
5k

R3
R1
R2
1k 50k 1k

R9
50k

VEE

ECE 6412 - Analog Integrated Circuit Design - II

R8
100

50k
Fig. 210-01

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 3

Simplified Schematic of the 741 Op Amp with Idealized Biasing


VCC = 15V
Q9

Q8

550A

180A
Q14

Q2

Q1
Q3

VCC

Cc

Q4

Q5

R10
40k

VCC

Q7

19A

R6
27

Q19
Q18

vout

R7
27

Q16

Q20
Q23

Q6
Q17
R3
R1
R2
1k 50k 1k

R8
100

R9
50k
VEE = -15V

Fig. 210-05

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 4

SMALL-SIGNAL ANALYSIS OF THE 741 OP AMP


Input Stage
+
vid
2

Q2

Q1
Q3

Q4
ic4
iout

ic2
Q7
Q5

ic6
Q6

R3
R1
1k 50k

ECE 6412 - Analog Integrated Circuit Design - II

R2
1k

vid
2
+
vid
-

Rid
Gmvid

Ro1

Fig. 220-01

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 5

Small-Signal Analysis of the Input Stage - Continued


+
vid
2

Q2

Q1
Q3

vid
2

Q4

ic3

vid
2

v1

r1

gm1v1

gm3v3

+
v3

ic4

r3

Fig. 220-02

Start with, 0.5vid = v1+v3


KCL at the emitters gives,
gm1v1 + g1v1 = gm3v3 + g3v3

1
1
gm1v11+o1 = gm3v31+o3

gm3(1+1/o3)
0.5vid = -v gm1(1+1/o1) +1

Assuming that gm1 = gm3 (|IC1| = |IC3|) and o1, o3>>1, then
ic4 = +gm4vid/4 (symmetry)
v3 = -vid/4 and ic3 = -gm3vid/4 and
iout = -ic4 + ic3 = -gm3vid/2 = -gm1vid/2
gm1
9.5A
1
Gm1 = -iout/vid = 2 = 2(25.9mV) = 5.4k

Gm1 = 183.4S
Small-Signal Analysis of the Input Stage - Continued

ECE 6412 - Analog Integrated Circuit Design - II


Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

P.E. Allen - 2002


Page 220 - 6

The input resistance can be written as

(N+1)r3

Rid = 2r1 + P+1


Calculating the small-signal model parameters,
IC1
IC3
NVt
PVt
r1 = IC1 = 684k, gm1 = Vt = 365S, r3 = IC3 = 137k, gm3 = Vt = 365S

(N+1)r3

Rid = 2r1 + +1 = 2.72M


P

where

N 250

and P 50

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 7

Calculation of the Input Stage Output Resistance


+

Q2

Q1
Q3

1
gm2

Q4

Q4

ix

ix
Q7

vx

vx

Q5

Q6
R3
R1
1k 50k

Q6
R2
1k

R2
1k

Fig. 220-03

VAP
gm4

ro4 = IC4 = 5.26M


ro4T = ro41+gm2 = 10.53M

VAN
ro6T = ro6(1+gm2R2) = 18.7M
ro6 = IC6 = 13.7M
Ro1 = ro4T||ro6T = 6.8M

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 8

Two-Port Equivalent Network for the Input Stage


+
vid
-

Rid
2.7M

vid

5.4k

Ro1
6.8M
Fig. 220-04

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 9

Small-Signal Equivalent Model for the Second Stage


Q13B
vout

Ri2

Ri2

Q16

+
vi2
-

Q16
Q17

Req1
R9
50k

R9
50k

R8
100

Ri2

Gm2vi2

Ro2

Req1
Fig. 220-05

Output Resistance:
NVt
r17 = I
= 11.8k Req1 = r17 + (N + 1)R8 =36.9k
C17
Ri2 = r16 + ( N +1)(R9||Req1)= 5.72M
The first-stage load is RLoad1 = Ro1||Ri2 = 3.1M
Av1 = Gm1RLoad1= 565 55dB

NVt
r16 = IC16 = 394k

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 10

Small-Signal Equivalent Model for the Second Stage - Continued


Transconductance:
gm17
1
Gm2 = 1+g R = 6.79mS
Gm2 = 147
m17 8

gm17R8

Ro2 = ro13B||ro171+
gm17R8 ro13B||[ro17(1+gm17R8)] if 0 >> gm17R8

1 + 0
[Recall that the output resistance of a BJT cascoding a resistor RE is ro(1+gmRE)]
ro13B = VAP/IC13B = 50V/550A = 90.9k
ro17 = VAN/IC17 =130V/550A = 236.4k
Ro2 = ro13B||ro17T = 80.9k
ro17T = ro17(1+gm17R8) = 732.3k
+
vi2
-

5.72M
vi2

147

80.9k

+
vo2
-

Fig. 220-09

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 11

Simplified Output-Stage Circuit


VCC
ro13
Q14
vout

Q19
Q18

Q20
Q23

Req2
Q14

rd19

Req3

RL

rd18

RL=2k

Ri3
Q23

VEE

Fig. 220-06

Finding the Loading of the Output Stage on the Second Stage:


Assume a nominal load resistance of RL = 2k and that Q14 is supplying a 2mA
current to this load. Further assume that Q20 is conducting very little current at this point
in time.
NVt
Req2 = r14 + (N14 +1)RL = 505.3k
r14 = IC14 = 3.25k (IC14 2mA)
Req3 Req2||ro13A=177.1k
ro13A = VAP/IC13A = 50V/180A = 272.7k
PVt
r23 = I
= 7.1k
Ri3 = r23 + (P + 1)Req3 = 9.04M
C13A
ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 12

Output-Stage Circuit - Continued


The effective load on the second stage is therefore
RLoad2 = Ri3||Ro2 = 80.15k
Av2 = Gm2RLoad2= 544.2 54.7dB
AvT = Av1Av2= (565.1)(544.4)= 307,700 109.8dB
Equivalent Circuit for Calculation of the Output
Resistance:
Ro2 + r23A
Req4 =ro13A||[rd19 + rd18 +
( +1) ]= 2.00k
Req4 + r14
Rout =
+1 = 21
Routtotal = 21 + 27 = 48
Voltage gain:
Assume the voltage gain is 1.

ro13

Req4
Q14
vout

rd19
rd18

Rout

Q23
Ro2=83k
Fig. 220-07

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 13

Small-Signal Equivalent Circuit for the Complete 741 Op Amp


Ro2 = 47
+
vid
-

Rid
2.7M

+
vi2
-

Ro1

vid

6.8M

5.4k

Ri2
5.7M

+
vi3
-

Ro2

vi2

83k

147

Ri3
9.1M

vout
-

vi3

Fig. 220-08

Voltage gain = 109.8dB


Differential input resistance = 2.72M
Output resistance = 48

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 14

741 Circuit for SPICE Simulation


21
3

Q9

VCC
23

Q8

Q13A

17

Q14

Q13B
Q19

Q12
1

Q2

Q1
4

R5

39k

Cc

VCC

Q23B

VCC
14

24

Q7

Q10

Q11

26

R4
5k

20

Q23A
Q21

19

Q16

vout

R7
27

15

Q4

18

R6
27

Q18

40k

Q3

16
R10

Q15

Q20

Q5

Q6

12

9
10

Q22

11

R3
R1
R2
1k 50k 1k

R9
50k

22 VEE
ECE 6412 - Analog Integrated Circuit Design - II

Q17
13

R8
100

25

Q24

50k
Fig. 210-09
P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 15

Spice Simulations of the 741 Op Amp


uA741 Operational Amp Spice File
** 741 OP AMP **
* BIAS CIRCUIT *
Q12 23 23 21 PNP
Q11 24 24 22 NPN
Q10 6 24 26 NPN
Q13A 17 23 21 PNP 1
Q13B 14 23 21 PNP 3
Q15 17 18 20 NPN
Q21 25 19 20 PNP
Q22 8 25 22 NPN
Q24 25 25 22 NPN
Q23B 22 14 8 PNP
R5 23 24 39K
R4 26 22 5K
R11 25 22 50K
CC 14 8 30PF
*
* DIFF AMP *
Q1 3 1 4 NPN
Q2 3 2 5 NPN
Q3 7 6 4 PNP
Q4 8 6 5 PNP
Q5 7 9 10 NPN
Q6 8 9 11 NPN
Q7 21 7 9 NPN
Q8 3 3 21 PNP
Q9 6 3 21 PNP
R1 10 22 1K
R2 11 22 1K
R3 9 22 50K
ECE 6412 - Analog Integrated Circuit Design - II
Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

* DARLINGTON **
Q16 21 8 12 NPN
Q17 14 12 13 NPN
R9 12 22 50K
R8 13 22 100
* OUTPUT STAGE *
Q19 17 17 16 NPN
Q18 17 16 15 NPN
Q23A 22 14 15 PNP
Q14 21 17 18 NPN 3
Q20 22 15 19 SPNP
R10 16 15 40K
R6 18 20 27
R7 20 19 22
* POWER SUPPLY *
VCC 21 0 DC=15
VEE 22 0 DC=-15
*
** ANALYSIS **
*DC Sweep to find input offset voltage
*Connect output to inverting input for unity gain buffer
*Rshort 20 2 0.001
*VIN+ 1 0 DC 0 AC 0
*.DC VIN+ -15V +15V .1V
* Now provide input offset voltage
*VIN- 2 0 DC=851.325UV AC=0
*Open Loop Gain
*Remove Rshort
*VIN+ 1 0 AC=1
*VIN- 2 0 DC=851.325UV AC=0
*.AC DEC 20 1 10MEG
P.E. Allen - 2002
Page 220 - 16

SPICE File - Continued


*.TF V(20) VIN+
*Slew Rate - Connect output (node 20 to node 2 with +Rshort)
*VIN+ 1 0 PULSE (0 1 10us .001us .001us 10us 30us)
*.TRAN .5us 30us
*
.MODEL NPN NPN(IS=5E-15 RB=200 RC=250 BF=250 +BR=2 RE=2 VA=130 TF=.35NS CJE=1PF PE=.7V ME=.33
+CJC=.3PF PC=.55V MC=.5 CCS=3PF PS=.52 MS=.5V)
*
.MODEL PNP PNP(IS=2E-15 RB=300 RC=300 RE=10 +BF=50 BR=4 VA=50 TF=30NS CJE=.3PF PE=.55V ME=.5
+CJC=2PF PC=.55V MC=.5 CCS=3PF PS=.52V MS=.5V)
.MODEL SPNP PNP(IS=1E-14 RB=150 RC=50 RE=2 +BR=4 BF=50 VA=50 TF=20NS CJE=.5PF PE=.55V ME=.5
+CJC=2PF PC=.52V MC=.5 CCS=3PF PS=.52V MS=.5V)
*
.OPTIONS LIMPTS=0
.PROBE
.END

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 17

Node Voltages
****

SMALL SIGNAL BIAS SOLUTION

NODE
( 1)
( 6)
(11)
(16)
(21)
(26)

VOLTAGE
0.0000
-1.1088
-14.9920
0.0454
15.0000
-14.9020

NODE
( 2)
( 7)
(12)
(17)
(22)

TEMPERATURE = 27.000 DEG C

VOLTAGE
851.3E-06
-13.8950
-14.0460
0.6180
-15.0000

NODE
( 3)
( 8)
(13)
(18)
(23)

VOLTAGE
14.4120
-13.4680
-14.7480
0.0079
14.3030

NODE
(4)
( 9)
(14)
(19)
(24)

****

VOLTAGE
-0.5442
-14.4460
-1.3208
-0.0064
-14.3330

ECE 6412 - Analog Integrated Circuit Design - II

NODE
( 5)
( 10)
(15)
(20)
(25)

VOLTAGE
-0.5437
-14.9920
-0.6239
-5.094E-06
-15.0000

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 18

Bipolar Junction Transistors


NAME
MODEL
IB
IC
VBE
VBC
VCE
BETADC
GM
RPI
RX
RO
CBE
CBC
CJS
BETAAC
FT/FT2

Q1
NPN
3.44E-08
7.63E-06
5.44E-01
-1.44E+01
1.50E+01
2.22E+02
2.95E-04
7.53E+05
2.00E+02
1.89E+07
1.59E-12
5.75E-14
5.60E-13
2.22E+02
2.85E+07

Q2
NPN
3.48E-08
7.73E-06
5.45E-01
-1.44E+01
1.50E+01
2.22E+02
2.99E-04
7.43E+05
2.00E+02
1.87E+07
1.59E-12
5.75E-14
5.60E-13
2.22E+02
2.88E+07

Q3
PNP
-1.20E-07
-7.55E-06
-5.65E-01
1.28E+01
-1.34E+01
6.28E+01
2.92E-04
2.15E+05
3.00E+02
8.32E+06
9.40E-12
4.06E-13
5.70E-13
6.28E+01
4.73E+06

Q4
PNP
-1.23E-07
-7.65E-06
-5.65E-01
1.24E+01
-1.29E+01
6.24E+01
2.95E-04
2.11E+05
3.00E+02
8.16E+06
9.52E-12
4.13E-13
5.78E-13
6.23E+01
4.74E+06

Q5
NPN
3.74E-08
7.50E-06
5.46E-01
-5.51E-01
1.10E+00
2.01E+02
2.90E-04
6.92E+05
2.00E+02
1.74E+07
1.59E-12
2.12E-13
4.31E-11
201.00
2.5600e+07

NAME
MODEL
IC

Q6
NPN
7.52E-06

Q7
NPN
1.11E-05

Q8
PNP
-1.48E-05

Q9
PNP
-1.93E-05

Q16
NPN
3.04E-05

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 19

Bipolar Junction Transistors - Continued


NAME
MODEL
IB
IC
VBE
VBC
VCE
BETADC
GM
RPI
RX
NAME
MODEL
IC
VBE

Q12
PNP
-1.34E-05
-6.70E-04
-6.97E-01
0.00E+00
-6.97E-01
4.98E+01
2.59E-02
1.92E+03
3.00E+02

Q11
NPN
3.66E-06
7.31E-04
6.67E-01
0.00E+00
6.67E-01
2.00E+02
2.82E-02
7.07E+03
2.00E+02

Q17
NPN
2.51E-03
7.02E-01

Q19
NPN
2.06E-05
5.73E-01

Q10
NPN
8.88E-08
1.96E-05
5.69E-01
-1.32E+01
1.38E+01
2.20E+02
7.57E-04
2.91E+05
2.00E+02
Q18
NPN
7.91E-04
6.69E-01

Q13A
PNP
-1.28E-05
-8.13E-04
-6.97E-01
1.37E+01
-1.44E+01
6.34E+01
3.14E-02
2.02E+03
3.00E+02

Q23A
PNP
-8.04E-04
-6.97E-01

Q14
NPN
2.90E-04
6.10E-01

ECE 6412 - Analog Integrated Circuit Design - II

Q13B
PNP
-3.8200e-05
-2.50E-03
-0.69700
1.56E+01
0.0000
0.0000
0.096500
677.00
100.00
Q20
SNPN
-2.87E-04
6.10E-01

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 20

741 PSPICE SIMULATION RESULTS


Open Loop Voltage Gain (Magnitude and Phase)
180 d
100 d
( 667.9 47K,6 2.1 01)

0d
SEL>>
- 90d

( 2.584 5M,- 66 4.282 m )


18 0+VP( 20)

10 0

50
( 2.5 845M,-16.1
0
1.0Hz
10Hz
vdb ( 20)

( 6 67.94 7K,-65.52 0m )
1 00Hz

1.0KHz

10KHz

100KHz

1.0MHz

Frequency

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002

Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

Page 220 - 21

Closed Loop Step Response

1. 0V

I nput
0. 5V
Out put

0V

- 0. 4V
0s
V( 1)

5us
V( 20)

10us

ECE 6412 - Analog Integrated Circuit Design - II


Lecture 220 AC Analysis of the 741 Op Amp (2/25/02)

15us

20us

25us

30us

Ti me

P.E. Allen - 2002


Page 220 - 22

SUMMARY
The 741 is a classic Op Amp that exemplifies many of our ECE 6412 circuit concepts
The PSpice voltage gain is lower than for hand calculations due to more complete
model parameters
The gain bandwidth product for the 741 is approximately 1 MHz
The first 741 was designed, laid out, and fabricated by engineers without computers or
calculators and has stood the test of time

ECE 6412 - Analog Integrated Circuit Design - II

P.E. Allen - 2002