VLSI-II | Field Programmable Gate Array | Digital Signal Processing



M. Tech- II Semester Specialization: VLSID/VLSISD COURSE STRUCTURE

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Name of the Subject 1. Algorithms for VLSI Design Automation 2. Low Power VLSI Design 3. DSP Processors & Architecture 4. Design of Fault Tolerant Systems

L 4 4 4 4 4

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C 8 8 8 8 8

INT 40 40 40 40 40

EXT TOTAL 60 60 60 60 60 100 100 100 100 100

Elective III 1. Embedded and Real Time Systems 2.System Modeling & Simulation Elective IV 1.CPLD and FPGA Architecture and Applications 2. Advanced Microcontrollers and Processors Laboratory Mixed Signal Simulation Laboratory 4 4 40 60 100 4 8 40 60 100

UNIT VII PHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies. Simulated Annealing. Local Search. Tabu search. Algorithmic Graph Theory.Physical Design cycle for FPGA’s partitioning and Routing for segmented and staggered models. Computational Complexity. Placement – Chip array based and full custom approaches. Assignment and Scheduling. Concepts and Algorithms UNIT IV MODELLING AND SIMULATION: Gate Level Modelling and Simulation. Two – Level Logic Sysnthesis. Design Automation tools. High – level Transformations. Some aqspects of Assignment problem. Dynamic Programming. MCM physical design cycle. Internal representation of the input algorithm. Tractable and Intractable Problems UNIT II GENERAL PURPOSE MTHODS FOR COMBINATIONAL OPTIMIZATION: Backtracking. Multiple stage routing. routing and programmable MCM’s. Some Scheduling Algorithms. Switch level modeling and simulation UNIT V LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology. UNIT VI HIGH LEVEL SYNTHESIS: Hardware Models. Integer Linear Programming. Routing – Maze routing. UNIT VIII PHYSICAL DESIGN AUTOMATION OF MCM’S: MCM technologies.ALGORITHMS FOR VLSI DESIGN AUTOMATION UNIT I PRELIMINARIES: Introduction to Design Methodologies. Placement. Partitioning. Branch and Bound. Allocation. Topologic routing. Floorplanning and Routing Problems. Genetic Algorithms. UNIT III Layout Compaction. Integrated Pin – Distribution and routing. Binary – Decision diagram. .

1999.Gerez. 3rd edition.Ltd. 1998 .TEXT BOOKS: 1.H. Naveed Sherwani. John wiley & Sons (Asia) Pvt. Algorithms for VLSI Physical Design Automation. 2005 REFERENCES: 1. Wiley. Computer Aided Logical Design with Emphasis on VLSI – Hill & Peterson. Modern VLSI Design: Systems on silicon – Wavne Wolf. Springer International Edition. Algorithms for VLSI Design Automation. S. WILEY student edition. 2. Pearson Education Asia. 2nd Edition. 1993 2.

SOI CMOS. Performance evaluation UNIT VII LOW. UNIT III LOW-VOLTAGE/LOW POWER CMOS/ BICMOS PROCESSES: Deep submicron processes .LOW POWER VLSI DESIGN UNIT I LOW POWER DESIGN. limitations. future trends and directions of CMOS/BiCMOS processes. CMOS/BiCMOS ULSI low voltage. lateral BJT on SOI.voltage low power design. MOSFET in a Hybridmode environment. Integration and Isolation considerations.VOLTAGE LOW POWER LOGIC CIRCUITS: Comparison of advanced BiCMOS Digital circuits. UNIT VIII LOW POWER LATCHES AND FLIP FLOPS: Evolution of Latches and Flip flops-quality measures for latches and Flip flops. limitations of MOSFET models. Digital circuit operation and comparative Evaluation. TEXT BOOKS 1. Integrated Analog/Digital CMOS Process. AN OVER VIEW: Introduction to low. Silicon-on-Insulator. ESD-free Bi CMOS . low power by Yeo Rofail/ Gohl(3 Authors)-Pearson Education Asia 1st Indian reprint.2002 . UNIT II MOS/BiCMOS PROCESSES : Bi CMOS processes. UNIT IV DEVICE BEHAVIOR AND MODELING: Advanced MOSFET models. Design perspective. Bipolar models. UNIT V Analytical and Experimental characterization of sub-half micron MOS devices. UNIT VI CMOS AND Bi-CMOS LOGIC GATES: Conventional CMOS and BiCMOS logic gates.

REFERENCES 1. Parhi.Rabaey PH. Digital Integrated circuits . N. 2003 (chapter 17) 4. IEEE J. VLSI DSP systems .J 1996 2. John Wiley & sons. IEEE Trans Electron Devices. . and other National and International Conferences and Symposia. CMOS Digital ICs sung-moKang and yusuf leblebici 3rd edition TMH2003(chapter 11) 3. J.Solid State Circuits.

DSP using MATLAB. Interlocking. UNIT V PROGRAMMABLE DIGITAL SIGNAL PROCESSORS Commercial Digital signal-processing Devices. A/D Conversion errors. On-Chip Peripherals. PID Controller. A Digital signal-processing system. Program Control. UNIT VII IMPLEMENTATION OF FFT ALGORITHMS . Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). DSP Computational errors. Interrupt effects. Interpolation Filters. Branching effects. DSP Computational Building Blocks. Bus Architecture and Memory. Relative Branch support. Data Addressing modes of TMS320C54XX Processors. Memory space of TMS320C54XX Processors. Interrupts. Data Addressing modes of TMS320C54XX DSPs. Decimation Filters. FIR Filters.DSP PROCESSORS AND ARCHITECTURES UNIT I INTRODUCTION TO DIGITAL SIGNAL PROCESING Introduction. Analysis and Design tool for DSP Systems MATLAB. Pipeline Depth. Address Generation Unit. UNIT III ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES Basic Architectural features. Pipelining and Performance. Features for External interfacing. The sampling process. Linear time-invariant systems. Digital filters. Adaptive Filters. Stacks. Data Addressing Capabilities. 2-D Signal Processing. UNIT II COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS Number formats for signals and coefficients in DSP systems. UNIT IV EXECUTION CONTROL AND PIPELINING Hardware looping. Compensating filter. Decimation and interpolation. Pipeline Programming models. TMS320C54XX instructions and Programming. Dynamic Range and Precision. UNIT VI IMPLEMENTATIONS OF BASIC DSP ALGORITHMS The Q-notation. Sources of error in DSP implementations. Interrupts of TMS320C54XX processors. Discrete time sequences. IIR Filters. Pipeline Operation of TMS320C54XX Processors. Speed Issues. D/A Conversion Errors. Programmability and Program Execution.

2. Architecture. Interrupts and I/O. 2000. 2.An FFT Algorithm for DFT Computation. An 8-Point FFT implementation on the TMS320C54XX. REFERENCES 1. 2004. UNIT VIII INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES Memory space organization. 2004. Venkata Ramani and M. John Wiley. a CODEC interface circuit. Chand & Co. Srinivasan. . A Butterfly Computation. Digital Signal Processors. Overflow and scaling. Digital Signal Processing – Avtar Singh and S. TMH. Bhaskar. 2005. McBSP Programming. DSP Processor Fundamentals. Programmed I/O. A Multichannel buffered serial port (McBSP). Thomson Publications. Digital Signal Processing – Jonatham Stein. Architectures & Features – Lapsley et al. External bus interfacing signals. Memory interface. Computation of the signal spectrum. Programming and Applications – B. Parallel I/O interface. CODEC programming. Bit-Reversed index generation. Direct memory access (DMA). TEXT BOOKS 1. S. A CODEC-DSP interface example.

dynamic. use of control and syndrome testable design. Use of error correcting code. Parag K. Triple Modular Redundant System. LFSR as Signature analyzer. Pseudorandom testing. TEXT BOOKS: 1. Storage cells for scan design. Generic offline BIST architecture. Siftout redundancy (SMR). UNIT VII DESIGN FOR TESTABILITY FOR SEQUENTIAL CIRCUITS: Controllability and observability by means of scan register. UNIT III SELF CHECKING CIRCUITS: Basic concepts of Self checking circuits. Test pattern generation for BIST exhaustive testing. Berger code. UNIT II FAULT TOLERANT DESIGN: Basic concepts – Static. Level Sensitive Scan Design (LSSD). Relation between reliability and Meantime between failure. UNIT IV FAIL SAFE DESIGN: Strongly fault secure circuits. UNIT VI Theory and operation of LFSR. Lala – “Fault Tolerant & Fault Testable Hardware Design” (PHI) . controllability and observability. hybrid. Failure & Faults. Low cost residue code. constant weight patterns. classic scan design. totally self-checking PLA design. Time redundancy and software redundancy. UNIT VIII BUILT IN SELF TEST: BIST concepts. Maintainability and Availability. fail-safe design of sequential circuits using partition theory and Berger code. Checkers using m out of n codes.DESIGN OF FAULT TOLERANT SYSTEMS UNIT I BASIC CONCEPTS: Reliability concepts. Design of Totally Self Checking checker. Reliability and failure rate. SMR Configuration. Self purging redundancy. Parallel and Parallel-Series combinational circuits. pseudo exhaustive testing. Multiple-input Signature Register. UNIT V DESIGN FOR TESTABILITY FOR COMBINATIONAL CIRCUITS: Basic concepts of testability. the Reed Muller’s expansion technique. OR-AND-OR design. Reliability of series.

M. Abramovili. Friedman – “Digital Systems Testing and Testable Design” Jaico publications. D. A. Breues. M.2.A. .

Design technology.EMBEDDED AND REAL TIME SYSTEMS UNIT I: INTRODUCTION Embedded systems over view. RS232/UART. program state machine model(PSM.11. Tasks and task scheduler. interrupt service routines. UNIT II: GENERAL PURPOSE PROCESSORS Basic architecture. Trade-offs. Reuse of intellectual property codes. programmer’s view. Blue tooth. operations. Mutex. parallel evolution of compilation and synthesis. Ethernet. Logic synthesis. Automation. RT synthesis. custom purpose processor design(RT -level). Infrared. development environment.using state machines. Message Queues. UNIT V: EMBEDDED/RTOS CONCEPTS-I Architecture of the Kernel. Behavioral Synthesis. Pipes-Signals. communication among processes. synchronization among processes. finite state machines with data path model(FSMD). Synthesis.USB. IEEE 802. IEEE1394 Firewire. Semaphores. UNIT III: STATE MACHINE AND CONCURRENT PROCESS MODELS Introduction. optimizing custom single purpose processors. concurrent process model. design challenges. Application specific Instruction –Set processors (ASIPs)-Micro controllers and Digital signal processsors. UNIT VI: EMBEDDED/RTOS CONCEPTS-II Mailboxes. models Vs Languages. UNIT VII: EMBEDDED/RTOS OCNCEPTS-III Timers-Memory Management-Priority inversion problem-embedded operating systemsEmbedded Linux-Real-time operating systems-RT Linux-Handheld operating systemsWindows CE. concurrent processes. UNIT IV: COMMUNICATION PROCESSES Need for communication interfaces. RS422/RS485. data flow model. UNIT VIII: DESIGN TECHNOLOGY Introduction. real-time systems. Implementation. sequential logic(RTlevel). processor technology. Hardware/Software co-simulation. Systems Synthesis and Hard ware/Software Co-Design. Single purpose processors RT-level combinational logic. . Verification. Event Registers.

TEXT BOOKS 1.Thomson *** . REFERENCE BOOKS 1. 2. Tony D. pearson Ed. John Wiley & Sons.2005 Books/Cole.KVKK prased.David E. Embedded/Real Time Systems. Embedded Microcomputer Systems-Jonathan W. An Embedded Software Primer.Givargis.Frank Vahid. Introduction to Embedded Systems . 2.Embedded System Design-A Unified Hardware/Software Introduction.Simon. 3.Raj Kamal.2002. Inc. Dreamtech press-2005. Leaarning.Valvano. TMS-2002.

Object Oriented Simulation. Poisson processes. Linear Systems. the exponential distribution. Queing theory. UNIT V EXOGENOUS SIGNALS AND EVENTS: Disturbance signals. Discrete Time Markov processes. multidimensional optimization. simulating queing systems. Extend and others. UNIT II SIMULATION SOFTWARE: Comparison of simulation packages with Programming Languages. delays. UNIT VI MARKOV PROCESS Probabilistic systems. UNIT III BUILDING SIMULATION MODELS: Guidelines for determining levels of model detail. Alpha/beta trackers. Discrete Event Simulation. state machines. UNIT VII EVEN DRIVEN MODELS: Simulation diagrams. Models and Simulation. Simulation of Inventory System. Systems. modeling and simulation methodology. Techniques for increasing model validity and credibility. Types of Queues. UNIT VIII SYSTEM OPTIMIZATION: System identification. Classification of Software.SYSTEM MODELLING & SIMULATION UNIT I Basic Simulation Modeling. Examples of application oriented simulation packages. Alternative approach to modeling and simulation. Multiple servers. Desirable Software features. . General purpose simulation packages – Arena. System encapsulation. Searches. System Integration. Continuous – Time Markov processes. petri nets & analysis. Simulation of Single server queing system. Motion Control models. numerical experimentation. Random walks. simulating a poison process. UNIT IV MODELING TIME DRIVEN SYSTEMS: Modeling input signals.

2001. John Wiley&Sons.David Kelton.Severance. PHI. W. TMH. 2.Law. 3rd Edition. 2003 REFERENCE BOOKS: Systems Simulation – Geoffery Gordon. 1978 . Simulation Modeling and Analysis – Averill M.TEXT BOOKS: 1. System Modeling & Simulation. An introduction – Frank L.

UNIT. State Transition Table . design flow.VI Design Methods: One –hot design method. PLA. Programming. routing architecture. technology mapping for FPGAs. Cypress FLASH 370 Device technology. Finite State Machine-Case study. FPGA – Features. UNIT-V FSM Architectures: Architectures Centered around non registered PLDs.CPLD AND FPGA ARCHITECTURE AND APPLICATIONS (ELECTIVE IV) UNIT –I Programmable logic Devices: ROM. Lattice pLSI’s architectures – 3000 series – Speed performance and in system programmability. Meta Stability. encoded state machine. Use of ASMs in one-hot design method. Architectures. State assignments for FPGAs. Case studies Xilinx XC4000 & ALTERA’s FLEX 8000/10000 FPGAs: AT &T ORCA’s (Optimized Reconfigurable Cell Array): ACTEL’s ACT-1. CPLD. PAL. Synchronization. UNIT-II CPLDs: Complex Programmable Logic Devices: Altera series – Max 5000/7000 series and Altera FLEX logic-10000 series CPLD. AMD’s. Petrinets for state machines-Basic concepts and properties. One_Hot state machine.Logic blocks.3 and their speed performance UNIT-IV Finite State Machines (FSM): Top Down Design. linked state machine. Complex design using shift registers.CPLD (Mach 1 to 5). Extended Petri-nets for parallel controllers. Realization of state machine charts using PAL. Alternative realization for state machine charts using microprogramming. Applications of onehot design method. UNIT – III FPGAs: Field Programmable Gate Arrays.2. Design of state machines centered around shift registers. Applications and Implementation of MSI circuits using Programmable logic Devices. .

Field programmable gate array. parallel controllers. BSP. 2nd Edition. UNIT .TINDER. multiplexers. Trimberger. Digital Design Using Field Programmable Gate Array. 3. Edr.G. Academic press.Rose . 1994. P. 2. System level design using mentor graphics EDA tool (FPGA Advantage).Vranesic. R. Brown.K. Design flow using CPLDs and FPGAs. Mourad. Field Programmable Gate Array Technology . Engineering Digital Design . J. Roth.Chan & S. Fundamentals of logic design-Charles H. data path designing.S.VIII Case studies: Design considerations using CPLDs and FPGAs of parallel adder cell.Francis. 2007. .J. counters. REFERENCES: 1. 1994. Kluwer Academic Publications. S.UNIT-VII System Level Design: Controller. Prentice Hall. Functional partition. Digital front end digital design tools for FPGAs & ASICs.Z. parallel adder sequential circuits. 2.RICHARD F. TEXT BOOKS: 1. 4th Edition Jaico Publishing House.

the students are required to perform the following aspects using necessary software tools. Layout Extraction for Analog & Mixed Signal Circuits.MIXED SIGNAL SIMULATION LABORATORY By considering suitable complexity Mixed-Signal application based circuits (circuits consisting of both analog and digital parts). ***** . Mixed Signal Simulation Using Mixed Signal Simulators. • • • • • • • • Analog Circuits Simulation using Spice Software. Layout Vs Schematic. Parasitic Values Estimation from Layout. Digital Circuits Simulation using Xilinx Software. Design Rule Checks. Net List Extraction.

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