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S3C6410 Circuit Design Guide Rev1.00

S3C6410 Circuit Design Guide Rev1.00

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Published by: Dron_Gus on May 29, 2012
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04/10/2015

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Input Clock (X-tal or ExtCLK)

EXTCLK

XTIpll

XTOpll

EXTCLK

XTIpll

XTOpll

External
OSC

a) X-TAL Oscillation (OM[0]=0)

b) External Clock Source (OM[0]=1)

CEXT

CEXT

VDD_SYS

Rfed

Figure 3_8) Input Clock Example

Usual Conditions for A/MPLL & Clock Generator

PLL & Clock Generator generally uses the following conditions.

Loop filter capacitance

CLF

Need not Loop Filter
Capacitance

External X-tal frequency

-

10 – 20 MHz

External capacitance used for X-tal

CEXT

15 – 22 pF

Feedback resistor between XXTI
with XXTO

Rfed

1M Ohm

The output frequencies of APLL/MPLL can be calculated using the following equations:

FOUT = MDIV X FIN / (PDIV X 2SDIV
)

MDIV: 64 ≤ MDIV ≤ 1023

PDIV: 1 ≤ PDIV ≤ 63

SDIV: 0 ≤ SDIV ≤ 5

FVCO =(MDIV X FIN / PDIV): 800MHz ≤ FVCO ≤ 1600MHz

27

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

FIN : 10MHz ≤ FIN ≤ 20MHz

Don’t set the value P and M to all zeros

FOUT = MDIV X FIN / (PDIV X 2SDIV
)

NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.

FIN (MHz)

Target FOUT (MHz)

MDIV

PDIV

SDIV

12

100

400

3

4

12

200

400

3

3

12

266

266

3

2

12

400

400

3

2

12

533

266

3

1

12

667

333

3

1

Usual Conditions for EPLL & Clock Generator

PLL & Clock Generator generally uses the following conditions.

Loop filter capacitance

CLF

XpllEFILTER: 1.8nF

External X-tal frequency

-

10 – 20 MHz

External capacitance used for X-tal

CEXT

15 – 22 pF

The output frequencies of EPLL can be calculated using the following equations:

FOUT = (MDIV + KDIV / 216

) X FIN / (PDIV X 2SDIV
)

where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :

MDIV: 16 ≤ MDIV ≤ 255

PDIV: 1 ≤ PDIV ≤ 63

KDIV: 0 ≤ KDIV ≤ 65535

SDIV: 0 ≤ SDIV ≤ 4

FVCO (= (MDIV + KDIV / 216

) X FIN / PDIV) : 300MHz ≤ FVCO ≤ 600MHz

FOUT : 20MHz ≤ FOUT ≤ 600MHz

FIN : 10MHz ≤ FIN ≤ 20MHz

Don’t set the value P and M to all zeros

NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.

28

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

EPLL Value (P, M, S)

FIN (MHz)

FOUT (MHz)

MDIV

PDIV

SDIV

KDIV

12

36

48

1

4

0

12

48

32

1

3

0

12

60

40

1

3

0

12

72

48

1

3

0

12

84

28

1

2

0

12

96

32

1

2

0

12

32.768

43

1

4

45264

12

45.158

30

1

3

6903

12

49.152

32

1

3

50332

12

67.738

45

1

2

10398

12

73.728

49

1

3

9961

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