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S3C6410 Circuit Design Guide Rev1.00

S3C6410 Circuit Design Guide Rev1.00

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Sections

  • 1. Overview
  • 1.1 S3C6410 Pin Description
  • 1.2 Pin Power Domain
  • 1.3 Booting Option
  • 1.4 Feature of the IROM Boot mode
  • 1.5 Recommend Operating Conditions
  • 1.6 Difference of S3C6410 and S3C6400
  • 2. MEMORY MAP
  • 2.1 Maximum Address range of the Memory Port0
  • 2.2 Maximum Address range of the Memory Port1
  • 3. Syscon
  • 3.1 Power
  • 3.1.1 Power On Sequence
  • 3.1.2 Power Off Sequence
  • 3.1.3 Power Scheme Diagram
  • 3.1.4 Circuit Guide for DVS Scheme
  • 3.2 Clock
  • 3.2.1 PLL
  • 3.3 Reset
  • 3.3.1 HardWare Reset
  • 4. MEMORY SUBSYSTEM
  • 5. DRAM Controller
  • 5.1 Memory Port0
  • 5.2 Memory Port1
  • 5.3 DRAM Initialize Sequence
  • 5.4 PCB LAYOUT GUIDELINES FOR DDR
  • 6. SROM Controller
  • 6.1 Address Connection
  • 6.2 SRAM/ROM Interface Examples
  • 7. OneNAND Controller
  • 7.1 Overview
  • 7.2 Signal Description
  • 7.3 Circuit Diagram Example
  • 7.4 Caution
  • 8. NAND Flash
  • 8.1 Interface for Multi Chip Select NAND
  • 9. CF Controller
  • 9.1 CF Interface
  • 9.2 Cautions
  • 9.3 ATA 2 Slot operation guide
  • 10. GPIO
  • 11. DMA Controller
  • 12. VECTORED INTERRUPT CONTROLLER
  • 13. SECURITY SUB-SYSTEM
  • 14. DISPLAY CONTROLLER
  • 15. POST PROCESSOR
  • 16. TV SCALER
  • 17. TV ENCODER
  • 18. GRAPHICS 2D
  • 19. IMAGE ROTATOR
  • 20. CAMERA INTERFACE
  • 20.1 CAMIF INPUT
  • 20.2 Signal Description
  • 21. MULTI-FORMAT VIDEO CODEC
  • 22. JPEG CODEC
  • 23. MODEM INTERFACE
  • 23.1 Pin Description
  • 23.2 Pin Connection Example
  • 23.3 Caution
  • 24. HOST INTERFACE
  • 25. USB Host
  • 25.1 Power Domain
  • 25.2 Circuit Diagram Example
  • 25.3 USB Host connection
  • 25.4 Caution
  • 26. USB 2.0 HS OTG
  • 26.1 Power Domain
  • 26.2 Circuit Diagram Example
  • 26.3 USB PLL Specification
  • 26.4 USB SIGNAL ROUTING
  • 27. SD/MMC HOST CONTROLLER
  • 28. MIPI HSI INTERFACE CONTROLLER
  • 29. SPI
  • 30. IIC-BUS INTERFACE
  • 30.1 Pin Description
  • 30.2 Equation of the pull-up resistor value
  • 31. UART
  • 32. PWM TIMER
  • 33. RTC
  • 34. WATCHDOG TIMER
  • 35. AC97 CONTROLLER
  • 35.1 AC97 Signal Description
  • 35.2 Audio Ports
  • 35.3 Signal Description
  • 36. IIS BUS CONTROLLER
  • 36.1 Signal Description
  • 36.2 Audio Port
  • 36.3 External Clock Source
  • 36.4 Connection Example
  • 37. PCM BUS CONTROLLER
  • 37.1 Signal Description
  • 37.2. Audio Port
  • 37.3 External Clock Source
  • 37.4 Connection Example
  • 38. IRDA CONTROLLER
  • 39. ADC&TOUCH SCREEN INTERFACE
  • 40. KEYPAD INTERFACE
  • 41. IIS MULTI AUDIO INTERFACE
  • 41.1 Signal Description
  • 41.2 Audio Ports
  • 41.3 External Clock Source
  • 41.4 Connection Example
  • 42. GRAPHIC 3D

Circuit Design Guide

S3C6410X
RISC Microprocessor July 18, 2008 REV 1.00

Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. . S3C6410X RISC Microprocessor Circuit Design Guide, Revision 1.00 Copyright © 2008-2008 Samsung Electronics Co.,Ltd. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea 446-711 "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product

Home Page: http://www.samsungsemi.com/ E-Mail: mobilesol.cs@samsung.com Printed in the Republic of Korea

2

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

Revision History
Revision No 0.00 1.00 Description of Change - Initial Release for review - Public Release Refer to Author(s) W.J.JANG H.M.NOH Date June 2, 2008 July 18, 2008

3

................ 21 3..4 PCB LAYOUT GUIDELINES FOR DDR ................................................2 Power Off Sequence . 6 1......... 66 20............................................. 65 19...................................3 DRAM Initialize Sequence.................................................................................................................................................................................................................................................................................... 33 5.......................... DISPLAY CONTROLLER .............................................................................. 41 7.............1............................2 Cautions..................1 S3C6410 Pin Description ................................................................................................................................................................................................................................................................................... POST PROCESSOR........................................................................5 Recommend Operating Conditions ................................. 30 5............................................................. 20 2................................................................................2 Pin Power Domain ...................... 31 5....... 41 7....1 Power............................... 48 11......................................................................... 43 9............................................................... 27 3.................................................................. 20 3............................................................................................................................................................................................ GRAPHICS 2D ....................................................3 ATA 2 Slot operation guide.......... CAMERA INTERFACE...... 16 1...................... 17 1..............................................................................................4 Feature of the IROM Boot mode .........................6 Difference of S3C6410 and S3C6400 ..... 18 2...............................4 Circuit Guide for DVS Scheme ...... SECURITY SUB-SYSTEM.................................................... MEMORY SUBSYSTEM ...................................................................................................................................................1 PLL ............................. IMAGE ROTATOR .............................................................................. VECTORED INTERRUPT CONTROLLER....................... 57 15......2 Signal Description..................................... 25 3..........................................................................1 Interface for Multi Chip Select NAND ...................................................2 Memory Port1 ......................... 39 6.......................................................................................................................................1 Overview........................................................................................................ TV SCALER ......................................................................... 14 1..................................................................................................................................................................................................................................................................................... 21 3...................1...........3.............. 62 17.......................................................................... 44 9..................................... TV ENCODER....................... SROM Controller ...............................................................................................1 Maximum Address range of the Memory Port0..........................................................................................................4 Caution ...................................................................................................................................................................................................................................................................... CF Controller ..................... 39 6........................... MEMORY MAP ....................................................................................S3C6410_CIRCUIT DESIGN GUIDE REV 1... 26 3..... GPIO.............................1 CF Interface ........................................ 31 5................ 21 3...................... 29 4.................. 43 8................1 Address Connection ..................................................................................................................... 31 5.................................................................................................................................................... 54 12..... 56 14.................................................................................................................................................. 46 10.................. 63 18...1 Power On Sequence .............. 15 1........ 55 13.......... 45 9.............. Overview... 29 3...................................1 Memory Port0 ............................................................ NAND Flash .......................................................................................... 36 6.......... 44 9............................................................................................................................ 41 7..............................3 Booting Option ............................................................................................1 HardWare Reset................2 Maximum Address range of the Memory Port1....................... 6 1.................... DRAM Controller .....................................................................................................2 SRAM/ROM Interface Examples ....2 Clock..................................... OneNAND Controller............................................................................................... 24 3..................................................................2........................................................................................................... 41 7........................................................................................................................................................... 67 4 ..............................3 Power Scheme Diagram.................................................................................................................................................................................................................. 27 3........................................... 61 16........3 Circuit Diagram Example.................3 Reset ............00 Table of Contents 1........................ 20 2................................................1....................................................................................................................1........................................................................................................... 39 7................................................................................. 42 8............................................................................ Syscon.......... DMA Controller......................................................................................................................

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

20.1 CAMIF INPUT............................................................................................................................... 67 20.2 Signal Description......................................................................................................................... 67 21. MULTI-FORMAT VIDEO CODEC........................................................................................................... 69 22. JPEG CODEC ......................................................................................................................................... 70 23. MODEM INTERFACE ............................................................................................................................. 71 23.1 Pin Description ............................................................................................................................. 71 23.2 Pin Connection Example .............................................................................................................. 72 23.3 Caution ......................................................................................................................................... 72 24. HOST INTERFACE ................................................................................................................................. 73 25. USB Host................................................................................................................................................. 74 25.1 Power Domain .............................................................................................................................. 74 25.2 Circuit Diagram Example.............................................................................................................. 74 25.3 USB Host connection ................................................................................................................... 74 25.4 Caution ......................................................................................................................................... 74 26. USB 2.0 HS OTG .................................................................................................................................... 75 26.1 Power Domain .............................................................................................................................. 75 26.2 Circuit Diagram Example.............................................................................................................. 75 26.3 USB PLL Specification ................................................................................................................. 77 26.4 USB SIGNAL ROUTING .............................................................................................................. 77 27. SD/MMC HOST CONTROLLER ............................................................................................................. 79 28. MIPI HSI INTERFACE CONTROLLER................................................................................................... 82 29. SPI........................................................................................................................................................... 83 30. IIC-BUS INTERFACE.............................................................................................................................. 84 30.1 Pin Description ............................................................................................................................. 84 30.2 Equation of the pull-up resistor value ........................................................................................... 84 31. UART....................................................................................................................................................... 85 32. PWM TIMER ........................................................................................................................................... 86 33. RTC ......................................................................................................................................................... 87 34. WATCHDOG TIMER............................................................................................................................... 88 35. AC97 CONTROLLER.............................................................................................................................. 89 35.1 AC97 Signal Description............................................................................................................... 89 35.2 Audio Ports ................................................................................................................................... 89 35.3 Signal Description......................................................................................................................... 89 36. IIS BUS CONTROLLER .......................................................................................................................... 90 36.1 Signal Description......................................................................................................................... 90 36.2 Audio Port ..................................................................................................................................... 90 36.3 External Clock Source .................................................................................................................. 90 36.4 Connection Example .................................................................................................................... 90 37. PCM BUS CONTROLLER ...................................................................................................................... 92 37.1 Signal Description......................................................................................................................... 92 37.2. Audio Port .................................................................................................................................... 92 37.3 External Clock Source .................................................................................................................. 92 37.4 Connection Example .................................................................................................................... 93 38. IRDA CONTROLLER .............................................................................................................................. 94 39. ADC&TOUCH SCREEN INTERFACE .................................................................................................... 95 40. KEYPAD INTERFACE ............................................................................................................................ 96 41. IIS MULTI AUDIO INTERFACE .............................................................................................................. 97 41.1 Signal Description......................................................................................................................... 97 41.2 Audio Ports ................................................................................................................................... 97 41.3 External Clock Source .................................................................................................................. 98 41.4 Connection Example .................................................................................................................... 98 42. GRAPHIC 3D .......................................................................................................................................... 99

5

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

1. Overview
1.1 S3C6410 Pin Description
Check Items Signal Used Recommendations Unused Check

Shared Memory Port 0 (SROMC/OneNAND/NAND/ATA) Xm0BEn[1:0] Xm0CSn[5:0] GPO[5:4] Xm0ADDR[19:0] Xm0OEn Xm0WEn Xm0ADRVALID Xm0SMCLK Xm0DATA[15:0] Xm0WAITn Connect to Byte Enable of External device. Connect to Chip Select of External device. * Xm0CSn3 is not used for SROMC at OneNAND/Modem Boot Mode Using as GPIO Connect to Address lines of External device. Connect to Output Enable of External device. Connect to Write Enable of External device. Connect to Address Valid pin of OneNAND Connect to OneNAND Clock Connect to Data lines of External device. Connect to Wait signal of External device. 4.7Kohm pull-up resistor required. Connect to OneNAND Bank0 Ready Xm0RDY0_ALE Connect to NAND Flash or External device Address Latch Enable Connect to OneNAND Bank1 Ready Xm0RDY1_CLE Connect to NAND Flash or External device Command Latch Enable Connect to OneNAND Bank0 Interrupt Connect to NAND Flash Write Enable Connect to OneNAND Bank1 Interrupt Connect to NAND Flash Read Enable Connect to OneNAND Reset. Xm0RPn_RnB GPQ[6:2] Xm0INTata Xm0RESETata Connect to NAND Flash Ready/Busy. 4.7Kohm pull-up resistor required. Use as GPIO Connect to Interrupt Request pin of CF Socket (Indirect Path) Connect to CF Card Reset pin(Indirect Path) Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect

Xm0INTsm0_FWEn

Leave as a No Connect

Xm0INTsm1_FREn

Leave as a No Connect

6

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

Xm0INPACKata Xm0REGata Xm0WEata Xm0OEata Xm0CData

Connect to Input Ack pin of CF Socket(Indirect Path) Connect to REG pin of CF Socket(Indirect Path) Connect to Write Enable pin of CF Socket(Indirect Path) Connect to Read Enable pin of CF Socket(Indirect Path) Connect to Card Detect pin of CF Socket Pull-up resistor is required(Indirect Path).

Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect

Shared Memory Port 1 (SROMC/DRAM1) Xm1CKE[1:0] Xm1SCLK, Xm1SCLKn Xm1CSn[1:0] Xm1ADDR[15:0] Xm1RASn Xm1CASn Xm1WEn Xm1DATA[31:0] Xm1DQM[3:0] Xm1DQS[3:0] Connect to DRAM Clock Enable Connect to DRAM Clock Connect to Chip Select of DRAM. Connect to Address and bank select of DRAM. Connect to DRAM Row Address Strobe. Connect to DRAM Column Address Strobe. Connect to DRAM Write Enable Connect to Data lines of External device. Connect to DRAM Data Mask. Connect to DRAM Data Strobe UART/IrDA/CF XuRXD[1:0] XuTXD[1:0] XuCTSn[1:0] XuRTSn[1:0] Connect to UART Rx Data Lines Connect to UART Tx Data Lines Connect to UART Clear To Send signal Connect to UART Request To Send signal Connect to UART Rx Data Line. XuRXD[2] Connect to IrDA Rx Data Line. Connect to External DMA Request Line. Connect to Address[0] of the ATA device. Connect to UART Tx Data Line. XuTXD[2] Connect to IrDA Tx Data Line. Connect to External DMA Ack Line. Connect to Address[1] of the ATA device. XuRXD[3] Connect to UART Rx Data Line. Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect

7

10Kohm pull-up resistor to VDD_MMC is required Connect to IIS 5. Connect to IIC device Data 1Kohm pull-up resistor required.00 Connect to IrDA Rx Data Line. Connect to IIS 5. Connect to IrDA Tx Data Line. Connect to UART Tx Data Line.1CH CODEC Data Output XspiCS[1] Connect to SPI device Chip Select Connect to IIS 5. Connect to External DMA Request Line. 1Kohm pull-up resistor required Connect to Address[2] of the ATA device.1CH CODEC Data Output XspiMOSI[1] Connect to SPI device SPIMOSI Connect to SPI device Clock XspiCLK[1] Connect to MMC2 Card Clock. Connect to IIC device Data 1Kohm pull-up resistor is required SPI XspiMISO[0] XspiMOSI[0] XspiCLK[0] XspiCS[0] Connect to SPI device SPIMISO Connect to SPI device SPIMOSI Connect to SPI device Clock Connect to SPI device Chip Select Connect to SPI device SPIMISO XspiMISO[1] Connect to MMC2 Card Command. If necessary. Connect to IrDA transceiver control signal CF_Data_DIR/ XirSDBW Connect to Camera Field signal.1CH CODEC Data Output PCM/IIS/AC97 Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect 8 . XuTXD[3] Connect to External DMA Ack Line. Connect to IIC device Clock. use to control the Data Buffer Direction for ATA device IIC Bus Xi2cSCL Xi2cSDA Connect to IIC device Clock 1Kohm pull-up resistor is required.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

Connect like left column in order to supply 48MHz clock for other IPs (USB Host. HSMMC.1%) resistor to GND 9 . SPI) Connect to GND Connect like left column in order to supply 48MHz clock for other IPs (USB Host. XusbXTI Connect to 1M Ohm resistor between XusbXTI and XusbXTO (case of using Crystal) Connect to Crystal/Oscillator XO signal XusbXTO Connect to 1M Ohm resistor between XusbXTI and XusbXTO(case of using Crystal) XusbREXT Connect to External 44. XusbDP XusbDM Connect to USB Data pin DATA(+) Connect to USB Data pin DATA(-) Connect to Crystal XI signal if using Crystal. HSMMC. USB OTG Connect 15Kohm series resistor to GND.00 Connect to PCM Serial Shift Clock XpcmDCLK[1:0] Connect to IIS CODEC Serial Clock Connect to AC97 Bit Clock Connect to PCM reference clock(optional) XpcmEXTCLK[1:0] Leave as a No Connect Connect to IIS CODEC System Clock Connect to AC97 Codec H/W Reset pin Connect to PCM Sync indicating start of word. SPI) Leave as a No Connect Connect like left column in order to supply 48MHz clock for other IPs (USB Host. Connect to GND if using Oscillator. Connect to USB Hot Data plus .S3C6410_CIRCUIT DESIGN GUIDE REV 1. 15Kohm Pull-down resistor is required. Leave as a No Connect XpcmFSYNC[1:0] Connect to IIS CODEC channel Clock Connect to AC97 Codec SYNC pin Connect to PCM Serial Data Input Leave as a No Connect XpcmSIN[1:0] Connect to IIS CODEC Data Input Connect to AC97 CODEC Data Input pin Connect to PCM Serial Data Output Leave as a No Connect XpcmSOUT[1:0] Connect to IIS CODEC Data Output Connect to AC97 CODEC Data Output pin USB Host Leave as a No Connect XuhDN XuhDP Connect to USB Host Data Minus. Connect 15Kohm series resistor to GND. IrDA. HSMMC.2ohm(+/. 15Kohm Pull-down resistor is required. IrDA. IrDA. Leave as a No Connect Leave as a No Connect Connect to GND.

00 SPI) XusbVBUS XusbID Connect USB mini-receptacle VBUS Connect USB mini-receptacle Identifier Device Mode : leave as a no connect Connect to Drive Vbus for Off-Chip Charge Pump.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Device Mode : leave as a no connect External Interrupts XEINT[7:0] XEINT[15:8] Connect to External Device Connect to Row signals of Keypad Connect to External Device Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect XusbDRVVBUS Leave as a No Connect Host I/F / MIPI / Key I/F / ATA XhiCSn Connect to Chip Select that driven by Modem Connect to ATA Chip Enable0 Strobe Connect to Chip Select for LCD bypass main Connect to ATA Chip Enable1 Strobe Connect to Chip Select for LCD bypass sub Connect to ATA Read strobe for I/O Mode Connect to Write Enable that driven by Modem Connect to ATA Write strobe for I/O Mode Connect to Read Enable that driven by Modem Connect to ATA Wait signal Connect to Interrupt Request pin to the Modem Connect to CF Data DIR Connect to Address bus of Modem XhiADDR[7:0] Connect to Column signals of Keypad Connect to ATA Control Signal Connect to Address bus of Modem XhiADDR[12:8] Connect to ATA Control Signal Connect to Data bus of Modem XhiDATA[7:0] Connect to ATA Data[7:0] Connect to MIPI HIS I/F XhiDATA[15:8] Connect to Data bus of Modem Connect to Row signals of Keypad Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect XhiCSn_main Leave as a No Connect XhiCSn_sub Leave as a No Connect XhiWEn Leave as a No Connect XhiOEn Leave as a No Connect XhiINTR Leave as a No Connect 10 .

00 Connect to ATA Data[15:8] XhiDATA[17:16] Connect to Data bus for LCD bypass PWM XpwmECLK XpwmTOUT[1:0] Leave as a No Connect Connect to PWM Timer External Clock Input Connect to UART External Clock Input Connect to External Device Timer Output Camera Interface Leave as a No Connect Leave as a No Connect XciCLK XciHREF XciPCLK XciVSYNC XciRSTn XciYDATA[7:0] Connect to Camera Master Clock Connect to Camera Horizontal Synchronous Connect to Camera Pixel Clock Connect to Camera Vertical Synchronous Connect to Camera Software Reset Connect to Camera Pixel Data Lines Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect TFT LCD Display Interface XvVD[23:0] XvVCLK XvVSYNC XvHSYNC XvVDEN Connect to LCD Pixel Data Lines Connect to Pixel Clock signal Connect to Vertical synchronous signal Connect to Horizontal synchronous signal Connect to Data enable signal DAC XdacVREF XdacIREF XdacCOMP XdacOUT_0 XdacOUT_1 Connect 100nF capacitor to GND. Connect 100nF capacitor to VDDDAC. tie AIN [7] to VDDA_ADC or ADCTSC register must be setting to 0xd3. Connect 6.S3C6410_CIRCUIT DESIGN GUIDE REV 1.49Kohm resistor to GND. Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Leave as a No Connect Xadc_AIN[3:0] 11 . Leave as a No Connect Connect 100nF capacitor to GND. Connect to Video AMP Connect to Video AMP ADC Connect to Analog signal Xadc_AIN[7:4] Touch Panel Interface Connect to Analog signal PLL XpllEFILTER Connect 1.8nF capacitor to GND Leave as a No Connect If not use AIN[7]. Connect 100nF capacitor to VDDDAC.8nF capacitor to GND MMC Connect 1. Connect 6.49Kohm resistor to GND.

12 .00 XmmcCLK0 XmmcCMD0 Connect to MMC0 Card Clock.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Connect to 5M Ohm resistor between XrtcTI and XrtcTO Connect to crystal oscillator Connect to Reset Circuit or Reset Button Leave as a No Connect XrtcXTO XrtcXTO leave as a No Connect. Connect to Column Line of the Keypad Connect to MMC1 Card Command.1CH codec. XrtcXTI Pull-up resistor to VDD_RTC. 10Kohm pull-up resistor to VDD_MMC is required Connect to MMC0 or MMC1 Card Detect 10Kohm pull-up resistor is required. Connect to MMC0 Card Command. 10Kohm pull-up resistor to VDD_MMC Leave as a No Connect Leave as a No Connect XmmcDAT0[3:0] Leave as a No Connect XmmcCDN0 XmmcCLK1 Leave as a No Connect Leave as a No Connect XmmcCMD1 Leave as a No Connect XmmcDATA1[7:0] Connect to Column Line of the Keypad Connect to I2S 5. X27mXTI Connect to 1M Ohm resistor between X27mXTI and X27mXTO Connect to crystal oscillator Pull-up resistor to VDD_SYS X27mXTO XXTO Connect to 1M Ohm resistor between X27mXTI and X27mXTO Connect a 15~22pF capacitor from each Leave as a No Connect XXTO leave as a No Connect. Connect to ATA Address[2:0] Reset Leave as a No Connect XnRESET XnRSTOUT Connect to Reset Circuit or Reset Button Connect to External Device Reset Clock Connect a 13~22pF capacitor from each signal to GND. 10Kohm pull-up resistor to VDD_MMC is required Connect to Column Line of the Keypad Connect to MMC1 Card Data Lines. Connect to MMC1 Card Clock. Connect to 5M Ohm resistor between XrtcTI and XrtcTO Connect to crystal oscillator. 10Kohm pull-up resistor to VDD_MMC is required Connect to MMC0 Card Data Lines.

10Kohm pull-up resistor to VDD_SYS for SJF. JTAG Connect to JTAG Reset Port for Debugging.00 signal to GND. VDD_xPLL ) Connect to VDD_SYS or GND Connect to High. Connect to JTAG Data Input Port 10Kohm pull-dn resistor to GND for Core debugging. XXTI XEXTCLK Connect to 1M Ohm resistor between XXTI and XXTO Connect to External Clock Source(Oscillator). 10Kohm pull-dn resistor to GND Pull-up resistor to VDD_SYS Connect to VDD_SYS or GND. XSELNAND XnBATF XeffVDD WR_TEST 13 . 10Kohm pull-up resistor to VDD_SYS. 10Kohm pull-dn resistor to GND. 10Kohm pull-dn resistor to GND.(VDD_SYS) 10Kohm pull-dn resistor to GND Pull-up resistor to VDD_SYS 10Kohm pull-dn resistor to GND.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Connect to 1M Ohm resistor between XXTI and XXTO Connect to a crystal oscillator. MISC XOM[4:0] XPWRRGTON Connect to VDD_SYS or GND Connect to Regulator Enable Pin (VDD_ARM. Connect to Regulator Enable Pin (VDD_ARM. Connect to JTAG Mode Select Port. VDD_xPLL ) Connect to VDD_SYS for NAND Connect to GND for OneNAND Connect to Probe Signal for Battery State. 10Kohm pull-up resistor to VDD_SYS. Leave as a No Connect 10Kohm pull-up resistor to VDD_SYS. Connect 470ohm series resistor to nRESET XjTMS Connect to JTAG Mode Select Port. XjTRSTn 10Kohm pull-up resistor to VDD_SYS. 10Kohm pull-up resistor to VDD_SYS. VDD_INT. Connect to JTAG Return Clock Port Connect to JTAG Mode Select Port. VDD_INT. Leave as a No Connect Pull-up resistor to VDD_SYS Pull-dn resistor to GND XjTCK XjRTCK XjTDI XjTDO XjDBGSEL 10Kohm pull-dn resistor to GND.

XjTCK. XspiCLK[1]. XusbID. XdacOUT_0. Xm1CKE[1:0]. XjTMS. Xm0ADV. XciRSTn.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Xm0RDY1/CLE. XusbVBUS. XhiRQn XEINT[15:0]. Xm0INTsm1/FREn. XciPCLK. XXTO. XhiADDR[12:0]. Xm0WAITn. XciDATA[7:0]. XspiCLK[0].3V 3. Xm1RASn.3V 3. Xm0OEn. XusbREXT. Xm1WEn.0V 1. Xm1DQS[3:0] XuRXD[3:0].3V VDDPCM 1.8V~3. Xm0Cdata. SciCLK. Xm0REGata. XmmcCLK[1:0]. Xm0SMCLK. XpcmSOUT[1:0] 1. XpwmTOUT[1:0] XspiMISO[1]. Xm1DATA[31:0]. XmmcDATA1[7:0] XpcmDCLK[1:0]. XdacCOMP XuhDN. XjTRSTn. Xm1SCLKn. XuRTSn[1:0]. XdacOUT_1. Xm0INTATA. Xm0CSn[5:0]. XOM[4:0].3V VDDMMC 1. XjDBGSEL. XuTXD[3:0].3V XvVD[23:0].8V~3. Power VDDRTC VDDMEM0 VDDSS VDDMEM1 Voltage 1. XirSDBW. XpcmEXTCLK[1:0]. Xm1CASn. XSELNAND. XspiCS[0]. Xm1CSn[1:0]. XvVCLK VDDHI 1.3V 14 . XmmcCMD[1:0]. XhiWEn. XusbDRVVBUS VDDSYS VDDADC VDDDAC VDDUH VDDOTG 1.3V XrtcXTI. Xm0DATA[15:0]. XusbDM. Xm0RPn/RnB. XspiMISO[0].8V~2.8V~3. XnRESET. XuhDP XusbDP.8V~3. Xm0Wen. Xm0RDY0/ALE. XhiCSn. XciVSYNC. XjRTCK. Xm0INPACKata.2 Pin Power Domain User should obey the operating voltage range between External device and S3C6410 IP.3V VDD_LCD 1. XvHSYNC. XpcmFSYNC[1:0]. XjTDO. Xm0OEata. XuCTSn[1:0]. XhiCSn_sub. XmmcDATA0[3:0]. XmmcCDN0. XusbXTO. XsRSTOUTn. Xm0WEata. XjTDI. XusbXTI.3V XhiDATA[17:0].3V 1.8V~3. X27mXTI. XspiMOSI[0]. Xm0CData Xm1ADDR[15:0]. XnBATF. XspiCS[1]. Xm0RESETata.3V 3. XEXTCLK Xadc_AIN[7:0].8V~3.5V VDDEXT 1. Xm0BEn[1:0]. XciHREF. XdacVREF. XpwmECLK. XspiMOSI[1]. Xi2cSDA.8V~3. XPWRRGTON. XrtcXTO Xm0ADDR[19:0]. Xi2cSCL. XdacIREF. WR_TEST.00 1. XvVDEN.8V~3. XcVSYNC. XhiOEn.8V ~3. XXTI. XhiCSn_main. Xm1SCLK. Xm1DQM[3:0]. Xm0INTsm0/FWEn. GPQ[6:2] Xm0INTata. X27mXTO.3V 3. XpcmSIN[1:0].

3 Booting Option OM[4:0] pin should be tied with VDDSYS or GND. let’s we assume IROM boot and crystal □ OM[4:0] = b’11110 OM[4] OM[3] OM[2] OM[1] 0 0 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 Internal Boot Internal ROM OM[0] 0 1 0 1 Ext.00 1. Boot OneNAND EXT OSC EXT OSC EXT Internal ROM NOR(26bit) OM[4] OM[3] OM[2] SROM OM[1] OM[0] OSC EXT OSC EXT OSC Muxed OneNAND (XSELNAND pin must be “0”) MODEM SROM Operation Mode MODEM * IROM Boot loader of the S3C6410X support boot from various memory devices such as MoviNAND. But if you have to get an option. directly. MMC. Muxed OneNAND and NAND. you should add a pull-up and pull-down resistor with 100K ohms over. It is aimed for minimize leakage current when entering the sleep mode.S3C6410_CIRCUIT DESIGN GUIDE REV 1. It’s defined by OM[4:0] and GPN[15:13] 15 . For example.

But It can be changed to 8bit by BL1 3. For detail. GPN15 is toggled.4 Feature of the IROM Boot mode IROM Boot loader of the S3C6410X supports boot from various memory devices such as MoviNAND. Muxed OneNAND and NAND. NAND : Using S/W 8bit ECC at boot page 2. SDMMC(Channel1) is supported as 4bit. refer to “IROM Application Note” 16 . Don’t use GPN[15:13] as GPIO or EINT in IROM Boot. MMC. 4.00 1. When NAND uncorrectable ECC error is detected.S3C6410_CIRCUIT DESIGN GUIDE REV 1. It’s defined by OM[4:0] and GPN[15:13] Boot Device SDMMC(Channel 0) OneNAND Page Size 512 Address Cycle 3 4 4 5 5 - GPN1 5 0 0 0 0 1 1 1 1 GPN1 4 0 0 1 1 0 0 1 1 GPN1 3 0 1 0 1 0 1 0 1 OM[4:0] 5b’1111x (XOM[0]: Select Crystal or Oscillator) NAND 2048 4096 SDMMC(Channel1) - Note) 1.

8 / 2.3 1.8~3.0 3.3 3.00 1.7 Unit VDDMEM0 VDDSS VDDMEM1 VDDMMC/VDDHI/VD DLCD/VDDPCM/VDD EXT/VDDSYS VDDRTC VDDADC VDDDAC VDDOTG VDDOTGI VDDUH TA TA V DC Supply Voltage for I/O Block DC Supply Voltage for RTC DC Supply Voltage for ADC DC Supply Voltage for DAC DC Supply Voltage for USB OTG Phy 3.2 3.6 1.25 1.30 1.6 2.25 1.3 1.0 3.6 3.6 3.5 Recommend Operating Conditions Parameter DC Supply Voltage for Alive Block Symbol VDDALIVE VDDAPLL VDDMPLL VDDEPLL DC Supply Voltage for Core Block VDDINT VDDARM VDDARM VDDARM DC Supply Voltage for Memory Interface0 (NOR/NAND/OneNAND/ CF) DC Supply Voltage for ATA IO muxed in MEM0 port DC Supply Voltage for Memory Interface1 (DRAM) 533MHz 667MHz 800MHz Min 1.3 3.15 1.0 1.15 3.3 1.0 3.20 1.7 3.8 / 2.5/3.3 1.15 1.5 / 3.8 / 2.10 1.5 1.7 1.25 1.2 1.35 3.6 o o C C 17 .2 1.3V DC Supply Voltage for USB OTG Internal DC Supply Voltage for USB Host Operating Temperature 1.7 1.15 1.5/3.15 1.25 3.75 Typ 1.0 Industrial Extended 3.3 3.05 1.6 3.S3C6410_CIRCUIT DESIGN GUIDE REV 1.8 / 2.25 1.15 1.2 1.7 1.3 -40 to 85 0 to 70 Max 1.6 3.25 1.

2V 1. XrtcXTO) USBOTG(XotgTI.3V 1.4K Ohm 6.2V (Upto 634MHz) Not Available 1.0V 1. X27MXTO) RTC(XrtcXTI.2V 1.2V 1.1V 1. Signal Name XREXT XdacIREF S3C6410X 44.8V ~ 3.1V 2.2V 1.XotgTO) 1M Ohm 1M Ohm 5M Ohm 1M Ohm S3C6400X No need No need No need No need 3) The value of resistor on DAC and USB OTG is changed .0V S3C6400X 1.0V 1.49K Ohm S3C6400X 3. XXTO) 27MHz(X27MXTI.2 Ohm 6.2V 1.S3C6410_CIRCUIT DESIGN GUIDE REV 1.The value of pull down resistor is changed.6 Difference of S3C6410 and S3C6400 1) Typical Voltage of the S3C6410 Symbol 533MHz VDDARM 667MHz 800MHz VDDINT VDDALIVE VDDxPLL VDDOTGI VDDRTC 133MHz S3C6410X 1.1V 1.24K Ohm 4) SROM Address Bus Width (In case of using the x32 data bus width in memory port1) Address Bus Width S3C6410X 20 bit S3C6400X 16 bit 18 .5V 2) The Feedback resistors should be inserted between XTAL Input and Output pad S3C6410X Main Clock (XXTI.00 1.0V 1.

19 .S3C6410_CIRCUIT DESIGN GUIDE REV 1. please refer to Pin Description Document.00 5) DRAM Interface in Memory Port 0 DRAM I/F S3C6410X Not support S3C6400X SDR/mSDR/mDDR 16 bit 6) GPIO Muxing Function IIC IIS 5-Ch Camera Interlace Mode S3C6410X 2-Ch Support Support S3C6400X 1-Ch Not support Not support For detail.

MEMORY MAP 2. 0 OneNAND Ctrl. OneNAND Ctrl. The decision is made by System Controller.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Refer to Memory sub-system chapter for details. This address range can be assigned to both SROM controller and OneNAND controller. ROM SROM Ctrl.00 2. In case of OneNAND boot mode. Size 1MB 128MB 2. 1 DRAM Ctrl 1 O - 1 O - 1 O O - 1 O 2 O O O O O O 2 2 O 2 O O - 1 2 Refer to Memory sub-system chapter(Refer to User’s manual) for details.2 Maximum Address range of the Memory Port1 1) 16bit Data Bus Width DRAM : 1Gb / Chip Select 2) 32bit Data Bus Width DRAM : 2Gb / Chip Select Start Address 0x00000000 0x08000000 0x0C000000 0x10000000 0x18000000 0x20000000 0x28000000 0x30000000 0x38000000 0x40000000 0x48000000 0x50000000 0x60000000 End Address 0x07FFFFFF 0x0BFFFFFF 0x0FFFFFFF 0x17FFFFFF 0x1FFFFFFF 0x27FFFFFF 0x2FFFFFFF 0x37FFFFFF 0x3FFFFFFF 0x47FFFFFF 0x4FFFFFFF 0x5FFFFFFF 0x6FFFFFFF Int. It is not used for SROM controller. 20 .1 Maximum Address range of the Memory Port0 Data pin [26:16] of memory port 1 can be used as Address pin [26:16] of memory port 0 by configuration from system controller (MEM_SYS_CFG[7]) Address Range of the SROMC Memory Port 1: 32bit Bus width DRAM Memory Port 1: 16bit Bus width DRAM Address Width 20bit 27bit Max.

tRST2RUN .. tOR nRESET PLL is configured by S/W Clock Disable tPLL VCO is adapted to new clock frequency ... FCLK is new frequency .00 3. Figure 3_1) Power on sequence Note) OSC’s frequency should be meet the specification which is 10Mhz ~ 20Mhz 21 .1 Power On Sequence tOA VDD_IO tAE VDDALIVE tAI After VDD_IO & VDDALIVE are turned on. XPWRRGTON is always HIGH XPWRRGTON HIGH is possible in this area XPWRRGTON VDDINT/ARM/PLL XTIpll or EXTCLK tOSC .. VCO output . It can operate PLL .S3C6410_CIRCUIT DESIGN GUIDE REV 1. FCLK MCU operates by XTIpll or EXTCLK clcok . Syscon 3..1 Power 3..1.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. Figure 3_3) XTI Clock Timing 22 . Figure 3_2) Sleep Mode Return Oscillation Setting Timing tXTALCYC 1/2 VDD_SYS 1/2 VDD_SYS NOTE: The clock input from the XTIpll pin.00 EXTCLK XTIpll W ake up from sleep mode Clock Disable tOSC2 VCO Output Several slow clock cycles (XTIpll or EXTCLK) FCLK Sleep mode is initiated.

3V ± 0.3V. (2) Symbol tOA tAI tAE tOSC tOR tEXTHIGH tEX2HC tHC2CK tHC2SCLK tRESW tPLL tOSC2 tRST2RUN Min 0 1 1 10 1 25 5 4 2 4 24 5 Typ Max Unit ms us 10 ns cycle us 10 10 8 300 300 216 - ns ns ns ns XTIpll or EXTCLK us us XTIpll or EXTCLK XTIpll or EXTCLK The interval before CPU runs after nRESET is released. 1. TA = -40 to 85°C. 23 . Figure 3_4) XEXTCLK Input Timing Clock Timing Constants (VDDINT= 1.15V) Parameter VDDpadIO to VDDalive VDDalive to VDDi/VDDarm VDDarm to PWR_EN(PWRRGTON) VDDLOGIC/VDDarm to Oscillator stabilization Oscillator stabilization to nRESET & nTRST high External clock input high level pulse width External clock to HCLK (without PLL) HCLK (internal) to CLKOUT HCLK (internal) to SCLK Reset assert time after clock stabilization APLL&MPLL Lock Time EPLL Lock Time Sleep mode return oscillation setting time. 2.25V.5V ± 0.2V± 0.00 tEXTCYC tEXTHIGH tEXTLOW 1/2 VDD_SYS VIH VIH 1/2 VDD_SYS VIL VIL NOTE: The clock input from the EXTCLK pin.05V.S3C6410_CIRCUIT DESIGN GUIDE REV 1. VDDSYS = 3.8V ± 0.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.2 Power Off Sequence Figure 3_5) Power off sequence Symbol tloa tloi Description VDDIO/VDDMEM to VDDALIVE VDDIO/VDDMEM to VDDINT/VDDARM Min 0 0 TYP Max Units ms ms 24 .1.00 3.

1.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 3.3 Power Scheme Diagram Figure 3_6) Power Scheme Diagram Note 1) VDDxPLL can use same power source with VDDINT 25 .

VDDINT voltage using feedback resister.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Figure 3_7) Example of the Power Scheme Diagram 26 . User can control the VDDARM. The following diagram describes 2 step DVS application circuit.4 Circuit Guide for DVS Scheme VDDARM and VDDINT are depended by operating frequency.1.00 3. Recommended circuit guide is that used Voltage Controlled regulator for VDDARM and VDDINT.

1 PLL Input Clock (X-tal or ExtCLK) E X T C L K E x te rn a l O S C V D D _ S Y S E X T C L K C E X T X T Ip ll R fe d X T Ip ll C E X T X T O p ll X T O p ll a ) X -T A L O s c illa tio n (O M [0 ]= 0 ) b ) E x te r n a l C lo c k S o u r c e (O M [0 ]= 1 ) Figure 3_8) Input Clock Example Usual Conditions for A/MPLL & Clock Generator PLL & Clock Generator generally uses the following conditions.00 3.S3C6410_CIRCUIT DESIGN GUIDE REV 1.2.2 Clock 3. Loop filter capacitance External X-tal frequency External capacitance used for X-tal Feedback resistor between XXTI with XXTO CLF CEXT Rfed Need not Loop Filter Capacitance 10 – 20 MHz 15 – 22 pF 1M Ohm The output frequencies of APLL/MPLL can be calculated using the following equations: FOUT = MDIV X FIN / (PDIV X 2SDIV) MDIV: 64 ≤ MDIV ≤ 1023 PDIV: 1 ≤ PDIV ≤ 63 SDIV: 0 ≤ SDIV ≤ 5 FVCO =(MDIV X FIN / PDIV): 800MHz ≤ FVCO ≤ 1600MHz 27 .

SDIV for APLL and MPLL must meet the following conditions : MDIV: 16 ≤ MDIV ≤ 255 PDIV: 1 ≤ PDIV ≤ 63 KDIV: 0 ≤ KDIV ≤ 65535 SDIV: 0 ≤ SDIV ≤ 4 FVCO (= (MDIV + KDIV / 216) X FIN / PDIV) : 300MHz ≤ FVCO ≤ 600MHz FOUT : 20MHz ≤ FOUT ≤ 600MHz FIN : 10MHz ≤ FIN ≤ 20MHz Don’t set the value P and M to all zeros NOTE: Although there is the equation for choosing PLL value. FIN (MHz) 12 12 12 12 12 12 Target FOUT (MHz) 100 200 266 400 533 667 MDIV 400 400 266 400 266 333 PDIV 3 3 3 3 3 3 SDIV 4 3 2 2 1 1 Usual Conditions for EPLL & Clock Generator PLL & Clock Generator generally uses the following conditions. Loop filter capacitance External X-tal frequency External capacitance used for X-tal CLF CEXT XpllEFILTER: 1. we strongly recommend only the values in the PLL value recommendation table. please contact us. If you have to use other values.S3C6410_CIRCUIT DESIGN GUIDE REV 1. please contact us. PDIV. MDIV. we strongly recommend only the values in the PLL value recommendation table.00 FIN : 10MHz ≤ FIN ≤ 20MHz Don’t set the value P and M to all zeros FOUT = MDIV X FIN / (PDIV X 2SDIV) NOTE: Although there is the equation for choosing PLL value. 28 .8nF 10 – 20 MHz 15 – 22 pF The output frequencies of EPLL can be calculated using the following equations: FOUT = (MDIV + KDIV / 216) X FIN / (PDIV X 2SDIV) where. If you have to use other values.

Caution: An external power source. XnRSTOUT pin is asserted when XnRESET is asserted. All pins get their reset state. M.3 Reset 3.728 MDIV 48 32 40 48 28 32 43 30 32 45 49 PDIV 1 1 1 1 1 1 1 1 1 1 1 SDIV 4 3 3 3 2 2 4 3 3 2 3 KDIV 0 0 0 0 0 0 45264 6903 50332 10398 9961 3. • • • All internal registers and ARM1176 core go to the pre-defined reset states. 29 .152 67. Otherwise. S) FIN (MHz) 12 12 12 12 12 12 12 12 12 12 12 FOUT (MHz) 36 48 60 72 84 96 32.738 73. regulator. During this period. the following actions occur. it damages to S3C6410X and its operation will not be guaranteed.768 45.158 49.3.1 HardWare Reset The hardware reset is invoked when XnRESET pin is asserted and all units in the system (except RTC) are reset to known states.S3C6410_CIRCUIT DESIGN GUIDE REV 1. for S3C6410X must be stable prior to the deassertion of XnRESET.00 EPLL Value (P.

typ:1.6V. NOR.typ:1. DDR x32 mSDR. OneNAND (OneNAND Booting: Xm0nCS2 and Xm0nCS3 can’t support SROMC at OneNAND/Modem booting mode) Xm0nCS[5:4] : SRAM.1 USAGE OF THE MEMORY PORT0 & MEMORY PORT1 Memory Port0 Op. CF If use x32 DRAM in Memory Port1. Memory Port0 use only Xm0ADDR[19:0] Memory Port1 VDD_MEM1(1. Voltage Device VDD_MEM0(1.7V~3.8/2.5V/3. DDR Chip Select Xm1nCS0. MEMORY SUBSYSTEM 4. NAND. NOR. SDR. mDDR.75V~2. NOR ( NOR Booting : Xm0nCS0) Xm0nCS[3:2] : SRAM.8/2. Xm1nCS1 : DRAM Others Can’t be connected with x16 mSDR 16bit Data Bus: Default. NAND.3V) SRAM. CF I/F Xm0nCS[1:0] : SRAM.7V.5V) x16 mDDR.S3C6410_CIRCUIT DESIGN GUIDE REV 1. OneNAND. NOR. ADDR_EXPAND =”1” 32bit Data Bus: ADDR_EXPAND=”0” 30 .00 4.

8V 25pF@133MHz. MEM_SYS_CFG sfr) 3) Memory Interface Example 31 .2 Memory Port1 Addr. 2) To expand data bus. set ‘ADDR_EXPAND’ field to “0”(In SYSCON.1 Memory Port0 The Memory Port0 of the S3C6410 can’t support DRAM.S3C6410_CIRCUIT DESIGN GUIDE REV 1. 15pF@133MHz. when reset state.00 5.5V 1) Xm1DATA[26:16] are operating as address[26:16] of the memory port0. Connection (DDR/SDRAM) BA[1:0] addr for SDR/DDR Data Bus Width Bus Loading DRAM 16bit 32bit A0 A0 S3C6410X Xm1ADDR0 Xm1ADDR0 Xm1ADDR14 and Xm1ADDR15 fixed regardless of memory size Xm1DATA[26:16] are muxed with SROMC(Memory Port0) address[26:16] signal. 2. 5. 1. DRAM Controller 5.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. 32 . The SFR in DRAM Controller can change in Config and Low power state.00 Caution ) The state of the DRAM Controller can be controlled by DRAM Controller Command Register.

3 DRAM Initialize Sequence 33 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 5.

Program mem_cmd to ‘2’b10’ in direct_cmd. All of external DRAM should be executed memory device initialize sequence by “DIRECTCMD” Sfr MOBILE DDR SDRAM INITIALIZATION SEQUENCE Program mem_cmd in direct_cmd to ‘2’b10’.00 Caution) 1. Memory burst ( It must be matched the memory device). Program mem_cmd to ‘2’b10’ in direct_cmd. Read delay 3. Row/Column address 2) Memory type. Program mem_cmd in direct_cmd to ‘2’b11’. which makes DRAM Controller issue ‘Autorefresh’ memory command. Memory width.S3C6410_CIRCUIT DESIGN GUIDE REV 1. o Bank address for MRS must be set. Should be set to correct value to “Memory Configuration” and “Memory Configuration 2” Check Point : 1) Active chips. which makes DRAM Controller issue ‘Prechargeall’ memory command. 34 . The value of the SFRs should be changed in “Config” state of the DRAM Controller. which makes DRAM Controller issue ‘NOP’ memory command. AP bit. which makes DRAM Controller issue ‘MRS’ memory command o Bank address for EMRS must be set. 2. Program mem_cmd in direct_cmd to ‘2’b11’. which makes DRAM Controller issue ‘MRS’ memory command. Program mem_cmd in direct_cmd to ‘2’b00’. which makes DRAM Controller issue ‘Autorefresh’ memory command.

which makes DRAM Controller issue ‘MRS’ memory command o Bank address for EMRS must be set. Program mem_cmd in direct_cmd to ‘2’b11’. Program mem_cmd to ‘2’b10’ in direct_cmd. Program mem_cmd in direct_cmd to ‘2’b11’.S3C6410_CIRCUIT DESIGN GUIDE REV 1. which makes DRAM Controller issue ‘MRS’ memory command. which makes DRAM Controller issue ‘Prechargeall’ memory command. which makes DRAM Controller issue ‘NOP’ memory command. o Bank address for MRS must be set. Program mem_cmd to ‘2’b10’ in direct_cmd. Assert Reset DLL Program mem_cmd in direct_cmd to ‘2’b00’. o Bank address for MRS must be set. which makes DRAM Controller issue ‘MRS’ memory command.00 DDR1 SDRAM INITIALIZATION SEQUENCE Program mem_cmd in direct_cmd to ‘2’b10’. Enable DLL should be set. which makes DRAM Controller issue ‘Prechargeall’ memory command. Program mem_cmd in direct_cmd to ‘2’b00’. Program mem_cmd to ‘2’b10’ in direct_cmd. Deassert Reset DLL 35 . which makes DRAM Controller issue ‘Autorefresh’ memory command. which makes DRAM Controller issue ‘Autorefresh’ memory command.

00 5.5mm for equalizing timing skew.2 TRACE ROUTING GUIDE I. I. And the number of capacitors is as large as possible considering of PCB space. Ground layer has to be placed adjacent to signal layer for current return path. Data Group DQ [7:0] DQ [15:8] DQ[23:16] DQ[31:24] Mask Signal DQM0 DQM1 DQM2 DQM3 Clock DQS0 DQS1 DQS2 DQS3 36 . b) Connect to ground plane through ground via near ground pad of bypass capacitor as short as possible. impedance of the layer must be considered.4 PCB LAYOUT GUIDELINES FOR DDR 5.S3C6410_CIRCUIT DESIGN GUIDE REV 1. c) Join together ground pins adjacent each other for making lower impedance. IV. DQ.1 POWER AND GROUND DESIGN GUIDE General design rule is applied on this case. DQS signal Signals in same group have pattern length matched within 1. III. II. If signals in same group have to be routed on different layer. DQM. Connection of power pin a) Place bypass capacitor near power pin as short as possible. 5. b) Connect to power plane through power via near power pad of bypass capacitor as short as possible. Ground plane has not to be splitted. c) Pay attention whether power via makes ground plane splitted or not. Connection of ground pins a) Connect to ground plane through ground via near ground pin as short as possible.4.4. The value of bypass capacitor is determined by considering capacitance of PCB board.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. c) General design rules have to be kept according to know-how of PCB design engineer. III. DQM. resisters may be applied. AP signal These signals are routed separating with other signal groups. CSn. The adequate value of resister is not mentioned on this document. DQS} < {CSn. ADDR[13:0]. BA. AP} < {SCLK.00 II. BA[1:0]. RASn. CASn. WEn. Others a) If termination resister is required for EMI or signal integrity. IV. SCLK. {DQ. CKE. X O O O X 37 . SCLKn signal These clock signals must have differential impedance. SCLKn} The difference of pattern length between signal groups is around 10mm. shared signals have to be branched near AP side. WEn. ADDR. The length of clock signal is longer than signals in data signal group and control signal groups. RASn. CKE. CASn. b) If there is another device connected on MEM0.

3V/T2012 K4X51163PE-L(F)E/GC6 [2] Xm1ADDR[15:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 U22 J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3 H8 H9 F8 F2 E8 E2 G1 G2 G3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 LDM UDM LDQS UDQS CKE CK nCK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nCS nRAS nCAS nWE NC NC VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ Xm1DATA[31:0] [2] A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 H7 G9 G8 G7 F3 F7 A1 F1 K1 C1 E1 A3 B9 D9 [2] Xm1ADDR14 [2] Xm1ADDR15 Xm1DATA16 Xm1DATA17 Xm1DATA18 Xm1DATA19 Xm1DATA20 Xm1DATA21 Xm1DATA22 Xm1DATA23 Xm1DATA24 Xm1DATA25 Xm1DATA26 Xm1DATA27 Xm1DATA28 Xm1DATA29 Xm1DATA30 Xm1DATA31 !!SAME ROUTE LENGTH VDD_DMEM [2] [2] [2] [2] Xm1DQM2 Xm1DQM3 Xm1DQS2 Xm1DQS3 [2] Xm1CKE0 [2] Xm1SCLK [2] Xm1SCLKn Xm1CSn0 [2] Xm1RASn [2] Xm1CASn [2] Xm1WEn [2] CTB30 CB69 CB70 CB71 CB72 CB73 CB74 + A9 F9 K9 C9 E9 A7 B1 D1 100nF 100nF 100nF 100nF 100nF 100nF 10uF/6.3V/T2012 K4X51163PE-L(F)E/GC6 Figure 5_1) Memory port 1 interface example 38 .00 [2] Xm1ADDR[15:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12 [2] Xm1ADDR14 [2] Xm1ADDR15 [2] [2] [2] [2] Xm1DQM0 Xm1DQM1 Xm1DQS0 Xm1DQS1 U20 J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3 H8 H9 F8 F2 E8 E2 G1 G2 G3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 BA0 BA1 LDM UDM LDQS UDQS CKE CK nCK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nCS nRAS nCAS nWE NC NC VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ Xm1DATA[31:0] [2] A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2 H7 G9 G8 G7 F3 F7 A1 F1 K1 C1 E1 A3 B9 D9 Xm1DATA0 Xm1DATA1 Xm1DATA2 Xm1DATA3 Xm1DATA4 Xm1DATA5 Xm1DATA6 Xm1DATA7 Xm1DATA8 Xm1DATA9 Xm1DATA10 Xm1DATA11 Xm1DATA12 Xm1DATA13 Xm1DATA14 Xm1DATA15 !!SAME ROUTE LENGTH VDD_DMEM [2] Xm1CKE0 [2] Xm1SCLK [2] Xm1SCLKn Xm1CSn0 [2] Xm1RASn [2] Xm1CASn [2] Xm1WEn [2] CTB28 + CB57 CB58 CB59 CB60 CB61 CB62 A9 F9 K9 C9 E9 A7 B1 D1 100nF 100nF 100nF 100nF 100nF 100nF 10uF/6.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

6. SROM Controller
6.1 Address Connection
SRAM/ROM Addr. connection 8bit data bus 16bit data bus A0 A0 S3C6410X Xm0ADDR0 Xm0ADDR1

6.2 SRAM/ROM Interface Examples

Figure 6_1) Memory Interface with 8-bit SRAM

39

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

Figure 6_2) Memory Interface with 16-bit SRAM Note. 1) The Xm0CSn3 can’t be used for SROM controller in OneNAND/Modem Boot mode.

40

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00

7. OneNAND Controller
7.1 Overview
S3C6410X supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory via shared memory port 0.

7.2 Signal Description

Signal Xm0DATA[15:0]

I/O IO

Description Xm0DATA[15:0] (Data Bus) outputs address during memory read/write address phase, inputs data during memory read data phase and outputs data during memory write data phase. Xm0CSn[3:2] (Chip Select) are activated when the address of a memory is within the address region of each bank. Xm0CSn[3:2] can be assigned to either SROMC or OneNAND controller by System Controller SFR setting. Active LOW. Xm0WEn (Write Enable) indicates that the current bus cycle is a write cycle. Active LOW. Xm0OEn (Output Enable) indicates that the current bus cycle is a read cycle. Active LOW. Interrupt inputs from OneNAND memory Bank 0, 1. If OneNAND memory is not used, these signals must be tied to zero. Address valid output. Active LOW. System reset output for OneNAND memory. Active LOW. Xm0RDY is a synchronous burst wait input that the external device uses to delay a synchronous burst transfer. Xm0RDY indicates data valid in synchronous read modes and is activated while Xm0CSn is low. Static memory clock for synchronous static memory devices. Must be less than 67MHz.

Xm0CSn[3:2]

O

Xm0WEn

O

Xm0OEn Xm0INTsm0_FWEn Xm0INTsm1_FREn Xm0ADDRVALID Xm0RPn_RnB Xm0RDY0_ALE Xm0RDY1_CLE Xm0SMCLK

O

I O O I

O

7.3 Circuit Diagram Example
Xm0CSn2 is used for OneNAND boot device. If you want OneNAND boot, Xm0CSn2 should be used for boot. Optionally you can use Xm0CSn3 for storage.

41

For detail.4 Caution • Each memory bank supports only Muxed OneNAND • To use OneNAND Flash. • OneNand signal power domain belongs to VDD_MEM0 42 . ‘XSELNAND’ pin must be connected to zero (Low level).00 Xm0DATA[15:0] Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15 D1 A3 A6 B1 C3 C4 B5 B2 C1 D6 D5 C2 C5 E3 B3 D3 A4 A5 ADQ0 ADQ1 ADQ2 ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 VSS0 VSS1 UM1 RDY INT nRP nAVD nOE nCE nWE CLK H1 G1 A2 F3 B4 E2 A1 E1 Xm0RDY 0_ALE Xm0INTsm0_FWEn Xm0RPn_RnB Xm0ADDRVALID Xm0OEn Xm0CSn2 Xm0WEn Xm0SMCLK VCCcore VCCIO B6 C6 C508 VDD_mem KFN2G16Q2M-DEB6 100nF Figure 7_1) Using only one OneNand Device Xm0DATA[15:0] Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15 D1 A3 A6 B1 C3 C4 B5 B2 C1 D6 D5 C2 C5 E3 B3 D3 A4 A5 ADQ0 ADQ1 ADQ2 ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 VSS0 VSS1 UM1 RDY INT nRP nAVD nOE nCE nWE CLK H1 G1 A2 F3 B4 E2 A1 E1 Xm0DATA[15:0] Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15 D1 A3 A6 B1 C3 C4 B5 B2 C1 D6 D5 C2 C5 E3 B3 D3 A4 A5 ADQ0 ADQ1 ADQ2 ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 VSS0 VSS1 UM2 RDY INT nRP nAVD nOE nCE nWE CLK H1 G1 A2 F3 B4 E2 A1 E1 Xm0RDY 1_CLE Xm0INTsm1_FREn Xm0RPn_RnB Xm0ADDRVALID Xm0OEn Xm0CSn3 Xm0WEn Xm0SMCLK Xm0RDY 0_ALE Xm0INTsm0_FWEn Xm0RPn_RnB Xm0ADDRVALID Xm0OEn Xm0CSn2 Xm0WEn Xm0SMCLK VCCcore VCCIO B6 C6 C508 VDD_mem VCCcore VCCIO B6 C6 C508 VDD_mem KFN2G16Q2M-DEB6 100nF KFN2G16Q2M-DEB6 100nF Figure 7_2) Using two OneNand Device 7. refer to Overview Chapter.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

Figure 8_1) 1-CE case and 2-CE case connection Figure 8_2) 4-CE case connection (1) Nand signal power domain belongs to VDD_MEM0. NAND Flash 8. so user should add external 4.S3C6410_CIRCUIT DESIGN GUIDE REV 1.7K pull-up resistor. you can use GPIO which have external 10K pull-up resistor because the GPIO default setting is input/pulldown. But large capacity NAND flash have two nCE signal.00 8. Confirm the voltage level another SRAM interface.1 Interface for Multi Chip Select NAND Xm0nCS2/Xm0nCS3 are used for nand device. If some nand flash have 4-CE device. 43 . (2) RnB signal have open-drain input.

(These two pins can be used as a control bit not only in UDMA mode but also in PC-CARD mode and PIO mode. Indirect mode Xm0CSn[4] Direct mode (UDMA mode only) XhiCSn XhiADR[8] XhiCSn_main Xm0CSn[5] XhiADR[9] Xm0REGata XhiADDR[6] Xm0OEata Xm0RESETata XhiADDR[4] Xm0WEata XhiCSn_sub XhiADR[10] XhiWEn XhiADR[11] XhiADDR[0]. XuTXD[2]. XmmcDATA1[6]. The other address line is connected to GND. XhiIRQn or XirSDBW. The Level shifter needs a direction control bit for data bus. If the IO voltage of external memory is not 3. CF Controller 9. The host(CF controller in S3C6410X) can control device through EBI in indirect mode. can be selected for a direction control bit.1 CF Interface There are two operational modes in CF Controller. XmmcDATA1[5] XhiADDR[2]. The one is an indirect mode and the other is a direct mode. a level shifter is required for data bus.) CF card or micro-drive can be connected directly to S3C6410X chip without being through memory port 0 in direct mode.00 9. XuRXD[3] O O I/O Description Card enable strobe PC card mode : lower byte enable strobe True-IDE mode : chip selection (nCS0) Card enable strobe PC card mode : higher byte enable strobe True-IDE mode : chip selection (nCS1) Register in CF card strobe PC card mode : It is used for accessing register in CF card True-IDE mode : DMA Acknowledge Output enable strobe PC card mode : output enable strobe for memory True-IDE mode : GND. There are multiplexed signals which refer to below table. Xm0ADDR[2] O 44 . Read strobe for I/O mode UDMA mode : host strobe Write strobe for I/O mode Xm0REGata O Xm0OEata O Xm0RESETata O Xm0WEata Xm0OEn Xm0WEn Xm0ADDR[0] O O O O Xm0ADDR[1] O CF card address PC card mode : full address use True-IDE mode : only ADDR[2:0] use. These operational modes can be selected by configuring INDEP_CF bit of MEM_SYS_CFG register(0x7E00F120) in System Controller. XuRXD[2]. direct mode column for direct mode. CF card reset PC card mode : active high True-IDE mode : active low Write enable strobe PC card mode : output enable strobe for memory True-IDE mode: VCC.S3C6410_CIRCUIT DESIGN GUIDE REV 1.3V. XmmcDATA1[4] XhiADDR[1]. Two pins.

UART. If user use 1.00 Xm0ADDR[10:3] Xm0DATA[15:0] Xm0CData XhiDATA[0] XhiDATA[1] XhiDATA[2] XhiDATA[3] XhiDATA[4] XhiDATA[5] XhiDATA[6] XhiDATA[7] XhiDATA[8] (XhiDATA[16]) XhiDATA[9] (XhiDATA[17]) XhiDATA[10](XhiCSn) XhiDATA[11] (XhiCSn_main) XhiDATA[12] (XhiCSn_sub) XhiDATA[13] (XhiWE) XhiDATA[14] (XhiOEn) XhiDATA[15](XhiIRQn) Xm0CData XhiADDR[7] Xm0INTata O B B B B B B B B B B B B B B B B I Card detect signals Interrupt request from CF card.S3C6410_CIRCUIT DESIGN GUIDE REV 1. 45 .8V NAND flash.2 Cautions (1) Check voltage domain of CF address and data. Xm0CSn5 = nCS_CF1 (3) If using CF device in direct mode. (2) S3C6410X has dedicated CF chip select signals as Xm0CSn4 = nCS_CF0. PC card mode : active low (memory mode : level triggering. because addr/data shared another SRAM interface. you cannot utilize some functions multiplexed with CF direct path such as Host I/F. you should add a level shifter. I/O mode : edge triggering) True-IDE mode : active high Wait signal from CF card UDMA mode : device strobe Input acknowledge in I/O mode PC card mode : not used True-IDE mode : DMA request CF data bus Xm0INTata XhiADDR[3] Xm0WAITn Xm0INPACKata XhiADR[12] XhiOEnI Xm0INPACKata XhiADDR[5] I I I 9. Keypads.

3 ATA 2 Slot operation guide (1) S3C6410X CF Controller can use CF card and HDD together by using 2slot operation (master and slave) (2) Follow Figure 9_2) using 2 slot schematic CF pin list A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 matched S3C6410X Signal XhiADDR[0] or XuRXD[2] or XmmcDAT1[4] XhiADDR[1] or XuTXD[2] or XmmcDAT1[5] XhiADDR[2] or XuRXD[3] or XmmcDAT1[6] XhiDATA[0] XhiDATA[1] XhiDATA[2] XhiDATA[3] XhiDATA[4] XhiDATA[5] XhiDATA[6] XhiDATA[7] XhiDATA[8] XhiDATA[9] XhiDATA[10] XhiDATA[11] CF pin list D12 D13 D14 D15 CS0 CS1 IORD IOWR IORDY INTRQ RESET nINPACK REG CData matched S3C6410X Signal XhiDATA[12] XhiDATA[13] XhiDATA[14] XhiDATA[15] XhiCSn or XhiADDR[8] XhiCSn_main or XhiADDR[9] XhiCSn_sub or XhiADDR[10] XhiWEn or XhiADDR[11] XhiOEn or XhiADDR[12] XhiADDR[3] XhiADDR[4] XhiADDR[5] XhiADDR[6] XhiADDR[7] 46 .00 VDD_CF 10K R1312 CON2 CE_CF0 CE_CF1 nIORD_CF nIOWR_CF IORDY _CF 7 32 34 35 42 1 37 38 39 40 41 24 43 44 45 46 9 13 33 36 26 25 8 10 11 D0 nCE1 D1 nCE2 D2 nIORD D3 nIOWR D4 nWAIT D5 GND1 D6 IREQ D7 VCC2 D8 nCSEL D9 nVS2/OPEN D10 RESET D11 WP D12 nINPACK D13 nREG D14 nSPKR D15 nSTSCHG GND2 nOE A7 VCC1 A6 nVS1/GND A5 nWE A4 CD1 A3 CD2 A2 A10 A1 A9 A0 A8 CompactFlash_1 21 22 23 2 3 4 5 6 47 48 49 27 28 29 30 31 50 12 14 15 16 17 18 19 20 P_DATA0 P_DATA1 P_DATA2 P_DATA3 P_DATA4 P_DATA5 P_DATA6 P_DATA7 P_DATA8 P_DATA9 P_DATA10 P_DATA11 P_DATA12 P_DATA13 P_DATA14 P_DATA15 B_ADDR7 B_ADDR6 B_ADDR5 B_ADDR4 B_ADDR3 P_ADDR2 P_ADDR1 P_ADDR0 P_DATA[15:0] VDD_CF B_RESET B_INTata R36 R37 10K 10K R1311 R38 R40 R41 0 10K 10K 10K B_INPACKata B_REGata B_OEata B_WEata CD1_CF CD2_CF B_ADDR[26:0] P_ADDR[2:0] B_ADDR10 B_ADDR9 B_ADDR8 B_ADDR[26:0] Figure 9_1) CF Connection Example 9.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

00 Figure 9_2) CF ATA 2 Slot Operation Schematic 47 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.

GPM and GPN ports. GPM[4:0] and GPN[15:0] ports. And registers in off-part register can keep their values by each GP(*)SLPCON and GP(*)PUDSLP register during sleep mode. Internal pull-up and pull-down register is about 50~100Kohm. alive-part and off-part. GPL. all interrupts can be wake-up sources. but in off-part it is not the same. GPIO GPIO consists of two parts. Therefore. In idle mode. Alive part GPIO register groups contain GPK.00 10. Pin Name XURXD0/GPA0 XUTXD0/GPA1 XUCTSN0/GPA2 XURTSN0/GPA3 XURXD1/GPA4 XUTXD1/GPA5 XUCTSN1/GPA6 XURTSN1/GPA7 XURXD2/GPB0 XUTXD2/GPB1 XURXD3/GPB2 XUTXD3/GPB3 XIRSDBW/GPB4 XI2CSCL/GPB5 XI2CSDA/GPB6 XSPIMISO0/GPC0 XSPICLK0/GPC1 XSPIMOSI0/GPC2 XSPICS0/GPC3 XSPIMISO1/GPC4 XSPICLK1/GPC5 XSPIMOSI1/GPC6 XSPICS1/GPC7 XPCMDCLK0/GPD0 XPCMEXTCLK0/GPD1 XPCMFSYNC0/GPD2 Default Function GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 CF_data_dir GPB5 GPB6 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPD0 GPD1 GPD2 I/O state @Reset I/O Type hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) O(L) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) 48 . Every S3C6410X pin reset value is as below. the registers in alive-part can keep their values during sleep mode. External Interrupt is consists of 10 groups numbered from 0 to 9. Only external interrupt group 0 is used for wakeup source in Stop and Sleep mode.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Wakeup source GPIO is GPL[14:8]. And. In Alive-part power is supplied on sleep mode.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 XPCMSIN0/GPD3 XPCMSOUT0/GPD4 XPCMDCLK1/GPE0 XPCMEXTCLK1/GPE1 XPCMFSYNC1/GPE2 XPCMSIN1/GPE3 XPCMSOUT1/GPE4 XCICLK/GPF0 XCIHREF/GPF1 XCIPCLK/GPF2 XCIRSTN/GPF3 XCIVSYNC/GPF4 XCIYDATA0/GPF5 XCIYDATA1/GPF6 XCIYDATA2/GPF7 XCIYDATA3/GPF8 XCIYDATA4/GPF9 XCIYDATA5/GPF10 XCIYDATA6/GPF11 XCIYDATA7/GPF12 XPWMECLK/GPF13 XPWMTOUT0/GPF14 XPWMTOUT1/GPF15 XMMCCLK0/GPG0 XMMCCMD0/GPG1 XMMCDATA0_0/GPG2 XMMCDATA0_1/GPG3 XMMCDATA0_2/GPG4 XMMCDATA0_3/GPG5 XMMCCDN0/GPG6 XMMCCLK1/GPH0 XMMCCMD1/GPH1 XMMCDATA1_0/GPH2 XMMCDATA1_1/GPH3 XMMCDATA1_2/GPH4 XMMCDATA1_3/GPH5 XMMCDATA1_4/GHP6 XMMCDATA1_5/GPH7 XMMCDATA1_6/GPH8 XMMCDATA1_7/GPH9 XVVD0/GPI0 GPD3 GPD4 GPE0 GPE1 GPE2 GPE3 GPE4 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPF8 GPF9 GPF10 GPF11 GPF12 GPF13 GPF14 GPF15 GPG0 GPG1 GPG2 GPG3 GPG4 GPG5 GPG6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GHP6 GPH7 GPH8 GPH9 GPI0 I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag hag_a 49 .

00 XVVD1/GPI1 XVVD2/GPI2 XVVD3/GPI3 XVVD4/GPI4 XVVD5/GPI5 XVVD6/GPI6 XVVD7/GPI7 XVVD8/GPI8 XVVD9/GPI9 XVVD10/GPI10 XVVD11/GPI11 XVVD12/GPI12 XVVD13/GPI13 XVVD14/GPI14 XVVD15/GPI15 XVVD16/GPJ0 XVVD17/GPJ1 XVVD18/GPJ2 XVVD19/GPJ3 XVVD20/GPJ4 XVVD21/GPJ5 XVVD22/GPJ6 XVVD23/GPJ7 XVHSYNC/GPJ8 XVVSYNC/GPJ9 XVDEN/GPJ10 XVVCLK/GPJ11 XHIDATA0/GPK0 XHIDATA1/GPK1 XHIDATA2/GPK2 XHIDATA3/GPK3 XHIDATA4/GPK4 XHIDATA5/GPK5 XHIDATA6/GPK6 XHIDATA7/GPK7 XHIDATA8/GPK8 XHIDATA9/GPK9 XHIDATA10/GPK10 XHIDATA11/GPK11 XHIDATA12/GPK12 XHIDATA13/GPK13 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPI8 GPI9 GPI10 GPI11 GPI12 GPI13 GPI14 GPI15 GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 GPJ5 GPJ6 GPJ7 GPJ8 GPJ9 GPJ10 GPJ11 XHIDATA0 XHIDATA1 XHIDATA2 XHIDATA3 XHIDATA4 XHIDATA5 XHIDATA6 XHIDATA7 XHIDATA8 XHIDATA9 XHIDATA10 XHIDATA11 XHIDATA12 XHIDATA13 I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a 50 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.

00 XHIDATA14/GPK14 XHIDATA15/GPK15 XHIDATA16/GPL13 XHIDATA17/GPL14 XHIADR0/GPL0 XHIADR1/GPL1 XHIADR2/GPL2 XHIADR3/GPL3 XHIADR4/GPL4 XHIADR5/GPL5 XHIADR6/GPL6 XHIADR7/GPL7 XHIADR8/GPL8 XHIADR9/GPL9 XHIADR10/GPL10 XHIADR11/GPL11 XHIADR12/GPL12 XHICSN/GPM0 XHICSN_MAIN/GPM1 XHICSN_SUB/GPM2 XHIWEN/GPM3 XHIOEN/GPM4 XHIIRQN/GPM5 XEINT0/GPN0 XEINT1/GPN1 XEINT2/GPN2 XEINT3/GPN3 XEINT4/GPN4 XEINT5/GPN5 XEINT6/GPN6 XEINT7/GPN7 XEINT8/GPN8 XEINT9/GPN9 XEINT10/GPN10 XEINT11/GPN11 XEINT12/GPN12 XEINT13/GPN13 XEINT14/GPN14 XEINT15/GPN15 XM0CSN2/GPO0 XM0CSN3/GPO1 XHIDATA14 XHIDATA15 XHIDATA16 XHIDATA17 XHIADR0 XHIADR1 XHIADR2 XHIADR3 XHIADR4 XHIADR5 XHIADR6 XHIADR7 XHIADR8 XHIADR9 XHIADR10 XHIADR11 XHIADR12 XHICSN XHICSN_MAIN XHICSN_SUB XHIWEN XHIOEN XHIIRQN GPN0 GPN1 GPN2 GPN3 GPN4 GPN5 GPN6 GPN7 GPN8 GPN9 GPN10 GPN11 GPN12 GPN13 GPN14 GPN15 XM0CSN2 XM0CSN3 I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-down) I(pull-up) I(pull-up) I(pull-up) I(pull-up) I(pull-up) O(H) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) I (pull-down) O(H) O(H) hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hag_a hbg hbg 51 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 XM0CSN4/GPO2 XM0CSN5/GPO3 GPO4 GPO5 XM0ADDR6/GPO6 XM0ADDR7/GPO7 XM0ADDR8/GPO8 XM0ADDR9/GPO9 XM0ADDR10/GPO10 XM0ADDR11/GPO11 XM0ADDR12/GPO12 XM0ADDR13/GPO13 XM0ADDR14/GPO14 XM0ADDR15/GPO15 XM0ADRVALID/GPP0 XM0SMCLK/GPP1 XM0WAITN/GPP2 XM0RDY0_ALE/GPP3 XM0RDY1_CLE/GPP4 XM0INTSM0_FWEN/GPP5 XM0INTSM1_FREN/GPP6 XM0RPN_RNB/GPP7 XM0INTATA/GPP8 XM0RESETATA/GPP9 XM0INPACKATA/GPP10 XM0REGATA/GPP11 XM0WEATA/GPP12 XM0OEATA/GPP13 XM0CDATA/GPP14 XM0ADDR[18]/GPQ0 XM0ADDR[19]/GPQ1 GPQ2 GPQ3 GPQ4 GPQ5 GPQ6 Xm0ADDR[17]/GPQ7 Xm0ADDR[16]/GPQ8 XM0CSN4 XM0CSN5 Reserved Reserved XM0ADDR6 XM0ADDR7 XM0ADDR8 XM0ADDR9 XM0ADDR10 XM0ADDR11 XM0ADDR12 XM0ADDR13 XM0ADDR14 XM0ADDR15 XM0ADRVALID XM0SMCLK XM0WAITN XM0RDY0_ALE XM0RDY1_CLE XM0INTSM0_FWEN XM0INTSM1_FREN XM0RPN_RNB XM0INTATA XM0RESETATA XM0INPACKATA XM0REGATA XM0WEATA XM0OEATA XM0CDATA Xm0ADDR[18] Xm0ADDR[19] Reserved Reserved Reserved Reserved Reserved Xm0ADDR[17] Xm0ADDR[16] O(H) O(H) O(H) O(H) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(H) I I/O(L) I/O(L) I/O(H) I/O(H) O(L)/I I O(H) I O(H) O(H) O(H) I O(L) O(L) O(L) O(H) O(H) I I O(L) O(L) hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hb_c hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg hbg 52 .

00 THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS.8V~2. 3. Pull-up Disable.USB Host’s DN. . ADC should be set as Standby mode if ADC operation doesn't run. which doesn't have internal Pull-up/dn control. Controllable Pull-up/down Resistor and B type Output driver 1. Controllable Pull-up/down Resistor and A type Output driver 1. XP & YP pins should not be connected to any external GND source in sleep mode.DP should be Pull-down as follows.S3C6410_CIRCUIT DESIGN GUIDE REV 1.DP pull-down with 15K Ohm resistors.5V Wide Range Bi-directional Buffer with Schmitt Trigger Input.8V~3. In other words.3V Wide Range Bi-directional Buffer with Schmitt Trigger Input. Don’t leave Floating Condition.3V Wide Range Bi-directional Buffer with Schmitt Trigger Input. Controllable Pull-up/down Resistor and B type Output driver Pin configuration guide in Sleep mode Pin Condition which are configured as Input GPIO Pin Input Pin. XP & YP should be floating in sleep mode. 53 .8V~3. USB Host’s DN. (even if USB Host is not used. Configuration Internal Pull-up/dn Enable or Output Low Internal Pull-up/dn Disable or Output Low External Pull-up Enable with Pull-up Resistor Output Low High or Low (It depends on External device's status) Output Low If Buffer can hold bus level. Controllable Pull-up/down Resistor and A type Output driver 1. USB OTG pads should be Suspend mode or Turn off the VDDOTG&VDDOTGI 5. Output pin. Output Low If External Device's Power is Off If External Device's Power is On If Memory's Power is Off and External Buffer does Memory's Power exist is On and no External Buffer NOTE: 1.3V Wide Range Bi-directional Alive Buffer with Schmitt Trigger Input. which are connected to External device Dat a Bus which are configured as Ouput If External Device doesn't always drive Pin's level. User should consider his own Board condition and application. 4.8V~3. Input (I)/Output (O) Type hag(pvhbsudtartg) hag_a (pvhbsudtag_alv) hbg(pvhbsudtbrtg) mbg(pvmbsudtbrtg) Descriptions 1. 2.) * This table is just for informational use only.

The DMA request occurred when “DMA Request” signal is falling edge ( H -> L).00 11. These signals are multiplexed with UART RXD[3:2] and UART TXD[3:2].S3C6410_CIRCUIT DESIGN GUIDE REV 1. 54 . Refer to the description of GPB0 . GPB1. GPB2 and GPB3 on GPBCON register. DMA Controller DMA Controller has 2 signals out which are external DMA Request(ExdREQ) and External DMA Acknowledge(ExdACK). Therefore it is requisite to set GPIO 's GPB ports as a external DMA function.

55 .00 12. VECTORED INTERRUPT CONTROLLER This Chapter is for internal Logic.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

56 . SECURITY SUB-SYSTEM This Chapter is for internal Logic.00 13.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

Support 1/2/4 BPP Palletized Color. Support 1/2/4/8 BPP Palletized Color.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Support 1/2/4 BPP Palletized Color.601 I/F (YUV 422 8bit) 5 Windows & Color Key & 16-level alpha blending Support 1/2/4/8 BPP Palletized Color. Window4 Support 16/18/24BPP non-palletized color Maximum Maximum 16M virtual screen size Upto WVGA(800x480) Recommended : 24BPP Window 2ea + Window 1ea(for cursor) Video Output Interface Layer Size 57 .00 14. DISPLAY CONTROLLER 14. Window0 Support 16/18/24BPP non-palletized color Support local bus. Window2 Support 16/18/24BPP non-palletized color Support local bus. Window1 Support 16/18/24BPP non-palletized color Support local bus.1 FEATURE OF THE DISPLAY CONTROLLER Parallel RGB I/F : upto 24BPP Serial RGB I/F : upto 24BPP I80 I/F ITU-R BT. Window3 Support 16/18/24BPP non-palletized color Support 1/2 BPP Palletized Color.

2 VD SIGNAL CONNECTION Below table shows that how to connect VD signal connection each bpp mode.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 14. Parallel RGB 24BPP (888) VD[23] VD[22] VD[21] VD[20] VD[19] VD[18] VD[17] VD[16] VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8] VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0] R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] 18BPP (666) R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] G[2] G[1] G[0] B[5] B[4] B[3] B[2] B[1] B[0] 16BPP (565) R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] G[2] G[1] G[0] B[4] B[3] B[2] B[1] B[0] Serial RGB 24BPP (888) D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 18BPP (666) D[5] D[4] D[3] D[2] D[1] D[0] VEN_DATA[7] VEN_DATA[6] VEN_DATA[5] VEN_DATA[4] VEN_DATA[3] VEN_DATA[2] VEN_DATA[1] VEN_DATA[0] 601 58 .

00 I80 CPU I/F (Parallel) 16BPP(565) Lx_DATA1 6 VD[23] VD[22] VD[21] VD[20] VD[19] VD[18] VD[17] VD[16] VD[15] VD[14] VD[13] VD[12] VD[11] VD[10] VD[9] VD[8] VD[7] VD[6] VD[5] VD[4] VD[3] VD[2] VD[1] VD[0] 000 1st R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] G[2] G[1] G[0] B[4] B[3] B[2] B[1] B[0] R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] G[2] G[1] G[0] B[5] B[4] B[3] B[2] 18BPP(666) 001 2nd B[1] B[0] 1st R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] 18BPP(666) 010 2nd G[2] G[1] G[0] B[5] B[4] B[3] B[2] B[1] B[0] 1st R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] 24BPP (888) 011 2nd B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] R[5] R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] G[2] G[1] G[0] B[5] B[4] B[3] B[2] B[1] B[0] 18BPP(666) 100 1st R[4] R[3] R[2] R[1] R[0] G[5] G[4] G[3] 16BPP(565) 101 2nd G[2] G[1] G[0] B[4] B[3] B[2] B[1] B[0] When S3C6410X display controller output interface is parallel RGB(RGB16bpp).S3C6410_CIRCUIT DESIGN GUIDE REV 1. you want to connect parallel RGB(RGB18bpp) to LDI. Check example as below. 59 .

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 Figure 14_1) LCD connection example 60 .

POST PROCESSOR This Chapter is for internal Logic.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 15. 61 .

62 . TV SCALER This Chapter is for internal Logic.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 16.

49KΩ to GND Connect 150Ω to GND 27MHz.1uF ceramic capacitor to GND Connect 6.3V C176 100nF + C175 10uF/6.3V) Connect 0. 10ppm 25pF@CL=12.1uF ceramic capacitor to VDDDAC Connect 0.00 17.7K R323 XdacOUT_0 0 C178 5 4 C177 33uF/10V C179 33uF/10V + + U50 R324 R325 0 75 R326 0 COMPOSITE 1 VIDEO GND 2 100nF R327 150 NJM2561 VDD3.7K R329 XdacOUT_1 0 C183 5 4 C182 33uF/10V C184 33uF/10V + + R330 CN1 3 Y 4 C 100nF R331 150 NJM2561 75 2 Yn Cn 1 CONN_SVIDEO_12P Figure 17_1) TV Encoder connection example 63 .3V 6 U51 V+ GND VIN POWER VOUT VSAG 1 2 3 R328 4.5 Note.S3C6410_CIRCUIT DESIGN GUIDE REV 1.3V C181 100nF + C180 10uF/6.3V (± 0. 1M Ohms VDD3.3V 6 U49 V+ GND VIN POWER VOUT VSAG 1 2 3 R322 4. TV ENCODER VDDDAC XdacCOMP XdacIREF XdacVREF XdacOUT[1:0] External X-tal frequency External capacitance used for X-tal Feedback resistor between X27mXTI with X27mXTO CEXT V 3. This value depends on the board design.

00 DACVREF TP9 VDD_DAC C2 XdacIREF XdacVREF CB5 R26 100nF 100nF XdacCOMP 6.S3C6410_CIRCUIT DESIGN GUIDE REV 1.49K/R1005 Figure 17_2) DAC Reference pin connection 64 .

00 18.S3C6410_CIRCUIT DESIGN GUIDE REV 1. GRAPHICS 2D This Chapter is for internal Logic. 65 .

66 .00 19.S3C6410_CIRCUIT DESIGN GUIDE REV 1. IMAGE ROTATOR This Chapter is for internal Logic.

67 .1 CAMIF INPUT CAMIF can support the next video standards. driven by the Camera processor Horizontal Sync.00 20. 4096 x 4096 pixels Camera input support Preview & Codec max. HREF should be valid after VSYNC pulse at capture start. driven by the Camera processor Frame Sync. driven by the Camera processor Pixel Data driven by the Camera processor Master Clock to the Camera processors Software Reset or Power Down for the Camera processor 601 FIELD signal for External Camera Interface User check interface signal mapping properly. CAMERA INTERFACE 20.S3C6410_CIRCUIT DESIGN GUIDE REV 1. (1) ITU-R BT 601 YCbCr 8-bit mode (2) ITU-R BT 656 YCbCr 8-bit mode * Maximum. Note) S3C6410X have some restriction about video timing. User should be check following items 1. Horizontal size Preview Prescaled input Max Hsize Scaler bypass TargetHsize (no rotation) TargetHsize (with rotation) 720 pixels 4096 pixels 4096 pixels (Bypass YCbCr) 720 pixels (Except Bypass) 720 pixels (RGB) 360 pixels (YCbCr) 2048 pixels 4096 pixels 4096 pixels (Bypass YCbCr) 2048 pixels (Except Bypass) Codec 20.2 Signal Description Name XciPCLK XciVSYNC XciHREF XciDATA[7:0] XciCLK XciRSTn XcamFIELD I/O I I I I O O I Active H/L H/L H/L H/L Description Pixel Clock.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. the input data is stored in four buffers(pingpong memory which is designated by SFR). even field frame data and odd field frame data is stored in turn. CAM FIELD.54mm header f emale Figure 20_1) Camera Interface 68 . In case of image capture. start frame is always even field frame. In this mode. CF Data DIR and EINT1[12]. Camera Interface VDD_CAM VDD_CAM R204 10K J7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 B_XciY DATA[7:0] B_XciY DATA1 B_XciY DATA3 B_XciY DATA5 B_XciY DATA7 B_XciPCLK B_XciVSY NC Xi2cSCL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 B_XciY DATA[7:0] B_XciY DATA0 B_XciY DATA2 B_XciY DATA4 B_XciY DATA6 B_XciCLK B_XirSDBW B_XciHREF Xi2cSDA B_XciRSTn 2.PROGRESSIVE INPUT In progressive mode. In 601 interlaced input mode GPIO B[4] port is used field signal.00 . .INTERACED INPUT In interlace mode. GPIO B[4] port is used IrDA SDBW . Therefore even field frame data is stored in 1st and 3rd pingpong memory while odd field frame data is stored 2nd and 4th pingpong memory. input. all the input data is stored in four buffers (pingpong memory which is designated by SFR) sequentially by the unit of frame. output.

00 21. MULTI-FORMAT VIDEO CODEC This Chapter is for internal Logic. 69 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 22. 70 . JPEG CODEC This Chapter is for internal Logic.

the AP (Application Processor. driven by the Modem chip External interrupts IO Data bus. MODEM INTERFACE This specification defines the interface between the Base-band Modem and the Application Processor for the data-exchange of these two devices. driven by the Modem chip 71 . driven by the Modem chip Read enable. For the data-exchange. S3C6410X) has a DPSRAM(Dual Port SRAM.S3C6410_CIRCUIT DESIGN GUIDE REV 1. driven by the Modem chip Write enable.1 Pin Description Signal XhiCSn XhiWEn XhiOEn XhiINTR XhiADDR[12:0] XhiDATA[17:0] XEINT[27:16] I/O I I I O I I Description Chip select. 23.00 23. driven by the Modem chip Interrupt request to the Modem chip Address bus. 8KB) buffer (on-chip) and the Modem chip can access that DPSRAM buffer using a typical asynchronous-SRAM interface.

you must connect the CS(Chip Select) which is used to boot-up your device to S3C6410’s CS(XhiCSn). Confirm the datasheet what you want to use.3 Caution (1) Voltage level is same between MODEM(memory bus and EXINT) and AP(MODEM I/F). (3) If you use AP booing function. Any other extra interrupt request pin needs not between AP and modem because interrupt requests from modem to AP are delivered through Xhi_A[12:0] and Xhi_D[16:0] by writing some value to INT2AP register of DPSRAM in AP. (4) Refer the datasheet’s timing specification.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 23. (5) Address connection between MODEM and AP follows the memory controlling policy of MODEM.2 Pin Connection Example Figure 23_1) Modem I/F Pin connection example 23. (2) There is only one interrupt request pin from AP to MODEM(XhiINTR). 72 .

These signals are not used for Host Interface.00 24. HOST INTERFACE Host I/F is same as Modem I/F except XhiADDR[6:3].S3C6410_CIRCUIT DESIGN GUIDE REV 1. 73 . So you may leave these signals as no connect.

25.3 USB Host connection Power Domain Signal Others VDDUH XuhDN.4 Caution The S3C6410X USB system can be configured as following 1.00 25.A ty pe DN and DP should be routed evenly Figure 25_1) USB circuit example 25. 74 .1 Host 1 Port & USB 2. refer to S3C6410X User’s Manual.S3C6410_CIRCUIT DESIGN GUIDE REV 1. USB 1.1 Host 2 Ports For detail.0 OTG 1 Port 2.1 Power Domain VDD_UH is for USB Host power supplied with 3. USB 1. USB Host 25.2 Circuit Diagram Example C_PWR_5V R701 15K R702 33 CON7A 1 2 3 4 VBUS DD+ GND USB(HOST) SOCKET XuhDN XuhDP R703 33 R704 15K Dual USB Port .3V 25. XuhDP Connect to 15Kohms series resistor to GND.

S3C6410X can control usb power block freely using GPIO. VDD_D RA09 C_PWR_5V USB20_EN 10K Vout=0.2K 1% (1. (1) XusbID : leave as a no connect(Device mode) (2) XusbDRVVBUS : leave as a no connect (The charge pump circuit should be removed) (3) Refer to following circuit diagram about other signals. For implementing this scheme. SEC recommends that user should use external regulators for VDD_OTG and VDD_OTGI.0K. USB 2.8(1+R2/R1) RA13 100K JA07 1 VDD_OTG RA14 75.1 Power Domain VDD_OTG is for USB OTG phy power supplied with 3. To use Only Device mode but OTG mode. VDD_OTG and VDD_OTGI can be off to reduce power consumption if USBOTG function is not used. (1) use regulator with enable function pin.3V and VDD_OTGI is for phy logic power supplied with 1.2 Circuit Diagram Example To minimize power consumption in USB block.8(1+R2/R1) UA04 4 1 2 CTA07 10uF/16V + SHDN IN IN POK OUT OUT SET GND MAX1806EUA15 3 8 7 6 5 RA10 100K JA06 1 VDD_OTGI RA11 RA12 169K 1% 42.3K 1% 10uF/16V Figure 26_1) USB OTG Power Example 75 .3V) 2 CTA10 + OTG CTA09 10uF/16V + RA15 24. (2) use Charge Pump Circuit in order to supply VBUS to a bus-powered USB device. 26.S3C6410_CIRCUIT DESIGN GUIDE REV 1.2V. 1% (3.1V) 2 CTA08 + OTGI 10uF/16V C_PWR_5V UA05 4 1 2 SHDN IN IN POK OUT OUT SET GND MAX1806EUA33 3 8 7 6 5 Vout=0.0 HS OTG 26. user should consider following circuit.00 26.

C) XotgTO XREXT VDD_D X701 1M ohm XotgTO OSC2 4 1 VDD OE OUT GND 3 2 XotgTO R723 44.2ohm 1% 1 C703 15pF 1 C704 15pF OSCILLATOR 48Mhz 2 2 Figure 26_4) Clock input(Oscillator or X-tal) and REXT connection 76 .2uF C707 C708 MAX682 Figure 26_2) Charge pump circuit example CON8 XVBUS XotgDM XotgDP XotgID C705 100nF CT701 + 10uF 1 2 3 4 5 VBUS DD+ ID GND USB_MINI-AB Figure 26_3)2 USB Otg Connector TP703 XotgTI R724 48MHz(N.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 C_PWR_5V XVBUS U701 R707 0 1 XotgDRV_VBUS R708 110K 2 3 C706 1uF 4 nSKIP nSHDN IN GND OUT CXP CXN PGND 8 7 6 5 0.47uF 2.

We should basically consider the following instruction.1 Introduction This document conducts a guide to integrate a discrete high speed usb device onto a four layer PCB. The third layer is for power and the fourth layer is for signal layer again.2 Ω ± 1% 12/24/48 MHz tolerance +-100ppm peak jitter 100ps duty cycle 40/60~60/40 12M/24M .4. The second layer is for ground.4 USB SIGNAL ROUTING 26. The deviation should be minimized. III. VI. The board design guidelines handle trace separation. Do not route usb traces under crystals. This reduces signal reflections and impedance changes that affect signal quality. Route high-speed USB signals not using vias and stubs with using two 45 degree turns or an arc instead of making a single 90 degree trun. magnetic devices or ICs that use and/or duplicate clocks. oscillators.4.2 PCB layout guidelines Routing and placement When an engineer lays out a new design. termination placement requirements and overall trace length guidelines 26.00 26. V.3 USB PLL Specification PLL & Clock Generator generally uses the following conditions.20 pF 48M . That is based on four layer board. The first layer is for signal layer. Route all traces over continuous planes(VCC and GND). Ther parallelism between USB differential signals with the trace spacing should be maintained. clock synthesizers. Avoid crossing over anti-etch if at all possible. the excellent signal quality and minimized EMI problem must be required. with no interruptions. REXT External Oscillator frequency R 44. IV. 77 . HS signals should be placed on top shown in the below figure II. I.S3C6410_CIRCUIT DESIGN GUIDE REV 1. HS clock and HS USB different pairs should be first routed with minimum trace length.15 pF 1M Ohm External capacitance used for X-tal Feedback Resistor between XusbTI and XusbTO CEXT 26.

00 The minimized length of high speed clock and periodic signal traces is highly recommended.0254mm) VIII. you should 20-mil minimum spacing between HS usb signal pairs. Poor routing mistake 78 . VII. To prevent crosstalk. Max trace length mismatch between HS usb signal pairs such as DM and DP should be under 150mils. For example. IX. The suggested spacing to clock signal is 50mils ( 1mils = 0.S3C6410_CIRCUIT DESIGN GUIDE REV 1. X.

(1) Voltage level is same between device and SD/MMC GPIO whether VDD_MMC or not. (6) DAT[3] card detection method didn’t recommend. Case 1 (3 Channel Usage) Case 2 (2 Channel Usage) Channel 0 4-bit mode 4-bit mode Channel 1 4-bit mode 4-bit or 8-bit mode Channel 2* 4-bit mode Not Used Every controller has up to 52MHz speed. Refer the datasheet. Every MMC controller belongs to VDD_MMC power. Function Function 5 6 GPC4 SPI MOSI[1] MMC CMD2 I2S_V40 DO[0] EINT Input Output GPC5 SPI CLK[1] MMC CLK2 I2S_V40 DO[1] EINT Input Output (4) MMC channel 0 and MMC channel 1 is shared same card detection pin. GPIO Name Function 1 Function 2 Function3 Function4 79 . So clock and data line should have same routing path. (5) MMC channel 2 hasn’t card detection pin. the other channel should assign external GPIO for card detection pin. So should assign one external GPIO for card detection. (3) MMC Channel 2 and SPI Channel 1 are can’t use at the same time. SDMMC1 support 8-bit MMC or two 4-bit MMC interfaces. (2) Confirm the pull-up resistor value chosen by specification.00 27. If one channel assign card detection pin. SDMMC0 as 4-bit MMC interface. Refer to below table. Confirm the datasheet what you want to use.S3C6410_CIRCUIT DESIGN GUIDE REV 1. SD/MMC HOST CONTROLLER S3C6410X has three slots for supporting high speed SD/MMC interface.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 VDD_MMC VDD_MMC 1 2 R1 R2 R816 R817 R818 3 4 5 6 7 8 9 10 11 12 13 14 15 NC NC DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP XmmcDATA0_2 XmmcDATA0_3 XmmcCMD0/ADDR_CF1 XmmcDATA0_0/ADDR_CF2 XmmcDATA0_1 XmmcCLK0/ADDR_CF0 16 17 18 19 20 21 22 23 24 25 26 27 28 SD Socket [Taisol] Figure 27_1)3 SDMMC0 interface example 29 P29/GND P30/GND MMCDATA & CLK path must be same length and route 10K 10K 10K 10K 10K CON1 30 80 .

S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 VDD_MMC VDD_MMC 1 2 R6 R7 R8 R9 R10 R11 R12 R13 R14 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC NC DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP XmmcDATA1_2 XmmcDATA1_3 XmmcCMD1 XmmcDATA1_4/XmmcDATA2_0 XmmcDATA1_5/XmmcDATA2_1 NC XmmcCLK1 XmmcDATA1_6/XmmcDATA2_2 XmmcDATA1_7/XmmcDATA2_3 XmmcDATA1_0 XmmcDATA1_1 R16 SD Socket [Taisol] Figure 47_2) SDMMC1 interface example 29 P29/GND P30/GND MMCDATA & CLK path must be same length and route 10K 10K 10K 10K 10K 10K 10K 10K 10K CON2 30 81 .

00 28.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Cellular Modem rxDATA rxFLAG rxWAKE rxREADY R e c e iv e r txDATA txFLAG txWAKE txREADY T r a n s m itt e r Figure 28_1) MIPI HSI connection with FPC Cable connector 82 . MIPI HSI INTERFACE CONTROLLER There are 4 Tx signals and 4 Rx signals Here is an example to connect MIPI by FPC cable connecter.

5V~3.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Refer to below table.6V. GPIO Name GPC4 GPC5 Function 1 SPI MOSI[1] SPI CLK[1] Function 2 MMC CMD2 MMC CLK2 Function3 I2S_V40 DO[0] I2S_V40 DO[1] Function4 EINT EINT Function 5 Input Input Function 6 Output Output 83 . channel1. SPI 29.2 SPI MAXIMUM SPEED The maximum frequency Master Tx/Master Rx/Slave Rx/Slave Tx(CPHA=0) is up to 50MHz. The maximum frequency Slave Tx is up to 20MHz(CPHA=1).4 MUXED PIN LIMITATION MMC Channel 2. Output capacitance must be lower than 10pF at the channel 0.1 EXTERNAL LOADING CAPACITANCE S3C6410X has two SPI controllers.3 SUPPORTED VOLTAGE RANGE SPI interface voltage range is 2. 29. SPI channel 0 voltage follow by VDD_EXT and channel 1 voltage follow by VDD_MMC. I2S and SPI Channel 1 are can’t use at the same time. 29. 29. Both controllers should follow the external loading capacitance below.00 29.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. Please refer to datasheet 30.7 VBDDB Figure 30_1) Definition of timing for High-Speed mode devices on the IIC –bus 1) tr (Rising time) which depends on Pull. But this resistor value should be changed by signal bus loading capacitance.up resistance and bus capacitance affects SCL frequency change ( Higher tr makes slower SCL).2 Equation of the pull-up resistor value VBILB = 0.2039 84 . minimum is 20 + 0. Cb and tr Rp(Pull-up resistance) Max is a function of the rise time minimum (tr) and the estimated bus capacitance(Cb) RBpB x CBbB = tBrB / 1.00 30.1 Pin Description Signal Xi2cSCL Xi2cSDA XuRXD[3] XuTXD[3] I/O IO IO IO IO Description I2C CH0 bus clock I2C CH0 bus data Can select I2C CH1 bus clock. especially when it is High-Speed mode (400kHz) 2) tr (Rising time) maximum is 300 ns . Please refer to datasheet Can select I2C CH1 bus data. Each signal need to be pulled up by 1Kohm resistor to VDDEXT. IIC-BUS INTERFACE IIC Bus interface has 2 signals out which are Xi2cSCL and Xi2cSDA.1 Cb (bus capacitance) 3) When tr (Rising time) is 300ns. 30. SCL might be maximum 13% slower than original setting value 4) To make real SCL within 1% variation of setting value(400kHz) .3 VBDDB VBIHB = 0. tr (Rising time) should be less than 80nsec 5) User can use this fomula to determine Rp . Generally.

00 31.5 / 3 ) ‘ Also S3C6410X’s Target Max High speed is 4Mbps.7Mbps 3. UART Figure 31_1) UART connection with COM port example User must use EPLL or MPLL as a UART source clock to use High-Speed (upto 4Mbps) User must use EPLL or MPLL as a UART source clock which is higher than baudrate * 16 for high-speed Max High speed baudrate is changeable depends on PCLK (System bus clock) which is ‘ Baudrate * 16 ≤ PCLK * ( 5.8% ± 1.6Mbps 4.S3C6410_CIRCUIT DESIGN GUIDE REV 1.0Mbps Error tolerance rate ± 2% ± 2% ± 1.0Mbps 4.1 supports Auto Flow Control with RTS & CTS signal. We don’t guarantee above 4Mbps even though a above formula is satisfied Max speed table (under using EPLL or MPLL as a UART source clock circumstance) PCLK 25MHz 33MHz 50MHz 66MHz Max Baudrate 2. 85 .8% - Therefore user must make PCLK (System bus clock) higher than 33MHz to use Bluetooth 2.0 (3Mbps baudrate) Channel #0.

S3C6410_CIRCUIT DESIGN GUIDE REV 1. Note ) XCLKOUT signal which is multiplexed with XpwmTOUT0 is just PLL out and designed for debugging. For this reason.00 32. 86 . this port is appropriate to a test point. XpwmTOUT0 and XpwmTOUT1. If you use this signal as an external clock source. we don’t recommend to use these signal as an external clock source. PWM TIMER There are only two output signals. Therefore. it may not be work well.

768KHz 15pF 5M Ohm 87 .8~3.S3C6410_CIRCUIT DESIGN GUIDE REV 1.0V 32.00 33. RTC VDDRTC RTC X-tal frequency X-tal capacitance used for X-tal Feedback resistor V CEXT 1.

88 .00 34. WATCHDOG TIMER This Chapter is for internal Logic.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

35.288MHz BITCLK from AC97 CODEC nReset for CODEC 48KHz Frame SYNC Serial Data In From AC97 CODEC Serial Data OUT to AC97 CODEC 35.S3C6410_CIRCUIT DESIGN GUIDE REV 1. (Port D.00 35. Port E).2 Audio Ports In S3C6410X. it is decided to the Port for the AC97 controller. AC97 CONTROLLER 35.3 Signal Description S3C6410X AC97 Controller AC97 CODEC(WM9713) Figure 55_1) AC97 connection example 89 . Thus. There is one AC97 Controller and two ports are available for AC97 Controller.1 AC97 Signal Description Signal XpcmDCLK[0] XpcmDCLK[1] XpcmEXTCLK[0] XpcmEXTCLK[1] XpcmFSYNC[0] XpcmFSYNC[1] XpcmSIN[0] XpcmSIN[1] XpcmSOUT[0] XpcmSOUT[1] Input(I)/Output(O) I O O I O Function X97BITCLK X97RESETn X97SYNC X97SDI X97SDO Description 12.

IIS BUS CONTROLLER 36. 36.00 36.2 Audio Port There are two IIS Interface Controllers in S3C6410X. and Controller 1 uses Audio Port 1 (Port 1). If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks. MPLL or PCLK (refer to the User’s Manual). S3C6410X uses and divides EPLL. Each Controller has a port to accept and drive signals external codec. For the making Master Clock.3 External Clock Source S3C6410X provides a master clock to the codec through the Xi2sCDCLK line. 36. there is a way to accept to this frequency as a source of master clock through the Xi2sCDCLK line.1 Signal Description Signal XpcmDCLK[0] XpcmDCLK[1] XpcmEXTCLK[0] XpcmEXTCLK[1] XpcmFSYNC[0] XpcmFSYNC[1] XpcmSIN[0] XpcmSIN[1] XpcmSOUT[0] XpcmSOUT[1] Input(I)/Output(O) I/O I/O I/O I O Function Xi2sCLK[0] Xi2sCLK[1] Xi2sCDCLK[0] Xi2sCDCLK[1] Xi2sLRCK[0] Xi2sLRCK[1] Xi2sSI[0] Xi2sSI[1] Xi2sSO[0] Xi2sSO[1] Description IIS-bus serial clock IIS CODEC system clock IIS-bus channel select clock IIS-bus serial data input IIS-bus serial data output 36.4 Connection Example Figure 66_1) IIS Connection Example with WM8753 (Master Mode) 90 . Controller 0 uses Audio Port 0 (Port D).S3C6410_CIRCUIT DESIGN GUIDE REV 1. This configuration has an advantage that it is not necessary to configure oscillator circuit.

00 Figure 36_2) External OSC Circuit for IISCDCLK (with WM8753) 91 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.

When these clocks are divided. MPLL or PCLK (refer to the User’s Manual). Each Controller has a port to accept and drive signals external codec. 37. Audio Port There are two PCM Interface Controllers in S3C6410X. PCM BUS CONTROLLER 37. Controller 0 uses Audio Port 0 (Port D).S3C6410_CIRCUIT DESIGN GUIDE REV 1.2.3 External Clock Source To make PCM Serial clock and PCM Frame Sync. 92 . PCM interface controller divides EPLL. its advantage is that it is not necessary to configure oscillator circuit.00 37. and Controller 1 uses Audio Port 1 (Port 1).1 Signal Description Signal XpcmDCLK[0] XpcmDCLK [1] XpcmEXTCLK[0] XpcmEXTCLK[1] XpcmFSYNC[0] XpcmFSYNC[1] XpcmSIN[0] XpcmSIN[1] XpcmSOUT[0] XpcmSOUT[1] Input(I)/Output(O) I/O I/O I/O I O Function XpcmDCLK [0] XpcmDCLK [1] XpcmEXTCLK [0] XpcmEXTCLK [1] XpcmFSYNC [0] XpcmFSYNC [1] XpcmSIN [0] XpcmSIN [1] XpcmSOUT [0] XpcmSOUT [1] Description PCM Serial Shift Clock Optional reference clock PCM Sync indicating start of word PCM Serial Data Input PCM Serial Shift Clock 37. If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks. there is a way to accept to this frequency as source of PCM Serial clock and PCM Frame Sync through the XpcmEXTCLK line.

4 Connection Example Figure 37_1) Internal clocks(ex:EPLL) for PCM master clock (with WM8753) Figure 37_2) External clocks(ex:16.9344MHz) for PCM master clock (with WM8753) 93 .S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 37.

XirSDBW) are multiplexed with UART and IIC.00 38. IRDA CONTROLLER IrDA signals (XirRXD. 94 .S3C6410_CIRCUIT DESIGN GUIDE REV 1. XirTXD. Therefore it is requisite to set GPIO 's GPB port as a IrDA function. GPB1 and GPB4 on GPBCON register. Refer to GPB0 .

Touch screen interface can control/select pads (XP.XM. ADC&TOUCH SCREEN INTERFACE The 10/12bit CMOS ADC is a recycling type device with 8-channel analog inputs. -AIN[6] = XM.YP. It’s maximum conversion rate of 1Msps with 5MHz A/D converter clock.00 39. tie AIN [7] to VDDA_ADC or ADCTSC register must be setting to 0xd3. AIN[4:7] mapped with touch signal like bellows -AIN[4] = YM. -AIN[7] = XP. Note) If not use AIN[7](XP). 95 .YM) of the touch screen for X.S3C6410_CIRCUIT DESIGN GUIDE REV 1. -AIN[5] = YP.Y position.

Figure 40_1) Multi-key input keypad example 96 . GPL and GPN registers. Refer to GPH. KEYPAD INTERFACE Keypad signals(Key_pad_ROW and Key_pad_COL) are multiplexed with MMC channel 1. Host I/F and EINT. GPK.00 40.S3C6410_CIRCUIT DESIGN GUIDE REV 1. Therefore it is requisite to set GPIO ports as keypad function.

XpcmSOUT[0] XpcmDCLK[1]. PCM1 Audio Port 2 GPC. XmmcData1[5]. I2S1. Controller that can use this port Audio Port 0 GPD XpcmFSYNC[0].2 Audio Ports Port No GPIO Group Signals XpcmDCLK[0]. XmmcData1[6]. 97 . I2S0. GPH I2S Multi channel* *Note : When I2S Multi Channel use GPC and GPH.S3C6410_CIRCUIT DESIGN GUIDE REV 1.00 41. XpcmEXTCLK[0]. XmmcData1[4]. IIS MULTI AUDIO INTERFACE 41. XpcmSIN[1]. XpcmSOUT[1] XspiMISO[1]. AC97. XspiCLK[1]. XpcmSIN[0]. XspiCS[1]. SPI Channel 1 and 8bit MMC1 channel dose not operate. XmmcData1[7]. PCM0 Audio Port 1 GPE XpcmFSYNC[1]. AC97. XpcmEXTCLK[1].1 Signal Description Signal XmmcData[4] XmmcData [5] XmmcData [6] XmmcData [7] XspiMISO[1] XspiCLK [1] XspiCS [1] Input(I)/Output(O) I/O I/O I/O I O O O Function I2SMULTI_BCLK I2SMULTI_CDCLK I2SMULTI_LRCLK I2SMULTI_DI I2SMULTI _DO[0] I2SMULTI _DO[1] I2SMULTI _DO[2] Description IIS-bus serial clock IIS CODEC system clock IIS-bus channel select clock IIS-bus serial data input IIS-bus serial data output IIS-bus serial data output IIS-bus serial data output 41.

S3C6410_CIRCUIT DESIGN GUIDE REV 1.3 External Clock Source S3C6410X provides a master clock to the codec through the XmmcData[5] line. If an oscillator circuit is configured for a precise clock for the Sampling Frequency without PLLs or Internal clocks.4 Connection Example Figure 41_1) IIS Connection Example with WM8753 (Master Mode) 98 . For the making Master Clock.00 41. there is a way to accept to this frequency as a source of master clock through the XmmcData[5] line. S3C6410X uses and divides EPLL. This configuration has an advantage that it is not necessary to configure oscillator circuit. 41. MPLL or PCLK (refer to the User’s Manual).

GRAPHIC 3D This Chapter is for internal Logic. 99 .00 42.S3C6410_CIRCUIT DESIGN GUIDE REV 1.

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