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Philips Semiconductors

80C51 Family

80C51 family programmer’s guide and instruction set

PROGRAMMER’S GUIDE AND INSTRUCTION SET Memory Organization
Program Memory The 80C51 has separate address spaces for program and data memory. The Program memory can be up to 64k bytes long. The lower 4k can reside on-chip. Figure 1 shows a map of the 80C51 program memory. The 80C51 can address up to 64k bytes of data memory to the chip. The MOVX instruction is used to access the external data memory. The 80C51 has 128 bytes of on-chip RAM, plus a number of Special Function Registers (SFRs). The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing (MOV @Ri). Figure 2 shows the Data Memory organization. Direct and Indirect Address Area The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into three segments as listed below and shown in Figure 3. 1. Register Banks 0-3: Locations 0 through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each

register bank contains eight 1-byte registers 0 through 7. Reset initializes the stack pointer to location 07H, and it is incremented once to start from location 08H, which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the RAM where it is not used for data storage (i.e., the higher part of the RAM). 2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). The bits can be referred to in two ways, both of which are acceptable by most assemblers. One way is to refer to their address (i.e., 0-7FH). The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: 30H through 7FH are available to the user as data RAM. However, if the stack pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. Figure 2 shows the different segments of the on-chip RAM.

FFFF

FFFF

60k BYTES EXTERNAL OR 64k BYTES EXTERNAL

1000 AND 0FFF 4k BYTES INTERNAL 0000 0000

SU00567

Figure 1. 80C51 Program Memory

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Philips Semiconductors

80C51 Family

80C51 family programmer’s guide and instruction set

0FFF

INTERNAL

FF SFRs DIRECT ADDRESSING ONLY 80 AND 7F DRIECT AND INDIRECT ADDRESSING

64k BYTES EXTERNAL

00

0000

SU00568

Figure 2. 80C51 Data Memory

8 BYTES

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 0 ... 3 2 1 0 ... 7F

7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 REGISTER BANKS BIT ADDRESSABLE SEGMENT SCRATCH PAD AREA

SU00569

Figure 3. 128 Bytes of RAM Direct and Indirect Addressable

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Philips Semiconductors

80C51 Family

80C51 family programmer’s guide and instruction set

Table 1.
SYMBOL ACC* B* DPTR DPH DPL

80C51 Special Function Registers
DESCRIPTION Accumulator B register Data pointer (2 bytes) Data pointer high Data pointer low 83H 82H AF AE – BE – AD – BD – AC ES BC PS AB ET1 BB PT1 AA EX1 BA PX1 A9 ET0 B9 PT0 A8 EX0 B8 PX0 xx000000B 0x000000B 00H 00H DIRECT ADDRESS E0H F0H BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H

IE*

Interrupt enable

A8H

EA BF

IP*

Interrupt priority

B8H

87 P0* Port 0 80H AD7

86 AD6

85 AD5

84 AD4

83 AD3

82 AD2

81 AD1

80 AD0 FFH

97 P1* Port 1 90H –

96 –

95 –

94 –

93 –

92 –

91 T2EX

90 T2 FFH

A7 P2* Port 2 A0H A15

A6 A14

A5 A13

A4 A12

A3 A11

A2 A10

A1 A9

A0 A8 FFH

B7 P3* PCON1 Port 3 Power control B0H 87H RD SMOD

B6 WR –

B5 T1 –

B4 T0 –

B3 INT1 GF1

B2 INT0 GF0

B1 TxD PD

B0 Rxd IDL FFH 0xxxxxxxB

D7 PSW* SBUF Program status word Serial data buffer D0H 99H 9F SCON* SP Serial controller Stack pointer 98H 81H 8F TCON* TH0 TH1 TL0 TL1 Timer control Timer high 0 Timer high 1 Timer low 0 Timer low 1 88H 8CH 8DH 8AH 8BH TF1 SM0 CY

D6 AC

D5 F0

D4 RS1

D3 RS0

D2 OV

D1 –

D0 P 00H xxxxxxxxB

9E SM1

9D SM2

9C REN

9B TB8

9A RB8

99 TI

98 RI 00H 07H

8E TR1

8D TF0

8C TR0

8B IE1

8A IT1

89 IE0

88 IT0 00H 00H 00H 00H

TMOD Timer mode 89H GATE C/T M1 M0 GATE C/T NOTES: * Bit addressable 1. Bits GF1, GF0, PD, and IDL of the PCON register are not implemented on the NMOS 8051/8031.

M1

M0

00H

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Philips Semiconductors

80C51 Family

80C51 family programmer’s guide and instruction set

8 BYTES F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 PCON SBUF PSW ACC B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87

BIT ADDRESSABLE

SU00570

Figure 4. SFR Memory Map

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Philips Semiconductors

80C51 Family

80C51 family programmer’s guide and instruction set

Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE. CY
CY AC F0 RS1 RS0 OV – P

AC
PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

F0

RS1

RS0

OV

P

Carry Flag. Auxiliary Carry Flag. Flag 0 available to the user for general purpose. Register Bank selector bit 1 (SEE NOTE 1). Register Bank selector bit 0 (SEE NOTE 1). Overflow Flag. Usable as a general purpose flag. Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of ‘1’ bus in the accumulator.

NOTE: 1. The value presented by RS0 and RS1 selects the corresponding register bank. RS1 0 0 1 1 RS0 0 1 0 1 REGISTER BANK 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE. SMOD – – – GF1 GF0 PD IDL

SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the Serial Port is used in modes 1, 2, or 3. – – – GF1 GF0 PD IDL Not implemented, reserved for future use.* Not implemented reserved for future use.* Not implemented reserved for future use.* General purpose flag bit. General purpose flag bit. Power Down Bit. Setting this bit activates Power Down operation in the 80C51. (Available only in CMOS.) Idle mode bit. Setting this bit activates Idle Mode operation in the 80C51. (Available only in CMOS.)

If 1s are written to PD and IDL at the same time, PD takes precedence.
* User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features.

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User software should not write 1s to reserved bits. reserved for future use. If the bit is 0. See Table below. EA EA — — ES ET1 EX1 ET0 EX0 * – IE.0 – ES ET1 EX1 ET0 EX0 Disables all interrupts. the following three steps must be taken. 3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. Set the EA (enable all) bit in the IE register to 1.3) must be set to 1.2 and P3.3 IE. These bits may be used in future 80C51 products to invoke new features. Enable or disable the Timer 0 overflow interrupt. 2. for external interrupts. and depending on whether the interrupt is to be level or transition activated. pins INT0 and INT1 (P3. no interrupt will be acknowledged.6 IE. reserved for future use.7 IE. Set the corresponding individual interrupt enable bit in the IE register to 1.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set INTERRUPTS: To use any of the interrupts in the 80C51 Family.* Not implemented. INTERRUPT SOURCE IE0 TF0 IE1 TF1 RI & TI VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H In addition.* Enable or disable the serial port interrupt. If EA = 1.2 IE. 1997 Sep 18 6 .1 IE. If the bit is 1. the corresponding interrupt is enabled. each interrupt source is individually enabled or disabled by setting or clearing its enable bit. 1. ITx = 0 level activated ITx = 1 transition activated IE: INTERRUPT ENABLE REGISTER. Not implemented. Enable or disable External Interrupt 0. If EA = 0. BIT ADDRESSABLE. bits IT0 or IT1 in the TCON register may need to be set to 1.5 IE. Enable or disable the Timer 1 overflow interrupt. the corresponding interrupt is disabled.4 IE. Enable or disable External Interrupt 1.

3 IP. BIT ADDRESSABLE.4 IP. interrupt sources are listed below: IE0 TF0 IE1 TF1 RI or TI IP: INTERRUPT PRIORITY REGISTER.7 IP. 1997 Sep 18 7 .5 IP.2 IP. Defines the Timer 1 interrupt priority level. User software should not write 1s to reserved bits. – – – – PS PT1 PX1 PT0 PX0 * – IP.1 IP. If the bit is 0. These bits may be used in future 80C51 products to invoke new features. Defines the Timer 0 interrupt priority level.* Not implemented. reserved for future use. the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a higher priority. reserved for future use. it cannot be interrupted by a lower or same level interrupt.0 – PS PT1 PX1 PT0 PX0 Not implemented. Defines the External Interrupt 0 priority level. Defines External Interrupt 1 priority level.* Not implemented. PRIORITY WITHIN LEVEL: Priority within level is only to resolve simultaneous requests of the same priority level.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS: In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1. From high to low.* Defines the Serial Port interrupt priority level.6 IP. reserved for future use. Remember that while an interrupt service is in progress.

Set by hardware when the Timer/Counter 0 overflows. Set by hardware when External Interrupt edge is detected. TIMER/COUNTERx will run only while TRx = 1 (software control). Cleared by hardware when interrupt is processed. Set/cleared by software to specify falling edge/low level triggered External Interrupt. (NOTE 1) M0 0 1 0 1 1 Operating Mode 0 1 2 3 3 13-bit Timer (8048 compatible) 16-bit Timer/Counter 8-bit Auto-Reload Timer/Counter (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standart Timer 0 control bits. Set/cleared by software to turn Timer/Counter 0 ON/OFF.0 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 overflow flag.3 TCON.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set TCON: TIMER/COUNTER CONTROL REGISTER. (NOTE 1) Mode selector bit.4 TCON. Interrupt 1 type control bit. TH0 is an8-bit Timer and is controlled by Timer 1 control bits. TMOD: TIMER/COUNTER MODE CONTROL REGISTER. Cleared for Timer operation (input from internal system clock). GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 M0 GATE C/T M1 M0 NOTE 1: M1 0 0 1 1 1 When TRx (in TCON) is set and GATE = 1. (Timer 1) Timer/Counter 1 stopped.5 TCON. External Interrupt 1 edge flag. Timer 1 run control bit. TF1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TR1 TCON. Cleared by hardware as processor vectors to the service routine. Set for Counter operation (input from Tx input pin). When GATE = 0. Timer 0 overflow flag. Mode selector bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF.7 TCON. Cleared by hardware as processor vectors to the interrupt service routine. External Interrupt 0 edge flag. 1997 Sep 18 8 . Set by hardware when External Interrupt edge detected. Set by hardware when the Timer/Counter 1 overflows.2 TCON. Set/cleared by software to specify falling edge/low level triggered External Interrupt.1 TCON. BIT ADDRESSABLE. Timer or Counter selector.6 TCON. NOT BIT ADDRESSABLE. Timer 0 run control bit. TIMER/COUNTERx will run only while INTx pin is high (hardware control). Cleared by hardware when interrupt is processed. Interrupt 0 type control bit.

in any mode.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set TIMER SET-UP Tables 2 through 5 give some values for TMOD which can be used to set up Timer 0 in different modes. it is assumed that the user. Moreover. TIMER/COUNTER 0 Table 2. is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx (in TCON) to 1. at this point. The timer is turned ON/OFF by setting/clearing bit TR0 in the software. If it is desired to run Timers 0 and 1 simultaneously. As a Counter: TMOD MODE COUNTER 0 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload One 8-bit Counter INTERNAL CONTROL (NOTE 1) 04H 05H 06H 07H EXTERNAL CONTROL (NOTE 2) 0CH 0DH 0EH 0FH 0 1 2 3 NOTES: 1. then the value that must be loaded into TMOD is 69H (09H from Table 2 ORed with 60H from Table 5). and Timer 1 in mode 2 COUNTER. The Timer is turned ON/OFF by the 1-to-0 transition on INT0 (P3. As a Timer: TMOD MODE TIMER 0 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers INTERNAL CONTROL (NOTE 1) 00H 01H 02H 03H EXTERNAL CONTROL (NOTE 2) 08H 09H 0AH 0BH 0 1 2 3 Table 3. It is assumed that only one timer is being used at a time. For example. the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6). 1997 Sep 18 9 . 2.2) when TR0 = 1 (hardware control). if it is desired to run Timer 0 in mode 1 GATE (external control).

As a Counter: TMOD MODE COUNTER 1 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload Not available INTERNAL CONTROL (NOTE 1) 40H 50H 60H – EXTERNAL CONTROL (NOTE 2) C0H D0H E0H – 0 1 2 3 NOTES: 1. 1997 Sep 18 10 . The Timer is turned ON/OFF by the 1-to-0 transition on INT1 (P3.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set TIMER/COUNTER 1 Table 4.2) when TR1 = 1 (hardware control). 2. As a Timer: TMOD MODE TIMER 1 FUNCTION 13-bit Timer 16-bit Timer 8-bit Auto-Reload Does not run INTERNAL CONTROL (NOTE 1) 00H 10H 20H 30H EXTERNAL CONTROL (NOTE 2) 80H 90H A0H B0H 0 1 2 3 Table 5. The timer is turned ON/OFF by setting/clearing bit TR1 in the software.

Only the SCON register needs to be defined. In mode 0.1 SCON. if SM2 = 0. Must be cleared by software. BIT ADDRESSABLE. SM0 SM0 SM1 SM2 SM1 SCON. (NOTE 1) Serial Port mode specifier. In mode 1. (NOTE 1) Enables the multiprocessor communication feature in modes 2 & 3.0 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate FOSC. or halfway through the stop bit time in the other modes (except see SM2). Receive interrupt flag. or at the beginning of the stop bit in the other modes. (See Table 6./64 or FOSC./12 Variable FOSC. SM2 should be 0. Set by hardware at the end of the 8th bit time in mode 0.2 SCON. RB8 is the stop bit that was received.3 SCON. In mode 2 or 3. Transmit interrupt flag. In mode 1. RB8 is not used. Osc Freq Baud Rate + 12 Serial Port in Mode 1: Mode 1 has a variable baud rate.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set SCON: SERIAL PORT CONTROL REGISTER. if SM2 = 1 then RI will not be activated if a valid stop bit was not received.6 SCON.7 SCON. In mode 0. Set/Cleared by software. Must be cleared by software. In modes 2 & 3. To run the serial port in this mode none of the Timer/Counters need to be set up.) Set/Cleared by software to Enable/Disable reception. if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0.4 SCON. The 9th bit that will be transmitted in modes 2 & 3. MODE 0 1 2 3 0 1 2 3 SCON 10H 50H 90H D0H NA 70H B0H F0H SM2 VARIATION Single Processor Environment (SM2 = 0) Multiprocessor Environment (SM2 = 1) GENERATING BAUD RATES Serial Port in Mode 0: Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. 1997 Sep 18 11 . Set by hardware at the end of the 8th bit time in mode 0. REN TB8 RB8 TI RI NOTE 1: SM0 0 0 1 1 SCON. The baud rate is generated by Timer 1.5 SM2 REN TB8 RB8 TI RI Serial Port mode specifier./32 Variable SERIAL PORT SET-UP: Table 6. is the 9th data bit that was received.

Baud Rate = 1/32 Osc Freq.. depending on the value of the SMOD bit in the PCON register. K Osc Freq TH1 + 256 * 384 baud rate TH1 must be an integer value. The address of PCON is 87H. SERIAL PORT IN MODE 3: The baud rate in mode 3 is variable and sets up exactly the same as in mode 1. 1997 Sep 18 12 . SERIAL PORT IN MODE 2: The baud rate is fixed in this mode and is 1/32 or 1/64 of the oscillator frequency.e. one way to set the bit is logical ORing the PCON register (i. In this mode none of the Timers are used and the clock comes from the internal phase 2 clock. The address of PCON is 87H. then K = 1. K Osc Freq Baud Rate + 32 12 [256 * (TH1)] If SMOD = 0. Baud Rate = 1/64 Osc Freq. then K = 2 (SMOD is in the PCON register). SMOD = 0.#80H). Since the PCON register is not bit addressable.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set USING TIMER/COUNTER 1 TO GENERATE BAUD RATES: For this purpose. Rounding off TH1 to the nearest integer may not produce the desired baud rate. the user may have to choose another crystal frequency. ORL PCON.#80H. To set the SMOD bit: ORL PCON. Refer to Timer Setup section of this chapter. In this case. SMOD = 1. If SMOD = 1. Most of the time the user knows the baud rate and needs to know the reload value for TH1. Timer 1 is used in mode 2 (Auto-Reload).

@Ri A.@Ri A. (128-255)].direct A. Direct Addressed bit in Internal Data RAM or Special Function Register. Instructions that Affect Flag Settings(1) Instruction ADD ADDC SUBB MUL DIV DA RRC RLC SETB C (1)Note Flag C X X X 0 0 X X X 1 OV X X X X X AC X X X Instruction CLR C CPL C ANL C.bit CJNE C 0 X X X X X X X Flag OV AC that operations on SFR byte address 208 or bit addresses 209-215 (i. 80C51 Instruction Set Summary Interrupt Response Time: Refer to Hardware Description Chapter. status register.direct A. control register.Rn A.Rn A. Used by SJMP and all conditional jumps.#data A. 8-bit internal data RAM location (0-255) addressed indirectly through register R1 or R0.e.. I/O port.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set 80C51 FAMILY INSTRUCTION SET Table 7.e. Range is –128 to +127 bytes relative to first byte of the following instruction./bit ORL C. A branch can be anywhere within the 64k-byte Program Memory address space.direct A. 8-bit internal data location’s address. 11-bit destination address.@Ri A. The branch will be within the same 2k-byte page of program memory as the first byte of the following instruction. 8-bit constant included in the instruction. 16-bit constant included in the instruction 16-bit destination address.. etc.bit ORL C. Signed (two’s complement) 8-bit offset byte. MNEMONIC DESCRIPTION BYTE OSCILLATOR PERIOD ARITHMETIC OPERATIONS ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC A./bit MOV C.bit ANL C. Notes on instruction set and addressing modes: Rn direct @Ri #data #data 16 addr 16 addr 11 rel bit Register R7-R0 of the currently selected Register Bank.#data A.#data A Rn Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with carry Add direct byte to Accumulator with carry Add indirect RAM to Accumulator with carry Add immediate data to ACC with carry Subtract Register from ACC with borrow Subtract direct byte from ACC with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from ACC with borrow Increment Accumulator Increment register 1 2 1 2 1 2 1 2 1 2 1 2 1 1 12 12 12 12 12 12 12 12 12 12 12 12 12 12 All mnemonics copyrighted © Intel Corporation 1980 1997 Sep 18 13 . Used by LCALL and LJMP. This could be an Internal Data RAM location (0-127) or a SFR [i. the PSW or bits in the PSW) will also affect flag settings.Rn A. Used by ACALL and AJMP.

#data direct.@Ri A.direct A.#data direct.@Ri A.#data A.#data A A A A A A A AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator left Rotate Accumulator left through the carry Rotate Accumulator right Rotate Accumulator right through the carry Swap nibbles within the Accumulator 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 12 12 DATA TRANSFER MOV MOV MOV A.Rn A.direct A.direct A.Rn A.A direct.@Ri A. 80C51 Instruction Set Summary (Continued) MNEMONIC DESCRIPTION BYTE OSCILLATOR PERIOD ARITHMETIC OPERATIONS (Continued) INC INC DEC DEC DEC DEC INC MUL DIV DA direct @Ri A Rn direct @Ri DPTR AB AB A Increment direct byte Increment indirect RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal Adjust Accumulator 2 1 1 1 2 1 1 1 1 1 12 12 12 12 12 12 24 48 48 12 LOGICAL OPERATIONS ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A.A direct.@Ri Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator 1 2 1 12 12 12 All mnemonics copyrighted © Intel Corporation 1980 1997 Sep 18 14 .#data direct.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set Table 7.Rn A.#data A.Rn A.A direct.direct A.

direct RN.#data DPTR./bit C.Rn direct.bit bit.@Ri direct.bit C.@DPTR A.@A+DPTR A.@Ri A.A Rn.@Ri Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to ACC Move Code byte relative to PC to ACC Move external RAM (8-bit addr) to ACC Move external RAM (16-bit addr) to ACC Move ACC to external RAM (8-bit addr) Move ACC to external RAM (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order digit indirect RAM with ACC Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND complement of direct bit to carry OR direct bit to carry OR complement of direct bit to carry Move direct bit to carry Move carry to direct bit Jump if carry is set Jump if carry not set 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 12 12 24 12 12 24 24 24 24 12 24 12 24 24 24 24 24 24 24 24 24 12 12 12 12 BOOLEAN VARIABLE MANIPULATION CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV JC JNC C bit C bit C bit C.#data @Ri.@A+PC A.A @DPTR.A @Ri.direct @Ri.direct direct.@Ri.Rn A.direct A.#data direct.bit C.A direct direct A. 80C51 Instruction Set Summary (Continued) MNEMONIC DESCRIPTION BYTE OSCILLATOR PERIOD DATA TRANSFER (Continued) MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD A.#data Rn.#data16 A./bit C.@Ri A.C rel rel 1 2 1 2 1 2 2 2 2 2 2 2 2 2 12 12 12 12 12 12 24 24 24 24 12 24 24 24 All mnemonics copyrighted © Intel Corporation 1980 1997 Sep 18 15 .Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set Table 7.A direct.

rel Rn.rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Compare direct byte to ACC and jump if not equal Compare immediate to ACC and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 12 All mnemonics copyrighted © Intel Corporation 1980 1997 Sep 18 16 . 80C51 Instruction Set Summary (Continued) MNEMONIC DESCRIPTION BYTE OSCILLATOR PERIOD BOOLEAN VARIABLE MANIPULATION (Continued) JB JNB JBC rel rel bit.rel direct.#data.#data.rel A.rel @Ri.#data.direct.rel Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit 3 3 3 24 24 24 PROGRAM BRANCHING ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel A.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set Table 7.rel RN.

The label “SUBRTN” is at program memory location 0345 H. SP will contain 09H. and the PC will contain 0345H. The subroutine called must therefore start within the same 2k block of the program memory as the first byte of the instruction following ACALL. opcode bits 7-5. No flags are affected. respectively. then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set INSTRUCTION DEFINITIONS ACALL addr11 Absolute Call ACALL unconditionally calls a subroutine located at the indicated address. and the second byte of the instruction. Bytes: Cycles: Encoding: Operation: 2 2 a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 Function: Description: Example: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 (SP) ← (PC7-0) (SP) ← (SP) + 1 (SP) ← (PC15-8) (PC10-0) ← page address 1997 Sep 18 17 . After executing the instruction. The instruction increments the PC twice to obtain the address of the following instruction. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC. Initially SP equals 07H. ACALL SUBRTN at location 0123H. internal RAM locations 08H and 09H will contain 25H and 01H.

#data Bytes: Cycles: 2 1 0 0 1 0 0 1 0 0 immediate data Encoding: Operation: ADD (A) ← (A) + #data 1997 Sep 18 18 . Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B).@Ri Bytes: Cycles: 1 1 0 0 1 0 0 1 1 i Encoding: Operation: ADD (A) ← (A) + ((Ri)) ADD A. Description: ADD A. if there is a carry-out from bit 7 or bit 3. Four source operand addressing modes are allowed: register. or a carry-out of bit 7 but not bit 6. When adding unsigned integers.direct Bytes: Cycles: 2 1 0 0 1 0 0 1 0 1 direct address Encoding: Operation: ADD (A) ← (A) + (direct) ADD A. OV is set if there is a carry-out of bit 6 but not out of bit 7.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ADD A.Rn Bytes: Cycles: 1 1 0 0 1 0 1 r r r Encoding: Operation: ADD (A) ← (A) + (Rn) ADD A. leaving the result in the Accumulator. or a positive sum from two negative operands. OV indicates a negative number produced as the sum of two positive operands. When adding signed integers. the carry flag indicates an overflow occurred. ADD A. and cleared otherwise. direct. The instruction. otherwise OV is cleared. or immediate. respectively. The carry and auxiliary-carry flags are set.R0 will leave 6DH (01101101B) in the Accumulator with the AC flag cleared and both the Carry flag and OV set to 1. register-indirect.<src-byte> Function: Add ADD adds the byte variable indicated to the Accumulator.

OV indicates a negative number produced as the sum of two positive operands. or a positive sum from two negative operands. leaving the result in the Accumulator. When adding unsigned integers. OV is set if there is a carry-out of bit 6 but not out of bit 7. direct.R0 will leave 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.Rn Bytes: Cycles: 1 1 0 0 1 1 1 r r r Encoding: Operation: ADDC (A) ← (A) + (C) + (Rn) ADDC A. When adding signed integers.@Ri Bytes: Cycles: 1 1 0 0 1 1 0 1 1 i Encoding: Operation: ADDC (A) ← (A) + (C) + ((Ri)) ADDC A. The carry and auxiliary-carry flags are set. ADDC A. the carry flag indicates an overflow occurred. and cleared otherwise. otherwise OV is cleared. register-indirect.#data Bytes: Cycles: 2 1 0 0 1 1 0 1 0 0 immediate data Encoding: Operation: ADDC (A) ← (A) + (C) + #data 1997 Sep 18 19 .<src-byte> Add with Carry ADDC simultaneously adds the byte variable indicated.direct Bytes: Cycles: 2 1 0 0 1 1 0 1 0 1 direct address Encoding: Operation: ADDC (A) ← (A) + (C) + (direct) ADDC A. Function: Description: Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. Four source operand addressing modes are allowed: register. respectively. if there is a carry-out from bit 7 or bit 3. or a carry-out of bit 7 but not out of bit 6.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ADDC A. ADDC A. or immediate. The instruction. the carry flag and the Accumulator contents.

Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set AJMP addr11 Absolute Jump AJMP transfers program execution to the indicated address. the value used as the original port data will be read from the output data latch. The label “JMPADR” is at program memory location 0123H. the source can be the Accumulator or immediate data. When the destination is a directly addressed byte. No flags are affected. Example: If the Accumulator holds 0C3H (11000011B) and register 0 holds 55H (01010101B) then the instruction. AJMP JMPADR is at location 0345H and will load the PC with 0123H. when the destination is a direct address. register-indirect. Bytes: Cycles: 2 2 a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 Function: Description: Example: Encoding: Operation: AJMP (PC) ← (PC) + 2 (PC10-0) ← page address ANL <dest-byte>. not the input pins. When the destination is the Accumulator. this instruction will clear combinations of bits in any RAM location or hardware register. The destination must therefore be within the same 2k block of program memory as the first byte of the instruction following AJMP. The instruction. direct.#01110011B will clear bits 7. ANL P1. and the second byte of the instruction. The two operands allow six addressing mode combinations.R0 will leave 41H (01000001B) in the Accumulator. 1997 Sep 18 20 . ANL A. or immediate addressing. and 2 of output port 1. the source can use register. The instruction. Description: Note: When this instruction is used to modify an output port. which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice).<src-byte> Function: Logical-AND for byte variables ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. opcode bits 7-5. 3.

A Bytes: Cycles: 2 1 0 1 0 1 0 0 1 0 direct address Encoding: Operation: ANL (A) ←〈direct) ∧ (A) ANL direct.Rn Bytes: Cycles: 1 1 0 1 0 1 1 r r r Encoding: Operation: ANL (A) ← (A) ∧ (Rn) ANL A.#data Bytes: Cycles: 3 2 0 1 0 1 0 0 1 1 direct address immediate data Encoding: Operation: ANL (direct) ←〈direct) ∧ #data 1997 Sep 18 21 .Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ANL A.@Ri Bytes: Cycles: 1 1 0 1 0 1 0 1 1 i Encoding: Operation: ANL (A) ← (A) ∧ ((Ri)) ANL A.direct Bytes: Cycles: 2 1 0 1 0 1 0 1 0 1 direct address Encoding: Operation: ANL (A) ← (A) ∧ (direct) ANL A.#data Bytes: Cycles: 2 1 0 1 0 1 0 1 0 0 immediate data Encoding: Operation: ANL (A) ← (A) ∧ #data ANL direct.

and only if. Only direct addressing is allowed for the source operand.<src-bit> Function: Logical-AND for bit variables If the Boolean value of the source bit is a logical 0 then clear the carry flag./OV . otherwise leave the carry flag in its current state.7. BIT 7 C.0 .bit Bytes: Cycles: 2 2 1 ANL 0 0 0 0 0 1 0 bit address Encoding: Operation: (C) ← (C) ∧ (bit) ANL C.7 = 1. and OV = 0: MOV ANL ANL C. but the source bit itself is not affected./bit Bytes: Cycles: 2 2 1 0 1 1 0 0 0 0 bit address Encoding: Operation: ANL (C) ← (C) ∧  (bit) 1997 Sep 18 22 .LOAD CARRY WITH INPUT PIN STATE C.0 = 1. A slash (“/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value.AND WITH INVERSE OF OVERFLOW FLAG Description: ANL C. ACC. P1.P1.ACC. Example: Set the carry flag if.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ANL C.AND CARRY WITH ACCUM. No other flags are affected.

CJNE . NOT_EQ JC .. the carry is cleared. (C) ← 1 ELSE (C) ← 0 1997 Sep 18 23 .. after incrementing the PC to the start of the next instruction. this instruction determines whether R7 is greater or less than 60H. .rel Compare and Jump if Not Equal CJNE compares the magnitudes of the first two operands. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>.. . The first instruction in the sequence. and branches if their values are not equal. the program will loop at this point until the P1 data changes to 34H. otherwise. R7 = 60H. R7. The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data. then the instruction.#60H. sets the carry flag and branches to the instruction at label NOT_EQ. Function: Description: Example: The Accumulator contains 34H.. If the data being presented to Port 1 is also 34H.<src-byte>. and any indirect RAM location or working register can be compared with an immediate constant. . . Register 7 contains 56H. WAIT: CJNE A..WAIT clears the carry flag and continues with the next instruction in sequence.direct...NOT_EQ .. REQ_LOW . (If some other value was being input on P1. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC. . since the Accumulator does equal the data read from P1. By testing the carry flag.P1.) CJNE A.rel Bytes: Cycles: Encoding: Operation: 3 2 1 0 1 1 0 1 0 1 direct address rel... address (PC) ← (PC) + 3 IF (A) < > (direct) THEN (PC) ← (PC) + relative offset IF (A) < (direct) THEN. IF R7 < 60H. R7 > 60H. Neither operand is affected.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set CJNE <dest-byte>.

rel Bytes: Cycles: 3 2 1 0 1 1 1 r r r immediate data rel.#data.rel Bytes: Cycles: 3 2 1 0 1 1 0 1 1 i immediate data rel.#data.#data. address Encoding: Operation: (PC) ← (PC) + 3 IF ((Ri)) < > data THEN (PC) ← (PC) + relative offset IF ((Ri)) < data THEN (C) ← 1 ELSE (C) ← 0 1997 Sep 18 24 . address Encoding: Operation: (PC) ← (PC) + 3 IF (Rn) < > data THEN (PC) ← (PC) + relative offset IF (Rn) < data THEN ELSE (C) ← 1 (C) ← 0 CJNE @Ri.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set CJNE A.rel Bytes: Cycles: 3 2 1 0 1 1 0 1 0 0 immediate data rel. address Encoding: Operation: (PC) ← (PC) + 3 IF (A) < > data THEN (PC) ← (PC) + relative offset IF (A) < data THEN ELSE (C) ← 1 (C) ← 0 CJNE Rn.

No flags are affected.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set CLR A Function: Clear Accumulator The Accumulator is cleared (all bits reset to zero). The instruction. CLR P1. Description: Example: CLR C Bytes: Cycles: 1 1 1 1 0 0 0 0 1 1 Encoding: Operation: CLR (C) ← 0 CLR bit Bytes: Cycles: 2 1 1 1 0 0 0 0 1 0 bit address Encoding: Operation: CLR (bit) ← 0 1997 Sep 18 25 . No other flags are affected. The instruction. CLR Bytes: Cycles: 1 1 1 1 1 0 0 1 0 0 A will leave the Accumulator set to 00H (00000000B). Description: Example: Encoding: Operation: CLR (A) ← 0 CLR bit Function: Clear bit The indicated bit is cleared (reset to zero). CLR can operate on the carry flag or any directly addressable bit. Port 1 has previously been written with 5DH (01011101B). The Accumulator contains 5CH (01011100B).2 will leave the port set to 59H (01011001B).

2 will leave the port set to 5BH (01011011B). The instruction sequence. A bit which had been a one is changed to zero and vice-versa. Bits which previously contained a one are changed to a zero and vice-versa. Description: Note: When this instruction is used to modify an output pin. CPL Bytes: Cycles: 1 1 1 1 1 1 0 1 0 0 A will leave the Accumulator set to 0A3H (10100011B). CPL can operate on the carry or any directly addressable bit.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set CPL A Function: Complement Accumulator Each bit of the Accumulator is logically complemented (one’s complement). CPL CPL P1. The Accumulator contains 5CH (01011100B).1 P1. No flags are affected. the value used as the original data will be read from the output data latch. The instruction. CPL C Bytes: Cycles: Encoding: Operation: 1 1 1 0 1 1 0 0 1 1 CPL (C) ←  (C) CPL bit Bytes: Cycles: Encoding: Operation: 2 1 1 0 1 1 0 0 1 0 bit address CPL (bit) ←  (bit) 1997 Sep 18 26 . No other flags are affected. Example: Port 1 has previously been written with 5DH (01011101B). Description: Example: Encoding: Operation: CPL (A) ←  (A) CPL bit Function: Complement bit The bit variable specified is complemented. not the input pin.

#99H A will leave the carry set and 29H in the Accumulator. The carry and auxiliary carry flags will be cleared. If Accumulator bits 3-0 are greater than nine (xxx1010-xxx1111). 67. depending on initial Accumulator and PSW conditions. this would set the carry flag if there was a carry-out of the high-order bits. resulting in the value 0BEH (10111110B) in the Accumulator.R3 A will first perform a standard two’s-complement binary addition. The true sum 56. The Decimal Adjust instruction will then alter the Accumulator to the value 24H (00100100B). nor does DA A apply to decimal subtraction. since 30 + 99 = 129. Example: The Accumulator holds the value 56H (01010110B) representing the packed BCD digits of the decimal number 56. but wouldn’t clear the carry. ADDC DA A. indicating the packed BCD digits of the decimal number 24. allowing multiple precision decimal addition. producing the proper BCD digit in the high-order nibble. these high-order bits are incremented by six. six is added to the Accumulator. producing two four-bit digits. producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits. Again. The carry flag will be set by the Decimal Adjust instruction.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set DA A Function: Decimal-adjust Accumulator for Addition DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variable (each in packed-BCD format). or if the four high-order bits now exceed nine (1010xxx-111xxxx). the low-order two digits of the decimal sum of 56. OV is not affected. 67. If the Accumulator initially holds 30H (representing the digits of 30 decimal). Register 3 contains the value 67H (01100111B) representing the packed BCD digits of the decimal number 67. Bytes: Cycles: Encoding: Operation: 1 1 1 1 0 1 0 1 0 0 DA –contents of Accumulator are BCD IF [[(A3-0) > 9] ∨ [(AC) = 1]] THEN(A3-0) ← (A3-0) + 6 AND IF [[(A7-4) > 9] ∨ [(C) = 1]] THEN(A7-4) ← (A7-4) + 6 1997 Sep 18 27 . Essentially. The instruction sequence. 60H. but it would not clear the carry flag otherwise. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100. If the carry flag is now set. or 66H to the Accumulator. and the carry-in. this instruction performs the decimal conversion by adding 00H. Description: Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation. Any ADD or ADDC instruction may have been used to perform the addition. indicating that a decimal overflow occurred. 06H. ADD DA A. The carry flag is set. The low-order byte of the sum can be interpreted to mean 30 – 1 = 29. All of this occurs during the one instruction cycle. or if the AC flag is one. the the instruction sequence.. and 1 is 124. BCD variables can be incremented or decremented by adding 01H or 99H.

DEC A Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 1 0 1 0 0 DEC (A) ← (A) – 1 DEC Rn Bytes: Cycles: 1 1 0 0 0 1 1 r r r Encoding: Operation: DEC (Rn) ← (Rn) – 1 DEC direct Bytes: Cycles: 2 1 0 0 0 1 0 1 0 1 direct address Encoding: Operation: DEC (direct) ← (direct) – 1 DEC @Ri Bytes: Cycles: 1 1 0 0 0 1 0 1 1 i Encoding: Operation: DEC ((Ri)) ← ((Ri)) – 1 1997 Sep 18 28 . or register-indirect. An original value of 00H will underflow to 0FFH. No flags are affected. register. not the input pin. The instruction sequence. Internal RAM locations 7EH and 7FH contain 00H and 40H. the value used as the original data will be read from the output data latch. direct. Example: Register 0 contains 7FH (01111111B). respectively. DEC DEC DEC @R0 R0 @R0 will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set DEC byte Function: Decrement The variable indicated is decremented by 1. Four operand addressing modes are allowed: accumulator. Description: Note: When this instruction is used to modify an output port.

Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). Carry and OV will both be cleared. Bytes: Cycles: Encoding: Operation: 1 4 1 0 0 0 0 1 0 0 DIV (A)15-8 ← (A)/(B) (B)7-0 1997 Sep 18 29 . The instruction. since 251 = (13 x 18) + 17. the values returned in the Accumulator and B-register will be undefined and the overflow flag will be set.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set DIV AB Function: Divide DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. register B receives the integer remainder. The carry and OV flags will be cleared. The Accumulator receives the integer part of the quotient. The carry flag is cleared in any case. DIV AB will leave 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B. Description: Exception: if B had originally contained 00H.

and 15H in the three RAM locations. This instruction provides a simple was of executing a program loop a given number of times. The location decremented may be a register or directly addressed byte. The instruction sequence. The instruction sequence. and branches to the address indicated by the second operand if the resulting value is not zero. causing four output pulses to appear at bit 7 of output Port 1. An original value of 00H will underflow to 0FFH.LABEL_2 60H. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC.#8 P1.rel Bytes: Cycles: 3 2 1 1 0 1 0 1 0 1 direct data rel. or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.7 eight times. the value used as the original port data will be read from the output data latch.rel Bytes: Cycles: Encoding: Operation: 2 2 1 1 0 1 1 r r r rel. address DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC) + rel DJNZ direct. two for DJNZ and one to alter the pin.7 R2. DJNZ DJNZ DJNZ 40H.TOGGLE will toggle P1. not the input pins. 6FH. 70H.<rel-addr> Decrement and Jump if Not Zero DJNZ decrements the location indicated by 1. and 60H contain the values 01H.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set DJNZ <byte>. 50H. No flags are affected. and 15H. after incrementing the PC to the first byte of the following instruction.LABEL_3 will cause a jump to the instruction at LABEL_2 with the values 00h. Example: Internal RAM locations 40H. The first jump was not taken because the result was zero. respectively. address Encoding: Operation: DJNZ (PC) ← (PC) + 2 (direct) ← (direct) – 1 IF (direct) > 0 or (direct) < 0 THEN (PC) ← (PC) + rel 1997 Sep 18 30 . Function: Description: Note: When this instruction is used to modify an output port.LABEL_1 50H. Each pulse will last three machine cycles. DJNZ Rn. MOV TOGGLE: CPL DJNZ R2.

Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set INC <byte> Function: Increment INC increments the indicated variable by 1. Three addressing modes are allowed: register. INC INC INC @R0 R0 @R0 will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 41H. the value used as the original port data will be read from the output data latch. or register-indirect. respectively. An original value of 0FFH will overflow to 00H. Description: Note: When this instruction is used to modify an output port. Internal RAM locations 7EH and 7FH contain 0FFH and 40H. direct. Example: Register 0 contains 7EH (01111110B). INC A Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 0 0 1 0 0 INC (A) ← (A) + 1 INC Rn Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 0 1 r r r INC (Rn) ← (Rn) + 1 INC direct Bytes: Cycles: Encoding: Operation: 2 1 0 0 0 0 0 1 0 1 direct address INC (direct) ← (direct) + 1 INC @Ri Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 0 0 1 1 i INC ((Ri)) ← ((Ri)) + 1 1997 Sep 18 31 . No flags are affected. The instruction sequence. not the input pins.

The Accumulator holds 56 (01010110B). The instruction sequence. Example: Registers DPH and DPL contain 12H and 0FEH. INC INC INC DPTR DPTR DPTR Description: will change DPH and DPL to 13H and 01H. after incrementing the PC to the first byte of the next instruction.LABEL1 ACC. an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment the high-order byte (DPH). respectively. No flags are affected.2. The bit tested is not modified. Bytes: Cycles: Encoding: Operation: 1 2 1 0 1 0 0 0 1 1 INC (DPTR) ← (DPTR) + 1 JB bit. A 16-bit increment (modulo 216) is performed. Bytes: Cycles: Encoding: Operation: 3 2 0 0 1 0 0 0 0 0 bit address rel.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set INC DPTR Function: Increment Data Pointer Increment the 16-bit data pointer by 1. JB JB P1. The instruction sequence.2.LABEL2 Description: Example: will cause program execution to branch to the instruction at label LABEL2. No flags are affected. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC. otherwise proceed with the next instruction. The data present at input port 1 is 11001010B. address JB (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + rel 1997 Sep 18 32 . jump to the address indicated. This is the only 16-bit register which can be incremented.rel Function: Jump if Bit set If the indicated bit is a one.

The bit will not be cleared if it is already a zero. with the Accumulator modified to 52H (01010010B). No flags are affected. Bytes: Cycles: Encoding: Operation: 3 2 0 0 0 1 0 0 0 0 bit address rel. Note: When this instruction is used to test an output pin. JBC JBC ACC. branch to the address indicated. address JBC (PC) ← (PC) + 3 IF (bit) = 1 THEN (bit) ← 0 (PC) ← (PC) + rel JC rel Function: Jump if Carry is set If the carry flag is set. after incrementing the PC to the first byte of the next instruction. otherwise proceed with the next instruction. The instruction sequence.2.LABEL1 ACC. The carry flag is cleared. after incrementing the PC twice. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC. branch to the address indicated. address JC (PC) ← (PC) + 2 IF (C) = 1 THEN (PC) ← (PC) + rel 1997 Sep 18 33 . No flags are affected. otherwise proceed with the next instruction. Example: The Accumulator holds 56H (01010110B). Bytes: Cycles: Encoding: Operation: 2 2 0 1 0 0 0 0 0 0 rel. The instruction sequence. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set JBC bit.rel Function: Jump if Bit is set and Clear bit If the indicated bit is a one. not the input pin. JC CPL JC LABEL1 C LABEL2 Description: Example: will set the carry and cause program execution to continue at the instruction identified by the label LABEL2. the value used as the original data will read from the output data latch.3.LABEL2 Description: will cause program execution to continue at the instruction identified by the LABEL2.

No flags are affected.LABEL1 ACC. Remember that AJMP is a two-byte instruction. The bit tested is not modified.rel Function: Jump if Bit Not set If the indicated bit is a zero. JNB JNB P1.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set JMP @A+DPTR Function: Jump indirect Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer. No flags are affected.#JMP_TBL @A+DPTR LABEL0 LABEL1 LABEL2 LABEL3 Description: Example: JMP_TBL: If the Accumulator equals 04H when starting this sequence. This will be the address for subsequent instruction fetches. Neither the Accumulator nor the Data Pointer is altered. and load the resulting sum to the program counter. The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP_TBL: MOV JMP AJMP AJMP AJMP AJMP DPTR. The data present at input port 1 is 11001010B. Bytes: Cycles: Encoding: Operation: 3 2 0 0 1 1 0 0 0 0 bit address rel.3. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits.LABEL2 Description: Example: will cause program execution to continue at the instruction at label LABEL2. otherwise proceed with the next instruction. An even number from 0 to 6 is in the Accumulator. branch to the indicated address. Bytes: Cycles: Encoding: Operation: 1 2 0 1 1 1 0 0 1 1 JMP (PC) ← (A) + (DPTR) JNB bit. address JNB (PC) ← (PC) + 3 IF (bit) = 0 THEN (PC) ← (PC) + rel 1997 Sep 18 34 .3. execution will jump to label LABEL2. The instruction sequence. after incrementing the PC to the first byte of the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC. so the jump instructions start at every other address. The Accumulator holds 56H (01010110B).

The instruction sequence. JNZ INC JNZ LABEL1 A LABEL2 Description: Example: will set the Accumulator to 01H and continue at label LABEL2. The Accumulator originally holds 00H.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set JNC rel Function: Jump if Carry Not set If the carry flag is a zero. JNC CPL JNC LABEL1 C LABEL2 Description: Example: will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2. Bytes: Cycles: Encoding: Operation: 2 2 0 1 0 1 0 0 0 0 rel. after incrementing the PC twice. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC. otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC. The Accumulator is not modified. The instruction sequence. Bytes: Cycles: Encoding: Operation: 2 2 0 1 1 1 0 0 0 0 rel. after incrementing the PC twice to point to the next instruction. branch to the address indicated. address JNC (PC) ← (PC) + 2 IF (C) = 0 THEN (PC) ← (PC) + rel JNZ rel Function: Jump if Accumulator Not Zero If any bit of the Accumulator is a one. branch to the indicated address. No flags are affected. The carry flag is set. otherwise proceed with the next instruction. The carry flag is not modified. address JNZ (PC) ← (PC) + 2 IF A ≠ 0 THEN (PC) ← (PC) + rel 1997 Sep 18 35 .

after incrementing the PC twice. No flags are affected. Bytes: 3 2 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0 Function: Description: Example: Cycles: Encoding: Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC7-0) (SP) ← (SP) + 1 ((SP)) ← (PC15-8) (PC) ← addr15-0 1997 Sep 18 36 . incrementing the Stack Pointer by two. Bytes: Cycles: Encoding: Operation: 2 2 0 1 1 0 0 0 0 0 rel. internal RAM locations 08H and 09H will contain 26H and 01H. LCALL SUBRTN at location 0123H. Initially the Stack Pointer equals 07H. address JZ (PC) ← (PC) + 2 IF A = 0 THEN (PC) ← (PC) + rel LCALL addr16 Long Call LCALL calls a subroutine located at the indicated address. respectively. and the PC will contain 1235H. The Accumulator originally holds 01H. The high-order and low-order bytes of the PC are then loaded. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC. Program execution continues with the instruction at this address. with the second and third bytes of the LCALL instruction. branch to the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first). the Stack Pointer will contain 09H. The subroutine may therefore begin anywhere in the full 64k-byte program memory address space. No flags are affected. The instruction sequence. JZ DEC JZ LABEL1 A LABEL2 Description: Example: will change the Accumulator to 00H and cause program execution to continue at the instruction identified by the label LABEL2. The Accumulator is not modified.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set JZ rel Function: Jump if Accumulator Zero If all bits of the Accumulator are zero. otherwise proceed with the next instruction. After executing the instruction. The label “SUBRTN” is assigned to program memory location 1234H.

by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes.B < = 10H . MOV A.P1 P2. 40H in both the Accumulator and register 1.Rn Bytes: Cycles: Encoding: Operation: 1 1 1 1 1 0 1 r r r MOV (A) ← (Rn) 1997 Sep 18 37 .@R0 R1.#30H A. No other register or flag is affected. Example: Internal RAM location 30H holds 40H. The instruction sequence.P2 #0CAH Function: Description: leaves the value 30H in register 0.R1 < = 40H . The instruction.R0 < = 30H . The destination may therefore be anywhere in the full 64k program memory address space.@R1 @R1.A < = 40H . 10H in register B.P1 . The source byte is not affected.RAM (40H) < = 0CAH .A B. and 0CAH (11001010B) both in RAM location 40H and output on port 2. The label “JMPADR” is assigned to the instruction at program memory location 1234H.<src-byte> Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand.) Long Jump LJMP causes an unconditional branch to the indicated address. This is by far the most flexible operation. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). Fifteen combinations of source and destination addressing modes are allowed.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set LJMP addr16 (Implemented in 87C751 and 87C752 for in-circuit emulation only. LJMP Bytes: Cycles: 3 2 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 JMPADR at location 0123H will load the program counter with 1234H. No flags are affected. Function: Description: Example: Encoding: Operation: LJMP (PC) ← addr15-0 MOV <dest-byte>. MOV MOV MOV MOV MOV MOV R0.

direct Bytes: Cycles: 2 1 1 1 1 0 0 1 0 1 direct address Encoding: Operation: MOV (A) ← (direct) MOV A.#data Bytes: Cycles: 2 1 0 1 1 1 1 r r r immediate data Encoding: Operation: MOV (Rn) ← #data *MOV A. 1997 Sep 18 38 .A Bytes: Cycles: 1 1 1 1 1 1 1 r r r Encoding: Operation: MOV (Rn) ← (A) MOV Rn.@Ri Bytes: Cycles: 1 1 1 1 1 0 0 1 1 i Encoding: Operation: MOV (A) ← ((Ri)) MOV A.direct Bytes: Cycles: 2 2 1 0 1 0 1 r r r direct address Encoding: Operation: MOV (Rn) ← (direct) MOV Rn.ACC is not a valid instruction.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set *MOV A.#data Bytes: Cycles: 2 1 0 1 1 1 0 1 0 0 immediate data Encoding: Operation: MOV (A) ← #data MOV Rn.

A Bytes: Cycles: 2 1 1 1 1 1 0 1 0 1 direct address Encoding: Operation: MOV (direct) ← (A) MOV direct.A Bytes: Cycles: 1 1 1 1 1 1 0 1 1 i Encoding: Operation: MOV ((Ri)) ← (A) 1997 Sep 18 39 .#data Bytes: Cycles: 3 2 0 1 1 1 0 1 0 1 direct address immediate data Encoding: Operation: MOV (direct) ← #data MOV @Ri. (src) dir.direct Bytes: Cycles: 3 2 1 0 0 0 0 1 0 1 dir. addr. (dest) Encoding: Operation: MOV (direct) ← (direct) MOV direct.@Ri Bytes: Cycles: 2 2 1 0 0 0 0 1 1 i direct address Encoding: Operation: MOV (direct) ← ((Ri)) MOV direct.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set MOV direct.Rn Bytes: Cycles: 2 2 1 0 0 0 1 r r r direct address Encoding: Operation: MOV (direct) ← (Rn) MOV direct. addr.

C Function: Description: Example: will leave the carry cleared and change Port 1 to 39H (00111001B). MOV C.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set MOV @Ri.C Bytes: Cycles: 2 2 1 0 0 1 0 0 1 0 bit address Encoding: Operation: MOV (bit) ← (C) 1997 Sep 18 40 . MOV MOV MOV P1.#data Bytes: Cycles: 2 1 0 1 1 1 0 1 1 i immediate data Encoding: Operation: MOV ((Ri)) ← #data MOV <dest-bit>. The instruction sequence. The carry flag is originally set.direct Bytes: Cycles: 2 2 1 0 1 0 0 1 1 i direct address Encoding: Operation: MOV ((Ri)) ← (direct) MOV @Ri.3. No other register or flag is affected. the other may be any directly addressable bit.C C. One of the operands must be the carry flag.bit Bytes: Cycles: Encoding: Operation: 2 1 1 0 1 0 0 0 1 0 bit address MOV (C) ← (bit) MOV bit. The data present at input Port 3 is 11000101B.P3. The data previously written to output Port 1 is 35H (00110101B).<src-bit> Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand.3 P1.2.

it will return with 77H in the Accumulator. the PC is incremented to the address of the following instruction before being added with the Accumulator. A value between 0 and 3 is in the Accumulator.@A+DPTR Bytes: Cycles: Encoding: Operation: 1 2 1 0 0 1 0 0 1 1 MOVC (A) ← ((A) + (DPTR)) 1997 Sep 18 41 . The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive: REL_PC: INC MOVC RET DB DB DB DB A A. data15-8 immed. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. Example: The instruction. while the third byte (DPL) holds the low-order byte. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register. The second byte (DPH) is the high-order byte. No flags are affected. The 16-bit constant is loaded into the second and third bytes of the instruction.@A+PC 66H 77H 88H 99H Function: Description: Example: If the subroutine is called with the Accumulator equal to 01H. No flags are affected. If several bytes of code separated the MOVC from the table.#1234H will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H. This is the only instruction which moves 16 bits of data at once. Function: Description: Encoding: Operation: MOV (DPTR) ← (#data15-0) DPH DPL ← #data15-8 #data7-0 MOVC A. or constant from program memory.#data16 Load Data Pointer with a 16-bit constant The Data Pointer is loaded with the 16-bit constant indicated.@A+<base-reg> Move Code byte The MOVC instructions load the Accumulator with a code byte. The INC A before the MOVC instruction is needed to “get around” the RET instruction above the table. MOVC A. otherwise the base register is not altered. In the latter case.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set MOV DPTR. MOV Bytes: Cycles: 3 2 1 0 0 1 0 0 0 0 immed. which may be either the Data Pointer or the PC. the corresponding number would be added to the Accumulator instead. data7-0 DPTR.

MOVX A.A copies the value 56H into both the Accumulator and external RAM location 12H. differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the second type of MOVX instruction. since no additional instructions are needed to set up the output ports. P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) with data. hence the “X” appended to MOV.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set MOVC A. The Data Pointer generates a sixteen-bit address. Location 34H of the external RAM holds the value 56H. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. This form is faster and more efficient when accessing very large data arrays (up to 64k bytes).@Ri Bytes: Cycles: Encoding: Operation: 1 2 1 1 1 0 0 0 1 i MOVX (A) ← ((Ri)) MOVX A. Port 3 provides control lines for the external RAM. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays.<src-byte> Move External (Not implemented in the 8XC752 or 8XC752) Function: Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory. Registers 0 and 1 contain 12H and 34H. The P2 Special Function Register retains its previous contents while the P2 output buffers are emitting the contents of DPH. It is possible in some situations to mix the two MOVX types. the contents of R0 or R1 in the current register bank provide an eight-bit address multiplexed with data on P0. MOVX MOVX A. port pins can be used to output higher-order address bits. The instruction sequence. or with code to output high-order address bits to P2 followed by a MOVX instruction using R0 or R1. There are two types of instructions. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer.@A+PC Bytes: Cycles: 1 2 1 0 0 0 0 0 1 1 Encoding: Operation: MOVC (PC) ← (PC) + 1 (A) ← ((A) + (PC)) MOVX <dest-byte>.@R1 @R0. Ports 1 and 2 are used for normal I/O. In the first type.@DPTR Bytes: Cycles: 1 2 1 1 1 0 0 0 0 0 Encoding: Operation: MOVX (A) ← ((DPTR)) 1997 Sep 18 42 . These pins would be controlled by an output instruction preceding the MOVX.

800 (3200H). Originally the Accumulator holds the value 80 (50H). Bytes: Cycles: 1 4 1 0 1 0 0 1 0 0 Description: Example: Encoding: Operation: MUL (A)7-0 ← (A) x (B) (B)15-8 1997 Sep 18 43 . Register B holds the value 160 (0A0H).A Bytes: Cycles: 1 2 1 1 1 1 0 0 1 i Encoding: Operation: MOVX ((Ri)) ← (A) MOVX @DPTR. otherwise it is cleared. The carry flag is always cleared. The low-order byte of the sixteen-bit product is left in the Accumulator. The overflow flag is set. If the product is greater than 255 (0FFH) the overflow flag is set.A Bytes: Cycles: 1 2 1 1 1 1 0 0 0 0 Encoding: Operation: MOVX ((DPTR)) ← (A) MUL AB Function: Multiply MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. carry is cleared.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set MOVX @Ri.The instruction. MUL AB will give the product 12. and the high-order byte in B. so B is changed to 32H (00110010B) and the Accumulator is cleared.

When the destination is a directly addressed byte. CLR NOP NOP NOP NOP SETB Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 0 0 0 0 0 P2. This may be done (assuming are enabled) with the instruction sequence. the source can be the Accumulator or immediate data. ORL P1. ORL A. storing the results in the destination byte. the source can use register. no registers or flags are affected. No flags are affected.#00110010B will set bits 5. so four additional cycles must be inserted. the instruction can set combinations of bits in any RAM location or hardware register. The instruction. direct. Description: Note: When this instruction is used to modify an output port.7 P2. 4.R0 will leave the Accumulator holding the value 0D7H (11010111B). and 1 of output Port 1. not the input pins. when the destination is a direct address. Other than the PC. or immediate addressing. The two operands allow six addressing mode combinations.Rn Bytes: Cycles: Encoding: Operation: 1 1 0 1 0 0 1 r r r ORL (A) ← (A) ∨ (Rn) 1997 Sep 18 44 . register-indirect. The pattern of bits to be set is determined by a mask byte.7 NOP (PC) ← (PC) + 1 ORL <dest-byte>. the value used as the original port data will be read from the output data latch. ORL A. Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the instruction.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set NOP Function: Description: Example: No Operation Execution continues at the following instruction. which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. A simple SETB/CLR sequence would generate a one-cycle pulse. When the destination is the Accumulator.<src-byte> Function: Logical-OR for byte variables ORL performs the bitwise logical-OR operation between the indicated variables. It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles.

#data Bytes: Cycles: 3 2 0 1 0 0 0 0 1 1 direct address immediate data Encoding: Operation: ORL (direct) ← (direct) ∨ #data 1997 Sep 18 45 .@Ri Bytes: Cycles: 1 1 0 1 0 0 0 1 1 i Encoding: Operation: ORL (A) ← (A) ∨ ((Ri)) ORL A.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ORL A.direct Bytes: Cycles: 2 1 0 1 0 0 0 1 0 1 direct address Encoding: Operation: ORL (A) ← (A) ∨ (direct) ORL A.A Bytes: Cycles: 2 1 0 1 0 0 0 0 1 0 direct address Encoding: Operation: ORL (direct) ← (direct) ∨ (A) ORL direct.#data Bytes: Cycles: 2 1 0 1 0 0 0 1 0 0 immediate data Encoding: Operation: ORL (A) ← (A) ∨ #data ORL direct.

P1. leave the carry in its current state otherwise.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set ORL C. but the source bit itself is not affected.ACC.<src-bit> Function: Logical-OR for bit variables Set the carry flag if the Boolean value is a logical 1. ACC./bit Bytes: Cycles: 2 2 1 0 1 0 0 0 0 0 bit address Encoding: Operation: ORL (C) ← (C) ∨ (bit) 1997 Sep 18 46 . BIT 7 . No other flags are affected. Description: Example: ORL C. A slash (“/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value. or OV = 0: ORL ORL ORL C.bit Bytes: Cycles: 2 2 0 1 1 1 0 0 1 0 bit address Encoding: Operation: ORL (C) ← (C) ∨ (bit) ORL C.OR CARRY WITH THE INVERSE OF OV./OV .0 C.LOAD CARRY WITH INPUT PIN P10 .7 C.7 = 1. Set the carry flag if and only if P1.0 = 1.OR CARRY WITH THE ACC.

At this point the instruction. POP POP DPH DPL Description: Example: will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. The instruction sequence. The Data Pointer holds the value 0123H. Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). and internal RAM locations 30H through 32H contain the values 20H. The instruction sequence. respectively. and the Stack Pointer is decremented by one. Bytes: Cycles: Encoding: Operation: 2 2 1 1 0 0 0 0 0 0 direct address PUSH (SP) ← (SP) + 1 ((SP)) ← (direct) 1997 Sep 18 47 . PUSH PUSH DPL DPH Function: Description: Example: will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM locations 0AH and 0BH. 23H. Bytes: Cycles: Encoding: Operation: 2 2 1 1 0 1 0 0 0 0 direct address POP (direct) ← ((SP)) (SP) ← (SP) – 1 PUSH direct Push onto stack The Stack Pointer is incremented by one. The value read is then transferred to the directly addressed byte indicated. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. The Stack Pointer originally contains the value 32H. Otherwise no flags are affected.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set POP direct Function: Pop from stack The contents of the internal RAM location addressed by the Stack Pointer is read. respectively. POP SP will leave the Stack Pointer set to 20H. and 01H. No flags are affected. On entering an interrupt routine the Stack Pointer contains 09H.

Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set RET Function: Description: Return from subroutine RET pops the high. decrementing the Stack Pointer by two. Program execution continues at the resulting address. and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. An interrupt was detected during the instruction ending at location 0122H. If a lower. generally the instruction immediately following an ACALL or LCALL.and low-order bytes of the PC successively from the stack. The Stack Pointer is left decremented by two. Bytes: Cycles: Encoding: Operation: 1 2 0 0 1 0 0 0 1 0 Example: RET (PC15-8) ← ((SP)) (SP) ← (SP) – 1 (PC7-0) ← ((SP)) (SP) ← (SP) – 1 RETI Function: Description: Return from interrupt RETI pops the high. The Stack Pointer originally contains the value 0BH. No other registers are affected. Program execution continues at the resulting address. The instruction. RET will leave the Stack Pointer equal to the value 09H. respectively. that one instruction will be executed before the pending interrupt is processed. Internal RAM locations 0AH and 0BH contain the values 23H and 01H. the PSW is not automatically restored to its pre-interrupt status. The instruction. Internal RAM locations 0AH and 0BH contain the values 23H and 01H. RETI will leave the Stack Pointer equal to 09H and return program execution to location 0123H. Program execution will continue at location 0123H.or same-level interrupt has been pending when the RETI instruction is executed. which is generally the instruction immediately after the point at which the interrupt request was detected.and low-order bytes of the PC successively from the stack. The Stack Pointer originally contains the value 0BH. No flags are affected. respectively. Bytes: Cycles: Encoding: Operation: 1 2 0 0 1 1 0 0 1 0 Example: RETI (PC15-8) ← ((SP)) (SP) ← (SP) – 1 (PC7-0) ← ((SP)) (SP) ← (SP) – 1 1997 Sep 18 48 .

n = 0 – 6 (A0) ← (A7) RLC A Function: Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. the original state of the carry flag moves into the bit 0 position. Bit 7 moves into the carry flag. The instruction. RL Bytes: Cycles: Encoding: Operation: 1 1 0 0 1 0 0 0 1 1 A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected. Bit 7 is rotated into the bit 0 position. and the carry is zero. No other flags are affected. The instruction. Description: Example: Encoding: Operation: RLC (An+1) ← (An). n = 0 – 6 (A0) ← (C) (C) ← (A7) 1997 Sep 18 49 . The Accumulator holds the value 0C5H (11000101B).Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set RL A Function: Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left. RLC Bytes: Cycles: 1 1 0 0 1 1 0 0 1 1 A leaves the Accumulator holding the value 8AH (10001010B) with the carry set. The Accumulator holds the value 0C5H (11000101B). Description: Example: RL (An+1) ← (An). No flags are affected.

n = 0 – 6 (A7) ← (C) (C) ← (A0) 1997 Sep 18 50 . the original state of the carry flag moves into the bit 7 position. RR Bytes: Cycles: Encoding: Operation: 1 1 0 0 0 0 0 0 1 1 A leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. n = 0 – 6 (A7) ← (A0) RRC A Function: Rotate Accumulator Right through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. The instruction. RRC Bytes: Cycles: 1 1 0 0 0 1 0 0 1 1 A leaves the Accumulator holding the value 62 (01100010B) with the carry set.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set RR A Function: Rotate Accumulator Right The eight bits in the Accumulator are rotated one bit to the right. The Accumulator holds the value 0C5H (11000101B). Bit 0 moves into the carry flag. No flags are affected. Bit 0 is rotated into the bit 7 position. No other flags are affected. Description: Example: Encoding: Operation: RRC (An) ← (An+1). and the carry is zero. The instruction. Description: Example: RR (An) ← (An+1). The Accumulator holds the value 0C5H (11000101B).

Therefore. SETB SETB C P1. the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. (Note: Under the above conditions the instruction following SJMP will be at 102H. Output Port 1 has been written with the value 34H (00110100B).) Bytes: Cycles: 2 2 1 0 0 0 0 0 0 0 rel. The label “RELADR” is assigned to an instruction at program memory location 0123H.0 Function: Description: Example: will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B). After the instruction is executed. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC. SETB C Bytes: Cycles: Encoding: Operation: 1 1 1 1 0 1 0 0 1 1 SETB (C) ← 1 SETB bit Bytes: Cycles: 2 1 1 1 0 1 0 0 1 0 bit address Encoding: Operation: SETB (bit) ← 1 SJMP rel Short Jump Program control branches unconditionally to the address indicated. an SJMP with a displacement of 0FEH would be a one-instruction infinite loop. SJMP RELADR will assemble into location 0100H. the PC will contain the value 0123H. The instruction. Therefore. the displacement byte of the instruction will be the relative offset (0123H-0102H) = 21H. No other flags are affected. Put another way. after incrementing the PC twice. address Function: Description: Example: Encoding: Operation: SJMP (PC) ← (PC) + 2 (PC) ← (PC) + rel 1997 Sep 18 51 . The carry flag is cleared. The instructions.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set SETB <bit> Set Bit SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit.

<src-byte> Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator. but not bit 6. and the carry flag is set. or into bit 7.#data Bytes: Cycles: 2 1 1 0 0 1 0 1 0 0 immediate data Encoding: Operation: SUBB (A) ← (A) – (C) – (#data) 1997 Sep 18 52 .Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set SUBB A. it should be explicitly cleared by a CLR C instruction SUBB A. direct. or a positive result when a positive number is subtracted from a negative number.direct Bytes: Cycles: 2 1 1 0 0 1 0 1 0 1 direct address Encoding: Operation: SUBB (A) ← (A) – (C) – (direct) SUBB A. and cleared otherwise. (If C was set before executing a SUBB instruction. leaving the result in the Accumulator. and clears C otherwise. The instruction. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7. Notice that 0C9H minus 54H is 75H The difference between this and the above result is due to the carry (borrow) flag being set before the operation. so the carry is subtracted from the Accumulator along with the source operand.R2 will leave the value 74H (01110100B) in the Accumulator.Rn Bytes: Cycles: 1 1 1 0 0 1 1 r r r Encoding: Operation: SUBB (A) ← (A) – (C) – (Rn) SUBB A. SUBB A.) AC is set if a borrow is needed for bit 3. register 2 holds 54H (01010100B). or immediate. this indicates that a borrow was needed for the previous step in a multiple precision subtraction. Function: Description: Example: The Accumulator holds 0C9H (11001001B). register-indirect. but not into bit 7. If the state of the carry is not known before starting a single or multiple-precision subtraction. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value. with the carry flag and AC cleared but OV set. The source operand allows four addressing modes: register.@Ri Bytes: Cycles: 1 1 1 0 0 1 0 1 1 i Encoding: Operation: SUBB (A) ← (A) – (C) – (Ri) SUBB A. OV is set if a borrow is needed into bit 6.

The Accumulator holds the value 0C5H (11000101B).direct Bytes: Cycles: 2 1 1 1 0 0 0 1 0 1 direct address Encoding: Operation: XCH → (A) ← (direct) XCH A. SWAP Bytes: Cycles: 1 1 1 1 0 0 0 1 0 0 A leaves the Accumulator holding the value 5CH (01011100B).Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set SWAP A Swap nibbles within the Accumulator SWAP A interchanges the low.@Ri Bytes: Cycles: 1 1 1 1 0 0 0 1 1 i Encoding: Operation: XCH → (A) ← ((Ri)) 1997 Sep 18 53 .<byte> Function: Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable. No flags are affected. R0 contains the address 20H. direct. The Accumulator holds the value 3FH (00111111B). The instruction. The operation can also be thought of as a four-bit rotate instruction. Function: Description: Example: Encoding: Operation: SWAP → (A3-0) ← (A7-4) XCH A.and high-order nibbles (four-bit fields) of the Accumulator (bits 3-0 and bits 7-4). Description: Example: XCH A. XCH A. or register-indirect addressing. The source/destination operand can use register.Rn Bytes: Cycles: 1 1 1 1 0 0 1 r r r Encoding: Operation: XCH → (A) ← (Rn) XCH A. at the same time writing the original Accumulator contents to the indicated variable. The instruction.@R0 will leave the RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the Accumulator. Internal RAM location 20H holds the value 75H (01110101B).

generally representing a hexadecimal or BCD digit. or immediate addressing. Internal RAM location 20H holds the value 75H (01110101B). No flags are affected. The instruction. When the destination is a directly addressed byte. Function: Description: Example: Encoding: Operation: XCHD → (A3-0) ← ((Ri3-0)) XRL <dest-byte>.<src-byte> Function: Logical Exclusive-OR for byte variables XRL performs the bitwise logical Exclusive-OR operation between the indicated variables.#00110001B will complement bits 5. the source can use register. storing the results in the destination. when the destination is a direct address. XRL A. with that of the internal RAM location indirectly addressed by the specified register. this instruction can complement combinations of bits in any RAM location or hardware register. The two operands allow six addressing mode combinations. either a constant contained in the instruction or a variable computed in the Accumulator at run-time.) Example: If the Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then the instruction.@Ri Exchange Digit XCHD exchanges the low-order nibble of the Accumulator (bits 3-0). the source can be the Accumulator or immediate data. and 0 of output Port 1. XRL P1. Description: 1997 Sep 18 54 . the value used as the original port data will be read from the output data latch. When the destination is the Accumulator. The instruction. XCHD Bytes: Cycles: 1 1 1 1 0 1 0 1 1 i A.R0 will leave the Accumulator holding the value 69H (01101001B). The high-order nibbles (bits 7-4) of each register are not affected.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set XCHD A. 4. direct. The pattern of bits to be complemented is then determined by a mask byte. register-indirect. R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). not the input pins. No flags are affected. (Note: When this instruction is used to modify an output port.@R0 will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator.

#data Bytes: Cycles: 2 1 0 1 1 0 0 1 0 0 immediate data Encoding: Operation: XRL (A) ← (A) ∨ #data XRL direct.@Ri Bytes: Cycles: 1 1 0 1 1 0 0 1 1 i Encoding: Operation: XRL (A) ← (A) ∨ (Ri) XRL A.A Bytes: Cycles: 2 1 0 1 1 0 0 0 1 0 direct address Encoding: Operation: XRL (direct) ← (direct) ∨ (A) XRL direct.Philips Semiconductors 80C51 Family 80C51 family programmer’s guide and instruction set XRL A.direct Bytes: Cycles: 2 1 0 1 1 0 0 1 0 1 direct address Encoding: Operation: XRL (A) ← (A) ∨ (direct) XRL A.Rn Bytes: Cycles: 1 1 0 1 1 0 1 r r r Encoding: Operation: XRL (A) ← (A) ∨ (Rn) XRL A.#data Bytes: Cycles: 3 2 0 1 1 0 0 0 1 1 direct address immediate data Encoding: Operation: XRL (direct) ← (direct) ∨ #data 1997 Sep 18 55 .

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