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FEATURES 330 MSPS Throughput Rate Triple 8-Bit DACs RS-343A/RS-170 Compatible Output Complementary Outputs DAC Output Current Range 2 to 26 mA TTL Compatible Inputs Internal Reference (1.23 V) Single-Supply 5 V/3.3 V Operation 48-Lead LQFP Package Low Power Dissipation (30 mW Min @ 3 V) Low Power Standby Mode (6 mW Typ @ 3 V) Industrial Temperature Range (–40°C to +85°C) APPLICATIONS Digital Video Systems High Resolution Color Graphics Digital Radio Modulation Image Processing Instrumentation Video Signal Reconstruction

CMOS, 330 MHz Triple 8-Bit High Speed Video DAC ADV7125
FUNCTIONAL BLOCK DIAGRAM
VAA BLANK SYNC DATA REGISTER

BLANK AND SYNC LOGIC IOR DAC IOR IOG 8 DAC IOG IOB DAC IOB VOLTAGE REFERENCE CIRCUIT

R7–R0

8

8

G7–G0

8

DATA REGISTER

B7–B0

8

DATA REGISTER

8

PSAVE CLOCK

POWER-DOWN MODE

VREF

ADV7125
GND RSET COMP

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The ADV®7125 is a triple high speed, digital-to-analog converter on a single monolithic chip. It consists of three high speed, 8-bit video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. The ADV7125 has three separate 8-bit-wide input ports. A single 5 V/3.3 V power supply and clock are all that are required to make the part functional. The ADV7125 has additional video control signals, composite SYNC and BLANK, as well as a powersave mode. The ADV7125 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7125 is available in a 48-lead LQFP package.

1. 330 MSPS (3.3 V only) throughput 2. Guaranteed monotonic to eight bits 3. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170

ADV is a registered trademark of Analog Devices, Inc.

REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

RSET = 560 . VIL Input Current.62 mA NOTES 1 Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz.ADV7125–SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage. VIH Input Low Voltage. COUT Offset Error Gain Error2 VOLTAGE REFERENCE (Ext. All specifications TMIN to TMAX1. 4 These max/min specifications are guaranteed by characterization in the 4.25 +1 +1 Guaranteed Monotonic VIN = 0.25 V range.5 18.025 +5. CL = 10 pF.0 1. VREF = 1. 3 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.5 18 67 8 2.) Reference Range.9896.4 ± 0.235 3. Sync = High R/G/B DAC. 0°C to +70°C at 240 MHz and 330 MHz. where Ideal = V REF/RSET × K × (FFH) × 4 and K = 7.1 0.5 5 1.4 0. ROUT Output Capacitance.0 1. Digital.35 9 15 25 72 5. VREF POWER DISSIPATION Digital Supply Current3 Digital Supply Current3 Digital Supply Current3 Analog Supply Current Analog Supply Current Standby Supply Current4 Power Supply Rejection Ratio Min 8 –1 –1 2 –1 20 10 2. –2– REV.0 1.12 1.75 V to 5.4 10. 0 .) Typ Max Unit Bits LSB LSB V V µA µA pF mA mA % V kΩ pF % FSR % FSR V mA mA mA mA mA mA %/% fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz RSET = 530 Ω RSET = 4933 Ω PSAVE = Low. Sync = Low IOUT = 0 mA Tested with DAC Output = 0 V FSR = 18.025 –5.0 0. CIN ANALOG OUTPUTS Output Current Output Current DAC-to-DAC Matching Output Compliance Range. and Control Inputs at VDD Test Conditions1 ± 0.1 +0. and Int.235 V. unless otherwise noted. 2 Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100). TJ MAX = 110 C. Specifications subject to change without notice. VOC Output Impedance.0 2.0 V or VDD Green DAC.8 +1 (VAA = 5 V ± 5%.5 26. IIN PSAVE Pull-Up Current Input Capacitance.0 0 100 10 –0.

CL = 10 pF. VOC Output Impedance. 4 Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.6 V.8 –1 20 10 2. CIN ANALOG OUTPUTS Output Current Output Current DAC-to-DAC Matching Output Compliance Range. 0 –3– . VREF = 1. Sync = Low 0 Tested with DAC Output = 0 V FSR = 18.6 V range.0 0.0 V to 3.12 1. TJ MAX = 110 C.0 12.3 V ELECTRICAL CHARACTERISTICS1 Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage. COUT Offset Error Gain Error3 VOLTAGE REFERENCE (Ext. REV.5 18. Digital. VIH Input Low Voltage. unless otherwise noted.5 ± 0.5 +1 VIN = 0.0 1.ADV7125 3. 0°C to +70°C at 240 MHz and 330 MHz. 2 Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz.) Typ Max 8 +1 +1 Unit Bits LSB LSB V V µA µA pF mA mA % V kΩ pF % FSR % FSR V V 5. Specifications subject to change without notice.1 0.0 V or VDD Green DAC.0 V to 3. RSET = 560 . Sync = High R/G/B DAC.235 V. VREF POWER DISSIPATION Digital Supply Current4 Digital Supply Current4 Digital Supply Current4 Digital Supply Current4 Analog Supply Current Analog Supply Current Standby Supply Current Power Supply Rejection Ratio Min (VAA = 3.0 2.35 NOTES 1 These max/min specifications are guaranteed by characterization in the 3.) Reference Range. where Ideal = V REF/RSET × K × (FFH) × 4 and K = 7.1 1.9896. VREF VOLTAGE REFERENCE (Int.2 6.0 15 72 5.235 1.5 mA mA mA mA mA mA mA %/% fCLK = 50 MHz fCLK = 140 MHz fCLK = 240 MHz fCLK = 330 MHz RSET = 560 Ω RSET = 4933 Ω PSAVE = Low.) Reference Range. ROUT Output Capacitance. and Control Inputs at VDD Test Conditions2 RSET = 680 Ω RSET = 680 Ω RSET = 680 Ω –1 –1 2.25 0.0 0 70 10 0 0 1.4 26.235 2. IIN PSAVE Pull-Up Current Input Capacitance.0 ± 0. All specifications TMIN to TMAX2. VIL Input Current.5 11 16 67 8 2. 3 Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100).62 mA 1.

VREF = 1. All specifications TMIN to TMAX3. t106 0. 3 Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz. t85 Analog Output Skew.0 10 MHz MHz MHz ns ns ns ns ns ns ns ns ns Clock Cycles ns 50 MHz Grade 140 MHz Grade 240 MHz Grade fCLK_MAX = 240 MHz fCLK_MAX = 240 MHz fCLK_MAX = 140 MHz fCLK_MAX = 140 MHz fCLK_MAX = 50 MHz fCLK_MAX = 50 MHz NOTES 1 Timing specifications are measured with input levels of 3. 2 These maximum and minimum specifications are guaranteed over this range.5 1.85 2.0 (VAA = 5 V ± 5%2.5 0.0 15 1 Max Unit ns ns ns ns .5 0. 0°C to +70°C at 240 MHz.5 4.5 1. t46 Clock Pulsewidth Low. 7 fCLK max specification production tested at 125 MHz and 5 V. t74 Analog Output Transition Time.0 2 1.ADV7125 5 V TIMING SPECIFICATIONS1 Parameter ANALOG OUTPUTS Analog Output Delay. t5 Pipeline Delay. Limits specified here are guaranteed by characterization.17 1. 0 . RSET = 560 unless otherwise noted.875 2. t56 Clock Pulsewidth High.0 1. 5 Measured from 50% point of full-scale transition to 2% of final value.235 V. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition. t56 Clock Pulsewidth High. TJ MAX = 110 C. fall time from the 90% to 10% point of a full-scale transition. t26 Clock Period. t6 Analog Output Rise/Fall Time.875 1.5 0.) Min Typ 5. –4– REV. Specifications subject to change without notice. tPD6 PSAVE Up Time.0 8. Condition 2 50 140 240 1. t3 Clock Pulsewidth High. t4 Clock Pulsewidth Low.85 8. CL = 10 pF. t46 Clock Pulsewidth Low. 6 Guaranteed by characterization.0 V (V IH) and 0 V (VIL) for both 5 V and 3.3 V supplies. t16 Data and Control Hold. t96 CLOCK CONTROL fCLK7 fCLK7 fCLK7 Data and Control Setup.

3 Temperature range: T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz.6 V2.) Typ 7. VREF = 1. 0°C to +70°C at 240 MHz and 330 MHz. t96 CLOCK CONTROL fCLK7 fCLK7 fCLK7 fCLK7 Data and Control Setup. t106 (VAA = 3. t16 Data and Control Hold.3 V TIMING SPECIFICATIONS1 Parameter ANALOG OUTPUTS Analog Output Delay. Specifications subject to change without notice. t5 Pipeline Delay. RSET = 560 . tPD6 PSAVE Up Time. t3 t4 CLOCK DIGITAL INPUTS (R7–R0. fall time from the 90% to 10% point of a full-scale transition. CL = 10 pF. t46 Clock Pulsewidth Low. IOG. Limits specified here are guaranteed by characterization.5 1. BLANK) t5 t2 DATA t1 t6 t8 ANALOG OUTPUTS (IOR.875 1. OUTPUT DELAY (t6 ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.2 1.3 V supplies. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. 6 Guaranteed by characterization.0 1.0 8. Figure 1. G7–G0. t3 Clock Pulsewidth High. 7 fCLK max specification production tested at 125 MHz and 5 V. IOG.85 8.0 4 1.4 1.ADV7125 3. All specifications TMIN to TMAX3. unless otherwise noted.235 V. IOR. t4 Clock Pulsewidth Low. 2 These maximum and minimum specifications are guaranteed over this range. SYNC. t56 Clock Pulsewidth High. t46 Clock Pulsewidth Low. IOB.0 V to 3. t56 Clock Pulsewidth High. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition. 2. t74 Analog Output Transition Time. t85 Analog Output Skew.0 15 1 Max Unit ns ns ns ns MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns Clock Cycles ns 50 MHz Grade 140 MHz Grade 240 MHz Grade 330 MHz Grade Condition Min 2 50 140 240 330 0.5 3 1. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. t6 Analog Output Rise/Fall Time.85 2.0 10 NOTES 1 Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) for 3. t26 Clock Period. IOB) t7 NOTES 1.0 fCLK_MAX = 330 MHz fCLK_MAX = 330 MHz fCLK_MAX = 240 MHz fCLK_MAX = 240 MHz fCLK_MAX = 140 MHz fCLK_MAX = 140 MHz fCLK_MAX = 50 MHz fCLK_MAX = 50 MHz 1. 3. 0 –5– .875 2.4 1. B7–B0. TJ MAX = 110 C. 5 Measured from 50% point of full-scale transition to 2% of final value. t56 Clock Pulsewidth High. t46 Clock Pulsewidth Low. Timing Diagram REV.

. . Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. . .5 V to VAA + 0. . . . . . . . . PIN CONFIGURATION GND GND PSAVE RSET R7 R6 R5 R4 R3 R2 R1 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 GND 2 G0 3 G1 4 G2 5 G3 6 G4 7 G5 8 G6 9 G7 10 BLANK 11 SYNC 12 R0 PIN 1 IDENTIFIER 36 35 34 33 VREF COMP IOR IOR IOG IOG VAA VAA IOB IOB GND GND ADV7125 TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 GND GND B0 B1 B2 B3 B4 B5 B6 B7 CAUTION ESD (electrostatic discharge) sensitive device. permanent damage may occur on devices subjected to high energy electrostatic discharges. . . . . . –6– CLOCK VAA REV. . . 300°C Vapor Phase Soldering (1 Minute) . . . 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Analog output short circuit to any power supply or common can be of an indefinite duration. ORDERING GUIDE Speed Options Package Plastic LQFP (ST-48) 50 MHz 1 140 MHz 1 240 MHz2 ADV7125JST240 330 MHz2. . . . . . . . . . . . . . . 7 V Voltage on any Digital Pin . . . . Although the ADV7125 features proprietary ESD protection circuitry. . . . . . . . . . . . . . 0 . This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. .5 V Ambient Operating Temperature (TA) . . 3 Available in 3. . . . .ADV7125 ABSOLUTE MAXIMUM RATINGS 1 VAA to GND . . . proper ESD precautions are recommended to avoid performance degradation or loss of functionality. . functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. . . . . . . . . . . . . 3 ADV7125JST330 ADV7125KST50 ADV7125KST140 NOTES 1 Specified for –40°C to +85°C operation. . . . . . . 220°C IOUT to GND2 . . . . 2 Specified for 0°C to +70°C operation. . . . . . . –40°C to +85°C Storage Temperature (TS) . . . . GND – 0. .3 V version only. Therefore. . . . 150°C Lead Temperature (Soldering. . . . –65°C to +150°C Junction Temperature (TJ) . . 0 V to VAA NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. . .

This is a compensation pin for the internal reference amplifier. and Blue Current Outputs. All GND pins must be connected.e. A logic zero on this control input drives the analog outputs. IOB 28. 34 IOR. 41–48 11 G0–G7. SYNC does not override any other control or data input. 16–23. and IOB is given by: IOG (mA) = 11. 29. and IOG. 1. Analog Power Supply (5 V ± 5%). 444. to the blanking level. All three current outputs should have similar output loads whether or not they are all being used. The BLANK signal is latched on the rising edge of CLOCK.6 × V REF (V ) / RSET (Ω) The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used. Pixel data is latched on the rising edge of CLOCK.1 µF ceramic capacitor must be connected between COMP and VAA. 31. CLOCK should be driven by a dedicated TTL buffer. IOG. If the complementary outputs are not required. SYNC. G0–G7. i.. 14. and B0–B7 pixel inputs are ignored. it should only be asserted during the blanking interval. These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load.8 × VREF (V ) / RSET (Ω)(SYNC being asserted ) IOR . and BLANK pixel and control inputs. The rising edge of CLOCK latches the R0–R7. 39. IOR. Green. A logical zero on the SYNC input switches off a 40 IRE current source. these outputs should be tied to ground. IOB (mA ) = 7. B0–B7. Green. SYNC is latched on the rising edge of CLOCK. This is internally connected to the IOG analog output. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Green. Red. therefore. All VAA pins on the ADV7125 must be connected. R0. Clock Input (TTL Compatible). and Blue Current Outputs (High Impedance Current Sources). 40 3–10. Voltage Reference Input for DACs or Voltage Reference Output (1. and B0 are the least significant data bits. 32. the R0–R7. regardless of the full-scale output current. While BLANK is a logical zero. Red. IOB 35 36 37 COMP VREF RSET 38 PSAVE Power Save Control Pin. If sync information is not required on the green channel.ADV7125 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function Ground. GND 26. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 11. 30 24 VAA CLOCK 27. G0. It is typically the pixel clock rate of the video system. R0–R7 BLANK 12 SYNC 13. 15. IOG. 25. 445 × VREF (V ) / IOG (mA) The relationship between RSET and the full-scale output current on IOR. Differential Red. 33 IOR. SYNC tied permanently low.235 V) A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Compensation Pin. 2. the SYNC input should be tied to logical zero. REV. IOG. A 0. B0–B7. G0–G7. and Blue Pixel Data Inputs (TTL Compatible). Note that the IRE relationships are maintained. Composite Blank Control Input (TTL Compatible). Reduced power consumption is available on the ADV7125 when this pin is active. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. Composite Sync Control Input (TTL Compatible). IOB. 0 –7– . 989.

An 8-bit DAC contains 256 different levels. The discrete levels of video signal between reference black and reference white levels. resulting in the blackest possible picture. and blue to produce color pictures within the usual spectrum. 0 . this is the portion that may be visually observed. –8– REV. Sync Signal (SYNC) The maximum positive polarity amplitude of the video signal. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level This usually refers to the technique of combining the three primary colors of red. one for each color. Usually referred to as the front porch or back porch. three DACs are required. At 0 IRE units. Sync Level The peak level of the SYNC signal. In RGB monitors. Grayscale The portion of the composite video signal that varies in grayscale levels between reference white and reference black. green.ADV7125 TERMINOLOGY Blanking Level Raster Scan The level separating the SYNC portion from the video portion of the waveform. it is the level that will shut off the picture tube. Video Signal The position of the composite video signal that synchronizes the scanning process. Also referred to as the picture signal. Color Video (RGB) The most basic method of sweeping a CRT one line at a time to generate and display images.

as determined by the logic levels on the BLANK and SYNC digital inputs. according to the following equation: Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/(Retrace Factor) Horiz Res = Number of Pixels/Line Vert Res = Number of Lines/Frame Refresh Rate = Horizontal Scan Rate. IOB) The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output. IOR. RLOAD = 37. 3.62 18.62 SYNC 1 1 0 1 0 1 0 BLANK 1 1 1 1 1 0 0 DAC Input Data FFH Data Data 00H 00H xxH xxH REV.62 0.3 BLANK LEVEL 43 IRE 0 0 SYNC LEVEL NOTES 1. G7–G0. SYNC. IOB IOR. and B0–B7 are latched into the device on the rising edge of each clock cycle.235V. CLOCK DIGITAL INPUTS (R7–R0.62 18. B7–B0.62 18.62 – Video 18. Video Data Input/Output The ADV7125 has two additional control signals that are latched to the analog video outputs in a similar fashion. RGB Video Output Waveform Table I.62 18.62 – Video 18. RGB video waveform of the ADV7125.05 Video 8. Figure 3 shows the analog output.000 WHITE LEVEL 100 IRE 0 0 8. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e. 2. Digital Inputs Twenty-four bits of pixel data (color information) R0–R7. Video Output Truth Table (RSET = 530 Ω. Also integrated on board the part is a reference amplifier.62 – Video 18. All these digital inputs are specified to accept TTL logic levels.. This is done by adding appropriately weighted current sources to the analog outputs.g.67 V 1.8). V REF = 1. BLANK) ANALOG OUTPUTS (IOR. will be determined by the on-screen resolution. It is also known as the dot rate. G0–G7.62 Video Video 0 0 0 0 IOR/IOB 0 18. 0. Figure 3.62 IOR/IOB 18. Retrace Factor = Total Blank Time Factor. typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75 LOAD.05 0 IOG (mA) 0 18. each containing an 8-bit register. BLUE mA 18.62 V 0.62 – Video 18.05 0 8. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.ADV7125 CIRCUIT DESCRIPTION AND OPERATION The ADV7125 contains three 8-bit DACs. The dot rate. RSET = 530 . This is the rate at which the screen must be refreshed.7 GREEN mA 26. CRT control functions BLANK and SYNC are integrated on board the ADV7125. IOG. Table I details the resultant effect on the analog outputs of BLANK and SYNC. 0 –9– . The influence of SYNC and BLANK on the analog video waveform is illustrated. Figure 2. and thus the required CLOCK frequency.67 Video + 8. This data is presented to the three 8-bit DACs and then converted to three analog (RGB) output waveforms (See Figure 2).62 18. RED. Clock Input DATA The CLOCK input of the ADV7125 is typically the pixel clock rate of the system.5 Ω) Description WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL IOG (mA) 26. BLANK and SYNC are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream.62 18. with three input channels.

The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND (bit = “0”) by a sophisticated decoding scheme. Analog Output Termination for RS-170 *Applies to the ADV7125 only when SYNC is being used.6 MHz. IOB (mA) = 7 . grayscale (monochrome) or composite video applications (i. the part could. vertical sync (VSYNC). Many graphics processors and CRT controllers have the ability to generate horizontal sync (HSYNC). green. the diagram also shows the contributions of SYNC and BLANK for the ADV7125.. The on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. IOG.ADV7125 Therefore. Reference Input TERMINATION REPEATED THREE TIMES FOR RED. GREEN. high speed. as previously described in the Digital Inputs section. RSET. If SYNC is not being encoded onto the green channel. The VREF pin is normally terminated to VAA through a 0. Grayscale Operation Using a variable value of RSET allows for accurate adjustment of the analog output video levels. As all this circuitry is on one monolithic device. a noninterlaced 60 Hz refresh rate. AND BLUE DACs Figure 4a.. green.6 × VREF (V ) / RSET (Ω) (1) (2) TERMINATION REPEATED THREE TIMES FOR RED. The unused analog outputs should be terminated with the same load as that for the used channel. matching between the three DACs is optimized.8. if we have a graphics system with a 1024 × 1024 resolution. Alternatively. Use of a fixed 560 Ω RSET resistor yields the analog output levels quoted in the specification page. connected between the RSET pin and GND determines the amplitude of the output video level according to Equations 1 and 2 for the ADV7125: IOG * (mA) = 11. producing the specific output level requirements for video applications. IOG. 444. 0 . and a retrace factor of 0. red. if required. and composite SYNC. As well as the gray scale levels (black level to white level). The sync current is internally connected directly to the IOG output. These control inputs add appropriately weighted currents to the analog outputs. can be used to input the digital video data. the inclusion of some additional logic circuitry enables the generation of a composite SYNC signal. In a graphics system that does not automatically generate a composite SYNC signal.8 × VREF (V ) / RSET (Ω) IOR .5 Ω load. be overdriven by an external 1. Analog Output Termination for RS-343A IOR. 989. IOR. These values typically correspond to the RS-343A video waveform values as shown in Figure 3. The ADV7125 can be used for standalone. DACs The ADV7125 contains three matched 8-bit DACs.com/library/applicationNotes/video/AN205. but the source termination resistance. only one channel used for video information). The output current levels of the DACs remain unchanged. The red. Video Synchronization and Control Analog Outputs The ADV7125 has three analog outputs. is available in an application note entitled.23 V reference (AD1580). GREEN. Table I details how the SYNC and BLANK inputs modify the output levels. IOB DACs ZS = 75 (SOURCE TERMINATION)  (CABLE) ZL = 75 (MONITOR) ZO = 75 The ADV7125 has a single composite sync (SYNC) input control. The two unused video data channels should be tied to logical zero. thus encoding video synchronization information onto the green video channel. ZS. It is recommended that the CLOCK input to the ADV7125 be driven by a TTL buffer (e. More detailed information regarding load terminations for various output configurations. (www. A resistance. The DACs are designed using an advanced. Any one of the three channels. green. If it is not required to encode sync information onto the ADV7125. Figure 3 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Ω load of Figure 4a. Video Formats and Required Load Terminations available from Analog Devices.8 = 78. Figure 4a shows the required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement develops RS-343A video output voltage levels across a 75 Ω monitor. including RS-343A and RS-170. IOB DACs ZS = 150 (SOURCE TERMINATION)  (CABLE) ZL = 75 (MONITOR) ZO = 75 The ADV7125 contains an on-board voltage reference. All video data and control inputs are latched into the ADV7125 on the rising edge of CLOCK. the use of identical current sources in a monolithic design guarantees monotonicity and low glitch.e. AND BLUE DACs Figure 4b. then: Dot Rate = 1024 × 1024 × 60 / 0. on each of the three DACs is increased from 75 Ω to 150 Ω. and blue video signals. the SYNC input should be tied to logic low. 74F244).6 MHz The required CLOCK frequency is thus 78.g. and blue analog outputs of the ADV7125 are high impedance current sources.pdf).analog. if the red –10– REV. As well as matching. segmented architecture. Equation 1 will be similar to Equation 2. Each one of these three RGB current outputs is capable of directly driving a 37. In other words. or blue.1 µF capacitor. A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 4b. corresponding to the red. such as a doubly terminated 75 Ω coaxial cable.

it may be required to drive long transmission line cable lengths. consideration could be given to using a three-terminal voltage regulator. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. AD848 As an Output Buffer PC Board Layout Considerations The ADV7125 is optimally designed for lowest noise performance. The regular PCB ground plane area should encompass all the digital signal traces.5 B0 B7 GND Figure 5. this rejection decreases with frequency. the AD8061 is recommended. Optimum performance is achieved by the use of 0.1 F GAIN (G) = 1 + Z1 Z2 Figure 6. This bead should be located within three inches of the ADV7125. The analog output configurations to drive such loads are described in the Analog Outputs section and are illustrated in Figure 6. The layout should be optimized for lowest noise on the ADV7125 power and ground lines. Alternatively. the designer should pay close attention to reducing power supply noise. The digital signal lines to the ADV7125 should be isolated as much as possible from the analog outputs and other analog circuitry. Figure 7 shows a recommended connection diagram for the ADV7125. excluding the ground pins.1 F ZO = 75 (CABLE) ZL = 75 (MONITOR) The PC board layout should have two distinct power planes. Digital Signal Interconnect 75 AD848 DACs ZS = 75 (SOURCE TERMINATION) –VS 0. IOB and IOG should be terminated with 37. Power Planes IOB 37. REV. power supply bypass circuitry. Buffers with large full power bandwidths and gains between two and four will be required. Z2 Z1 +VS IOR. it is imperative that great care be given to the PC board layout. voltage reference circuitry. However.5 Ω resistors (See Figure 5). as illustrated in Figure 7. the analog output traces. This can be achieved by shielding the digital inputs and providing good decoupling. in some applications. To complement the excellent noise performance of the ADV7125. IOG. This bead should be located as close as possible (within three inches) to the ADV7125. 0 –11– . Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170.5 Ω). The PCB power plane should provide power to all digital logic on the PC board. and any output amplifiers. Due to the high clock rates used. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 7). It is important to note that while the ADV7125 contains circuitry to reject power supply noise. Each of the two groups of VAA should be individually decoupled to ground. The analog power plane should encompass the ADV7125 (VAA) and all associated analog circuitry. Digital signal lines should not overlay the analog power plane. In very high frequency applications (80 MHz). The PCB power and ground planes should not overlay portions of the analog power plane. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. both radiated and conducted noise. and the analog power plane should provide power to all ADV7125 power pins. The lead length between groups of VAA and GND pins should by minimized to minimize inductive ringing.5 Ground Planes IOR ADV7125 G0 G7 IOG The ADV7125 and associated analog circuitry should have a separate ground plane referred to as the analog ground plane. as illustrated in Figure 6. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. long clock lines to the ADV7125 should be avoided to minimize noise pickup. thus minimizing lead inductance.1 µF ceramic capacitors. VIDEO INPUT R0 R7 DOUBLY TERMINATED 75 LOAD 37. The analog ground plane should encompass all ADV7125 ground pins. If a high frequency switching power supply is used. leading up to the ADV7125. These include the AD84x series of monolithic op amps. as are most monitors rated. one for analog circuitry and one for digital circuitry. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. More information on line driver buffering circuits is given in the relevant op amp data sheets. Analog Devices produces a range of suitable op amps for such applications. and any output amplifiers. Input and Output Connections for Standalone Grayscale or Composite Video Video Output Buffers The ADV7125 is specified to drive transmission line loads. voltage reference circuitry. Altering the gain components of the buffer circuit will result in any desired video level. IOB 0. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead.ADV7125 channel is used and IOR is terminated with a doubly terminated 75 Ω load (37. The inclusion of output buffers will compensate for some cable distortion. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC) and not the analog power plane.

POWER SUPPLY DECOUPLING (0. The video output signals should overlay the ground plane and not the analog power plane.20 0.15 0.S. 25.45 1.01 F CAPACITOR FOR EACH VAA GROUP) 13. 26. 15.5 0 0. For optimum performance.00 BSC 48 1 37 36 1.09 SEATING PLANE TOP VIEW (PINS DOWN) 7.60 MAX 0.60 0. 40 IOR IOB Figure 7. Typical Connection Diagram OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.A.40 1. 29. 2.analog. 30 0.01 F 0.08 MAX COPLANARITY VIEW A 12 13 24 25 VIEW A ROTATED 90 CCW 0.4 mm Thick (ST-48) Dimensions shown in millimeters 1.1 F 5V (VAA) R7–R0 3–10 VREF RSET RSET 530 VIDEO DATA INPUTS 16–23 G7–G0 IOR B7–B0 IOG COAXIAL CABLE 75 75 75 MONITOR (CRT) IOB 75 75 75 BNC CONNECTORS COMPLEMENTARY OUTPUTS 75 ADV7125 SYNC BLANK IOG CLOCK PSAVE GND 1.35 0.45 PIN 1 INDICATOR 9.1 F 5V (VAA) 41–48 VAA 10 F L1 (FERRITE BEAD) VCC 33 F COMP VAA ANALOG GROUND PLANE 0. thereby maximizing the high frequency power supply rejection.05 SEATING PLANE 7 3. Additional information on PCB design is available in an application note entitled Design and Layout of a Video Graphics System for Reduced EMI.pdf). This termination resistance should be as close as possible to the ADV7125 to minimize reflections.22 0. 39. 0 PRINTED IN U.1 F AND 0.com/ library/applicationNotes/designTech/AN333.ADV7125 Analog Signal Interconnect The ADV7125 should be located as close as possible to the output connectors. thus minimizing noise pickup and reflections due to impedance mismatch.27 0. E1309–15–10/89 (www. 14.75 0. This application note is available from Analog Devices.00 BSC 0. publication no.50 BSC 0.1 F 0. C03097–0–10/02(0) .17 COMPLIANT TO JEDEC STANDARDS MS-026BBC –12– REV. the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration).