Jawaharlal Nehru Engineering Collage 

Laboratory Manual 
EDC-I For Second Year Students

Manual made by Prof. Neeta Pingle Ó Author JNEC, Aurangabad

Jawaharlal Nehru Engineering College 

Technical Document 
This technical document is a series of Laboratory manuals of Electronics and Telecommunication Department and is a certified document of Jawaharlal Nehru engineering College. The care has been taken to make the document error-free. But still if any error is found, kindly bring it to the notice of subject teacher and HOD.

Recommended by. HOD

Approved by. Principal

  This lab manual provides a platform to the students for understanding the basic concepts of electronic devices and  circuits. This being a core subject.  Good Luck for your Enjoyable Laboratory Sessions. it becomes very essential to have  clear theoretical and designing aspects.O. This practical background will help students to gain confidence in qualitative and quantitative approach to  electronic circuits. Electronic  Devices &circuits­I  covers basic concepts of electronics.  H.FOREWORD  It is my great pleasure to present this laboratory manual for second year engineering students for the subject of  Electronic Devices &circuits­I  to understand and visualize the basic concepts of various circuits using ICs.D  ECT Dept  LABORATORY MANUAL CONTENTS 3  .

Neeta Pingle  SUBJECT INDEX: 4  .This manual is intended for the Second Year students of ECT/IE branches in the subject of Electronic Devices & Circuits-I. Good Luck for your enjoyable Laboratory Sessions. Students are advised to thoroughly go through this manual rather than only topics mentioned in the syllabus as practical aspects are the key to understanding and conceptual visualization of theoretical aspects covered in the books. Prof. This manual typically contains practical/ Lab Sessions related to Electronic Devices & Circuits covering various aspects related to the subject for enhanced understanding.

To study class c amplifier as a Tuned Amplifier 8. To study JFET self bias circuit arrangement & to find 'Q' point with graphical method 3. Lab Exercises 1. To plot forward characteristics of pn junction diode (If vs. Quiz 4. 5.Ri.1. Ro. 2.To find performance for JFET amplifier Av .. Conduction of viva voce examination 5. 6. Evaluation & marking scheme  Dos and Don’ts in Laboratory :­ 5  . To study BJT fixed bias with & without emitter resistor. To plot output characteristics of JFET. Vf) 2. To plot Frequency Response of RC coupled amplifier 7. Do‛s & Don‛ts in Laboratory. i) Plot of transfer characteristics from the output characteristics 4. To study JFET CS as an amplifier . To plot Input & output characteristics of BJT in CE configuration 3.

Do not forcefully place connectors to avoid the damage. For Indian equipment. After the experiment is over. Submission related to whatever lab work has been completed should be done during the next lab session. wires. 2. 3. 4. 2. which will damage the equipment.. as our normal supply is 230V/50Hz. the power ratings are normally 230V/50Hz. 6  . CRO probe to the lab assistant/teacher. Students should be instructed to switch on the power supply after getting the checked by the lab assistant / teacher. the students must hand over the circuit board. Read carefully the power ratings of the equipment before it is switched ON. The promptness of submission should be encouraged by way of marking and evaluation patterns that will benefit the sincere students. Do not handle any equipment before reading the instructions /Instruction manuals. 3.1. whether ratings 230 V/50 Hz or 115V/60 Hz. If you have equipment with 115/60 Hz ratings. Observe type of sockets of equipment power to avoid mechanical damage. Strictly observe the instructions given by the Teacher/ Lab Instructor. Instruction for Laboratory Teachers:1. do not insert power plug. 5.

voltmeter.1 Practical Aim :.D. Observations:-  7  . 2. By varying applied voltage measure corresponding reading for voltage & current. Plot the graph of voltage & forward current. Diode(1N4007).To plot forward characteristics of pn junction diode (If vs.regulated power supply (0-30V) .C. 3. ammeter (0-25mA) Connecting wires Circuit Diagram :- R1  1k Vf  30V  D1  DIODE  A  a +  10V  ­  +  Procedure:1. Vf) Apparatus :. Resistance (820 Ω).Exercise No. Connect the circuit as shown in fig.1:(2 Hours):.

Input voltage (Vdc) = -------V Applied voltage Vdc ( V) O/P Voltage Vf ( V) Current If ( mA) Result:.Current increases exponentially with respect to voltage after cut in voltage as seen from the graph 8  .

c. PNP(BC157).DC current gain & AC current gain using the formulae given below. Plot the input curve between IB & VBE for different values of VCE. 3.NPN(BC148). b. BJT.Exercise No. c. d.regulated power supply . 2. Repeat the same procedure for different values of VCE.1 Practical Aim :. Keep IB constant (by setting P1) change P2 note IC & VCE . Ammeter(0-10μA)&(0-25mA). 9  .C. change P1 note IB & VBE . Plot the output curve between IC & VCE for different values of IB.To plot Input & output characteristics of BJT in CE configuration Apparatus :. Keep VCE constant. Find out the dynamic input resistance from curve plotted. Output characteristics:a. Make the circuit for CE configuration.Voltmeter (0-12V)& (0-15V) Circuit Diagram :- R1  1k  R2  1k  Q1  NPN Procedure:1. Find out the dynamic output resistance .2:(2 Hours):. Connect all the voltmeters & Ammeters. Input characteristics:a. b. b.D. Repeat the same procedure for different values of IB.

Formulae:Input characteristics:i) Dynamic input resistance (ri) = Δ VBE Δ IB Output characteristics:i) Dynamic ouput resistance (ro) = Δ VCE Δ Ic ii) DC current gain βdc = IC IB ii) AC current gain β = Δ IC Δ IB Observations :i) ri = ---------Ω ii) ro = ---------Ω iii) βdc = --------iv) β = --------- For Input characteristics:- 10  .

Thus we have plotted the input – output characteristics of BJT in CE mode. 11  .VCE = 2V VBE (V) IB (mA) VCE = 6V VBE (V) IB (mA) VBE (V) VCE = 10V IB (mA) For output characteristics:- IB=10µA VCE(V) IC(mA) IB=20µA IB=40µA VCE(V) IC(mA) VCE(V) IC(mA) Result :.

4. Repeat the steps from 6 to 8 for different values of VGS For transfer characteristics: 1. Ammeter(0-10mA). Now increase the VDD in steps & note down the readings of ID &VDS.5V interval of VDS 7. with the 1V interval of VGS 12  . JFET (BFW10). Rg=1K . i) Plot the transfer characteristics from the drain characteristics Apparatus :. 8. Now increase the VGG in steps & note down the readings of ID &VGS. Connect the milliammeter & voltmeters at the respective places.Digital multimeter (DMM) or Voltmeter (0-25V).Exercise No.To plot drain characteristics of JFET. Keep the VDS at constant voltage say VDS =1V 2. Switch on the power supply.3:(2 Hours):. Keep the VGS at fixed value say VGS=0V 6. Keep the VGG & VDD at minimum positions.1 Practical Aim :. Plot the graph with VDS along x axis & ID along y axis. RD=100Ω Circuit Diagram :- RD  1k RG  1K  NJFET  Q1  VGG  0­12V  +  +  VDD  0­12V  Procedure:For output characteristics: 1. with the 0. 5. 3. 2. Study the circuit provided on the front panel of the kit.

VGS=-2V. Repeat the steps from 1 to 3 for different values of VDS Observations :For output characteristics:VGS=0V . 4. Exercise No.1 Practical 13  .4:(2 Hours):.VGS =-4V Sr. VGS(V) ID(mA) Result :.VGS=-1V. Plot the graph with VGS along x axis & ID along y axis.The Drain & Transfer characteristics of JFET has been studied. VDS(V) ID(mA) For transfer characteristics:VDS(V) = ----------V Sr. VGS =-3V .No.3.No. From the experiment it can be conclude that the depletion layer increases & decreases as the gate to source voltage is reduced & increased respectively.

Ro. of I/P frequency Fi VS Gain Vo /Vi . Apply a sine wave I/P Vi of 1KHz. Switch on the power supply 6. 1MΩ. Resistors. 14  . Connect the function generator at the input terminals.To find performance for JFET amplifier Av. Adjust the amplitude so that transistor should not enter in saturation 5. Now increase I/P frequency Fi from 100 Hz to 200 KHz in suitable steps.87KΩ.4. 62Ω . Function generator. JFET -BFW10. 4. Plot the graph.Aim :. Determine it‛s gain. 2. 7. Apparatus :.1μf Circuit Diagram :- Vcc  12V  R1  1k  C1  1uF  RD  1k  Q1  BFW10  V0  R2  1k  RS  1k CS  1uF  Procedure :1.To study JFET CS as an amplifier . Patch chords.360Ω. C=0.1μf. Observe & note the corresponding amplified output voltage VO on the CRO which should be 1800 out of phase with respect to input. Connect the CRO at the output terminals. Determine its bandwidth. Study the circuit provided on the front panel of the kit. Ri. by keeping the input voltage constant. 3.CRO.

5:(2 Hours):.JFET in common source mode work as an amplifier. AV = VO/ Vi 2.Formulae :1. Ri = 3. Ro = Observations:Input voltage (Vi) = -------V(constant) I/P Frequncy Fi 100 Hz O/P Voltage VO (V) Gain AV = VO/ Vi 100 KHz Result :. The bandwidth is found to be ----------.1 Practical 15  .Hz Exercise No.

β=173 approx. RC=470Ω. bulb . Supply voltage :+12V. Study the circuit provided on the front panel of the kit & connect the 16  .To study BJT fixed bias with & without emitter resistor.Transistor BC148.Aim :. Voltmeter(0-15V) Circuit Diagram :- V1  10V  +V  RC  470  RB1  100k  RB2  180K 1  2  Q1  NPN  RE  180K  Procedure:1. Ammeter (0-100μA)(0-25mA). . RB2=180k. Apparatus :. resistors RB1 =100k. RE=180 Ω.

ammeter voltmeter as shown in circuit diagram.the circuit becomes Fixed Bias with Emitter Resistor . Connect Base of transistor to base resistor RB1 and Emitter to point 2 (ground) . Draw the DC load line . by observing ammeter & voltmeter readings. Now . 2. by using patch cords the circuit becomes Fixed Bias. Calculate the theoretical value of currents & voltages and note the corresponding values as per observation table . Repeat the above procedure for R=RB2 4. Repeat the above procedure for R=RB1. connect the Emitter resistor RE in the circuit & select R=R B1.Repeat the above procedure & note the ammeter voltmeter reading as per observation table.β =173 Base Resistor IB=VCC/R B IB (PR) IC=β IB (TH) IC (PR) VCE = VCC + ICRC (TH) VCE (PR) (TH) RB =RB1 =--------RB =RB2 =--------- -----mA -----mA -----mA -----mA -----mA -----mA 17  . Observations:For Fixed Bias:. 3.

Ω .VE S= 1+ β RE RE +RC 1+ β .respectively.Ω.1 Practical Aim :. RC =---------. Exercise No.Stability factor= S=1+ β For Fixed Bias with Emitter Resistor :β =173 .Ω . RE =---------.The stability factor for fixed bias & fixed bias with emitter resistor is found to be -----------&----------. . VCE= VC .IC RC . IB = VCC RB VC= VCC . RB IB (TH) IB (PR) ICsat (TH) VC (TH) VC (PR) VE (TH) VE (PR) VCE (TH) VCE (PR) S RB =RB1 =------RB =RB2 =------- Result:. RB2 =---------. RB1 =----------Ω . IC (sat) = VCC RE +RC Actual IC = VCC RE +RB/ β VE= IE RE ≈ IE R E .6:(2 Hours):.To study Frequency Response of two stage RC coupled amplifier 18  .

Keep the input signal amplitude Vi constant so that transistor should not enter in saturation. Observe & note the 19  . RC1= 2K . Connect the CRO at the output terminal of the first stage.R1=1K. 3. Resistors:. R3=47K . Q2 =BC548 Circuit Diagram :Vcc  12V  R1  1k Rc1  1k  C2  1uF  R3  1k  Rc2  1k  C3  1uF  C1  1uF  Q1  NPN  Q2  NPN  +  Vs1  10V  ­  R2  1k  Re1  1k  Ce1  1uF  R4  1k  Ce2  Re2  1uF  1k  Rf  1k Cf  1uF  S1  Procedure:1.Apparatus :. 5.6K.RC2=1K . CRO dual channel. Now vary Input frequency Fi from 100 Hz to 200 KHz in suitable steps. Patch chords. Connect the signal generator at the input terminal of the circuit.C1= C3=100µF. Apply a sine wave input. RE1= 100K . R4 =1K Capacitors:. C2=1µF. 6. R2=1K. RE2=5.Signal Generator. 4. Study the circuit provided on the front panel of the kit. Switch ‘ON‛ the power supply. C=100µF Transistors Q1. 2.

Also observe & note the output voltage (VO1) at collector of Q1 . Plot the graph. Calculate the overall gain AV= AV1 .The output signal of a two stage RC coupled amplifier is in phase with the input signal .fL Observations:Input voltage (Vi) = -------(constant) I/P Frequncy Fi 100 Hz O/P Voltage VO Gain AV = VO/ Vi Gain in dB 100 KHz Result :.AV2 Formulae:Bandwidth BW = fH . Also observe & note the output voltage (VO2) at collector of Q2 .corresponding O/P voltage VO.Calculate the gain of first stage AV1 = VO1/ Vi 9. Exercise No.By using two stages the overall gain increases. Determine the gain AV = VO/ Vi 7.1 Practical 20  . Determine its bandwidth. frequency of I/P Fi VS gain. It is because of the fact that its phase has been reversed twice by the transistor amplifier .Calculate the gain of second stage AV2 = VO2/ Vi.7:(2 Hours):. 8.

Switch ‘ON‛ the power supply. Observe & note the corresponding O/P voltage ‘VO‛. Calculate Q factor of tuned circuit which is given by F0 / BW . Determine the voltage gain AV = VO/ Vi 7. Connect the CRO at the output terminals. Keeping the input signal amplitude Vi constant. CRO dual channel. Note the values of inductor & capacitor. of voltage gain ‘AV‛ VS Input signal frequency Fi. 9.Aim :. vary the Input signal frequency Fi from 1 KHz to 100 KHz in regular steps. 3.159 Hz √LC 8. Determine its bandwidth. 21  . Plot the graph. Patch chords. 2. Study the circuit provided on the front panel of the kit.Note 3dB bandwidth & resonant frequency F0 (Fr) from graph. 5. digital multimeter Circuit Diagram :Vcc  6V  +V  T1  10TO1  R1  1k R4  1k  C1  1uF  Q1  NPN  + Vi  10V  R2  1k  R3  1k  Ce  1uf  Procedure :1. Determine theoretical values of resonant frequency F0= 0. 4.To study class c amplifier as a Tuned Amplifier Apparatus :. 6.Signal Generator. Apply a RF signal at input.

8:(2 Hours):.Hz & Q factor is -----------.For class-C amplifier resonant frequency ‘F0‛ is ----------.fL Observations :Input voltage (Vin) = -------(constant) I/P Frequncy Fi 1KHz O/P Voltage VO Gain AV = VO/ Vin 100 KHz Result :.1 Practical 22  .Formulae:F0 = 0. Exercise No.Hz .The bandwidth is found to be ----------.159 √LC Hz Bandwidth BW = fH .

To study JFET self bias circuit arrangement & to find 'Q' point with graphical method. Apparatus :.(VGS) 2.Ii is desirable to set the point near the midpoint of transfer characteristics curve of JFET 3.Signal Generator. JFET Circuit Diagram :- V  RD V  NJFET  Q1  RG  RS  Procedure:Setting a Q point:1.The Q point for a self biased JFET is established by determining the value of drain current (ID) for a desired gate to source voltage.Aim :.Draw a self bias line in such a way that it intersect the transfer charactristic curve near its midpoint.then any of the following method is used : 1)Analytical method 2)Graphical method Graphical method:1. 3. CRO.The value of source resistor (Rs) is given by the ratio of source voltage (VGS) to the drain 23  . If we want to design a self bias circuit . Patch chords.The point of intersection of the self bias line & the transfer characteristic curve gives us the required 'Q' point. 2.The midpoint bias allows a maximum amount of drain current swing betweeen the values of IDS 4.

Formulae:Rs=VGS/ID Result:. 3.current(ID).Thus we have found out the 'Q' point with graphical method.Quiz on the subject:24  .

the reverse current in a silicon diode is about (a) 10mA (b) 1μA (c) 1000 μA (d) none of these Q:3 The most commonly used transistor circuit arrangement is (a) CB (b) CE (c) CC (d) none of these Q:4 The emitter of transistor is doped (a) heavily (b) lightly (c) moderately (d) none of these Q:5 The biasing circuit which gives best stability to the Q point is (a) base resistor biasing (b) feedback resistor biasing (c) potential divider biasing (d) emitter resistor biasing Q:6 The ideal value of stability factor is (a) 1 (b) 5 (c) 10 (d) 100 Q:7 A practical constant current source should have internal resistance as (a) zero (b) low (c) high (d) none of these 25  .Q:1 When a pn-junction is forward biased (a) electrons in the n region enter into the p region (b) holes in the p region enter into the n region (c) both a and b (d) none of these Q:2 under normaloperating voltage .

the objective questions with guess are to be avoided. the questions should be such that 26  . Normally.4. To make it meaningful. Conduction of Viva­Voce Examinations:  Teacher should conduct oral exams of the students with full preparation.

  5. 27  . The marking patterns should be justifiable to the students without any ambiguity and teacher should see that students are faced with just circumstances. Oral examinations are to be conducted in cordial environment amongst the teachers taking the examination. It is a primary responsibility of the teacher to see that right students who are really putting up lot of hard work with right kind of intelligence are correctly awarded.depth of the students in the subject is tested. Teachers taking such examinations should not have ill thoughts about each other and courtesies should be offered to each other in case of difference of opinion. Evaluation and marking system: Basic honesty in the evaluation and marking system is absolutely essential and in the process impartial nature of the evaluator is required in the examination system to become. which should be critically suppressed in front of the students.

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