Hrs / Week Sl. No. Course No. Subject L Electronic System Modelling and Design T P TA 1 2 3 4 5 6 7 8 MECAE 101 3 3 3 3 3 3 0 0 18 1 1 1 1 0 0 0 0 4 0 0 0 0 0 0 3 2 5 25 25 25 25 25 25 25 50 225 CT 25 25 25 25 25 25 25 0 175 Evaluation Scheme (Marks) Sessional Sub Total 50 50 50 50 50 50 50 50 400 ESE Total Credits (C)

100 100 100 100 100 100 100 0 700

150 150 150 150 150 150 150 50 1100

4 4 4 4 3 3 2 1 25

MECAE 102 Analog Integrated Circuit Design MECAE 103 Digital Integrated Circuit Design MECAE 104 RF System Design MECAE 105 Elective – I MECAE 106 Elective – II MECAE 107 Electronic System Design Lab-I MECAE 108 Seminar – I Total

Elective – I (MECAE 105)
MECAE 105 - 1 Digital Communication System Design MECAE 105 - 2 RF Components and Circuit Design MECAE 105 - 3 Image and Video Processing System Design MECAE 105 - 4 VLSI System Design MEC AE 106 - 1 MEC AE 106 - 2 MEC AE 106 - 3 MEC AE 106 - 4

Elective – II (MECAE 106) Communication System Modelling and Design RF Antenna Design Speech and Audio Processing System Design Embedded System Design

L – Lecture, T – Tutorial, P – Practical TA – Teacher’s Assessment (Assignments, attendance, group discussion, Quiz, tutorials, seminars, etc.) CT – Class Test (Minimum of two tests to be conducted by the Institute) ESE – End Semester Examination to be conducted by the University Electives: New Electives may be added by the department according to the needs of emerging fields of technology. The name of the elective and its syllabus should be submitted to the University before the course is offered.


Hrs / Week Sl. No. Course No. Subject L T P TA 1 2 3 4 5 6 7 8 MECAE 201 Electronic Product Design MECAE 202 Analog and Data Conversion System Design 3 3 3 3 3 3 0 0 18 1 1 1 1 0 0 0 0 4 0 0 0 0 0 0 3 2 5 25 25 25 25 25 25 25 50 225 CT 25 25 25 25 25 25 25 0 175 Evaluation Scheme (Marks) Sessional Sub Total 50 50 50 50 50 50 50 50 400 ESE Total Credits (C)

100 100 100 100 100 100 100 0 700

150 150 150 150 150 150 150 50 1100

4 4 4 4 3 3 2 1 25

MECAE 203 High Speed Digital System design MECAE 204 DSP Algorithm and Architecture Design

MECAE 205 Elective – III MECAE 206 Elective – IV MECAE 207 Electronic System Design Lab-II MECAE 208 Seminar – II Total

Elective – III (MECAE 205)
MECAE 205 - 1 MECAE 205 - 2 MECAE 205 - 3 MECAE 205 - 4

Elective – IV (MECAE 206)
MECAE 206 - 1 MECAE 206 - 2 MECAE 206 - 3 MECAE 206 - 4

Wireless Communication System Design RF Integrated Circuit Design DSP System Design ASIC Design

Optical Communication System Design RF and Microwave Network Design Detection and Tracking System Design Embedded Network Design

L – Lecture, T – Tutorial, P – Practical TA – Teacher’s Assessment (Assignments, attendance, group discussion, Quiz, tutorials, seminars, etc.) CT – Class Test (Minimum of two tests to be conducted by the Institute) ESE – End Semester Examination to be conducted by the University Electives: New Electives may be added by the department according to the needs of emerging fields of technology. The name of the elective and its syllabus should be submitted to the University before the course is offered.


Hrs / Week Sl. No. Course No. Subject L Industrial Training or Industrial Training and Mini Project Master’s Thesis Phase - I Total T P TA* 1 2 MECAE 301 MECAE 302 0 0 0 0 0 0 20 10 30 50 100*** 150 CT 0 0 0 Evaluation Scheme (Marks) Sessional Sub Total 50 100 150 ESE** Total (Oral) Credits (C)

100 0 100

150 100 250

10 5 15


TA based on a Technical Report submitted together with presentation at the end of the Industrial Training and Mini Project

** Evaluation of the Industrial Training and Mini Project will be conducted at the end of the third semester by a panel of examiners, with at least one external examiner, constituted by the University. *** The marks will be awarded by a panel of examiners constituted by the concerned institute

Hrs / Week Sl. No. Course No. Subject L T P TA* 1 2 MECAE 401 MECAE 402 Master’s Thesis Master’s Comprehensive Viva Total Grand Total of all Semesters 30 100 0 100 0 0 30 100 CT 0 Evaluation Scheme (Marks) Sessional ESE** (Oral Total & Sub Total Viva) 100 100 100 200 200 100 300 2750 15 80 Credits (C)



50% of the marks to be awarded by the Project Guide and the remaining 50% to be awarded by a panel of examiners, including the Project Guide, constituted by the Department

** Thesis evaluation and Viva-voce will be conducted at the end of the fourth semester by a panel of examiners, with at least one external examiner, constituted by the University.




L T P C 3 1 0 4

Module 1: Representation of Systems Electrical / Mechanical / Hydraulic / Acoustic Systems: Transfer Function Vs. State Space Representation, Numerical Methods and Discretization. Linear Systems: Methods of Model Order Determination, Impulse and Frequency Response Methods. Time Varying (Linear) Systems: Stability Concepts, Fractal Behaviour. Nonlinear Models: Introduction to Stable Oscillations, Chaotic Behaviour, Jump Phenomena. Module 2: Modelling, Identification and Simulation Linear Modelling, Identification and Simulation: Least Squares Identification Methods; Off-Line and On-Line, Applications of LS and ARMA Methods, Regression Methods. Introduction to Non Linear Modelling, Identification and Simulation: Examples of Non Linear Models and Methods of Nonlinear Identification. Module 3: Analog and Digital Circuit Simulator Algorithms Basic flow of the Circuit Simulators: Inputs and Outputs. Simulation Algorithms: Modified Nodal Analysis, LU Decomposition, Sparse Matrix Algorithms, NewtonRaphson Iterative Techniques, and Numerical Integration. Convergence Issues and Simulation Accuracy. Basics of Logic Simulation: Event Queues and Event-Driven Simulation Techniques. Module 4: Modelling With Hardware Description Languages Semantics of representing Mixed-Signal Circuit behaviour, Modelling Conservation Laws, Implicit Relationships, Multi-Dimensional Observed Phenomena, and Multiple

Technology Domains (Thermal, Electrical, Mechanical, etc.). Operations for Moving from Analog to Digital and vice-versa: Thresholding to obtain an event from an Analog Quantity, Ramping to convert an event into an Analog Quantity. Analysis of MixedSignal Circuits and Systems: Basic and Advanced Analysis Capabilities in the State-ofthe-Art Simulators: AC, DC, Transient, Noise, Distortion Analysis and Stress, Sensitivity, and Failure Modes and effects


Severance. “Circuit Simulation”. & Singhal K. G. “Electronic Circuit and System Simulation Methods”. Morgan-Kaufman. John Wiley & Sons.. 5 . Wiley.. 4. T.. Najm F. & Teegarden D. 5. Rohrer R. 3. N. “System Modelling and Simulation: An Introduction”. & Visweswariah C. Pillage L. A. 2001. 2003. 2010. 2nd Ed. Vlach J. McGraw Hill. “The System Designer’s Guide to VHDLAMS”.. Kluwer Academic Publishers. “Computer Methods for Circuit Analysis and Design”. 2003. Frank L. 2. Ashenden P.. 1995.References: 1. Peterson...

Self-Biased Voltage References. Current Source Loads: Common-Source Amplifier. Small Signal Models. Common-Gate Amplifier. Parasitic Diode-Based References: Long-Channel BGR Design. MOSFET Noise Modeling. Module 3: Differential Amplifiers and Voltage References Differential Amplifiers: Source-Coupled Pair: DC Operation. I-V Characteristics of MOSFETs. Distortion. CMRR. Module 4: Operational Amplifiers One-Stage and Two-Stage Op-Amps: Low-Frequency. Input CommonMode Range. Cascode Loads. Source Follower. Source Follower. Short-Channel Design. Constant Transconductance Diff-Amp.MECAE 102 ANALOG INTEGRATED CIRCUIT DESIGN L T P C 3 1 0 4 Module 1: MOSFET Operation and Models for Analog Design MOSFET Capacitance Overview / Review. Module 2: Current Mirrors and Single-Stage Amplifiers Current Mirrors: Basic Current Mirror: Long-Channel Design. Temperature Behaviour. Cascoding the Current Mirror: Simple Cascode. Push-Pull Amplifier: DC Operation and Biasing. Output Swing and Current Source / Sinking Capability. Slew-Rate Limitations. Threshold Voltage. Voltage References: MOSFET-Resistor Voltage References: Resistor-MOSFET Divider. Models for Analog Design: Long-Channel MOSFETs. Matching Currents in the Mirror. Short-Channel MOSFETs. AC Operation. Short-Channel BGR Design. Common-Gate Amplifier. Low-Voltage (Wide-Swing) Cascode. Wide-Swing. Square-Law Equations. Matching Considerations. Cascode Amplifier. Power Dissipation. Biasing Circuits: Long-Channel Biasing Circuits. Open Loop Gain. Temperature Effects. Wide-Swing Differential Amplifiers: Current Differential Amplifier. Biasing the Current Mirror. Biasing in the Subthreshold Region. Short-Channel Biasing Circuits. General Design. Source CrossCoupled Pair: Operation of the Diff-Amp. 6 . Amplifiers: Gate-Drain Connected Loads: Common-Source Amplifiers. Noise Performance. Regulated Drain Current Mirror. MOSFET-Only Voltage Divider. Small-Signal Analysis. Short-Channel Design. Current Source Load.

“Design of Analog CMOS Integrated Circuits”. Three-Stage Op-Amp Design. References: 1. Ltd. Wiley India Pvt. Blalock. Johns & Ken Martin. “Analysis and Design of Analog Integrated Circuits”. 5th Ed. Op-Amp with Output Buffer. “CMOS: Circuit Design. Folded-Cascode OTA. Slew-Rate Limitations. McGraw Hill Higher Education. 5. “CMOS Analog Circuit Design”. 2003. Holberg. 4. Compensation for HighSpeed Operation. Layout. Paul J. “Microelectronic Circuit Design with CDROM”. Lewis & Robert G. CMRR and PSRR. 7 . 2. Hurst. Paul R. Oxford University Press. Richard C... 2nd Ed. Compensating the Op-Amp: Gain and Phase Margins. Wiley. Meryer. Behzad Razavi. 2009. Jacob Baker R. 2008.Offsets. Gray. David A. 6. 2nd Ed. Jaeger & Travis N. OTA with Output Buffer. Gain-Enhancement. and Simulation”. McGraw Hill. Allen & Douglas R. Operational Transconductance Amplifier. 2003. “Analog Integrated Circuit Design”... Philip E. Wiley 2009. 2010. Stephen H. 3..

Perspective: Choosing a Clocking Strategy. Analyzing Power Consumption using SPICE. Propagation Delay: First-Order Analysis.MECAE 103 DIGITAL INTEGRATED CIRCUIT DESIGN L T P C 3 1 0 4 Module 1: CMOS Inverter Issues in Digital Integrated Circuit Design. Dynamic Logic: Basic Principles. Mesochronous Interconnect. Plesiochronous Interconnect. Speed and Power Dissipation of Dynamic Logic. Issues in Dynamic Design. Ratioed Logic. Functionality and Robustness. Energy.Logic Style for Pipelined Structures. Dynamic Latches and Registers. Non-Bistable Sequential Circuits. Noise Margins. Synchronous Interconnect. Pipelining: An Approach to Optimize Sequential Circuits. Performance. Clock-Distribution 8 . Pass-Transistor Logic. Astable Circuits.Clock-Skew Insensitive Approach. Classification of Memory Elements. Performance of CMOS Inverter: Dynamic Behavior. Static CMOS Inverter: Static Behavior. Dynamic CMOS Design. Cost of an Integrated Circuit. NORA-CMOS . Computing the Capacitances. Module 3: Designing Sequential Logic Circuits Timing Metrics for Sequential Circuits. and Energy-Delay. Static Latches and Registers. Perspectives: How To Choose A Logic Style? Designing Logic for Reduced Supply Voltage. Asynchronous Interconnect. Propagation Delay from a Design Perspective. Schmitt Trigger. Monostable Sequential Circuits. True Single-Phase Clocked Register (TSPCR). Bistability Principle. Complementary CMOS. Sense-Amplifier Based Registers. Register-Based Pipelines. Latch Vs. Power and Energy Consumption. Sources of Skew and Jitter. Synchronous Design: Synchronous Timing Basics. Power. Alternative Register Styles. Module 4: Timing Issues in Digital Circuits Timing Classification of Digital Systems. Dynamic Transmission-Gate Edge-Triggered Registers. Quality Metrics of a Digital Design. Cascading Dynamic Gates. Switching Threshold. Master-Slave Edge-Triggered Register. CMOS . Multiplexer-Based Latches. Dynamic Power Consumption. Pulse Registers. Low-Voltage Static Latches. Static SR Flip-Flops. Static Consumption. Perspective: Technology Scaling And its Impact on the Inverter Metrics Module 2: Designing Combinational Logic Gates in CMOS Static CMOS Design.

“Digital Integrated Circuit Design”. Completion-Signal Generation. Jacob Baker R. Layout. Self-Timed Logic Asynchronous Technique. 2008. Anantha Chandrakasan & Borivoje Nikolic. “Analysis and Design of Digital Integrated Circuits”.. Cambridge University Press. Latch-Based Clocking. Wiley. Clock Synthesis and Synchronization using A Phase-Locked Loop: Basic Concept. 2. 3rd Ed. Horace Jackson & Resve Saleh. 5. 2003. Distributed Clocking using DLLs. Jan M. Self-Timed Signaling. and Simulation”. 2007. “Digital Integrated Circuit Design from VLSI Architectures to CMOS Fabrication”. Ken Martin. McGraw Hill. Rabaey. Synchronizers and Arbiters: Synchronizers .Concept and Implementation. 1999. 9 . “CMOS: Circuit Design. Self-Timed Circuit Design. 4. 2nd Ed.Techniques. 3. Practical Examples of Self-Timed Logic. Oxford University Press. Building Blocks of a PLL. “Digital Integrated Circuits: A Design Perspective”. Hubert Kaeslin & Eth Zürich.. 3rd Ed. “CMOS Digital Integrated Circuits Analysis and Design”.. Pearson Education Asia. References: 1. 6. David Hodges. 2010. McGraw Hill. Sung-Mo (Steve) Kang & Yusuf Leblebici. 2002. Arbiters.

“Radio Frequency and Microwave Electronics”.. Pearson Education Asia. 2nd Ed. David M. Pearson Education Asia. Filter Implementations. 3r Ed. Microstrip. 4. Constant VSWR Circles. Basic Oscillator Model. “RF Circuit Design – Theory and Applications”. Load Impedance. Single Stub Matching Network . Special Filter Realizations. Oscillators and Mixers Characteristics. 10 . Module 3: Impedance Matching Networks Impedance Matching using Discrete Components.. 3. Planar Transmission-Lines: Stripline. Module 2: RF Filter Design Overview. “ Microwave Engineering”. Double Stub Matching Network. Constant Gain Circles.. Pozzar . High Frequency Oscillator Configurations. Radmanesh. 2. 2006. Basic Resonator and Filter Configuration. Quarter-Wave Transformers. Mathew M. References: 1. Parallel and Series Connection. Wiley India. 2007. 2004. Impedance Transformation. Noise Figure Circles. Revision of S-Parameters. SWR. Smith Chart: Reflection Coefficient. Admittance Transformation. Radmanesh. Terminated Lossless Lines. Coplanar-Line. Multi-Section and Tapered Transformers. Basic Characteristics of Mixers. Amplifier Power Relations. “Advanced RF & Microwave Circuit Design-The Ultimate Guide to System Design”. 2009. and Impedance Mismatches. Reinhold Ludwig & Powel Bretchko.MECAE104 RF SYSTEM DESIGN L T P C 3 1 0 4 Module 1: Transmission Line Theory Review of Transmission Line Theory: Lumped Element Model. Low Noise Circuits. 1st Ed. Module 4: RF Amplifiers. Coupled Filter. Pearson Education Ltd. Mathew M. Stability Considerations. Broadband. Field Analysis of Transmission Lines. High Power and Multistage Amplifiers. Microstripline Matching Networks.

Carr. John Blyer & Cheryl Ajluni “ RF Circuit Design”. John Wiley & Sons. 2nd Ed. Sayre. 2000.. 9. 2008. 11 . “RF Components and Circuits”. McGraw-Hill. “Complete Wireless Design”. Rohde & David P. “RF / Microwave Circuit Design”.. Newnes. 2nd Ed. Cotter W. 2007. 7. Alan. 2002. 6. “Radio Frequency Circuit Design”. Davis W. NewKirk. Ulrich L. Wiley India. Joseph J. 8. Christopher Bowick.5. 2009. Newnes.

“Digital Communications: A Discrete-Time Approach”.. Operations on Signals: Correlation. 12 . Quantization. Properties and Representation of Noise.. Rice M. 2009. Energy and Power Spectral Density. Frequency Selectivity and Multipath Fading. 2008.1 DIGITAL COMMUNICATION SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Overview of Communication System Overview of a Communication System: Channel. “Digital Communications. Pulse-Code Modulation. Review of Signal Classification and Characteristics. Orthogonality. Two-Dimensional M-ary Signaling: M-PSK and M-QAM. Spatial Transmit Diversity Techniques for Multipath Channels." 5th Ed. Pulse-Amplitude Modulation. References: 1. Channel Equalization. Signal Transmission through a Linear System: Distortion. M-ary Pulse Amplitude Modulation. Geometric Representation of Signals. Analysis and Transmission of Signals: Fourier Series. Signaling for Frequency-Selective Channels: Equalization. Effect of Noise on Communication Systems. 2. Module 3: Channels Wireless (Multipath) Channel Models. Module 4: Diversity Techniques Spatial Receive Diversity Techniques for Multipath Channels. McGraw Hill. Module 2: Signaling and Modulation Communication System in AWGN Noise. Classification of Wireless Channel Models. Digital Modulations for Flat-Fading Channels. Band Pass and Band Limited Digital Modulation. Sampling. John G. Signal Space Representation. Signaling for Flat-Fading Channels: Error Control Coding. Binary PSK and FSK Systems. and Performance Issues. MIMO Systems. Fourier Transform. M-dimensional M-Ary Signaling: M-FSK and OFDM. Time-Division Multiplexing. Adaptive Equalizer. Inter Symbol Interference. Matched Filter. Prentice-Hall. Proakis & Masoud Salehi.MECAE 105 . OFDM. Digital Modulations for Frequency-Selective Channels.

John G... 8. 9. Prentice Hall. Papoulis A.. B.W. “A First Course in Digital Communication”. 10. Ha H. Random Variables and Stochastic Processes”. 3rd Ed. 2005. Ha. 5. G. Kluwer Academic / Plenum Publishers. McGraw Hill. & Lindsey W.U. 2005. Barry J. 2010. Nguyen & Ed Shwedyk. Anderson.. 11. Prentice Hall. & Svensson A. 2004. C.. & Messerschmitt D. 1995. 6. California Cambridge University Press. 2009. Kluwer Academic Publishers.3. John B. Lee E. A. “Digital Transmission Engineering”. “Digital Communication TechniquesSignal Design and Detection”. “Probability and Random Processes with Applications to Signal Processing”. Proakis & Masoud Salehi. Wiley Inter-Science. & Pillai S. Tri T. K. Stark H. Simon M. “Digital Communication. Cambridge University Press. & Woods J.. “Fundamentals of Communication Systems”. R. “Theory and Design of Digital Communication Systems”. 4. M.” 3rd Ed.. 2002. 2002.. “Coded Modulation Systems”. Prentice Hall. 7. 13 . Hinedi S. “Probability. 2003. Anderson J..

Cascaded Linear Two-Port Networks. Cut and Selection. “RF Circuit Design – Theory and Applications”. Noise Figure Parameters. GaAs. Importance of RF Design. Small Signal FET Models. Binary Phase Shifters. Module 4: Microwave Circuit Technology Introduction. Phase Shifters: True Relay and Slow Wave Phase Shifters. Temperature Models. Variable Attenuators. Linear Diode Model. Via Holes. “Microwave and RF Engineering”.Schottky Diode. Hybrid and Monolithic Integrated Circuits. Microwave Transistor Issues: Silicon Vs. MMIC Statistical Models. On-Wafer Testing. Prentice Hall Ltd. Scattering Parameter Device Characterization. Inductors. MMIC Production Techniques: Lithography.MECAE 105 . Advanced Hybrid MICs. Chip Components and Circuit Board Considerations. Reflection Phase Shifters. FET Switches. Capacitors. Tunnel Diode. Non Linear Models. High Mobility Transistors.. Transistor Models: Large Signal BJT Models. Small Signal BJT Models. Signal Flow Graph. 2. Parasitic elements associated with Physical Devices. Basic MMIC Elements: Transmission Lines. MMICs. Resistors. PIN Diode. Alternative Multi Port Switch Structure. Large Signal FET Models. & Bianchi G. Module 2: Active RF Components Modelling Diode Models: Non Linear Diode Model. Module 3: Microwave Control Components Introduction. Noise in Two-Port Network. 2nd Ed. Scalable Models. S-Parameters. Sorrentino R. 14 . 2008. RF Behaviour of Passive Components. Active RF Components: RF Diodes .. Stepped Phase Shifters. John Wiley. Switches: PIN Diode Switches. TRAPATT. High Frequency PCB.. Snap Diode. Hybrid MICs. IMPATT. Non-Linear Two-Port Networks. References: 1. Noise Diode. Semiconductor Devices. Varactor Diode. 2010. BARRIT and Gunn Diodes. Simulation Models: Single Element Models. Noise Sources. MEMS Switches. Reinhold Ludwig & Powel Bretchko.2 RF COMPONENTS AND CIRCUIT DESIGN L T P C 3 0 0 3 Module 1: RF Components Introduction. RF Field Effect Transistors.

2007. 5. 3rd Ed. “ Microwave Engineering”. Artech House. 7. 2002. Mathew M. Lancaster M. Wiley India. 2001. 6. “RF Components and Circuits”. 2008. 9. 1997. John Wiley & Sons. 8. & Waun Ed.. Pozzar . Inder Bahl. “An introduction to Radio Frequency Engineering”. Cotter W. 11. Jia-Sheng Hong. “Advanced RF & Microwave Circuit Design – The Ultimate Guide to System Design”. Hong. Wiley Interscience. “Microstrip Filters for RF / Microwave Applications”. “Lumped Elements for RF and Microwave Circuits”.. 2009. 10. Radmanesh. 2nd Ed. J. 15 . Prentice Hall. 2004.. “Complete Wireless Design”. Sayre. “Fundamentals of RF and Microwave Transistor Amplifiers”. 2009. Joseph J.3. Inder Bahl. Cambridge. McGraw Hill. Coleman C. 4. 2003. David M. Guillermo Gonzalez. Newnes. Carr. Pearson Education Asia. “Microwave Transistor Amplifiers: Analysis and Design”.

Conversion from Interlaced to Progressive. Image Quantization. Thresholding. Negation. Noise Reduction and Restoration in Videos. Video Filtering by Motion Compensation. Colormap Look-Up Tables. Fourier Transforms and their Applications in Image Processing. Algebraic Operators. Block Matching Algorithm. Histogram Equalization. Processing Via Spatial Operations: Weighted Local Area Smoothing or Averaging. Concepts of Probabilities applied to Images. Interframe Coding. Bit-Plane Slicing. Pixel Based Motion Estimation. Gray Level Interpolation. Sharpening Filters. Object Following. Multi Resolution Motion Estimation. Region Based Motion Estimation. Predictive Coding. Sums and Differences of Images. Resolution Pyramids and Sub Band Coding. Analysis of Images and Video. Basic Principles of Wavelet Transform. Background Removal. Averaging Noisy Images. Space-Time Sampling. Module 3: Image and Video Encoding Systems General Block Diagram of an Image and Video Encoding System. Mathematical Morphology Filters. Human Sight System: Application to Image and Video Encoding. Calculation of Optical Flow General Methodologies. Range Compression. Histogram Specification. Notions of the Theory of Information. Linear Filters. Frequency Domain. Colour and its Representation. Derivative Filters.MECAE 105 . Clipping. Gray-Level Slicing. Processing via Algebraic Operations: Input And Output Histograms. Module 2: Image and Video Enhancement Spatial Domain Vs. Mesh-Based Motion Estimation. Spatial Transformations. Image Equalization. Enhancement via Point Operations: Contrast Stretching. Conversion of Frame-Rate. Enhancement via Histogram Modeling: Histogram Modification. Discrete Cosine Transform. Aliasing.3 IMAGE AND VIDEO PROCESSING SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Image and Video Basics Human System of Sight. Change or Motion Detection. Sampling. Median Filtering. Application of Motion Estimation in Video Coding. Transform Coding. Mathematical Morphology: Basic Operations. Video Processing Applications. Analog Video and PAL / NTSC Systems. Global Motion Estimation. Still 16 . Video Digital Signature. Basic Laws of Perception. Error Resiliency. 2-D Motion Estimation: Optical Flow.

Image Compression Standards: JPEG and JPEG 2000. “Multiple View Geometry in Computer Vision”. 6. “Video Processing and Communications”. 6th Ed. 2. 3. Video Compression Standards: H. Comparison with other Formats of Still Image. & Ponce J. Camera Calibration. Yi Ma.. 2002. Basic Concepts of Projective Geometry of Planes and Spaces. 2009. Scene Plans and Homographies.. 2004. Murat Tekalp A. “Digital Video Processing”. Cambridge University Press. Springer-Verlag. 2010. “An Invitation to 3-D Vision . 2-D Homography Estimations. Richardson. Iain E. Calculation of the Fundamental Matrix. Image Rectification. Prentice Hall. Wiley Interscience.. Prentice Hall. 2D and 3D Geometrical Transformations. 2003. Module 4: Three Dimensional Vision Affine and Metric Geometry. 2008. Jana Kosecka. Prentice-Hall. “Computer Vision: A Modern Approach”. References: 1. 2002. Richard Hartley & Andrew Zisserman. Yao Wang. Trifocal Tensor. MPEG-1/2 and Others. 7.261. Stefano Soatto. “Computer Vision: Algorithms and Applications”. Epipolar Geometry. Geometry of Three or More Views. Jorn Ostermann & Ya-Qin Zhang. Springer. Boguslaw Cyganek & Paul Siebert J. “An Introduction to 3D Computer Vision Techniques and Algorithms”. Wiley Inter Science. Models of Cameras. Three-Dimensional Reconstruction of a Scene. Richard Szeliski. 1996. & Shankar Sastry. Forsythe D. 4. 17 . 8. “Video Codec Design: Developing Image and Video Compression Systems”. 5..From Images to Geometric Models”. Representation of Perspective.

Wire Model. Sequencing Static Circuits. Module 4: Routing. Special Routing. Circuit Design of Latches and Flip Flops. Supply Scaling. Logic Design Considerations of Adder. Static Properties. Sequencing Dynamic Circuits. Inverter Design for a given VTC and Speed. Wind Mill Constraint. BiCMOS Logic: Static and Dynamic Behaviour. Transistors and Layout. SPICE Simulation of MOSFET I-V Characteristics and Parameter Extraction Post Layout Simulation.MECAE 105 .4 VLSI SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Introduction to CMOS VLSI Design Introduction to Digital IC Design: Custom and Semicustom Flow. MOSFET Models. Propagation Delay. Synchronizers. Latch Up Effect. DCVSL. Placement. Channel Definition. PTL. Static and Dynamic Power Dissipation. Scheduling and Allocation Partitioning. CMOS Memory Design: SRAM and DRAM. Combinational Logic Synthesis: Technology Independent and Technology Dependent Optimization. TSPC Registers. Pseudo NMOS Inverter. Energy and Power Delay Product. Data Paths in Processor Architecture. Module 2: Static and Dynamic CMOS Design Static CMOS Design: Complementary CMOS. Low Power Design Techniques. Effect of Input Rise Time and Fall Time. Sizing Chain of Inverters. C2MOS. Dynamic CMOS Design: Speed and Power Considerations. CMOS Inverter: Effect of Process Variation. Domino Logic and Its Derivatives. Multiplier. Standard Cell Layout. DPTL & Transmission Gate Logic. CMOS Layout Elements: Parasitics. Logical Effort for Transistor Sizing. Clock 18 . Timing: Slack Delay Model. MOSFET Capacitances. Static Sequencing Element Methodology. Wires and Vias. Delay and Power Consumption in BiCMOS Logic. Slicing Tree. Shifter. Layout Design. NORA CMOS. Ratioed Logic. Sources of Skew and Jitter. Floor Planning and Pin Assignment. Power Consumption. Effect of Skew and Jitter on Timing. Technology Scaling Effect on Interconnect and Noise in Interconnects. Channel Routing Order. Elmore Delay Model. Simulation of Static and Dynamic Characteristics. Module 3: Subsystem Design and Timing Issues Subsystem Design Principles: Pipelining. Design Rules. Clocking Disciplines.

FPGA Logic Element and Interconnect Architecture. Switch Box Routing.. Logic Synthesis. Maze Routing. Line Probe Algorithm. 2nd Ed. Armstrong & Gail Gray F. Vertical Constraint. Springer. 4. 2005. “Algorithms for VLSI Physical Design Automation”. Functional Unit Allocation. “Digital Integrated Circuits . 2005. Wiley. Logic Synthesis for FPGA. 2. Pearson. Global Routing. James R. High Level Synthesis. 3rd Ed. Rabae..Routing for Regular and Irregular Structures. “FPGA-Based System Design”. 1999. Scheduling and Allocation: ASAP and ALAP Scheduling.A Design Perspective”. Register Transfer Design. I / O Circuits. 2002. 19 . Left Edge Algorithm. Sherwani. Hardware Description Languages: Synthesis. 3rd Ed. Register Allocation. Detail Routing. 3. References: 1. Weste & Harris “CMOS VLSI Design”.. Wayne Wolf. Interconnect Path Allocation. Prentice Hall. Off Chip Connections. ESD Protection. Pearson Education. Physical Design for FPGA. Naveed A. Power Routing. “Introduction to VLSI Circuits and Systems”. Uyemura J. 2009. Event Driven Simulation. 2007. P. 5. 6. “VHDL Design Representation and Synthesis”.. Pearson Education. Jan M.

"Simulation of Communication Systems". Random Access Systems.MECAE 106 . Dorling Kindersley (India) Pvt. Non-Linear Sequences. Troposcatter and Satellite Channels. Monte Carlo Method and Importance of Sampling Method. Analog Channel Model. 4th Ed. "Simulation. 4. Burke's Theorem. “Modeling and Analysis of Computer Communication Networks”. Jeruchim M. M. Congestion and Flow Chart. Carson & Barry L Nelson. Store and Forward Communication Networks. Network Layout and Reliability. Kluwer Academic Publishers. Network of Queues: Queues in Tandem. Probability Density Functions of Analog Communication System. Bounds and Approximation. Digital Channel Model: Gilbert Model of Bursty Channels. 2002. Philip Balaban & Sam Shanmugan K. References: 1. Computer Generation and Testing of Random Numbers. 2nd Ed. Pseudo Noise Sequences. Modelling and Analysis". HF. Hayes J. Noise and Fading. Light Wave System Models. Jerry Banks. 2. Random Process Models: Markov and ARMA Sequences. Sampling Rate for Simulation. Tata McGraw Hill. 20 . M/G/I Queue. 3. Estimation of Power Spectral Density Module 4: Communication Networks Queuing Models.. “Discrete-Event System Simulation”.. Capacity Allocation. F. Polling. M/M/I and M/M/I/N Queues. Embedded Markov Chain Analysis of TDM Systems. Switched Telephone Channels. Transformation of Random Variables. Routing Model.. 3rd Ed. Little Formula. Analog and Digital Communication System Models.. Kluwer Academic Publishers.. C. Module 2: Simulation of Random Variables and Random Process Univariate and Multivariate Models.1 COMMUNICATION SYSTEM MODELLING AND L T P C DESIGN 3 0 0 3 Module 1: Modelling of Communication Systems Model of Speech and Picture Signals. Law A. 2007.. Module 3: Estimation of Performance Measures Quality of an Estimator.. 2002.. Ltd. John S. 2007. Estimator for SNR. BER of Digital Communication Systems.

Module 4: A. “Microstrip Antenna Design Handbook”. Wiley-Inter science.MECAE 106 . Garg R. Module 3: Circular Microstrip Antenna Introduction. Models of Rectangular Patch Antenna. Effect of Substrate Parameters on Bandwidth. Module 2: Rectangular Microstrip Antenna Introduction. 2001. Loss Factor. Coaxial Feed / Probe Coupling. Microstrip Patch Antenna. 2002. Aperture Coupled Microstrip Feed.... 1st Ed. Printed Dipole Antenna. Advantages and Limitations of Microstrip Antenna. Quality Factor and Impedance Bandwidth. Element Width and Length. References: 1. & Ittipiboon A. Use of a Meandered Ground Plane. Radiation Pattern and Radiation Resistance.2 RF ANTENNA DESIGN L T P C 3 0 0 3 Module 1: Microstrip Radiators Introduction. 2. Feed Point Location and Polarization. Artech House Publishers. Selection of Suitable Patch Shape. Feeding Techniques and Modeling. Radiation Mechanism of a Microstrip Antenna. Cavity Model Analysis. Analysis of a Circular Disk Microstrip Antenna Using Cavity Model. Coplanar Waveguide Feed. Various Microstrip Antenna Configurations. Selection of Suitable Feeding Technique. Compact Microstrip Antennas Introduction. Feed Location and Polarization. Use of a Shorted Patch with a Thin Dielectric Substrate. Design Considerations of Rectangular Patch Antenna. Use of an Inverted U-Shaped or Folded Patch. Substrate Selection. Transmission Line Model Analysis . Bhartia P. Design Considerations: Substrate Selection. Kin-Lu Wong. 21 . Broad Banding of Microstrip Antennas Introduction. Radiation Pattern. B. Radiation Fields. Inder Bahl. Microstrip (Coplanar) Feed. Radiation Efficiency. Aperture-Coupled Microstrip Antenna. Use of a Meandered Patch. Bandwidth. Proximity Coupled Microstrip Feed. “Compact and Broadband Microstrip Antennas”. Use of a Planar Inverted-L Patch. Printed Slot Antenna.

“Antenna Theory and Microstrip Antennas”. Fang D. 4. 2009.G. Saunders & Alejandro Aragon-Zavala. “Antennas and Propagation for Wireless Communication System”.3.. 2007. CRC Press. 22 . John Wiley & Sons. Simon R.

Psychophysics. Music Applications Based on Audio Processing. 23 . PCM Encoding. Pitch Period Estimation using Auto Correlation Function. Pitch and Formant Extraction. Human Hearing System: Ear. Spectral Modelling of Music Signals. Speech Signal Characteristics. Dolby AC-3 Audio. Rate / Distortion Techniques. Encoding in the Frequency Domain. Human Auditory System: Application to Voice and Audio Encoding. Short Time Auto Correlation Function. Analysis by Synthesis.MECAE 106 . Formant and Pitch Estimation. Channel Vocoder. Auditory Scene Analysis. Predictive Encoding. Sampling Rates. MPEG-1 Audio. Methods for Extracting the Parameters: Energy. Average Magnitude. Spectrographic Displays.Time Domain Parameters of Speech and Music Signal. Analysis-Synthesis Systems: Phase Vocoder. Homomorphic Speech Analysis: Cepstral Analysis of Speech. Discrete Cosine Transform. MPEG-2 Audio and MPEG-2 AAC. Waveguides and Environmental Characteristics. Encoding in The Time Domain. Analysis of Audio and of Music. Zero Crossing Rate. Homomorphic Vocoder. Extraction of Perceptual Attributes of Music Signals. Silence Discrimination using ZCR and Energy. Applications: Voice over IP.3 SPEECH AND AUDIO PROCESSING SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Review of Audio Sources and Propagation Waves. Module 2: Frequency Domain Methods Short Time Fourier Analysis: Fourier Transform and Linear Filtering Interpretations. Predictive Encoding. Bit Localization Strategies. MPEG-4 Audio. Sinusoidal Plus Residual Modelling of Music Signals. Sound and Music Processing: Time Domain Methods . Auditory Physiology. Human Speech and Hearing: Human Speech Generation Mechanism. Perceptual Issues. Sub-Band Analysis. Human Hearing Characteristics. Module 3: Voice and Audio Encoding Systems General Block Diagram of a Voice and Audio Encoding System.

4. Eargle J. 2009. 1999. Elsevier. Synchronous Vs. 2. “Digital Sound Processing for Music and Multimedia”. L. H. 3. 1995.Module 4: Real Time Audio Processing Sampling. Communication Protocols (MIDI. John Watkinson. R. Nelson Morgan & Ben Gold. H. Van Nostrand Reinhold. Latency and Jitter. Speech. 24 . 7. ICA. Quatieri. G. & Hunt A. TCP. “Speech and Audio Signal Processing: Processing and Perception of Speech and Music” 1999. Kirk R. “Visual Data Flow"-Type Programming Languages for Real Time Audio. References: 1. Hansen J. Thomas F. Buffering. 8. Focal Press. Deller J. “Discrete Time Processing of Speech Signals”. 2001. and Similarity. Elsevier. Music Analysis & Recognition: Transcription. Pearson Education. “Video. and Model-Based Separation. Sound Mixtures and Separation: CASA. 2004.. Summarization. “The Art of Digital Audio”. OSC).. 2004. 6. Time Resolution. CRC Press. Asynchronous Models in the Generation and Processing of Real Time Interactive Sound. “Music Sound and Technology”. IEEE Press. John Wiley. “Discrete-Time Speech Signal Processing”. & Proakis J. Vijay Madisetti. 1999. Focal Press. Aspects of Control and of Mapping. Martin Russ. and Audio Signal Processing and Associated Standards”. UDP Vs. Focal Press. 5. “Sound Synthesis and Sampling”.

Execution. 25 . Case Study. Marwedel P. Springer. & Schirner G. System Design Tools. Doemer R. Gerstlauer A. Register Sharing. Verification”. Gajski D. “Embedded System Design: Modeling. Peng J. 2001. System Design Methodologies: Bottom-up Methodology. System Synthesis. Kluwer. Internal Communication.. Chaining and MultiCycling. Hardware Design Tools. Embedded Software Design Tools. Embedded Design Practice: System Level Design Tools. & Gajski D. “ Embedded System Design”. Springer. Software Synthesis Overview.MECAE 106 .. 2. Synthesis. Automatic TLM Generation. Functional Unit Sharing. Module 4: Hardware Synthesis RTL Architecture. Module 2: Modelling and Synthesis Models of Computation. System Design Trends. Abdi S. Processor-Level Models. Input Models. Register Merging. Processor Modeling. Code Generation. Estimation and Optimization. Platform Methodology. Control and Datapath Pipelining Scheduling. 3. System Design Languages. Startup Code. References: 1. Datapath Pipelining. Functional-Unit Pipelining. Connection Sharing. 2006. 4. Binary Image Generation. Top-down Methodology. System-level Synthesis. 2009.. Module 3: Software Synthesis Target Languages for Embedded Systems. Platform Synthesis. D. Multi-Task Synthesis. Interface Synthesis. Peckol & James “Embedded Systems: A Contemporary Design Tool”. System Modeling.4 EMBEDDED SYSTEM DESIGN L T P C 3 0 0 3 Module 1: System Design Methodologies System Design Challenges. Gerstlauer A. Processor Synthesis. 2008... FPGA Methodology.. John Wiley & Sons. System-Level Models. Meet-in-the-middle Methodology. RTOS. “System Design: A Practical Guide with SpecC”.

John Wiley & Sons. Martin G. Groetker T. 2001.. Kluwer. & Swan S.. “System Design with SystemC”. 26 .. Vahid F. & Givargis T.. 6. Liao S. “Embedded System Design: A Unified Hardware / Software Introduction”. 2002.5.

The students should undertake a detailed study on the topic and submit a report at the end of the semester. Tech. MECAE 108 SEMINAR – I L T P C 0 0 2 1 Each student shall present a seminar on any topic of interest related to the core / elective courses offered in the first semester of the M. He / she shall select the topic based on the references from international journals of repute. Marks will be awarded based on the topic. MECAE 102. MECAE 103 and MECAE 104 and the elective courses opted by the student in the first semester. 27 . They should get the paper approved by the Programme Co-ordinator / Faculty member in charge of the seminar and shall present it in the class. participation in the seminar and the report submitted.MECAE 107 ELECTRONIC SYSTEM DESIGN LAB . Programme. Every student shall participate in the seminar. presentation.I L T P C 0 0 3 2 System simulation experiments based on the courses MECAE 101. preferably IEEE journals.

Design Considerations for PCBs for Different Applications: Digital Circuits. Single-Point and Multipoint-Point Ground Systems. etc. Effect of Shield on Capacitive. Exceptions. FCC Regulations. Capacitive and Inductive Coupling. Practical Low Frequency Grounding. Signal Grounds. Expensive and Complex Service and Support. etc. Thermal Management for IC and PCBs. Simple Component Manufacture Vs. CISPR / IEC Regulations. SMT Technologies. Growth. Ground Loops. Lower Cost. Common Mode Choke. Shield Grounding at High Frequencies. Shield Transfer Impedance. Functional Ground Layout. Hardware Grounds. Design for Manufacturability. Designer Vs. Complex Manufacturing Process. Design Rule Checks: Signal Layer Checks. 28 . Grounding: Safety Grounds. Analog Circuits. Common EMC Units. Radiated Susceptibility. Automated Processes. Layout Rules and Parameters. Development of DFM Rules: Design Guidelines. Grounding of Cable Shields. Shielding Properties of Various Cable Configurations. Better Yield Etc. Different Equipment and Processes. Multilayer PCB. Inductive and Magnetic Coupling. Different Applications.MECAE 201 ELECTRONIC PRODUCT DESIGN L T P C 3 1 0 4 Module 1: Design for Manufacturability Introduction. Product Life Cycle Management. Mature and Saturation. Non-Ideal Behavior of Electronic Components. High Speed Circuits. Drill Check. etc. Guarded Instruments. Flexible PCB. Different Manufactures. Solder Mask Check. Need of DFM: Higher Quality. Practical Experiences and Concerns. Measurement of Radiated and Conducted Interference. Power / Ground Checks. Cooling Requirements. Radiated Emission. Hybrid Grounds. Complex and Expensive Components. Faster Time to Market. Electronic Cooling Methods. Through Hole Vs. Power Circuits. Module 2: PCB Design and Manufacturing Process Design Considerations for Different Types of PCBs: Single Layer PCB. Module 3: Electromagnetic Compatibility Conducted Emission. Manufacturer Need for Different DFM Techniques for Different Companies. Simple and Inexpensive Design Vs. Simple Assembly Process Vs. Conducted Susceptibility.

Materials for Microelectronic Packaging. Opto-Isolators. 29 . Owen Molloy. Henry W. 8. ESD Vs. ESD Protection in Equipment Design. Brown. 2nd Ed. Material for High-Density Interconnect Substrates. Isolation Transformers. Design Process. Signal Distribution. “Noise Reduction Techniques in Electronic Systems”. Module 4: Electrostatic Discharge and Electronic Packaging Electrostatic Discharge (ESD): Static Generation. “Design for Manufacturability and Statistical Design: Constructive Approach”. 2008. 2006.EMC Components : EMI Suppression Cables. Measurements. Power Distribution. Software and ESD Protection. 2001. “Engineering Electromagnetic Compatibility: Principles. Transient and Surge Protection Devices. Kawa & Jamil “Design for Manufacturability and Yield for Nano-Scale CMOS”. Michael Orshansky. Human Body Model. 5. 1998. 2nd Ed. “Design for Manufacturing and Assembly: Concepts. 6. References: 1. ESD Testing. Chiang. Architectures and Implementation”. Springer. Functions of an Electronic Package: Packaging Hierarchy. 1998. Springer. Driving Forces on Packaging Technology. Wiley. “Advanced Electronic Packaging”. 7.. 2007. Charles. 2009. “Electromagnetic Compatibility Engineering”. EMC Connectors. Ulrich &William D. Electrical Anatomy of Systems Packaging. 2nd Ed. Prasad Kodali V. Richard K. Wiley. Wiley. Sani Nassif & Duane Boning.. McGraw Hill. 3.. EMC. Wiley. EMC Gaskets. Static Discharge.. “Printed Circuits Handbook”. Electromagnetic Interference. Clyde F. Springer. 2. Technologies and Computer Models”. 2007. Coombs. Ott. Steven Tilley & Ernest Warman. Henry W Ott. 4.

Discrete Time Signals. Types of SHA / THA. Amplifier Output Errors. Current to Voltage and Voltage to Current Converters. Low Input Offset Voltage Op-Amps. Pipeline ADC. Module 2: Dynamic Analog Circuits Characteristics of MOSFET Switch. Charge-Scaling DAC. Low Input Offset Current Op-Amps. Sample and Hold Circuits: Sample and Hold / Track and Hold Amplifiers. First and Second Order Switched Capacitor Circuits. Models of Two-Phase Switched Capacitor Circuits. Op-Amp Noise. Module 3: Data Converter Fundamentals and Architecture Analog Vs. SHA and Analog Multiplexers. Comparators: Characterization. Characteristics of Op-Amps used in Data Converters. Amplifier Input Errors. Switched Capacitor Integrators. Current-Steering DAC. Analog Multiplexers. Wide-Swing Current-Mode R-2R DAC. Instrumentation Amplifier. Oversampling ADC. Noise Filtering. Low Noise Op-Amps. Mixed-Signal Layout Issues. Current Amplifiers. Difference Amplifiers. SHA / THA Performance Parameters. Successive Approximation ADC. Specifications of Analog-to-Digital Converter (ADC). Integrating ADC. Two-Stage Open-Loop Comparators. Input Offset Error. DAC Architectures: Resistor-String DAC. Module 4: Implementation of Data Converters Implementation of DACs: R-2R Topologies for DACs. Low Level and High Level. Topologies without an OP-Amp. Specifications of Digital-to-Analog Converter (DAC). ADC Architectures: Flash ADC. 30 . Implementation of ADCs: Implementing the Sample and Hold.MECAE 202 ANALOG AND DATA CONVERSION SYSTEM DESIGN L T P C 3 1 0 4 Module 1: Linear Op-Amp Circuits Review of Inverting and Non-Inverting Configurations. Current-Mode and Voltage-Mode R-2R DAC. Cyclic DAC. Implementing Cyclic and Pipelined ADCs Design of Multi Channel. Pipeline DAC. Data Acquisition Systems using ADC / DAC. Compensation in Op-Amp Circuits. Switched Capacitor Circuits: Switched Capacitor Amplifiers. High-Speed Comparators. Switched Capacitor Filters. Discrete-Time Comparators.

. “Mixed-Signal and DSP Design Techniques”. and Simulation”. Newnes. Jacob Baker R. Johns & Ken Martin.. McGraw Hill.. 3. 2008. David A. 31 . 2nd Ed.. Oxford University Press. 5. 2010. 2. Holberg. 4. Ltd. 6.References: 1. Analog Devices Inc. 2002. Walt Kester.. 2003. Layout. “CMOS Analog Circuit Design”. Walt Kester. 2004. Philip E.. “CMOS: Circuit Design. “Analog Integrated Circuit Design”. Franco S. Allen & Douglas R. 3rd Ed. Wiley India Pvt. Wiley. 2009. “Design with Operational Amplifiers and Analog Integrated Circuits”. Elsevier Science. “Analog-Digital Conversion”.

William S. 2. Speed and Power. Jan M. References: 1. Area Bonding. Module 3: Signalling Convention and Circuits Signalling Modes for Transmission Lines. Modelling of Wires: Geometry and Electrical Properties of Wires. Electrical Models of Wires. Signals and Events. Open Loop Timing Level Sensitive Clocking. Prentice Hall. 32 . Capacitance and Inductance Effects. “Digital Integrated Circuits: A Design Perspective”. Terminations. Noise Sources in Digital System: Power Supply Noise. Driving Lossy LC Lines. Cambridge University Press. 2008. “High Speed Digital Circuits”.MECAE 203 HIGH SPEED DIGITAL SYSTEM DESIGN L T P C 3 1 0 4 Module 1: Introduction to High Speed Digital Design Frequency. Intersymbol Interference. Local Power Regulation. High Speed Properties of Logic Gates. Transmission Lines: Lossless LC Transmission Lines. Howard Johnson & Martin Graham. Pearson Education Asia. Special Transmission Lines. 1996. Rabaey. Signalling over Lumped Transmission Media. 3. Anantha Chandrakasan & Borivoje Nikolic. Closed Loop Timing. “High Speed Digital Design: A Handbook of Black Magic”. Cross Talk. Addison Wesley Publishing Company. Onchip Bypass Capacitors. Symbiotic Bypass Capacitors. Time and Distance. 1993. Lossy LRC Transmission Lines. Pipeline Timing. Simultaneous Bi-Directional Signalling. Masakazu Shoji. “Digital Systems Engineering”. 2nd Ed. 2007. PLL and DLL Based Clock Aligners. Poulton. Synchronization Failure and Metastability. Dally & John W. 4. Signalling over RC Interconnect. Clock Distribution. IR Drops. Module 4: Timing Convention and Synchronisation Timing Fundamentals: Timing Properties of Clocked Storage Elements. Module 2: Power Distribution and Noise Power Supply Network. Transmitter and Receiver Circuits. Power Supply Isolation.

Folding. Projection of the Dependence Graph using a Projection Direction. and Signal-Flow Graphs. Module 2: Circuits and DSP Architecture Design Fast Filtering Algorithms (Winograd's. Synthesis Place-And-Route. Impact of Non Ideal Characteristics of Analog Functional Blocks on the System Performance. Canonic Signed Digit Arithmetic. Block Diagrams). Coefficient Quantization. Algebraic Technique for Mapping Algorithms. Distributed Arithmetic Architectures. The Delay Operator and Z-Transform Techniques for Mapping DSP Algorithms onto Processor Arrays. and Speed). Filter Structures (Recursive. Carry-Save Architectures. High Performance Arithmetic Unit Architectures (Adders. Modeling for Synthesis In HDL. Non-Recursive and Lattice). Multipliers. Short-Length FIR). Data Broadcast and Pipelining. Retiming and Pipelining. Module 3: DSP Module Synthesis Distributed Arithmetic (DA). System Modeling and Performance Measures.MECAE 204 DSP ALGORITHM AND ARCHITECTURE DESIGN L T P C 3 1 0 4 Module 1: DSP Algorithm Design DSP Representations (Data-Flow. Advantages of Using DA. Block Processing. Implementation of Elementary Functions Table-Oriented Methods. Computation Domain. Scheduling and Projection Functions. Analog Signal Processing for Fast Operation. Applications using Common DSP Algorithms. Fixed-Point DSP Design (A / D Precision. Behavioral Modelling in HDL. System Timing using the Scheduling Vector. Module 4: Parallel Algorithms and their Dependence Applications to Some Common DSP Algorithms. Bit-Serial. Polynomial Approximation Random Number Generators. Algorithmic Simulations of DSP Systems in C. 33 . Power. Dividers). Dependence Matrix of a Variable. Bit-Parallel. Control-Flow. FFT. Redundant Number System. VLSI Performance Measures (Area. Size Reduction of Look-Up Tables. Structural Modeling in VHDL. Round-off and Scaling). Linear Feedback Shift Register. Digit-Serial.

Kuo. Sen M. “DSP Principles. 2002. John G. Natick. 6. K. Peters. Oxford University Press. Pirsch. Proakis & Dimitris Manolakis K. John Wiley & Sons. “Computer Arithmetic Algorithms”. 1995.References: 1. “Architectures for Digital Signal Processing”. 2. 4. Prentice Hall. 1998. 2004. 3. “Digital Signal Processing with Field Programmable Gate Array”. 1999.Verlag. and Applications”. 7. 2000. 34 . Prentice Hall. Design and Implementation”. Implementations. 1999. Algorithms and Applications”. 8. Uwe Meyer-Baese. 5. Parhami & Behrooz “Computer Arithmetic: Algorithms and Hardware Designs”. John Wiley & Sons. 2001. Springer. Lars Wanhammar. Parhi. “VLSI Signal Processing Systems. Gan. “DSP Integrated Circuits”. “Digital Signal Processors: Architectures. Israel Koren & A. Woon-Seng S. Keshab K. Academic Press.

Performance Gains. Capacity of Cellular CDMA Networks. 35 . 3G Systems: UMTS & CDMA 2000 Standards and Specifications. Receive Diversity. Module 3: Spread Spectrum and CDMA Direct Sequence Spread Spectrum (DS-SS). Diversity: Time Diversity. Co-Channel Interference Analysis. Cellular Wireless Communication Standards: Overview of Second Generation Cellular Wireless Systems: GSM and IS-95 Standards. Frequency and Space Diversity. Multiple Access: FDMA. Hard and Soft Hand-off Strategies. Spectral Efficiency and Grade of Service. Vision of 4G Standards. Rake Receiver. Erlang Capacity Analysis. Performance Analysis. Maximal Ratio Combining. Module 2: Cellular Communication Cellular Networks. Spatial Reuse. ISI and Narrow Band Interference Rejection. Concept of Diversity Branches and Signal Paths.MECAE 205 . Diversity in DS-SS Systems. Frequency Hopping Spread Spectrum (FH-SS). Gold Codes. Review of Performance of Digital Modulation Schemes over Wireless Channels. Code Design. Hand-off. Reverse Link Power Control.Maximal Length Sequences. Design of SS Transmitters. Module 4: Capacity and Standards Capacity of Wireless Channels: Capacity of Flat and Frequency Selective Fading Channels. Design of SS Receivers. TDMA. Equal Gain Combining. Statistical Fading Models. Narrow Band and Wideband Fading Models. Improving Capacity: Cell Splitting and Sectorization. Combining Methods: Selective Combining.1 WIRELESS COMMUNICATION SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Fading and Diversity Wireless Channel Models: Path Loss and Shadowing Models. CDMA Systems: Interference Analysis for Broadcast and Multiple Access Channels. Performance Analysis for Rayleigh Fading Channels.

Prentice Hall of India. “ Modern Wireless Communications”. J. 2nd Ed. 3. L. L. principles & practice”. Pearson Education.. 1995. 2007. Andrea Goldsmith. 4. 2002. 36 . “Wireless Communication. Viterbi A. Kluwer Academic Publishers. Addison Wesley. 2001. E. “Introduction to Spread Spectrum Communication”. “CDMA: Principles of Spread Spectrum”. 2. Person Education. & David E.References: 1. Stuber G. Borth. 6. “Wireless Communications”. 5. Peterson R. Ziemer R. S. “Principles of Mobile Communications”.. Simon Haykin & Michael Moher. 1995. Cambridge University press. Rappaport T.. 2006.

Hybrid Technology: Thin Film. & Amarjit Singh. 3. DRC and LVS. References: 1. Etching and Photo Resist. 1975.MECAE 205 -2 RF INTEGRATED CIRCUIT DESIGN L T P C 3 0 0 3 Module 1: Elements of Microwave Integrated Circuits (MIC) Planar Transmission Line. Variational Approach. Parasitic Extraction. Time and Frequency Domain Circuit Simulation. Heat Dissipation. Module 3: RF IC Design Flow System Design and Behavioral Modelling. Springer. Schematic Entry and Design Environment. 2004. Method of Conformal Transformation. Module4: Coupled Microstrip. Verification in System Bench. Directional Couplers. Hoffman R. Elsevier. Dielectric and Resistive Materials. Layout. 2. Thick Film and Mid Film Technologies. Maloratsky. Planar Transmission Lines. RFIC Packaging and System Integration. Transverse Transmission Line Technique. Power. Parameter Tradeoffs. Directional Couplers Introduction to Coupled Microstrip. RFIC Layout. K. Frank Ellinger. “Passive RF & Microwave Integrated Circuits”. 1987. Steps Involved in the Fabrication of MOSFET. MMIC Fabrication Techniques. Epitaxial Growth. “Microwave Integrated Circuits" John Wiley & Sons. Lumped Element for MIC. Conductor. Module 2: Microwave Integrated Subassemblies Salient Features of MICs. 4.. C. 2007. Diffusion and Ion Implantation. Method of Analysis TEM Analysis. Monolithic Technology. Artech House Publishers. Substrate for MIC. Leo G. “Radio Frequency Integrated Circuits and Technologies”. System Design Considerations: Packaging. Electromagnetic Extraction. Finite Difference Method. Branch Line Coupler. Gupta K. Deposition Methods. Lithography. Even and Odd Mode Analysis. Oxidation and Film Deposition. “Handbook of Microwave Integrated Circuits”. Characteristics and Properties of Substrate. 37 .

Artech House. Joseph J. 6. 2003. 2002. “RF Components and Circuits”. Carr.5. 38 . Inder Bahl. Newnes. “Lumped Elements for RF and Microwave Circuits”.

Effect of Data Types and Memory Map: TMS320C6713 Assembly Language Programming: Instructions Set And Addressing Modes. Analog Devices DS Processors: Introduction to Sharc / Tiger Sharc / Blackfin Series. “Digital Signal Processing Implementation Using the TMS320C6000 Processors”. On Chip Peripherals: Timers. 4. “Digital Signal Processing and Applications With the C6713 and C6416 DSK”. Writing Efficient Code: Optimizing Compiler. Module 4: Current Trends Current Trend in Digital Signal Processors: DSP Controllers. Architecture Trends of Other Texas Instruments DSP Processors.. CPU Architecture. Multi Channel Buffered Serial Ports. Processor Trends: Von Newmann Vs.3 DSP SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Introduction Need for Special Digital Signal Processors. 2000. Quantization and Working with the AIC23 Codec. Sampling.ti.MECAE 205 . John Wiley & Sons. Code Composer Studio IDE. Review of IIR Filtering: IIR Filter Design Techniques and Tools. Architectures of Superscalar and VLIW Fixed and Floating Point Processors. Online TI Materials for the TI C6713 DSK Board: http://www. Module 3: Filter Design Techniques Design Aspects: Introduction to the C6713 DSK. Review of FIR Filtering: FIR Filter Design Techniques and Tools. New Digital Signal Processing Hardware Trends. Pipelining. Internal Data / Program Memory. CPU Data Paths and Control. References: 1. 2004. Naim Dahnoun. Chassaing R. Prentice Hall. Extended Direct Memory Access. 3. User's Manuals of Various Fixed and Floating Point DS Processors. 39 . Harvard Architecture. Selection of DS 2. Module 2: Typical DS Processor Introduction to a Popular DSP from Texas Instruments (TMS330C6000 Series). Interrupts. Architecture of TMS320C28XX Series DSP and its Applications. Other Major Vendors in the DSP Market and the Latest Trends. Linear Assembly. Matlab and Basic Skills.

Prentice Hall. 2009.. W. Manolakis. Joseph G. Algorithms and Applications”. “Digital Signal Processing: A System Design Approach”. Pearson. Hodgkiss. Wiley India. Pearson. “Digital Signal Processing: Principles. De Fatta. 6. 2nd Ed. 1989. and Applications”. 40 . 7. Implementations. 2007. Sen M. “Digital Signal Processors: Architectures. 8. John G. 2005. Lucas & William S. Proakis & Dimitris G. David J. 4th Ed. Kuo & Woon-Seng Gan. Oppenheim A. & Schafer R..5. “Discrete-Time Signal Processing”. V..

Block Level Verification. Routing. Verification Methodology. Floor Planning & Placement. Soft IP Vs. Half Gate ASIC. MPSoCs. 41 . Faranak Nekoogar & Jeffrey Ebert. References: 1. Cell Compilers. Economics of Asics. Design for Timing Closure. “From ASICs to SOCs: A Practical Approach”. Physical Design Issues. Logical Effort Programmable ASIC Design Software: Design System. Module 2: ASIC Library Design Transistors as Resistors. Manufacturing Test Strategies. Hard IP.4 ASIC DESIGN L T P C 3 0 0 3 Module 1: Types of Asics Design Flow. Logic Design Issues.MECAE 205 . 2008. Verification Strategy. Hardware / Software Co-Verification. Techniques for Designing MPSoCs. Specification Requirements. Logic Synthesis. System Design Process. Verification Approaches. Spiral. Parasitic Capacitance. Farzad Nekoogar . Prentice Hall. “Application Specific Integrated Circuits”. System Level Verification. ASIC Cell Libraries. CMOS Logic Cell Data Path Logic Cells. I / O Cells. 2003. and Verification Plans. 2. Types of Specifications. SoC Design Flow. Bottom-Up. Michael John Sebastian Smith. Top-Down Vs. Module 4: Soc Verification Verification Technology Options. Waterfall Vs. System Level Design Issues. and Static Net List Verification. Verification Languages. Module 3: System on Chip Design Process A Canonical SoC Design. Pearson Education India. Low Power. On-Chip Buses and Interfaces. ASIC Construction.

Transmission Windows. Plastic and Polymer-Clad-Silica Fibers. Outdoor Cables. Attenuation. and Coherent Detection. Gain Equalizer. WDM and Hybrid Multiplexing Methods. Network Architecture: SONET / TDH. OFDM. Power Splitter. Combiner. Multimode Fibers. Very Low Loss Materials. Broadcast and Select WDM Concepts. Filters. The Numerical Aperture (NA). Space. First and Second-Generation System. Dispersion Flattened Fiber. Future Systems. Fiber Dispersion. Constrained Coding.1 OPTICAL COMMUNICATION SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Review of Fiber Optic Communication Systems Evolution. Noise Sources. Detectors and Receivers. Cut-Off Condition and V-Parameter. Wave Propagation in Step Index and Graded Index Fiber. Optical Access Network. MAC Protocols. Absorption. and Optical Transmission System Design. Bending Loses. Gratings. Optical Switching and Routing. Passive and Active Devices. Power Budget. Advanced Modulation Formats. Computer Networks. Local Distribution Series. Polarization Multiplexing. Optical Premise Network. Module 2: Fiber Optic System Design Considerations and Components Indoor Cables. Local Data Transmission. and Wavelength Granularity. Network Element Technology: (D)WDM Technology. Polarization. Subscriber Multiplexing (SCM). Add / Drop Mux. Single Mode Fibers. Dispersion. Network Topologies. Time. Different Losses and Issues in Fiber Optics. Electrical and Optical Bandwidth. Module 3: Advanced Multiplexing Strategies Optical TDM. Bandwidth and Rise Time Budgets. Wavelength Routed 42 . Dispersion Shifted Fiber. Channel Impairments. Benefits and Disadvantages of Fiber Optics. Module 4: Optical Networking Data Communication Networks. Advanced Optical Signal Processing. Connectors and Splices. Digital Optical Fiber Communication System. Scattering. Light Sources and Transmitters. Connectors. Types of Fiber. Coupler. Functions of Photonic Integrated Circuits. Optical Fiber Communication System: Telecommunication. Transmission through Optical Fiber. Cabling Example. Signal Processors. Optical Transport Network. Fiber Optic Couplers.MECAE 206 . The Optical Fiber.

43 . Javier Aracil. Springer. Devices. Solitons. 2.. Introduction to IP Over WDM. Masataka Nakazawa. 2010. Volume II. Optical Packet Switching.Protocols. Springer. “Elements of Photonics”. 2008. 3. Optical CDMA. “OFDM for Optical Communications”... Optical Society of America. 2002. 2001. “High Spectral Density Optical Communication Technologies”. Elsevier. Iizuka K. 2009. 4.. Optical Burst Switching. & Djordjevic I. “Enabling Optical Internet with Advanced Network Technologies”. and Systems for Optical Communications”. 3rd Ed. John Senior. Prentice Hall. Shieh W. “Optical Fiber Communications: Principles and Practice”. 2009. Performance of WDM + EDFA Systems. Optical Switch Fabrics OSFs and their Application. Wiley. 5. McGraw Hill. 6. “Fiber Optics Handbook: Fiber. References: 1.

Scattering Matrix of a Two Port Network. Properties of the Scattering Matrix. Scattering Matrix Representation of Microwave Networks. N-Port Microwave Network. Even and Odd Mode Analysis. Distributed-Element Matching Networks. Module 2: Analysis of Symmetrical Networks Introduction. Qualitative Description of Two-Hole and Multi-Hole Waveguide Couplers. Signal Flow Graphs. Directional Couplers: Performance Measures. Odd Mode and Layout. Transmission (ABCD) Matrix. Generalized Scattering Parameters.2 RF AND MICROWAVE NETWORK DESIGN L T P C 3 0 0 3 Module1: Microwave Network Analysis Equivalent Voltages and Currents. Short Circuit Admittance Parameters of a Π-Network. Parallel Line Coupler: S-Parameter Determination. Transmission Loss. Return Loss. Wilkinson Power Divider. Salient Features of Multiport Network. Insertion Loss. Losses in Microwave Circuits. Coupler Applications. Coupler Scattering Matrix. S-Parameters at Arbitrary Planes. S-Matrix for H-Plane Tee Junctions. Input Considerations. Impedance Matrix. Equivalent Circuits for Two-Port Networks.MECAE 206 . Concept of Impedance. Lumped-Element Matching Networks. S-Matrix for E-Plane Tee Junction. Simultaneous Conjugate Match Theorem for A 2-Port Passive Lossless Circuit. Input and Output Matching Network Theorem. Definition of Scattering Matrix. T-Junction Power Divider. Microwave One-Port Network. Determinate Theorem For 2-Port Passive Lossless Circuits. Salient Features of S-Matrix. Reflection Loss. Even and Odd Mode Analysis. Types of 4-Port Couplers. Magnitude Theorem For 2-Port Passive Lossless Circuits. Impedance and Admittance Matrices of Microwave Junctions. Odd Mode. Bandwidth Considerations for Matching Networks. Performance 44 . Even Mode. Branchline Coupler: Even and Odd Mode Decomposition. S-Matrix of Series Element in the Transmission Line. Mode Decomposition: Even Mode. Module 3: Power Dividers and Couplers Scattering Matrix of 3-Port and 4-Port Junctions. Mode Decomposition. Symmetry of Input Impedance and Reflection Coefficient. Hybrid Junctions.

Ferrite Loaded Waveguides. 2. Robert E. Leo G Maloratsky. 1997. 45 . 2007. McGraw Hill. Ferrite Circulators. “Foundations for Microwave Engineering”. Isolators and Phase Shifters. Sorrentino R. 2nd Ed.” John Wiley. 2006. & Bianchi G.. Design Procedure. Permeability Tensor. Prentice Hall. 2004. Birefringence. John Wiley & Sons. Wave Propagation in Ferrite Medium. Guillermo Gonzalez. 7. Lang Couplers. 2010. “ Microwave Engineering”. Module 4: Ferrimagnetic Components Microwave Ferrites. David M.. Faraday Rotation. Wiley India. Carr. 6. Pozzar.. “Microwave and RF Engineering. 5. “RF Components and Circuits “.Comparison. “Microwave Transistor Amplifiers: Analysis and Design”. 2002. References: 1. 1992. “Passive RF & Microwave Integrated Circuits”. 3. Collin. Joseph J. Directivity Enhancement Techniques for Microstrip Parallel Line Couplers: Analysis. Hee-Ran Ahn. 2nd Ed. “Asymmetric Passive Components in Microwave Integrated Circuits”. 4. Newnes. Elsevier.

Simultaneous Estimation of Several Parameters. Passive Listening. 46 . 2011. Springer. Samuel S. Sensor Arrays. Estimation of a Parameter. 3. Stationary Colored Noise and Infinite Observation Time. Adaptive Processing. 2. Richard P. 2002. Detection Performance. System Simulation Technique in Digital Sonar Design. Tracking Target Motion Analysis and Localization. François Le Chevalier. Optimum Reception in White Noise: Principle. Artech. Module 3: Tracking Modeling Detection and Tactical Decision Aids. The Active Radar or Sonar Signal. The Ambiguity Function. 4. Physical Interpretation. Wiley. “Design and Analysis of Modern Tracking Systems”. 2010. 1999. Receiver Structure. “Underwater Acoustics: Analysis. Adaptive Filtering using a Transversal Filter. “Principles of Radar and Sonar Signal Processing”. References: 1. Cumulative Probability of Detection.MECAE 206 . Examples of Typical Modern Digital Sonar. Blackman & Robert Popoli. Adaptive Whitening. Design and Evaluation of Sonars and Radars. Passive Listening. Optimum Receiver. Li Qihu. Design and Performance of Sonar”. Module 4: Digital Sonar System Design of Digital Sonar: Implementation Method of Various Function of Digital Sonar. MUSIC. Optimum Detection. Module 2: Reception in Colored Noise Optimum Reception in Colored Noise. Artech. Optimum Detector. Application to Spurious Echoes or Jammers. Space-time Processing. Hodges. “Digital Sonar Design in Underwater Acoustics”.3 DETECTION AND TRACKING SYSTEM DESIGN L T P C 3 0 0 3 Module 1: Reception in White Noise Introduction.

ARM-7. Protocol Implementation On Microcontroller And Processors: Device Awareness: PIC. Networked Embedded Systems in Industrial Automation: Fieldbus Systems. 80211. Module 3: Device Drivers Recapitulation of Kernel Mechanisms. 12C. WLAN Authentication and Data Transfer Protocols: TCP / IP 80211.11. Module 2: Embedded Communication Systems Standards for Embedded Communication.MAE 206 . Configuring Network Devices. Module 4: Automotive Networked Embedded Systems Trends. Task Synchronization: Mutual Exclusion. Block Drivers. MP3 Decoding Using C. Writing Codes for Serial Communication in C or CPP.B. System Software for Automotive Applications. Mobile Operating Systems. Java Enabled Information Appliances. OS: Ucos2. Security Issues in Embedded Communication. 8051. Scheduling Algorithms: Priority Based. etc. LIN Standard. Character Drivers. Bluetooth. SPI. RTOS: OS Basics. Porting RTOS or EOS on a Hardware Platform.G. OS Compilation and Optimization. Linux Internals. 802. WLAN and WPAN for Industrial Environments. Wireless Communications like IrDA. 80211. AVR. Embedded Operating Systems. USB.A. Ethernet. Device Driver and Networking Stack Development. Voice-Over IP. Mobile Java Application (Jini). Time Triggered Communication. Round-Robin. USART.. Shortest Job First. Semaphores. Embedded Database Applications. Firewire. Encryption Protocols. CAN for Embedded Systems. Device Driver Development on Linux. etc.4 EMBEDDED NETWORK DESIGN L T P C 3 0 0 3 Module 1: Programming for Embedded Systems Pointers and Memory Mapping in Operating System. C Internals. Real Time OS Kernel Architecture. 47 . FIFO. Real-Time Ethernet. Network Drivers. Linux. CAN.

2. PHI Learning. “Programming for Embedded Systems: Cracking the Code”. 2nd Ed. 2009. “Designing Embedded Hardware”. Daniel Wesley Lewis. 48 . 2009. Kaiser. 2009. “Fundamentals of Embedded Software: Where C and Assembly Meet”. Gregory J. John Catsoulis..References: 1. “Embedded Systems Handbook. Pottie & William J. Cambridge University Press. 2009. Second Edition: Networked Embedded Systems”. Dreamtech Software Team. Richard Zurawski. O’reilly Media. 5. 2005. 4. 3. CRC Press. “Principles of Embedded Networked Systems Design”.

MECAE 202. presentation. MECAE 203. Tech. preferably IEEE journals. MECAE 204 and the elective courses opted by the student in the second semester. They should get the paper approved by the Programme Co-ordinator / Faculty member in charge of the seminar and shall present it in the class. Programme. 49 . participation in the seminar and the report submitted. Every student shall participate in the seminar. The students should undertake a detailed study on the topic and submit a report at the end of the semester. He / she shall select the topic based on the references from international journals of repute.MECAE 207 ELECTRONIC SYSTEM DESIGN LAB -II L T P C 0 0 3 2 System simulation experiments based on the courses MECAE 201. Marks will be awarded based on the topic. MECAE 208 SEMINAR – II L T P C 0 0 2 1 Each student shall present a seminar on any topic of interest related to the core / elective courses offered in the second semester of the M.

which is useful in the field or practical life. Emphasis should be given to the introduction to the topic.I thesis report covering the content discussed above and highlighting the features of work to be carried out in Phase – II of the thesis. Student should submit two copies of the Phase . At the end of the training he / she have to submit a report on the work being carried out. and scope of the proposed work along with some preliminary work / experimentation carried out on the thesis topic. Student should follow standard practice of thesis writing. literature survey. It is expected that students should refer national & international journals and proceedings of national & international seminars.I) shall consist of research work done by the candidate or a comprehensive and critical review of any recent development in the subject or a detailed report of project work consisting of experimentation / numerical work. MECAE 302 MASTER’S THESIS PHASE . At the end of the training he / she have to submit a report on the work being carried out.I of the thesis. In Phase .I L T P C 0 0 10 5 The thesis (Phase . These examiners should give suggestions in writing to the student to be incorporated in the Phase – II of the thesis. 50 . design and or development work that the candidate has executed. The candidate will deliver a talk on the topic and the assessment will be made on the basis of the work and talks there on by a panel of internal examiners one of which will be the internal guide. it is expected that the student should decide a topic of thesis. OR ii) An Industrial Training of 1 month duration and Mini Project of 2 months duration in an industry / company / institution approved by the institute under the guidance of a staff member in the concerned field.MECAE 301 INDUSTRIAL TRAINING AND /OR MINIPROJECT L T P C 0 0 20 10 The student shall undergo i) An Industrial Training of 12 weeks duration in an industry / company / institution approved by the institute under the guidance of a staff member in the concerned field.

They should have submitted the paper before M. The work carried out should lead to a publication in a National / International Conference. 51 . MECAE 402 MASTER’S COMPREHENSIVE VIVA A comprehensive viva-voce examination will be conducted at the end of the fourth semester by an internal examiner and external examiners appointed by the university to assess the candidate’s overall knowledge in the respective field of specialization. evaluation and specific weightage should be given to accepted papers in reputed conferences.MECAE 401 MASTER’S THESIS L T P C 0 0 30 15 In the fourth semester. the student has to continue the thesis work and after successfully finishing the work. Tech. he / she have to submit a detailed thesis report.

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