SIMULATION OF DOUBLE GATE TUNNEL FIELD EFFECT TRANSISTOR

REQUIREMENT FOR THE AWARD OF THE AWARD OF THE DEGREE OF Bechelore of Technology in Electronics and Communication Engineering

Rasika Gupta Beena Kothari Jyotsana Rawat Parvati Bhandari

2012
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING G B PANT ENGINEERING COLLEGE PAURI GARHWAL (UTARAKHAND)-246194

Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii Certificate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowlegement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 1.2 1.3 1.4 MOTIVATION FOR THE PRESENT RESEARCH . . . . . . NATURE OF THE PROBLEM . . . . . . . . . . . . . . . . . . RECENT RESEARCH RELEVANT TO THE PROBLEM . RESEARCH PROBLEM STATEMENT . . . . . . . . . . . . . ix x xi 1 1 3 3 5 6 6 6 6 7 7 9 10 13 14 14

2. DEVICE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 SEMICONDUCTOR PHYSICS . . . . . . . . . . . . . . . . . . 2.1.1 SILICON CRYSTAL STRUCTURE . . . . . . . . . . . . 2.1.2 2.1.3 2.2 2.3 2.4 ENERGY BAND THEORY . . . . . . . . . . . . . . . . . ELECTRONS AND HOLES . . . . . . . . . . . . . . . .

2.1.4 DOPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET AND ITS CHARACTERISTICS . . . . . . . . . . . 2.2.1 OPERATING MODES . . . . . . . . . . . . . . . . . . . . CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 SCALING AND POWER DENSITY . . . . . . . . . . . BAND-TO-BAND TUNNELING TRANSISTOR . . . . . . .

Contents

iii

2.5 2.6

2.4.1 PRINCILPLE OF OPERATION . . . . . . . . . . . . . . ADVANTAGES OF PIN TFET OVER MOSFET . . . . . . . DEVICE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . DEVICE PARAMETERS . . . . . . . . . . . . . . . . . . WORKING . . . . . . . . . . . . . . . . . . . . . . . . . . . BAND TO BAND TUNNELING TRANSMISSION . SUB-THRESHOLD SWING IN TUNNEL FETS . . . TUNNEL FET TEMPERATURE CHARACTERIS . .

15 16 17 17 18 18 19 22 25 27 27 27 27 28 34 35 35 37 38 38 40 40 40 41 41 41 41 45 45 47 48 52 52

3. DEVICE SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 SILVACOS ATLAS DEVICE SIMULATOR . . . . . . . . . . . 3.1.1 3.1.2 3.1.3 3.2 3.3 ATLAS INPUTS AND OUTPUTS . . . . . . . . . . . . MODES OF OPERATION . . . . . . . . . . . . . . . . . ORDER OF COMMANDS . . . . . . . . . . . . . . . . .

Comparison between MOSFET and DGTFET Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGTFET PARAMETERS OPTIMIZATION . . . . . . . . . . 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 DIELECTRIC CONSTANT OF GATE DIELECTRIC THICKNESS OF SILICON BODY . . . . . . . . . . . . CHANNEL LENGTH . . . . . . . . . . . . . . . . . . . . GATE WORK FUNCTION . . . . . . . . . . . . . . . . . GATE DI-ELECTRIC THICKNESS . . . . . . . . . . .

3.4

RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 STRUCTURE AND PARAMETERS . . . . . . . . . . . 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 ON-CURRENT OF DGTFET . . . . . . . . . . . . . . . TRANS-CONDUCTANCE VS VGS CURVE . . . . . ENERGY BAND DIAGRAMS . . . . . . . . . . . . . . . ELECTRIC FIELD . . . . . . . . . . . . . . . . . . . . . . POTENTIAL . . . . . . . . . . . . . . . . . . . . . . . . . . CURRENT FLOWLINES . . . . . . . . . . . . . . . . . .

4. CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 FUTURE SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . A. DECKBUILD CODING FOR ATLAS . . . . . . . . . . . . . . . . . . . . A.1 Code for ON-current comparison between DGTFET before optimization and after optimization . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . 55 . . . . . .2 Code for contour plots comparison between DGTFET before optimization and after optimization .Contents iv A. . . . . . . . . . . . .

12 : Energy band diagrams taken horizontally across the body of a Tunnel FET in (a) the off-state where the only current comes from p-i-n leakage. . . . . . . . crystal lattice structure doped with a Boron impurity . . . . . . . . . . .10 Left: Structure of a n-i-p Tunnel FET with external voltage sources. . . . A basic energy diagram at room temperature . . Structure of a MOSFET . . crossection of MOSFET operating in saturation . . 14 15 18 19 . . . . . . . . . .11 n-FETs. . . . . . .4 2. . . . . . . . . . and (c) the on-state with a positive bias on the gate leading to nFET-type behavior. . . SiO2 and high. . . . . . . .6 2. . . . . . . .8 2. . . . . . .7 2. . . . . . . . . . . . 2. . Structure of a CMOS . . . . .gate dielectrics . . (b) the on-state with a negative bias on the gate leading to pFET-type behaviour.List of Figures 2. . . . . . . . . . . . . . . . . . . .5 2. . . . . . crossection of MOSFET operating in linear region . . .1 2. . . . The Fermi-distributions in source and drain are plotted in gray . . . . . . (b) DG. . . . . . . . . .9 A simple diagram of an isolated si atom and si crystal structure . . . . .2 2. . . . (a) Active power consumption has been increasing with shrinking technology nodes (b)Standby leakage power also increasing with shrinking 8 8 8 9 10 11 12 13 technology nodes. . .3 2. . The bandgap blocks any current flow between source and drain. . . . . . 2. . . . . . . . Right: Band profile of the Tunnel FET in the off-state without applied VDS. . . . . . 2. . A basic energy diagram at 0K . . . . . . . . . (a) Single-gate. .

. . Ioff increases. .5 3. . .1 3. DGTFET Transfer Characteristics for various Gate Dielectric . . . . Inset: Subthreshold swing at specific VGS values. . . . . . . . . . . . . . . DGTFET Transfer Characteristics for various Gate Dielectric . 2. .8 3. . . .13 : Band-to-band tunneling can be calculated by approximating the energy barrier width by a triangular potential energy barrier. ATLAS Doping Profile of DGTFET . .18 Simulated IDS-VGS characteristics for various temperatures for a doublegate Tunnel FET with dielectric = 21. . . . . . . . . . . . . . . . . . . . . . .9 ATLAS Inputs and Outputs . . . . . . . . . . . . where the electrons must tunnel through the widest distance at the base of the triangle. . . . .14 Energy band cross section of a Tunnel FET showing the triangular barrier approximation within the bands. 2. . . . . . 3. . . As temperature increases. . . . .2 3. . ATLAS Mesh and Region Boundaries for a DGTFET . . . . . Characteristics of a simplified single-gate NMOSFET for various gate dielectrics. . but Ion changes very little. . 3. . . . . . . . . . . . Comparison of mesh grids when using a multiplier of 5 and 1 . . . . . . . . . . . . . . . . 24 2. . the screening length . Some of the mobility models available in ATLAS . 3. . . . L=50 nm. . . . . . tox=3 nm. . . . . .15 Dependence of the Tunnel FET subthreshold slope on gate voltage for 20 22 different dielectric constants . . .6.11 DGTFET Trans-conductance (gm) vs VGS Curve for various tsi . vs. .7 3. . . . . . . . . . . . . and the filtering behavior of the device in the on-state . . . . . . . .4 3. . . . . . . . . . . .10 DGTFET Transfer Characteristics for various tsi . . . . . . . . . . . . . . . . . . . L . . . . . .3 3. . . . . . . . . . . . . . . . . . . . . . . . .1) . . . . .6 3. . . tsi=10 nm) . 3. . . .16 comparison of IDS-VGS for a conventional MOSFET and a Tunnel FET 24 2. . . . . .12 DGTFET Transfer Characteristics for various channel lengths. and average swing.14 DGTFET Transfer Characteristics for various gate work function . . . . . . DGTFET Trans-conductance (gm) vs VGS Curve for various Dielectrics 24 25 30 30 30 31 32 34 34 36 36 37 37 38 38 39 (VDS=1V. . The swing is only slightly affected by changes in temperature. . . . 3.List of Figures vi 2. . . 2. . . . . . 3. . temperature in Kelvin.13 DGTFET Trans-conductance (gm) vs VGS Curve for various L (Other parameters are same as for Fig. . taken at the steepest point of the IDS-VGS curve. . . . VDS = 1 V. . . . . . taken as the average from turn-on to threshold. . . . . . . .17 Visual definitions of point swing. . . .

3.20 Comparison of transconductance vs VGS curve for optimized DGTFET and DGTFET before optimization . . . . 3. 3. . . . . . 3. .28 Contour plot of current flowlines in DGTFET after optimization . . . . . . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . . .22 Energy Band Diagram of DGTFET after Optimization . . . . . .26 Contour plot of potential across DGTFET after optimization . . . . . . . . . . . .List of Figures vii 3. . 3. . . . . . .17 DGTFET Trans-conductance (gm) vs VGS Curve for various gate dielectric thickness . . 3. . 3. .18 Optimized structure of DGTFET . . . .16 DGTFET Transfer Characteristics for various gate dielectric thickness 3. . . . . . . . . . .15 DGTFET Trans-conductance (gm) vs VGS Curve for various gate work function . . 3.25 Contour plot of potential across DGTFET before optimization .21 Energy Band Diagram of DGTFET before Optimization . . . . . . . . . . . .27 Contour plot of current flowlines in DGTFET before optimization . . .23 Contour plot of Electric Field across DGTFET before optimization . . . . . 3. . . . . . . . . . . 3. . . . . . . . . . . 3. . 39 40 42 42 42 43 43 43 44 44 45 45 46 46 . . . . . . . . .24 Contour plot of Electric Field across DGTFET after optimization . . . . . . . . .19 Comparison of ON-Current for optimized DGTFET and DGTFET before optimization . . . . . .

which are gated p-i-n diodes whose on-current arises from band-to-band tunneling. are attractive new devices for low-power applications due to their low off-current and their potential for a small subthreshold swing. Numerical simulations based on correct underlying models are important for emerging devices. The numerical simulations presented in this thesis have been carried out using a non-local band-to-band tunneling model in Silvaco Atlas. . and can be the basis for the formation of an accurate compact model. in which static power consumption is becoming too high.Abstract The down-scaling of conventional MOSFETs has led to an impending power crisis. since they can provide insights about optimization before fabrication is carried out. can aid the understanding of device physics through 1D and 2D cross sections. small swing switches are interesting candidates to replace or complement the MOSFETs used today. In order to improve the energy-efficiency of electronic circuits. Tunnel FETs.

Balraj Singh Assistant Professor Deptt of Electrical & Electronics Engg G. Pauri Garhwal (Uttarakhand) for the award of Bachelor of Technology in Electronics and Communication Engineering. Pant Engineering College Pauri Garhwal (UK)-246194 . I wish them all success in their future endeavours. G B Pant Engineering College. BEENA KOTHARI. Pauri Mr. Date: 2 June 2012 Place: GBPEC. The results embodied in the report have not been submitted for the award of any other degree.Certificate This is to certify that the project entitled “SIMULATION OF DUAL GATE TUNNEL fIELD EFFECT TRANSISTOR” being submitted by RASIKA GUPTA.JYOTSANA RAWAT AND PARVATI BHANDARI to Department of Electronics and Communication Engineering.B. is a bonafide work carried out by them under my guidance and supervision.

looking at dielectric constant of gate dielectric (ox). . gate work function () and gate dielectric thickness (tox). For this reason. Numerical simulations have proven to be an effective means to investigate Tunnel FET behaviour and the dependence of its static characteristics on changes in dimensions. The work presented here can be useful to other researchers who will be designing and fabricating Tunnel FETs. without requiring processes whose mastery lies many years in the future.Preface One goal of this thesis is to stay within the framework of what is possible in standard industrial nano-electronics clean-rooms today. the focus of this thesis is on all-silicon devices The optimization of the static characteristics of a Tunnel FET is carried out. silicon body thickness (tsi). Channel Length (L). and developing analytical and compact models for these devices. doping. and other parameters.

).C. the project guide who helped us find this interesting thesis topic.O.) and Dr. O.P. ECE Department. Balraj Singh.Acknowlegement This little work of creation would not have been possible without the kind help. coordination and extended support of some people. Asst Professor. Singh (H. GBPEC for providing us the facilities and making us strive for the best possible output under their ardent observations. Singh (H.B. Gautam. K.D. We would like to thank Dr. Associate Professor. intelligent instructions in the details of semiconductor device operations and for sharing his knowledge and working with us on several Tunnel FET studies and publications. Thanks first and foremost to Mr. Y. for his guidance. RASIKA GUPTA BEENA KOTHARI JYOTSANA RAWAT PARVATI BHANDARI . Pauri. A. Last but not the least we would like to thank our institute G. Y. for including such type of curriculum that helped us improves our knowledge.E. We would like to thank again to Dr. D. His constructive criticism and timely review on the project has resulted in several improvements in the project.

which negatively affects device performance. the Ion/ Ioff ratio and dynamic speed (Cg VDD/Ion). or VT can be scaled down more aggressively. But this scaling [8] rule no longer worked well as due to scaling 1. Applied voltages were scaled by 1/. The reason behind this is that in previous simulations MOSFET was scaled by keeping the electric fields inside it unchanged . When the supply voltage decreases along with device dimensions. which means that the energy needed to drive the chip. and the heat produced by the chip.CHAPTER 1 INTRODUCTION 1. For this all device dimensions were scaled by 1/. on-current decreases. When gate overdrive decreases. VDD scaling has slowed down drastically.1 MOTIVATION FOR THE PRESENT RESEARCH At present there is a power crisis currently faced by conventional MOSFETs. also goes down. There are two possible solutions to this problem of needing a high gate overdrive: either VDD can stay higher than it should with constant field scaling [?].4 m node changes to the 65 nm node and supply voltage VDD decreased to about 20 The most important consequence of VDD reducing during device scaling while VT reduces significantly less. while the doping of the source and drain regions was increased by a factor of . remain constant. is that the gate overdrive. If VDD does not decrease. In order to maintain acceptable levels of gate overdrive. due to their ever increasing static power consumption. and yet device dimensions decrease. and more devices are added to a chip . then the power density remains constant.

Since logic devices operate at a given on/off-current-ratio. Second solution for power crisis is to design conventional MOSFETs with S ¡ 60mV/decade [34] at room temperature. On a more personal level. then the price to pay is an increase of one dynamic. starting from 1978 and continuing to the present day (2010). we pay a price in leakage current [9]. leading to avalanche breakdown.then the structure . And on a comfort level. the continuous down-scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) [22] enabled faster and more complex chips while at the same time the space and power-consumption [23] was kept under control. The impact ionization [32] process means . working and characteristics of MOSFET. One efficient solution for reducing leakage is to cut off the power supply to idle circuit blocks by using sleep transistors. Example of small swing device is IMOS which is a gated p-i-n junction whose gate is offset from one of the junctions such a very high electric field exists in the non-gated portion of the i-region when the device is on. Over the last decades. showing that the Tunnel FET is still an emerging device with much unexplored potential. appliances. its more convenient for battery-operated gadgets because their batteries will last longer before needing to be charged. On a practical level. Our report started with the history of transistors that use band-to-band tunneling [20] current in their on-state. its less expensive to use less electricity. tunnel MOSFET and double gate tunnel MOSFET [26] are discussed. since we would like our appliances. This too has a limit. If we want to decrease VT by shifting the curve left. This give motivation order to circuit engineers to design circuit that respond to the power crisis. and gadgets to stay the same size or shrink. INTRODUCTION 2 such that chip size is not significantly reduced. computers. it is better when laptops and hand-held gadgets have a lower power density and therefore produce less heat. static power and off current. a handful of currentlyused circuit-level solutions will be presented in this section. then it can be expected that power consumption will rise considerably. and gadgets to use less power [22] because its better for the environment. which is the main parameter to reduce the power consumption. Is to decrease sub threshold swing S = dV GS/d(log IDS) and if we want to shift VT by 60 mV. At this time we would like our computers. the limited sub threshold swing will prevent further reduction of the operation voltage. The basics of semiconductor materials . Second option for keeping a high gate overdrive: scaling down VT.Chapter 1. not get larger in order to accommodate a large heat sink required by the power-hungry chip inside.

and that could be scaled down more easily without running into problems such as punch-through. Therefore in our current project we worked on previously designed dual gate tunnel Fet and then optimized its parameters for better performance .3 RECENT RESEARCH RELEVANT TO THE PROBLEM Quinn et al. 1. seemingly unaware of all the previously mentioned work. and suggested the usefulness of this device for spectroscopy.In 2000. Further researched examples are shown MEM and NEM switches. at Brown University were the first to propose the gated p-i-n structure of a Tunnel FET [32] in 1978. and noted the saturation behaviour in the ID-VG characteristics. at the University of the German Federal Armed Forces in Munich showed experimental results from a reverse-biased vertical silicon tunneling transistor [32]. with a highly-doped boron delta-layer [17] to create an abrupt tunnel junction. In order to create the energy bands necessary for tunneling. then Tunnel Fet and finally double gate Tunnel Fet. though the experimental results which were presented showed a device that was forward-biased. Reddick and Amaratunga at Cambridge. They were motivated by the desire for devices that would be faster than conventional MOSFETs.2 NATURE OF THE PROBLEM Numerical simulations of DG Tunnel FETs [10] such as the ones presented in this thesis allow the investigation of the device physics. INTRODUCTION 3 that the IMOS can have a very small sub threshold swing and high on-current. 1. In 1997. The researchers claimed that the one-dimensionality of the CNTs led to extremely different band bending conditions . band-to-band tunneling was demonstrated in carbon nanotube (CNT) FETs [14] by Appenzelleret al. a back gate and a top gate were used. Hansch et al. as tunneling devices are.Chapter 1. They are sometimes erroneously given credit for being the first to make silicon Tunnel FETs [7]. published measured characteristics of silicon Surface Tunnel Transistors [24]. Koga and Toriumi at Toshiba proposed a post-CMOS three-terminal silicon tunneling device [15] with the same structure as a Tunnel FET. In 2004. In 1995. with the possibility to see inside a device through cross sections in 2D to obtain optimal DGTFET structure for low power application [30].

but does not cover the majority of the intrinsic region. Member. A subthreshold swing [16] smaller than the 60 mV/dec limit of conventional MOSFETs was reported for the first time. would be the same as for a gated p-i-n structure. at Purdue University did an atomistic study of InAs Tunnel FETs [16]. In 2010. or for nanowires [31]of less than approximately 10 nm diameter. at Notre Dame remarked once again what others before them had noticed that theoretically. in which they found that subthreshold swings of less than 60 mV/decade at room temperature could only be attained if single-gate body thicknesses were less than 4 nm. Tunnel FETs could one day be fabricated on grapheme nanoribbons [31]. which are basically unrolled single-walled carbon nanotubes [14]. depending on the device design. Kathy Boucart and Adrian Mihai Ionescu. IEEE proposed and validated a novel design for a double-gate tunnel field-effect transistor (DG Tunnel FET) [5]. Verhulst et al. has the benefits of decreasing off-current (tunneling through the drain-side junction) and reducing speed. showing the effects of varying source and drain doping levels. with a small or no reduction in the on-current. In 2006. Zhang et al. Toh at the National University of Singapore published a study of double-gate Tunnel FET silicon body thickness optimization. gate dielectric thickness. and the band-to-band tunneling behaviour. so that the gate covers the source-side junction where tunneling takes place. and a minimum point slope of 11 mV/dec. There were also some fabricated Tunnel FET results in 2009. In 2007. and device length. in which he showed an optimal device thickness for maximum on-current.19 mV/dec. Sandow et al. but the general equations they put forth. Showing an ON-current as high as 0. for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. INTRODUCTION 4 than those in 3D semiconductors. The structure they studied was a gated p-n diode.23 mA for a gate voltage of 1. Looking at more exotic material systems. from Forschungszentrum Jlich published experimental data for p-type Tunnel FETs on SOI [9] [21]. In the same year.8 V. Luisier et al. at IMEC showed by simulation that shortening Tunnel FET gate length [29]. an improved average sub-threshold swing of 57 mV/dec.Chapter 1. . it is indeed possible for Tunnel FETs to have a sub-threshold swing lower than 60mV/dec [33]. and double-gate body thicknesses [1] were less than 7 nm. an OFF-current of less than 1 fA (neglecting gate leakage). The simulated transfer characteristics presented in represent the extremely optimistic upper bounds of possible device performance and reach a simulated subthreshold swing of 0.

2. INTRODUCTION 5 1.4 RESEARCH PROBLEM STATEMENT The work accomplished in this dissertation has been carried out in terms of the following intermediate stages as follows: 1. Simulation of Dual Gate TFET device structure.Chapter 1. Optimization of device parameters to improve sub-threshold swing and ON-current. .

Semiconductors are the most intriguing type of material and have lead the way for the many of the advancements of technology in society. These electrons are called valance electrons and when perfect pure Silicon crystal structure occurs these electrons are shared between atoms next to each other producing a bonded diamond structure. By being a Group IV element when isolated it has 4 electrons in its outer most shell [11].CHAPTER 2 DEVICE DESCRIPTION 2.1 SEMICONDUCTOR PHYSICS When discussing basic electrical properties. To understand what happens when temperature increases or impurities are added knowledge of band theory is required [11]. This bonded pure intrinsic Silicon is an ideal structure at zero Kelvin with no impurities or crystal defects.2 ENERGY BAND THEORY Energy band theory is an important concept in explaining how electrons react to different conditions within a crystal structure.1.1 SILICON CRYSTAL STRUCTURE The Periodic Table shows that Silicon (Si) is a Group IV element. 2. 2. The most basic intrinsic semiconductor is silicon and it will be used to demonstrate basic semiconductor physics and operation [2]. materials can be broken into three basic categories: insulator.1. The spread of energies of electrons can . conductor and semiconductor.

2]. Different elements have different value bandgaps and these different bandgaps greatly affect these elements electrical properties. which is called the bandgap [Ref. Fig. In an intrinsic semiconductor EF is usually placed in the center of the bandgap. The Fermi level (EF) is also used in the band diagram and it denotes the average energy level for electrons. These energy bands consist of a lower band of energy states called the valence band. For a material to conduct electricity it must have electrons in the conduction band or holes in the valance band.fig2. DEVICE DESCRIPTION 7 Fig.2: A basic energy diagram at 0K . 2.Chapter 2.2]. Electrons naturally gravitate towards lower energy levels and when an element is at zero Kelvin the valance band is completely full of electrons and the conduction band is completely void of electronics [2].1: A simple diagram of an isolated si atom and si crystal structure be described by a set of allowed states that are called energy bands [Ref.fig2. 2. Electrons must either exist in the Conduction Band or the Valence Band. Elements with larger bandgaps are insulators. with no bandgaps or negative band gaps are conductors and semiconductors fall in between the two . an upper band of energy states called the conduction band and the energy gap between these states.

During a covalent bond two atoms supply electrons to fill each others valance band.1. Since Si is a Group IV.Chapter 2. These electrons are free to move and allow electricity to conduct through the material.3 ELECTRONS AND HOLES When an electron is excited and moves from the valance band to the conduction band the absences of the electron in the bond is called a hole. When the electron moves to fill the hole it leaves a hole behind.4 DOPING The electrical properties of pure Si can be greatly changed by introducing small amounts of impurities. at room temperature have a limited population of free electrons that can be artificially increased or decreased to change the materials ability to conduct electricity. 2. like silicon. Thermal generation is the lattice vibrations that apply enough energy for electrons to jump the bandgap and become free in the conduction band [11]. it forms strong covalent bonds with the other Si atoms in the diamond lattice.3: A basic energy diagram at room temperature 2. Fig. These electrons and holes provide a method of current flow through a semiconductor. When an electric field is applied to a semiconductor the electrons will move towards the negative side of the field and the holes will move towards the positive side [11].At room temperature the free electrons in the conduction band at equilibrium are caused by thermal generation. and has 4 valance electrons. DEVICE DESCRIPTION 8 Electrons in the conduction band are called free electrons. This . This gives the appearance of a hole moving in the opposite direction of the electron. This apparent movement is called hole flow. 2. Semiconductors. When a hole is created a free electron will move and fill it.1.

It takes very little energy to free the extra electron and it is usually freed by the thermal energy of atomic vibrations at room temperature. The MOSFET has two terminals. DEVICE DESCRIPTION 9 forms a strong bond because both atoms treat the shared electrons as there own . These regions are either p. Boron only has three electrons in its valance shell when it bonds with four Si atoms in the lattice one of the covalent bonds will be missing an electron which will be a hole.Chapter 2. Since the B atom creates this hole that will accept an electron therefore it is called an acceptor. which are connected to highly doped regions which are separated by a region called the channel.4: crystal lattice structure doped with a Boron impurity Intrinsic Silicon can also be doped with a Group V element such as Arsenic (As). but they must both be of the same type. The structure of a MOSFET is shown in Figure 3. is added as a dopant to a pure Si lattice it will change the electrical properties of the semiconductor. Since As donates an electron to the conduction band it is called a donor.5. called source and drain.2 MOSFET AND ITS CHARACTERISTICS A MOSFET is based on the modulation of charge concentration caused by a MOS capacitance.Since As has five valance band electrons when it bonds with four Si atoms in the lattice structure there is one extra electron which is not used in the covalent bonds. 2. If a Group III atom. This extra electron continues to orbit the As within the Si lattice structure. The highly doped regions are denoted . This action is repeated until a free hole is created. This type of doping produces an n-type material. such as Boron (B). This doping produces a p-type extrinsic semiconductor [11]. 2. Nearby electrons can tunnel into this hole and this will make a hole away from the original B impurity.or ntype. Fig.

The operation of both types of MOSFETs is similar and is used depending on the applications. Since the enhancement MOSFET is common. DEVICE DESCRIPTION 10 by a ’+’ following the type of doping as shown in the Figure5 and are separated by a doped region of opposite type. The third electrode in the MOSFET. However. it creates a channel at the surface of the p. 2. Fig. The MOSFET can be of two types. The MOSFET can be of n-channel or p-channel depending on the doping material in the source and drain of the MOSFET.1 OPERATING MODES In the case of n-channel MOSFET.Chapter 2. When a negative voltage is applied between gate and source. Depletion MOSFET and Enhancement MOSFET. called the gate. when there is no voltage applied to the gate there is no channel formation between source and drain and hence there is no current flow between them. In the case of depletion type of MOSFET the channel is lightly doped with the same material as that of source and drain to reduce the threshold voltage. known as the body or substrate.2. when a positive gate-source voltage is applied. the channel disappears and no current can flow between the source and the drain. under the oxide. holes for p-channel) that flow through the channel.region which is negatively charged. is located above the body and insulated from all of the other regions by an oxide (usually an oxide of Si) [2]. the drain is where the charge carriers leave the channel. This region is not so highly doped.5: Structure of a MOSFET The source is so named because it is the origin of the charge carriers (electrons for n-channel. The different modes of operation of an enhancement type MOSFET are discussed below. 2. the operation discussed here are based on enhancement MOSFET only. similarly. .

DEVICE DESCRIPTION 11 If the MOSFET is a p-channel or p-MOSFET.region.6. sometimes called subthreshold leakage is very critical in low power digital circuit].Chapter 2. depending upon the voltages at the terminals. 2 Triode or linear region ( When V GS > V th and V DS < V GSV T H ) In the linear region where the gate to source voltage VGS is greater than the threshold voltage Vth the transistor is turned on. the Boltzmann distribution of electron energies allows some energetic electrons at the source to enter the channel and flow to the drain creating a diffusion current. The three regions of operation are cutoff. the subthreshold current or weak inversion region is an efficient region of operation in some analogue circuits. This condition is depicted in Figure 3. When a negative gate-source voltage is applied. the weakinversion current. However. it creates a channel which is positively charged at the surface of the nregion. Fig. and a channel has been created which allows current to flow between the drain and source. However. linear and saturation which are explained below [2] 1 Cut-off or subthreshold mode (WhenV GS < V th ) where Vth is the threshold voltage of the device and VGS is the gate to source voltage)Under these operating conditions the transistor is turned off. then the source and drain are ’P+’ regions and the body is an n. 2. The MOSFET operates like a resistor. and there is minimal conduction between the drain and source. This subthreshold current is an exponential function of the gate to source voltage. just below the oxide. The current between the drain and source should ideally be zero when the transistor is being used as a turned-off switch. The operation of a MOSFET can be divided into three different regions.6: crossection of MOSFET operating in linear region . controlled by the gate voltage relative to both the source and drain voltages.

Channel length modulation leads to an increase of current in the channel with drain bias and hence a lower output resistance for the MOSFET .Chapter 2. a channel has been created. In this region the drain current is now relatively independent of the drain voltage and the current is controlled by only the gate to source voltage. Since the drain voltage is higher than the gate voltage. which allows current to flow between the drain and source. DEVICE DESCRIPTION 12 The drain current is given by the relation Id = µn CoxW V ds2 ((V gs − V th)V ds − ) L 2 Where n is the charge-carrier mobility. a portion of the channel is turned off. Saturation (WhenV GS < V DS and V DS < V GS − V T H ) In this case when the drain voltage is increased. above Equation can be multiplied by (1 + VDS) to take account of the channel length modulation effect.7: crossection of MOSFET operating in saturation The equation for the current in this region is given by Id = µn CoxW (V gs − V th)2 2L For larger drain biases. The onset of this region is also known as pinch-off. 2. This operating condition is shown in Figure 3. the length of the inverted drain region decreases with increase in drain bias leading to channel length modulation which is discussed later in this chapter. where is the channel length modulation parameter.7 Fig. W is the gate width. L is the gate length and Cox is the gate oxide capacitance per unit area. .

CMOS benefits from the geometric scaling of dimensions that comes with every new technology node associated with semiconductor processing. The designer can make optimizations at all levels of the design space. DEVICE DESCRIPTION 13 2. CMOS has become the predominant technology in digital integrated circuits and still maintains this position. telecommunications and signal processing equipment. Complimentary Metal Oxide Semiconductors (CMOS) circuits were invented in 1963 by Frank Wanlass at Fairchild Semiconductor as a lowpower alternative to Transistor Transistor Logic (TTL). low-power dissipation and larger integration densities. Much work has been concentrated on architecture. algorithm.Chapter 2. CMOS uses a combination of p-type and n-type MOSFETs on the same substrate to implement logic gates and other digital circuits found in computers. After around twenty-five years. CMOS found applications in the watch industry and in other fields where battery standby capability was more important than speed. which have a cumulative effect on the overall system power reduction. The first CMOS integrated circuits were made by Radio Corporation of America (RCA) in 1968 by a group led by Albert Medwin . Besides all these advantages.8: Structure of a CMOS . has made it the mainstay of the microelectronics world. compared to bipolar junction transistors. The main advantages of CMOS over TTL are its energy efficiency. Figure 3. 2. smaller area occupation. comparable operating speed and manufacturing costs . Fig. and system-level power minimization.8 shows the structure of a CMOS [23]. The technology for IC manufacturing is the only level that the designer has limited control to meet the constraints.3 CMOS A balance of low power and high throughput are the main goals which the microelectronics industry must address in satisfying the demand for more advanced applications in the consumer market sector for portable equipment in the modern world.

started to investigate the TFET in 2000 and J.9: (a) Active power consumption has been increasing with shrinking technology nodes (b)Standby leakage power also increasing with shrinking technology nodes. it also drives faster circuits. Fig. Appenzeller et al. Eisele et al.10 shows that Vdd scaling has however remained stagnant at 1V for several technology generations now. There is also the issue of increased leakage power and its impact on the battery life of electronic equipment [4].4 BAND-TO-BAND TUNNELING TRANSISTOR Although the principle of band-to-band tunneling [8] was already discovered in 1957 by L. found in 2004 that the TFET might provide a means to overcome the 60 mV/dec switching . The active and standby power is seen to increase steadily with scaling transistor dimensions. This changed rapidly after W. Figure 3. the interest in the first results on TFETs was limited. 2. Hansch and I. Figure 3. As the number of transistors per unit area increases the rising power density leads to severe packaging/thermal management concerns.9(b) illustrate the increase in active power consumption and standby leakage (subthreshold leakage) power consumption for various CMOS technology nodes . The increase in circuit density and functionality yields higher computing power at the cost of increased power consumption per chip.1 SCALING AND POWER DENSITY Generations of CMOS technologies have thrived from scaling transistor dimensions. While scaling primarily drives cheaper and denser integrated circuits because of the reduced area.Chapter 2. As shown by the equations embedded in the figures both active and standby power scale with the operation voltage (Vdd) and can therefore be reduced by scaling Vdd. 2.9(a) and 3. Esaki and the first gated p-i-n structure was proposed in 1978 .3. DEVICE DESCRIPTION 14 2.

The Fermi-distributions in source and drain are plotted in gray 2. power consumption . source and drain are of opposite doping types. performance comparison to CMOS. The bandgap blocks any current flow between source and drain. electron and hole currents are blocked by the built-in potential barriers. threshold voltage . if a negative gate-bias is applied. The device structure and band profile in equilibrium are drawn in Figure 2.1 PRINCILPLE OF OPERATION The device structure of the TFET resembles that of the MOSFET with one exception. source and drain are doped with the same type of dopant. gate overlap . the built-in potentials of the p-i and n-i junctions result in a staircase-like band-profile. While Appenzellers results were obtained with carbon-nanotube FETs [14]. Among those were the impact of the channel dimensionality .10. In equilibrium. For negative VDS. temperature dependence. in the TFET. strain and general modeling. phonon scattering [18]. heterostructure TFETs. Now.Chapter 2. While in the MOSFET. This operating mode is the p-channel on-state of the TFET because holes accumulate in the channel. Following these initial results. If a small VDS is applied to the equilibrium state [12].10: Left: Structure of a n-i-p Tunnel FET with external voltage sources. charge carriers can tunnel through the bandgap at the source/channel junction as soon as the valence band in the channel is lifted above the conduction band in the source. The n-channel on-state can be created by applying a positive VGS . 2. the adoption of the operating principle to silicon FETs seems to be more attractive because the mature silicon technology Fig. Right: Band profile of the Tunnel FET in the off-state without applied VDS. This is the off-state of the TFET. several groups started to study the theoretical aspects of TFET operation. the bands in the channel move up.4. DEVICE DESCRIPTION 15 limit of the classical MOSFET.

the bands in the channel move down and tunneling occurs at the channel-drain junction as soon as the conduction band in the channel is pushed below the valence band in the drain [6]. and the electron charge. BTBT occurs in two different transistor geometries. Indeed.Chapter 2. Consequently. a device with S below the aforementioned conventional limit is desirable for continued voltage scaling. a popular p-i-n geometry (hereafter called the TFET). The subthreshold swing (S) of a conventional MOSFET. as well as in carbon nanotube (CNT) based transistors . T. based on the thermionic emission of carriers over a channel barrier. phonon scattering has a less dramatic effect on TFETs.5 ADVANTAGES OF PIN TFET OVER MOSFET With the continual miniaturization of the MOSFET transistors. and thereby reducing power dissipation in circuits. and q are the Boltzmann constant. this has been experimentally demonstrated in CNTs and more recently with a silicon based BTBT FET . 2. and useful device properties are preserved under practical biasing conditions . the physical operational principles of conventional MOSFETs. numerous breakthroughs in device and material design have sustained an exponential increase in system performance. has a fundamental limit of ()2. and the conventional MOSFET . In this case.3BkTq where kB. In the case of CNT-MOSFETs it has been established that BTBT is dominated by phonon assisted inelastic tunneling that severely deteriorates the device characteristics . temperature. the requirement of achieving a large on-state current (ION). power dissipation in integrated circuits has become a major roadblock to performance scaling [19] . Nevertheless. Therefore. It has been predicted through detailed device simulations that BTBT FETs could produce subthreshold swings below the thermal limit in conventional semiconductor materials such as silicon . On the other hand. For more than 30 years. DEVICE DESCRIPTION 16 and negative VDS. while maintaining a small off-state leakage (IOFF). which determines the ability to turn off the transistor with the gate gate (VGS). has hindered the scaling of the power supply voltage (VDD) in recent years . The recent introduction of high-k gate oxides into semiconductor technology has also allowed much needed reduction in gate leakage and improved the scalability of future devices. have imposed fundamental limits on voltage scaling and the reduction of energy dissipation. The important task of a comprehensive comparison of device performance between the . respectively (S = 60mV/decade at room temperature) [4]. Field-effect transistors based on the band-to-band tunneling (BTBT) [20] phenomenon are being actively investigated due to their potential for low standby leakage .

Furthermore. Therefore. Surface Tunnel Transistors (STTs) or Tunneling FETs. Since a reverse bias is needed across the p-i-n structure in order to create tunneling. Tunnel FETs are interesting as lowpower devices because of their quantum tunneling barrier. DEVICE DESCRIPTION 17 p-i-n TFET and the conventional n-i-n MOSFET geometries. 2. In order to be consistent with MOSFET technology. Here. and high performance transistors that operate near the ballistic limit have already been demonstrated .1 STRUCTURE Tunnel FETs are gated p-i-n diodes [19].6 DEVICE DESCRIPTION Tunnel FETs. CNTs [14] allow one-dimensional carrier transport without depletion capacitance effects. or less commonly. the presence of the barrier keeps the off-current extremely low.6. the diode is reverse biased. Here we use similar device metrics to compare the performance between TFETs and MOSFETs using a uniform simulation environment for both the devices. When the devices are off. They also have a direct energy bandgap and small carrier effective masses that are favorable for BTBT devices . also referred to as TFETs. They offer the potential for a very low offcurrent and a small subthreshold swing [16]. the carriers must tunnel through the barrier in order for current to flow from source to drain. To switch the device on.Chapter 2. the n-region of a Tunnel FET is referred to as its drain. and the p+ region as its source for an ntype device. the names of the device terminals are chosen such that voltages are applied in a similar way for Tunnel FET operation. such as the effect of phonon scattering on device performance. are promising devices to complement or even replace conventional MOSFETs for low-power applications. many realistic aspects. we use CNTs as the model channel material due to many benefits of that system. and benchmarked against experiments. several orders of magnitude lower than the off-current of a conventional MOSFET. 2. gated p-n diodes. Previous work has also compared CNT transistor performance to that of silicon transistors and to that based on silicon nanowires . have been comprehensively explored in the case of CNT based MOSFETs as well as TFETs . a detailed simulation framework has been developed for modeling carrier transport through CNT transistors . . When the devices are turned on. and a voltage is applied to the gate. and since an NMOS operates when positive voltages are applied to the drain and gate.

only p-i-n diode leakage current flows between the source and drain.6. When a Tunnel FET is designed with symmetry between the n. the source would be doped n+ and the drain would be doped p+. and this current can be extremely low (less than a fA/m). Fig. The third incorporates a gate dielectric with two components: a 1 nm interfacial layer of oxynitride ( = 5.6.gate dielectrics 2. (b) DG. which could be HfO2 or ZrO2.5 eV.5.and p-sides .2 DEVICE PARAMETERS The double-gate n-type Tunnel FETs investigated here have been simulated with Silvaco Atlas. All Tunnel FETs simulated here use a midgap (metal) gate work function of 4. and 5x1018 atoms/cm3 respectively. but no voltage applied to the gate. Fig. 2. The first uses 3 nm of SiO2 as a gate dielectric ( = 3. In all simulations.5. SiO2 and high.Chapter 2. with a p+ source and an n+ drain.3 WORKING When a Tunnel FET is OFF. version 5. and the p-type source. Three different gate stacks were studied.2(a) shows the energy bands horizontally across the body of a Tunnel FET in the off-state [10].7) and 2 nm of a high-k dielectric ( = 25).5 nm).C. and n-type drain were doped at 1x1020. 2. intrinsic region. The second employs 3 nm of a high-k dielectric [6] ( = 25).1 shows the basic device structure for a typical p-i-n Tunnel FET.24. junctions were quasi-perfectly abrupt (junction width 0. The gate dielectric covers the drain. DEVICE DESCRIPTION 18 Fig. The structure shown is an n-type device.9).11: n-FETs. intrinsic region. (a) Single-gate. and source in all simulations. with a reverse bias applied across the p-i-n junction. 1x1017. The silicon body thickness is 10 nm.11. corresponding to a more realistic fabrication process. In a p-type Tunnel FET.

and (c) the on-state with a positive bias on the gate leading to nFET-type behavior. (b) the on-state with a negative bias on the gate leading to pFET-type behaviour.4 BAND TO BAND TUNNELING TRANSMISSION An expression for the band-to-band tunneling [20] current in Tunnel FETs can be found by using the WKB approximation and taking the tunnel barrier as a triangularly [28] shaped potential barrier as shown in Fig. the band-to-band tunneling transmission is given by . Fig.3 With the WKB approximation. as in Fig. and tunneling takes place between the valence band of the p+-region and the conduction band of the intrinsic region [10].6. DEVICE DESCRIPTION 19 (similar doping levels. and a negative voltage applied to the gate [10]. whereby the transfer characteristics resemble those of a pFET when a negative voltage is applied to the gate.2(c). 2. the energy bands in the intrinsic region are pushed down. on the other hand. 5.12: : Energy band diagrams taken horizontally across the body of a Tunnel FET in (a) the off-state where the only current comes from p-i-n leakage. and those of an nFET when a positive voltage is applied to the gate. the device exhibits ambipolar behavior. similar gate alignment.5. Fig. When a positive voltage is applied to the gate. 2.2(b)shows the energy bands with a reverse bias applied across the device.). and the energy barrier is now small enough for bandto-band tunneling to take place between the valence band of the intrinsic region and the conduction band of the n+-region. etc. The energy bands in the intrinsic region under the gate are lifted.5.Chapter 2. The energy barrier width for band-to-band tunneling is the single most important factor that determines the amount of drain current through a Tunnel FET.

where the electrons must tunnel through the widest distance at the base of the triangle.1) where k(x) is the quantum wave vector of the electron inside the barrier.3. Fig. the wave vector is 2m∗ (P E − E) (2.5) . where Eg is the band gap of the semiconductor material at the tunnel junction.Chapter 2.13: : Band-to-band tunneling can be calculated by approximating the energy barrier width by a triangular potential energy barrier. DEVICE DESCRIPTION 20 −x2 Tt ≈ exp −x1 |k(x)| dx (2. k(x) = Plugging this into Eq.1 gives 2m∗ Eg ( − qF x) h∗ 2 (2.5. then the E term goes away. and PE can be replaced by the equation for the triangle: Eg/2-qFx.4) The next step is to carry out the integration √ 3 4 2m∗ 3 ( − qF x) 2 ) Tt ≈ exp( 3qǫh 2 (2. and E is the energy of the incoming electron. When the triangular barrier is drawn at the coordinates shown in Fig.2) h2 Here. with the k(x) = electron at the energy of the widest part of the triangle (at E=0). PE is the potential energy. Inside a triangular barrier.3) −x2 Tt ≈ exp(−2 −x1 2m∗ Eg ( − qF x) dx) h2 2 (2. and F is the electric field. Then. 2.

we must also cancel out an electron charge. The effective mass m* must then change to mrx*. It has several different names. There are four important conditions in order for band-to-band tunneling to take place: available states to tunnel from. and the new term has the units eV/m. This equation can be improved slightly by making it more specific to tunneling transistors. available states to tunnel to. and ox and tox are the . or the length over which an electric charge has an influence before being screened out by the opposite charges around it .7) is the energy range over which tunneling can take place. natural length. and Eg in the numerator of Eq.6 is a general expression for band-to-band tunneling transmission. including screening length. and refers to the spatial extent of the electric field. (Eg/2 qFx) = 0.7. Since electric field is measured in V/m. and Debye length. where Ep is the phonon energy. The parameter deserves a bit more explanation.8) where Si and tSi are the dielectric permittivity and thickness of the silicon (or whatever semiconductor material is used to make the device).6) Eq. DEVICE DESCRIPTION 21 Looking back at the triangular barrier.5. and that at x = -x1. an energy barrier that is sufficiently narrow for tunneling to take place. the dimensions of the shaded triangular barrier [27] are a height of + Eg. and depends upon gate geometry. Eg is the band gap at the tunnel junction.Chapter 2. is a screening length. so we can replace the electric field F by y/x = ( + Eg)/. band-to-band tunneling current is overestimated for indirect materials. and conservation of momentum . The magnitude of the electric field corresponds to the slope of the energy bands. The expression for a double-gate device is λ= ǫsi tsi tox 2ǫox (2. crystal phonons [18] are necessary in order to conserve momentum. If these changes are not made to Eq. which gives IBT B √ 3 4λ 2m∗ Eg 2 ) ∝ Tt ≈ exp(− 3h(∆φ + Eg) (2. and m* is the tunneling mass.7 is replaced by Eg-Ep. In order for band-to-band tunneling to take place in materials with an indirect band gap such as silicon.4. so √ 3 4 2m∗ Eg 2 ) Tt ≈ exp(− 3qhF (2. and a width of . we know that at x = x2. Now referring to Fig. which is the reduced effective mass in the tunneling direction. (Eg/2 qFx) = Eg. It can be expressed in terms of the dielectric constants and thicknesses of the gate dielectric and semiconductor body of a device.

the factor of (1/2)0.5 SUB-THRESHOLD SWING IN TUNNEL FETS The dependence of swing on gate voltage up to the threshold voltage (taken at IDS = 10-7 A/m) is shown in Fig.Chapter 2. and this time the high-energy tail is crossed out since those energy levels cant exist inside the band gap of the channel. DEVICE DESCRIPTION 22 dielectric permittivity and thickness of the gate dielectric. 2. demonstrating two important things. First.5.4 shows how the band-to-band tunneling behavior [7] of the Tunnel FET acts as a band pass filter that cuts off the low-energy and high-energy tails of the Fermi distribution of the n+-type source. in which only the electrons in the source within the energy range are available for tunneling. the expression becomes more complicated . the subthreshold swing of Tunnel FETs is not constant.5. The result is the version of the distribution shown at the far right. and the low-energy tail of the distribution is crossed out because no carriers can exist at energies inside the band gap. Then on the channel side.14: Energy band cross section of a Tunnel FET showing the triangular barrier approximation within the bands. but rather is a function of gate voltage. The Fermi-Dirac distribution and Fermi level for the source are first drawn at the left within the source. Fig. And second.5 must be removed from the expression. the screening length . . These equations for were created to describe conventional MOSFET behavior.6. it is possible for Tunnel FETs to have a subthreshold swing less than the 60 mV/decade MOSFET limit at room temperature. but have also been used for Tunnel FETs. Fig. at low gate voltages. and for a wrap-around gate. we can start with the expression given by Sze for the tunneling . In order to derive an expression for the subthreshold swing of a band-to-band tunneling device. and the filtering behavior of the device in the on-state 2.5. the source Fermi-Dirac distribution is shown again. For a single-gate device.

though in order to truly utilize the average slope as shown in Fig. 5.5. the result is: S = ln[ F +b 1 dV ef f /dV GS + dF/dV GS]−1 V ef f F2 (2. up to threshold. it should be noted that in sharp contrast with a conventional MOSFET. often defined using the constant current technique.12) Several conclusions can be drawn from this equation. the gate work function would need to be adjusted in order for the turn-on point to fall right at VGS =0V . This means that the subthreshold region does not appear as a straight line when IDS-VGS is plotted on a log-lin scale.7.7.10) Veff is the bias at the tunnel junction and F is the electric field at the tunnel junction.Chapter 2. DEVICE DESCRIPTION 23 current through a reverse-biased p-n junction: I = aV ef f F exp( where Aq 3 a= and √ 3 4 m∗ Eg 2 b= 3qh (2. the subthreshold swing is a function of VGS. These are illustrated in Fig. Average swing is taken from the point where the device starts to turn on. it is useful to define two different types of swing. Point swing is the smallest value of the subthreshold swing anywhere on the IDS-VGS curve.7 shows a comparison of the IDSVGS curves for a typical conventional MOSFET. and increases as VGS increases. and the swing does not have one unique value [24].11) 2m∗ Eg −b ) F (2.6. Average swing is the more useful value for circuit designers.5. Due to the changing values of swing along the IDS-VGS curve. typically found right as the device leaves the offstate and tunneling current starts to flow. as already illustrated in Fig 5. and for a typical Tunnel FET. When the subthreshold swing is calculated as S = dVGS/d(log IDS). point swing (Spt) and average swing (Savg).9) 4π 2 h2 (2. Fig. Swing is smallest at the lowest VGS. First.

2. 2. taken at the steepest point of the IDSVGS curve.Chapter 2. taken as the average from turn-on to threshold.16: comparison of IDS-VGS for a conventional MOSFET and a Tunnel FET Fig. . 2.17: Visual definitions of point swing.15: Dependence of the Tunnel FET subthreshold slope on gate voltage for different dielectric constants Fig. DEVICE DESCRIPTION 24 Fig. and average swing.

coming from band-to-band tunneling. which degrades proportionally to the increase in temperature.Chapter 2. as shown in Fig. temperature in Kelvin. As temperature increases. caused by the generation of carriers in a reverse-biased junction. Inset: Subthreshold swing at specific VGS values. The inset of Fig. Ioff increases.3 mV/K for Tunnel FETs with a gate dielectric constant of 21. as can be seen in Eq.5.18: Simulated IDS-VGS characteristics for various temperatures for a doublegate Tunnel FET with dielectric = 21. but beyond the leakage level. This is to be expected with the constant current method of VT extraction. unlike that of a MOSFET. VDS = 1 V.2-0. vs. taken from turn-on . since with a higher dielectric constant. Fig. DEVICE DESCRIPTION 25 2.6.8. changes only slightly.6 TUNNEL FET TEMPERATURE CHARACTERIS The temperature dependence [4] of silicon Tunnel FETs with an SiO2 gate dielectric has been reported in and. the average subthreshold swing of Tunnel FETs will significantly degrade with increasing temperature. The swing is only slightly affected by changes in temperature. VT falls on a steeper part [13] of the IDS-VGS curve. Although subthreshold swing doesnt degrade with increased temperature. when taken at a fixed value of VGS. The use of a high-k dielectric rather than SiO2 leads to a decrease in the threshold voltage shift caused by temperature. we find that VT/T is 0. 5. 2. but Ion changes very little. Simulations of Tunnel FETs with a high-k dielectric show the same general trends: the off-current. while the on-current. Due to rising offcurrent. They would be more interested in average swing. While VT/ T is in the range of 1-2 mV/K for Si/SiO2 Tunnel FETs and MOSFETs. 5.8 shows that the subthreshold swing of the Tunnel FET for fixed values of VGS is nearly constant as temperature increases. increases with temperature. it must be kept in mind that circuit designers dont care about swing at a fixed value of gate voltage. the current characteristics remain nearly unchanged.

5. the steepest part of the curve is lost as temperature goes up.8. and so Savg will be significantly degraded. Since an increase in temperature has a strong effect on Ioff.Chapter 2. as seen in Fig. . DEVICE DESCRIPTION 26 up to threshold.

1 SILVACOS ATLAS DEVICE SIMULATOR ATLAS is a physically-based two and three dimensional device simulator [1]. ATLAS has the ability to run in several different modes that are with Deckbuild including Interactive Mode.CHAPTER 3 DEVICE SIMULATION 3.1.1.Output file: This file is the solution file. 3. 3. No Windows Batch Mode and inside Deckbuild.1 ATLAS INPUTS AND OUTPUTS ATLAS produces three types of output files: 1. Majority of the work in this thesis uses Deckbuild to create the device to run in ATLAS so that will be the main focus of explanation. It predicts the electrical behaviour of specified semiconductor structures and provides insight into the internal physical mechanisms associated with device operation. 2. 3. Batch Mode. which stores 2D and 3D data relating to the values of solution variables within the device at a given bias point [1]. Inside Deckbuild is the . The primary method of interfacing with the ATLAS simulator is using Silvacos Deckbuild operating environment.2 MODES OF OPERATION All simulations in this thesis were run using Deckbuild to provide the device structure information to the device simulator ATLAS [1].Run-time output file: This file gives progress and error and warning messages as the simulation proceeds.Log file: This file stores all terminal voltages and current from the device analysis.

GROUPS Structure Specification Material Model Specification Numerical Method Selection Solution Specification Result Analysis STATEMENTS Mesh. When programming in Deckbuild the is used to indicate that the line is only a programmers note and not part of the program [1].1. the mesh must be divided into regions. Contacts. Load. Models. Each time the designer wants to run ATLAS inside Deckbuild the first programming line should be: go atlas This input will start ATLAS simulator and allow it to input the rest of the conditions stated in the code in Deckbuild. The statements in each group in most cases must be run in order.3 ORDER OF COMMANDS The order in which commands are entered into Deckbuild are very important to ensure that ATLAS runs the program correctly.2 shows the groups and the order in which they should be inputted into Deckbuild [1]. DEVICE SIMULATION 28 recommended method by Silvaco and will be the only way ATLAS is run during this thesis. a two or three dimensional grid. called the mesh. Fig. Silvaco breaks the commands into five groups and each group will have several statements in that group. Structure Specification Structures of devices to be simulated are entered in plain text into the Deckbuild input deck. 3.4. The key parameters in the structure command group include the following. Electrode. To properly build a device in Deckbuild a designer must define several key parameters to get an accurate result. In this thesis all the device designs will be using a two dimensional grid. Interface Method Log. Solve.Chapter 3. electrode locations and materials must be defined. Region. Doping Materials. doping levels and dopants must be defined. ATLAS needs to have the commands in the proper order or it will give an error message. The mesh is the two or three dimensional grid used as the frame work to build your device. . Save Extract. Tonyplot This thesis will use ATLAS five command groups to describe how to use ATLAS to build and simulate a DGTFET.

The next step to defining the mesh is to specify the actual grid make up. The mesh will be less dense for a large number and denser for a smaller number.4 shows also the ATLAS regions for a DGTFET. DEVICE SIMULATION 29 The mesh statement will define the boundaries of the device you are building and the resolution of detail. ATLAS allows the user to define up to 200 different regions for one device. . 4. they will next have to define the regions of the device.mult =< value > This command will tell ATLAS the scaling factor of the mesh.Chapter 3. Regions can be defined using cylindrical coordinates but this type of region definition is not used in this research so it will not be addressed.3 shows an example of a mesh with a space. If the designer overlaps any of the two regions ATLAS will assign the material type to the last region that was defined. The electrodes can be specified as a certain material or you can leave them undefined and ATLAS will use an ideal conductor. ATLAS will automatically adjust the grids to represent the desired resolution the user has entered. Fig. 4. For ATLAS to find the electrical properties of the structure the designer must define the location of the electrodes. Mesh statements are entered in as vertical and horizontal lines in microns and as distance from the center line.4 which shows the ATLAS mesh and the mesh statements of a DGTFET. The first mesh command must be the mesh space multiplier Command. meshspace. ATLAS requires a minimum of one electrode and has a maximum limit of 50 electrodes for one device. Fig.mult value of 5 compared to a mesh with a value of 1. The value for this is normally set to equal 1. The regions will be used to assign materials and properties to the device. The regions must be defined along the mesh lines and the statements will be similar to those used for the mesh states. The user can use a higher resolution over areas of the device that the user wants more detail. This can be seen in Fig. The entire two dimensional mesh area must be defined into regions or ATLAS will not run successfully. The designer will list the material type when defining a region but to define the material properties of the material type the design must wait until second command group. After the designer has defined the device mesh. The designer must specify the electrode name and where it is located. Notice the tighter grid along the junction in the middle of the device. ATLAS divides the grid using a triangle format. Typically a high grid resolution is used at junctions and material boundaries.4.

Chapter 3.3: ATLAS Mesh and Region Boundaries for a DGTFET .1: ATLAS Inputs and Outputs Fig. DEVICE SIMULATION 30 Fig. 3. 3. 3.2: Comparison of mesh grids when using a multiplier of 5 and 1 Fig.

doping. ATLAS also has the ability to float contacts. An example of this would be: contact name=drain current This would make the contact named drain a current controlled contact. 3. In the default condition an electrode in contact is assumed to be ohmic.8eV.4: ATLAS Doping Profile of DGTFET Material Models Specification Once the designer has defined the structure and the geometry of the device being designed they can now change the default material properties and choose which models ATLAS will use to solve the devices electrical characteristics. An example of this would be: contact name=gate workfunction=4. The designer can also use the contact command to change an electrode from being voltage controlled and make it current controlled. ATLAS has the ability to distribute the dopants in a uniform or Gaussian profile. is one of the most important actions a designer does to affect the electrical properties of the structure they are designing. If the designer wants the electrode to be treated like a Sckottky contact the design must use the workfunction. notice how the impurity concentrations change in the junction region Fig. Fig. and make an open circuit contact.5 shows the doping concentration of a DGTFET.8 This command would treat the contact as Sckottky contact and set the contact named gate to 4. It also allows the designer to specify the distribution of the doping material. The first of all properties investigated will be the contact command. The uniform doping profile has an easy set of commands to dope the material exactly how the design wishes it. . Silvaco allow the designer to specify the type of dopant and the concentration. This command is used to tell ATLAS how to treat the electrode. 4. DEVICE SIMULATION 31 The next action. short two contacts together.Chapter 3.

6 shows an example of some of the mobility models available. 3. compounds and alloys with their properties already defined. Silvaco allows the designer to edit these allows or create completely new materials. Some of the properties defined are bandgaps. Fig. The designer should look and see what type of method the model they are using. impact. mobility.Chapter 3. . and material. mobility and absorption coefficients.5: Some of the mobility models available in ATLAS Numerical Method Selection ATLAS allows several different methods for calculating the solution for semiconductor device problems. The next step in the ATLAS design process is to designate material properties for the regions that are being used.12 mun=1100 This command would set the bandgap and low field electron mobility for all the silicon in the device. These models would change the parameters of the device using the following command statements: models. ATLAS has over seventy models that a designer can choose to use to improve the accuracy of the structure they are trying to simulate. The next statement to investigate is the models statement. Using the wrong method can lead to nonconvergence or incorrect results. ATLAS has an extensive library of different elements. 4. Fig. For each model type there are various types of solution techniques such as Newton and Gummel [1]. DEVICE SIMULATION 32 Since none of these features were used in this research these are not discussed in detail. An example of a way to use the material statement to improve the simulation is as follows: Material Material=Silicon EG300=1.

R. The log files allow you to view the results of ATLASs electrical analysis in a graph format.1 name=anode This will solve the circuit parameters by holding cathode voltage at 0 and sweeping the anode voltage from -5 to 5 with 0. Results Analysis The primary method when working with ATLAS to view the results of a simulation is using Tonyplot. The currently used nonlocal model works by calculating the tunnelling probability from the energy-band diagrams across the device. and it is informative to look at vertical cross sections of the energy bands of the Tunnel FET. small signal and transient solutions. The simulations use a very fine mesh across the region where the tunneling takes place. The structure files allow you to view the mesh diagram. are determined. which uses a nonlocal Hurkx band-to-band tunneling model [1]. Obtaining a solution is similar to setting up a test device. DEVICE SIMULATION 33 Solution Specifications ATLAS will calculate AC. . version 5. DC.16. The designer can also solve a sweeping bias using the following commands: solve vcathode=0 solve vanode=-5 vfinal=5 vstep=0. The results can be saved to a log file by using the following command: log outfile=simplesidiode-iv. and other parameters. It can also produce cylindrical graphs. An example of solving a DC solution is given below: solve vcathode=1. doping concentrations. All simulations were done in Silvacos ATLAS. Tonyplot is viewing program for ATLAS that allows the designer to view the structure and log files that are created by ATLAS.0 This will solves a single bias point with 1 volt on the cathode.1 voltage steps. from which energy band profiles and the energies for which band-to-band tunneling is permitted. Once the command has been made the user will typically save the results using a log or save command.log This will save a log output file of the results from the voltage sweep in them. in order to understand the functioning of the device. as well as contour plots in two dimensions.Chapter 3. current densities. Tonyplot [1] has the ability to do cutlines to look at a specific slice of the device and see what is electrical occurring at the slice point or plane. All simulations carried out in Silvacos ATLAS are 2-D.3. It can show both log and linear scaling. If no solve voltage is designated Silvaco will put a default of 0.

as we saw in. that.6: DGTFET Transfer Characteristics for various Gate Dielectric Fig.Chapter 3. 3. . the ON-current does not increase merely proportionally to the increase in the gate capacitance.2 Comparison between MOSFET and DGTFET Transfer Characteristics It can be observed from the following fig. and the current increases exponentially with a reduction in this barrier width. For Tunnel FETs. The ON-current of a Tunnel FET depends on the width of the energy barrier between the intrinsic and p+ regions. 3. DEVICE SIMULATION 34 3.7: Characteristics of a simplified single-gate NMOSFET for various gate dielectrics. as it would for a MOSFET. the improved coupling between the gate and the tunneling barrier has an exponential effect rather than a linear one. Fig. A simplified MOSFET 2-D structure has been designed for numerical simulation in order to show the difference between the two.

all with a physical thickness of 3 nm.3 DGTFET PARAMETERS OPTIMIZATION Before investigating the unique properties of Tunnel FETs or looking in detail at their behaviour. .2 show that the optimized value for dielectric constant of gate material can be chosen as 29. The off-current is less than 1fA for all materials. 5.Silicon Body Thickness.1 and 6. Si3N4 and two high-k dielectrics with dielectric constants of 21 and 29 are compared with SiO2.3. Here. In this chapter.1) IBT B ∝ Tt ≈ exp(− 3h(∆φ + Eg) where λ= ǫtsi tox 2ǫox (3. As shown in Fig. The off-current is less than 1 fA for all materials. trans-conductance (gm) also increases as gate dielectric constant increases. Tunnel FET optimization is explored.Gate Work Function. DEVICE SIMULATION 35 3.2) These two figures Fig.2. In addition to improved Ion. The above statements are in full agreement to the equation of band-to-band tunnelling current.1 DIELECTRIC CONSTANT OF GATE DIELECTRIC An improved on-current and decreased sub-threshold swing can be obtained by the careful choice of a gate dielectric. tsi 3.Chapter 3. As shown in Fig. L 4. both the point and average sub-threshold swing improve as the result of the better gate coupling given by a high-k dielectric [6].Channel Length.1. and to show why each choice was made as it was. √ 3 4λ 2m∗ Eg 2 ) (3.Gate Dielectric Thickness.6. tox 3.Dielectric Constant of Gate Dielectric. ox 2.6. considering the following parameters: 1. 6. current increases as the gate dielectric constant increases. it is important to carefully choose all device parameters such that characteristics are optimized [3].

L=50 nm. tsi=10 nm) . tox=3 nm.8: DGTFET Transfer Characteristics for various Gate Dielectric Fig. 3.Chapter 3. 3. DEVICE SIMULATION 36 Fig.9: DGTFET Trans-conductance (gm) vs VGS Curve for various Dielectrics (VDS=1V.

Fig.11: DGTFET Trans-conductance (gm) vs VGS Curve for various tsi Several trends can be seen in this figure. 3. As the film gets thinner than 7 nm. First. . on-current starts to drop possibly due to the reduced cross-sectional area available for current flow.Chapter 3. 3. 6.6.3 Fig. which influences the shape of its IDS-VGS curve as shown in Fig. the off-currents are practically independent of the thickness. DEVICE SIMULATION 37 3.2 THICKNESS OF SILICON BODY Tunnel FETS are sensitive to the thickness of silicon body.3.10: DGTFET Transfer Characteristics for various tsi Fig. tsi .4 showing gm vs VGS curve shows that among all these values of silicon body thickness maximum trans-conductance is obtained for silicon body thickness equal to 15 nm and thus is the optimized value of tsi for DGTFET.

it is observed that with the reduction in . 3.12: DGTFET Transfer Characteristics for various channel lengths.13: DGTFET Trans-conductance (gm) vs VGS Curve for various L (Other parameters are same as for Fig.6. L Fig.6 shows that the trans-conductance value is maximized for channel length of 70 nm. It is shown that Tunnel FETs ON-current is immune to the effects of length scaling as shown in Fig.Chapter 3. .3.1) Thus channel length is optimized to length of 70 nm. 3.3.6.6. 3. in which all other parameters stayed constant. on the ION in a DMG-DGTFET is analyzed.5 .4 GATE WORK FUNCTION When the impact of the work function of the gate.3 CHANNEL LENGTH A detailed study of the length scaling [25] of Tunnel FETs is conducted. But Fig. the band overlap increases. DEVICE SIMULATION 38 3. Fig.

14: DGTFET Transfer Characteristics for various gate work function Fig. 3. DEVICE SIMULATION 39 Fig. 3.Chapter 3.15: DGTFET Trans-conductance (gm) vs VGS Curve for various gate work function .

.7..5 GATE DI-ELECTRIC THICKNESS Tunnel FETs show high sensitivity to changes in gate dielectric thickness.4 nm 3. 4. DGTFET suffers from a low ION and high VT . DEVICE SIMULATION 40 and the tunneling width decreases.Chapter 3.6. Therefore. it is desirable to adjust the device parameters to obtain a maximum ION and a minimum VT . But to further decrease the effective oxide thickness alternative high dielectric constant material can be used. This limits the downscaling [22] thickness to about 3. a thin gate oxide reduces the short channel effect and improves the driving capabilities of a MOS transistor [12].3. 3.6. we choose to be the lowest possible value. So optimum value of gate dielectric thickness is chosen as 3 nm as Fig.e. Fig.4 3. However a trade off between this benefits and gate leakage is necessary.1 RESULTS STRUCTURE AND PARAMETERS The following table shows the parameters of the proposed device. in general. 3. i.10 shows maximized value of ON-current and gm for this value of thickness. The gate leakage increases exponentially as the oxide thickness is reduced.4. Since. Dual Gate TFET with their optimized values for better performance in terms of low sub-threshold swing and high ON-current.5 nm. leading to a significant increase in the tunneling probability and hence the ON-current is increased as shown in Fig. On the other hand.16: DGTFET Transfer Characteristics for various gate dielectric thickness 3.4 eV.

we see a maximum positive field throughout the depth of the device.1e-6 A/V by optimizing the already discussed parameters.4.4.13 mA for gate voltage of 1.5 ELECTRIC FIELD Looking first at the x direction component of the electric field across a device which is ON. 0. DGTFET proposed by us has better performance in terms of high ON-current. ON-current value for optimized device is 0. where the tunnelling takes place. DEVICE SIMULATION 41 PARAMETER Silicon Body Thickness Gate Dielectric Thickness Gate Dielectric Constant Drain Doping(N+) Source Doping(P+) Intrinsic Region(N) Channel Length Gate Work function 15 nm 3 nm 29 5 ∗ 1018 /cm3 1 ∗ 1020 /cm3 1 ∗ 1017 /cm3 70 nm 4. we see that the electric field is close to zero nearly everywhere. 3.8V and an improved average sub-threshold swing of 57 mV/dec.4 eV The following figure shows the optimized structure of DGTFET with ON-current as high as 0.3 TRANS-CONDUCTANCE VS VGS CURVE The following figure shows considerable improvement in terms of trans-conductance of DGTFET.09mA for the device before optimization. .2 ON-CURRENT OF DGTFET The following figure shows that the device. 3.4.4. 3. Between the intrinsic and p+ regions.Chapter 3.4 ENERGY BAND DIAGRAMS The following two figures show that the optimized DGTFET has better probability of band-to-band tunneling as compared to that before optimization due to the reduction in barrier width after optimization.25e-6 A/V which is raised to 2. 3.13mA which is higher than its value. Before optimization of parameters its value was 1.

19: Comparison of ON-Current for optimized DGTFET and DGTFET before optimization . 3.Chapter 3.17: DGTFET Trans-conductance (gm) vs VGS Curve for various gate dielectric thickness Fig. 3. DEVICE SIMULATION 42 Fig.18: Optimized structure of DGTFET Fig. 3.

3.22: Energy Band Diagram of DGTFET after Optimization . DEVICE SIMULATION 43 Fig. 3.21: Energy Band Diagram of DGTFET before Optimization Fig.20: Comparison of transconductance vs VGS curve for optimized DGTFET and DGTFET before optimization Fig.Chapter 3. 3.

3.23: Contour plot of Electric Field across DGTFET before optimization Fig.Chapter 3. DEVICE SIMULATION 44 Fig. 3.24: Contour plot of Electric Field across DGTFET after optimization .

3. flow closer to the interface before spreading back out and passing through . this holds true for the entire device depth. not just at the surface. DEVICE SIMULATION 45 3. they move parallel to the interface through most of the source. then. then move away from the dielectric interface at about the location of the tunnel junction and.4. we see that the potential drops abruptly at the tunnel junction.6 POTENTIAL In the potential contour plot for this same device in the same state . shown at the threshold voltage.25: Contour plot of potential across DGTFET before optimization Fig.4. 3. Fig.Chapter 3. attracted by the positive voltage on the gate. As the electrons move from right to left (source to drain) in the Tunnel FET.7 CURRENT FLOWLINES In the diagrams of current flow lines. it is clear that the current does not stay close to the gate dielectric as in a MOSFET.26: Contour plot of potential across DGTFET after optimization 3. and once again.

28: Contour plot of current flowlines in DGTFET after optimization . DEVICE SIMULATION 46 the drain parallel to the interface. 3. Fig. 3.27: Contour plot of current flowlines in DGTFET before optimization Fig. as they were in the source (electrical contacts are on the sides of the source and drain).Chapter 3.

CHAPTER

4

CONCLUSION

Numerical simulations have proven to be an effective means to investigate Tunnel FET behavior and the dependence of its static characteristics on changes in dimensions, doping, and other parameters. The work presented here can be useful to other researchers who will be designing and fabricating Tunnel FETs, and developing analytical and compact models for these devices.The main accomplishments of this work can be summarized as follows: The optimization of the static characteristics of Tunnel FETs by the variation of gate structure (single or double), source, drain, and intrinsic region doping levels, gate dielectric material, and silicon body thickness was carried out. The proposed device had a double gate, a high source doping and lower drain doping to suppress ambipolar behavior, a high-k dielectric of 29, silicon body thickness of 15 nm ,work function of 4.4 eV, oxide thickness of 3 nm and channel length of 70 nm. 1.Dielectric permittivity constant was investigated and by increasing its value there was a significant change in on current and trans-conductance. 2.The optimization of work function shows that the increasing value of work function decreases the threshold voltage significantly. 3.Channel length variation doesnt show much change in Ion current but by increasing channel length breakdown improves significantly. 4.Oxide thickness reduction increases leakage current so in our proposed device we had not reduce its value .

Chapter 4. CONCLUSION

48

Our proposed Tunnel FET showed improved characteristics including higher ONcurrent, .higher trans-conductance and a lower sub-threshold swing after the modifications in the design of previously proposed device. The Tunnel FETs promising behaviour makes it a strong candidate to complement or replace MOSFET technology, particularly for low power applications.

4.1

FUTURE SCOPE

Since the beginning of this thesis work in early 2005, the progress made with Tunnel FETs has come a long way. Referring back to the Recent research relevant to the problem in chapter 1, it can be seen that the majority of Tunnel FET work has been done in the past few years. but there is still much progress to be made in terms of optimization to achieve superior device characteristics. The biggest future challenge is to successfully design and fabricate fully-optimized Tunnel FETs of both n-type and p-type, that show low off-currents beyond what is possible for conventional MOSFETs, high on-currents, and average sub-threshold swings of less than 60 mV/decade at room temperature. Further work will also be necessary in order to develop accurate analytical and compact models for Tunnel FETs. Although some work has been done in these areas, the theoretical framework which will allow experimental data to be fitted has not yet been developed. More calibration and tuning of the models is required, and will become possible once more experimental data is available. Finally, one last important point is the current state of device simulators. For novel devices such as Tunnel FETs, it would be extremely advantageous to have a close interaction between the developers of the simulation tools, and the researchers producing the experimental data. Then it will become possible for the simulators to go beyond predicting trends, and give accurate estimations of on-current and other important device characteristics. I am optimistic that these devices, or some variation upon them, will bring lower power consumption and better energy-efficiency to computers, appliances, and devices everywhere.

References

[1] Atlas user’s manual. May 2006. [2] Donald A.Neame. Semiconductor Physics and Devices. Mc Graw Hill, 2003. [3] T. Baba. april 1992. [4] M. Born and K. Bhuwalka. tunnel fet: A cmos device for high temperature applications. Microelectron devices, pages 124–127, 2006. [5] Kathy Boucart and Adrian M. Ionescu. Threshold voltage in tunnel fets: physical definition, extraction, scaling and impact on ic design. IEEE, pages 299–302, 2007. [6] Kathy Boucart and Adrian Mihai Ionescu. Double-gate tunnel fet with high-k gate dielectric. IEEE Transactions on Electron Devices, 54(7), July 2010. [7] Anupama Bowonder. low power band to bandd tunnel transistors. Electrical Engg and Computer Sciences University of California, (154), Dec 2010. [8] L. T. Yang C. Shen and E. H. Toh. [9] Anurag Chaudhry and M. jagadesh Kumar, Sept. [10] E. J. Tan et al. Observation of tunneling fet operation in mosfet. IEEE Electronic Device Letters, 29(902), August 2008. [11] Ben G.Streetman. Solid State Electronic Devices. PHI Learning Pvt.Ltd, 2009.

pages 331–338. Toriumi. pages 909–917. [15] J. July 1995. Kawamoto J. [21] J. 2007. Oct 1999. Einfeld. Oct 2011. 73:190–196. Performance comparison between pin tunneling transistors and conventional mosfets. Klaassen. Hurkx and D. Amaranatunga. Thermo chemical description of dielectric breakdown in high dielectric constant material. Quinn and B. 93(19):196805–1–196805–4. Wang and C. volume 82. May 1978. May 2005. [13] G. Lundstrom. 20(10):529–531. [19] Siyuranga O. 2011. A new recombination model for device simulation including tunneling. Avouris. Band to band tunneling in carbon nano tube field effect transistors. on semiconductor devices. Letter. Mar 2003. Jan 2006. pages 44–51. Bhuwalka and I. Feb 1992. Scaling properties of tfet: Devices and circuits. 2008. Complementary tunneling transistor for low power application. Dec 2004. volume 39. Letter. Vandenberghe. [18] Siyuranga O. pages 2281–2286. Electron. Broken-gap tunnel mosfet: A constant-slope sub-60-mv/decade transistor. Nirschn and J. IEEE Electron Device Letters. M. Koswatta and Mark S. Sub band spectroscopy by surface channel tunneling. [14] y. [16] Saptarshi Das Joshua T. volume 48. Verhulst Kuohsing Kao and W. Eisele.References 50 [12] G. volume 50. IEEE trans. [24] W. Smith and Joerg Appenzeller. McPherson and A. Schulzze K. [23] M. [22] T. Direct and indirect band to band tunneling in silicon based tfets. Silicon suface tunnel transistor.F. pages 1–10.McCombe. [17] J. Influence on phonon scattering on the performance of pin band to band tunneling transistors. Three terminal silicon surface junction tunneling device for room temperature operation. performance enhancement of vertical tunnel field effect transistor with sige in the delta p+ layer. 67(4):494–496. Electron. Lundstrom. Stepper.Koga and A. pages 2121–2123. Nov 2004.Appenzeller and P. Koswatta and Mark S. G. Reddick and G. 32(10). . Shanware. Lin J. [20] Anne S. Oswald P.

September 1987. 369(1). [29] Verhulst and A.References 51 [25] G. new dual material double gate nano scale soi mosfet 2-d analytical modelling and simulation. gated pn diode: subthreshold swing less than 60mv/dec. [30] A. Hansch and I. [33] M. Jagadesh Kumar. [31] Anne S. [34] Q. . A vertical mos gated esaki tunneling transistor in silicon. Verhulst and W. Sep 2010. 2011. Vandenderghe. Zhang and W. Venkateshwar Reddy and M. Electronics Letters. Sulima. Eisele. pages 161–162. Born Zhang and T. [28] F. IEEE. Zhao. pages 212–215. April 2006. Advanced depleted substrate tranistor: Single gate. Number 9. 2005 2005. Double gate soi transistor with volume inversion. volume 4. Jagadesh kumar. [32] C. july 2000. Verhulst and W. Jun 2005. IEEE Transactions on electron devices. 45(4). IEEE trans. pages 260–268. [27] Sneh Saurabh and M. S. volume 86. double gate and tri gate. Valestra and M. [26] Brain Doyle Robert Chau and Jack Kavalieros. Shanware. Benachir. Vandenberghe. pages 410–412. on thin solid films. Silicon based tunnel fet for low power nanoelectronics. Tunnel fet:shortening of gate length. G. 2002. Fink W. Mar 2007. Analytic expression and approach for low sub threshold swing tunnel transistors. G.

1 Code for ON-current comparison between DGTFET before optimization and after optimization go atlas mesh space.mesh loc=2.mesh loc=4e-3 spac=5e-4 y.mesh loc=126e-3 spac=2e-3 x.mesh loc=1e-3 spac=5e-4 y.0 spac=2e-3 y.mesh loc=9e-3 spac=2e-3 .mesh loc=151e-3 spac=5e-4 x.mesh loc=201e-3 spac=2e-3 x.mesh loc=0e-3 spac=2e-3 x.0 x.mesh loc=252e-3 spac=2e-3 y.mesh loc=1e-3 spac=5e-4 x.mesh loc=0.mesh loc=51e-3 spac=2e-3 x.APPENDIX A DECKBUILD CODING FOR ATLAS Given in the following appendix is the coding used to do the simulations that are performed during this thesis A.mult=1.5e-3 spac=2e-3 y.mesh loc=101e-3 spac=5e-4 x.mesh loc=251e-3 spac=5e-4 x.

min=151e-3 x.min=1e-3 y.min=251e-3 x.log solve vdrain=1.max=4e-3 region num=3 oxide x.max=151e-3 y.min=17e-3 y.type conc=1e17 x.min=4e-3 y.str contact name=gate workf=4.max=17e-3 region num=4 oxide x.max=151e-3 y.min=0 x.max=17e-3 electr name=gate x.max=251e-3 y.min=101e-3 x.min=101e-3 x.min=17e-3 y.min=0 x.max=18e-3 region num=6 oxide x.min=4e-3 y.mesh loc=17e-3 spac=5e-4 y.min=0e-3 y.min=0e-3 y.0 .max=151e-3 y.type conc=1e20 x.min=1e-3 y.max=252e-3 y.max=14e3 material material=silicon EG300=1.min=251e-3 x.min=1e-3 y.max=17e-3 region num=9 oxide x.min=1e-3 x.max=18e-3 region num=8 oxide x.min=1e-3 x.max=17e-3 electr name=source x.tunnel method newton gummel solve init log outfile=simulated. DECKBUILD CODING FOR ATLAS 53 y.max=151e-3 y.type conc=5e18 x.min=151e-3 x.max=14e3 doping uniform p.max=18e-3 doping uniform n.min=101e-3 x.max=251e-3 y.min=101e-3 x.max=151e-3 y.min=17e-3 y.max=1e-3 region num=5 oxide x.max=1e-3 y.min=1e-3 y.max=14e3 doping uniform n.mesh loc=15.5 models mos print models cvt bbt.max=1e-3 y.kl boltzman print temperature=300 models bbt.min=4e-3 y.mesh loc=18e-3 spac=2e-3 region num=1 silicon x.mesh loc=14e-3 spac=5e-4 y.min=4e-3 y.max=101e-3 y.min=0 y.max=17e-3 region num=10 oxide x.max=1e-3 region num=11 oxide x.max=252e-3 y.klassen trap.min=17e-3 y.min=0e-3 y.min=101e-3 x.min=1e-3 x.min=0e-3 x.max=101e-3 y.max=14e-3 region num=2 oxide x.kl bgn.max=251e-3 y.str tonyplot DG.min=14e-3 y.min=151e-3 x.max=18e-3 electr name=drain x.min=1e-3 x.min=0 x.max=1e-3 region num=7 oxide x.max=251e-3 y.Appendix A.max=252e-3 y.5e-3 spac=2e-4 y.max=101e-3 y.12 material material=oxide permittivity=29 save outf=DG.min=1e-3 y.max=1e-3 electr name=gate x.max=252e-3 y.

max=22e-3 electr name=gate x.min=0 x.min=0e-3 x.mesh loc=20.max=252e-3 y.max=4e-3 region num=3 oxide x.min=19e-3 y.mesh loc=2.max=252e-3 y.min=1e-3 y.max=1e-3 region num=11 oxide x.min=22e-3 y.max=91e-3 y.max=161e-3 y.max=19e-3 region num=2 oxide x.max=22e-3 region num=10 oxide x.min=22e-3 y.max=23e-3 electr name=drain x.mult=1.min=1e-3 y.max=161e-3 y.min=0 x.min=0e-3 y.mesh loc=252e-3 spac=2e-3 y.max=22e-3 region num=4 oxide x.Appendix A.max=1e-3 region num=5 oxide x.min=251e-3 x.max=91e-3 y.mesh loc=22e-3 spac=5e-4 y.max=1e-3 y.min=91e-3 x.mesh loc=4e-3 spac=5e-4 y.min=1e-3 y.0 x.max=1e-3 electr name=gate x.0 spac=2e-3 y.5 vstep=0.max=251e-3 y.max=251e-3 y.max=1e-3 y.min=1e-3 x.mesh loc=0.max=23e-3 region num=8 oxide x.max=22e-3 region num=9 oxide x.max=252e-3 y.max=22e-3 electr name=source x.min=1e-3 x.min=22e-3 y.mesh loc=46e-3 spac=2e-3 x.5 vfinal=10 name=gate log off mesh space.min=22e-3 y.min=0 x.mesh loc=0e-3 spac=2e-3 x.min=91e-3 x.max=1e-3 region num=7 oxide x. DECKBUILD CODING FOR ATLAS 54 solve vgate=-0.min=1e-3 y.min=4e-3 y.min=0 y.min=1e-3 x.min=1e-3 y.mesh loc=1e-3 spac=5e-4 y.max=23e-3 region num=6 oxide x.mesh loc=126e-3 spac=2e-3 x.5e-3 spac=2e-3 y.5e-3 spac=2e-4 y.max=161e-3 y.mesh loc=251e-3 spac=5e-4 x.mesh loc=19e-3 spac=5e-4 y.min=161e-3 x.mesh loc=206e-3 spac=2e-3 x.min=0e-3 y.min=91e-3 x.mesh loc=11.min=251e-3 x.mesh loc=1e-3 spac=5e-4 x.min=0e-3 y.5e-3 spac=2e-3 y.min=91e-3 x.min=161e-3 x.max=161e-3 y.mesh loc=161e-3 spac=5e-4 x.mesh loc=91e-3 spac=5e-4 x.max=252e-3 y.max=23e-3 .max=251e-3 y.mesh loc=23e-3 spac=2e-3 region num=1 silicon x.

min=4e-3 y.type conc=5e21 x.type conc=1e17 x.mesh loc=126e-3 spac=2e-3 x.str contact name=gate workf=4.0 solve vgate=-0.0 spac=2e-3 y.max=251e-3 y.max=161e-3 y.4 models mos print models cvt bbt.mesh loc=1e-3 spac=5e-4 x.max=91e-3 y.min=1e-3 x.12 material material=oxide permittivity=29 save outf=DG.log A.type conc=5e18 x.mesh loc=201e-3 spac=2e-3 x.max=19e3 doping uniform p.mesh loc=252e-3 spac=2e-3 y.5 vstep=0.min=161e-3 x.max=19e3 material material=silicon EG300=1.tunnel method newton gummel solve init log outfile=optimized.mesh loc=151e-3 spac=5e-4 x.log optimized.mesh loc=51e-3 spac=2e-3 x.0 x.min=4e-3 y.mesh loc=101e-3 spac=5e-4 x.mult=1.kl bgn.mesh loc=0.mesh loc=251e-3 spac=5e-4 x.Appendix A.kl boltzman print temperature=300 models bbt.klassen trap.str tonyplot DG. DECKBUILD CODING FOR ATLAS 55 doping uniform n.5 vfinal=10 name=gate tonyplot -overlay simulated.mesh loc=1e-3 spac=5e-4 .min=4e-3 y.max=19e3 doping uniform n.2 Code for contour plots comparison between DGTFET before optimization and after optimization go atlas mesh space.log solve vdrain=1.min=91e-3 x.mesh loc=0e-3 spac=2e-3 x.

min=14e-3 y.min=101e-3 x.max=251e-3 y.max=18e-3 electr name=drain x.max=4e-3 region num=3 oxide x.max=18e-3 region num=6 oxide x.5e-3 spac=2e-3 y.min=1e-3 x.max=14e3 doping uniform n.min=0 y.tunnel method newton gummel solve init log outfile=simulated.min=0 x.max=252e-3 y.min=1e-3 x.min=17e-3 y.max=14e3 material material=silicon EG300=1.min=0e-3 x.min=4e-3 y.min=1e-3 x.min=1e-3 y.min=0e-3 y.max=18e-3 doping uniform n.min=251e-3 x.max=252e-3 y.max=17e-3 region num=9 oxide x.min=4e-3 y.mesh loc=18e-3 spac=2e-3 region num=1 silicon x.5e-3 spac=2e-4 y.max=17e-3 region num=4 oxide x. DECKBUILD CODING FOR ATLAS 56 y.min=1e-3 y.max=251e-3 y.max=17e-3 electr name=gate x.Appendix A.mesh loc=17e-3 spac=5e-4 y.max=1e-3 y.kl boltzman print temperature=300 models bbt.klassen trap.max=17e-3 electr name=source x.min=4e-3 y.max=1e-3 region num=5 oxide x.max=252e-3 y.type conc=1e17 x.min=101e-3 x.max=101e-3 y.max=252e-3 y.12 material material=oxide permittivity=29 contact name=gate workf=4.mesh loc=14e-3 spac=5e-4 y.mesh loc=9e-3 spac=2e-3 y.min=17e-3 y.min=0 x.max=101e-3 y.min=151e-3 x.max=251e-3 y.min=101e-3 x.min=101e-3 x.type conc=5e18 x.min=251e-3 x.max=1e-3 region num=11 oxide x.max=151e-3 y.max=18e-3 region num=8 oxide x.max=151e-3 y.min=17e-3 y.log .max=101e-3 y.max=251e-3 y.5 models mos print models cvt bbt.min=151e-3 x.max=151e-3 y.mesh loc=4e-3 spac=5e-4 y.min=101e-3 x.min=0e-3 y.max=1e-3 region num=7 oxide x.max=151e-3 y.min=1e-3 y.type conc=1e20 x.min=0e-3 y.max=1e-3 y.max=1e-3 electr name=gate x.max=17e-3 region num=10 oxide x.max=14e3 doping uniform p.min=1e-3 y.kl bgn.min=0 x.min=4e-3 y.max=151e-3 y.min=1e-3 x.max=14e-3 region num=2 oxide x.mesh loc=15.mesh loc=2.min=17e-3 y.min=1e-3 y.min=151e-3 x.

min=0 x.max=251e-3 y.max=1e-3 y.str go atlas mesh space.max=22e-3 region num=10 oxide x.mesh loc=206e-3 spac=2e-3 x.min=4e-3 y.Appendix A.max=1e-3 region num=11 oxide x.mesh loc=161e-3 spac=5e-4 x.max=91e-3 y.min=22e-3 y.min=0e-3 x.min=161e-3 x.mesh loc=126e-3 spac=2e-3 x.max=252e-3 y.min=0 y.min=1e-3 y.min=251e-3 x.max=252e-3 y.mesh loc=46e-3 spac=2e-3 x.band val.mesh loc=20.min=0 x.max=1e-3 region num=5 oxide x.mesh loc=0e-3 spac=2e-3 x.mesh loc=252e-3 spac=2e-3 y.mesh loc=91e-3 spac=5e-4 x.mesh loc=4e-3 spac=5e-4 y.5e-3 spac=2e-3 y.max=22e-3 region num=4 oxide x.max=19e-3 region num=2 oxide x.max=4e-3 region num=3 oxide x.min=0e-3 y.min=91e-3 x.max=251e-3 y.mesh loc=1e-3 spac=5e-4 x.min=1e-3 x.max=1e-3 y.min=19e-3 y.max=251e-3 y.min=91e-3 x.max=23e-3 region num=8 oxide x.max=252e-3 y.max=22e-3 region num=9 oxide x.mesh loc=0.min=1e-3 x.min=1e-3 y.mesh loc=251e-3 spac=5e-4 x.0 spac=2e-3 y.0 output qfp qfn con.mult=1.5e-3 spac=2e-3 y.str tonyplot simulated.max=161e-3 y.max=23e-3 region num=6 oxide x.mesh loc=23e-3 spac=2e-3 region num=1 silicon x.mesh loc=19e-3 spac=5e-4 y.min=0e-3 y.5e-3 spac=2e-4 y.max=23e-3 electr name=drain x.max=91e-3 y.min=161e-3 x.min=1e-3 x.min=22e-3 y.min=1e-3 y.0 x.min=0 x.0 solve vgate=0.max=161e-3 y.mesh loc=1e-3 spac=5e-4 y.max=1e-3 region num=7 oxide x.min=22e-3 y.band flowlines struct outfile=simulated.mesh loc=11.min=1e-3 y. DECKBUILD CODING FOR ATLAS 57 solve vdrain=1.max=22e-3 .mesh loc=2.mesh loc=22e-3 spac=5e-4 y.

0 solve vgate=0.log solve vdrain=1.max=161e-3 y.max=91e-3 y.min=1e-3 y.max=23e-3 doping uniform n.min=0e-3 y.min=251e-3 x.max=252e-3 y.max=19e3 doping uniform n.kl boltzman print temperature=300 models bbt.max=161e-3 y.max=1e-3 electr name=gate x.klassen trap.0 output qfp qfn con.type conc=1e17 x. DECKBUILD CODING FOR ATLAS 58 electr name=source x.min=161e-3 x.str .type conc=5e18 x.kl bgn.min=22e-3 y.4 models mos print models cvt bbt.min=91e-3 x.type conc=1e20 x.min=4e-3 y.band val.min=91e-3 x.max=161e-3 y.band flowlines struct outfile=optimized.max=19e3 material material=silicon EG300=1.max=251e-3 y.min=4e-3 y.12 material material=oxide permittivity=29 contact name=gate workf=4.Appendix A.tunnel method newton gummel solve init log outfile=optimized.max=22e-3 electr name=gate x.min=4e-3 y.min=1e-3 x.max=19e3 doping uniform p.min=91e-3 x.str tonyplot optimized.

Sign up to vote on this title
UsefulNot useful