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Digital Electronics Lab

Digital Electronics Lab

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Published by: Juno Hera Magallanes Huyan on Jul 13, 2012
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DIGITAL ELECTRONICS LABORATORY List of Experiments

:
1. Outline of digital Integrated Circuits (ICs) 2. AND, OR and NOT gate 3. NAND, NOR and EXCLUSIVE-OR gate 4. Boolean Algebra and Combinational Logic Design 5. Half Adder and Full Adder 6. Decoder/Encoder and Multiplexer/De-multiplexer 7. Parity Generator and Parity checker 8. Flip-Flip and Latch 9. Composition of register 10. Asynchronous Counter 11. Synchronous counter 12.(a) Clock Generator (b) A/D Converter

Grading:
• • • • • Attendance; 20% Lab. Work: 20% Report: 20% Mid-semester Exam: 20% Final Exam: 20%

OUTLINE OF DIGITAL INTEGRATED CIRCUITS (ICs) Aim: To study the digital ICs outline and electrical parameters.

1

Components Required: Various types of ICs say Transistor - Transistor Logic (TTL) and Complementary Metal Oxide Semiconductor (CMOS) ICs. Description: All digital ICs operate with 5V DC power supply. The number of external pin connection varies with a minimum number of pins as 14. The pins are numbered in anti clockwise starting pin 1 from the marking dot or grove. It is a dual-in-line (DIP) package. Normally all ICs operate in dual state High (1) and Low (0). TTL devices are also available in open collector form. These devices have more drive current. These devices operate in TRISTATE (High, Low and High Impedance State) Electrical Characteristics: Parameter Supply Voltage Power Dissipation Propagation Delay Fan Out Operating Frequency TTL 5VDC 10mW 10nSec 25 30MHz CMOS 3-16VDC < 1mW 100nSec 20 5MHz

Propagation Delay: This is the time taken for the signal to reach the output on applying steady state input. Fan-in: This indicates how many input terminals are connected to a gate. It is normally less than or equal to 15 for a TTL gate Fan Out: It is the output drive that a device can support with out over load.. It is less than or equal to 25 for a TTL gate. Conclusion: The digital ICs Physical & Electrical Characteristics are studied.

AND OR & NOT Gate AIM: To study the logics of AND OR and NOT gates.

2

Equipments Required: Oscilloscope, Power Supply, Single Pole Double Throw (SPDT) Switch, Diodes, NPN Transistor, Resistors, 7408 (Quad two input AND gate), 7432 (Quad two input OR gate), 7404 (Hex Inverter), LED etc. Description: A logic gate is an electronic circuit, which takes one or more inputs and produces a single output. The possible combinations of the inputs and the corresponding outputs are tabulated in the truth tables for verification. All the digital logics under discussion use Positive logic (High/ True= 1 and Low/ False= 0). The AND, OR and NOT gates are basic gates while NAND, NOR gates are universal gates. The NAND and NOR gates are sufficient enough to build all other gates. (a) AND Gate: The logic of an AND gate is that it produces a High (1) output only if all its inputs are High (1) and produces Low (0) output if any of its inputs are Low (0). The AND gate is realized by the Boolean Expression Y = A.B This can be implemented using diodes as shown in Fig.1
A Y B 1KΩ

+
Fig. 1

-5V

The AND gate is symbolic representation is given in Fig.2. The Truth Table of AND gate is verified using IC 7408 and the same is listed.
A B Fig . 2

Input
Y

B 0 0 1 1

A 0 1 0 1

Output Y 0 0 0 1

(b) OR Gate: The logic of an OR gate is that it accepts one or more inputs and produces a single output which will be High if one or more inputs are High. The gate can be realized by the Boolean expression Y=A+B This can be implemented using diodes as shown in Fig.3.
3

5 The symbolic representation of NOT is as given in Fig. The truth table of OR gate is verified using 7432 and the same is listed. The gate may be realized using a transistor +5V DC 1 kΩ A 100 kΩ Y Fig. The Boolean expression for NOT is Y=A That is if the input is A then the output is as given in Fig.5 A .6 and the truth table is verified using IC 7404. It has single input and single output. 4 .5V + Fig. 4 1 1 1 (c) NOT Gate (INVERTOR) The logic of NOT gate is that it produces the complement of the input. Input Output A Y A Y 0 1 A 1 0 Conclusion: The logics AND.A Y B 1KΩ . Input Output B A Y A Y 0 0 0 B 0 1 1 1 0 1 Fig. OR and NOT are constructed and their truth tables are verified. 3 The logic symbol is given in Fig.4.

NOR and EXCLUSIVE-OR Gate AIM: To study the logics of NAND.1. DESCRIPTION: (a) NAND gate: It provides the complementary output of AND gate. NAND gate 74LS00. and EXCLUSIVE-OR 74LS86. LED etc. 5 . SPDT Switch. The equivalent circuit of NAND is as given in Fig.NAND. oscilloscope. NOR gate 74LS02. EQUIPMENTS REQUIRED: DC Power supply. NOR and EXCLUSIVE-OR gates. That is AND gate followed by NOT gate.

2 which is OR gate followed NOT gate. A B OR + NOT Y Ξ A B Y = A+B The Boolean expression for NOR (74LS02) gate is Y = A + B and the truth table is listed.A B AND + NOT Y Ξ A B Y = A.3 (b). The output will be Low if both the inputs are LOW or HIGH.3 (a) and Fig. The exclusive-OR gate may be realized either using NAND gate or NOR gate as given in Fig. Input B A 0 0 0 1 1 0 1 1 Output Y 1 1 1 0 (b) NOR gate: It produces the complementary output of OR gate. Input B A 0 0 0 1 1 0 1 1 Output Y 1 0 0 0 (c) EXCLUSIVE-OR gate: The output of EXCLUSIVE-OR is High only if any one of the inputs is High.B The Truth table of NAND gate is verified using the IC 74LS00. 6 . The equivalent circuit is given in Fig.

INVERTER (NOT) gates. using the binary numbers “0” and “1”. NOR and EXCLUSIVE-OR are studied and their truth tables are verified. 7 . oscilloscope.3 The truth table of EXCLUSIVE-OR is verified using IC 74LS86 and the same is listed. OR. Requirements: AND. BOOLEAN ALGEBRA AND COMBINATIONAL LOGIC Aim: To understand the operations of Boolean algebra and use this to build combinational logic with minimum hardware. It is widely used while designing digital circuits. Input B A 0 0 0 1 1 0 1 1 Output Y 0 1 1 0 CONCLUSION: The logics of NAND. DC power supply. Description: BOOLEAN ALGEBRA: It is a technique of mathematical manipulation.A+B A A Ξ B Y Y B (a) A A Ξ B Y Y B (b) Fig. LED etc.

Distributive law: X x (Y + Z) = (X x Y) + (X x Z) X + (Y x Z) = (X + Y) x (X + Z) D’Morgan’s Theorem: Statement: The complement of a product is equal to sum of the complements and the complement of a sum is equal to product of the complements. Its implementation is given in Fig. 0 = 1 THEOREMS OF BOOLEAN ALGEBRA Boolean algebra deals with logical relation between Boolean variables. 2.BOOLEAN POSTULATES: If X= 0. then X =1 0x0=0 1x1=1 1+1=1 1x0=0x1=0 1+0=0+1=1 1 = 0.1 8 . A fundamental rule relating Boolean variables is called a Boolean theorem. we want to simplify the given Boolean expression and realize using logic gates. 1. Associative law: (X+Y)+Z=X+(Y+Z) (XxY)xZ=Xx(YxZ) 3. Let us consider a sum of product Y= A B C +A B C+ABC To implement this logic we need Inverters (NOT). Commutative law: X+Y=Y+X X x Y = Y x X. AND and OR gates. X xY = Y + X X + Y = X xY COMBINATIONAL LOGIC DESIGN: Here.

two AND gates and one OR gate other wise we need to use three NOT gates three AND gates and two OR gates for the same function. we need two NOT gates.2.C Y A.2(b) Y Input C 0 0 0 B 0 0 1 9 . Thus using Boolean algebra. FIG. (a). 1 Simplification of combinational logic: Consider an expression Y=AB+A B C + A B C Y = A B + A C ( B +B ) Y= A B + A C Now.2 (b) Y=AB+A B C + A B C Y= A B + A C Now connect the circuit as shown in Fig. Repeat the same for Fig.2.2 AB A A. (b). we can minimize the hardware requirements.ABC A B C ABC ABC Y Fig.B.C A B B Ξ Y C C Fig.2 (a) Fig.2(a) Y A 0 1 0 FIG. after simplifying the equation. Note down the outputs for all the possible combinations of inputs.B. This is shown in the Fig.

AND gates. DC power supply etc. HALF ADDER: 10 .0 1 1 1 1 Conclusion: 1 0 0 1 1 1 0 1 0 1 Boolean algebra is used to build combinational logic with minimum hardware to realize the same function. HALF ADDER & FULL ADDER Aim: construct and verify the operation of binary half adder and full adder Requirements: EX-OR. Let us see the details of hardware and operation in detail. OR. oscilloscope. Description: There are two types of Adders namely HALF ADDER and FULL ADDER.

the SUM follows truth table of EX-OR and Carry follows AND gate truth table. 2 11 . The same can be realized using hardware as given in Fig. A B HALF ADDER HALF ADDER S CY C Fig. Here there are three inputs (A. 1 The truth table is given and the same is verified. C) which in turn produces two outputs (S. while the Carry is provided by the AND gate as shown in Fig. The hardware requirements are two EX-OR gates. then we need to go for Full Adder. The Sum in a half adder is provided by an EX-OR gate.1 A B S C Fig.3. Hence we need one EX-OR (74LS86) and one AND gate (74LS08) to realize Half Adder. The truth table is given and the same is verified. B. if the inputs are more than two. FULL ADDER: Here. CY). two AND gates and one OR gates.Half Adder performs the addition of two binary digits.2. A block diagram sing two half adder is shown in Fig. ______________________________________________ INPUT SUM CARRY B A (S) (CY) ______________________________________________ 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 ______________________________________________ If we look the truth table closely.

A parity bit is an extra bit included with the message to make the number of 1’s either even or odd. A parity bit is used for the purpose of detecting errors during transmission of binary transmission. The circuit that generates the parity bit at the 12 . 3 Truth Table: ____________________________________________ C B A SUM (S) CARRY (CY) ____________________________________________ 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ____________________________________________ Conclusion: Half Adder and Full Adder are realized using hardware and their operations are verified. PARITY GENERATOR AND CHECKER Aim: To understand and design of Parity generator and checker used in data communication. Description: Parity generator and checker are used in data communication. An error is detected if the checked parity does not correspond with the transmitted one. The message including the parity bit is transmitted and checked at the receiving end for errors. Requirement: EX-OR. Oscilloscope. DC power supply etc.A B S CY C Fig.

• • Odd Parity Even Parity Odd Parity: Odd parity is to see that the total number of 1’s in the word is ODD including the parity bit. Even Parity: Even parity is to see that the total number of 1’s in the word is EVEN including the parity bit.transmitter is the parity generator and the circuit that checks the parity t the receiver is called the parity checker. Connect the even Parity generator and verify the truth table. Hence EX-OR gate output is suitable to generate even parity. B and C is input to the Parity generator circuit shown in Fig. A B C Fig. The EX-OR gate generates ‘1’ if the odd number of inputs is ‘1’ and a ‘0’ if even number of inputs is ‘1’. Procedure: Consider a message to be transmitted with an Even Parity.1. There are two types of parity bit. 1 P Truth Table: __________________________________ C B A Parity (P) __________________________________ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 _________________________________ 13 . Let A.

The output of the parity checker denoted by CK is 1 if there is an error.Parity Checking: Message bits along with the parity (3+1) is transmitted to the destination and applied to the parity checker for possible channel error during transmission.Connect the circuit using three Ex-OR gates. 2 Even Parity Checker Truth Table: C 0 0 0 0 0 0 B 0 0 0 0 1 1 A 0 0 1 1 0 0 P 0 1 0 1 0 1 Parity Checker (CK) 0 1 1 0 1 0 14 . Verify the truth table as listed A B CK C P Fig. Since the information was transmitted with an even parity.2. Parity checker circuit is as shown in Fig. the 4 bits must have an even parity of 1’s.An error is said to have occurred during transmission if the four bits received have an odd number of 1’s indicating that one bit has changed its value.

0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 Conclusion: An even parity generator and checker is designed and verified. A digital multiplexer is a combinational logic circuit that selects information (data ) from one of the many input lines and direct them to a single output line called a channel. Here it is necessary to use AND. There are TWO BINARY input lines to select four lines as shown in the Fig.1. Multiplexer: Multiplexing means transmitting a large number of information units over a communication channel. The 15 . DC Power supply etc. OR and NOT gates in addition to resistor and LEDs. NOT gates. OR. This gives 4 to 1 line multiplexer. Description: Multiplexer and De-multiplexers are widely used to transmit and receive digital data over a communication channel. Requirements: AND. The selection of a particular input line is controlled by a set of selection lines. MULTIPLEXER AND DE-MULTIPLEXER Aim: To understand and design digital Multiplexer and De-multiplexer. LEDs.

LEDs are useful as indicator to see which line has been selected. The selection of a specific line is controlled by the input binary value. A de-multiplexer is the reverse action of multiplexer. When the data selection is disabled (“0”) the De-multiplexer will not select any data line. The truth table may be verified. 16 . Truth Table: _________________________ Data Selection output _______________ B A __________________________ 0 0 D 0 1 D 1 0 D 1 1 D _________________________ DEMULTIPLEXER: It is a circuit that receives information on a single line (channel) and sends this information on one of the possible output lines. The conversion may enabled/disabled by setting 0 or 1.2. The circuit diagram of de-multiplexer is given in Fig. It is used to convert serial data into parallel.

ENCODER AND DECODER Aim: To understand the working principle and design encoder and decoder Requirements: AND. 17 .1. OR. which converts Decimal to Binary number. DC power supply. NOT gates. It has 2 inputs and “n” output lines. The circuit diagram of encoder is given in Fig. Here let us discuss an encoder. Here only one input should be present at a time to get the corresponding binary output. The truth table is given for verification.The truth table of de-multiplexer is given here for verification. Description: Encoders and Decoders are widely used in digital systems. ___________________________________________________ input Enable/ output Disable ________________________________________________ B A 1/0 y y y y ________________________________________________ 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 X X 0 X X X X ________________________________________________ Conclusion: Multiplexer and De-multiplexer are designed and verified using their truth table. If more than one input is present the output goes to an undefined state. Let us first briefly see about encoder. ENCODER: Encoder: It is used to encode decimal number into binary or some other code say BCD. LEDs etc. Io over come this problem it is advisable to use priority encoder.

D0 D0 D1 220 Ω D2 A D3 220 Ω B Fig. There are three output lines namely A. B. when many devices are ready to transfer data. The Boolean expressions for the outputs of priority encoder are A= D3+D 1D2 B= D2+D3 Y=D0+D1+D2+D3 18 . Here the highest number (D) gets the top priority and the lowest number D gets the least priority while encoding.2. A priority encoder circuit is sown in Fig. 1 Truth Table Input D3 0 0 0 1 D2 0 0 1 0 D1 0 1 0 0 D0 1 0 0 0 B 0 0 1 1 output A 0 1 0 1 PRIORITY ENCODER: Here many devices want to communicate simultaneously then. and Y. The highest decimal is given top priority whereas the lowest decimal (0) gets least priority. Here we need to encode decimal to binary and also need to give priority. which data is to be taken first results in priority. The bits A and B indicate the data selection and Y indicates High (1) if one or more inputs are High. Accordingly a priority encoder is described. The input data lines are D to D.

It is also known as decimal converter. Here two to four line decoders is discussed. 19 . The decoder can be extended to any number of input lines.D3 A D2 D1 B D0 220 Ω Y Fig. Other type of decoders is not covered here. Here two to four lines are shown in the Fig. 2 The truth table of the priority encoder is given in the Table Input D3 0 0 0 0 1 1 0 0 0 D2 0 0 0 1 0 1 1 0 0 D1 0 0 1 0 0 1 1 1 0 D0 0 1 0 0 0 1 1 1 1 B 0 0 0 1 1 1 1 0 0 Output A 0 0 1 0 1 1 0 1 0 Y 0 1 1 1 1 1 1 1 1 DECODER: A decoder is a combinational logic circuit that converts binary into decimal number.3 for simplicity. Depending on the inputs one of the four output lines go high at a time. The input lines are A and B.

function generator.A A D0 220 Ω B D1 B 220 Ω D2 220 Ω D3 220 Ω Fig. understand and test RS Flip Flop with and without clock Requirements: NAND gate. A flip flop has two outputs. Study of Flip Flop: A Flip Flop is a bi-stable multivibrator. DC Power supply etc. oscilloscope. 3 Truth Table: Input B 0 0 1 1 A 0 1 0 1 D3 0 0 0 1 D2 0 0 1 0 Output D1 0 1 0 0 D0 1 0 0 0 Conclusion: Design and implementation of encoder and decoder are studied RS FLIP FLOPS Aim: To design. one for normal value and the other for complement value. The input to multi vibrator can be fed in a number of ways and 20 . which is capable of storing one bit information.

(1) The flip flop is a bistable device that can store binary bit information. The inputs to the NAND gate are 1 and the output goes to Low (Q=0). then its inputs are High. Thus it remains unchanged.this fact gives rise to different types of flip flops.e.1 Truth Table --------------------------------------R S Q -------------------------------------0 0 not used 0 1 1 1 0 0 1 1 Q1 _________________________ Q 21 . the NAND gate 2 gets 0 as input and the output of this gate is 1. when the reset input is High the flip-flop is reset to Low (Q=0). the NAND gate outputs go High. The flip-flop has two inputs R and S. 4. 3.. Reset (R) and Set (S) and two outputs Q and Q . If Q =0. 2. The NAND gate output goes high when any one of its input is low. This is an undefined condition and it is not used. RS FLIP FLOP using NAND Gates: The RS FLIP FLOP circuit is as shown in Fig. Thus. This Q goes as one input to NAND gate 2 and the other input S=1. NAND 2 produces a High output as S = 1 and the other input Q = 0. However there are two characteristics shared by all flip flops. To start with when the power is on to the gate let Q = 0 and Q =1. When R=0 and S=1. i. gate 1 of NAND output is SET to High and hence Q=1. R Q S Fig. When R=1 and S=1. The output level will remain constant until input condition remains same.1. When R=0 and S=0. RS FLIP FLOP: It can be realized using either NAND or NOR gates. The gate 1 and gate 2 checks their respective second input and produces output as per the NAND gate truth table. The output of gate 2 Q is “0” ( Q =0). The gates are cross coupled which give a feedback to the input from the output. When R=1 and S=0. (2) The flip has two output levels which is complement of each other. 1.

e. S Q CLOCK Q R Fig. the flip flop operates only when both the clock input and RS flip flop inputs are present simultaneously.CLOCKED RS FLIP FLOP: In this type. The clock is NAND-ed with R and S inputs as shown. Review questions: (1) What is a Flip-Flop ? (2) How does Flip-Flop act as a memory element? 22 .2 Conclusion: The RS flip flop operation is studied in detail with and without clock. The NAND gate responds when both the inputs are High and hence any change can occur when the clock is High along with other input i. The operation of RS flip-flop with the clock level remains same as previous one. R or S.2. The circuit diagram is given in Fig.

JK Flip Flop using NAND gate is shown in Fig. Here the state of the Flip Flop is determined by the clock inputs and the previous state outputs. Procedure: The JK flip Flop has two inputs apart from the clock input. Consider a clocked RS Flip Flop circuit. 23 . The circuit is enabled when the clock is high. Requirements: NAND. DC power supply etc.JK FLIP FLOP Aim: To understand the principle of operation and test to JK Flip Flop operation. function generator. It can be realized using clocked RS Flip Flop.1. oscilloscope. AND Gates.

K=0: Here the output of AND gate 2 is Zero and the output of the AND gate 1 is “0” or “1” depending on whether Q is 0 or 1. the state of the Flip Flop is unchanged.1 (1) When J=0.and AND gate 2 is “1”. (4) When J = 1. K=1: Here the output of the AND gate 1 is 0 and AND gate 2 is “0” or “1” depending on the state of Q . Thus it is clear that the output gets complemented when both the inputs are High. If Q is “0” then S=0. then the output of AND gate 2 is goes to 1 and the Flip Flop is set to “1” since S=1 and R=0. R=0 and the output is unchanged. Hence the Flip Flop is set to “1”. K=0: The output of AND gate 1 and 2 is Zero and hence the state of the Flop Flop remains unchanged since S=0 and R=0. This condition is defined as TOGGLE CONDITION. ---------------------------------------J K Q Q ---------------------------------------0 1 0 0 0 1 Q 0 1 Q 1 0 24 . On the other hand if Q = 1. the output of AND gate 1 is “1” and hence S=0 and R=1 which resets the Flip Flop. (2) When J=1. If Q = 0 the output of AND gate 1 is “0”. (3) When J=0.gate1 K Q clock Q J gate2 Fig. K = 1: Here the AND gate outputs depend on the state of Q and Q . The measurements are tabulated. If Q=0. If Q =1 the AND gate 1 gives “1” and AND gate 2 is “0” thereby resets the Flip Flop. If Q=1.

DELAY Flip Flop Aim: To construct and study the operation of Delay (D) Flip Flop Requirements: AND. NOT.1 1 Q Q ----------------------------------------Conclusion: The JK Flip Flop is designed and tested. which has one input and the data at the input is transferred to the output after receiving the clock pulse. Description: Flip Flop output changes when both R and S inputs are dissimilar. Since the clock pulse delays the data transfer. The D Flip Flop circuit diagram is as given in Fig. This resulted in a D Flip Flop. NAND gates.1. the Flip Flop is known as D Flip Flop. DC power supply etc. 25 . Function generator. Here the output with an inverter (NOT) serves as S and R inputs.

When the clock input is low the Flip Flop remains disabled. If both the states are quasi-stable. A multivibrator has two states. the circuit is known as Monostable Multivibator or One-Shot Multivibrator. FLIPFLOPs are said to be BISTALE MULTIVIBRATOR circuits. A trigger pulse initiates the one shot action and generates a pulse of desired width. capacitances. This type of circuit is known as bi-stable multivibrator. the output at Q=1. the circuit. If both the states of a multivibrator circuit are stable. The duty cycle of a repetitive pulse waveform is defined as percent duty cycle i. the output at Q=0. the data at the D=S is transferred to the output. it becomes Astable Multivibrator. where as re-triggerable one-shot have unlimited duty cycle. DC power supply etc. Introduction: Multivibrators are used to generate pulse waveforms of different duration and repletion rate. resistors. When =D=1. Monostable multivibrators are used to set the timing of an event or control a sequence of events in a digital system. Therefore trigger pulses should not be applied so often to cause the ON time of the one shot to exceed the duty cycle specified by the manufacturers. The non-triggerable one shot needs time to recover after it returns to the stable state subsequent to a triggering event. Components Required: IC 74121. If additional triggers are applied to a one shot when it is in the quasi-stable state. The output goes directly to S input and the complement to R input. continues to remain in that state until some thing is done (triggered) from an external source. they are ineffective unless the one shot is re-triggerable. S=0 and R=1. S=1 and R=0. When =D=0. Truth Table ------------------------------------------------------Clk =D S R Q Low X X X X High 1 1 0 1 High 0 0 1 0 -----------------------------------------------------------Conclusion: The D Flip Flop is constructed and its operation is verified. Thus it is clear that the data is transferred to the output only when the goes high. When the clock is high. 1. 2.This Flip Flop is realized using RS Flip Flop with an inverter in between R and S. which is in a particular state. The duty cycle of non-triggerable one shot is limited. If one of the states is stable and the other is not stable (quasi-stable). 26 .e. It is essentially a FLIP-FLOP with only one state is stable state. MONOSTABLE MULTIVIBRATOR Aim: To study the monostable multivibrator circuit using IC74121.

7.1 (a) Fig. there must be a rising pulse-edge at Z. +5V R 11 A1 A2 Q C 10 B Q +Vcc GND Fig.4 KΩ and 40 KΩ . The timing capacitor should be connected between pins 10 and 11.2 27 . by which an internal timing resistor of 2KΩ becomes effective . The monostable multi-vibrator input output waveform is shown in Fig.1 (b) The duration of the output pulse is determined by the timing resistor and capacitor connected to it. The duration of the output pulse in seconds is given by T ON = 0. This is possible in one of the following two ways: (i) One or both of the A inputs are at logic 0 and the B input goes to logic 1. The timing resistor must be in the range of 1. The maximum allowable value of the timing capacitor is 1000 µF. The maximum allowable duty cycle for IC 74121 is 67 % with the internal timing resistor and goes up to 90 % with external timing resistor of 40KΩ.R.1 (a) and (b) respectively. or (ii) to connect an external timing resistor between pin 11 and Vcc in which case the pin 9 must be left open. there are two options: (i) to connect the pin 9 to Vcc. For connecting the timing resistors.Ton Toff Input Output Q 1 1 1 1 A1 A2 B Q T (P rio ) e d 0 X 1 0 X 0 1 0 Ton 0 0X 100 Percent DutyX Cycle =X 1 1 (Ton + Toff )1 X 1 1 ↓ 1 1 ↓ Procedure: 1 ↓ ↓ The functional diagram and functional table of 0 X ↑ X 0 ↑ most popular and commonly used one-shot TTL IC-74121 are given inFig.C Where R and C are the timing resistor and capacitor in Ohms and Farads respectively. In order to trigger the one-shot. (ii) The B input is at logic 1 and one of the A inputs goes to logic 0 while the other A input remains at logic 1 or both the A inputs go to logic 0 simultaneously.

Observe the output waveform and calculate the frequency. 330Ω R output 0. Procedure: An astable multivibrator (also known as free-running multivibrator) is an oscillator. DC power Supply etc.2 Conclusion: The monostable multivibrator is designed and tested successfully. Astable multivibrator circuit is as shown in the figure 1.01uF 0. resistors. ASTABLE MULTIVIBRATOR Aim: To study the astable multivibrator circuit using IC gates Components Required: NAND gate. Here let us design a multivbrator in detail using NAND gates.01µF. breadboard. The value of resistance R is set to 330 Ω and the capacitance C = 0.01uF c c R 330Ω Figure 1 28 .Clock Ton Q output Clock Ton Q output Fig. OPAMPs. capacitors. These circuits can be designed using discrete devices. These are required to control the timings in digital circuits. gates or monostable multivibrators. which generates square waves.

Toff Ton T Waveform Period (T) = T ON + T OFF Frequency= 1 T Now change the capacitance from 0.01 to 0.1µF measure the period and note down the time constant (τ =RC) graph. The waveform is as shown here. Ton TOFF Waveform Conclusion: It is observed that the frequency is inversely to time constant. Review Question: (1) What is the difference between a one-shot (mono-shot) and free-running multivibrator? 29 . The frequency is calculated as 1/ period.

SHIFT REGISTER Aim: to understand the functions and operations of shift register. Here. sequence generator. let us consider 4-BIT BIDIRCTIONAL UNIVERSAL SHIFT REGISTER (74LS194A). DC Power supply etc. digital delay line. Description: A flip flop is a one bit register which stores either 1 or 0. A shift register takes either serially or parallelly and sends out the data serially or parallelly. it has the advantage of less hardware and disadvantage of taking larger execution time. A shift register is an array of flip flops which shifts data in a particular sequence and direction in response to clock pulse. S1 Mode control input p 0 -p 3 D SR D SL Parallel data inputs Serial (Shift Right) data input Serial (Shift Left) data input 30 . When operated in the parallel mode. oscilloscope. ring counter etc. When it operates in a serial mode. It is used for temporary data storage. Shift registers are available in both Bipolar and MOS forms. Requirements: Shift registers. The shift register is another building block of a digital system. It has the following features: • Asnchronous Master Reset • Fully synchronous Serial or Parallel data Transfers • Shift left or Shift right operation +V c c 1 6 Q0 1 5 Q1 1 4 1 3 Q2 Q3 1 2 C P 1 1 S1 1 0 9 S0 7 L 14 A 4 S 9 1 M R 2 DSR 3 P0 4 P1 5 P2 6 P3 7 DSL 8 Pin Names: S 0 . the hardware required is more while the execution time is less. (a) 4-BIT BIDIRCTIONAL UNIVERSAL SHIFT REGISTER (74LS194A). It is a Bidirectional high speed shift register.

All data and mode control inputs are edge triggered. S 1 =LOW. 1. Master Reset: It is an asynchronous operation and all the output goes to ZERO (Q 0 -Q 3 ) when MR is LOW. When the CP goes from LOW to HIGH transfer of data from P 0 -P 3 inputs to Q 0 -Q 3 outputs is taking place. Mode Selection . SHIFT LEFT: SET MR= HIGH and S 1 =HIGH and S 0 = LOW. 3. 2.CP MR Q 0 -Q 3 Clock (active high going edge) input Master Reset (active LOW) input Parallel output. Parallel load: Set the 4 bit parallel data input at P 0 -P 3 (say 1011) then set the mode control input MR=HIGH. S 0 = S 1 = High. S 0 =HIGH and the D SL may be set to HIGH or LOW. The SERIAL DATA (shift Left) Input may be set to HIGH or LOW. For every clock pulse (Low to High) the output will change as given in the Table: Q 3 Q 2 Q1 Q 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 Set D SR =1 Set D SL =1 31 . responds only to the LOW to HIGH transition of the clock (CP). For every clock pulse (Low to High) the output will change as given in the Table: Table: Q 3 Q 2 Q1 Q 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Set D SL =0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 4. All the operation is in synchronous with the clock pulse.truth Table Operating Mode Input Output MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L L L L H H L X L X q1 q2 q3 L SHIFT LEFT H H L X H X q1 q2 q3 H H L H L X X L q0 q1 q2 SHIFT RIGHT H L H H X X H q0 q1 q2 Parallel Load H H H X X Pn P0 P1 P2 P3 Check the following operations: The Truth Table indicate the functional characteristic of the 74LS194A. SHIFT RIGHT: For this operation set MR= HIGH.

SYNCHRONOUS COUNTER Aim: To design and test the count sequences of a synchronous counter. Clock (active High Going Edge) input. Description: Synchronous Counters eliminate the cumulative propagation delays of Flip Flops. addressing. Synchronous Reset (active LOW) input. Requirements: Synchronous counter (74LS161). It has the following features:     Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge Triggered Operation. Count Enable Trickle Input. DC Power supply etc. memory. All the Flip Flops in this counter are under the control of the same clock pulse. which generally limits the performance of the ripple counters. Oscilloscope. frequency division and other applications.1 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Set D SR =0 Conclusion: The operation of 4 Bit Shift BIDIRECTIONAL UNIVERSAL Shift Register(74LS194A) operations are studied in detail. Parallel Inputs. It has an asynchronous Master Reset (clear) input that overrides and is independent of the clock and all other control inputs. Count Enable Parallel Input. Master Reset (active LOW) Input. The 74LS161 is a high speed 4-bit synchronous counter. It is edge triggered synchronously pre-settable and cascadable MSI building blocks for counting. +Vc c 1 6 T C 1 5 Q0 1 4 1 3 Q1 Q2 1 2 Q3 1 1 CT E 1 0 P E 9 PIN NAMES: 711 46 1 M R 2 C P 3 P0 4 P1 5 P2 6 P3 7 CP E 8 PE P 0 -P 3 CEP CET CP Parallel Enable (active LOW) input. Therefore the repetition rate is limited only by the propagation delay of one Flip Flop. MR SR 32 .

The counter output at Q 0 -Q 3 may take a random value of 0s and 1s. 2. PE =L.Q 0 -Q 3 TC Parallel Output. When the clock pulse goes from LOW to HIGH the contents of P 0 -P 3 is transferred to Q 0 -Q 3 respectively. It overrides all other input conditions and set the output to ZERO. Set MR = LOW (0). Note that the counter increments for every rising edge transition of the clock. Parallel Load: Set the number to be loaded on P 0 -P 3 say 1010. Note the waveforms of the output on the oscilloscope with reference to clock pulse. 3. 33 . Master Reset: Switch on the Power Supply. CEP X X H X L Action on the Rising Clock Edge Reset (Clear) Load (P n → Q n ) Count (increment) No Change No Changego Mode Select Table: SR PE CET L X X H L X H H H H H L H H X 1. It is a 4 Bit counter and hence the counting is from 0000 to 1111. The Terminal Count goes HIGH when the counter reaches its maximum Value of “1111”. CEP=H and then apply clock at CP. CET=H. Synchronous Count Incrementing: Set the control inputs MR =H. The Counter output divides the clock frequency by a factor of TWO. Set the control inputs MR =H. PE =H. Note that all count change takes place only at the Low to High transition period of the clock pulse. Now apply a clock pulse CP. Terminal Count Output.

34 .Clock input Q0 output Q1 output Q2 output Q3 output Terminal Count(TC) Conclusion: The control bits function and the counter operations are studied in detail.

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