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CMPEN 411 VLSI Di it l Circuits Digital Ci it Spring 2011 Lecture 12: Logical Effort

[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

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PMOS/NMOS Ratio Effects


5 x 10
-11

= (W/Lp)/(W/Ln)
tpLH tpHL

4.5

tp

of 2.4 (= 31 k/13 k) gives symmetrical response of 1.6 to 1 9 gi es 1 6 1.9 gives optimal performance

3.5 3

3 1 2 3 4 5

= (W/Lp)/(W/Ln)

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Example of Inverter Chain Sizing


In
Cg,1 1 CL = 8 Cg,1

Out

CL/Cg,1 has to be evenly distributed over N = 3 inverters F = CL/Cg,1 = 8/1 f =

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Heads up
This lecture
Logical Effort
- Reading assignment textbook pp251-257, and handout

Next lecture
Designing energy efficient logic
- R di assignment R b Reading i Rabaey, et al, 5.5 & 6 2 1 l 6.2.1

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History
First proposed by Ivan Sutherland and Bob Sproull in 1991
Logical Effort: Designing for Speed on the back of an Envelope, IEEE Advanced Research in VLSI, 1991 Both authors are vice president and fellow at Sun Microsystems

Gain-based synthesis based on Logical effort y g


Implemented in IBMs logic synthesis tool BooleDozer Also adopted by Magmas logic synthesis tool

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Inverter Delay
Divide capacitive load CL, into load,
Cint : intrinsic - diffusion and Miller effect (Cg) Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint) =0.69(ReqCint + ReqCext)


where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate

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Logical Effort Delay Model


Delay of logic gate has two components
d=f+p f: effort delay p: parasitic delay

Effort delay fg has two components: f=gh


g: logical effort h: electrical effort = Cout/ Cin (the ratio of output capacitance to input capacitance)

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Gate Delay Components

Cin Logic g Gate Cout

Split delay of logic gate into three components Delay = Logical Effort x Electrical Effort + Parasitic Delay Logical Effort Complexity of logic function (Invert, NAND, NOR, etc) Define inverter has logical effort = 1 Depends only on topology not transistor sizing Electrical Effort Ratio of output capacitance to input capacitance Cout/Cin Parasitic Delay Intrinsic delay Independent of transistor sizes and output load
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Computing Logical Effort


g represents the fact that for a given that, load, complex gates have to work harder than an inverter to produce a similar (speed) response
the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver the same output current) Logical effort is the ratio of the input capacitance of a gate to the input capac ta ce of an capacitance o a inverter de e g e te delivering the same output current Defined to be 1 for an inverter

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Computing Logical Effort

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Logic Gate Delay

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Logic Gate Delay

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Example
Estimate th d l E ti t the delay of an inverter driving 4 identical f i t di i id ti l inverter: (FO4)

g=

h=

p=

d=

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Example

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Path Delay of Complex Logic Gate Network


Total th d l through a combinational l i bl k T t l path delay th h bi ti l logic block tp = dj = pj + hj gj the i i th minimum d l th delay through th path d t h the th determines th t each stage i that h t should bear the same gate effort h1g1 = h2g2 = . . . = hNgN

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Application of Logical Effort


Alternative logic structures, which is the fastest? F = ABCDEFGH

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Application of Logical Effort


Alternative logic structures, which is the fastest? F = ABCDEFGH
g1=10/3 g2=1

1 6/3 2 /3 g1=6/3 g2=5/3 g1=4/3 g2=5/3 g3=4/3 g4=1

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Review: Design Technique 4


Isolating f fan-in f from fan-out using buffer insertion f ff

CL

CL

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Questions
d = gh+p How to derive the model from Elmore delay model? Why logical effort g is independent of transistor sizing? How to calculate parasitic delay p ? Why it is independent of transistor sizing? How to calculate single delay parameter: What if the ratio of p-type to n-type transistor widths changes?

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From Elmore model to Logical Effort Model R Cin Cp Cout

Elmore Delay = R(Cp+Cout) R(Cp Cout) = R*Cout + R*Cp = RCin*(Cout/Cin)+R*Cp

g
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Parasitic Delay
CgateP

Main cause is drain capacitances These scale with t Th l ith transistor width i t idth so it is independent of transistor sizes For inverter:

RonP

CdrainP

RonN

Parasitic Delay ~= 1.0


CdrainN

CgateN

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How to calculate single delay parameter:


Characterize process speed with single d l parameter: Ch t i d ith i l delay t

~= 15 ps for 0.18um

~=20 ps for 0.25 um

How to estimate it for a new process? (such as 0.13 or 0.09 um)

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Inverter Chain Delay

For each stage: Delay = Logical Effort x Electrical Effort + Parasitic Delay = 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps) = 2.0 units

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Multistage Logic Network

Path logical effort, G = gi Path electrical effort, H = Cout/Cin Parasitic d l P iti delay, P = pi Path effort, F= fi = gi hi D= D F+P

(gi = L.E. stage i) (hi = E.E. stage i) (p P.D. t ( i = P D stage i)

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Paths that Branch


Consider paths that branch: C

G H GH h1 h2 F

= = = = = = GH?
5

15

90

15

90

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Paths that Branch


No! C Consider paths that branch:

G H GH h1 h2 F

=1 = 90 / 5 = 18 = 18 = (15 +15) / 5 = 6 = 90 / 15 = 6 = g1g2h1h2 = 36 = 2GH


5

15

90

15

90

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Add Branching Effort


Branching effort:
b= Con path + Coff path Con path

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Multistage Networks
Path electrical effort: H= Cout/Cin Path logical effort: G = g1g2gN g Branching effort: B = b1b2bN Path ff t F= P th effort: F GBH Path delay D = F+P=GBH+P

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Optimal Number of Stages


Cin Coutt
Minimum delay when: stage effort = logical effort x electrical effort = 3 4-3 8 ~ 4 3.4-3.8 Fan-out-of-four (FO4) is convenient design size (~5)

FO4 delay: Delay of inverter driving four copies of itself

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Method of Logical Effort


Compute the path effort: F = G C ff GBH Find the best number of stages N ~ log4 F Compute the stage effort f = F1/N Sketch the path with this number of stages p g Work either from either end, find sizes: Cin = Cout*g/f

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Example of Inverter (Buffer) Staging


N
1 Cg,1 = 1 1 Cg,1 = 1 1 Cg,1 = 1 1 Cg,1 = 1 2.8 8 4 16 CL = 64 Cg,1 22.6 CL = 64 Cg,1 8 CL = 64 Cg,1 CL = 64 Cg,1

f 64

tp 65

18

15

2.8

15.3

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Summary

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Next Lecture and Reminders


Next lecture
Designing energy efficient logic
- Reading assignment Rabaey, et al, 5.5 & 6.2.1

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