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[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

5 x 10

-11

= (W/Lp)/(W/Ln)

tpLH tpHL

4.5

tp

of 2.4 (= 31 k/13 k) gives symmetrical response of 1.6 to 1 9 gi es 1 6 1.9 gives optimal performance

3.5 3

3 1 2 3 4 5

= (W/Lp)/(W/Ln)

In

Cg,1 1 CL = 8 Cg,1

Out

Heads up

This lecture

Logical Effort

- Reading assignment textbook pp251-257, and handout

Next lecture

Designing energy efficient logic

- R di assignment R b Reading i Rabaey, et al, 5.5 & 6 2 1 l 6.2.1

History

First proposed by Ivan Sutherland and Bob Sproull in 1991

Logical Effort: Designing for Speed on the back of an Envelope, IEEE Advanced Research in VLSI, 1991 Both authors are vice president and fellow at Sun Microsystems

Implemented in IBMs logic synthesis tool BooleDozer Also adopted by Magmas logic synthesis tool

Inverter Delay

Divide capacitive load CL, into load,

Cint : intrinsic - diffusion and Miller effect (Cg) Cext : extrinsic - wiring and fanout

where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate

Delay of logic gate has two components

d=f+p f: effort delay p: parasitic delay

g: logical effort h: electrical effort = Cout/ Cin (the ratio of output capacitance to input capacitance)

Split delay of logic gate into three components Delay = Logical Effort x Electrical Effort + Parasitic Delay Logical Effort Complexity of logic function (Invert, NAND, NOR, etc) Define inverter has logical effort = 1 Depends only on topology not transistor sizing Electrical Effort Ratio of output capacitance to input capacitance Cout/Cin Parasitic Delay Intrinsic delay Independent of transistor sizes and output load

Sp11 CMPEN 411 L12 S.8

g represents the fact that for a given that, load, complex gates have to work harder than an inverter to produce a similar (speed) response

the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver the same output current) Logical effort is the ratio of the input capacitance of a gate to the input capac ta ce of an capacitance o a inverter de e g e te delivering the same output current Defined to be 1 for an inverter

Example

Estimate th d l E ti t the delay of an inverter driving 4 identical f i t di i id ti l inverter: (FO4)

g=

h=

p=

d=

Example

Total th d l through a combinational l i bl k T t l path delay th h bi ti l logic block tp = dj = pj + hj gj the i i th minimum d l th delay through th path d t h the th determines th t each stage i that h t should bear the same gate effort h1g1 = h2g2 = . . . = hNgN

Alternative logic structures, which is the fastest? F = ABCDEFGH

Alternative logic structures, which is the fastest? F = ABCDEFGH

g1=10/3 g2=1

Isolating f fan-in f from fan-out using buffer insertion f ff

CL

CL

Questions

d = gh+p How to derive the model from Elmore delay model? Why logical effort g is independent of transistor sizing? How to calculate parasitic delay p ? Why it is independent of transistor sizing? How to calculate single delay parameter: What if the ratio of p-type to n-type transistor widths changes?

g

Sp11 CMPEN 411 L12 S.20

Parasitic Delay

CgateP

Main cause is drain capacitances These scale with t Th l ith transistor width i t idth so it is independent of transistor sizes For inverter:

RonP

CdrainP

RonN

CdrainN

CgateN

Characterize process speed with single d l parameter: Ch t i d ith i l delay t

~= 15 ps for 0.18um

For each stage: Delay = Logical Effort x Electrical Effort + Parasitic Delay = 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps) = 2.0 units

Path logical effort, G = gi Path electrical effort, H = Cout/Cin Parasitic d l P iti delay, P = pi Path effort, F= fi = gi hi D= D F+P

Consider paths that branch: C

G H GH h1 h2 F

= = = = = = GH?

5

15

90

15

90

No! C Consider paths that branch:

G H GH h1 h2 F

5

15

90

15

90

Branching effort:

b= Con path + Coff path Con path

Multistage Networks

Path electrical effort: H= Cout/Cin Path logical effort: G = g1g2gN g Branching effort: B = b1b2bN Path ff t F= P th effort: F GBH Path delay D = F+P=GBH+P

Cin Coutt

Minimum delay when: stage effort = logical effort x electrical effort = 3 4-3 8 ~ 4 3.4-3.8 Fan-out-of-four (FO4) is convenient design size (~5)

Compute the path effort: F = G C ff GBH Find the best number of stages N ~ log4 F Compute the stage effort f = F1/N Sketch the path with this number of stages p g Work either from either end, find sizes: Cin = Cout*g/f

N

1 Cg,1 = 1 1 Cg,1 = 1 1 Cg,1 = 1 1 Cg,1 = 1 2.8 8 4 16 CL = 64 Cg,1 22.6 CL = 64 Cg,1 8 CL = 64 Cg,1 CL = 64 Cg,1

f 64

tp 65

18

15

2.8

15.3

Summary

Next lecture

Designing energy efficient logic

- Reading assignment Rabaey, et al, 5.5 & 6.2.1

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