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# UNIT 1:

## MOSFET and CMOS gate characteristics

Aims and Objectives In this unit you will learn the basic characteristics of MOSFETS and how their behaviour can be modelled using simple equations. The simple model will be used to understand and evaluate the static and dynamic performance of the simplest possible CMOS logic gate the inverter. 1 Introduction In order to appreciate VLSI design at the gate level, it is important to understand the characteristics of the metal oxide semiconductor field effect transistor (MOSFET) and the way in which these characteristics affect the performance of logic gates. To do this, we will use simple models (this is not a specialised course on deep sub-micron silicon) and explore the behaviour of a logical inverter (or NOT gate) built using MOSFETs. Some of you may find this material new, but many will find some of the content is no more than revision. 2 MOSFET characteristics

2.1 MOSFET types There are two types of MOSFET the NMOSFET and the PMOSFET. The two types have similar characteristics, but the NMOSFET uses electrons (negatively charged) for conduction and the PMOSFET uses holes (positively charged) for conduction. The N and PMOSFETS are complementary to one another, and as we will see, this fact is used to advantage in VLSI design. Each FET type is further subdivided into two modes of operation depletion mode and enhancement mode. The circuit symbols that will be used in Units 1-6 of this course are shown in Fig. 1. The symbols are labelled with source (S), drain (D), gate (G) and bulk (B) (or substrate) connections.
D G S (a) D G S (c) B G S (d) B G S (b) D B D B

Figure 1. MOSFET circuit symbols and terminal names. (a) Enhancement mode NMOS. (b) Enhancement mode PMOS. (c) Depletion mode NMOS. (d) Depletion mode PMOS. We will begin our discussion by reviewing the behaviour of an enhancement mode NMOSFET. 2.2 IV characteristics of an enhancement mode NMOSFET A typical (simplified) cross-section through the physical structure that forms an NMOSFET is shown in Fig. 2.

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## n+ poly-Si oxide (SiO2 ) Al n+ drain gate Al n+ source Al p+ bulk

Figure 2. A cross-section through an NMOSFET. The FET silicon has four differently doped areas: the substrate, which is slightly p-type, the source and drain areas that are heavily doped n-type, and the bulk contact, which is heavily doped p-type. In addition, there is also a gate contact, which is traditionally made of polysilicon, but more recent processes have started to use refractory metals. A thin dielectric between the gate and the substrate that is made of silicon dioxide is vital to the device. Each terminal has a metal contact (not shown on the gate). This is often made of aluminium, but modern processes use copper. In simple terms, the gate electrode forms a capacitor that couples to the substrate material between the source and drain. A positive voltage on the gate, with respect to the bulk and the source potentials, will induce a thin layer of electrons under the gate and allow conduction between the source and drain. Since this is not a physical electronics course, we will not dwell on the details. Figure 3 shows the source-drain IV characteristic of an NMOSFET for several gate-source voltages. The circuit symbol is annotated to show the direction of the voltages and currents. The gate current is zero (no DC current in a capacitor) and the bulk terminal is omitted. It is omitted because for digital circuits the bulk is always connected to the lower supply rail that is usually 0 V.
IDS triode region line joins knee of IV curves saturation region VGS5

VGS4

Gate

VGS3

+ VGS Source

## VGS2 cut-off region VGS1 VDS

Figure 3. Typical IV characteristic of an enhancement mode NMOS device. Note that the bulk terminal is omitted. In Fig. 3 VGS1 < VGS2 << VGS5, etc. The IV characteristic has three distinct operating regions: If the gate-source voltage (VGS) is less than the so-called threshold voltage (Vt) no current will flow between the source and the drain (IDS = 0). This is the cut-off region of operation. If VGS > Vt, but the source-drain voltage (VDS) is small, the device will operate in the triode or linear region. The region lies between the IDS axis and the solid parabola. In this region the current increases in response to increasing both VGS and VDS. If VGS > Vt and VDS is large, the device will operate in the saturation region. The region lies to the right of the solid parabola. In this region, the ideal transistor has an IDS that

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only increases with increasing VGS (a slight slope is shown, to depict a more realistic characteristic in which IDS increases slightly with increased VDS). The device characteristics are loosely modelled by the following equations: 0 VGSn < Vtn cut-off "n 2 0 < VDSn < (VGSn - Vtn) linear 2( GSn ! Vtn ) DSn ! VDSn V V IDSn = 2 "n (VGSn ! Vtn )2 0 < (VGSn - Vtn) < VDSn saturation 2

The subscript n denotes that this is an NMOSFET the need for the distinction will become clear later in the unit. The IV characteristics follow a quadratic behaviour as a function of both VGSn and VDSn. As already stated, there is ideally no current dependence on VDSn in the saturation region. The saturation region is the portion of the IV characteristic where IDS is most sensitive to VGS, and is where the FET has the highest gain. The boundary (the parabola in Fig. 3) is defined by the relation VDSn = VGSn Vtn. The equations are based on a physical model, where
' Wn \$ % % L " , (! ox = ! 0 ! r , ! r = 3.9 for SiO 2 ) . " & n# The parameters are: n = voltage to current coefficient (in units of A/V2) n = electron mobility (in units of m2/Vs) ox = permittivity of gate oxide (in units of F/m2) Wn = transistor width (in units of m) Ln = gate length (in units of m) tox = thickness of gate dielectric (in units of m) Note that a subscript n has only been used where it is necessary to make a distinction between N and PMOSFETS. Parameters such as ox and tox are ideally the same for all transistors on any given chip. Because of the simple relationship with physical parameters that this model provides, we will use it to analyse some of the fundamental properties of VLSI circuits later in the Unit. (n = n ! ox t ox

2.3 IV characteristics of an enhancement mode PMOSFET Broadly speaking, the characteristics of a PMOSFET are the same as those of a NMOSFET, but because the conduction is due to holes, all current/voltage has the opposite orientation.

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VDS

VGS Gate

## VGS1 cut-off region VGS2

VGS3

VGS4

saturation region

triode region

VGS5

IDS

Figure 4. The IV characteristics of a PMOSFET. The behaviour is shown in Fig. 4, where VGS1 > VGS2 > > VGS5, etc. Another key difference to be aware of is that the threshold voltage, Vtp, is negative. When all current and voltage signs are properly taken into consideration, a PMOSFET can be described using the same equations as a NMOSFET. 2.4 Enhancement and depletion mode Depletion mode NMOS was once a vital technology (see Unit 2), but is now more or less reduced to a footnote in history so far as digital design is concerned. The key difference between a depletion mode NMOSFET and an enhancement mode NMOSFET is that a depletion mode NMOSFET has a threshold voltage that is negative. This means that a depletion mode NMOSFET will conduct even when VGSn = 0. Similarly, the threshold voltage for a depletion mode PMOSFET is positive, so that a depletion mode PMOSFET will conduct when VGSp = 0 V. 3 The CMOS inverter The Complementary Metal Oxide Semiconductor (CMOS) inverter has the circuit shown in Fig. 5. The negative power supply (VSS) is usually zero and both the source and the bulk contact to the NMOSFET are connected to it. The positive power supply (VDD) has both the source and bulk contact of the PMOSFET connected to it. The two FET drains are connected together to form the output, and the two gates are connected together to form the input. As shown Fig 5b, it is usual to omit detail such as the bulk connections from a circuit diagram, since it can be taken for granted.
VDD M2 Vin Vout M1 VSS Vin M2 Vout M1

(a) (b) Figure 5. (a) a CMOS inverter showing all the detail and (b), the same circuit with detail that is well-understood by convention removed. 3.1 The CMOS inverter transfer characteristic A transfer characteristic is a plot of the output voltage in response to the input voltage. A typical CMOS transfer characteristic is shown in Fig. 6.

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Vout VDD

## I - PMOS LIN, NMOS OFF II - PMOS LIN, NMOS SAT

III - PMOS SAT, NMOS SAT Vth IV - PMOS SAT, NMOS LIN V - PMOS OFF, NMOS LIN

VSS = 0

Vth

VDD

Vin

Figure 6. The transfer characteristic of a CMOS inverter. A similar characteristic can drawn for all CMOS gates. In region III the gate passes through the gate threshold Vth. This corresponds to VIN = VOUT and is the voltage at which the gate makes the transition from a logic-high to logic-low condition. 3.1.1 CMOS operating regions The transfer characteristic of Fig. 6 shows 5 distinct operating regions (I, II, III, IV and V). They are summarised in Table I. Table I. The five regions of operation. Region NMOS PMOS I VIN < Vtn cut-off VIN - Vtp < VOUT < VDD linear II 0 < VIN - Vtn < VOUT saturation VIN - Vtp < VOUT < VDD linear III 0 < VIN - Vtn < VOUT saturation VOUT < VIN - Vtp < VDD saturation IV 0 < VOUT < VIN - Vtn linear VOUT < VIN - Vtp < VDD saturation V 0 < VOUT < VIN - Vtn linear VIN > VDD + Vtp cut-off Figure 7 shows the IV characteristics of both the NMOS and PMOSFET in the inverter overlaid on top of one another. To allow this, the right-hand Y-axis shows the magnitude of IDSp. The voltage values have been chosen to correspond to VDD = 5 V (still quite commonplace). In all operating conditions: VGSn = VIN and VGSp = VIN - VDD Similarly: VDSn = VOUT and VDSp = VOUT - VDD If there is no external load (taking an external current at the output), then IDSn = -IDSp = IDS for all VIN. (They share the same current path). From Fig. 7 it can be seen that there is a region in the centre (III) where both transistors will be in saturation. The blue and red lines for the N and PMOSFETs overlap. In the other regions, the current can be extracted from the intercept of the blue and red curves. For example, in region II, as VIN decreases, IDSn falls, forcing the PMOSFET into linear operation.

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VIN = VGSn = VDD - VGSp Region III IDSn 5V |IDSp| Region II Region IV 4V 3V Region V 0 1V 2V 1V 2V 3V VOUT = VDSn VDSp 4V 5V VDD Region I

Figure 7. The voltages and currents of the N and PMOS devices in a CMOS inverter are overlaid. 3.1.2 Calculating voltages in the transfer characteristic of a CMOS inverter Because IDSn = -IDSp is always true when there is no external load, the following calculations can be performed.
Region I

IDS = 0 since NMOSFET is cut-off. VOUT = VDD. 0 < VIN < Vtn. At boundary between regions I and II VIN = Vtn.
Region II

" "n (VIN ! Vtn )2 = p 2( IN ! VDD ! Vtp )VOUT ! VDD )! (VOUT ! VDD )2 ( V 2 2 "p 2 2 = 2VOUT ( IN ! Vtp ! VDD )! 2VDD ( IN ! VDD ! Vtp )! VOUT + 2VOUT VDD ! VDD thus V V 2 (n 2 (VIN ! Vtn )2 = 2VOUT ( IN ! Vtp )! 2VDD 'VIN ! VDD ! Vtp \$ ! VOUT V % " (p 2 & #

We could solve this quadratic equation to find VOUT(VIN) for the inverter. However to obtain a sketch we observe that at logic threshold, on the boundary between region II and III, VOUT = (VDD - VIN) - Vtp because the PMOSFET moves from linear to saturation mode. Since VIN = Vth (see calculation for region II) we have VOUT = (VDD Vth) Vtp Vth is calculated in the next region (region III).

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Region III

"p

## VDD + Vtp + Vtn 1+ !n !p

!n !p

The simple model predicts that the transfer characteristic in region III is a vertical line (i.e. gain is infinite!). Somewhere on the vertical line the condition VIN = VOUT = Vth must be met therefore

!n !p

## Note that if Vtp = -Vtn and n = p, then Vth = VDD/2.

Region IV

"p "n 2 ( IN ! VDD ! Vtp )2 , thus 2( IN ! Vtn ) OUT ! VOUT = V V V 2 2 "p 2 ( IN ! VDD ! Vtp )2 VOUT = 2( IN ! Vtn ) OUT ! V V V "n

As for region II we could solve this quadratic equation to find VOUT(VIN) for the inverter. However to obtain a sketch we observe that at gate threshold, on the boundary between region III and IV, VOUT = VIN - Vtn because the NMOSFET moves from linear to saturation mode. Since VIN = Vth we have VOUT = Vth Vtn
Region V

IDS = 0, since PMOS is cut-off. VOUT = 0 V. VDD + Vtp < VIN < VDD. At boundary between regions IV and V, VIN = VDD + Vtp. Using the above analysis, it is therefore possible to obtain a rough sketch like Fig. 6 of the transfer characteristic by joining the points calculated at the boundaries. A more detailed (and messy) analysis can be done to obtain a general solution for regions II and IV, viz

## VOUT = VIN ! Vtp +

( V

IN

V ( % " 2 ! Vtp )! 2VDD &VIN ! DD ! Vtp # ! n ( IN ! Vtn ) in region II, and V 2 ' \$ "p

(VIN ! Vtn )2 !

"p "n

( V

DD

## + Vtp ! VIN ) in region IV.

2

Exercise 1 Derive the preceding pair of equations for regions II and IV. Exercise 2

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Ideally Vtp = -Vtn and n = p. By using these assumptions, draw an annotated sketch of the transfer characteristic for a CMOS inverter if Vtn = 0.75 V and VDD = 3.3 V. On the same axis draw a second transfer characteristic for the case where Vtp = -0.95 V and all other parameters are the same. 3.1.3 Noise Margins It is desirable that the input and output voltage ranges that define "HI" and "LO" be as wide as possible. This is to prevent incorrect logical evaluation due to system noise interfering with voltage levels. Two noise margins are defined.
Vout VOH dVout = -1 dVin

## dVout = -1 dVin VOL 0 VOL VIL VIH VOH Vin

NML

NMH

Figure 8. Calculating noise margin from an arbitrary transfer characteristic. NML (noise margin low) - the voltage range for which an input signal can be guaranteed low. NML = VIL - VOL. NMH (noise margin high) - the voltage range for which an input signal can be guaranteed high. NMH = VOH - VIH. To calculate noise margins, VIL, VIH, VOH and VOL are determined at the unity |gain| points of the transfer characteristic (Fig. 8). The full rail-to-rail output swing of the CMOS output gives excellent noise margin compared to other logic families. For CMOS: If n/p = 1 and Vtn = -Vtp = Vt, it can be shown that NML = NMH = (VDD + 2Vt)/4 Example For VDD = 3.3 V and Vt = 0.75 V, NML = NMH = (3.3+1.5)/4 = 1.2 V Modern CMOS processes operate at 2.2 V and Vt 0.5 V, so noise margins are dangerously small. 3.2 Dynamic characteristics of a CMOS inverter The switching speed of a CMOS INVERTER is determined by its drive strength and the load conditions. Current only flows in CMOS when the signal is changing (e.g. from HI to LO), because, as we have seen, the source drain current in either transistor is zero at logic-high or low. This current is required to charge/discharge capacitance (e.g. gate capacitance) in the circuit, therefore CMOS loads are modelled as a capacitor (Fig. 9).

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## VDD Vin Vout CL

V
0.9 VDD VDD - Vtn 0.1 VDD t0 t1 t2 t3

## Figure 10. Step response of a CMOS inverter.

Input transitions to logic gates clearly give rise to output transitions when the logical conditions are correct. Using an inverter as a model, the four main timing characteristics are: tf - 90% - 10% fall-time tr - 10% - 90% rise-time tpddu - propagation delay for falling (down) input and rising (up) output measured at VIN and VOUT = Vth tpdud - propagation delay for rising (up) input and falling (down) output measured at VIN and VOUT = Vth dV To switch the capacitor the load current required will be I L = C L OUT , thus the time dt dV required will be t = C L ! OUT . IL is a function of VOUT, so careful consideration of IL transistor operation is required for a complete analysis. In Fig. 10 an inverter receives a perfect step function as its input stimulus at time t0 = 0. Before t0, the PMOS device is ON and the NMOS device is OFF. Immediately after t0, VGSn = VDD and VGSp = 0 V, thus the PMOS device is OFF and the NMOS device is in saturation since VOUT > VGSn Vtn. At t = t1, VOUT = 0.9VDD, the NMOS device is still saturated. IL = IDSsat At t = t2, VOUT has fallen to VDD Vtn, and the NMOS device enters its linear region. IL = IDSlin At t = t3, VOUT = 0.1VDD. IL = IDSlin The integral that must be solved to calculate the 90 % to 10 % FALL-TIME is therefore:
& 0.9VDD dVOUT VDD 'Vtn dVOUT t f = (t 3 ' t1 ) = (t 2 ' t1 )+ (t 3 ' t 2 ) = C L \$ ( + ( I DS LIN \$VDD 'Vtn I DS SAT 0.1VDD % By substituting the IV equations for an NMOS device we obtain # ! ! "

& VDD 'Vtn \$ 0.9VDD dVDS dVDS t f = CL \$ ) + ) 2 \$VDD 'Vtn ( n ( DD ' Vtn )2 0.1VDD ( n 2( DD ' Vtn ) DS ' VDS V V V \$ 2 2 %

# ! ! ! ! "

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VDD -Vtn & 2(V - 0.1VDD ) # , 1 ) 2 1 * 'dVDS ! = C L \$ tn + 2 . n ( DD - Vtn ) 0.1/DD * VDS VDS - 2( DD - Vtn )' V V \$ . n ( DD - Vtn ) ! ( V + % V "

& 2(V - 0.1VDD ) & , VDD - Vtn 2 = C L \$ tn + \$ln* 2 . n ( DD - Vtn ) % * 0.1VDD V + \$ . n ( DD - Vtn ) % V
=

## , - (VDD - Vtn ) ) ' - ln* ' * - 1.9V + 2V DD tn ( +

& knCL \$# \$ "V n DD %

## )# # '! ! ' (" ! "

) 19VDD ! 20Vtn 2C L ( tn ! 0.1VDD ) V CL + ln' 2 " n ( DD ! Vtn ) ' V VDD " n ( DD ! Vtn ) V ( V 2(n ! 0.1) ln ( ! 20n ) 19 + and n = tn 2 1! n VDD (1 ! n )

where k n =

The ratio Vtn/VDD is a constant for any circuit, and kn is a slowly varying function of VDD that is typically in the range 3 4 and can be treated as if it was a constant. We can then draw simple conclusions: large CL = slow large = fast large VDD = fast Example VDD = 2.2 V, Vt = 0.5 V, CL = 100 fF, = 0.0007 A/V2, hence n = 0.5/2.2 = 0.23, kn = 3.35 and tf = 220 ps Exercise 3 Derive a similar expression for tr. Propagation delay in CMOS The rising and falling edges in CMOS are almost linear (often called trapezoidal) due to the constant current source-like behaviour of the MOSFETs for most of the transition from low to high or vice-versa. Therefore: tf t t pdud ! and t pddu ! r 2 2 3.4 Power consumption in CMOS Since the output voltage swings of CMOS are rail to rail, and either the NMOS or PMOS channel is shut off so that there is no supply current, there is no static power consumption in CMOS. However, there is dynamic power consumption. Dynamic current flows to charge or discharge the load capacitance CL.
voltage Vout

IL

current

time

## Figure 11. Dynamic current in CMOS.

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Figure 11 shows the typical (simplified to straight lines) output current and voltage characteristics of CMOS. Power dissipation is defined to be:
P= 1 I L (t )VOUT (t )dt , where T is the voltage waveform period (for example a clock). T! 0
dVOUT , therefore dt
T

I L = CL

P=

## dV CL T C T VOUT (t ) OUT dt = L ! VOUT (t )dVOUT T ! dt T 0 0

We now have an integral with respect to VOUT, for which we do not know VOUT(t), but we do know that it swings from VOL to VOH (rising edge) and from VOH to VOL (falling edge) within a single period, thus, by substitution,
OL \$ CL 2 C L 'OH 2 PD = VOH ! VOL % ( VOUT dVOUT ! ( VOUT dVOUT " = T & OL OH # T 1/T is the frequency (f) and for CMOS, VOL = 0 V and VOH = VDD, thus

2 PD = C LVDD f

So, for CMOS the power consumption varies as the square of the supply voltage and linearly as the capacitance. Previously we saw that increasing VDD increased the speed of a gate, so now we have an apparent conflict of requirements we can have faster gates, but at the cost of much higher power consumption. Because the power consumption increases quadratically with VDD and the speed improvement is only linear, the trend is to work at lower voltages. Reducing the capacitance reduces the power consumption and increases the speed, so the drive is towards smaller devices (shorter L and W). Example A microprocessor is built using a 0.25 m CMOS process. The system clock has a frequency of 400 MHz. A parameter extraction tool is used to estimate the capacitance of all the transistors and metal interconnects on the clock tree, which turns out to be 5 nF. For VDD = 2.2 V, P = 400M*4.84*5n = 9.7 W. These are not untypical figures for a large-ish chip today with perhaps 10 million MOSFETs. It is also worth noting that the clock tree (net) can dissipate more than 50% of the total power for a modern chip. 4 Summary In this unit we have reviewed the IV characteristics of a MOSFET and stated, without proof, some well-known equations to model these characteristics. Using these models we have analysed the static and dynamic behaviour of a CMOS inverter circuit. The above analyses demonstrate that the transfer characteristic is sensitive to n and p. Since n and p are controlled by Wn and Wp respectively, we will see in Unit 2 how these parameters can be judiciously chosen to affect the behaviour and performance of a circuit design.

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5 Problems The following problems, selected from the recommended course texts, can be used as study aids. From Smith: Chapter 2, Exercises 3, 5 From Rabaey: Chapter 3, Exercises 1, 2, 3

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