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Submitted By: Name: AMBER BHAUMIK College Roll No.:E092010 University Roll No.:90180410983 Under the Guidance of: Name: VEMU SULOCHANA VERMA Designation: PROJECT ASSOCIATE & COURSE COORDINATOR Department: ACSD


The successful completion of any task would be incomplete without accomplishing the people who made it all possible and whose guidance and encouragement secured us the success Each time I write this report, I gain a stronger appreciation for the following fact: I couldnt do it without the help of many talented and dedicated people. So I wish to express my appreciation to those whose help has been most valuable .Firstly, I would like to express my gratitude and appreciation to Ms. Vemu Sulochana Verma(Project Associate and Course Coordinator) who explained me everything about the training process at the company and made me familiar with the company staff. I am equally grateful to Mr. Amandeep Singh (Instructor) who sorted out many of my problems regarding the training and gave me proper material to work with.

Finally, I would like to say thanks to all the people of the company for their kind cooperation.

The world is shrinking. New era is going to be an era of great technology and only those Engineers who will have the ability to move along with fast paced technology are going to survive. To move along with technology an Engineer must be equipped with the practical knowledge of work. Now the quality of knowledge is more important than the quantity. So a person without practical knowledge is nil no matter how many books he has studied.

The practical training is highly conducive for the development of Solid foundation of knowledge and personality Confidence Excellence and Self-discipline

It was my pleasure that I got an opportunity to undergo my six weeks industrial training in C-DAC, MOHALI. When I joined C-DAC, I was associated with the VLSI TECHNOLOGY DEPTT for the six weeks training period.

In this report, I have tried to sum up the technical knowledge that I had gained during this precious training period.


Centre for Development of Advanced Computing (C-DAC) is the premier R&D organization of the Department of Information Technology (DIT), Ministry of Communications & Information Technology (MCIT) for carrying out R&D in IT, Electronics and associated areas. Different areas of C-DAC, had originated at different times, many of which came out as a result of identification of opportunities. The setting up of C-DAC in 1988 itself was to built Supercomputers in context of denial of import of Supercomputers by USA. Since then C-DAC has been undertaking building of multiple generations of Supercomputer starting from PARAM with 1 GF in 1988. Almost at the same time, C-DAC started building Indian Language Computing Solutions with setting up of GIST group (Graphics and Intelligence based Script Technology); National Centre for Software Technology (NCST) set up in 1985 had also initiated work in Indian Language Computing around the same period. Electronic Research and Development Centre of India (ER&DCI) with various constituents starting as adjunct entities of various State Electronic Corporations, had been brought under the hold of Department of Electronics and Telecommunications (now DIT) in around 1988. They were focusing on various aspects of applied electronics, technology and applications. With the passage of time as a result of creative echo system that got set up in C-DAC, more areas such as Health Informatics, etc., got created; while right from the beginning the focus of NCST was on Software Technologies; similarly C-DAC started its education & training activities in 1994 as a spinoff with the passage of time, it grew to a large efforts to meet the growing needs of Indian Industry for finishing schools. C-DAC has today emerged as a premier third party R&D organization in IT&E (Information Technologies and Electronics) in the country working on strengthening national technological capabilities in the context of global developments in the field and responding to change in the market need in selected foundation areas. In that process, C-DAC represents a unique facet working in close junction with DIT to realize nation's policy and pragmatic interventions and initiatives in Information Technology. As an institution for high-end Research and Development (R&D), C-DAC has been at the forefront of the Information Technology (IT) revolution, constantly building capacities in emerging/enabling technologies and innovating and leveraging its expertise, caliber, skill sets to develop and deploy IT products and solutions for different sectors of the economy, as per the mandate of its parent, the Department of Information Technology, Ministry of Communications and Information Technology, Government of India and other stakeholders including funding agencies, collaborators, users and the market-place.

The technologies dealt with within the house of C-DAC are Natural language processing (NLP), Artificial Intelligence (AI), e-Learning, Multilingual computing, Multimedia computing, Geomatics, Cyber Security, Real Time Systems, Software & Industrial automation, High Performance Computing, Data Warehousing/Data Mining, Digital/Broadband Wireless networks, Modeling and Visualization etc. The sectors addressed are Finance, Healthcare, Power, Steel, Defence, Telecom, Agriculture, Industrial Control, Broadcasting, Education and e-Governance.

Some of the major research areas are: Graphics and Intelligence based scripting Technology: GIST is one of the Dynamic Groups working in Multilingual Technologies. System Area Network: HTDG is currently working on products based on the VI Architecture specification. These include high-performance SAN interface cards and high-speed, scalable switches for these SANs. Reconfigurable Computing System: Reconfigurable Computing System Cards at C-DAC Parallel Programming Environments High Performance Communication Subsystems High Performance Storage Systems Computational Atmospheric Sciences Computational Structural Mechanics Computational Fluid Dynamics Seismic Data Processing Bioinformatics TETRA Basic Sciences Evolutionary Computing


S.NO. 1. 2.

TOPIC Introduction to VLSI, IC History, EDA Tools Basics of Digital Design Introduction to VHDL : Target device is from Xilinx &

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Spartan 3 Need, Scope, Use and History of VHDL VLSI Design(FPGA) process Design Simulation and Design Synthesis VHDL Modelling Styles Data Types in VHDL Objects in VHDL Operators in VHDL


4. 5. 6. 7. 8. 9. 10. 11.

27 35 36 48 50 51 53










Flip Flops & Latches



Flip Flops



Shift Registers



Finite State Machines Project on simulation of Traffic Light Control System using Modelsim/ISE simulator. Programming Code












VLSI is the short-form for Very-large-scale integration, a process that means to create integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI finds immediate application in DSP, Communications, Microwave and RF, MEMS, Cryptography, Consumer Electronics, Automobiles, Space Applications, Robotics, and Health industry. Nearly all modern chips employ VLSI architectures, or ULSI (ultra large scale integration). The line that demarcates VLSI from ULSI is very thin.

There is a rising demand for chip driven products in consumer electronics, medical electronics, communication, aero-space, computers etc. More and more chip designing companies have set up their units in India eying on the Indian talents; besides many of the Indian Major IT companies have forayed in Application Specific Integrated Circuit (ASIC) design in a big way. With the design & manufacturing market (both domestic & international) expanding rapidly, there is an enhanced demand of trained professionals who will boost the technical work force in the VLSI domain.

What is an FPGA?
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), FPGAs can be used to implement any logical function that an ASIC could perform. The FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that can be viewed as standard components. Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a matrix of wires and programmable switches. A user's design is implemented by specifying the simple logic function for each cell and selectively closing the switches in the interconnect matrix. The array of logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex designs are created by combining these basic blocks to create the desired circuit. Implementation includes many phases Translate : Merge multiple design files into a single netlist Map : Group Logical symbols from the netlist (Gates) into physical components (CLB s and IOBs ) Place & Route : Place components onto the chip, connect them and extracts timing data into reports Timing (Sim) : Generate a back annotated netlist for timing simulation tools Configure : Generate a bit stream for device configuration

Module -I ( 1st Week)

1.Introduction to VLSI, IC History, EDA Tools
1.1 About VLSI
VLSI is the field which involves packing more and more logic devices into smaller and smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimetres across! This has opened up a big opportunity to do things that were not possible before. VLSI circuits are everywhere ... your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you. All this involves a lot of expertise on many fronts within the same field, which we will look at in later sections.

1.2 Integrated Circuits (Chips)

Integrated circuits consist of: -- A small square or rectangular die, < 1mm thick Small die: 1.5 mm x 1.5 mm => 2.25 mm2 Large die: 15 mm x 15 mm => 225 mm2

-- Larger die sizes mean: More logic, memory Less volume Less yield

-- Dies are made from silicon (substrate) Substrate provides mechanical support and electrical common point

1.3 IC History in terms of number of Transistors

SSI Small-Scale Integration (0-102) MSI Medium-Scale Integration (102-103) LSI Large-Scale Integration (103-105) VLSI Very Large-Scale Integration (105-107) ULSI Ultra Large-Scale Integration (>=107)

1.4 Integration Level Trends

Obligatory historical Moores law plot The figure shows that every 2 years the number of components on an area of silicon(chip) doubled, which is called Moores Law. Electronic design automation (EDA)- Set of software tools used for VLSI chip design.

1.5 EDA Tool Categories:

1. Based on design methodology Full Custom Design Standard Cell Based Design FPGA Design Structured ASIC Design

2. Bases on Design Flows

2. Basics of Digital Design

2.1 From transistors to chips
Chips from the bottom up: 1) Basic building block: the transistor = on/off switch 2) Digital signals voltage levels high/low 3) Transistors are used to build logic gates 4) Logic gates make up functional and control units 5) Microprocessors contain several functional and control units This section provides an introduction into digital logic 1) Combinatorial and sequential logic 2) Boolean algebra and truth tables. 3) Basic logic circuits. 4) Decoders, multiplexers, latches, flip-flops. 5) Simple register design.

2.2 Boolean expressions

Uses Boolean algebra, a mathematical notation for expressing two-valued logic

2.3 Logic diagrams

A graphical representation of a circuit; each gate has its own symbol. Logic blocks are categorized as one of two types, depending on whether they contain memory. Blocks without memory are called combinational; the output of a combinational block depends only on the current input. In blocks with memory, the outputs can depend on both the inputs and the value stored in memory, which is called the state of the logic block.

2.4 Truth tables

A table showing all possible input value and the associated output values. Truth tables can completely describe any combinational logic function; how- ever, they grow in size quickly and may not be easy to understand. Sometimes we want to construct a logic function that will be 0 for many input combinations, and we use a shorthand of specifying only the truth table entries for the nonzero out- puts.

2.5 Six types of gates

NOT , AND , OR, XOR, NAND, NOR 2.5.1 NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output

2.5.2 AND Gate An AND gate accepts two input signals If both are 1,the output is 1;otherwise,the output is 0

2.5.3 OR Gate An OR gate accepts two input signals. If both are 0, the output is 0; otherwise,the output is 1

2.5.4 XOR Gate An XOR gate accepts two input signals If both are the same,the output is 0; otherwise,the output is 1

The difference between the XOR gate and the OR gate; they differ only in one input situation. When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0. XOR is called the exclusive OR.

2.5.5 NAND Gate The NAND gate accepts two input signals, If both are 1, the output is 0; otherwise, the output is 1

2.5.6 NOR Gate The NOR gate accepts two input signals If both are 0, the output is 1; otherwise, the output is 0

2.6 Combinational circuit

The input values explicitly determine the output. Gates are combined into circuits by using the output of one gate as the input for another.

Three inputs require eight rows to describe all possible input combinations. This same circuit using a Boolean expression is (AB + AC).

2.7 Circuit equivalence

Two circuits that produce the same output for identical input. Boolean algebra allows us to apply provable mathematical principles to help design circuits. A(B + C) = AB + BC (distributive law) so circuits must be equivalent.

2.8 Properties of Boolean Algebra

2.9 Adders At the digital logic level, addition is performed in binary Addition operations are carried out by special circuits called, appropriately, adders. The result of adding two binary digits could produce a carry value Recall that 1 + 1 = 10 in base two . 2.9.1 Half adder A circuit that computes the sum of two bits and produces the correct carry bit

Boolean expressions sum = A B carry = AB

2.9.2 Full adder A circuit that takes the carry-in value into account

2.10 Basic Laws of Boolean Algebra

Identity laws: A + 0 = A A*1=A Inverse laws: A + A = 1 A*A=0 Zero and one laws: A + 1 = 1 A*0=0 Commutative laws: A + B = B+A A*B=B*A Associative laws: A + (B + C) = (A + B) + C A * (B * C) = (A * B) * C Distributive laws : A * (B + C) = (A * B) + (A * C) A + (B * C) = (A + B) * (A + C)

2.11 Sequential circuit

The output is a function of the input values and the existing state of the circuit We describe the circuit operations using Boolean expressions Logic diagrams Truth tables

2.12 Circuits as Memory

Digital circuits can be used to store information These circuits form a sequential circuit, because the output of the circuit is also used as input to the circuit Example An S-R latch stores a single binary digit (1 or 0).There are several ways an S-R latch circuit can be designed using various kinds of gates. The design of this circuit guarantees that the two outputs X and Y are always complements of each other. The value of X at any point in time is considered to be the current state of the circuit. Therefore, if X is 1, the circuit is storing a 1; if X is 0, the circuit is storing a 0

Module -II (2nd Week)

3. Introduction to VHDL : Target device is from Xilinx & Spartan 3

Need, Scope, Use and History of VHDL Application of VHDL in Market and Industries Special Features of this Language Design Process and Steps Design Simulation and Design Synthesis Design Methodology VHDL Modelling Styles Discussion on VHDL and Other Languages Data Types, Objects & Operators in VHDL


With Select Statements When Else Statements If Statement Case Statement Loops in VHDL


Components Benefits of Structural Style Structural Style of Modelling


Up/Down Binary & BCD Counters 1D and 2D Array in VHDL Flip Flops and Latches Shift Registers


Moore's Machine Traffic Light Controller


4. Need, Scope, Use and History of VHDL

VHDL is a language for describing digital electronic systems. It arose out of the United States Governments Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US.

4.1 Need
VHDL is designed to fill a number of needs in the design process. 1) It allows description of the structure of a design, that is how it is decomposed into subdesigns, and how those sub designs are interconnected. 2) It allows the specification of the function of designs using familiar programming language forms. 3) As a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.

4.2 Scope
VHDL is suited to the specification, design and description of digital electronic hardware.

4.3 System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardwaresoftware split. Simulation at this level is usually stochastic, and is concerned with modeling performance, throughput, queuing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation.

4.4 Digital
VHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gatelevel simulation. VHDL tools usually provide an integrated design environment in this area.VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fan-out loading effects providing coding styles are adhered to and delay calculation tools are available.

4.5 Uses and Benefits

Fits effectively into structured, top down electronic design process hierarchical design database structure mixed design database, i.e., circuit schematic, IP & VHDL. VHDL programming language includes concurrent language constructs ideally suited to hardware description The use of VHDL is not restricted to electronics, though non electronic applications are unlikely. Reduces Time To Market (TTM). Enables implementation of increased complexity designs Provides higher quality designs Provides common, language-based description of digital hardware operation Guidelines on writing VHDL models for synthesis commonly exist within design group Effective design documentation : Provides a detailed specification which can be executed. Simpler maintenance than schematic-based capture methods for well commented VHDL code Enables exploration of alternative system architectures early in design cycle by describing the system in a high level

abstract HDL model (without need for detailed design to gate level) Enables early problem detection since describing functional behavior at high level of abstraction (without complex timing

problems associated with gates/transistors) Therefore, detailed gate level implementation not required before testing can begin. Technology independent hardware description : Technology selection is left until the synthesis stage

Synthesis tools automate much of the technology specific decisions (timing, area, driving strength, choice). Allows designer to concentrate on system function. New ECAD tools can provide next generation implementations of an existing VHDL design database. VHDL models can be easily reused & adapted. Many VHDL models of commercial ICs are now available to designers [as Intellectually Property (IP) blocks] and may be easily

adapted to suit individual design needs. VHDL supported by wide range of ECAD tools & development platforms.

4.6 History
4.6.1 The Requirement The development of VHDL was initiated in 1981 by the United States Department of Defense to address the hardware life cycle crisis. The cost of reprocuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology. 4.6.2 Standardization The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version 7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the DoD to the IEEE in order to encourage industry acceptance and investment. 4.6.3 VHDL 1993 As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to ensure its ongoing relevance to the industry. The first such revision was completed in September 1993, and this is still the most widely supported version of VHDL.

4.6.4 VHDL 2000 and VHDL 2002 One of the features that was introduced in VHDL-1993 was shared variables. Unfortunately, it wasn't possible to use these in any meaningful way. A working group eventually resolved this by proposing the addition of protected types to VHDL. VHDL 2000 Edition is simply VHDL-1993 with protected types.

5. VLSI Design(FPGA) process

6. Design Simulation and Design Synthesis

6.1 Synthesis
Is the process of translating a design description to another level of abstraction, i.e., from behavior to structure. We achieved synthesis by using a Synthesis tool like Foundation Express which outputs a net list. It is similar to the compilation of a high level programming language like C into assembly code

6.2 Simulation
Is the execution of a model in the software environment. During design creation/verification, a design is captured in an RTL-level (behavioral) VHDL source file. After capturing the design, you can perform a behavioral simulation of the VHDL file to verify that the VHDL code is correct. The code is then synthesized into an gate-level (structural) VHDL netlist. After synthesis, you can perform an optional pre-layout structural simulation of the design. Finally, an EDIF netlist is generated for use in Designer and a VHDL structural postlayout netlist is generated for timing simulation in a VHDL simulator.

6.3 Design Creation/Verification

6.3.1 VHDL Source Entry Enter your VHDL design source using a text editor or a context-sensitive HDL editor. Your VHDL design source can contain RTL-level constructs. 6.3.2 Behavioral Simulation Perform a behavioral simulation of your design before synthesis. Behavioral simulation verifies the functionality of your VHDL code. Typically, you use zero delays and a standard VHDL test bench to drive simulation. 6.3.3 Synthesis After you have created your behavioral VHDL design source, you must synthesize it. Synthesis transforms the behavioral VHDL file into a gate-level netlist and optimizes the design for a target technology. 6.3.4 Simulation Then simulator will check functionality. It means that design and code should be working according to truth table or not. Simulation is just testing the system at software level where as real testing is at hardware level.

7. VHDL Modelling Styles

There are three modeling styles: Behavioral Data flow Structural

7.1 Behavioral
Describe how the circuit works is meant to work and let the synthesizer work out the details. This is most useful for Finite State Machines and programs involving sequential statements and processes. Example : XOR-gate entity xor is port (a,b:in std_logic; q:out std_logic); end xor; architecture behavioral of xor is begin process(a,b) begin if (a/=b) then q <= 1; else q <= 0; end if; end process; end behavioral;

7.2 Dataflow
In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components (ex. an and gate) are connected together. In other words we describe how signals (data) flow through the circuit. Example : Xor gate entity xor is port (a,b:in std_logic; q:out std_logic); end xor; architecture dataflow of xor is begin q <= a xor b; Or in behavioral data flow style: q <= 1 when a/=b else 0; end dataflow;

7.3 Structural
Structurally defined code assigns a logical function of the inputs to each output. This is most useful for simple combinatorial logic. Example : Xor gate entity xor is port (a,b:in std_logic; q:out std_logic); end xor; architecture structural of xor is component xor1 is port(x,y:in std_logic;

m: out std_logic); end component; signal ai,bi,t3,t4:std_logic; begin u1: inverter port map (a,ai); u2: inverter port map (b,bi); u3: and_gate port map (ai,b,t3); u4: and_gate port map (bi,a,t4); u5: or_gate port map (t3,t4,q); End structural;

8. Data Types in VHDL

VHDL provides a number of basic, or scalar, types, and a means of forming composite types. The scalar types include numbers, physical quantities, and enumerations (including enumerations of characters), and there are a number of standard predefined basic types. The composite types provided are arrays and records. VHDL also provides access types (pointers) and files.

8.1 Scalar Types

8.1.1 Integer An integer type is a range of integer values within a specified range. The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range 2147483647 to +2147483647. Example : architecture test_int of test is begin process(x) variable a:integer; begin a:=1; --ok a :=-1; --ok a:=1.0; --illegal end test_int; 8.1.2 Real The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range 1.0E38 to 1.0E38. This type consists of the real numbers within a simulator-specific . Example architecture test_int of test is begin

process(x) variable a:integer; Begin a:=1.3; --ok a:=1; --illegal end test_int; 8.1.3 Enumeration An enumeration type is an ordered set of identifiers or characters. The identifiers and characters within a single enumeration type must be distinct, however they may be reused in several different enumeration types. Example type binary is ( on, off); architecture test_enu of test is begin process(x) variable a:binary ; begin a:= on; --ok a:=off; --ok end process; end test_enu; 8.1.4 Physical A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage. The declaration of a physical type includes the specification of a base unit, and possibly a number of secondary units, being multiples of the base unit. Example

type resistance is range 0 to 1000000 units ohm ; -- units kohm =1000 ohm; mohm = 1000kohm; end units;

8.2 Composite types

8.2.1 Arrays An array in VHDL is an indexed collection of elements all of the same type. Arrays may be one-dimensional (with one index) or multidimensional (with a number of indices). In addition, an array type may be constrained, in which the bounds for an index are established when the type is defined, or unconstrained, in which the bounds are established subsequently. Example type word is array (31 downto 0) of bit; type memory is array (address) of word; type transform is array (1 to 4, 1 to 4) of real; type register_bank is array (byte range 0 to 132) of integer;

8.2.2 Records VHDL provides basic facilities for records, which are collections of named elements of possibly different types. Example type instruction is record

op_code : processor_op; address_mode : mode; operand1, operand2: integer range 0 to 15; end record;

8.3 Subtypes
The use of a subtype allows the values taken on by an object to be restricted or constrained subset of some base type. There are two cases of subtypes. Firstly a subtype may constrain values from a scalar type to be within a specified range (a range constraint). Example: subtype pin_count is integer range 0 to 400; subtype digits is character range '0' to '9'; Secondly, a subtype may constrain an otherwise unconstrained array type by specifying bounds for the indices. For example: subtype id is string(1 to 20); subtype word is bit _vector(31 downto 0);

9. Objects in VHDL
An object is a named item in a VHDL description which has a value of a specified type. There are four classes of objects: Constants. Variables . Signals. Files.

9.1 Constants
Constant declarations with the initializing expression missing are called deferred constants, and may only appear in package declarations . The initial value must be given in the corresponding package body. Example constant e : real := 2.71828; constant delay : Time := 5 ns; constant max_size : natural;

9.2 Variables
A variable is an object whose value may be changed after it is created. The initial value expression, if present, is evaluated and assigned to the variable when it is created. If the expression is absent, a default value is assigned when the variable is created. The default value for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the lowest in an ascending range, or the highest in a descending range. If the

variable is a composite type, the default value is the composition of the default values for each element, based on the element types. Example variable count : natural := 0; variable trace : trace_array; variable instr : bit_vector(31 downto 0); alias op_code : bit_vector(7 downto 0) is instr(31 downto 24);

9.3 Signals
It is used for communication between VHDL components .Real, Physical signal in the systems are often mapped to VHDL signals. All VHDL signal assignment require either delta cycle or user specified delay before new value is assumed. Example signal a: bit; a <= 0;

9.4 Files
File provide a way for VHDL design communicate with host enviornment.File declaration will make file available for the use to design. It can also open for reading and writing. The package standard defines basic file I/O routines for VHDL types.

10. Operators in VHDL

VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of operators are-

10.1 Logical operators

The logical operators and, or, nand, nor, xor and not operate on values of type bit or Boolean, and also on one-dimensional arrays of these types. For array operands, the operation is applied between corresponding elements of each array, yielding an array of the same length as the result. Logic operators are the heart of logic equations and conditional statements. These are AND, OR, NOT,NAND,NOR,XOR, XNOR

10.2 Relational operators

The relational operators =, /=, <, <=, > and >= must have both operands of the same type, and yield Boolean results. The equality operators (= and /=) can have operands of any type. For composite types, two values are equal if all of their corresponding elements are equal. The remaining operators must have operands which are scalar types or one-dimensional arrays of discrete types. These are used in conditional statements. = equal to ; or equal to ; > /= not equal to ; < less than ; <= less then

greater than;


greater than or equal to

10.3 Sign operators

The sign operators (+ and ) and the addition (+) and subtraction () operators have their usual meaning on numeric operands. The concatenation operator (&) operates on onedimensional arrays to form a new array with the contents of the right operand following the contents of the left operand. It can also concatenate a single new element to an array, or two individual elements to form an array. The concatenation operator is most commonly used with strings. Example: signal A: bit_vector(5 downto 0); signal B,C: bit_vector(2 downto 0); B <= 0 & 1 & 0; C <= 1 & 1 & 0; A <= B & C; -- A now has 010110

10.4 Multiplication operator

The multiplication (*) and division (/) operators work on integer, floating point and physical types types. The modulus (mod) and remainder (rem) operators only work on integer types. The absolute value (abs) operator works on any numeric type. Finally, the exponentiation (**) operator can have an integer or floating point left operand, but must have an integer right operand. A negative right operand is only allowed if the left operand is a floating point number. / mod rem division modulus remainder

mod & rem operate on integers & result is integer rem has sign of 1st operand and is defined as: A rem B = A (A/B) * B mod has sign of 2nd operand and is defined as: A mod B = A B * N Examples: 7 mod 4 -7 mod 4 7 mod (-4) -7 mod (-4 ) -- has value 3 -- has value 3 -- has value 1 -- has value 3 -- for an integer N

10.5 Misc. Operators

These are as follows ** exponentiation left operand = integer or floating point right operand = integer only abs absolute value not inversion

10.6 Shift Operators

sll shift left logical (fill value is 0) srl shift right logical (fill value is 0) sla shift left arithmetic (fill value is right-hand bit) sra shift right arithmetic (fill value is left-hand bit) rol rotate left ror rotate right All operators have two operands: left operand is bit vector to shift/rotate right operand is integer for # shifts/rotates - integer same as opposite operator with + integer examples: 1100 sll 1 yields 1000 1100 srl 2 yields 0011 1100 sla 1 yields 1000 1100 sra 2 yields 1111 1100 rol 1 yields 1001 1100 ror 2 yields 0011 1100 ror 1 same as 1100 rol 1


11.1 With Select Statements
A selected assignment statement is also a concurrent signal assignment statement. It is sequential version of the select statement is the case statement. Syntax with expression select target <= waveform when choice [, waveform when choice ] ; Exampleentity mux4to1 is port ( a,b,c,d : in std_logic; sel: in std_logic_vector (1 downto 0); dout: out std_logic); end mux4to1; architecture whenelse of mux4to1 is begin with sel select dout <= b when "01", c when "10", d when "11", a when others; end select_statement;

11.2 When Else Statements

When is one of the fundamental concurrent statements. It appears in two forms: when/else and with/select/when. The when-else construct is useful to express logic function in the form of a truth table. Syntaxassignment when condition else

assignment when condition else Exampleentity mux4to1 is port ( a,b,c,d : in std_logic; sel: in std_logic_vector (1 downto 0); dout: out std_logic); end mux4to1; architecture whenelse of mux4to1 is begin dout <= b when (sel = "01") else c when (sel = "10") else d when (sel = "11") else a; -- default end process; end whenelse;

11.3 If Statement
Conditional structure. The if statement in VHDL is a sequential statement that conditionally executes other sequential statements, depending upon the value of some condition. An if statement may optionally contain an else part, executed if the condition is false. Syntax [ label: ] if condition1 then

sequence-of-statements elsif condition2 then

elsif condition3 then else sequence-of-statements end if [ label ] ;

Example-Mux architecture behavioral of mux is begin process (sel, a, b) begin if sel = '1' then f <= a; else f <= b; end if; end process;

11.4 Case Statements

Execute one specific case of an expression equal to a choice. The choices must be constants of the same discrete type as the expression. The selection expression must result in either a discrete type, or a one dimensional array of characters. The alternative whose choice list includes the value of the expression is selected and the statement list executed. Note that all the choices must be distinct, that is, no value may be duplicated. Syntax[ label: ] case expression is when choice1 => sequence-of-statements when choice2 => sequence-of-statements when others => sequence-of-statements end case [ label ] ; Examplearchitecture Behavioral of mux is begin process(a,b,c,d,sel) begin

case sel is when "00" => o <= a; when "01" => o <= b; when "10" => o <= c; when "11"=> o <= d; when others=> null; end case; end process; end Behavioral;

11.5 Loop Statements

VHDL has a basic loop statement, which can be augmented to form the usual while and for loops seen in other programming languages. Three kinds of iteration statements. Syntax[ label: ] loop sequence-of-statements end loop [ label ] ; [ label: ] for variable in range loop sequence-of-statements end loop [ label ] ; [ label: ] while condition loop sequence-of-statements -- use exit statement to get out

end loop [ label ] ; Exampleentity EX is port (A : in std_logic_vector(0 to 3); SEL : in integer range 0 to 3; Z : out std_logic); end EX; architecture RTL of EX is begin WHAT: process (A, SEL) begin for I in 0 to 3 loop if SEL = I then Z <= A(I); end if; end loop; end process WHAT; end RTL;

Module -III (3rd Week)


12.1 Structural Style of Modelling

Structural VHDL describes the arrangement and interconnection of components. Structural descriptions can show a more concrete relation between code and physical hardware. Structural descriptions show interconnects at any level of abstraction. The component instantiation is one of the building blocks of structural descriptions. The component instantiation process requires component declarations and component instantiation statements. Component instantiation declares the interface of the components used in the architecture. At instantiation, only the interface is visible. The internals of the component are hidden.

12.2 Components
The components and signals are declared within the architecture body, architecture architecture_name of NAME_OF_ENTITY is -- Declarations

component declarations signal declarations begin -- Statements component instantiation and connections : end architecture_name;

12.3 Component declaration

Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface (ports). The syntax is as follows: component component_name [is] [port (port_signal_names: mode type; port_signal_names: mode type; : port_signal_names: mode type);] end component [component_name]; The component name refers to either the name of an entity defined in a library or an entity explicitly defined in the VHDL file.The list of interface ports gives the name, mode and type of each port, similarly as is done in the entity declaration. Example component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component;

12.4 Component Instantiation and interconnections

The component instantiation statement references a component that can be :Previously defined at the current level of the hierarchy or Defined in a technology library (vendors library). The syntax for the components instantiation is as follows,

instance name : component name port map (port1=>signal1, port2=> signal2, port3=>signaln);

The instance name or label can be any legal identifier and is the name of this particular instance. The component name is the name of the component declared earlier using the component declaration statement. The port name is the name of the port and signal is the name of the signal to which the specific port is connected. The above port map associates the ports to the signals through named association. Example: component NAND2 port (in1, in2: in std_logic; out1: out std_logic); end component; signal int1, int2, int3: std_logic; architecture struct of EXAMPLE is U1: NAND2 port map (A,B,int1); U2: NAND2 port map (in2=>C, in2=>D, out1=>int2); U3: NAND3 port map (in1=>int1, int2, Z);

12.5 Benefits of Structural Style

Circuits can be described like a netlist Components can be customized Large, regular circuits can be created

A counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In electronics, counters can be implemented quite easily using register-type circuits such as the flip flop, and a wide variety of designs exist, e.g.: Asynchronous (ripple) counter changing state bits are used as clocks to subsequent state flip-flops. Synchronous counter all state bits change under control of a single clock. Decade counter counts through ten states per stage. Updown counter counts both up and down, under command of a control input. Ring counter formed by a shift register with feedback connection in a ring. Johnson counter a twisted ring counter. Cascaded counter.

13.1 Johnson counter

The Johnson counter can be made with a series of D flip-flops or with a series of J-K flip flops. Here Q3 and Q3 are fed back to the J and K inputs with a twist.

The disadvantage to this counter is that it must be preloaded with the desired pattern (usually a single 0 or 1) and it has even fewer states than a Johnson counter (n, where n = number of flip-flops. On the other hand, it has the advantage of being self-decoding with a unique output for each state.

13.2 Up/Down Counter

entity updown is Port ( clr,clk,up : in STD_LOGIC; count : inout STD_LOGIC_VECTOR(3 downto 0)); end updown; architecture Behavioral of updown is signal output: std_logic_vector(3 downto 0); begin process(clr,clk,up) begin if clr = '1' then output <= "0000"; elsif(clk'event and clk ='1') then if up ='0' then output <= output + 1; else output <= output -1; end if; end if; end process; count <= output; end Behavioral;

13.3 BCD Counter

A 4-bit BCD-counter built with JK-flip flops. This is an asynchronous implementation of a cascadable, 4-bit, binary-coded decimal counter. In total, the circuits needs just the four flip flops and one additional AND gate. VHDL Code: entity bcd is Port ( clr,clk : in STD_LOGIC; count : inout STD_LOGIC_VECTOR (3 downto 0)); end bcd ; architecture Behavioral of mod16 is begin process(clr,clk)

begin if(clk'event and clk ='1') then if (clr = '1' or count >= 9) then count <="0000"; else count <= count + 1; end if; end if; end process; end Behavioral;

14. Flip Flops & Latches

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Memory means circuit remains in one state after condition that caused the state is removed. Two outputs designated Q and Q-Not that are always opposite or complimentary. When referring to the state of a flip flop, referring to the state of the Q output. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic When used in a finite-state machine the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs.) It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Flip-flops can be either simple (transparent or opaque) or clocked(synchronous or edge-triggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.

15. Flip Flops

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of crosscoupled NOR logic gates. The stored bit is present on the output marked Q.While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low. Symbol and Diagram and truth table Basic flip-flop circuit with NOR gates

Basic flip-flop circuit with NAND gates

15.2 JK flip-flop
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flipflop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop. The characteristic equation of the JK flip-flop is:

Symbol and Diagram

Logic diagram

Graphical symbol Transition table

15.3 D flip-flop
The D ip-op is the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output Q looks like a delay of input D).The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise. Symbol and Diagram

Logic diagram with NAND gates

Graphical symbol Transition table

Module -IV (4th Week)

16. Shift Registers

A register is a digital circuit with two basic functions: Data Storage and Data Movement A shift register provides the data movement function A shift register shifts its output once every clock cycle

A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is active.

16.1 Shift Register Applications

Communications UART Converting between serial data and parallel data Temporary storage in a processor Scratch-pad memories Some arithmetic operations Multiply, divide Some counter applications Johnson counter

Ring counter LSFR counters Time delay devices and more

16.2 Shift Register Characteristics

16.2.1 Types

Serial-in, Serial-out Serial-in, Parallel-out Parallel-in, Serial-out Parallel-in, Parallel-out Universal

16.2.2 Direction

Left shift Right shift Rotate (right or left) Bidirectional

16.3 Data Movement

The bits in a shift register can move in any of the following manners

16.4 Serial-In Serial-Out

Data bits come in one at a time and leave one at a time. One Flip-Flop for each bit to be handled. Movement can be left or right, but is usually only a single direction in a given register Asynchronous preset and clear inputs are used to set initial values.

16.5 Serial-to-Parallel Conversion

We often need to convert from serial to parallel e.g., after receiving a series transmission. The diagrams at right illustrate a 4-bit serial-in parallel-out shift register. Note that we could also use the Q of the right-most Flip-Flop as a serial-out output

16.6 Parallel-to-Serial Conversion

We use a Parallel-in Serial-out Shift Register. The DATA is applied in parallel form to the parallel input pins PA to PD of the register. It is then read out sequentially from the register one bit at a time from PA to PD on each clock cycle in a serial format. One clock pulse to load. Four pulses to unload.

16.7 Parallel in parallel out

All data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output

17. Finite State Machines

A finite state machine a set of states and two functions called the next state function and the output function. The set of states corresponding to all the possible combinations of the internal storage If there are n bits of storage , there are 2n possible states. The next state function is a combinational logic function that given the inputs and the current state, determines the next state of the system. The output function produces a set of outputs from the current state and the inputs.

Sequential circuits primitive sequential elements combinational logic Models for representing sequential circuits Finite-state machines (Moore and Mealy) Basic sequential circuits revisited Shift registers Counters Design procedure State diagrams State transition table Next state functions Hardware description languages These are the topics that will be discussed in this chapter. Of course the next state depends on the current state and the input values. The FSMs fall into two categories: Moore and Mealy machines. Also we will look at how inputs are handled in sequential systems. Still registers and counters are key parts of the sequential circuits.

17.1 Finite state machine design procedure

Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Hardware description languages

We start with simple FSMs like counters and shift registers, where states are outputs directly. We should differentiate Moore and Mealy models. With either model, we should be able to design a FSM. Counters are simple finite state machines Counters proceed through well-defined sequence of states in response to enable Many types of counters: binary, BCD, Gray-code 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

In the case of a 3bit up counter, every clock tick will make a transition without any inputs. In this case the numbers follow binary coding; hence it is called a binary counter. Example: FSM design procedure: state diagram to encode state transition table Tabular form of state diagram Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters just use value

For the 3-bit up counter, here is the state transition table. Its like there are three inputs and three outputs. In this case the literals for states are the inputs for the state transition. If there are other outside inputs, those should be also written in the table.

17.2 Implementation
D flip-flop for each state bit Combinational logic based on encoding

VHDL notation to show function represents an input to D-FF

These are K-maps for three outputs. <= is a non-blocking assignment operator. That is, all values (N1, N2, N3) are changed at the same time, not sequentially.


AIM: The aim of the project is to design a Traffic Light Control System using VHDL and simulate it using ModelSim/ISE Simulator. INTRODUCTION: The project aims to design a Traffic Light Controller using VHDL and implement the Traffic Light Controller in FPGA. The traffic in road crossings/junctions are controlled by switching ON/OFF Red, Green & Yellow lights in a particular sequence. The Traffic Light Controller is designed to generate a sequence of digital data called switching sequences that can be used to control the traffic lights of a junction in a fixed sequence. The traffic department is trying out a new system of traffic lights based on the usual European model. We have to design a synchronous digital circuit, a Moore machine, which operates this new type of traffic light at two types of road crossing. The traffic in road crossings/junctions are controlled by switching ON/OFF Red, Green & Yellow lights in a particular sequence. The Traffic Light Controller is designed to generate a sequence of digital data called switching sequences that can be used to control the traffic lights of a junction in a fixed sequence. DESIGN: Our task is to implement a controller for a traffic light. The sequence of lights is to be as follows: STATES S0 S1 S2 S3 S4 S5 S6 S7 I Lights Red Red Red Red Red Yellow Green Yellow II Lights Red Red Red Yellow Green Yellow Red Red III Lights Red Yellow Green Yellow Red Red Red Red IV Lights Green Yellow Red Red Red Red Red Yellow

The red-red condition provides a bit of a safety margin.

However, traffic controllers also have timing requirements. For example I can specify that a Green light is required to stay on for 30 seconds and the Yellow light for 4 seconds. If I add the requirement that both lights are Red for only one second, the timing for the traffic light controller is completely specified. For this purpose, I am using a counter to control the timings.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.STD_LOGIC_arith.ALL; entity traffic_light_control_system is Port ( clk,rst : in STD_LOGIC; r1,y1,g1 : out STD_LOGIC; r2,y2,g2 : out STD_LOGIC; r3,y3,g3 : out STD_LOGIC; r4,y4,g4 : out std_logic); end traffic_light_control_system; architecture Behavioral of traffic_light_control_system is type state is( s0,s1,s2,s3,s4,s5,s6,s7); signal ps,ns: state; signal count : std_logic_vector(4 downto 0); begin p1:process(clk) begin if ( rst='1') then ps<= s0; count<="00000"; elsif( clk'event and clk ='1') then

ps <= ns; count<=count+"00001"; end if; end process; p2:process (clk,count) begin case ps is when s0=> r1<= '1'; r2<= '1'; r3<= '1'; r4<= '0'; y1<= '0'; y2<= '0'; y3<= '0'; y4<= '0'; g1<= '0'; g2<= '0'; g3<= '0'; g4<= '1'; if(count>="00100")then ns<= s1; else ns<=s0; end if; when s1=> r1<= '1';

r2<= '1'; r3<= '0'; r4<= '0'; y1<= '0'; y2<= '0'; y3<= '1'; y4<= '1'; g1<= '0'; g2<= '0'; g3<= '0'; g4<= '0'; if(count>="01000")then ns<= s2; else ns<=s1; end if; when s2=> r1<= '1'; r2<= '1'; r3<= '0'; r4<= '1'; y1<= '0'; y2<= '0'; y3<= '0'; y4<= '0'; g1<= '0'; g2<= '0';

g3<= '1'; g4<= '0'; if(count>="01100")then ns<= s3; else ns<=s2; end if; when s3=> r1<= '1'; r2<= '0'; r3<= '0'; r4<= '1'; y1<= '0'; y2<= '1'; y3<= '1'; y4<= '0'; g1<= '0'; g2<= '0'; g3<= '0'; g4<= '0'; if(count>="10000")then ns<= s4; else ns<=s3; end if; when s4=> r1<= '1';

r2<= '0'; r3<= '1'; r4<= '1'; y1<= '0'; y2<= '0'; y3<= '0'; y4<= '0'; g1<= '0'; g2<= '1'; g3<= '0'; g4<= '0'; if(count>="10100")then ns<= s5; else ns<=s4; end if; when s5=> r1<= '0'; r2<= '0'; r3<= '1'; r4<= '1'; y1<= '1'; y2<= '1'; y3<= '0'; y4<= '0'; g1<= '0'; g2<= '0';

g3<= '0'; g4<= '0'; if(count>="11000")then ns<= s6; else ns<=s5; end if; when s6=> r1<= '0'; r2<= '1'; r3<= '1'; r4<= '1'; y1<= '0'; y2<= '0'; y3<= '0'; y4<= '0'; g1<= '1'; g2<= '0'; g3<= '0'; g4<= '0'; if(count>="11100")then ns<= s7; else ns<=s6; end if; when s7=> r1<= '0';

r2<= '1'; r3<= '1'; r4<= '0'; y1<= '1'; y2<= '0'; y3<= '0'; y4<= '1'; g1<= '0'; g2<= '0'; g3<= '0'; g4<= '0'; if(count>="11111")then ns<= s0; else ns<=s7; end if; end case; end process; end Behavioral;


I hereby conclude that after attending the six weeks industrial training in C-DAC, Mohali in VLSI technology. I had gained a knowledge of circuit designing using VHDL coding .With the help of XILINX ISE software and FPGA kit (SPARTAN-3), I have become familiar with various modules such as Design Entry, Synthesizing the Design, Behavioral Simulation, etc. I have also got knowledge about designing of a Digital Circuit using Xilinx software and how to implement that design on a FPGA kit using this software. This helps me gaining a lot of knowledge about the implementation of a particular design on a FPGA kit.


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