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Module 1
Power Semiconductor Devices
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Lesson 1
Power Electronics
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Introduction
This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) Create an awareness of the general nature of Power electronic equipment; Brief idea about topics of study involved, The key features of the principal Power Electronic Devices; An idea about which device to choose for a particular application. A few issues like base drive and protection of PE devices and equipment common to most varieties.

Power Electronics is the art of converting electrical energy from one form to another in an efficient, clean, compact, and robust manner for convenient utilisation. A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the scene it consumes less power with reduced stresses on the motor and corruption of the utility mains.

Fig. 1.1 The block diagram of a typical Power Electronic converter Power Electronics involves the study of • • • • • • • • Power semiconductor devices - their physics, characteristics, drive requirements and their protection for optimum utilisation of their capacities, Power converter topologies involving them, Control strategies of the converters, Digital, analogue and microelectronics involved, Capacitive and magnetic energy storage elements, Rotating and static electrical devices, Quality of waveforms generated, Electro Magnetic and Radio Frequency Interference, Version 2 EE IIT, Kharagpur 3 www.jntuworld.com

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• Thermal Management The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.

How is Power electronics distinct from linear electronics?
It is not primarily in their power handling capacities. While power management IC's in mobile sets working on Power Electronic principles are meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand watts. The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best symbolises the difference. In Power Electronics all devices are operated in the switching mode either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3. Saturation and cutoff zones in the VCE - IC plane are avoided. In a Power electronic switching amplifier, only those areas in the VCE - IC plane which have been skirted above, are suitable. Onstate dissipation is minimum if the device is in saturation (or quasi-saturation for optimising other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch will try to traverse the active zone as fast as possible to minimise switching losses.

Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier

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Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a switching amplifier Linear operation Active zone selected: Good linearity between input/output Switching operation Active zone avoided : High losses, encountered only during transients Saturation & cut-off zones avoided: poor Saturation & cut-off (negative bias) zones linearity selected: low losses Transistor biased to operate around No concept of quiescent point quiescent point Common emitter, Common collector, Transistor driven directly at base - emitter common base modes and load either on collector or emitter Output transistor barely protected Switching-Aid-Network (SAN) and other protection to main transistor Utilisation of transistor rating of secondary Utilisation of transistor rating optimised importance

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An example illustrating the linear and switching solutions to a power supply specification will emphasise the difference. Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W
Ferrite core HF transfr: Light, efficient Series regulator high losses 230 V

230 V

Line freq transformer: heavy, lossy

(a)
High-freq Duty-ratio (ON/OFF) control - low losses

(b)

Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification above The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the supply voltage to 12-0-12 V through a power frequency transformer. The output would be rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance of the voltage between the output of the rectifier and the output drops across the regulator device which also carries the full load current. The power loss is therefore considerable. Also, the stepdown iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripples appear at the output and material cost and technical know-how required is low. In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line voltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency (HF) transformer is used. Losses are negligible compared to the first solution and the converter is extremely light. However significant high frequency (related to the switching frequency) noise appear at the output which can only be minimised through the use of costly 'grass' capacitors.

Power Semiconductor device - history
Power electronics and converters utilizing them made a head start when the first device the Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The necessity arose of extending the application of the SCR beyond the line-commutated mode of action, which called for external measures to circumvent its turn-off incapability via its control terminals. Various turn-off schemes were proposed and their classification was suggested but it became increasingly obvious that a device with turn-off capability was desirable, which would permit it a wider application. The turn-off networks and aids were impractical at higher powers. The Bipolar transistor, which had by the sixties been developed to handle a few tens of amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior to the SCR in its turn-off capability, which could be exercised via its control terminals. This permitted the replacement of the SCR in all forced-commutated inverters and choppers. However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor Version 2 EE IIT, Kharagpur 6 www.jntuworld.com

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and the high base currents required to switch the Bipolar spawned the Darlington. Three or more stage Darlingtons are available as a single chip complete with accessories for its convenient drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the 'fast' inverter-grade SCRs permitting reduction of filter components. But the Darlington's operating frequency had to be reduced to permit a sequential turn-off of the drivers and the main transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This device also represents the first successful marriage between modern integrated circuit and discrete power semiconductor manufacturing technologies. Its voltage drive capability – giving it again a higher gain, the ease of its paralleling and most importantly the much higher operating frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the MOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier device its on-state voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about VDSS2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially viable. Improvements were being tried out on the SCR regarding its turn-off capability mostly by reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol for the device. The requirement for an extremely high turn-off control current via the gate and the comparatively higher cost of the device restricted its application only to inverters rated above a few hundred KVA. The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded in different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated Gate Bipolar Transistor (IGBT) – basically a MOSFET driven Bipolar from its terminal characteristics has been a successful proposition with devices being made available at about 4 KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET has been able to continue in the sub – 10 KVA range primarily because of its high switching frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA. Subsequent developments in converter topologies – especially the three-level inverter permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based converters are possible at the highest range where line-commutated or load-commutated converters were the only solution. The surge current, the peak repetition voltage and I2t ratings are applicable only to the thyristors making them more robust, specially thermally, than the transistors of all varieties.

1200V Version 3 ASIPM

Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A Version 2 EE IIT, Kharagpur 7 www.jntuworld.com

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IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated Gate Commutated Thyristors) of ABB which are promising at the higher power ranges. However these new devices must prove themselves before they are accepted by the industry at large. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about 2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a high-quality native oxide suitable for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times higher than in silicon. This is important for high-voltage power switching transistors. For example, a device of a given size in SiC will have a blocking voltage 8 times higher than the same device in silicon. More importantly, the on-resistance of the SiC device will be about two decades lower than the silicon device. Consequently, the efficiency of the power converter is higher. In addition, SiC-based semiconductor switches can operate at high temperatures (~600 C) without much change in their electrical properties. Thus the converter has a higher reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink size. Moreover, the high frequency operating capability of SiC converters lowers the filtering requirement and the filter size. As a result, they are compact, light, reliable, and efficient and have a high power density. These qualities satisfy the requirements of power converters for most applications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offer substantially better performance. With the SCR and the pin-diodes, so called because of the sandwiched intrinsic ‘i’-layer between the ‘p’ and ‘n’ layers, having mostly line-commutated converter applications, emphasis was mostly on their static characteristics - forward and reverse voltage blocking, current carrying and over-current ratings, on-state forward voltage etc and also on issues like paralleling and series operation of the devices. As the operating speeds of the devices increased, the dynamic (switching) characteristics of the devices assumed greater importance as most of the dissipation was during these transients. Attention turned to the development of efficient drive networks and protection techniques which were found to enhance the performance of the devices and their peak power handling capacities. Issues related to paralleling were resolved by the system designer within the device itself like in MOSFETS, while the converter topology was required to take care of their series operation as in multi-level converters. The range of power devices thus developed over the last few decades can be represented as a tree, Fig. 1.5, on the basis of their controllability and other dominant features.

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POWER SEMICONDUCTOR DEVICES

UNCONTROLLED

CONTROLLED

RECTIFIERS

ACCESSORIES

REGENERATIVE SCR TRIAC GTO

NON-REGENERATIVE BJT MOSFET IGBT

INTEGRATED IGCT PIC INTELLIGENT POWER MODULES

POWER SILICON DIODES FREDS SCHOTTKY

DIAC Zenner MOV

Fig. 1.5 Power semiconductor device variety

Power Diodes
diF /dt

t0

t1

t2

SNAPPY

SOFT Δ to Q1 Q2

IRM

VRM

Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode' Silicon Power diodes are the successors of Selenium rectifiers having significantly improved forward characteristics and voltage ratings. They are classified mainly by their turn-off (dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time - trr (reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (= Q1 + Q2) - the charge to be dissipated as a negative current when the and diode turns off and trr (= t2 - t0) - the time it takes to regain its blocking features, impose strong current stresses on the controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt voltages on all associated power device in the converter because of load or stray inductances present in the network. There are broadly three types of diodes used in Power electronic applications: Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent overcurrent (surge rating about six times average current rating) and surge-voltage withstand capability. They have relatively large Qrr and trr specifications.

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Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's, have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and are mainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers and rectifier applications. Fast recovery diodes also find application in induction heating, UPS and traction. Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any Qrr.. However, they are available with voltage ratings up to a hundred volts only though current ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no competition in low voltage SPMS applications and in instrumentation.

Silicon Controlled Rectifier (SCR)
The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer regenerative devices. It is normally turned on by the application of a gate pulse when a forward bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot be turned off via the gate terminals specially at the extremely high amplification factor of the gate. There are two main types of SCR's. Converter grade or Phase Control thyristors These devices are the work horses of the Power Electronics. They are turned off by natural (line) commutation and are reverse biased at least for a few milliseconds subsequent to a conduction period. No fast switching feature is desired of these devices. They are available at voltage ratings in excess of 5 KV starting from about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are built with series-parallel combination of these devices. Conduction voltages are device voltage rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation components. The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years borrowing emitter shorting and other techniques adopted for the faster variety. The requirement for hard gate drives and di/dt limting inductors have been eliminated in the process. Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 μsecs when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly used in circuits that are operated on DC supplies and no alternating voltage is available to turn them off. Commutation networks have to be added to the basic converter only to turn-off the SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time, tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite a few commutation networks were designed and some like the McMurray-Bedford became widely accepted. Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the basic SCR have been proposed for specific applications. The Asymmetrical thyristor is convenient when reactive powers are involved and the light activated SCR assists in paralleling or series operation.

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MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device for SMPS, lighting ballast type of application where high switching frequencies are desired but operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency applications, where the currents drawn by the equivalent capacitances across its terminals are small, it can also be driven directly by integrated circuits. These capacitances are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of its main terminals permit easy paralleling externally also. At high current low voltage applications the MOSFET offers best conduction voltage specifications as the RDS(ON) specification is current rating dependent. However, the inferior features of the inherent antiparallel diode and its higher conduction losses at power frequencies and voltage levels restrict its wider application.

The IGBT
It is a voltage controlled four-layer device with the advantages of the MOSFET driver and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punchthrough (NPT) structures. In the punch-through IGBT, a better trade-off between the forward voltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about 1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more robust than PT IGBTs particularly under short circuit conditions. However they have a higher forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably shaping the drive signal. This gives the IGBT a number of advantages: it does not require protective circuits, it can be connected in parallel without difficulty, and series connection is possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe Operating Area devoid of a Second Breakdown region.

The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode current to be turned off. Hence there is no need for an external commutation circuit to turn it off. Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is short, thus giving it more capability for highfrequency operation than thyristors. The GTO symbol and turn-off characteristics are shown in Fig. 30.3. GTOs have the I2t withstand capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs, the critical aspects are proper design of the gate turn-off circuit and the snubber circuit.

Power Converter Topologies
A Power Electronic Converter processes the available form to another having a different frequency and/or voltage magnitude. There can be four basic types of converters depending upon the function performed: Version 2 EE IIT, Kharagpur 11 www.jntuworld.com

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CONVERSION FROM/TO

NAME

FUNCTION

SYMBOL

DC to DC

Chopper

Constant to variable DC or variable to constant DC

DC to AC

Inverter

DC to AC of desired voltage and frequency

~ ~ ~

AC to DC

Rectifier

AC to unipolar (DC) current

AC to AC

Cycloconverter, AC-PAC, Matrix converter

AC of desired frequency and/or magnitude from generally line AC

~

Base / gate drive circuit
All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The amplification factor of all the devices (barring the now practically obsolete BJT) are quite high, though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy the control terminal characteristics to efficiently tun-on each of the devices of the converter, turn them off, if possible, again optimally and also to protect the device against faults, mostly overcurrents. Being driven by a common controller, the drives must also be isolated from each other as the potentials of the Main Terminal which doubles as a Control terminal are different at various locations of the converter. Gate-turn-off-able devices require precise gate drive waveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier is located after the isolation stage. Thus separate isolated power supplies are also required for each Power device in the converter (the ones having a common Control Terminal - say the Emitter in an IGBT - may require a few less). There are functionally two types of isolators: the pulse transformer which can transmit after isolation, in a multi-device converter, both the un-shaped signal and power and optical isolators which transmit only the signal. The former is sufficient for a SCR without isolated power supplies at the secondary. The latter is a must for practically all other devices. Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR. Version 2 EE IIT, Kharagpur 12 www.jntuworld.com

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IGBT

Vref
COMPARATOR

TIMER

Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCR

Protection of Power devices and converters
Power electronic converters often operate from the utility mains and are exposed to the disturbances associated with it. Even otherwise, the transients associated with switching circuits and faults that occur at the load point stress converters and devices. Consequently, several protection schemes must be incorporated in a converter. It is necessary to protect both the Main Terminals and the control terminals. Some of these techniques are common for all devices and converters. However, differences in essential features of devices call for special protection schemes particular for those devices. The IGBT must be protected against latching, and similarly the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible turn-off-able current specification. Power semiconductor devices are commonly protected against: 1. 2. 3. 4. 5. 6. 7. 8. Over-current; di/dt; Voltage spike or over-voltage; dv/dt ; Gate-under voltage; Over voltage at gate; Excessive temperature rise; Electro-static discharge;

Semiconductor devices of all types exhibit similar responses to most of the stresses, however there are marked differences. The SCR is the most robust device on practically all counts. That it has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further, the transistors permit designed gate current waveforms to minimise voltage spikes as a consequence of sharply rising Main terminal currents. Gate resistances have significant effect on turn-on and turn-off times of these devices - permitting optimisation of switching times for the reduction of switching losses and voltage spikes.

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are guided by the energy content of the surges.www. additionally minimise switching losses of the device .thus reducing its temperature rise. e) SCR . (f) GTO. Forced-cooling techniques are very important for the higher rated converters and whole environments are air-cooled to lower the ambient.jntuworld. It has a resistive load and is supplied from a 100 V DC supply. Metal Oxide Varistors (MOV's). These 'snubbers' or 'switching-aid-networks'.7 may be used. c) MOSFET. Ans: The most important ratings of the Pulse transformer are its volt-secs rating. the isolation voltage and the turns ratio.the zener being also a very fast-acting device. Consequently the volt secs may be in the range of 9 x 50 = 450 μvolt-secs = 2. The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period for which the pulse is applied to the winding If the primary pulse voltage = (Supply voltage – drive transistor drop) The turn-on time of he SCR may be in the range 50 μsecs for an SCR of this rating. Protection against issues like excessive case temperatures and ESD follow well-set practices. b) SCR. Highest voltage / current ratings.com Protection schemes for over-voltages . f) Gate-turn off capability with regenerative features. Can be most effectively paralleled. Kharagpur 14 www. IM = 150 mA The Pulse transformer may be chosen as: 1:1. (g) IGBT Qs#2 An SCR requires 50 mA gate current to switch it on. 1. This is achieved with the help of Zener clamps .the prolonged ones and those of short duration . Easy drive features. R-C or R-C-D clamps are used depending on the speed of the device.jntuworld. Gates of all devices are required to be protected against over-voltages (typically + 20 V) specially for the voltage driven ones. 450 μVs.com . Diodes 1N4002 Series resistance = (Supply voltage – drive transistor drop – gate-cathode drop)/100mA = (10 –1 –1) / 100 E-3 = 80 Ohm = 49 or 57 Ohm (nearest available lower value) Version 2 EE IIT. For high dv/dt stresses. if the driver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V. Specify the Pulse transformer details and the circuit following it. g) Easy drive and High power handling capability Ans: a) MOSFET. e) Can be protected against over-currents with a fuse. Objective type questions Qs#1 Which is the Power semiconductor device having a) b) c) d) Highest switching speed.5 KV. d) MOSFET. Visol The circuit shown in Fig. which again have similar effect on all devices. capacitive dynamic voltage-clamps and crow-bar circuits are some of the strategies commonly used.

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www.com . Kharagpur 2 www.jntuworld.com Lesson 2 Constructional Features. Characteristics and Specification of Power Semiconductor Diode Version 2 EE IIT. Operating Principle.jntuworld.

8. Identify the constructional features that distinguish a power diode from a signal level diode. Calculate the voltage drop across a forward biased diode for a given forward current and vice-verse. Draw the spatial distribution of charge density. 6. 4. 3. Evaluate the forward current specifications of a diode for a given application. electric field and electric potential in a step junction p-n diode. 7. Differentiate between different reverse voltage ratings found in a Power Diode speciation sheet. Identify the difference between the forward characteristic of a power diode and a signal level diode and explain it.com .com Instructional Objective On Completion the student will be able to 1. Version 2 EE IIT.www.jntuworld. Draw the “Turn On” and “Turn Off” characteristics of a power diode.jntuworld. 2. “Reverse recovery current” “Reverse Recovery charge” as applicable to a power diode. Define “Forward recovery voltage”. Kharagpur 3 www. 5.

At this point the p-n junction is said to be in thermal equilibrium condition. important to understand the nature and implication of these modifications in relation to the simplest of the power devices.com Power Semiconductor Diodes 2. In an open circuit p-n junction diode. the electric field and the potential along the device is shown in Fig 2. This region of immobile ionized atoms is called the space charge region. 2.1 (a). a power semiconductor diode.jntuworld. are required to carry up to several KA of current under forward bias condition and block up to several KV under reverse biased condition. Variation of the space charge density. however.com .2 Review of Basic p-n Diode Characteristics A p-n junction diode is formed by placing p and n type semiconductor materials in intimate contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type silicon crystal or by the opposite sequence. These power devices. majority carriers from either side will defuse across the junction to the opposite side where they are in minority. i. This process continues till the resultant electric field (created by the space charge density) and the potential barrier at the junction builds up to sufficient level to prevent any further migration of carriers.jntuworld.1 Introduction Power semiconductor diode is the “power level” counter part of the “low power signal diodes” with which most of us have some degree of familiarity.. These extreme requirements call for important structural changes in a power diode which significantly affect their operating characteristics. Version 2 EE IIT. It is.e. These diffusing carriers will leave behind a region of ionized atoms at the immediate vicinity of the metallurgical junction.www. Kharagpur 4 www. therefore. These structural modifications are generic in the sense that the same basic modifications are applied to all other low power semiconductor devices (all of which have one or more p-n junctions) to scale up their power capabilities.

Reverse break down is caused by "impact ionization" as explained below.com . Version 2 EE IIT. Therefore. The electric field strength at the junction and the width of the space change region (also called “the depletion region” because of the absence of free carriers) also increases. These two components of current together is called the “reverse saturation current Is” of the diode. This reverse bias adds to the height of the potential barrier. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. This cascading effect (avalanche) may produce a large number of free electrons very quickly resulting in a large reverse current. free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge of the depletion region on either side (Fig 2.com (a) (b) (c) Fig 2. When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition.jntuworld. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process.jntuworld.1: Space change density the electric field and the electric potential in side a p-n junction under (a) thermal equilibrium condition. The liberated electron in turn may repeat the process. The power dissipated in the device increases manifold and may cause its destruction. (c) forward biased condition. On the other hand. This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. Value of Is is independent of the reverse voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. The diode is said to have undergone “reverse break down”.1 (b)). When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly.www. operation of a diode in the reverse breakdown region must be avoided. Kharagpur 5 www. (b) reverse biased condition.

e. (ii) The maximum electric field strength at the center of the depletion layer increases with _______________ in the reverse voltage.1 (1) Fill in the blanks with the appropriate word(s). The injected minority carriers eventually recombines with the majority carries as they defuse further into the electrically neutral drift region.2.. Version 2 EE IIT. Kharagpur 6 www. The excess free carrier density in both p and n side follows exponential decay characteristics.com .jntuworld.1) Where Is = Reverse saturation current ( Amps) v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzman’s constant T = Temperature in Kelvin From the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn as shown in Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode Exercise 2. (i) The width of the space charge region increases as the applied ______________ voltage increases. (iii) Reverse saturation current in a power diode is extremely sensitive to ___________ variation. While drawing this characteristics the ohmic drop in the bulk of the semiconductor body has been neglected. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current IF (flowing from p side to n side) which can be expressed as IF = IS ( exp ( qv/kT ) ) -1 (2. p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction.com When the diode is forward biased (i.www. Fig 2.jntuworld.

What should be the value of the forward current for a forward voltage drop of 0.1 ⎟ . Answer: ⎛ VF VT ⎞ iF = Is ⎜ e -1⎟ ∴ ⎝ ⎠ VF Is diF = e dVF VT VT N ow I s = 5 × 10 -8 A . di (3) For the diode of Problem-2 calculate the dynamic ac resistance ra c = F d v F at 32°C and a forward voltage drop of 0. (iii) temperature.5V.com . Assume VT = KT/q at 32°C = 26 mv. the power loss at the required rated current will be unacceptably high.24 Am ps. Large blocking voltage requires wide depletion layer in order to restrict the maximum electric field strength below the “impact ionization” level.com (iv) Donor atoms are _____________________ carrier providers in the p type and _________________ carrier providers in the n type semiconductor materials. Consequently.F dVF V = ra c = T e V T = 2 . Space charge density in the depletion layer should also be low in order to yield a wide depletion layer for a given maximum Electric fields strength. VT = 26×10-3 V V = 0. (iv) Minority Majority. Is = 5×10-8 A. Answer ⎛ V ⎞ I F = I s ⎜ e VT . V F = 0. Such a construction. On the other hand if forward resistance (and hence power loss) is reduced by increasing the doping level.5V .jntuworld. reverse break down voltage will reduce. Kharagpur 7 www. (ii) increase. VT = 26 ×10 -3 V at 32o C ∴ V . (v) inversely (2) A p-n junction diode has a reverse saturation current rating of 50 nA at 32°C. These two requirements will be satisfied in a lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer.3 1 3 m Ω diF Is 2. Answer: (i) Reverse.www. This apparent contradiction in the requirements of a power diode is resolved by introducing a lightly doped “drift layer” of required Version 2 EE IIT.jntuworld. (v) Forward current density in a diode is __________________________ proportional to the life time of carriers. will result in a device with high resistively in the forward direction.5V ⎝ ⎠ ∴ I F = 11. however.3 Construction and Characteristics of Power Diodes As mention in the introduction Power Diodes of largest power rating are required to conduct several kilo amps of current in the forward direction with very little power loss while blocking several kilo volts in the reverse direction.5V.

com . However.1 Power Diode under Reverse Bias Conditions Back As in the case of a low power diode the applied reverse voltage is supported by the depletion layer formed at the p+ n. This p type region acts as the anode. Fig 2. 2. To arrive at the structure shown in Fig 2.3 (c) a lightly doped n. The Implication of introducing this drift region in a power diode is explained next. Kharagpur 8 www. In a low power diode this drift region is absent.epitaxial layer of specified width (depending on the required break down voltage) and donor atom density (NdD) is grown on a heavily doped n+ substrate (NdK donor atoms.region.3 (a) and (b) shows the circuit symbol and the photograph of a typical power diode respectively.3(c).3: Diagram of a power. (a) circuit symbol (b) photograph.jntuworld. since NdD << NaA. Impurity atom densities in the heavily doped cathode (Ndk . (c) schematic cross section.com thickness between two heavily doped p and n layers as shown in Fig 2. 2.Cm-3) p+ region into the epitaxial layer.jntuworld.Cm -3) and anode (NaA.metallurgical junction. Overall neutrality of the space change region dictates that the number of ionized atoms in the p+ region should be same as that in the n.www. Finally the p-n junction is formed by defusing a heavily doped (NaA acceptor atoms. (b) Fig.3.drift Version 2 EE IIT.Cm -3) are approximately of the same order of magnitude (10 19 Cm -3) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (NdD ≈ 10 14 Cm-3).Cm -3) which acts as the cathode. the space charge region almost exclusively extends into the n.

Voltage across the device dose not increase any further while the reverse current is limited by the external circuit. Excessive power loss and consequent increase in the junction temperature due to continued operation in the reverse brake down region quickly destroies the diode.punch through” construction. in the punch through construction the field strength is more uniform. (ii) punch through type.com . reduced width of the drift region in these diodes lowers the on-state voltage drop for the same forward current density compared to a non-punch through diode. by choosing a very lightly doped n.e from cathode to anode). (i) non punch through type. This reverse current is independent of the applied reverse voltage but highly sensitive to junction temperature variation.com region. Lower drift region doping in a “punch through” diode does not carry the penalty of higher conduction lasses due to “conductivity modulation” to be discussed shortly. However. Version 2 EE IIT.5. In fact. reverse current increases very rapidly due to impact ionization and consequent avalanche multiplication process.drift region. Under the assumption of uniform electric field strength it can be shown that for the same break down voltage. In non-punch through type diodes the electric field strength is maximum at the p+ n. due to very large doping density of the cathode. the “punch through” construction will require approximately half the drift region width of a comparable “ non .jntuworld. Kharagpur 9 www. In fact. Under reverse bias condition only a small leakage current (less than 100mA for a rated forward current in excess of 1000A) flows in the reverse direction (i. When the applied reverse voltage reaches the break down voltage. (a) Non-punch through type.4. A typical I-V characteristic of a power diode under reverse bias condition is shown in Fig 2. Electric field strength inside the drift region of both these type of diodes at break down voltage is shown in Fig 2.www. Electric field strength in this region can be mode almost constant. (b) punch through type. Fig 2.4: Electric field strength in reverse biased power Diodes. Where as. Now the physical width of the drift region (WD) can be either larger or smaller than the depletion layer width at the break down voltage. Consequently two type of diodes exist. On the other hand in “punch through” diodes the depletion layer spans the entire drift region and is in contact with the n+ cathode.junction and decrease to zero at the end of the depletion region. In “non-punch through” diodes the depletion layer boundary doesn’t reach the end of the drift layer. continued operation in the reverse break down region should be avoided. Therefore. penetration of drift region inside cathode is negligible.jntuworld.

com . DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reverse direction (i. Version 2 EE IIT. Useful for selecting diodes for controlled / uncontrolled power frequency line commutated AC to DC rectifiers.e cathode positive with respect to anode) across the device for indefinite period of time. 2.6 shows the relationship among these different reverse voltage specifications.5: Reverse bias i-v characteristics of a power Diode. Such transient reverse voltage can be generated by power line switching (i.jntuworld. This rating is different for resistive and capacitive loads. It is useful for selecting free-wheeling diodes in DC-DC Choppers and DC-AC voltage source inverter circuits. This type of period reverse voltage may appear due to “commutation” in a converter. It is given by the manufacturer under the assumption that the supply voltage may rise by 10% at the most.e 10ms for 50 HZ supply).e circuit Breaker opening / closing) or lightning surges.jntuworld. Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of the instantiations reverse voltage appearing periodically across the device. RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) since wave voltage that can be directly applied across the device. Kharagpur 10 www.com Fig 2. The time period between two consecutive appearances is assumed to be equal to half the power cycle (i. A few other important specifications of a power Diode under reverse bias condition usually found in manufacturer’s data sheet are explained below. Fig. Peak Non-Repetitive Reverse Voltage (VRSM): It is the maximum allowable value of the instantaneous reverse voltage across the device that must not recur.www.

(a) Supply voltage wave form. Therefore Vak = Vj + RON IF (2. (b) Reverse i-v characteristics 2.jntuworld. However. At low level of injections (i.6: Reverse Voltage ratings of a power diode.com Fig.e Vak = Vj + VRD (2.jntuworld.e δp << nno) all excess p type carriers recombine with n type carriers in the n. The voltage dropt across a forward conducting power diode has two components i.junction becomes forward biased there will be injection of excess p type carrier into the n.n+ junction with carrier densities δn = δp.n+ junction and attracts electron from the n+ cathode. This leads to electron injection into the drift region across the n. Kharagpur 11 www. This is due to substantial injection of excess carriers from both the p+ and the n+ regions in the drift region as explained next.3) The ohmic drop makes the forward i-v characteristic of a power diode more linear.e large forward current density) the excess p type carrier density distribution reaches the n.drift region. As the metallurgical p+ n. the effective resistance of this region in the ON state is much less than the apparent ohmic resistance calculated on the basis of the geometric size and the thermal equilibrium carrier densities.2) Where Vj is the drop across the p+n.junction and can be calculated from equation (2. However at high level of injection (i. Version 2 EE IIT.3. The component VRD is due to ohmic drop mostly in the drift region.www. 2. It may appear that this lightly doped drift region will offer high resistance during forward conduction.side. Detailed calculation shows (2.com .2 Power Diode under Forward Bias Condition In the previous section it was shown how the introduction of a lightly doped drift region in the pn structure of a diode boosts its blocking voltage capacity. If the width of the drift region is less than the diffusion length of carries the spatial distribution of excess carrier density in the drift region will be fairly flat and several orders of magnitude higher than the thermal equilibrium carrier density of this region.1) for a given forward current jF. This mechanism is called “double injection” Excess p and n type carriers defuse and recombine inside the drift region.3) VRD ∞ JF WD Where JF is the forword current density in the diode and WD is the width of the drift region. Conductivity of the drift region will be greatly enhanced as a consequence (also called conductivity modulation).

com Fig 2. However. Therefore.7: Characteristics of a forward biased power Diode. Maximum Average Forward Current (IFAVM): Diodes are often used in rectifier circuits supplying a DC (average) current to be load. RMS value of the forward current determines the conduction power loss.jntuworld. (b) i-v characteristics. this specification can be used as a guideline for almost all wave shapes of the forward current.www. Kharagpur 12 www.jntuworld. Both Vj and VAK have negative temperature coefficient as shown in the figure. The specification gives the maximum allowable RMS value of the forward current of a given wave shape (usually a half cycle sine wave of power frequency) and at a specified case temperature.com . In such cases the average load current and the diode forward current usually have a simple relationship. Maximum RMS Forward current (IFRMS): Due to predominantly resistive nature of the forward voltage drop across a forward biased power diode. it will be of interest to know the Version 2 EE IIT. (a) Excess free carrier density distribution. Few other important specifications related to forward bias operation of power diode as found in manufacturer’s data sheet are explained next.

Version 2 EE IIT. Fig 2. “Derating curves” provide by the manufacturers give the relationship between IFAVM (IFRMS) with allowable case temperature as shown in Fig. If the case temperature increases beyond this limit these ratings has to be reduced correspondingly. Average Forward Power loss (PAVF): Almost all power loss in a diode occurs during forward conduction state. Average current rating of a diode decreases with reduction in conduction angle due to increase in current “form factor”. Kharagpur 13 www.jntuworld.www.8.jntuworld. average forward current of a power Diode. The forward power loss is therefore an important parameter in designing the cooling arrangement.com maximum average current a diode can conduct in the forward direction.9: Average forward power loss vs.com . 2. Fig 2.8: Derating curves for the forward current of a Power Diode. Both IFRMS and IFAVM ratings are given at a specified case temperature.9. Average forward power loss over a full cycle is specified by the manufacturers as a function of the average forward current (IAVF) for different conduction angles as shown in Fig 2. This specification gives the maximum average value of power frequency half cycle sine wave current allowed to flow through the diode in the forward direction.

A diode is expected to operate normally after the surge duration is over. a fault current is a non repetitive surge current.10: Peak Repetitive surge current VS time curve of a power diode. The diode should be capable of withstanding maximum repetitive peak reverse voltage (VRRM) and Maximum allowable average forward current (IFAVM) following the surge. On the other hand.com . Therefore.4) Peak Non-Repetitive surge current (IFRM): This specification is similar to the previous one except that the current pulse duration is assumed to be within one half cycle of the power Version 2 EE IIT. I FRM \ n = m I \ n FRM m (2. The surge current specification is usually given as a function of the surge duration in number of cycles of the power frequency as shown in figure 2.jntuworld. fault current arising due to some abnormality in the power circuit may have a higher peak valve but exists for shorter duration (usually less than an half cycle of the power frequency).www.com Surge and Fault Current: In some rectifier applications a diode may be required to conduct forward currents far in excess of its RMS or average forward current rating for some duration (several cycles of the power frequency). Peak Repetitive surge current rating (IFRM): This is the peak valve of the repetitive surge current that can be allowed to flow through the diode for a specific duration and for specified conditions before and after the surge. The surge current waveform is assumed to be half sinusoidal of power frequency with current pulses separated by “OFF” periods of equal duration. Power diodes are capable of withstanding both types of surge currents and this capability is expressed in terms of two surge current ratings as discussed next. Kharagpur 14 www.10 Fig 2. This is called the repetitive surge forward current of a diode.jntuworld. The case temperature is usually specified at its maximum allowable valve before the surge. A diode circuit is expected to be disconnected from the power line following a fault. In case the surge current is specified only for a fixed number of cycles ‘m’ then the surge current specification applicable to some other cycle number ‘n’ can be found from the approximate formula.

This specification is also given as a function of the current pulse duration as shown Fig 2. vi. (vi) IFAVM/IFRM. vii.11 Fig.jntuworld. ii. The average current rating of a power diode _______________ with reduction in the conduction angle due to increase in the current ___________________ .jntuworld.www. iv.11. Answer: (i) drift. Kharagpur 15 www.com frequency. (vii) protective fuse. form factor. (v) decrease. (iv) linear.2 (1) Fill in the blanks with the appropriate word(s). Version 2 EE IIT. The reverse breakdown voltage of a Power Diode must be greater than ________________ . Maximum surge current Integral (∫i2dt): This is a surge current related specification and gives a measure of the heat energy generated inside the device during a non-repetitive surge. The ____________ region in a power diode increases its reverse voltage blocking capacity. (ii) free wheeling. v. The derating curves of a Power diode provides relationship between the ______________ and the _________________ . (iii) VRSM. current pulse width characteristics of a power Diode. The maximum DC voltage rating (VRDC) of a power diode is useful for selecting ________________ diodes in a DC-DC chopper. 2 ∫ i dt rating of a power diode is useful for selecting the ________________ . It is useful for selecting the protective fuse to be connected in series with the diode. This specification is given as a function of the current pulse duration as shown in Fig 2. i.11: Non-repetitive surge current and surge current integral vs. The i-v characteristics of a power diode for large forward current is __________ . 2. case temperature. iii. Exercise 2.com .

com (2). Therefore. Hence.www. Will the required VRRM rating change if a inductor is placed between the diode and n capacitor. If the load disconnected the capacitor voltage will not change when the supply goes through its negative peak as shown in the associated waveform. Since there is no discharge path for the capacitor this voltage across the capacitor will be maintained when the supply voltage goes through negative peak. the diode will be subjected to a reverse voltage greater than the peak to peak supply voltage.com . Also find the i2t rating of the protective fuse to be connected in series with the diode. The source of the single phase rectifier circuit has an internal resistance of 2 Ω. Kharagpur 16 www. The required VRRM rating will increase.jntuworld. Answer: (a) During every positive half cycle of the supply the capacitor charges to the peak value of the supply voltage. If the load is disconnected the stored energy in the inductor will charge the capacitor beyond the peak supply voltage.jntuworld. Version 2 EE IIT. Find out the required Non repetitive peak surge current rating of the diode. Assume a resistive load. What will be the required VRRM rating if the capacitor is removed. (a) (b) (c) (d) For the single phase half wove rectifier shown find out the VRRM rating of D. Therefore the diode will be subjected to a reverse voltage equal to the peak to peak supply voltage in each cycle. the required VRRM rating will be VRRM = 2 × 2 × 230V = 650V (b) When an inductor is connected between the diode and the capacitor the inductor current will have some positive value at t = t1.

So the required VRRM rating will be VRRM = 2 × 230V = 325 Volts (d) Peak surge current will flow through the circuit when the load is accidentally short circuited. The rate of rise of the forward current through the diode during Turn ON has significant effect on the forward voltage drop characteristics. Therefore the maximum i2t rating of the fuse is ∫i 2 dt M ax = ∫ π o I 2 F S M S in 2 w td w t = π 2 I 2 F S m = 4 1 . Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt limiting inductors. Kharagpur 17 www.com .jntuworld.3 Switching Characteristics of Power Diodes Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch ON) and vice versa (switch OFF). At high switching frequency this may contribute significantly to the overall power loss in the diode. the protective fuse (to be connected in series with the diode) must blow during the negative half cycle following the fault. Voltage and current exist simultaneously during switching operation of a diode.com (c) If the capacitor is removed and the load is resistive the voltage VKN during negative half cycle of the supply will be zero since the load current will be zero.3. Therefore.jntuworld. • • Severe over voltage / over current may be caused by a diode switching at different points in the circuit using the diode. Therefore. Version 2 EE IIT. 2.5 5 × 1 0 3 A 2 s e c 2. Therefore the reverse voltage across the diode will be equal to the peak supply voltage.12. every switching of the diode is associated with some energy loss. Behavior of the diode current and voltage during these switching periods are important due to the following reasons. The peak surge current rating will be 2 × 230 I FSM = A = 162.www. A typical turn on transient is shown in Fig.64 A 2 The peak non repetitive surge current should not recur.

jntuworld. It is observed that the forward diode voltage during turn ON may transiently reach a significantly higher value Vfr compared to the steady slate voltage drop at the steady current IF.12: Forward current and voltage waveforms of a power diode during Turn On operation.com Fig. Observed Turn OFF behavior of a Power Diode: Figure 2.www. Version 2 EE IIT. Typical values lie within the range of 10-30V. In some power converter circuits (e. 2.jntuworld. Vfr (called forward recovery voltage) is given as a function of the forward di/dt in the manufacturer’s data sheet. Kharagpur 18 www.g voltage source inverter) where a free wheeling diode is used across an asymmetrical blocking power switch (i.13 shows a typical turn off behavior of a power diode assuming controlled rate of decrease of the forward current. Forward recovery time (tfr) is typically within 10 us.e GTO) this transient over voltage may be high enough to destroy the main power switch.com .

Other parameters are interrelated and also depend on S. Also in high frequency switching circuits (e.com .com Fig. reverse recovery time (trr). inverters) this reverse current flows through the main power switch in addition to the load current. inverters) this may create an effective short circuit across the supply. It may be required to protect the diode using an RC snubber. Manufacturers usually specify these parameters as functions of diF/dt for different values of IF. peak reverse recovery current (Irr).jntuworld. Of these parameters. choppers. Towards the end of the reverse recovery period if the reverse current falls too sharply. In many power electronic circuits (e. drift region width.). Therefore.g. doping lever.13: Reverse Recovery characteristics of a power diode Salient features of this characteristics are: • The diode current does not stop at zero. this reverse recovery current has to be accounted for while selecting the main switch. reverse recovery charge (Qrr) and the snappiness factor S. At high switching frequency this may result in considerable increase in the total power loss. (low value of S). In many power electric circuits (choppers. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF and decreases with diF/dt. carrier life time etc. Voltage drop across the diode does not change appreciably from its steady state value till the diode current reaches reverse recovery level. 2.www. • • During the period t5 large current and voltage exist simultaneously in the device. current being limited only by the stray wiring inductance. Version 2 EE IIT.g. stray circuit inductance may cause dangerous over voltage (Vrr) across the device. Important parameters defining the turn off characteristics are. the snappiness factor S depends mainly on the construction of the diode (e. SMPS) if the time period t4 is comparable to switching cycle qualitative modification to the circuit behavior is possible. instead it grows in the negative direction to Irr called “peak reverse recovery current” which can be comparable to IF.g. Kharagpur 19 www.jntuworld.

While this is acceptable for line frequency rectifiers (these diodes are also called rectifier grade diodes) high frequency circuits (e. thereby.13 is typical of a particular type of diodes called “normal recovery” or “soft recovery” diode (S>1).jntuworld. Here the current flowing through Ll at the time of diode current “snapping” is bypassed to Cs. The problems with this approach are: i) Increase of diF/dt also increases the magnitude of Irr ii) Large recovery current coupled with ”snappy” recovery may give rise to current and voltage oscillation in the diode due to the resonant circuit formed by the stray circuit inductance and the diode depletion layer capacitance. The total recovery time (trr) in this case is a few tens of microseconds.Rs & Cs forms a damped resonance circuit and the initial energy stored in Ll is partially dissipated in Rs. A typical recovery characteristics of a “snappy” recovery diode is shown in Fig 2. if the drift Version 2 EE IIT.g PWM inverters.14: Diode overvoltage protection circuit.www. Fig. Ll.14 (b) may to used to restrict Vrr. comes at the expense of the steady state performance.14(c).14 (a). Fast recovery diodes offer significant reduction in both Irr and trr (10% . It can be shown that the forward voltage drop in a diode is directly proportion to the width of the drift region and inversely proportional to the carrier life time in the drift region. Therefore. On the other hand.jntuworld. This improvement in turn OFF performance. (b) Capacitive snubber circuit.e. by reducing stray circuit inductance) and by using “snappy” recovery (S<<1) diode.com The reverse recovery characteristics shown in Fig. 2. 2. restricting Vrr . Also snubber circuits increase the overall power loss in the circuit since the energy stored in the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode. On the other hand both Irr and trr increases with increase in carrier life time and drift region width. Therefore if Irr and trr are reduced by reducing the carrier life time. in high frequency circuits other types of fast recovery diodes (Inverter grade) are preferred. Large reverse recovery current may lead to reverse voltage peak (Vrr) in excess of VRSM and destroy the device. it is difficult to correctly estimate the value of Ll and hence design a proper snubber circuit. SMPS) demand faster diode recovery. (a) “Snappy recovery characteristics.20% of a rectifier grade diode of comparable rating). however. Normalized values of Vrr as a function of the damping factor ξ with normalized Irr as a parameter is shown in Fig. Diode reverse recovery time can be reduce by increasing the rate of decrease of the forward current (i. 2.com . 2. However. Kharagpur 20 www. (c) snubber characteristics. A capacitive protection circuit (also called a “snubber circuit) as shown in Fig. forward voltage drop increases.

law. Turn Off. The magnitude of the forward recovery voltage also depends on the _______________ of the diode forward current. vi.jntuworld. iii.www. x. (vii) large. some increase in the forward voltage drop in the diode (and hence conduction power lass) can be tolerated since the Turn OFF loss associated with reverse recovery is greatly reduced. On state voltage drop is also less compared to a p-n junction diode for equal forward current densities. (ix) low. A fast recovery diode has _______________________ reverse recovery current and time compared to a __________________ recovery diode. improvement in the reverse recovery performance offered by normal fast recovery diode is not sufficient. Kharagpur 21 www. If the required reverse blocking voltage is less (<100v) schottky diodes are preferred over fast recovery diodes. In the buck converter shown the diode D has a lead inductance of 0. In some very high frequency applications (fsw >100KHZ). (vi) decreases. The reverse recovery charge of a power diode increases with the _______________ of the diode forward current. 2. reverse breakdown voltage of these diodes are less (below 200V) Power schottky diodes with forward current rating in excess of 100A are available. The magnitude of the forward recovery voltage is typically of the order of few ______________ of volts. A Schottky diode has _______________ forward voltage drop and ______________ reverse voltage blocking capacity.com region width is reduced the reverse break down voltage of the diode reduces. viii. (iv) magnitude. For a given forward current the reverse recovery current of a Power Diode ______________ with the rate of decrease of the forward current. Compared to p-n junction diodes schottky diodes have very little Turn OFF transient and almost no Turn ON transient. (viii) lower. Schottky diodes have no __________________ transient and very little _________________ transient. Fill in the blanks with appropriate word(s) i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region of a power diode in the beginning of the Turn On process. However.3 1. Answer: (i) drift. Version 2 EE IIT. Find peak current through Q. (v) increases. v. A “snappy” recovery diode is subjected to _________________ voltage over shoot on recovery. In high voltage high frequency circuits switching loss is the dominant component of the overall power loss. For a given forward current the reverse recovery time of a Power diode ______________ with the rate of decrease of the forward current. iv. a compromise between the steady state performance and the switching performance.jntuworld. vii.com . Exerciser 2. Therefore.2μH and a reverse recovery change of 10μC at iF =10A. (ii) tens. (x) Turn On. The performance of a fast recovery diode is therefore. ii. ix. (iii) rate of rise.

2 × 1 0 -6 Assuming a snappy recovery diode (s ≈ o) Q rr = 1 ∴ t rr = 1 .com Answer: Assuming iL=10A (constant) the above waveforms can be drawn As soon as Q is turned ON. ∴ diF 20 = A S ec = 10 7 A S ec dt .jntuworld. 4 1 4 μ s ∴ I rr = diF dt 2 I rr t rr = 1 ⎛ diF ⎞ 2 ⎜ ⎟ t rr 2 ⎝ dt ⎠ = 1 0 × 1 0 -6 C t rr = 1 4 . 1 4 A ∴i Q peak =I L +I rr = 24.jntuworld.14 A Version 2 EE IIT. a reverse voltage is applied across D and its lead inductance. Kharagpur 22 www.www.com .

Robbins. Kharagpur 23 www. 1991. “Power Electronics” Tata McGraw Hill Publishing Company Limited. New Delhi. Ned Mohan. Third Edition 2003. Tata McGraw-Hill Publishing Company Limited.jntuworld. Converters. 1987. “Power Electronics. Version 2 EE IIT. Halkias.com . Publishers. C. Jacob Millman. P. Undeland. William P. Sen. Tore M.com References 1. Christos C. “Integrated Electronics. Application and Design” John Wiley & Sons(Asia).www. 2. 3. New Delhi.jntuworld. Analog and Digital Circuits and Systems”.

A power diode incorporates a lightly doped drift region between two heavily doped p type and n type regions. Normal or slow recovery diodes have smaller reverse recovery current but longer reverse recovery time.www. For continuous forward biased operation the RMS value of the diode forward current should always be less than its rated RMS current at a given case temperature. During “Turn Off” the diode current goes negative first before reducing to zero. uncontrolled switching device.com Module Summary • • • • • • • • • A p-n junction diode is a minority carrier. rate of decrease of the forward current and the type of the diode. A power diode should never be subjected to a reverse voltage greater than the reverse break down voltage. They are suitable for line frequency rectifier operation. The i-v characteristics of a forward biased power diode is comparatively more linear due to the voltage drop in the drift region. The total time for which the diode current remains negative during Turn Off is called “the reverse recovery time” of the diode.jntuworld. During “Turn On” the instantaneous forward voltage drop across a diode may reach a level considerably higher than its steady state voltage drop for the given forward current.wheeling operation. Fast recovery diodes have faster switching times but comparatively lower break down voltages. This is called reverse recovery of a diode. The forward voltage drop across a conducting power diode depends on the width of the drift region but not affected significantly by its doping density. A diode can not block reverse voltage till the reverse current through the diode reaches its peak value. Fast recovery diodes need to be protected against voltage transients during Turn Off” using R-C snubber circuit. They are suitable for high frequency rectifier or inverter free. Both the “reverse recovery current” and the “reverse recovery time” of a diode depends on the forward current during Turn Off. • • • • • • • • Version 2 EE IIT. The peak negative current flowing through a diode during Turn Off is called the “reverse recovery current” of the diode. This is called forward recovery voltage. unidirectional.com .jntuworld. Kharagpur 24 www. Surge forward current through a diode should be less than the applicable surge current rating. Maximum reverse voltage withstanding capability of a power diode depends on the width and the doping level of the drift region.

jntuworld.www.com .jntuworld. They are suitable for low voltage very high frequency switching power supply applications. Version 2 EE IIT. Kharagpur 25 www.com • Schottky diodes have lower forward voltage drop and faster switching times but comparatively lower break down voltage.

com .www.jntuworld.jntuworld.com Practice Problems and Answers Version 2 EE IIT. Kharagpur 26 www.

5 mΩ. Find the IFRMS and VRRM ratings of DI & DF. The dc resistance of the diode is 2.www. C is initially charged to 200 V with polarity as shown. 2. 4. Find out Irr & trr for DI. (Assume S = 1 for DI). Kharagpur 27 www. In the voltage commutated chopper of Problem 5 the voltage on C reduces by 1% due to reverse recovery of DI. 5. VT = k T q = 26 m v at 32 o C 3. What precaution must be taken regarding the forward recovery voltage of the free wheeling diodes in a PWM voltage source inverter employing Bipolar Junction Transistors of the n-p-n type? Version 2 EE IIT. Assume that the maximum junction temperature is restricted to 102°C.com Practice Problems (Module-2) 1. If a number of p-n junction diodes with identical i-v characteristics are connected in parallel will they share current equally? Justify your answer.com .jntuworld. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ.jntuworld. Find the forward voltage drop and power loss for a forward current of 200 Amps. A power diode have a reverse saturation current of 15μA at 32°C which doubles for every 10° rise in temperature.

9 2 m A ∴ Vt at 102 o = 31.www. If follows then (from Eqn. 2. Therefore. However. the total voltage drop across the diode is VD = VR + V j = 0. The voltage drop across that particular diode will decrease as a result and more current will be diverted towards that diode.jntuworld.com . in general. Since the reverse saturation current double with every 10°C rise in junction temperature.5V Therefore. Kharagpur 28 www. If due to some transient disturbance the current in a diode increases momentarily the junction temperature of that diode will increase due increased power dissipation. equal current sharing can be forced by connecting suitable resistances in series with the diodes so that the total resistance of each branch has positive temperature coefficient. The reverse saturation current of a p-n junction diode increases rapidly with temperature.1) the voltage drop across a diode for a given forward current decreases with increase in temperature.jntuworld. In other words if the volt ampere characteristics of a diode is modeled as a non linear (current dependent) resistant it will have a negative temperature coefficient.com Answers to Practice Problems 1. share current equally even if it is assumed that they have identical i-v characteristics.87V Version 2 EE IIT.97mv Vt = KT = 26mv at 32 o C q ∴ V j fo r i F = 2 0 0 A is V j = Vt 102 C o × ln iF Is 102o C = 0 . This “positive feedback mechanism” will continue to increase its current share till parasitic lead resistance drop becomes large enough to prevent farther voltage drop across that diode. 2. it can be concluded that a number of p-n junction diodes conned in parallel will not. Let us now consider the situation where a number of diodes are connected in parallel. Is 102o C = 2 1 0 2 -3 2 10 × Is 32o C = 1 .3 7 V Voltage drop across drift region VR = iF ×RD = 0.

jntuworld. Important wave forms of the system are shown in the figure.com 3.jntuworld. The current idi is given by i D I = I D IP S in ω n w here I D IP = 200 C L 0 ≤ ωn ≤ 7 = 89.44 A & ωn = 1 = 22.www. Kharagpur 29 www. As soon as T is turned ON the capacitor voltage starts reversing due to the L-C resenant circuit formed by C-T-L & DI.com .36×103 LC Version 2 EE IIT. Neglecting all the capacitor voltage reaches a -200V.

www.com ∴ Capacitor voltage reversal time = Tn 1 π = = = 140μs.94 Am ps 5.01× C × 200 = 40μc w ith S = 1 Q rr = I rr t rr = d i dI t rr 2 dt Now id I = I DIP Sin ω n t ∴ di dI = ω n I D IP C osω n t dt at ω n t = π. Kharagpur 30 www. di dI = ω n I DIP = dt 1 C . Since the Capacitor voltage reduces by 1% Q rr = 0. 2 2 fn ωn Capacitor voltage remains at -200 V till TA is turned ON when it is charged linearly towards +200 V.jntuworld.472 μs ∴ I rr = 8.58 Amps 5000 2100 = 12.96 Amps 5000 From figure VRRM for D I is 200 V VRRM for D F is 400 V 4. ∴ I FRMS For D I is I FRMS For D F is I DIP 2 20 140 = 10. Figure shows one leg of a PWM VSI using n-p-n transistor and freewheeling diode. Time taken for charging is TC = 2 × 200 × C = 400μs IL At the end of charging DF turns ON and remains on till T is turned on again.com . 200 = 2A μs L LC ∴ t rr 2 = 20 ×10-12 sec 2 or t rr = 4. Version 2 EE IIT.jntuworld.

com .jntuworld. Version 2 EE IIT. Therefore.www. The forward recovery voltage of D1 appears as a reverse voltage across the n-p-n transistor whose base emitter junction must with stand this reverse voltage. Kharagpur 31 www. the forward recovery voltage of the free wheel diodes must be less them the reverse break down voltage of the baseemitter junction of the n-p-n transistors for safe operation of the inverter.jntuworld.com Consider turning off operation of Q1. As the current through Q1 reduces D1 turns On.

www.jntuworld. Kharagpur 1 www.jntuworld.com .com Module 1 Power Semiconductor Devices Version 2 EE IIT.

jntuworld.www.jntuworld.com . Kharagpur 2 www.com Lesson 3 Power Bipolar Junction Transistor (BJT) Version 2 EE IIT.

Operating Principles. Distinguish between. and saturation region operation of a Bipolar Junction Transistor. Design a BJT base drive circuit.jntuworld. Draw and explain the Turn On characteristics of a BJT. Objective: On completion the student will be able to 1. 3. 10. Calculate switching and conduction losses of a Power BJT. Interpret manufacturer’s data sheet ratings for a Power BJT. cut off. 2. Draw the output characteristics of a Power BJT and explain the applicable operating limits under Forward and Reverse bias conditions. active. Differentiate between the characteristics of an ideal switch and a BJT. Draw and explain the Turn Off characteristics of a BJT. List the salient constructional features of a power BJT and explain their importance. Draw the input and output characteristics of a junction transistor and explain their nature. 8. Characteristics and specifications of Power Bipolar Junction transistors. 9. Kharagpur 3 www. 4.com Constructional Features. Version 2 EE IIT.www. 7.com .jntuworld. 5. 6.

They have. This is called an n-p-n transistor.com 3. From the point of view of construction and operation BJT is a bipolar (i. Base (B) & Collector (C) as shown in the figure. Hence. almost completely replaced BJTs. The terminals of a transistor are called Emitter (E).com .1 shows the circuit symbols and schematic representations of an n-p-n and a p-n-p transistor.jntuworld. operating principle and characteristics of a Power BJT will be explored.2 Basic Operating Principle of a Bipolar Junction Transistor A junction transistor consists of a semiconductor crystal in which a p type region is sandwiched between two n type regions. the construction. However.1 Introduction Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its Turn on and Turn off operations. However. the construction and operating characteristics of a Power BJT differs significantly from its signal level counterpart due to the requirement for a large blocking voltage in the “OFF” state and a high current carrying capacity in the “ON” state. minority carrier) current controlled device.e.jntuworld. It has been used at signal level power for a long time. Alternatively an n type region may be placed in between two p type regions to give a p-n-p transistor. Fig 3. VCE VCE E (p) iE VBE RC VBB iB B (n) C (p) iC RC iE E (n) VBE iB B (p) VBB RB C (n) + i C VCC VCC Version 2 EE IIT.www. Kharagpur 4 www. Many of them have superior performance compared to the BJT in some respects. Subsequently. Other “transistors” have characteristics that are qualitatively similar to those of the BJT (although the physics of operation may differ). It simplified the design of a large number of Power Electronic circuits that used forced commutated thyristors at that time and also helped realize a number of new circuits. it should be emphasized that the BJT was the first semiconductor device to closely approximate an ideal fully controlled Power switch. 3. it will be worthwhile studying the characteristics and operation a BJT in some depth. many other devices that can broadly be classified as “Transistors” have been developed. In this module. by now.

If no external biasing voltages are applied (i. It is clear from the diagram that p type carriers in the base region of an n-p-n transistor are trapped in a “potential well” and cannot escape.com . Similarly. 3. ΒΕ O O Corresponding depletion layer widths will be WBE and WCB . (a) n – p – n transistor .jntuworld. n A for n-p-n pB Version 2 EE IIT.1 ( PnE .1: Bipolar junction transistor under different biasing condition.e. WCB ) . (b) p – n – p transistor.jntuworld. When biasing voltages are applied as shown in the figure. 3.com (Emitter) n (E) (Base) p (B) (Collector) n (C) (Emitter) n (E) (Base) p (B) (Collector) n (C) S WBE S φBE 0 φBE S φCB A φCB 0 φBE S φ φBE A BE A φCB 0 φCB φ A BE W A WBE 0 WBE S CB 0 φCB x A WBE W S CB S WBE A WCB S φCB x 0 WCB A WCB 0 WBE 0 WCB JBE nS pB JCB JBE pS nB JCB pS nE pA nE n poB p noE n A pB pS nC p noC nS pE nA pE p noB nS pC n poE p A nB p A nC n poC nA pC x x (a) (b) Fig. Kharagpur 5 www. Potential barrier Α A and depletion layer width at JBE reduces to φΒΕ and WBE respectively. VBB and VCC are open circuited) all transistor currents must be zero. in a p-n-p transistor p type carriers in the emitter and collector regions are separated by a “potential hill”.www.. As the potential barrier at JBE is reduced a large number of minority CB A carriers are introduced in to Base and the Emitter regions as shown in Fig. Both these quantities A increase at JCB ( φA . The transistor will be in thermal equilibrium condition with potential o barriers φο and φCB at the base emitter and the base collector functions respectively. the base emitter junction (JBE) becomes forward biased where as the base collector junction is reverse biased.

B When a biasing voltage VBB of appropriate polarity is applied across the junction JBE the potential barrier at this junction reduces and at one point the junction becomes forward biased. 3.com . Similar explanation applies to a p-n-p transistor.www. however have some effect on this characteristic. in a normal transistor the emitter is much more heavily doped compared to the base the current crossing JBE is almost entirely determined by the excess minority carrier distribution in the base. Therefore iB for a given VBE reduces with increasing VCE as shown in Fig.1 by variables with a super script “s”. Kharagpur 6 www. the potential barrier at JCB starts reducing. Therefore. The effective base width thus reduces. 3. Under this condition the transistor is said to be in the saturation region.jntuworld. Under this condition the transistor is said to be in the Active region. The rest. 3. In the following section these characteristics of an n-p-n transistor will be discussed qualitatively. As VBE is increased injected minority charge into the base region increases and so does the base current and the collector current. The total voltage drop between collector and emitter will be the difference between the forward bias voltage drops at JBE and JCB. it can be concluded that the relationship between iB and VBE will be similar to the i-v characteristics of a p-n junction diode. From the operating principle described above one can form a qualitative idea about the input (iB vs VBE) and output (iC Vs VCE) characteristics of a transistor. Thus. p A for p-n-p transistor). VCE. These minority carriers constitute the major component of the total collector current. the voltage VCB reduces with increase in collector current due to increasing drop in the external resistance RC. Since.jntuworld.2(a). The current crossing this junction is governed by the forward biased p-n junction equation for a given collector emitter voltage. At one point JCB becomes forward biased. The base current iB is related to the recombination of minority carriers injected into the base from the emitter.2) Version 2 EE IIT. The potential barriers and depletion layer widths under this condition are indicated in Fig. The other component of the collector current consists of the small reverse saturation current of the reverse biased junction JCB. defuse to the edge of the depletion region at JCB where they are swept away to the collector region by the large electric field. For a fixed collector bias voltage VCC. The rate of recombination is directly proportional to the amount of excess minority carrier stored in the base. reducing the rate of recombination in the base region and hence the base current.1. Due to forward biasing of JCB there will be minority carrier injection into the base from this junction also as shown in Fig. As VCE increases reverse bias of JCB increases and the depletion region at JCB moves deeper into the base. A portion of the minority carriers reaching the base pE nB recombines with majority carriers.com transistor and n A . B B B It has been mentioned before that only a fraction (denoted by the letter “∝”) of the total minority carriers injected into the base reaches junction JCB where they are swept in to the collector region by the large electric field at JCB.1) (3. Therefore IC = ∝IE + Ics Where Ics is the reverse saturation current of junction JCB But IE = IB + IC B (3.

ICS is . At one point the junction JCB becomes forward biased. VCE reduces with increasing iC due to increased drop in an external load (i. B B Version 2 EE IIT.2 (a)). 3.3) (3. In saturation iC is almost entirely determined by the external load and further increase in iB changes iC or VCE very little.e.com ∴ IC = β By defining IC = βIB + (β+1) Ics ∝ 1− ∝ ICS ∝ + IB 1. From equation (3. The transistor is said to be in the “cut off” region under this condition. This is expected because with increasing VCE a larger value of VBE will be required to maintain a given iB (Fig.4) it will be expected that the collector current should increase proportionately independent of VCE.1).for all practical purpose.4) β is called the large signal common emitter current gain of the transistor and remains fairly constant for a large range of IC.∝ (3. base current starts flowing.jntuworld. With VBB = 0 or negative there is little injected minority carrier into the base from the emitter side. Fig: 3 (b) shows the complete out put characteristics (ic vs VCE) of an n-p-n transistor. 3.jntuworld.www. This is when the transistor enters the saturation mode of operation.com .∝ 1. Kharagpur 7 www.2 (b) does indicate a slight increase in iC with VCE for a given iB..2 (c). the component “∝IE” of collector current will increase. B As VBB is increased from zero. Therefore. as shown in Fig. However Fig 3. Therefore. Rc in Fig 3. This is the active or “amplifier mode” of operation of a transistor. iB = 0 and iC is negligibly small. The ratio iC/iB at the onset of saturation is called βMin and is an important parameter for a power transistor. For a given value of VCC. B B In the active region as iB increases iC also increases. VCE. independent of VCE. now is just the difference between the voltages across two forward biased junction JBE and JCB (a few handed milli volts).

e) When both B-E & C-B junction of a BJT are forward biased it is said to be in the _______________ region.1 Fill in the blank(s) with the appropriate word(s) a) Under forward bias condition a large number of ___________________ carriers are introduced in the base region.2: Input and output characteristics of an n – p – n transistor.jntuworld.com .com iC Saturation iB vCE increasing vBE iB6 iB5 iB4 iB3 Active iB2 iB1 iB = 0 Cut off iB increasing vCE (a) β (b) (c) Fig. (c) Current gain[β] characteristics Exercise 3. (a) Input characteristics.jntuworld.www. Version 2 EE IIT. b) Some minority charge carriers reaching base __________________ with majority carriers there and the rest of them ___________________ to the collector. (b) Output characteristics. d) When both B-E & C-B junction of a BJT are reverse biased it is said to be in the _________________ region. 3. c) When the base-emitter junction of a BJT is forward biased while the base-collector junction is reverse biased the BJT is said to be in the _______________ region. Kharagpur 8 www.

www. In order to maintain a large current gain “β” (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. In order to block large voltage during “OFF” state a lightly doped “collector drift region” is introduced between the moderately doped base region and the heavily doped collector region. Thus. Therefore. for a constant base current the number of minority carriers in the base region will increase and consequently.3 Constructional Features of a Power BJT Power transistors face the same conflicting design requirements (i.3 A power BJT has IC = 20 A at IB = 2. Therefore. (c) active. Kharagpur 9 www. However.3(a). the doping density donation of the base region being “moderate” the depletion region does penetrate considerably into the base. Answer: In the active region as the VCE voltage is increased the depletion layer width at the CB junction increases and the effective base width reduces. (e) saturation. 3.jntuworld. Exercise 3. The thickness of the base region is also made as small as possible. Therefore. Exercise 3. B B ∴ β = 7. the width of the base region in a power transistor can not be made as small as that in a signal level transistor. diffuse. Since Power Transistors are predominantly of the n-p-n type. (b) recombine. (d) cut-off.com Answer: (a) minority.5 A.com . it is only natural to extend some of the constructional features of power diodes to power BJT. collector current will increase. Ics = 15 mA. for a given VBE recombination of minority carriers in the base region reduces and base current also reduces. VBE must increased. B Answer: Ic = β IB + (β + 1) Ics = β( IB + Ics) + Ics.2 Why does the collector current of a BJT in the active region increases with increasing collector voltage for a given base current. The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows.e.jntuworld. Find out β & ∝. The function of this drift region is similar to that in a Power Diode. • A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 3. In order to main constant base current with increasing VCE. This comparatively larger base width has adverse effect on the current gain (β) of a Power transistor which • • Version 2 EE IIT. in this section and subsequently only this type of transistor will be discussed.95. on state resistance and power lass is minimized. large off state blocking voltage and large on state current density) as that of a power diode. Therefore. Following Section summarizes some of the constructional features of a Power BJT.

Kharagpur 10 www. As will be discusses later the collector drift region has significant effect on the out put characteristics of a Power BJT.(Collector Drift) n+ (Collector) (a) Collector contact Version 2 EE IIT. • Practical Power transistors have their emitters and bases interleaved as narrow fingers.www. Emitter contact Base contact n+ (emitter) n+ p (Base) n+ n.3 (b) shows the photograph of some community available Power transistors in different packages.3.jntuworld.com . Fig.jntuworld. These constructional features of a Power BJT are shown schematically in Fig 3.3(a). This is necessary to prevent “current crowding” and consequent “second break down”.com typically varies within 5-20. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path.

In fact output characteristics of a Version 2 EE IIT.com . 3. Moderately doped base regain of relatively larger width tend to reduce the dc current gain.4 A power transistor exhibits “Cut off”. The base width in a power transistor cannot be reduced below a certain level in order to avoid “reach through” of the base region under large applied voltage. narrow finger like distributed emitter structure is used to avoid emitter ___________________. “Active” and “Saturation regions” of operation in its output characteristics similar to a signal level transistor.4 Fill in the blank(s) with the appropriate word(s) a) Doping density of the emitter of a Power BJT is several orders of magnitude ______________ than the base doping density. (e) current crowding. Exercise 3. (d) low. (b) high reverse. Kharagpur 11 www. b) Collector drift region is introduced in a Power BJT to block _______________ voltage. e) In a Power BJT multiple. c) Doping density of the base region in a power BJT is ________________.4 Output i-v characteristics of a Power Transistor A typical output (iC vs VCE) characteristics of an n-p-n type power transistor is shown in Fig 3. (b) Photograph of commercial packages. narrow emitter regions distributed uniformly over the entire device cross section also tends to improve dc current gain by minimizing “current crowding”. Answer: (a) higher.3: Constructional Features of a Power Bipolar Junction Transistor (a) Schematic of Construction.jntuworld.5 What are the constructional features of a power transistor that affect the dc current gain? • • • Large doping density of the emitter increases dc current gain.jntuworld.www. (c) moderate. d) Power BJT has ________________ DC current gain compared to signal level transistors. Multiple. Exercise 3. 3.com (b) Fig.

www. Certain quantitative restrictions apply. Therefore. iC Hard Saturation Quasi Saturation iB10 iB9 iB8 iB7 iB6 iB5 iB4 iB3 iB2 iB1 iB ≤ 0 Cut off ϑCE Second break down limit Active Total Power dissipation limit Increasing iB Primary break down voltage VSUS VCB0 VCE0 (iB = 0) (iB < 0) Fig.com Power Transistor in the “Cut off” and “Active” regions are qualitatively identical to a signal level transistor.4 Output ( ic – vCE ) characteristics of an n – p – n type Power Transistor In the cut off region (iB ≤ 0) the collector current is almost zero. This graph is useful for designing the base drive of a Power transistor. This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case iB < o. since the open base configuration is more common the value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor. which are discussed next. Manufacturers usually provide a graph showing the variation of β as a function of the collector current for different junction temperatures and collector emitter voltages. Typically. B B B In the active region the ratio of collector current to base current (DC current Gain (β)) remains fairly constant upto certain value of the collector current after which it falls off rapidly. However. Kharagpur 12 www. however. reverse voltage (C negative with respect to E) should not appear across a power transistor. 3. For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with iB = 0. Version 2 EE IIT.jntuworld.jntuworld.com . the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the base-emitter junction. The maximum voltage between collector and emitter under this condition is termed “Maximum forward blocking voltage with base terminal open (iB = 0)” and is denoted by VCEO. Actually VCBO is the breakdown voltage of the collector base junction.

At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called “the Second Break down”.4. Kharagpur 13 www. In the hard saturation region base current looses control over the collector current which is determined entirely by the collector load and the biasing voltage VCC.com . B B Version 2 EE IIT. The resistivity of this region depends to some extent on the base current. It is in the saturation region that the output characteristics of a Power transistor differs significantly from its signal level counterpart. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of “current filamements” (localized areas of very high current density) by a positive feed-back mechanism. Therefore. Therefore. Also. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. This voltage. In the quasi saturation region the base-collector junction is forward biased but the lightly doped drift region is not completely shorted out by excess minority carrier injection from the base.jntuworld. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base). in the quasi saturation region. B Applicable operating limits on a power transistors are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. Typical safe operating areas of power transistors are shown in Fig 3.jntuworld. denoted by VSUS in Fig. since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given collector current compared to what it will be in the hard saturation region.5.www.com The maximum collector-emitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. Curves showing the variation of VCE (sat) with iB for different values of iC and junction temperature are also provided by certain manufacturers. The voltage VSUS can be attained only for relatively lower values of collector current.4 is usually smaller than VCEO. It appears on the output characteristics of the BJT as a precipitous drop in the collector-emitter voltage at large collector currents. the base current still retains some control over the collector current although the value of β decreases significantly. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. At higher collector current the limit on the “total power dissipation” defines the boundary of the allowable active region as shown in Fig 3. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. iC for different values of base current and junction temperature. Once current filaments are formed localized “thermal runaway” quickly takes the junction temperature beyond the safe limit and the device is destroyed. 3. Manufacturers usually provide the plots of the variation of VCE (sat) vs. for larger collector currents the collector-emitter voltage drop is almost proportional to the collector current. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor.

Kharagpur 14 www. However. It shows the limiting combinations of collector voltage and current so that second break down does not occur.jntuworld. The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature.com iC ICM 10-5sec 10-4sec 10-3sec 10-2sec DC (a) iC ICM Log ϑCE VSUS (b) ϑCE VCB0 VCE0 (VBE = 0) (VBE < 0) Fig. On the other hand the pulsed power dissipation limits are applicable to conduction duration up to the value marked on them (the figures on the right of Fig 3. Pulsed power dissipation limits are specified for a low value (1%-2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will be seen later. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. the rms value of the collector current waveform should not exceed this limit. This limit is different for dc and pulsed operation due to the thermal time constant of the device. On the log –log scale of the FBSOA this limit also appears as a straight limit.www. The “DC” limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active.5: Safe operating areas of a Power Transistor. the second break down limit is also different for “DC” and “Pulsed” operation of different pulse durations.com . The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of a Power transistor. (b) RBSOA.jntuworld. Since FBSOA is shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. for some reason is not dc or a pulse. quasi saturation or saturation). Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail.5 (a)) corresponding to a particular limit is also same. (a) FBSOA. The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS Version 2 EE IIT. The interpretation of the pulse duration (marked on the right side of Fig 3. 3. if the collector current. The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Like the maximum power dissipation limit.5 (a)).

e. Exercise 3. It essentially shows the limiting permissible combinations of VCE & iC with base emitter junction reverse biased. 3. the operating Version 2 EE IIT. c) Saturation region of a Power Transistor can be divided into _______________ region and ______________________ region. Typical specifications that are provided are VEBO : This is maximum allowable reverse bias voltage across the B-E junction IB B : Maximum allowable average base current at a given case temperature. hard saturation. (d) Power dissipation. b) In the __________________ region of a Power Transistor the dc current gain remains fairly constant. Both the maximum power dissipation limit and the second break down limits are to be derated as per the derating characteristics provided by the manufacturers when the case temperature exceeds the specified value.e. (b) active. However. Answer: (a) negligible. e) “Second breakdown” in a Power BJT occurs due to ________________ of the collector current distribution.jntuworld. the RBSOA (Fig 3. it operates in either “cut off” (switch OFF) or saturation (switch ON) regions.com The FBSOA of a Power transistor is given at a specified case temperature. limiting specification with respect to the base emitter junction is also provided by the manufacturer. If the base terminal is open (i. RBSOA is a switching SOA since a transistor can not conduct current for any appreciable duration under reverse biased condition. : Maximum allowable peak base current at a given case temperature and of specified pulse duration. iB = 0) then this voltage is VCEO. (e) non uniformity. The right hand side vertical limit corresponds the avalanche break down voltage of the transistor with reverse bias.com . B In addition to the applicable limits on the output characteristics as represented in the FBSOA and the RBSOA. B IBM The input characteristics (iB Vs VBE) at a given case temperature is also provided. d) Active region operation of a Power BJT is limited mostly by _______________ consideration. (c) Quasi saturation.5 Switching characteristics of a Power Transistor In a power electronic circuit the power transistor is usually employed as a switch i. In contrast to the FBSOA. If a negative voltage is applied across the BE junction the right hand side limit of the RBSOA increases somewhat to the value VCBO at low value of the collector current.6 Fill in the blank(s) with the appropriate word(s) a) In the “Cut off” region collector current of a Power Transistor is _____________.www.jntuworld.5 (b)) is plotted on a linear scale and has a more rectangular shape. The upper horizontal limit corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA. Kharagpur 15 www.

leakage current. • • • • • • It can conduct only finite amount of current in one direction when “ON” It can block only a finite voltage in one direction. 3. Therefore. Kharagpur 16 www.6 which shows a clamped inductive switching circuit with a flat base drive.1Turn On characteristics of a Power Transistor From the description of the basic operating principle of a power transistor presented in the previous sections it is clear that minority carriers must be moved across different regions of a power transistor in order to make it switch between cut off and saturation regions of operation. Version 2 EE IIT. b) In power transistor there will be power loss due to ON state ________________ and OFF state _________________. It has a voltage drop during “ON” condition It carries a small leakage current during OFF condition Switching operation is not instantaneous It requires non zero control power for switching Of these the exact nature and implication of the first two has been discussed in some depth in the previous section. Exercise 3. c) Unlike an ideal switch the switching of a power transistor is not ____________.com characteristics of a power transistor differs significantly from an ideal controlled switch in the following respects. one.7 Fill in the blank(s) with the appropriate word(s) a) An ideal switch can conduct current in ______________ directions.jntuworld. The third and fourth non idealities give rise to power loss termed the conduction power loss.jntuworld.www. (c) instantaneous. the switching characteristics of a power transistor is always specified in relation to the external load circuit and the base current waveform as shown in Fig 3. The rate at which these densities are attained is determined by the base current waveform. In this section the nature and implications of the last two non idealities will be discussed in detail.5. The time delay in the switching operation of a power transistor is due to the time taken by the minority carriers to reach appropriate density levels in different regions. The exact level of minority carrier densities (and depletion region widths) required for proper switching is determined by the collector current and biasing collector voltage during switching. While a power transistor conducts current in _______________ direction. (b) voltage drop. both of which are determined by external circuits.com . Answer: (a) two.

com .jntuworld.www.jntuworld.com VCC iD D IL iC + RB iB Q VCE VBE VBB - (a) Version 2 EE IIT. Kharagpur 17 www.

6 (a).jntuworld. (a) Switching circuit.com .6 (b) are the expanded and to some extent “idealized” version of the actual waveforms that will be observed in a clamped inductive switching circuit as shown in Fig.com VBB VBE 0 td tri tfv1 tfv2 VBE sat t VBB . These are Version 2 EE IIT.3. Some simplifying assumptions have been made to draw these waveforms. (b) Switching wave forms The switching wave forms shown in Fig 3.www. Kharagpur 18 www.6 Turn ON characteristics of a power transistor.jntuworld.VBE(sat) RB iB t ic id IL IL t vCE VCC VCE (sat) t Pe VCC IL vCE (sat) IL t (b) Fig 3.

Turn ON process ends here. tri is called the current rise time of the transistor. it is not shown in Fig 3. During this period the switching trajectory traverses through the active region of the output characteristics of the transistor. Power loss occurs at all time during the operation of a power transistor. Before t = 0. The energy lost during these periods is called the Turn ON loss and given by the area under the Pl curve in Fig 3. Power loss due to this leakage current is negligible compared to other components of power loss in a transistor. The collector voltage VCE which has so far been clamped to VCC because of the conducting diode “D” starts falling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. The rising base current that flows during this period can be thought of as this capacitor charging current. At the end of the current rise time the diode D regains reverse blocking capacity.jntuworld. the transistor (Q) was in the “OFF” state.6 (b). Kharagpur 19 www. The process is akin to charging of a capacitor. To turn the transistor ON at t = 0. This starts the process of charge redistribution at the base-emitter junction. the value of which is given by the manufacturer as a function of the base-emitter reverse bias voltage. At this point D starts blocking reverse voltage and VCE becomes unclamped.6 (b). and tfv2. Finally at t = td the BE junction is forward biased. Therefore. The entire load current flows through the diode and VCE is clamped to VCC (approximately). Under this condition only negligible leakage current flows through the transistor. tfv1. In order to utilize the increased break down voltage (VCBO) the base-emitter junction of a Power Transistor is usually reverse biased during OFF state. The average Turn ON loss is obtained by dividing this area by (tri + tfv1 + tfv2). the reverse biased base emitter junction is often represented by a voltage dependent capacitor. Power loss occurs during Turning ON a Power transistor due to simultaneous existence of non-zero VCE and ic during tri. Reverse recovery characteristics of D has been ignored.com . At the end of this rapid fall (tfv1) the transistor enters “quasi saturation region”. TSW (ON) = td (ON) + tri + tfv1 + tfv2.jntuworld. Indeed. The fall of VCE in the quasi saturation region is considerably slower. For safe Turn ON this average power loss must be less than the limit set on the maximum Version 2 EE IIT. At the end of the delay time (td ON) the minority carrier density at the base region quickly approaches its steady state distribution and the collector current starts rising while the diode current (id) starts falling. The values of iO and VCE remains essentially at their OFF state levels.com • • • The load inductor has been assumed to be large enough so that the load current does not change during Turn ON period. The junction voltage and the base current settles down to their steady state values. During this period. the base biasing voltage VBB changes to a suitable positive value. At t = tdON + tri the collector current becomes equal to the load current (and id becomes zero) IL. However. At the end of this slow fall (tfv2) the transistor enters “hard saturation” region and the collector voltage settles down to the saturation voltage level VCE (sat) corresponding to the load current IL. All parasitic elements have been ignored. called the “Turn ON delay time” no appreciable collector current flows. The total turn on time is thus.www. the collector leakage current is usually negligibly small and power loss due it can be safely neglected in comparison to the power loss during ON condition.

(c) slow. If this current is not negligible then for safe Turn ON operation the sum of the load current and the diode reverse recovery current must be less than the ICM rating of the transistor. As will be seen later this increases the Turn OFF time. Answer: (a) minority. 3. (b) voltage.7 (a) Version 2 EE IIT. Idealized waveforms of several important variables in the clamped inductive switching circuit of Fig. B B B B In figure 3. However. Thermal and second break down limits must also be observed. However large base current increases the quantity of excess carrier in the base and collector drift region which has to be removed during Turn Off. b) The reverse biased base emitter junction can be represented as a ______________ dependent __________________. Exercise 3. Manufacturers usually provide the values of td (ON). (d) increasing. in steady state iB settle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is observed. Just as in the case of Turn ON. base. d) Turn ON delay can be reduced by __________________ the rate of rise of the base current. This can be achieved by connecting a small capacitance across RB.6 (a) during the Turn OFF process of Q are shown in Fig 3. 3.jntuworld.www.jntuworld.2 Turn Off Characteristics of a Power Transistor During Turn OFF a power transistor makes transition from saturation to cut off region of operation.8 Fill in the blank(s) with the appropriate word(s) a) For faster switching of a BJT _______________ carriers are to be swept quickly from the ________________ region. c) In the quasi saturation region collector-emitter voltage falls at a ______________ rate. Kharagpur 20 www. Therefore. This increases the rate of rise of VBE & iB.5. tfv as functions of ic for a given base current and case temperature.com power dissipation in the FBSOA corresponding to a pulse width greater than tri + tfv1 + tfv2.6 (b) the reverse recovery current of D has been neglected.com . Similar restriction with respect to second break down should also be observed. capacitor. Turn ON time can be reduced by increasing the base current. substantial redistribution of minority charge carriers are involved in the Turn OFF process. Turn ON delay time decreases. Since current gain reduces during saturation (typically between 5 to 10) this power loss may become significant. tri. The Turn ON delay time can however be reduced by boosting the base current at the beginning of the Turn ON process. This power loss depends on the current gain of the transistor during hard saturation. It should be noted that there is some power loss at the BE junction as well.

www.jntuworld. Kharagpur 21 www.com VBB VBE VBB VBE(sat) t iB t iC id IL IL t VCE VCE(Sat) VCC t Pe t ts trv1 trv2 (a) tfi Version 2 EE IIT.jntuworld.com .

7: Turn off. VCE increases rapidly towards VCC and at the end of the time interval “trv2” exceeds it to turn on D. thereafter by the conducting diode D. In the active region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope.jntuworld. (a) Switching wave forms (b) Switching trajectory The “Turn OFF” process starts with the base drive voltage going negative to a value -VBB. The last trace of Fig 3.7 (a) shows the instantaneous power loss profile during these intervals.com . trv2 and tfi. characteristics of a BJT. VBE starts falling forward –VBB and the negative base current starts reducing. Kharagpur 22 www. Turn OFF process of the transistor ends at this point. 3.www. The stored charge in the base region at this point is insufficient to support the full negative base current. After a further time interval “trv1” the transistor completes traversing through the quasi saturation region and enters the active region. The total energy last per turn off operation is given by the area under this curve. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. the remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At the end of trv2 the stored base charge can no longer support the full load current through the collector and the collector current starts falling. minority carriers stored in the base region. For safe turn off the average power dissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOA corresponding to a pulse width greater than trv1 + trv2 + tfi. At the end of the current fall time tfi the collector current becomes zero and the load current freewheels through the diode D. Version 2 EE IIT. due to the excess. After a time “ts” called the storage time of the transistor.com log iC ICM Reverse recovery current of D P’ P FBSOA RBSOA Forward recovery Voltage of D Turn on Trajectory VCBO Turn off Trajectory (b) V(sus) VCEO log vCE Fig. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi As in the case of “Turn ON” considerable power loss takes place during Turn OFF due to simultaneous existence of ic and VCE in the intervals trv1. The base-emitter voltage however does not change from its forward bias value of VBE(sat) immediately. VCE remains clamped at VCC.jntuworld.

3 Switching Trajectory and Switching Losses in a Power Transistor It has been mentioned in the earlier sections that energy loss takes place in a power transistor during each switching operation.7 ) Version 2 EE IIT. c) VCE increases rapidly in the ________________ region.jntuworld. Instantaneous power loss during switching can be calculated and plotted as shown in Fig 3. if the load is resistive.5 ) ⎣ CC L ri ⎦ 2 ( ) Where VCEf1 is the value of VCE at the end of the interval tfv1 Similarly E OFF = 1 ⎡( VCE ( sat ) + VCEr1 ) I L t rv1 + ( VCEr1 + VCC ) I L t rv2 + VCC I L t fi ⎤ ( 3. Kharagpur 23 www.www. b) Negative _______________ current is required to remove excess charge carriers from the ______________ region of a BJT during Turn OFF process. 3. base.9 Fill in the blank(s) with the appropriate word(s) a) Turn OFF process in a BJT is associated with transition from the _______________ region to the ______________ region. Manufacturers usually specify these values as functions of collector current for given positive and negative base current and case temperatures. E ON = 1⎡ V I t + ( VCC + VCEf1 ) I L t fv1 + VCEf1 + VCE (sat ) I L t fv2 ⎤ ( 3. Cut-off. The switching Power loss in this case will also be substantially lower. (b) base.com .5. then the average switching power loss is given by PSW = ( E ON + E OFF ) fSW ( 3.7 (a). Indicating these areas as EON and EOFF during Turn ON and Turn OFF operations respectively one can write. Exercise 3. In this section and the precious one inductive load switching have been considered. However.com Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions and the base drive design.jntuworld.6 ) ⎦ 2⎣ If the switching frequency of the transistor is fSW. The areas under these curves indicate the energy loss during each switching operation (Turn ON and Turn OFF). Variations of these time intervals as function of the ratio of positive to negative base currents for different collector currents are also specified.6 (b) and 3. The freewheeling diode D will not be used. Answer: (a) Saturation. (c) active. In that case the collector voltage (VCE) and collector current (ic) will fall and rise respectively together during Turn ON and rise and fall respectively together during Turn OFF. Other characteristics of the switching process will remain same.

Therefore. EON and EOFF are constant.www.jntuworld.8) Where TON is the time period for which the base drive voltage remain positive. They serve two specific purpose. Clearly full voltage (VCEO) or current rating (ICM) of the transistor can not be utilized in such a trajectory. For safe switching operation. In this diagram the green line corresponds to the Turn ON trajectory while the blue line corresponds to the Turn OFF trajectory.t fv2 + t s ) fSW ( 3. Being a minority carrier device a BJT has comparatively larger switching times (compared to some other devices broadly categorized as transistors) and hence larger switching power loss for a given frequency. Even without any restriction on the switching power loss the maximum switching frequency of a BJT is limited by its Turn ON and Turn OFF times. From these figures the conduction power loss is given by PC = VCE ( sat ) IL ( TON . Version 2 EE IIT.t fv1 . however it is not sufficient to merely restrict the switching power loss.jntuworld.com On the other hand the conduction energy loss is given by the area hatched black in Fig 3.com . Switching aid circuits or “snubbers” (as they are popularly known) are used to enhance the switching performance of a power transistor.7 (b) shows these switching trajectories superimposed on the FBSOA /RBSOA. Therefore. a BJT is suitable for switching large current at moderate (around a few KHZ) switching frequency.10 ) For a given collector current and base drive design. Fig 3. • Shape the switching trajectory such that the voltage and current rating of a transistor can be fully utilized. These trajectories are rectangular in nature.7(a). the switching power loss is proportional to the switching frequency. The situation becomes worse a when the reverse recovery current and forward recovery voltage of D is considered.t ri .9) For a given VCC and IL and base drive design. At high frequency BJT based circuits tend to become inefficient due to increased switching power loss. Therefore PC = VCE ( sat ) IL TON fSW = VCE ( sat ) IL D Where D is the switching duly cycle. Usually ts – TSW(ON) << TON. ( 3.t d ( ON ) .6 (b) and 3. It will be necessary to restrict the switching trajectory (an instantaneous plot of ic vs VCE during switching with time as a parameter) within the FBSOA /RBSOA region corresponding to a pulse width greater than TSW (ON) or TSW (OFF). On the other hand a BJT has the lowest ON state voltage drop VCE (sat) among all fully controlled switches. The value of the maximum switching frequency is given by FSW ( Max ) = 1 TSW ( ON ) + TSW ( OFF ) ( 3. Kharagpur 24 www.

Version 2 EE IIT.8: Switching characteristics of a BJT with Snubber (a) Clamped inductive switching circuit with snubber (b) Switching trajectory.www. Kharagpur 25 www. 3. VCC D IL LS RS iC + DS CS RB VBB iB Q VCE + (a) - logic ICM IL RBSO FBSO A Turn on Turn off log vCE VCE(sus) VCEO VCBO VCC (b) Fig.jntuworld. 3.8 shows a typical snubber circuit for a power transistor and the corresponding switching trajectories. Fig.com • Reduce the switching power loss inside the device.com .jntuworld.

VCC. Maximum collector current that can be handled is also considerably higher (I L Max = ICM . At the end of the Turn OFF process VCE shoots over VCC due to Ls-Cs oscillation. by proper design VCE Max can be restricted well below VCBO. Version 2 EE IIT. However. Comparison of the switching trajectories with and with out snubber circuit makes it evident that the snubber circuit can considerably enhance the voltage and current capacity utilization of a Power transistor. However. In the snubber assisted trajectory VCE falls substantially before ic rises to any appreciable value. Therefore. LS also helps to reduce Irr (D) by restricting the rate of decrease of current through D. At the same time ic also starts rising towards IL. it should be emphasized that the total switching loss (device + snubber resistance) may not reduce. This also helps to increase I L Max Rs-Cs-Ds constitute the Turn OFF snubber. Therefore.jntuworld.com Fig 3.8 (b). The inductor LS connected between the load and the collector is the Turn ON snubber. Therefore. b) BJT has _______________ ON state voltage drop. In decouples the collector from the supply voltage during Turn ON. the turn OFF snubber circuit can effectively utilize the enhanced voltage withstanding capability of a power transistor with base reverse biased. VCC can be made larger than VCE(sat) and can be chosen closer to VCEO.www.8 (a) shows the same clamped inductive switching circuit of Fig 3. Kharagpur 26 www. In the unsnubbed case. The area enclosed under the switching trajectories is a measure of the switching loss occurring in the device at each switching.6 (a) but with the snubber elements. Components should also be chosen very carefully. since it is a _________________ carrier device. The resultant switching trajectory is shown by the solid green line in Fig 3. c) BJT is inefficient at ______________ switching frequencies. the collector current rises to the maximum value before VCE starts falling from VCC. This is popularly known as the “R-C-D snubber”. Rs must be non inductive and the lead inductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably large and its wattage should selected accordingly. it is evident from Fig 3.8 (b). must necessarily be smaller than VCE (SUS).com . as the junction VBE becomes forward biased VCE starts falling. In the unsnubbed case ) maximum IL is restricted essentially by the maximum power dissipation consideration and not by ICM. During Turn OFF as the base drive of Q is removed ic starts falling and the remaining load current is bypassed to Cs through Ds. Exercise 3. This should be compared with the unsnubbed Turn ON trajectory (broken green line). therefore. It is also necessary to place the snubber components very close to the transistor since any stray inductance in the Rs – Cs – Ds loop may give rise to an unacceptably large voltage spike across Q. To avoid excessive power loss in Rs.Irr ( D ) .jntuworld. lossless (regenerate) snubber circuits have been proposed.8 (b) that the snubber circuit reduces the switching power loss inside the device considerably. Therefore. the collector voltage rises simultaneously giving rise to the Turn OFF trajectory shown by the solid blue line in Fig 3.10 Fill in the blank(s) with the appropriate word(s) a) BJT has large switching times. Therefore.

one effect of introducing the drift region is the appearance of a “quasi saturation region” in the output i-v characteristics of a power transistor.4 Base Drive Design and Power Darlington The performance of a Power transistor depends largely on the base drive design. maximum forward voltage.jntuworld. The magnitude of the base current during turn on decides the values of the voltage fall time. (b) This characteristics gives the amount of base current required so that the transistor can operate in the saturation mode for a given collector current. (b) low. (b) β vs ic characteristics. In offers a resistance which is a function of the base current. 3. Exercise 3.com d) Turn OFF snubber circuit is used to improve _______________ withstand capacity of a BJT.5. this characteristics is used to design the base drive circuit for a given base power source. Exercise 3. Answer: (a) minority. Although the base current retain some control over collector current in this state the value of dc current gain reduces substantially due to increased effective base width. However.www. • • The rate of rise of base current in the beginning of the turn on process determines the turn on delay time. It is most useful in designing the switching trajectory of a power transistor. In the quasi saturation state the drift region is not completely shorted out by “conductivity modulation” by excess carriers from the base region.jntuworld. (c) After the base current is determined. maximum average & instantaneous power dissipation and second break down limits. (d) voltage.com . Version 2 EE IIT. current rise time and VCE (sat) for a given collector current. (c) high. Another effect of introducing the drift region is to make the VCE saturation voltage depend linearly on the collector current in the hard saturation region due to the ohmic resistance of the “conductivity modulated” drift region.12 Explain the importance of the following manufacturer’s specifications (a) FBSOA. (c) iB vs VBE characteristics B Answer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in terms of maximum forward current.11 What are the effects of introducing a drift region in the output i-v characteristics of a power transistor? Answer: The drift region in a power transistor is introduced in order to block large forward voltage. Kharagpur 27 www.

RBN is given R BN = VBB.jntuworld.12 ) Version 2 EE IIT. • Once iBP is known the turn on loss is fixed.com . • • A suitable negative base current (iBN) to give the desired voltage rise time is determined from the manufacturer’s data sheet.www. The required current fall and voltage rise times for the calculated turn off loss is determined for the given load current and VCC. These should be kept as low as possible in order to reduce base drive power requirement.VBE ( sat ) i BP ( 3.+ VBE ( sat ) i BN ( 3. Using the desired value of VCE (sat) for the given load current. the required value of forward base current (iBP) and the corresponding VBE (sat) is obtained from the manufacturer’s data sheet.jntuworld. The allowable turn off loss is determined by subtracting the turn on loss for the desired total switching loss. A negative bias at the base also enhances the voltage withstanding capacity of a power transistor. • The forward base drive resistance RBP is given by R BP = VBB+ . The following step by step procedure can be followed to arrive at the values. From the discussion of the switching characteristics of a BJT it is evident that the base drive voltage source should be bipolar and the base drive resistance should be different during turn on and turn off. voltage rise time and current fall time. • The forward and reverse base drive voltages (VBB + & VBB -) are decided on the basis of the availability of control power supply. Kharagpur 28 www. • • From the load current value (to be switched) and desired conduction power loss the desired value of VCE (sat) is determined. This is achieved by connecting a small capacitor across RBP.com • • The negative base current during turn off determines the storage time.11) It has been mentioned earlier that the turn on delay time can be reduced by increasing the rate of rise of iBP at the beginning of the turn ON process.

if a low value of VCE (sat) is desired at full load current. With such low gain large current switching becomes difficult since the base drive circuit is required to handle about 20% of the full load current.13) So that even when individual β’s are small effective β can still be quite large. Fig 3. Version 2 EE IIT. The storage time can be reduced by connecting a small capacitor across RBN. β can be as low as 5.com . The effective current gain of a Darlington pair is given by β = β Mβ D + β M + β D ( 3. Darlington connected transistors can solve this problem.com • • Once iBN is fixed the storage time (ts) can be determined from the manufacturer’s data sheet. Particularly. Kharagpur 29 www.jntuworld.www.10 shows the circuit connection and the vertical cross section of a Monolithic Darlington pair.9: Typical base drive circuit of a power transistor Power transistors have low values of dc current gain (β) compared to their signal level counterpart.9 VBB + RBP R1 From Control circuit R3 Optocoupler Q R2 RBN Electrical Isolation VBB - Fig 3. The resulting base drive circuit can be realized as shown in Fig 3. Monolithic.jntuworld.

Kharagpur 30 www. (b) schematic cross section.com iCD IBD C IL B iCM QD iED QM D iBM (a) E iED E B n+ iBD p iBM sio2 p’ n+ n- iCD n- iCM n+ n+ C (b) Fig 3.jntuworld.10: Monolithic Darlington connected power transistor. Version 2 EE IIT.www. (a) circuit diagram.jntuworld.com .

Exercise 3.t ri . VBB. The major quantitative difference in the operating characteristics of a Power Darlington is due to the fact that the main transistor can not go into hard saturation.7 V . IBP = 2.5 A. the ON state power dissipation of the main transistor will be larger than that of an otherwise comparable single BJT.5 A. E ON = 1 V I ( t + t ) = 32 mJ 2 CC L ri fv1 Turn off energy loss is given by E off = 1 2 VCC I L ( t fi + t rv2 ) = 32mJ So total energy loss per switching = EON + E0ff = 64 mJ. Conducting loss per switching is given by E COND = I L VCE sat ( D fsw .9 mJ ) ∴ Conduction power loss = 9. tfv2 = 0.com . The ON state voltage drop of the drive transistor prevents forward biasing of the C-B junction of the main transistor. trv1 = 0. The switching times will also be somewhat larger for the Darlington transistor. VBE drive transistors) = 0.www.t fv + t s = 9. Answer: Turn on energy loss is given by. ∴ Switching power loss = fsw (EON + Eoff) = 64 watts. tri = tfv1 = 8 μs. The silicon protrusion through the p layer (the base region for both transistors) isolates the two bases from each other. A discrete diode D is added (Fig 3. Kharagpur 31 www.jntuworld. Therefore. Switching times are as follows. VCE sat (of Version 2 EE IIT. 3. IBN = 1.3 V sat = 0.9 determine the values of the base resistors RBP & RBN for the following data VBB+ = 10 volts. switching frequency and duty cycle are 1 KHZ and 0. This drive transistor should have the same voltage rating as the main transistor but lower current rating. In a monolithic design both are fabricated from the same crystal. ts = 12 μs.jntuworld. tfi = trv2 = 8 μs.com In the Darlington configuration the base drive current for the main transistor is derived from the collector biasing power supply through a drive transistor. Exercise 3. The supply voltage is 200V.= -10 V. VCE sat = 1.0V at i c = 20 A Calculate switching and conduction losses in the transistor.10 (a)) to speed up the turn off time of the main transistor.5 respectively.t d . td = 1μs.9 watts.14 With reference to Fig.13 A Power BJT is used to switch an inductive load carrying 20 A.

www.jntuworld.6 ohms.jntuworld.VCE I BP sat = 3.VBB- = 6.com . Kharagpur 32 www.93 ohms Version 2 EE IIT.VBE sat .VCE I BN sat . R BN = VBE sat .com Answer: R BP = VBB + .

2003. Kharagpur 33 www. Christos C.jntuworld.com References 1) Jacob Millman. 1991. Halkis. William P.com . Tata McGrow-Hill publishing Company Limited. John Willey & Sons (Asia) Publishers. “Integrated Electronics. Undeland. New Delhi. Version 2 EE IIT.www. Robbins. “Power Electronics. 2) Ned Mohan. Analog and Digital circuit and systems”. Tore M.jntuworld. Application and Design”. Third Edition. Converters.

Operating restrictions applicable to a power transistor under forward and reverse bias conditions are represented compactly in FBSOA & RBSOA diagrams respectively. Consequently. Kharagpur 34 www. BJT being a minority carrier device have low on state voltage drop and longer switching delay times compared to some “majority” carrier “transistors”. A BJT can be of n-p-n or p-n-p type with three terminals called the collector. Switching of Power transistors from ON (saturation) to OFF (cut-off) state involves considerable redistribution of minority carriers. switching operation is not instantaneous. BJT has higher switching loss and lower conduction loss. current controlled unidirectional device. Power transistor output i-v characteristics exhibits a quasi saturation region not found in their signal level counterpart. active or saturation regions. It is the direct consequence of introducing a lightly doped n. Switching characteristics of a power transistor is greatly influenced by the external load circuit and the base drive circuit. maximum voltage.drift region in the structure of a power transistor which enhances its forward voltage blocking capacity. maximum power dissipation and second break down limits. Therefore. Energy loss takes place during each switching operation of a power transistor due to simultaneous existence of collector current and voltage. A BJT can operate in cut-off. or saturation mode.com • • • • • • • • • • .jntuworld. In saturation the VCE voltage drop of a transistor is very low. the base and the emitter. A Power transistor is suitable for large current switching at low to moderate (a few kHZ) frequency. In the active region the ratio of collector current to base current is fairly constant.www. n-p-n type transistor in the common emitter configuration with the base as the control terminal is used. Switching power loss is proportional to the switching frequency while the conduction power loss is proportional to the duly cycle. Conduction loss during the OFF state of a Power transistor is negligibly small. A transistor can be driven into saturation by increasing the base current for a given collector current. In the cut-off region the base emitter junction is reverse biased and the collector current is almost zero. For power application normally. This ratio is called the dc current gain (β).com Lesson Summary • • • • • • • A Bipolar Junction Transistor is a minority carrier. This is called switching loss. For safe operation power transistors must observe maximum current.jntuworld. Version 2 EE IIT. Energy loss taking place during ON condition of the transistor is called the conduction loss. They operate either in the cutoff.

Kharagpur 35 www.www.jntuworld. For that purpose lossless (regenerative) snubber circuits are used. But they have larger ON state voltage drop and longer switching times. Monolithic Power Darlingtons can solve the problem of low current gain. • • Version 2 EE IIT. Ordinary L-R-C-D snubber circuits may not reduce total switching loss. They also reduce switching loss internal to the device. base drive voltage should be bipolar and have different output resistance for Turn ON and Turn OFF operations.com • • • Switching aid circuits (snubbers) are used for enhancing the capacity utilization of a power transistor.com .jntuworld. Power transistors have relatively small current gain (β) and hence require large base drive current. For optimal operation. Proper design of the base drive circuit helps to reduce both conduction and switching losses.

jntuworld. Kharagpur 36 www.jntuworld.www.com Practice Problems and Answers Version 2 EE IIT.com .

VCE sat = 0.jntuworld. tfi = trv = 2. VD1 = VD2 = VD3 = 0. Kharagpur 37 www. The transistor of Problem -1 has the following switching time specifications. 10 ≤ β ≤ 40 Find maximum allowable value of RB and power output of the base source.5 μs. B VCC = 200V RL = 20Ω D3 RB + D1 VBB = 12V 2.www.5 μs. (i) conduction power loss.2 V 10 ≤ β ≤ 40 .7 v.com .jntuworld. Find out the value of RB and Power requirement of the base source. In the transistor switching circuit VBE sat = 0. In the transistor switching circuit shown VBE sat = 0. Also compare conduction power loss with the circuit shown in Problem – 1.5. Find out. Version 2 EE IIT. ts = 5 μs. The transistor is switched at a frequency of 10 KHZ with duty ratio d = 0.com VCC = 200V RL = 20Ω RB + VBB = 12V 1.75 V.75 v. (ii) switching power loss. td = 1μs. B D2 3. tri = tfv = 2.

7V. For QN VBE For Q sat = . What adverse effect does it have on the switching performance of a BJT? Suggest one solution to this problem. Kharagpur 38 www. VBE sat = 0. The comparator has an output voltage swing of ± 12 V. Also For QP VBE sat = 0.jntuworld. Find the values of RBP.com . Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal level counterpart.2 V. RBN and 5.com VBB ∫∫ 50μs ∫∫ 50μs ∫∫ t iC ∫∫ 10 A ∫∫ ∫∫ td t ri VCE 200v tfv Ploss ts t tfi ∫∫ 200v ∫∫ trv PSW (off) PCOND t PSW (on) t 4. Figure shows practical implementation of a power transistor base drive circuit. Also it is desired that negative base current should be at least Min equal to positive base current.0. β Min = 10. VCE sat = .jntuworld.www.75 V.0. VCE sat = 0.2V. β R1 of QP & QN are same.7 V. Version 2 EE IIT.

7. which indicates that the transistor is in hard saturation.jntuworld.4 Ω iB Power Drawn from base source is 12 × 0. 2.45 IL = ic = = 9.2 = 2 watts Conduction power lass in this case is 9.com 6. The load current I L = i c = VCE 200 . = 1 amps 10 ∴ R B = VBB . VCEO & VCBO of a Power BJT. The transistor is not in saturation since VCB is positive.4 watts B Note: This circuit is known as the anti-saturation clamp or the “Baker’s clamp”.75 volts Power drawn from base source is 12 × 1 = 12 watts. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle.25 Amps. In this case VCE = VBE sat + VD2 + VD1 .93 Amps. 20 i ∴ i B = c = 0.VD3 = 1.25 = 3 watts. How can these three voltage ratings of a BJT be utilized in an inductive switching circuit.com .www.45 volts .25 Ω ic So required base current = VBE sat = 0. Version 2 EE IIT. So β = βmax = 40 200 -1. Therefore β = βmin = 10.93 × 1. Then now does it help to extend the usable voltage and current rating of a BJT? Answer to Test Problems 1. Conduction power lass in 1st problem was 10 × 0. β For maximum value of RB current through D3 will be zero V -V -V -V So R B = BB D1 D2 BE sat = 39. Kharagpur 39 www. Differentiate between the voltage ratings VSUS.jntuworld.45 = 14.VCE sat ≈ 10 Amps 20 sat = 0.2V.VBE sat = 11.

In the interval t ri ( or t fv ) iC1 QP iE1 iB B TTL Pulse 1.t ⎞ = 10 (1 .4 × 105 t ) ⎜ t fi ⎟ ⎝ ⎠ VCE = 200 t = 80 × 10 6 t t rv Version 2 EE IIT.jntuworld. Major difference with clamped inductive switching waveform is that in this case rise and fall of ic & VCE are simultaneous. Figure shows switching waveforms of the transistor. Kharagpur 40 www.com .com + 15v + 12v RBP VCC IL = 50 A iB1 10 KΩ comp 0 Rl A iE2 QN iC2 RBN .www.t ⎞ = 200 ( 4 × 105 t ) .12v . ⎜ t fv ⎟ ⎝ ⎠ where VCE sat has been neglected.15v 3.jntuworld. In the interval t fi ( or t rv ) i c = 10 ⎛1.5v QP E iB2 ic = 10 t = 4×106 t t ri VCE ≈ 200 ⎛ 1.

jntuworld.55 = R BN R BN 12.83 mJ ∴ E SW = E SW ( ON ) + E SW ( OFF ) = 1.VBA + 12 12. 4.66 mJ ∴ PSW = E SW × f SW = 1. Kharagpur 41 www. & ic = 50 A. Conduction loss occurs in the interval from the end of tri to the beginning of tfi ∴ E COND = VCE sat × I L × ( TON .05 15. For the transistor Q.103 mJ ∴ PCOND = E COND × f SW = 0. ∴required positive i BP = 50 10 = 5 Amps Now i BP = i E1 = i c1 + i B1 12 .66×10-3 × 10 × 103 = 16.1 = R BP R BP 10.com .5×106 o 8×108 t (1.05 = R1 R1 VBE .VBE 10.VAB . β Min = 10 .com ∴ E SW ( ON ) = ∫ = ∫ ∫ t ri o VCE i c dt 8×108 t (1.td .5×106 o = 0.4×105 t ) dt = 0.03 watts.jntuworld.55 Now i B1 = = R1 R1 15 .t ri + t s ) = 0.www.83 mJ E SW ( OFF ) = t fi o VCE i c dt = ∫ 2.6 watts.VEC2 + 15 15.4×105t ) dt 2.VCE sat .1 So + = 5 R1 R BP i C1 = Now iBN ≥ iBP = 5A i BN = i E2 = i B2 + i C2 i B2 = i C2 = VBE .55 So + ≥ 5 R1 R BN Now βmin of QP & QN are same.VBE 14. Version 2 EE IIT.103 × 10 -3 × 10 × 103 = 1.55 14.

This requires a large base drive power supply and increased base drive power loss. The base width has to be larger than this penetration depth. Version 2 EE IIT.1 R 1 15. In these localized high current density regions β tends to fall off very sharply reducing the effective dc current gain.78 Ω 5.55 R BP 10. Unlike a power diode the doping density of the base region cannot be made very much large compared to the lightly doped collector drift region since it will reduce “β” by increasing minority carrier injection into the emitter.55 R 1 or = 10. The thicker base region is required to withstand the large blocking voltage. This problem can be solved to some extent by using two power transistors connected in the “Darlington configuration” as shown. A thicker base leads to larger rate of recombination of minority carriers injected by the emitter.www.55 R 1 5R 1 ≥ 12.jntuworld. Therefore.jntuworld. Kharagpur 42 www. A second reason for lowering of β arises from the “emitter crowding” effect where by the collector current tends to “crowd” near specific regions of the emitter.1 R 1 5R 1 Now 1 + = 10. The main reason for comparatively lower dc current gain in a power transistor is a relatively thicker base region (a few tens of μm compared to a fraction of a μm incase of a signal transistor).55 R BP 12.com So i C1 i = C2 i B1 i B2 14. Due to lower dc current gain the base current requirement of a power transistor switching circuit increases.05 10.05 R BN 12. As a result the depletion layer at the C-B junction penetrates considerably in to the base region.05 R BN 14.55 ⎠ 1+ or R 1 > 0 choose R 1 = 100 Ω ∴ R BP = 2.05 1 ⎞ ⎛ 1 ∴ 0 ≥ 5R 1 ⎜ ⎟ ⎝ 12.88 Ω R BN = 2.com .55 10. for a given collector current the required base current is relatively high and the dc current gain is low.

The main transistor (QM) does not go into hard saturation due to VCE drop of QD. there is considerable supply of minority carriers which are accelerated by the large CB junction electric field to start avalanche breakdown at a relatively lower voltage. with iB < 0 base emitter junction is reverse biased and there is no supply of minority carriers to the CB junction from the emitter. Therefore. Under this condition the supply of minority carriers at the CB junction is much less compared to the previous case. the conduction loss is higher.www. however. Power Darlington has one problem. Therefore. Therefore.com .com iCD iL iBD βD QD iCM βM QM iED For this configuration. However. With both iB and iC greater than zero. B The rating VCBO is the maximum allowable voltage between C & E terminals when the transistor is in cut off with iB < 0 and iC less than a specified value.jntuworld. i L = i CD + i CM But i CD = β D i BD i CM = β M i ED = β M ( i BD + i CD ) + β D + β Mβ D ) i BD = β eqv i BD ∴ i L = β Di BD + β Mi BD + β Mβ Di BD = (β M equivalent β (βeqv) can be increased considerably due to multiplication of βM & βD. Thus avalanche B B B Version 2 EE IIT. Thus VCEO > VSUS.jntuworld. The voltage rating VSUS is the maximum allowable voltage across C & E when the transistor is in active region with iB > 0 and collector current above a minimum value. With iB = 0 the EB junction is still forward biased and there is small injection of minority carriers from the emitter to the CB junction. B B The rating VCEO is the maximum allowable voltage between C & E terminals when the transistor is in cut off region with iB = 0 or iC is less than a specified value. avalanche breakdown of the CB junction occurs at a higher voltage. the voltage rating VSUS is the lowest of the three. Kharagpur 43 www. 6.

With only DC FBSOA the switching trajectory has to be restricted to something similar to AD BD CD. precaution must be taken such that the voltage over shoot decays before iB becomes equal to zero. This can be utilized to increase the usable steady state blocking voltage of the transistor up to VCEO. Version 2 EE IIT. Therefore. Since during turn off iB < 0 and the voltage.com break down of this junction occurs at a relatively higher voltage making the rating VCBO largest of the three. B B However.www. the increases FBSOA can be utilized and the switching trajectory improved to AP BP CP provided total switching time is less than the pulse period for which the increased FBSOA is applicable.jntuworld. log iC ICM CP CD DC BD BP Pulsed O AD AP log vCE 7. in general for a power transistor. Therefore. Both these limits require simultaneous existence of nonzero VCE & iC which for a power transistor occurs only during switching. However. Similarly during turn off iC does not fall till VCE rises to steady state blocking voltage level.jntuworld. VCBO > VCEO > VSUS In an inductive switching circuit using snubber the collector voltage falls considerably before iC builds up to any significant level.com . Since VCE will go below VSUS before iC can build up to the level where the rating VSUS becomes applicable. overshoot occurs with iC = 0 the applicable voltage limit will be VCBO and not VCEO. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to maximum power dissipation and second break down. Similarly during turn off. Kharagpur 44 www. with pulsed FBSOA applicable limits of power dissipation and second break down increases considerably. the overshoot in the VCE voltage can be accommodated in the difference between VCBO and VCEO. However. if a snubber circuit is not used the applicable voltage limit will always be VSUS since in this case VCE does not fall till iC rises to its full value during turn ON.

jntuworld.jntuworld. Kharagpur 45 www.com . Version 2 EE IIT. This condition can be easily satisfied provided total turn on and turn off times of the transistor expressed as a percentage of total “ON” and “OFF” periods of the transistor is less than this duty ratio since during ON or OFF period the transistor remain well within DC FBSOA.com In addition pulsed FBSOA s are usually specified for a very low duty ratio.www. In practice this condition is satisfied by specifying a minimum ON and OFF period of the transistor.

www. Kharagpur 1 www.jntuworld.jntuworld.com Module 1 Power Semiconductor Devices Version 2 EE IIT.com .

jntuworld.www. Kharagpur 2 www.com Lesson 4 Thyristors and Triacs Version 2 EE IIT.jntuworld.com .

Interpret data sheet rating of a thyristor. Kharagpur 3 www. Draw and explain the gate characteristics of a thyristor.com Instructional objects On completion the student will be able to • • • • • • Explain the operating principle of a thyristor in terms of the “two transistor analogy”.jntuworld. Explain the operating principle of a Triac. Version 2 EE IIT.jntuworld. Draw and explain the i-v characteristics of a thyristor.com . Draw and explain the switching characteristics of a thyristor.www.

light activated SCR (LASCR). coupled with the fact that a thyristor can not be turned off using a control input. the modern power electronics area truly began with advent of thyristors. Version 2 EE IIT. have all but eliminated thyristors in high frequency switching applications involving a DC input (i. During conduction it offers very low forward voltage drop due to an internal latch-up mechanism. Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT).jntuworld. However. Kharagpur 4 www.2 Constructional Features of a Thyristor Fig 4.e. schematic construction and the photograph of a typical thyristor. One of the first developments was the publication of the P-N-P-N transistor switch concept in 1956 by J. Silicon Controlled Switch (SCS). Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. minority carrier semi-controlled device. They have reigned supreme for two entire decades in the history of power electronics.1 Introduction Although the large semiconductor diode was a predecessor to thyristors. Moll and others at Bell Laboratories. Thyristors have longer switching times (measured in tens of μs) compared to a BJT.jntuworld. It can block voltage in both directions but can conduct current only in one direction. thyristors still remain the device of choice. engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in 1957. They include. 4. This. choppers. inverter grade fast thyristor.com 4. thyristor remain popular due to its low conduction loss its reverse voltage blocking capability and very low control power requirement. probably for use in Bell’s Signal application.com .L. Diac. three terminal. inverters). However in power frequency ac applications where the current naturally goes through zero. Triac and the Gate turn off thyristor (GTO).1 shows the circuit symbol. From the construction and operational point of view a thyristor is a four layer. It can be turned on by a current signal but can not be turned off without interrupting the main current. This had a continuous current carrying capacity of 25A and a blocking voltage of 300V.www. In fact. in very high power (in excess of 50 MW) AC – DC (phase controlled converters) or AC – AC (cyclo-converters) converters. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed.

3 Basic operating principle of a thyristor The underlying operating principle of a thyristor is best understood in terms of the “two transistor analogy” as explained below. Therefore. the cathode regions are finely distributed between gate contacts of the p type layer. 4. As it will be shown later. The top p layer acls as the “Anode” terminal while the bottom n+ layers acts as the “Cathode”.www.1 (b) the primary crystal is of lightly doped n.com A A p n- G K (a) G n+ p n+ K (b) (c) Fig. As in the case of power diodes and transistors depletion layer spreads mainly into the lightly doped nregion. (b) Schematic Construction. Kharagpur 5 www. 4. that for better switching performance it is required to maximize the peripheral contact area of the gate and the cathode regions. An “Involute” structure for both the gate and the cathode regions is a preferred design structure. The “Gate” terminal connections are made to the bottom p layer. The thickness of this layer is therefore determined by the required blocking voltage of the device. due to conductivity modulation by carriers from the heavily doped p regions on both side during ON condition the “ON state” voltage drop is less. Version 2 EE IIT. (c) Photograph As shown in Fig 4. However.jntuworld.jntuworld.com .type on either side of which two p type layers with doping levels higher by two orders of magnitude are grown.1: Constructional features of a thysistor (a) Circuit Symbol. The outer n+ layers are formed with doping levels higher then both the p type layers.

1 & 4. With this voltage polarity J1 & J3 are forward biased while J2 reverse biased. Kharagpur 6 www. i.1) ( 4.5 ) Version 2 EE IIT.4 IA = ( 4.com A p n - A p n J2 n+ - A IA Q1 (α1) iC2 np n+ J1 iC1 IG G p n+ J3 G p (α2) Q2 J2 J3 IK K G K (a) (b) K (c) Fig.e anode positive with respect to the cathode and the gate terminal open. i c1 + i c2 = I A & IA = IK Combining Eq 4.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction.4 ) (∵ I G = 0 ) ( 4.www.3) ( 4.( ∝1 + ∝ 2 ) .( ∝1 + ∝ 2 ) 1.jntuworld.jntuworld.2 (c). 4. (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors. Now from Fig 4. a) Schematic construction. Under this condition. Let us consider the behavior of this p n p n device with forward voltage applied.com I co1 + I co2 I co = 1.2 ) Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation currents of the CB junctions of Q1 & Q2 respectively. ic1 = ∝1 I A + I co1 ic 2 = ∝ 2 I K + I co2 ( 4. b) Schematic division in component transistor c) Equivalent circuit in terms of two transistors.

Since the p layers on either side of the n. Thus.jntuworld.jntuworld. Therefore. However. Kharagpur 7 www.4 can be written as IK = IA + IG ( 4.1 to 4. With a positive gate current equation 4.7 ) Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence VAK). Just after turn ON if Ia is larger than a specified current called the Latching Current IL. the junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side of this junction are heavily doped. As Ico increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity. the reverse characteristics of a thyristor is similar to that of a single diode. This is called gate assisted turn on of a Thyristor.www.Up to the break down voltage of J1 the reverse current of the thyristor remains practically constant and increases sharply after this voltage.com Where I co I co1 + I co2 is the total reverse leakage current of J2 Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity. voltage drop in the external resistance causes a collapse of voltage across the thyristor.com . The only way the thyristor can be turned OFF is by bringing IA below a specified current called the holding current (IH) where upon ∝1 & ∝2 starts reducing.e. restricted only by the external load resistance. The CB junctions of both Q1 & Q2 become forward biased and the total voltage drop across the device settles down to approximately equivalent to a diode drop. The thyristor can regain forward blocking capacity once excess stored charge at J2 is removed by application of a reverse voltage across A & K (ie. K positive with respect A).( ∝1 + ∝ 2 ) Combining with Eqns.) junctions J1 and J3 are reverse biased while J2 is forward biased. Under this condition large anode current starts flowing. ∝1 and ∝2 remain high enough to keep the thyristor in ON state. It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward break-over level. The thyristor is said to be in “ON” state. When a reverse voltage is applied across a thyristor (i. Of these. This is the usual method by which a thyristor is turned ON. The maximum value of the reverse voltage is restricted by a) The maximum field strength at junction J1 (avalanche break down) b) Punch through of the lightly doped n. Ico starts increasing rapidly due to avalanche multiplication process. Therefore. as VAK is increased up to the avalanche break down voltage of J2. Therefore. 4.layer. the forward and the reverse break down voltage of a thyristor are almost equal.region have almost equal doping levels the avalanche break down voltage of J1 & J2 are almost same.3 I A = ( 4. cathode positive with respect to anose. the applied reverse voltage is almost entirely supported by junction J1. However. total anode current IA is only slightly greater than Ico. Version 2 EE IIT.6 ) ∝ 2 I G + I co 1.

A thyristor may turn ON due to large forward ________________. gate. turn off. Version 2 EE IIT. If a forward voltage is suddenly applied across a reverse biased thyristor. Answers: (i) minority. iv. However.jntuworld. both. the transistors Q1 & Q2 now work in the reverse direction with the roles of their respective emitters and collectors interchanged.com If a positive gate current is applied during reverse bias condition. (iv) holding.jntuworld.e. the junction J3 becomes forward biased. The resulting current can become large enough to satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor. the constituent transistors have very low current gain in the reverse direction. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias condition (i.1 1) Fill in the blank(s) with the appropriate word(s) i. e cathode positive with respect to anode)? Answer: The two transistor analogy of thyristor shown in Fig 4.∝1 + ∝2 = 1). dt Exercise 4. A thyristor is a ________________ carrier semi controlled device. Therefore no reasonable value of the gate current will satisfy the turn ON condition (i. With a positive gate pulse applied it may appear that the device should turn ON as in the forward direction. iii. To turn OFF a thyristor the anode current must be brought below ________________ current and a reverse voltage must be applied for a time larger than ________________ time of the device. (iii) break over. This is called dv turn on of a thyristor and should be avoided. A thyristor can be turned ON by applying a forward voltage greater than forward ________________ voltage or by injecting a positive ________________ current pulse under forward bias condition. (ii) one. v. In fact. ii.2 (c) indicates that when a reverse voltage is applied across the device the roles of the emitters and collectors of the constituent transistors will reverse. A thyristor can conduct current in ________________ direction and block voltage in ________________ direction. the reverse ∝1 & ∝2 being significantly smaller than their forward counterparts latching of the thyristor does not occur.www. there will be considerable redistribution of charges across all three junctions.com . However. (v) dv dt 2. Kharagpur 8 www. However. Hence the device will not turn ON. reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device.

However. The right hand side figure in the inset shows a typical plot of the forward break over voltage (VBRF) as a function of the gate current (Ig) After “Turn ON” the thyristor is no more affected by the gate current.5v) while the anode current is determined by the external load. Hence.com 4. Beyond this point voltage across the thyristor (VAK) remains almost constant at VH (1-1.com . any current pulse (of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to effect control. Version 2 EE IIT.3: Static output characteristics of a Thyristor The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure.jntuworld.4 Steady State Characteristics of a Thyristor 4. The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure.4. Kharagpur 9 www.www. 4.1 Static output i-v characteristics of a thyristor IA VBRF + VAK - A IA ig K Ig IL VBRF ig1 ig2 ig3 ig4 VBRR Is IH VAK VH ig4 > ig3 > ig2 > ig1 > ig = 0 ig4 > ig3 > ig2 > ig1 > ig = 0 Fig. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (IL) level. With ig = 0.jntuworld. VAK has to increase up to forward break over voltage VBRF before significant anode current starts flowing. at VBRF forward break over takes place and the voltage across the thyristor drops to VH (holding voltage).

The gate terminal has no control over the turn OFF process.www. 4. In ac circuits with resistive load this happens automatically during negative zero crossing of the supply voltage.3 shows the reverse i-v characteristics of the thyristor.jntuworld. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). in dc circuits some arrangement has to be made to ensure this condition.com .4.2 Thyristor Gate Characteristics The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop and low reverse break down voltage.jntuworld. Kharagpur 10 www. At this point current starts rising sharply. This characteristic usually is not unique even within the same family of devices and shows considerable variation from device to device.4: Effect of junction temperature (Tj) on the output i – v characteristics of a thyristor. If ig > 0 during reverse bias condition the reverse saturation current rises as explained in the previous section.com The left hand side of Fig 4. This can be avoided by removing the gate current while the thyristor is reverse biased. Version 2 EE IIT. 4. This process is called “forced commutation. However.” During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse voltage reaches reverse break down voltage (VBRR). manufacturer’s data sheet provides the upper and lower limit of this characteristic as shown in Fig 4. VBRF IA Tj = 150° 135° 25° 75° 125° 150° Tj 25° 75° 125° VAK Tj = 125° 75° 25° 135° 150° Fig.5. This is called “natural commutation” or “line commutation”. Large reverse voltage and current generates excessive heat and destroys the device. Therefore. The static output i-v characteristics of a thyristor depends strongly on the junction temperature as shown in Fig 4.4.

Kharagpur 11 www.Rgig A typical load line is shown in Fig 4. The actual operating point will be some where between S1 & S2 depending on the particular device.5 by the line S1 S2.www. Therefore. For TON larger Version 2 EE IIT. gate current limit (Igmax) and maximum average gate power dissipation limit ( Pgav Max ) . 4.com Vg E Vg max c d Rg ig Vg Pgm e A • S2 Load line Vg min Vng g Ig min b h E Pgav ⎜Max K • S1 f Ig max Ig Fig. Maximum power dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn reduces the turn on time of the thyristor. Each thyristor has maximum gate voltage limit (Vgmax). It is however customary to trigger a thyristor using pulsed voltage & current. The useful gate drive area of a thyristor is then b c d e f g h.com .jntuworld. Referring to the gate drive circuit in the inset the equation of the load line is given by Vg = E . For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav curve without violating Vg Max Max or IgMax ratings. A gate non triggering voltage (Vng) is also specified by the manufacturers of thyristors. TON should be larger than the turn on time of the thyristor. All spurious noise signals should be less than this voltage Vng in order to prevent unwanted turn on of the thyristor.5: Gate characteristics of a thyristor. There are also minimum limits of Vg (Vgmin) and Ig (Igmin) for reliable turn on of the thyristor.jntuworld. The value of Pgm depends on the pulse width (TON) of the gate current pulse. These limits should not be exceeded in order to avoid permanent damage to the gate cathode junction. for a dc source E c f represents the optimum load line from which optimum values of E & Rg can be determined.

If there is a possibility of the reverse gate cathode voltage exceeding this limit a reverse voltage protection using diode as shown in Fig 4.com than 100 μs. gate negative with respect to the cathode) voltage specification. v. In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the ________________ time of the device.jntuworld. iii. Exercise 4. average power dissipation curve should be used. For TON less than 100 μs the following relationship should be maintained. A A Rg G E K E K (a) (b) Fig. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate ________________ voltage.jntuworld.6 should be used. f p = pulse frequency. The gate cathode junction also has a maximum reverse (i. Reverse saturation current of a thyristor ________________ with gate current. Kharagpur 12 www. iv. 4.6: Gate Cathode reverse voltage protection circuit.2 1) i. ii.e.com .9 ) Where δ = TON f p. The magnitude of the gate voltage and current required for triggering a thyristor is inversely proportional to the junction temperature.www. Reverse ________________ voltage of a thyristor is ________________ of the gate current. Version 2 EE IIT. δ Pgm ≤ Pgav Max ( 4. Fill in the blank(s) with the appropriate word(s) Forward break over voltage of a thyristor decreases with increase in the ________________ current.

2 watts. Its value is about 130% of VDRM. Version 2 EE IIT.9 δ Pgm ≤ Pgav ( Max ) or Pgm ≤ But Pgm = Ig Vg.5 = 0. independent. This rating is specified at a maximum allowable junction temperature with gate circuit open or with a specified biasing resistance between gate and cathode. This type of over voltage may be caused due to switching operation (i. Assuming the gate cathode voltage drop to be 1 volt.com Answer: (i) gate.www. anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand during working.5Amps.jntuworld. From Equation 4. (ii) break down. (v) nontrigger. Answer: On period of the gate current pulse is TON = δ TS = δ fs = 0.com .e. 10 4 Therefore. Kharagpur 13 www. 4. 2) A thyristor has a maximum average gate power dissipation limit of 0. However.2 watts = . Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value of the forward transient voltage that does not repeat.e. pulsed gate power dissipation limit Pgm can be used. (iv) Turn ON.5 Thyristor ratings Some useful specifications of a thyristor related to its steady state characteristics as found in a typical “manufacturer’s data sheet” will be discussed in this section. VDSM is less than the forward break over voltage VBRF. Find out the allowable peak gate current magnitude.5. It is useful for calculating the maximum RMS voltage of the ac network in which the thyristor can be used. ∴ I g Max = 1 4.4.jntuworld. (iii) increases. This type of repetitive transient voltage may appear across a thyristor due to “commutation” of other thyristors or diodes in a converter circuit.1 Voltage ratings Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i. circuit breaker opening or closing or lightning surge) in a supply network. Vg = 1V 0. It is triggered with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.5watts δ . A margin for 10% increase in the ac network voltage should be considered during calculation.4 sec = 40 μs < 100 μs. Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient voltage that a thyristor can block repeatedly in the OFF state.

RMS current rating is used as an upper limit for dc as well as pulsed current waveforms. ii. 4. This limit should not be exceeded on a continuous basis. Peak junction temperature is not exceeded RMS current limit is not exceeded Manufacturers usually provide the “forward average current derating characteristics” which shows Iav as a function of the case temperature (Tc ) with the current conduction angle φ as a parameter. Maximum average current (Iav): It is the maximum allowable average value of the forward current such that i. it is equal to the peak negative value of the ac supply voltage.7 shows different thyristor voltage ratings on a comparative scale.5.7: Voltage ratings of a thyristor. Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse transient voltage that does not repeat.e.8.2 Current ratings Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic joints. anode negative with respect to cathode) that a thyristor can with stand continuously. IA VBRR VRSM VRRM VRWM VDWM VDRM VDSM VBRF VAK Fig.jntuworld. Normally. VRSM is less than reverse break down voltage VBRR. 4. Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may occur repeatedly during reverse bias condition of the thyristor at the maximum junction temperature. leads and interfaces depends on the forward RMS current Irms.com Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.com .www. Kharagpur 14 www. However. Its value is about 130% of VRRM. Fig 4. Version 2 EE IIT.jntuworld. The current wave form is assumed to be formed from a half cycle sine wave of power frequency as shown in Fig 4.

4.jntuworld. Surge currents are assumed to be sine waves of power frequency with a minimum duration of ½ cycles.com .jntuworld. Kharagpur 15 www.com Iav Amps φ = 180° 120 100 80 60 40 20 0 ∫∫ φ = 120° φ = 60° φ = 30° φ 60° 80° TC (°C) 100° 120° 140° Fig. Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode current reaches this level. The device is assumed to be operating under rated blocking voltage. forward current and junction temperation before the surge current occurs. This rating is used in the choice of the protective fuse connected in series with the device. Manufacturers provide at least three different surge current ratings for different durations. upon removal of gate pulse.8: Average forward current derating characteristics Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the device can withstand. Otherwise. For example I sM = 3000 A for 1 cycle 2 I sM = 2100 A for 3 cycles I sM = 1800 A for 5 cycles Alternatively a plot of IsM vs. Maximum Squared Current integral (∫i2dt): This rating in terms of A2S is a measure of the energy the device can absorb for a short time (less than one half cycle of power frequency). Following the surge the device should be disconnected from the circuit and allowed to cool down.www. Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous forward current at a given junction temperature. applicable cycle numbers may also be provided. Holding Current (IH): The anode current must be reduced below this value to turn off the thyristor. Version 2 EE IIT. the device will turn off.

com Average power dissipation Pav): Specified as a function of the average forward current (Iav) for different conduction angles as shown in the figure 4.jntuworld.jntuworld. Version 2 EE IIT.com . Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below which reliable turn on of the thyristor can not be guaranteed. In the above diagram 1 φ i dθ 2π ∫o F 1 φ Pav = v i dθ 2π ∫o F F I av = ( 4. All spurious noise voltage in the gate drive circuit must be below this level. 4. Pav 60° 90° φ = 180° 30° iF ωt φ Iav Fig.11) 4.9.10 ) ( 4. Kharagpur 16 www.3 Gate Specifications Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on of the thyristor can not be guaranteed. Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which the thyristor can be guaranteed to remain OFF.9: Average power dissipation vs average forward current in a thyristor. The current wave form is assumed to be half cycle sine wave (or square wave) for power frequency.www.5. Usually specified at a given forward break over voltage. It is specified at the same break over voltage as IGT. Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate and the cathode terminals without damaging the junction.

www. v. (iv) greater. Find the corresponding rating for Φ = 60°. Kharagpur 17 www. (iii) case temperature.3 ⎞ = 2. Answer: The form factor of half cycle sine waves for a conduction angle φ is given by I F.778 ⎜ 3 4⎟ ⎝ ⎠ Since RMS current rating should not exceeded For φ = 60°. conduction angle. (ii) VRRM. ii. Maximum average current a thristor can carry depends on the ________________ of the thyristor and the ________________ of the current wave form. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180°. Exercise 4.F = RMS = Iav 1 2π 1 2π ∫ Sin θ dθ ∫ Sinθ dθ 2 o φ o φ = π φ . The ISM rating of a thyristor applies to current waveforms of duration ________________ than half cycle of the power frequency where as the ∫i2dt rating applies to current durations ________________ than half cycle of the power frequency.com .3 1) Fill in the blank(s) with the appropriate word(s) i. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted turn on of the thyristor due to ________________ voltage signals at the gate. less.jntuworld.jntuworld. Assume the current waveforms to be half cycle sine wave.1 Sin 2φ 2 1. iii. Version 2 EE IIT. iv. F. Answer: (i) switching.F = π 2 = 1885 Amps. Peak forward gate current (IGRM): The forward gate current should not exceed this limit even on instantaneous basis. F.com Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode junction should not exceed this value for gate current pulses wider than 100 μs. (v) noise 2. VRSM rating of a thyristor is greater than the ________________ rating but less than the ________________ rating. VBRR.F = 2 For φ = 180°. lightning.Cos φ ( ) 2 ∴RMS current rating of the thyristor = 1200 × π π ⎛ π . Peak non-repetitive over voltage may appear across a thyristor due to ________________ or ________________ surges in a supply network.

10.10: Turn on characteristics of a thyristor. anode current (iA) and anode cathode voltage (VAK) in an expanded time scale during Turn on. Kharagpur 18 www.6.00 Amps. The reference circuit and the associated waveforms are shown in the inset.6 Switching Characteristics of a Thyristor During Turn on and Turn off process a thyristor is subjected to different voltages across it and different currents through it. The time variations of the voltage across a thyristor and the current through it during Turn on and Turn off constitute the switching characteristics of a thyristor.9 VON vAK α Firing angle Vi iA Expanded scale Fig 4. As shown in Fig 4.10 there is a transition time “tON” from forward off state to forward on state.jntuworld. The total switching period being much smaller compared to the cycle time.1 ION vAK VON 0. 4. (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). 4.1 Turn on Switching Characteristics A forward biased thyristor is turned on by applying a positive gate voltage between the gate and cathode as shown in Fig 4. Version 2 EE IIT. These times are shown in Fig 4. 4.9 ION ION 0.com Maximum Iav for φ = 60° = 4 1200 × π π ⎛π ⎜ 3 ⎝ 3 ⎞ 4⎟ ⎠ = 679.jntuworld.www. iA and VAK before and after switching will appear flat.10 for a resistive load.1 VON td tON tr t tp Fig. ig Vi R t 0.com . + vAK ig iA t iA 0. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely.10 shows the waveforms of the gate current (ig).

This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive.6. If forward voltage is applied across the device during this period the thyristor turns on again. During this time conduction spreads over the entire cross section of the cathode of the thyristor. Fig 4. However. Version 2 EE IIT.2 Turn off Switching Characteristics Once the thyristor is on. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor.jntuworld. At the same time the voltage VAK falls from 90% of its initial value to 10% of its initial value.11 shows the variation of anode current and anode cathode voltage with time during turn off operation on an expanded scale. as the current increases. the reverse recovery time (trr) and the gate recovery time (tqr). Therefore. Time taken by this process constitute the turn on delay time of a thyristor. During turn off time.com .jntuworld. rate of change of anode voltage substantially decreases. Typical value of “td” is a few micro seconds.www. Usual values of maximum ⎝ dt ⎠ allowable di A is in the range of 20-200 A/μs. dt Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%. it is necessary to limit the rate of rise of the ⎛ di ⎞ ON state current ⎜ A ⎟ by using an inductor in series with the device. excess minority carriers from all the four layers of the thyristor must be removed. Accordingly tq is divided in to two intervals. If the anode current rises too fast it tends to remain confined in a small area. It can be turned off only by reducing the anode current below holding current. 4. Rise time (tr): For a resistive load. While for a capacitive load VAK falls rapidly in the beginning. However. For inductive load the voltage falls faster than the current. Kharagpur 19 www. and its anode current is above the latching current level the gate loses control. It is measured from the instant of application of the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls to 90% of its initial value).com Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This can give rise to local “hot spots” and damage the device. “rise time” is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. current rise and voltage fall characteristics are strongly influenced by the type of the load. The turn off time tq of a thyristor is defined as the time between the instant anode current becomes zero and the instant the thyristor regains forward blocking capability.

A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage is applied across the device. tc is called the “circuit turn off time”. The time taken for this recombination process to complete (between t3 & t4) is called the gate recovery time (tgr).jntuworld. Fast decaying reverse current during the interval t2 t3 coupled with the di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the dt device.www. The value of the anode current at time t2 is called the reverse recovery current (Irr). The time interval tq = trr + tgr is called “device turn off time” of the thyristor.com iA di A dt vAK iA ig Vi Qrr t Irr iA t Vrr Expanded scale vAK vi t vi trr tq tgr Fig. At dt time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The anode current becomes zero at time t1 and starts growing in the negative direction with the same di A till time t2. Total charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr). Up to time t2 the voltage across the device (VAK) does not change substantially from its on state value. These trapped charges are removed only by the process of recombination.11: Turn off characteristics of a thyristor.com . Version 2 EE IIT. Kharagpur 20 www. This negative current removes excess carriers from junctions J1 & J3. the thyristor regains reverse blocking capacity and VAK starts following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still exist at the junction J2 which prevents the device from blocking forward voltage just after trr. The reverse anode current reduces to the level of reverse saturation current by t3.jntuworld. after the reverse recovery time. 4. No forward voltage should appear across the device before the time tq to avoid its inadvertent turn on. This voltage must be limited below the VRRM rating of the device. However.

They also provide the value of the reverse recovery current Irr for a given IA and di A . Therefore. v. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter is of prime importance. iv.com The reverse recovery charge Qrr is a function of the peak forward current before turn off and its di for rate of decrease A . They usually employ a large number of thyristors connected in series parallel combination. However. Kharagpur 21 www. Typical turn off times of converter and inverter grade thyristors are in the range of 50-100 μs and 5-50 μs respectively. As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on the construction of the thyristor. large voltage spike due to this “snappy recovery” will appear across the device after the device turns off.com . As has been mentioned in the introduction thyristor is the device of choice at the very highest power levels.jntuworld. This helps reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher switching frequency).jntuworld. overcurrent and unintended turn on for each thyristor. Version 2 EE IIT. Total turn on time of a thyristor can be divided into ________________ time ________________ time and ________________ time. in a fast recovery “inverter grade” thyristor the interval t2 t3 is negligible compared to the interval t1 t2. However. For maximum utilization of the device capacity it is important that each device in this series parallel combination share the blocking voltage and on state current equally. Exercise 4. Special equalizing circuits are used for this purpose. A thyristor can be turned off by bringing its anode current below ________________ current and applying a reverse voltage across the device for duration larger than the ________________ time of the device. During rise time the rate of rise of anode current should be limited to avoid creating local ________________.www.4 1) i. Fill in the blank(s) with the appropriate word(s) A thyristor is turned on by applying a ________________ gate current pulse when it is ________________ biased. In normal recovery “converter grade” thyristor they are almost equal for a specified forward current and reverse recovery current. iii. ii. Manufacturers usually provide plots of Qrr as a function of di A dt dt different values of peak forward current. Reverse recovery charge of a thyristor depends on the ________________ of the forward current just before turn off and its ________________. suitable protection arrangement must be made against possible overvoltage. At the highest power level (HVDC transmission system) thyristor converters operate from network voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps of current. Alternatively Irr can be evaluated from the given Qrr dt characteristics following similar relationships as in the case of a diode.

jntuworld.10 find expressions for (i) turn on power loss and (ii) conduction power loss of the thyristor as a function of the firing angle ∝. rate of decrease (vi) faster 2. Vak = 2 Vi Sin ∝ ⎛1 . where V has been neglected. Answer: (i) positive. Vi = RMS value of supply voltage.www. (ii) delay. Instantaneous current through the device during this period is 2 Vi Sin ωt ia = R ∝ <ωt≤ π R Where tON & VH have been neglected for simplicity. (iii) hot spots (iv) holding. Current after the thyristor turns on for a resistive load is I ON = VON R = 2 Vi R Sin ∝ Neglecting delay and spread time and assuming linear variation of voltage and current during turn on ⎞ . Inverter grade thyristors have ________________ turn off time compared to a converter grade thyristor. With reference to Fig 4. Also assume constant on state voltage VH across the thyristor.t ⎜ H t ON ⎟ ⎝ ⎠ 2 Vi Sin ∝ R ∴ Total switching energy loss ia = E ON = ∫ t ON t t ON t ON 2Vi 2 ⎛1 . forward. spread. PON = E ON f = Vi 2 Sin 2 ∝ t ON f 3R (ii) If the firing angle is ∝ the thyristor conducts for π-∝ angle.com . turn off. Neglect turn on delay time and spread time and assume linear variation of voltage and current during turn on period.com vi. If the supply frequency is f then average turn on power loss is given by. rise. (v) magnitude. ∴ total conduction energy loss over one cycle is Version 2 EE IIT.t ⎞ t Sin 2 ∝ ∫ dt ⎜ t ON ⎟ t ON o o R ⎝ ⎠ 2Vi 2 t 2⎞ Vi 2 ⎛ = Sin 2 ∝ ON ⎜1 .jntuworld. Answer: (i) For a firing angle ∝ the forward bias voltage across the thyristor just before turn on is VON = 2Vi Sin ∝ .⎟ = Sin 2 ∝ t ON R 2 ⎝ 3⎠ 3R v ak i a dt = EON occurs once every cycle. Kharagpur 22 www.

Thus a triac is similar to two back to back (anti parallel) connected thyristosr but with only three terminals.7 The Triac The Triac is a member of the thyristor family.com E C = ∫ ∝ Vak i a dt = ω πω 1 π V ω ∫α H 2 Vi Sinθ dθ = R 2 Vi VH (1 + Cos ∝ ) ωR ∴ Average conduction power loss = PC = E cf = 2 Vi VH (1 + Cos ∝ ) 2πR Fuse i1 Vi if 220 V 50 HZ 3. The three terminals are marked as MT1 (Main Terminal 1).7. But unlike a thyristor which conducts only in one direction (from anode to cathode) a triac can conduct in both directions. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle ∝ after the positive going zero crossing of Vi while T3 & T4 are fired ∝ angle after the negative going zero crossing of Vi. As the Triac can conduct in both the directions the terms “anode” and “cathode” are not used for Triacs.12 (b) the gate terminal is near MT1 and is connected to both Version 2 EE IIT.jntuworld. Therefore.1 Construction and operating principle Fig. They are extensively used in residential lamp dimmers. 4.www. If all thyristors have a turn off time of 100 μs. a triac can be categorized as a minority carrier. the conduction of a triac is initiated by injecting a current pulse into the gate terminal. find out maximum allowable value of ∝. a bidirectional semi-controlled device. T3 & T4 are subjected to a negative voltage of –Vi. As in the case of a thyristor. MT2 (Main Terminal 2) and the gate by G. heater control and for speed control of small single phase series and induction motors. The triac turns off only when the current through the main terminals become zero.jntuworld.Max) ≥ ωt off ∴ ∝ Max = 178. As shown in Fig 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac respective.com . The gate looses control over conduction once the triac is turned on. Kharagpur 23 www. 4. 4. Answer: As T1 & T2 are fired at an angle ∝ after positive going zero crossing of Vi. Since this voltage remain negative for a duration (π-∝) angle (after which –Vi becomes positive) for safe commutation 0 ( π .2 .

Trigger mode 4 is usually averded. G positive with respect to MT1 The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.www. G positive with respect to MT1 2. there are four possible electrode potential combinations as given below 1. MT1 MT2 N3 N2 N2 P2 G P2 N1 P1 N3 G MT1 (a) P2 N1 N4 P1 MT2 (b) Fig.jntuworld.com . Kharagpur 24 www.jntuworld. G negative with respect to MT1 3. MT2 positive with respect to MT1. However. MT2 negative with respect to MT1. 4. G negative with respect to MT1 4.13 (a) and (b) explain the conduction mechanism of a triac in trigger modes 1 & 3 respectively. MT2 negative with respect to MT1. Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages. for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used. Version 2 EE IIT.12: Circuit symbol and schematic construction of a Triac (a) Circuit symbol (b) Schematic construction. MT2 positive with respect to MT1. Similarly MT1 is connected to N2 and P2 regions while MT2 is connected to N4 and P1 regions.com N3 and P2 regions by metallic contact. Fig 4.

When the gate current has injected sufficient charge into P2 layer the triac starts conducting through the P1 N1 P2 N2 layers like an ordinary thyristor.com G IG IG MT1 (-) N2 IG P2 N1 P1 MT1 (+) N3 IG P2 N1 P1 N4 MT2 (+) MT2 (-) (a) (b) Fig. 4.www. (b) Mode – 3 . In the trigger mode-3 the gate current Ig forward biases the P2 P3 junction and a large number of electrons are introduced in the P2 region by N3. In trigger mode-1 the gate current flows mainly through the P2 N2 junction like an ordinary thyristor.com . Finally the structure P2 N1 P1 N4 turns on completely.jntuworld. Kharagpur 25 www.13: Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode – 1 . Version 2 EE IIT.jntuworld.

com .14: Steady state V – I characteristics of a Triac From a functional point of view a triac is similar to two thyristors connected in anti parallel. in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the structure of the triac. it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. 4. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. current and frequency ratings of triacs are considerably lower than thyristors.jntuworld. Curves relating the device dissipation and RMS on state current are also provided for different conduction angles.2 Steady State Output Characteristics and Ratings of a Triac I Ig3 > Ig2 > Ig1 > Ig = 0 -VBO VBO -Ig3 < Ig2 < Ig1 V Ig = 0 Fig. the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. 4. Triacs also have a larger on state voltage drop compared to a thyristor. However. the voltage. most of the thyristor characteristics apply to the triac (ie. Kharagpur 26 www. Therefore. Therefore. latching and holding current).com 4. As shown in Fig. with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (VBO) of the device.www.7. Version 2 EE IIT.jntuworld. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig 4. As such.15.14. However.

The triac should be triggered carefully to ensure safe operation.3 Triac Switching and gate trigger circuit Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. Kharagpur 27 www. A rise time of about 1 μs will be desirable. If such a load (e. For phase control application. As a result the triacs are operated only at power frequency. However. Such a triac gate triggering circuit using a “diac” and an R-C timing network is shown in Fig 4.15: RMS ON state current Vs maximum case temperature.com A 200 Bidirectional ON state current (RMS) 150 100 For all conduction angles 50 0 20° 40° 60° 80° 100° 120° Maximum allowable case temperature (TC) Fig. °C 4. At the current zero instant (when the triac turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that instant. To prevent such condition an R-C snubber is generally used across a triac. 4. turn off of a triac is extremely sensitive to temperature variation and may not turn off at all if the junction temperature exceeds certain limit.www. Similar problem occurs when a triac is used to dt control the power to a resistive element which has a very low resistance before normal working condition is reached. The resulting dv may turn on the triac again. Switching characteristics of a triac is similar to that of a thyristor. Problem may arise when a triac is used to control a lagging power factor load.7.16. To ensure ‘clean turn ON’ the trigger signal must rise rapidly to provide the necessary charge. incandescent filament lamp) is switch on at full supply voltage very large junction capacitance charging current will turn ON the device.g. The rate of rise of this voltage is restricted by the triac junction capacitance only.com . Version 2 EE IIT.jntuworld. the triac is switched on and off in synchronism with the mains supply so that only a part of each half cycle is applied across the load.jntuworld.

16: Triac triggering circuit using a diac. ii. A Triac operates either in the ________________ or the ________________ quadrant of the i-v characteristics. R1.com LOAD R1 D1 R R2 V1 C1 C Fig.com . The voltage drop across diac D1 increases until it reaches its break over point. Kharagpur 28 www. In this circuit as Vi increases voltage across C1 increases due to current flowing through load. Fill in the blank(s) with the appropriate word(s) A Triac is a ________________ minority carrier device A Triac behaves like two ________________ connected thyristors. Version 2 EE IIT.jntuworld. vi.www. 4. iii. R2 and C1.5 1) i. The gate sensitivity of a triac is maximum when the gate is ________________ with respect to MT1 while MT2 is positive with respect to MT1 or the gate is ________________ with respect to MT1 while MT2 is negative with respect to MT1 iv. As D1 conducts a large current pulse is injected into the gate of the triac. In the ________________ quadrant the triac is fired with ________________ gate current while in the ________________ quadrant the gate current should be ________________. The maximum possible voltage and current rating of a Triac is considerably ________________ compared to thyristor due to ________________ of the two current carrying paths inside the structure of the triac. By varying R2 the firing can be controlled from zero to virtually 100%.jntuworld. Exercise 4. v.

com . Kharagpur 29 www. dt ________________ are used viii. For “clean turn ON” of a triac the ________________ of the gate current pulse should be as ________________ as possible. third.jntuworld. (viii) rise time. Version 2 EE IIT. (vii) R-C shubbers. negative. negative (vi) lower.www. (iv) first. interaction. To avoid unwanted turn on of a triac due to large dv across triacs.com vii. (iii) positive. third. positive. (v) first. small. (ii) anti parallel.jntuworld. Answer: (i) bidirectional.

P. Tata McGrow Hill Publishing Company Limited. “Power Electronics”. 2.S. “Power Electronics” Khanna Publishers Version 2 EE IIT. Bimbhra.com References 1. Kharagpur 30 www. Dr. Dr.C. Sen.com .jntuworld.jntuworld. P. New Delhi.www.

This is called gate triggering. A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. A thyristor is turned off by bringing the anode current below holding current and simultaneously applying a negative voltage (cathode positive with respect to anode) for a minimum time called “turn off time”. the cathode and the gate. Kharagpur 31 www. low frequency line commutated application. In the reverse direction a thyristor blocks voltage up to reverse break down voltage. light. A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage. It can be turned on in either half cycle by either a positive on a negative current pulse at the gate terminal. For this reason thyristors are preferred for high power. A triac has three terminals like a thyristor. A thyristor has a very low conduction voltage drop but large switching times.com . It can be turned off only by bringing the anode current below holding current. three terminal. • • • • Version 2 EE IIT. motors) control applications. Triacs are extensively used at power frequency ac load (eg heater. It can block voltages in both directions and conduct current in both directions. A thyristor can block voltage of both polarity but conducts current only from anode to cathode.www.jntuworld. semi-controlled device. A triac is functionally equivalent to two anti parallel connected thyristors. The three terminals of a thyristor are called the anode. After a thyristor turns on the gate looses control. minority carrier. After turn on the voltage across the thyristor drops to a very low value (around 1 volt).jntuworld.com Lesson Summary • • • • • • • • Thyristor is a four layer.

com .com Practice Problems and Answers Version 2 EE IIT. Kharagpur 32 www.jntuworld.www.jntuworld.

Find out the ∫ i 2 dt rating of the 2 thyristors.jntuworld.jntuworld.com 1. find out the turns ratio N1/N2 and the value of R.5 watts and a maximum allow able gate voltage limit of 10 volts.2 Ω and negligible armature inductance. The thyristor Th is triggered using the pulse transformer shown in figure. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. Version 2 EE IIT. The motor has on armature resistance of 0. The thyristors are fired at a firing angle ∝ = 0° when motor runs at rated speed. The thyristor has maximum average gate power dissipation limit of 0. (ii) forward and reverse leakage currents.www. Th 15 V • • R iB N1 N2 2. Why is it necessary to maximize the peripheral contact area of the gate and the cathode regions? A thyristor used to control the voltage applied to a load resistance from a 220v. The protective fuse in series with the motor is designed to disconnect the motor within 1 cycle of fault. Fuse i1 Vi if 220 V 50 HZ 3. Kharagpur 33 www. The pulse transformer operates at 10 KHZ with a duty cycle of 40%.com . 4. Assuming ideal pulse transformer. Find out the peak surge current rating of the thyristors such that they are not damaged due to sudden loss of field excitation to the motor. Explain the effect of increasing the magnitude of the gate current and junction temperature on (i) forward and reverse break down voltages.

jntuworld.com .com 50HZ single phase ac supply has a maximum value of the di a dt di a dt rating of 50 A / μs. Find out the limiting inductor to be connected in series with the load resistance. The main thyristor THM has a turn off time off 50μs and maximum dv rating of 500v/ μs. Kharagpur 34 www. Version 2 EE IIT. Find out a suitable value of C for safe dt commutation of THM.jntuworld.www. In a voltage commutated dc – dc thyristor chopper the main thyristor THM is commutated by connecting a pre-charged capacitor directly across it through the auxiliary thyristor THA as shown in the figure. THM + C THA 20 A 200V 200V 5.

www.jntuworld.com Answers to Practice Problems Version 2 EE IIT.jntuworld.com . Kharagpur 35 www.

10 i go + 0. Figure shows the equivalent gate drive circuit of the thyristor. ∴ instantaneous gate power dissipation limit can be used.5 ∴ i go 2 R . <100μs. 200V 200V 2. Reverse leakage current increases with both the junction temperature and the magnitude of the gate current.jntuworld.5 = 0 Version 2 EE IIT. Reverse break down voltage is independent of the gate current magnitude but decreases with increasing junction temperature.2 Max = = 0.5 Vg i g Max = Pav Let the operating Vg and ig be Vgo & igo ∴ Vgo = 10 .R i g The diode D clamps the gate voltage to zero when E goes negative.i go R Vgo i go = 0. For this circuit one can write E = R i g + Vg OR Vg = E . Now for ig = O.com 1. Since Vg Max = 10 v 10 = 1.www.5 E = 10 v But E = N2 N1 15 ∴ N2 N1 = 15 Gate pulse width = 0.com . i. Kharagpur 36 www.jntuworld.4 × 10-4 Sec = 40μs. Forward break down voltage reduces with increasing gate current.5 watts δ 0. THM + C THA 20 A ii.4 For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E – igR = 10 – igR should be tangent to the maximum power dissipation curve Vg ig = 0. ∴ 0. Forward leakage current is independent of the gate current magnitude but increases with junction temperature. Vg = E. It increases with junction temperature up to certain value of the junction temperature and then falls rapidly with any further increase in temperature.

5 = 50 Ω . If there is a sudden loss of field excitation back emf will become zero and armature current will be limited solely by the armature resistance. cycle of the fault occurring. the i t rating of the thyristor should be The fuse blows within 1 Version 2 EE IIT.go di g ( vgo.igo ) i g ( vgo.com Since Vg = 10 – ig R is tangent to Vg ig = 0.10i go + 0. igo) = -R ∴ -R = ∴R = ∴ i go 2 × dv g .www. 220 2 The peak magnitude of the fault current will be = 1556(Amps) .01 Back emf.5 at Vgo.com . Kharagpur 37 www.1 0.5 = go 2go = 2 i go i go i go or 10i go = 1 or i go = 0. Figure shows the armature voltage (firm line) and armature current of the motor under normal operating condition at rated speed.5 = 0 i go 2 i go 2 ∴ R = 0. igo. Therefore the thyristors must withstand 2 the fault for at least 1 cycle. . 2 2 Therefore.igo ) i go v go v i 0.jntuworld. Va t ia (normal) t ia (with field loss) t 3. Slope of the tangent of Vgig = 0.jntuworld.2 It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM > 2 1556 Amps.5 = 0.5 at (Vgo.vg v = = .5 .

However. dt The maximum di a dt will occur when the thyristor is triggered at ∝ = 90°. if rate of increase of anode current is lager than the rate of increase of the current conduction are.22 × 10 -6 H = 6. Kharagpur 38 www.jntuworld. if the contact area between the gate and the cathode is large a thyristor will be able to handle a di relatively large a without being damaged.jntuworld.21× 10 4 A 2 Sec 2 4.com 2 ∫ i dt = ∫ (1556 Sin 100 π t ) 0 10-2 2 = (1556 ) 2 2 ∫ 10-2 0 [1 - Cos 200 π t ] dt 2 = 1 × 10 -2 (1556 ) = 1. However.www. At the beginning of the turn on process the thyristor starts conducting through the area adjacent to the gate. This area spreads at a finite speed. t Version 2 EE IIT. Then L Since di a di a = dt 2 × 220 Sin 90 0 dt Max = 50 × 10 6 A Sec L min = 2 × 220 = 6. This may lead to thyristor failure due to excessive local heating.com .22 μH ⎛ di a ⎞ ⎜ dt ⎟ ⎝ ⎠ Max VC vTHM toff 200 V dv / dt t iC 20 Amps. the current density increases with time.

voltage across the main thyristor (VTHM) and the capacitor current ic.www. Version 2 EE IIT. From dv i = c figure c dt dv = 500 v μs Now ic = 20 Amps & dt Max ∴ C Min = ic dv dt = Max 20 -8 F = 0.04 μF 6 = 4 × 10 500×10 The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial value of 200v.jntuworld. Now C dv c = i c = 20 dt 20 × Δt ∴ Δv c = c ∴ 200 = Δv = 200 . Kharagpur 39 www. Figure shows the waveforms of voltage across the capacitor (vc). This time must be greater than the turn off time of the device. the voltage across THM is the negative of the capacitance voltage.com .0 = 200 Δt = t off 20 × 50 × 10 -6 C 20 × 50 × 10 -6 ∴C = = 5 μF 200 For safe commutation of THM the higher value of C must the chosen ∴ the required value of C = 5 μF.jntuworld. As soon as THA is turned on the load current transfer from THM to C.com 5.

Kharagpur 1 www.com Module 1 Power Semiconductor Devices Version 2 EE IIT.jntuworld.jntuworld.com .www.

www.com .com Lesson 5 Gate Turn Off Thyristor (GTO) Version 2 EE IIT.jntuworld. Kharagpur 2 www.jntuworld.

com Instructional objective On completion the student will be able to • • • • • • Differentiate between the constructional features of a GTO and a Thyristor. Version 2 EE IIT. Draw the block diagram of a GTO gate drive unit and explain the functions of different blocks.jntuworld.com . Kharagpur 3 www. Interpret the manufacturer’s data sheet of a GTO.jntuworld. Explain the turn off mechanism of a GTO. Draw and explain the switching characteristics of a GTO.www. Differentiate between the steady state output and gate characteristics of a GTO and a thyristor.

These are called “Asymmetric GTOs”. operating principle and characteristic of “Asymmetric GTOs” only. A bulky and expensive “commutation circuit” had to be used to ensure proper turning off of the thyristor. Here. 4000Amp) with the largest available thyristor.2 Constructional Features of a GTO Fig 5. has always suffered from the disadvantage of being a semi-controlled device. Kharagpur 4 www. where the main current does not naturally becomes zero. Devices with reverse blocking capability equal to their forward voltage ratings are called “symmetric GTOs”.e.www. they are designed to turn off when a negative current is sent through the gate. on the other hand. bipolar) device. Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and DC to DC converter circuits.com Introduction The thyristor has reigned supreme for well over two decades in the power electronics industry and continues to do so at the very highest level of power. The development of the Gate Turn off thyristor (GTO) has addressed these disadvantages of a thyristor to a large extent.1 shows the circuit symbol and two different schematic cross section of a GTO. This proved to be particularly inconvenient in DC to AC and DC to DC conversion circuits. The switching speed of the device was also comparatively slow even with fast inverter grade thyristor. Like thyristor. Reverse conducting GTOs (RC-GTO) constitute the third family of GTOs. thereby causing a reversal of the gate current. Although it could be turned on by applying a gate pulse but to turn it off the main current had to be interrupted.jntuworld. Although it has made a rather late entry (1973) into the thyristor family the technology has matured quickly to produce device comparable in rating (5000V. During conduction. A relatively high gate current is need to turn off the device with typical turn off gains in the range of 4-5. Several different varieties of GTOs have been manufactured. the GTO is a current controlled minority carrier (i. Version 2 EE IIT. the device behaves just like a thyristor with very low ON state voltage drop. a GTO is integrated with an anti-parallel freewheeling diode on to the same silicon wafer. However. GTOs differ from conventional thyristor in that.com .jntuworld. This lesson will describe the construction. however. 5. It. the most poplar variety of the GTO available in the market today has no appreciable reverse voltage (20-25v) blocking capacity.

In the first method. However. The most popular design features multiple segments arranged in concentric rings around the device center. In order to block several kv of forward voltage the doping level of this layer is kept relatively low while its thickness is made considerably higher (a few hundred microns).1 (b). heavily doped n+ layers are introduced into the p+ anode layer.jntuworld. For good turn on properties the efficiency of this anode junction should be as high as possible requiring a heavily doped p+ anode region.www. Therefore. the break down voltage of the function J3 is low (typically 20-40V). Kharagpur 5 www. p+ n+ p+ n p n+ p+ Anode Contact J1 Buffer Layer J2 J3 p+ n np n+ n+ G K (a) G n+ n+ G C (b) (c) C Fig. in order to optimize current turn off capability. The junction between the n base and p+ anode (J1) is called the “anode junction”. a GTO is also a four layer three junction p-n-p-n device. turn off capability of such a GTO will be poor with very low maximum turn off current and high losses. The p type gate region has conflicting doping requirement. Like a thyristor. They make contact with the same anode metallic contact. Due to presence of these “anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down Version 2 EE IIT. the n+ cathode layer is highly doped. A 3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a accessed via a common contact. (c) Buffer layer GTO structure. the gate cathode junction must be highly interdigitated. Additionally. Byond the maximum allowable forward voltage either the electric field at the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully depletes. To maintain good emitter efficiency the doping level of this layer should be low.com . In order to obtain high emitter efficiency at the cathode end. allowing its electric field to touch the anode emitter (punch through). There are two basic approaches to solve this problem. Therefore. 5.jntuworld.1: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol. This is the classic “anode shorted GTO structure” as shown in Fig 5. (b) Anode shorted GTO structure. the doping level of this layer is highly graded.com A Anode Short. on the other hand. Consequently. electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. from the point of view of good turn off properties. resistively of this layer should be as low as possible requiring the doping level of this region to be high. The maximum forward blocking voltage of the device is determined by the doping level and the thickness of the n type base region next.

1 (c). This is called the “Transparent emitter structure” and is shown in Fig 5. 5. Kharagpur 6 www. negative.jntuworld.type base and the anode. A GTO has _______________ layers and _______________ terminals. a moderately doped n type buffer layer is juxtaposed between the n. Exercise 5. In the other method. A GTO can be turned on by injecting a _______________ gate current and turned off by injecting a _______________ gate current. The reverse voltage blocking capacity of a GTO is small due to the presence of _______________. The anode shorts of a GTO improves the _______________ performance but degrades the _______________ performance. helps to reduce its width drastically. However. Therefore. (iv) turn off. Version 2 EE IIT.com .jntuworld. iv. the p-n-p-n structure of a GTO can be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerative configuration as shown in Fig 5. (v) anode shorts. A GTO is a _______________ controlled _______________ carrier device. (ii) four. turn on. iii. Therefore. v. In addition a large number of “anode shorts” reduces the efficiency of the anode junction and degrades the turn on performance of the device. In particular.com voltage of junction J3 (20-40 volts maximum). three. this buffer layer in a conventional “anode shorted” GTO structure would have increased the efficiency of the anode shorts.1 Fill in the blank(s) with the appropriate word(s) i.2. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection.base region from triangular to trapezoidal and in the process. Answer: (i) current. (iii) positive. in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. As in the case of a power diode and BJT this relatively high density buffer layer changes the shape of the electric field pattern in the n. ii. minority.3 Operating principle of a GTO GTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can be explained in a manner similar to that of a thyristor. the density of the “anode shorts” are to be chosen by a careful compromise between the turn on and turn off performance.www.

Once the device has been turned on in this manner. Under this condition both ∝n and ∝p are small and (∝p + ∝n) <<1. Normally.com A p n p Hole current Electron G current (a) n p n C IK C iB iC2 αn IA A p αp iC1 IG iB2 G n p A G n p n C (b) G p n p A Hole current Electron current Fig 5. The device is said to be in the forward blocking mode. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). The current gain ∝ of silicon transistors rises rapidly as the emitter current increases.jntuworld. As ∝n + ∝p approaches unity the anode current tends to infinity. any mechanism which causes a momentary increase in the emitter current can be used to turn on the device.1) ( 5.3) ( 5. To turn the device on either the anode voltage can be raised until ICBO1 and ICBO2 increases by avalanche multiplication process or by injecting a gate current. Reversion to the blocking mode occurs only when the anode current is brought below the “holding current” level. From the “two transistor analogy” (Fig 5. Physically as ∝n + ∝p nears unity the device starts to regenerate and each transistor drives its companion into saturation. Version 2 EE IIT. the external gate current is no longer required to maintain conduction.com .2: Current distribution in a GTO (a) During turn on. all junctions assume a forward bias and total potential drop across the device becomes approximately equal to that of a single p-n diode.2 (a)) of the GTO structure one can write. Kharagpur 7 www.www. i C1 = ∝p I A + ICBO1 i B1 = i C 2 = ∝n I k + ICBO2 I k = I A + IG and IA = i B1 + i C1 Combining I A = ∝n IG + ( iCBO1 + i CBO2 ) 1.4 ) With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2 are small. Therefore.jntuworld. since the regeneration process is self-sustaining.2 ) ( 5. (b) During turn off. Once in saturation. The anode current is restricted only by the external circuit. this is done by injecting current into the p base region via the external gate contract.( ∝n + ∝p ) ( 5.

2 Fill in the blank(s) with the appropriate word(s) i. A conducting GTO reverts back to the blocking mode when the anode current falls below _______________ current.2 (b)).jntuworld. although the cathode current has ceased the anode to gate current continues to flow (Fig 5.com . After a GTO turns on the gate current can be _______________. ii. At this point the device once again starts blocking forward voltage. “Anode shorts” help to reduce the _______________ current in a GTO. extracted from the p base through the gate metallization into the gate terminal (Fig 5. v. When the last filament disappears. cathode. The holes injected from the anode are. However. “Current filaments” produced during the turn off process of a GTO can destroy the device by creating local _______________.www. therefore. (v) tail. Kharagpur 8 www. iv. Once the tail current has completely disappeared does the device regain its steady state blocking characteristics. (iii) negatively. Exercise 5. The resultant voltage drop in the p base above the n emitter starts reverse biasing the junction J3 and electron injection stops here. iii. This “tail current” then decays exponentially as the n base excess carriers reduce by recombination. (ii) holding. The process originates at the periphery of the p base and the n emitter segments and the area still injecting electron shrinks. To turn off a conducting GTO the gate terminal is biased _______________ with respect to the _______________. Version 2 EE IIT. Answer: (i) removed.2 (b)) as the n base excess carriers diffuse towards J1. electron injection stops completely and depletion layer starts to grow on both J2 and J3. This is the most critical phase in the GTO turn off process since highly localized high temperature regions can cause device failure unless these current filaments are quickly extinguished.jntuworld. “Anode Shorts” (or transparent emitter) helps reduce the tail current faster by providing an alternate path to the n base electrons to reach the anode contact without causing appreciable hole injection from anode. (iv) hot spot.com To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode. The anode current is crowded into higher and higher density filaments in most remote areas from the gate contact.

Kharagpur 9 www. if the gate current is not sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable anode current.3 (a).3 (b) shows the gate characteristics of a GTO. This condition is not dangerous for the GTO provided the avalanche time and current are small. Increasing the value of this resistance reduces the forward blocking voltage of the GTO.1Steady state output and gate characteristics + VAK IA IA IG IL VBRR VBRF + IL VAK vg (a) vg IG Min Max (b) Fig. The zone between the min and max curves reflects parameter variation between individual GTOs. (b) Gate characteristics. VG in this case is much higher. Asymmetric GTOs have small (2030 V) reverse break down voltage. These characteristics are valid for DC and low frequency AC gate currents.3: Steady state characteristics of a GTO (a) Output characteristics. At least.4 Steady state and dynamic characteristics of a GTO 5. a low value resistance must be connected across the gate cathode terminal. The gate voltage during this period must remain negative.www. It should be noted that a GTO can block rated forward voltage only when the gate is negatively biased with respect to the cathode during forward blocking state. dt dt Version 2 EE IIT. The forward leakage current is also considerably higher.jntuworld. They do not give correct voltage when the GTO is turned on dI with high dia and G . In fact.com 5.jntuworld. Fig 5. This may lead the device to operate in “reverse avalanche” under certain conditions. However.com . the latching current of a GTO is considerably higher than a thyristor of similar rating. This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.4. 5.

Within a further time interval tr they reach 10% of their initial value and 90% of their final value respectively. When the GTO is off the anode current is zero and VAK = Vd. A substantial gate current ensure that all GTO cathode segments are turned on simultaneously and within a short time. It should be noted that large value of ig (IgM) increases maximum permissible on state A dt and dig are required during td and tr only. Kharagpur 10 www. High value of I gM and dig at turn on reduces these times and dt di .1VD td Ig Vg tr dig/dt ∫∫ Itail t ∫∫ IGM ∫∫ ts IG tf ttail QgQ IgQ digQ dt Fig. A minimum ON time period tON (min) is required for homogeneous anode current conduction in the GTO. called the turn on delay time td.com 5. Both td and maximum permissible on state di A dt much gate current dependent. To turn on the GTO.9VD VD di dt ∫∫ IL 0.4.www. 5.2 Dynamic characteristics of a GTO iA.1IL VDM Vd VD RL IL di/dt limiting L ig vg t VgR tON 0.jntuworld. Fig 5. After this time period both vg and ig settles down to dt their steady value. There is a delay between the application of the gate pulse and the fall of anode voltage.com .9IL VT 0. a positive gate current pulse is injected through the gate terminal. VAK 0.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching circuit shown on the right hand side.4: Switching characteristics of a GTO. tr is called the are very current rise time (voltage fall time). Version 2 EE IIT.jntuworld. After this time the anode voltage starts falling while the anode current starts rising towards its steady value IL. This time is also necessary for the GTO to be able to turn off its rated anode current.

GTOs have typically low turn off gain in the range of 4-5. both the gate cathode and the anode cathode voltage starts rising towards their final value while the anode current starts decreasing towards zero. At this point VAK starts rising rapidly and exceeds the dc voltage Vd (VdM) (due to resonance of snubber capacitor with di limiting inductor) before setting dt down at its steady value Vd . With the application of the negative bias the gate current starts growing in the negative direction.jntuworld. VAK does not start to rise appreciably till tf. Version 2 EE IIT. A typical gate drive arrangement for a large power GTO is show in Fig 5. At this point both the junctions J2 & J3 of the GTO starts blocking voltage. Consequently. Reinforce the blocking state of the device by a negative gate voltage. A GTO should not be retriggered within a minimum off period off (min) to avoid the risk of failure due to localized turn ON.4. The storage time increases di with the turn off anode current and decrease with gQ .www.5. Turn the GTO off with a high negative gate current pulse. • • • • Turn the GTO on by means of a high current pulse (IGM) Maintain conduction through provision of a continuous gate current (IG. During storage time the load current at dt the cathode end is gradually diverted to the gate terminal. the anode voltage. However.current or the gate voltage does not change appreciably from their on state levels for a further time period called the storage time (ts). At the end of the storage time gate current reaches its negative maximum value IgQ. 5.3 GTO gate drive circuit A GTO gate drive has to fulfill the following functions.jntuworld.com To turn off a GTO the gate terminal is negatively biased with respect to the cathode. At the end of current fall time “tf” the anode current reaches 10% of its initial value after which both the anode current and the gate current continues to flow in the form of a current tail for a further duration of ttail. A GTO is normally used with a R-C turn off snubber. also known as the “back-porch current”).com . Therefore. Kharagpur 11 www.

The top switch T1 sends positive gate pulse to the GTO gate.com H.DC to AC INV.5 (b) shows the circuit implementation of the output stage. (a) Block diagram. These optical signals are converted to electrical signals by a optical electrical converter. H.5 (a) it is assumed that there is a potential difference of several kVs between the master control and individual gate units.C2 acts almost as a short circuit and Version 2 EE IIT.F. Kharagpur 12 www. These electrical signals through the control logic then produces the ON and OFF signal for the out put stage which in turn sends positive and negative gate current to the GTO. (b) Circuit diagram of the output stage In the block diagram of Fig 5.www.jntuworld. Depending on the requirement the control logic may also supervise GTO conduction by monitoring the gatecathode voltage. At the instant of turn on of T1 . Fig 5.com . B & C) arrangement. The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic cables. Power supply for the Gate drive units are derived from a common power supply through a high frequency SMPS (Blocks A.F.F TXF H.jntuworld. AC to DC Rectifier Output Stage A E Optical B C F Control Logic D Fiber optic cable Electrical Optical Electrical Converter + (a) A R1 R2 C2 + - ON T1 G OFF (b) T2 + R3 K Fig. 5.5: Gate drive circuit of a GTO. Any fault is relayed back via fiber optic cable to the master control.

com . To ensure that all GTO cathode segments are turned on simultaneously the magnitude of the _______________ current should be _______________. However. (x) forward blocking.com the positive gate current is determined by the parallel combination of R1 and R2. Exercise 5. (vii) current. iv. the ON state resistance of T2 is utilized for this purpose. ix. vii. (iv) gate. (vi) cathode. The _______________ current and forward _______________ current of a GTO are considerably higher compared to a thyristor. After the current fall time during turn off of a GTO the anode current continuous for some more time in the form of a _______________. a large number of switches are connected in parallel to obtain the required current rating of T2. (iii) asymmetric. A low value resistance R3 is connected between the gate and the cathode terminals of the GTO to ensure minimum forward blocking voltage. High value of gate current and dig/dt enhances the _______________ capability of a GTO during turn on. Kharagpur 13 www. The gate drive unit of a GTO should provide continuous positive gate _______________ during ON period and continuous negative gate _______________ during OFF period.www. Instead. v. (v) di/dt.3 Fill in the blank(s) with the appropriate word(s) i. Version 2 EE IIT. leakage. at steady state only R1 determines the gate current IG. vi. gate. In practice. (ix) current. x. During storage time the load current in a GTO is diverted from the _______________ to the _______________ terminal. GTOs have low turn off _______________ gain. no external resistance is used in series with T2.jntuworld. In the gate drive unit of a GTO a low value resistance is connected between the gate and the cathode terminals to ensure minimum _______________ voltage. (ii) transistor. Reverse blocking voltage of _______________ GTO is small. high. If the gate current is insufficient a GTO can operate as a low gain _______________. Answer: (i) latching. (viii) current tail. relatively large negative gate current flows during turn off. ii. The bottom switch T2 is used for biasing the GTO gate negative with respect to the cathode. voltage. viii.jntuworld. Since. iii.

com 5.jntuworld. Version 2 EE IIT. For all asymmetric GTOs this value is in the range of 20-30 V. since it is determined by the gate cathode junction break down voltage. Kharagpur 14 www. the gate voltage must remain negative during this time. VRRM rating may be exceeded for a short time without destroying the device. Due to the anode shorted structure of the GTO the anode – base junction (J1) does not block any reverse voltage. This “reverse avalanche” capability of the GTO is useful in certain situations as explained in Fig 5. 5.6 (a).1Steady state voltage and current rating VDRM: It is the maximum repetitive forward voltage the GTO can block in the forward direction assuming line frequency sinusoidal voltage waveform.jntuworld.IG1) is transferred to the snubber capacitance of G1 and the voltage across G1 (VG1) starts increasing. dt VRRM: It is the maximum repetitive reverse voltage the GTO is able to withstand. D2 is forward biased. Manufactures usually provide the forward voltage withstanding capacity of the GTO as a functions of the gate cathode reverse voltage (and /or resistance) for a given forward dv . current waveforms. However. However.www. Unlike VDRM.6: Reverse avalanche capability of a GTO (a) Voltage source inverter phase leg. due to the forward recovery voltage of D2 (Vfr) the reverse voltage across G2 may exceed VRRM rating of G2 and drive it into reverse avalanche. When if becomes equal to the dc link voltage VD .6. VG1 IG1 VD VG1 G1 D1 IL VD VG2 G2 D2 ID2 VG2 IG1 VG1 IL ID2 IL t Vfr > VRRM IG1 VD t (a) (b) Fig. In the voltage source inverter phase leg shown in Fig 5. The difference current (IL .5.5 GTO Ratings 5. as the GTO G1 is turned off the current through it (IG1) starts reducing. This condition is not dangerous for G2 provided the avalanche time and current are small (typically within 10 μs and 1000 A respectively). (b) Voltage. It is important to note that GTO can block rated voltage only if the gate is reverse biased or at least connected to the cathode through a low value resistance.com .

IH: This is the holding current of the GTO. in case of a GTO1 .com VDC: This is the maximum continuous DC voltage the device can withstand. The i2t rating of a semiconductor fuse must be less than this value in order to protect the GTO. This problem can be avoided by feeding a continuous current into the gate (called the “back porch” current) during ON period of the device.com . VF : This is the plot of the instantaneous forward voltage drop vs instantaneous forward current at different junction temperatures. A substantial gate current ensures that all GTO cathode segments are turned ON simultaneously and within a short time so that no local hot spot is created. square wave) the plot of the average on state power dissipation as a function of the average on state current is provided by the manufacturers at a given junction temperature. di The g and IgM values specified in the operating conditions should.2 Gate specification Ig vs Vg: It is a plot of instantaneous gate current as a function of the gate voltage. The pulse is assumed to be applied at an instant when the GTO is operating at its maximum junction temperature. sine wave. be considered as dt minimum values. The voltage across the device just after the surge should be zero. Plots of both IFSM and ∫ i 2 dt as functions of surge pulse width are usually provided by the manufacturer. ∫ i dt : 2 This is the limiting value of the surge current integral assuming half cycle sine wave surge current. This current. The junction temperature is assumed to be at the maximum value before the surge and the voltage across the device following the surge is assumed to be zero.www.jntuworld. is considerably higher compared to a similarly rated thyristor. Serious problem may arise due to anode current variation because the GTO may “un-latch” at an in appropriate moment.g. but the probability of a cosmic radiation failure increases progressively with the applied dc voltage. therefore. Kharagpur 15 www. This value is very much dependent on the peak gate current magnitude and the rate of increase of the gate current. They do not define the gate Version 2 EE IIT. di crit : This is the maximum permissible value of the rate of change of forward current during dt turn on.jntuworld. This characteristic is valid for DC and low frequency AC gate currents. 5. IFSM: This is the maximum allowed peak value of a power frequency half sinusoidal nonrepetitive surge current. This DC gate current should be about 20% higher than the gate trigger current (IGT) at the lowest expected junction temperature. Exceeding this voltage does not immediately lead to device failure. IFAVM and IFRMS: These are maximum average and RMS on state current respectively.5. They are specified at a given case temperature assuming half wave sinusoidal on state current at power frequency. Pav : For some frequently encountered current waveforms (e.

5. localized turn on may destroy it. A large negative dig/dt during turn off also helps to increase IFgqm. It is a function of turn off anode current. It is the maximum negative turn off gate current. ts : The storage time ts is defined as the time between the start of negative gate current and the decrease in anode current. the instantaneous gate cathode voltage when Igt is flowing into the gate. Generally the gate cathode impedance of a GTO is much lower than that of a conventional thyristor. tf : This is the anode current fall time. Igt has a strong junction temperature dependence and increases very rapidly with reduced junction temperature. Igt: Igt is the gate trigger current and Vgt . The gate unit should be designed to di deliver this current under any condition. It can not be influenced much by gate control. Version 2 EE IIT. Vg in this dt case is much higher. Manufacturers specify them as functions of turn on anode current for different turn on di/dt and anode voltage EON reduces with increased IgM .www. td. It can be increased by increasing the value of the turn off snubber capacitance which limits the dv/dt at turn off. current and di . IFgqm : It is the maximum anode current that can be repetitively turned off by a negative gate current. toff(min) : This is the minimum off time before the GTO may be triggered again by a positive gate current.com .3 Specifications related to the switching performance These are turn on delay time and anode voltage fall time respectively. If the device is re-triggered during this time.jntuworld. be reduced with higher g dt dt ton (min) : This is the minimum time the GTO requires to establish homogeneous anode current. Igt merely specifies the minimum back porch current necessary to turn on the GTO at a low di and maintain it in conduction. tr. g during dt turn off and the junction temperature.5. Both of them can di and IgM for a given turn on anode voltage. Igrm: Igqm: It is the peak repetitive reverse gate current at Vgrm and Tj (max). dt Vgrm: It is the maximum repetitive reverse gate voltage. : EON : It is the energy dissipated during each turn on operation. High value of the turn off anode current and junction temperature increases it while a large negative dig/dt during turn off decreases it. This time is also necessary for the GTO to be able to turn off its rated anode current. Kharagpur 16 www. di g Vgt. exceeding which drives the gate cathode junction into avalanche breakdown.com voltage when the GTO is turned on from high anode voltage with high di/dt and .jntuworld.

Answer: (i) negatively. (vii) magnitude. iii. S. viii.www. (iii) larger. The turn on delay time and current rise time of a GTO can be reduced by increasing the gate current _______________ and _______________ during turn ON. Khanna Publlishers. A GTO can operate in the reverse _______________ region for a short time. (vi) peak. The maximum anode current that can be turned off repetitively can be increased by increasing the turn off snubber _______________ and negative _______________. Vol. Bimbhra. Proceedings of the IEEE. dig/dt. 2) “GTO Thyristors” . Kharagpur 17 www. dig/dt. cathode. April 1988. After a current surge the voltage across a GTO should be reduced to _______________.com . 4. Reference 1) “GTO and GCT product guide”. Exercise 5. vii. P. Version 2 EE IIT.76. pp 419-427. iv. ii. vi.4 Fill in the blank(s) with the appropriate word(s) i. The holding current of a GTO is much _______________ compared to a thyristor. (viii) capacitance. No. 1993. (ii) avalanche. A GTO can block rated forward voltage only when the gate is _______________ biased with respect to the _______________. 1997. ABB semiconductors AG. dig/dt.jntuworld. The gate cathode impedance of a GTO is much _______________ compared to a thyristor. (v) smaller. Eoff increases with increase in the turn off anode current and junction temperature while it reduces with turn off snubber capacitance. (iv) zero.jntuworld. 3) “Power Electronics”. The turn on di/dt capability of a GTO can be increased by in creasing the _______________ magnitude of the gate current and _______________ during turn on. Makoto Azuma and Mamora Kurata.com Eoff : This is the energy dissipated during each turn off operation of the GTO. v.

The GTO gate drive unit should be capable of injecting large positive and negative gate currents with large rate of rise for satisfactory switching of the device. The forward i-v characteristics of a GTO is similar to that of a thyristor. A GTO can block rated forward voltage only when the gate cathode junction is reverse biased. However.www. The switching delay times and energy loss of a GTO can be reduced by increasing the gate current magnitude and its rate of rise. These are called “asymmetric GTOs”. Kharagpur 18 www. The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate current and large rate of rise of the gate current. they have relatively larger holding current and gate trigger current. three terminal current controlled minority carrier device. A GTO can be turned on by applying a positive gate current pulse when it is forward biased and turned off by applying a negative gate current.com Lesson Summary • • • • • • • • • • • • • GTO is a four layer. The maximum turn off anode current of a GTO can be increased by increasing the turn off snubber capacitance. A GTO can operate safely in the “reverse avalanche” region for a short time provided the gate cathode junction is reverse biased. Due to relatively larger holding current of a GTO a continuous low value gate current (called the back porch current) should be injected through out the on period of the GTO. Version 2 EE IIT.com . A GTO has a “shorted anode” and highly inter-digitized gate cathode structure to improve the gate turn off performance.jntuworld.jntuworld. Due to the presence of “anode shorts” a GTO can block only a small reverse voltage. GTOs have relatively low turn off current gain.

com .jntuworld.www.com Practice Problems and Answers Version 2 EE IIT. Kharagpur 19 www.jntuworld.

jntuworld. What are the desirable characteristics of the gate drive circuit of a GTO? How do they influence the switching performance of a GTO? 4. Which paramers of the gate current waveform reduces the turn on energy loss (EON) of a GTO? How does one reduce the turn off energy lass of a GTO? Version 2 EE IIT. then which current should one use in a particular application? 5. What are the constructional features of a GTO that bestows it with a gate turn off capability? How do they affect the turn on performance of the GTO? 2. What are the main differences in the steady state output characteristics of a GTO and a thyristor? What effect do they have on the gate drive requirement of a GTO? 3. What is the significance of the specifications IFAVM and IFRMS in relation to a GTO? Is the specification IFgqm.www.com . Same as IFAVM / IFRMS? If not.com 1.jntuworld. Kharagpur 20 www.

if the gate current is not sufficient to turn on a GTO it may operate as a high voltage low gain transistor with considerable anode current. introduction of anode shorts effectively reduces the current gain ∝p of the top p-n-p transistor. A GTO can block rated forward voltage only when the gate voltage is negative with respect to the cathode or at least the gate is connected to the cathode through a low value resistance. from the cathode structure of a GTO. The forward leakage current of a GTO is considerably higher compared to a thyristor of equal rating. This has the effect of increasing the latching and holding current of a GTO compared to a thyristor.com • • • 2. “Anode shorts” consists of heavily doped n+ type region introduced inside the p+ type anodes. The minimum gate current require to trigger a GTO at a given forward blocking voltage is higher compared to a thyristor. Highly inter digitized gate-cathode structure of a GTO helps to enhance the turn on di/dt capability of the device due to faster and more even spreading of the injected gate current to adjacent cathodes. This highly inter digitized structure of the GTO cathode ensures that any “current filament” formed during the turn off process of a GTO is quickly extinguished. There are some important differences however. Thousands of cathode segments.com Answers to practice problems 1. Exceeding this reverse voltage forces the GTO to operate in the “reverse avalanche” mode. On the other hand. In the reverse blocking region (i.2 (a).jntuworld.e third quadrant of the output i-v plane) an asymmetric GTO has much lower reverse break down voltage (20-30V) compared to a thyristors. Version 2 EE IIT. Both holding and latching current of a GTO are considerably higher compared to a similarly rated thyrisstor.jntuworld. This helps to reduce the “tail current” during turn off of a GTO. presence of anode shorts has adverse effect on the turn on performance of a GTO. Referring to Fig 5. In fact. • The Gate-cathode junction of a GTO is far more inter digitized compared to a thyristor. Although a GTO is a four layer (p-n-p-n) three junction devices like a thyristor it has two important constructional differences with a thyristor which bestows it with the gate turn off capability. Kharagpur 21 www.www. The minimum gate current required to trigger a GTO also increases. “Anode shorts” are introduced at the p+ type anode and n type base junction of a GTO. • • • • • . They make direct contact with the anode metal plate and provide an alternate path for the electrons traveling through the n base to reach the anode metal contact without causing bole injection from the p+ anode. normally arranged in concentric rings around the device center. In the first quadrant of the output i-v plane the steady state output characteristics of a GTO appears to be similar to that of a thyristor.

The gate drive unit of a GTO should. To ensure that the GTO blocks rated forward voltage and operates safely in the “reverse avalanche” mode the gate voltage must be maintained negative with respect to the cathode for the entire off duration of the GTO. Both the turn on delay time (td) and the voltage fall time (tr) of a GTO can be reduced by increasing the peak positive gate current and its rate of rise during turn on. • • • • .com • • 3. IFAVM / IFRMS ratings. If the GTO is employed in a line commutated phase controlled converter application then these specifications give the maximum allowable average and RMS current through the device respectively. Energy loss per turn on (EON) also reduces. the gate drive unit must inject a peak gate current considerably larger (3-10 times) than the gate trigger current with fast rate of rise. To avoid localized transistor operation during turn on from a high anode voltage with large di/dt. However. IFgqm rating of a GTO gives the maximum anode current that can be repetitively turned off by gate control. On the other hand. In Version 2 EE IIT. A large negative gate current during turn off with a stiff slope considerably reduces the storage time (ts) and enhances maximum anode current turn off (IFgqm) capability. does not have any practical significance except for comparison of current carrying capacity of different devices. in most GTO applications the current waveform is for removed from a sinusoidal shape and the switching losses are a considerable part of the total power losses. The specifications of IFAVM and IFRMS are given with reference to power frequency half cycle sine wave anode current. The peak magnitude of the negative gate current should be at least 20-25% of the maximum anode current during turn off. Maintain conduction of the GTO through out the ON period by injecting a positive “back porch” gate current which is larger than the minimum gate trigger current.jntuworld. • Since the holding current of a GTO is considerably higher than that of a thyristor anode current variations can generate serious problem because the GTO might “unlatch” at an inappropriate moment. This rating is usually lower than IFAVM / IFRMS.jntuworld. To avoid this problem the gate drive unit of a GTO must feed the gate terminal with a continuous “back porch” current during the entire on period of the GTO. Kharagpur 22 www.com This mode of operation does not destroy the device provided the gate is negatively biased and the time of such operation is small. 4.www. This back porch current must be larger than the gate trigger current. in such cases. Reinforce the blocking state of the device by applying a negative voltage to the gate with respect to cathode for the entire off duration of the GTO. Turn the GTO on with a large (3-10 times the minimum gate trigger current) positive gate current pulse with high rate of rise. Turn the GTO off with a large negative gate current with high rate of fall.

com .jntuworld. Version 2 EE IIT. Kharagpur 23 www.www.jntuworld. Eon is reduced by increasing the peak magnitude of the positive gate current during turn on. Eoff is reduced by increasing the turn off snubber capacitance across the GTO.com high frequency switching application this specification gives the absolute peak value of any desired current waveform the GTO can conduct. 5.

com .www.jntuworld. Kharagpur 1 www.com Module 1 Power Semiconductor Devices Version 2 EE IIT.jntuworld.

www.com Lesson 6 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Version 2 EE IIT.com .jntuworld.jntuworld. Kharagpur 2 www.

Explain the salient constructional features of a MOSFET. Version 2 EE IIT. Design the gate drive circuit of a MOSFET. Draw the switching characteristics of a MOSFET and explain it. Interpret the manufacturer’s data sheet rating of a MOSFET. Kharagpur 3 www. operating principle and characteristics of Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Explain the difference between the safe operating area of a MOSFET and a BJT.jntuworld. Instructional Objectives On completion the student will be able to • • • • • • • Differentiate between the conduction mechanism of a MOSFET and a BJT.www.com Constructional Features.jntuworld.com . Draw the output i-v characteristics of a MOSFET and explain it in terms of the operating principle of the device.

the development of solid-state switches with increased power handling capability has been of interest for expending the application of these devices. can be of two types (i) depletion type and (ii) enhancement type. Kharagpur 4 www. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). namely. Ever since the invention of the transistor. All bipolar devices. Both of these can be either n. movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-source voltage characteristics (transfer characteristics). diode. however. The reliance of the power electronics industry upon bipolar devices was challenged by the introduction of a new MOS gate controlled power device technology in the 1980s.channel type or p-channel type depending on the nature of the bulk semiconductor.com 6.www. The initial claims of infinite current gain for the power MOSFET were. suffer from a common set of disadvantages. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred kHz. thyristor. it opened up the possibility of increasing the operating frequency in power electronic systems resulting in reduction in size and weight. The BJT and the GTO thyristor have been developed over the past 30 years to serve the need of the power electronic industry. Version 2 EE IIT.1 Introduction Historically.e. the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. bipolar semiconductor devices (i. Power MOSFETs. Thus. At high frequency of operation the required gate drive power becomes substantial.jntuworld. just like their integrated circuit counterpart. MOSFETs also have comparatively higher on state resistance per unit area of the device cross section which increases with the blocking voltage rating of the device. From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier device.com . Besides. (i) limited switching speed due to considerable redistribution of minority charge carriers associated with every switching operation. The power MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. Their primary advantage over the thyristors have been the superior switching speed and the ability to interrupt the current without reversal of the device voltage. bipolar devices can not be paralleled easily. Fig 6. thyristor. The new device promised extremely low input power levels and no inherent limitation to the switching speed. GTO etc) have been the front runners in the quest for an ideal power electronic switch. (ii) relatively large control power requirement which complicates the control circuit design.jntuworld. As the name suggests. Consequently. diluted by the need to design the gate drive circuit to account for the pulse currents required to charge and discharge the high input capacitance of these devices. however. transistor.

jntuworld.1: Different types of power MOSFET. 6.2 Constructional Features of a Power MOSFET As mentioned in the introduction section. The resulting technology was called lateral double deffused MOS (DMOS). This is the type of MOSFET which will be discussed in this lesson.jntuworld.e. Kharagpur 5 www. Power MOSFET is a device that evolved from MOS integrated circuit technology.com . Fig 6. with the gate terminal open a nonzero drain current can flow in these devices. the enhancement type MOSFETs (particularly of the n-channel variety) is more popular for power electronics applications.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i. (a) Circuit symbols and transfer characteristics (b) Photograph of n-channel enhancement type MOSFET.1 (b) shows the photograph of some commercially available n-channel enhancement type Power MOSFETs. Therefore.www. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. This is not convenient in many power electronic applications.com D ID G G D ID G D ID G D ID S ID S ID S ID S ID VGS n-channel depletion type MOSFET VGS p-channel depletion type MOSFET (a) VGS n-channel enhancement type MOSFET VGS p-channel enhancement type MOSFET (b) Fig 6. However it was soon realized that Version 2 EE IIT. From Fig 6.

Source Gate conductor FIELD OXIDE n+ p(body) n.2: Schematic construction of a power MOSFET (a) Construction of a single cell.jntuworld.www.2 (b)) to form a complete device.com much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure.com . Since then. 6. (b) Arrangement of cells in a device. Kharagpur 6 www. n+ p n+ n+ Single MOSFET Cell Version 2 EE IIT. vertical DMOS (VDMOS) structure has been adapted by virtually all manufacturers of Power MOSFET. A large number of such cells are connected in parallel (as shown in Fig 6. A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure.(drain drift) n+ Drain n+ n+ p(body) Gate oxide n+ (a) Contact to source Source Conductor Gate Oxide Field oxide Gate Conductor nn+ p n+ nn+ (b) Fig.jntuworld.

3: Parasitic BJT in a MOSFET cell. Kharagpur 7 www. Version 2 EE IIT. The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device.and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The gate terminal is placed over the n. D S n p Body spreading resistance + D Parasitic BJT G n Parasitic BJT nn+ D + MOSFET G G Body diode S S Fig. application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or “channel”. influences the ON state resistance of the MOSFET.jntuworld. The nonzero resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type substrate. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector-base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET.com The two n+ end layers labeled “Source” and “Drain” are heavily doped to approximately the same level.drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions. The n.jntuworld. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. However. There is no possibility of current injection from the gate terminal either since the gate oxide is a very good insulator. One interesting feature of the MOSFET cell is that the alternating n+ n.3 Operating principle of a MOSFET At first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the p n junctions (source – body and body-Drain) will be reverse biased for either polarity of the applied voltage between the source and the drain.com . The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n+ regions on both sides). 6.p n+ structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig 6. to same extent.3. Similarly all gate terminals are also connected together. 6.www. thus connecting the Source to the Drain as explained next.

When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO2 and the silicon as shown in Fig 6. +++ ++++++++ Gate Electrode Si02 p n- (a) VGS2 Source Electrode n+ Depletion layer boundary.jntuworld. Kharagpur 8 www.jntuworld.com The gate region of a MOSFET which is composed of the gate metallization.com .www. the gate (silicon) oxide layer and the p-body silicon forms a high quality capacitor. VGS2 > VGS1 +++ ++++++++ Gate Electrode Si02 p n- Ionized acceptor Free electron (b) Version 2 EE IIT.4 (a). VGS1 Source Electrode n+ Ionized acceptor Depletion layer boundary.

The inversion layer screens the depletion layer adjacent to it from increasing VGS.www. The immediate source of electron is electron-hole generation by thermal ionization.4 (b). (a) Depletion layer formation. (b) Free electron accumulation. The inversion layer has all the properties of an n type semiconductor and is a conductive path or “channel” between the drain and the source which permits flow of current between the drain and the source. since the density of free electrons increases further with increase in VGS. At the same time the electric field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in Fig 6. The value of VGS at which the inversion layer is considered to have formed is called the “Gate – Source threshold voltage VGS (th)”.com VGS3 Source Electrode n+ VGS3 > VGS2 > VGS1 +++ ++++++++ Gate Electrode Si02 Inversion layer with free electrons Depletion layer boundary.4: Gate control of MOSFET conduction.4 (c). (c) Formation of inversion layer. Version 2 EE IIT. The extra holes are neutralized by electrons from the source. As VGS is increased beyond VGS(th) the inversion layer gets some what thicker and more conductive. The depletion layer thickness now remains constant.type “channel” created by the electric field due to gate source voltage it is called “Enhancement type n-channel MOSFET”. As VGS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. Since current conduction in this device takes place through an n. This exposes the negatively charged acceptors and a depletion region is created. The holes are repelled into the semiconductor bulk ahead of the depletion region.jntuworld. Further increase in VGS causes the depletion layer to grow in thickness. p nIonized acceptor (c) Fig. Kharagpur 9 www. The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. 6. The layer of free electrons at the interface is called the inversion layer and is shown in Fig 6.jntuworld.com .

Kharagpur 10 www. i. Current conduction takes place between the drain and the source through this channel due to flow of electrons only (majority carriers). Enhancement type MOSFETs are normally ________________devices while depletion type MOSFETs are normally ________________ devices.5 (a) shows such a characteristics. Version 2 EE IIT. What are the main constructional differences between a MOSFET and a BJT? What effect do they have on the current conduction mechanism of a MOSFET? Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors.jntuworld. Thus a MOSFET is a voltage controlled majority carrier device while a BJT is a minority carrier bipolar device. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of ________________. 2. on.com Exercise 6. Conduction in a MOSFET occurs due to formation of a high density n type channel in the p type body region due to the electric field produced by the gate-source voltage. 6. (iii) SiO2. threshold. majority. current conduction occurs due to minority carrier injection across the Base-Emitter junction. The gate terminal is insulated for the semiconductor by a thin layer of SiO2.1 (after section 6. Fig 6. However. Fill in the blank(s) with the appropriate word(s) A MOSFET is a ________________ controlled ________________ carrier device. Source and Drain. (ii) off. (iv) BJT. The gate-source voltage at which the ________________ layer in a MOSFET is formed is called the ________________ voltage. The source terminal is common between the input and the output of a MOSFET. threshold. like the BJT is a three terminal device where the voltage on the gate terminal controls the flow of current between the output terminals.www.jntuworld. iii. unlike BJT the p type body region of a MOSFET does not have an external electrical connection.3) 1. vi. Where as in a BJT. The thickness of the ________________ layer remains constant as gate source voltage is increased byond the ________________ voltage. Thus minority carrier injection across the source-body interface is prevented. The output characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain – Source voltage (vDS) with gate source voltage (vGS) as a parameter.4 Steady state output i-v characteristics of a MOSFET The MOSFET. (vi) depletion. v.com . The MOSFET cell embeds a parasitic ________________ in its structure. iv. This n type channel connects n+ type source and drain regions. (v) inversion. Answer: (i) voltage. ii. The body itself is shorted with n+ type source by the source metallization.

The slope of the vDS – iD characteristics in this mode is called the ON state resistance of the MOSFET (rDS (ON)).com VGS – VGS (th) = VDS iD ohmic rDS(ON) Increasing VGS VGS6 Active VGS5 [VGS–VGS(th)]<VDS VGS4 VGS3 VGS2 vgs1 Cut off (VGS < VGS (th)) VDSS vDS (a) S n+ Source region resistance Channel p resistance nn+ (b) Drift region resistance Drain resistance G iD Electron Drift Velocity (c) Electric Field iD VGS(th) D (d) VGS Fig. (b) Components of ON-state resistance. Kharagpur 11 www. Note that rDS (ON) reduces with increase in vGS. This is mainly due to reduction of the channel resistance at higher value of Version 2 EE IIT. When VGS is increased beyond vGS(th) drain current starts flowing. 6.jntuworld. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. Therefore.www. (c) Electron drift velocity vs Electric field. the maximum applied voltage should be below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device. No drain current flows in this mode and the applied drain– source voltage (vDS) is supported by the body-collector p-n junction. Several physical resistances as shown in Fig 6. For small values of vDS (vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation is called “ohmic mode” of operation.jntuworld.5: Output i-v characteristics of a Power MOSFET (a) i-v characteristics. (d) Transfer With gate-source voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in the cut-off mode.5 (b) contribute to rDS (ON).com .

Both of them have three distinct modes of operation. the drift velocity of free electrons in the channel tends to saturate as shown in Fig 6. • The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. it is desirable in power electronic applications.3) is shown by a dotted line in Fig 6. This should be contrasted with three different break down voltages (VSUS.vGS (th))2 (6.vGS (th) (6. for power MOSFETs the transfer characteristics (iD vs vGS) is more linear as shown in Fig 6. to use as large a gate-source voltage as possible subject to the dielectric break down limit of the gate-oxide layer.com vGS. In addition.1) applies reasonably well to logic level MOSFETs.5 (c).com . first order theory predicts that in the active region the drain current is given approximately by i D = K(vGS . At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates from the linear relationship of the ohmic region and for a given vGS. As in the case of a BJT the operating limits of a MOSFET are compactly represented in a Safe Operating Area (SOA) diagram as shown in Fig 6. at large value of the electric field. The exact mechanism behind this is rather complex. vCE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated. As a result the drain current becomes independent of VDS and determined solely by the gate – source voltage vGS. At this point the similarity of the output characteristics of a MOSFET with that of a BJT should be apparent. produced by the large Drain – Source voltage. at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. At the boundary between the ohmic and the active region vDS = vGS .jntuworld.5 (a).5 (d). there are some important differences as well. The relationship of Equation (6.2) Therefore. i D = KvDS2 (6. On the other hand.3) Equation (6.jntuworld.www. namely. The primary break down voltage of a MOSFET remains same in the cut off and in the active modes. • • Unlike BJT a power MOSFET does not undergo second break down. iD tends to saturate with increase in vDS.6. This is the active mode of operation of a MOSFET. It will suffice to state that. VCEO & VCBO) of a BJT. However. Kharagpur 12 www. Hence. (ii) active and (iii) ohmic (saturation for BJT) modes. (i)cut off. Simple.1) Where K is a constant determined by the device geometry. However. As in the case of the FBSOA of a Version 2 EE IIT.

To the right. 6. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. operating restriction arise due to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). a MOSFET can not block any reverse voltage. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. A MOSFET operates in the ________________ mode when vGS < vGS(th) Version 2 EE IIT.www. This limit is different for DC (continuous) and pulsed operation of different pulse widths. The body diode.com .jntuworld. To the left. can carry an RMS current equal to IDM. They are identical.2 Fill in the blank(s) with the appropriate word(s) i. the SOA is restricted by the absolute maximum permissible value of the drain current (IDM) which should not be exceeded even under pulsed operating condition.6: Safe operating area of a MOSFET. A MOSFET does not undergo “second break down” and no corresponding operating limit appears on the SOA. When reverse biased it can block a voltage equal to VDSS. the maximum limit on the gate source voltage (VGS (Max)) must be observed. For safe operation of a MOSFET. On the top. the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. The device user should ground himself before handling any MOSFET to avoid any static charge related problem. This is an instantaneous limit. It also has a substantial surge current carrying capacity. Exercise 6. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET.jntuworld.com BJT the SOA of a MOSFET is plotted on a log-log graph. 10-3sec Power Dissipation DC Limit (Timax) Primary voltage breakdown limit VDSS Log (vDS) Fig. Kharagpur 13 www. however. Due to the presence of the anti parallel “body diode”. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which is decided by the avalanche break down voltage of the drain -body p-n junction. Log (iD) IDM 10-5sec rDS(ON) limit 10-4sec (VGS = VGS(max)) Max.

Unlike BJT a MOSFET does not undergo ________________.1 Circuit models of a MOSFET cell Like any other power semiconductor device a MOSFET is used as a switch in all power electronic converters. vDS. In the active region of operation the drain current iD is a function of ________________ alone and is independent of ________________. Unlike bipolar devices. There are several other capacitors in a MOSFET structure which are also involved in the switching process. The safe operating area of a MOSFET is restricted on the left hand side by the ________________ limit. Being a majority carrier device the switching process in a MOSFET does not involve any inherent delay due to redistribution of minority charge carriers. However. Version 2 EE IIT.jntuworld.5 Switching characteristics of a MOSFET 6. vi. iii.jntuworld. While making transition between these two states it traverses through the active region.5. In a Power MOSFET the relation ship between iD and vGS – vGS(th) is almost ________________ in the active mode of operation. iv. Answer: (i) Cut off. (iii) decreases. viii. ________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy ________________ of the devices. As a switch a MOSFET operates either in the cut off mode (switch off) or in the ohmic mode (switch on). (vii) Positive. v. formation of the conducting channel in a MOSFET and its disappearance require charging and discharging of the gate-source capacitance which contributes to the switching times.com ii. (viii) linear. vii.com . however. ix. The primary break down voltage of MOSFET is ________________ of the drain current. second 6. (vi) break down. Kharagpur 14 www. (ii) vDS. In the ohmic region of operation of a MOSFET vGS – vGS (th) is greater than ________________. rDS (ON) of a MOSFET ________________ with increasing vGS. these switching times can be controlled completely by the gate drive circuit design. (ix) rDS (ON). (v) independent. (iv) vGS.www. paralleling.

For low values of vDS (vDS < (vGS – vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS as shown in Fig 6. Although this capacitance is important for some design considerations (such as snubber design.com S n + G Gate oxide p CDS nn+ CGS CGD CGD Drain body depletion layer CGD1 idealized Actual CGD2 (a) D CGD G CGS S (cut off) G D VGS – VGS (th) = VDS VDS (b) D CGD iD = f(vGS) CGS S (Active) G CGS S CGD rDS(ON) (Ohmic) D (c) Fig. Kharagpur 15 www. It has the largest value (a few nano farads) and remains more or less constant for all values of vGS and vDS.jntuworld. Being a depletion layer capacitance its value is a strong function of the drain source voltage vDS. Although variation of CGD between CGD1 and CGD2 is continuous a step change in the value of CGD at vDS = vGS – vGS(th) is assumed for simplicity.7: Circuit model of a MOSFET (a) MOSFET capacitances (b) Variation of CGD with VDS (c) Circuit models. The lowest value capacitance is formed between the drain and the source terminals due to the drain – body depletion layer away form the gate metallization and below the source metallization. 6. Fig 6.com .jntuworld.7 (b). The next largest capacitor (a few hundred pico forwards) is formed by the drain – body depletion region directly below the gate metallization in the n.7 (a) shows three important capacitances inherent in a MOSFET structure. it will be neglected in our discussion.drain drift region. From the Version 2 EE IIT. The most prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the gate metallization and the n+ type source region. zero voltage switching etc) it does not appreciably affect the “hard switching” performance of a MOSFET. Consequently.www.

the gate drive voltage changes from zero to Vgg.7 (c).com . VD DF if iD CGD Rg Vgg + ig CGS VDS IO + Fig.com above discussion and the steady state characteristics of a MOSFET the circuit models of a MOSFET in three modes of operation can be drawn as shown in Fig 6.8: Clamped inductive switching circuit using a MOSFET. The gate source voltage which was initially zero starts rising towards Vgg with a time constant τ1 = Rg (CGS + CGD1) as shown in Fig 6. To turn the MOSFET on.www.9. 6.jntuworld.8. For simplicity the load current is assumed to remain constant over the small switching interval. Also the diode DF is assumed to be ideal with no reverse recovery current. 6. Kharagpur 16 www. Version 2 EE IIT. The gate is assumed to be driven by an ideal voltage source giving a step voltage between zero and Vgg in series with an external gate resistance Rg.2 Switching waveforms The switching behavior of a MOSFET will be described in relation to the clamped inductive circuit shown in Fig 6.5.jntuworld.

6. Till vGS reaches vGS (th) no drain current flows. At this point the complete load current has been transferred to the MOSFET from the free wheeling diode DF. iD does not increase byond this point. This time period is called turn on delay time (td(ON)).www. Byond td(ON) iD increases linearly with vGS and in a further time tri (current rise time) reaches Io. The corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.jntuworld. Therefore.9: Switching waveforms of a clamped inductive switching circuit using MOSFET Note that during this period the drain voltage vDS is clamped to the supply voltage VD through the free wheeling diode DF. A part of the total gate current ig charges CGS while the other part discharges CGD. The gate current ig now discharges CGD and the drain voltage starts falling.com . ig V -V I d d d v DS = ( vGS + vGD ) = v GD = = GG GS o dt dt dt CGD CGD R g ( 6.jntuworld. CGS and CGD can be assumed to be connected in parallel effectively.4 ) Version 2 EE IIT. Since in the active region iD and vGS are linearly related. Note that td(ON) can be controlled by controlling Rg.9. if I0 if VDS iD I0 if ∫∫ iD t I0ros (ON) ∫∫ tdON tri tfv1 tfv2 tON td(off) trv2 trvi tfi toff t Fig.com Vgg VGS VGSI0 VGS(th) ig ∫∫ τ2 τ1 τ2 = Rg(CGS+CGD2) ∫∫ t Vgg τ1 = Rg(CGS+CGD1) R g igI0 − ∫∫ Vgg igI0 t Rg ∫∫ iD. Kharagpur 17 www. vGS also becomes clamped at the value vGSIo.

Therefore. if fast charging and discharging of a MOSFET is desired at fast switching frequency the gate drive power requirement may become significant. rate of fall of vDS slows down considerably (tfv2). being a voltage controlled device.jntuworld.9. This fast fall time of vDS is marked tfv1 in Fig 6. To turn the MOSFET OFF.9. However. Version 2 EE IIT. The total turn off time toff = td(off) + trv1 + trv2 + tfi. Vgg is reduced to zero triggering the exact reverse process of turn on to take place. Therefore. 6. does not require a continuous gate current to keep it in the ON state. The switching times of a MOSFET essentially depends on the charging and discharging rate of these capacitors. Kharagpur 18 www. Note that all switching periods can be reduced by increasing Vgg or / and decreasing Rg. Once vDS reaches its on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a time constant τ2 = Rg (CGS + CGD2). once in the ohmic region. vDS falls rapidly. The total turn on time is tON = td(ON) + tri + tfv1 + tfv2.www.10 (a) shows a typical gate drive circuit of a MOSFET.3 MOSFET Gate Drive MOSFET. CGD = CGD2 >> CGD1. it is required to charge and discharge the gate-source and the gate-drain capacitors in each switching operation.com The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region (vDS > (vGS – vGS (th)) CGD = CGD1.5. However. Fig 6.jntuworld.com .Since CGD1 << CGD2. The corresponding waveforms and switching intervals are show in Fig 6.

(b) Effect of parasitic BJT. Where.10 (b) shows the equivalent circuit during turn on. 6. during turn on Q1 remains in the active region. Version 2 EE IIT. Kharagpur 19 www. (d) Parallel connection of MOSFET’s. The top circuit of Fig 6.www.jntuworld. β1 is the dc current gain of Q1. Note that. (b) Equivalent circuit during turn on and off.jntuworld. The effective gate resistance is RG + R1 / (β1 + 1). (a) Gate drive circuit.10: MOSFET gate drive circuit.com VGG R1 Logic level gate pulse Q3 Q1 Q2 RG VD VGG RG + R1 (β1 +1) RG VGG (a) VD (b) D DF IL RG D G R R B G S (c) S RB (d) Fig. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q3 turns off and Q1 turns on.com .

(iv) inversely. Some stray inductance of wiring may however be present. A very fast rising drain-source voltage will send sufficient displacement current through CDS and RB as shown in Fig 6. However.jntuworld.com . To parallel two MOSFETs the drain and source terminals are connected together as shown in Fig 6.10 (c). Exercise 6. iv. i. Kharagpur 20 www.jntuworld. iii. this problem can also be avoided by slowing down the MOSFET switching speed. v. This is avoided by the damping resistance R. Reducing RG will incase the switching speed of the MOSFET. Answer: (i) largest.www. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate qxide layer due to voltage increase during oscillations. The voltage fall time of a MOSFET is ________________ proportional to the gate charging resistance. (v) gate drive. During the turn on delay time the MOSFET gate source voltage rises from zero to the ________________ voltage. active. (iii) threshold. small resistances (R) are connected to individual gates before joining them together.com To turn off the MOSFET the logic level input is set to low state. Fill in the blank(s) with the appropriate word(s) The Gate-Source capacitance of a MOSFET is the ________________ among all three capacitances.10 (d). ii. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. The devices are now capable of dvDS/dt in excess to 10. Version 2 EE IIT.3 1. The body source short has some nonzero resistance. caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance (CDS) is actually connected to the base of the parasitic BJT at the p type body region. The corresponding equivalent circuit is given by the bottom circuit of Fig 6. However. Of course.10 (b) The switching time of the MOSFET can be adjusted by choosing a proper value of RG. (ii) ohmic. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the body-source short. This is because the gate inputs are highly capacitive with almost no losses.000 V/μs. Q3 and Q2 turns on whole Q1 turns off. The Gate-Drain transfer capacitance of a MOSFET has large value in the ________________ region and small value in the ________________ region. The voltage drop across RB may become sufficient to turn on the parasitic BJT. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design of the ________________ circuit.

vgs Min )= g f ( Vgg . vgs(th) = 3V. and gf = 4 I 20 VGS . gf = 4.com 2. The gate drive voltage is vgg = 15V. vGS(th) = 3V.v gs (th) ) dv gs di D = gf dt dt dv V -v But ( CGS + CGD ) gs = gg gs dt Rg ∴ ∴ dv di D gf = g f gs = ( Vgg .01×109 A sec -12 ( 50×950×10 From equation (6.8) of 20 Amps with a supply voltage VD= 200V.vgs ) dt dt R g ( CGS + CGD ) ∴ di D dt = Max R g ( CGS + CGD gf (V ) gg . dt 150×10-12 ×50 6.4) dv DS Vgg . Find out maximum dv DS did and during turn ON. CGD = 150 pF.com . Io = o + vgs (th) = + 3 = 8 volts gf 4 ∴ dv DS 15 -8 = = 933×106 V sec. Exceeding this limit will destroy the device due to avalanche break down of the body-drain p-n junction.www. and gate resistance Rg = 50Ω. VDSS: This is the drain-source break down voltage. value of dt dt Answer: During turn on i D ≈ g f ( v gs .jntuworld. Kharagpur 21 www. The following limits are specified. A Power MOSFET has the following data CGS = 800 pF . Io = dt CGD R g For Io = 20 A.6 MOSFET Ratings Steady state operating limits of a MOSFET are usually specified compactly as a safe operating area (SOA) diagram.VGS . Version 2 EE IIT.jntuworld.vgs (th) ) R g ( CGS + CGD ) since for vgs < vgs (th) iD = di D =0 dt ∴ di D dt = Max 4 15 .3) = 1. It is used to switch a clamped inductive load (Fig 6.

Input. specifications pertaining to the “body diode” are also provided. These are Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS in below this voltage. Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure of the MOSFET due to dielectric break down of the gate oxide layer.com IDM: This is the maximum current that should not be exceeded even under pulsed current operating condition in order to avoid permanent damage to the bonding wires.www. Kharagpur 22 www. VGS (th) decreases with junction temperature. output and reverse transfer capacitances (CGS. In a MOSFET switching circuit it determines the clamping voltage level of the gate – source voltage and thus influences dvDS/dt during turn on and turn off. Forward Transconductance (gfs): It is the ratio of iD and (vGS – vGS(th)). Continuous and Pulsed power dissipation limits: They indicate the maximum allowable value of the VDS.com . Its value decreases with increasing vGS and increases with junction temperature. Version 2 EE IIT. Exceeding these limits will cause the junction temperature to rise beyond the acceptable limit. iD product for the pulse durations shown against each limit.jntuworld. It should be noted that this limit may by exceeded even by static charge deposition. CDS & CGD): Value of these capacitances are specified at a given drain-source and gate-source voltage. They are useful for designing the gate drive circuit of a MOSFET. special precaution should be taken while handing MOSFETs. Specifications given are Reverse break down voltage: This is same as VDSS Continuous ON state current (IS): This is the RMS value of the continuous current that can flow through the diode. In addition to the main MOSFET. Forward voltage drop (vF): Given as an instantaneous function of the diode forward current. rDS (ON) determines the ON state power loss in the device. Drain Source on state resistance (rDS (ON)): This is the slope of the iD – vDS characteristics in the ohmic region.jntuworld. All safe operating area limits are specified at a given case temperature. In addition. several important parameters regarding the dynamic performance of the device are also specified. Therefore. Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ON state current through the diode given as a function of the pulse duration. Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified as functions of the diode forward current just before reverse recovery and its decreasing slope (diF/dt).

4 Fill in the blank(s) with the appropriate word(s) i. VOL. B. Undeland. Version 2 EE IIT. The gate oxide of a MOSFET can be damaged by ________________ electricity. The gate source threshold voltage of a MOSFET ________________ with junction temperature while the on state resistance ________________ with junction temperature. The reverse break down voltage of the body diode of a MOSFET is equal to ________________ while its RMS forward current rating is equal to ________________. [3] GE – Power MOSFET data sheet. No-4.www.com Exercise 6. increases. Answer: (i) independent. The maximum voltage a MOSFET can with stand is ________________ of drain current.com . John Wiley & Sons Publishers 2003. Kharagpur 23 www. IDM. April 1988.jntuworld. (ii) identical. (iv) static. Proceedings of the IEEE. Jayant Baliga.Converters Application and Design” Third Edition. iv.jntuworld. v. The FBSOA and RBSOA of a MOSFET are ________________. Reference [1] “Evolution of MOS-Bipolar power semiconductor Technology”.76. iii. Mohan. Robbins. (iii) decreases. (v) VDSS. ii. [2] “Power Electronics .

The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit. MOSFETs can be easily paralleled. Kharagpur 24 www. The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient.com . This is called the MOSFET “body – diode. For larger values of vDS the drain current is a function of vGS alone and does not depend on vDs. The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions. The drain – body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO2. With vGS > vGS (th) and vDS < (vGS – vGS (th)) the drain current in a MOSFET is proportional to vDS.” The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET. A MOSFET does not undergo second break down. Therefore. This is the “Ohmic region” of the MOSFET output characteristics.www. In power electronic applications a MOSFET is operated in the “Cut Off” and Ohmic regions only. p type semiconductor body separates n+ type source and drain regions.com Lesson Summary • • • • • • • • • • • • • • • • • • • • MOSFET is a voltage controlled majority carrier device. This is called the “active region” of the MOSFET. Version 2 EE IIT. Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current. When the gate source voltage is below threshold level a MOSFET remains in the “Cut Off” region and does not conduct any current. Switching times of a MOSFET can be controlled completely by external gate drive design. Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel.jntuworld.jntuworld. The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n+ type semiconductor. A Power MOSFET has a vertical structure of alternating p and n layers.

Therefore. The gate oxide layer can be damaged by static charge. a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. The transfer capacitor (Cgd) determines the drain voltage rise and fall times. rDS (ON) of a MOSFET determines the conduction loss during ON period. Therefore. to minimize conduction power loss maximum permissible vgs should be used subject to dielectric break down of the gate oxide layer.jntuworld. Therefore MOSFETs should be handled only after discharging one self through proper grounding.jntuworld.www. rDS (ON) reduces with higher vgs. Version 2 EE IIT. MOSFETs are more popular for high frequency (>50 kHz) low voltage (<100 V) circuits. For similar voltage rating. Kharagpur 25 www.com .com • • • • • • The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching.

www. Kharagpur 26 www.jntuworld.com Practice Problems and Answers Version 2 EE IIT.jntuworld.com .

A MOSFET has the following parameters VGS(th) = 3V. Find out the switching loss in the MOSFET.www. Version 2 EE IIT. find out the maximum allowable gate source voltage. 4. The gate drive circuit has a driving voltage of 15V and output resistance of 50Ω. 2.jntuworld. Explain your answer. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is always greater than current fall and rise times.jntuworld.com . How do you expect the gate source capacitance of a MOSFET to varry with gate source voltage. 3. Kharagpur 27 www. gfs = 3. CGD = 250 PF. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field strength of 5 × 106 V/cm and a safely factor of 50%. The switching frequency is 50 kHz. CGS = 800 PF.com Practice Problems 1. The MOSFET is used to switch an inductive load of 15 Amps from 150V supply.

www. When the gate voltage is zero the thickness of the gate-source capacitance is approximately equal to the thickness of the gate oxide layer. as vGS is increased further free electrons generated by thermal ionization get attracted towards the gate oxide-semiconductor interface. As the gate source voltage increases the width of the depletion layer in the p body region also increases. Since the depletion layer is a region of immobile charges it in effect increases the thickness of the gate-source capacitance and hence the value of this capacitances decreases with increasing vGS.5 3.com . Kharagpur 28 www.jntuworld. 2.vGS ) di D d = g fs vGS = g fs dt dt R g CGS During current rise Vgg >> vGS g fs di Vgg ∴ D ≈ dt R g CGS ∴ ∴ t ri = t fi ≈ Io R g CGS g fs Vgg where Io = load current. Io Vgg d v DS = ≈ dt R g CGD R g CGD Version 2 EE IIT. From the given data the break down gate source voltage v GS BD = E BD × t gs where EBD = Break down field strength tgs = thickness of the oxide layer. 1.Vg s .VGS (th) ) ( Vgg . We Know that for MOSFET i D = g fs ( VGS .5 vgs Max Max ∴ = vGS BD = 50 V ∴ vgs = 50 V ≈ 33 Volts.jntuworld. There after the value of CGS remains more or less constant. Now From equation (6. However. So v GS Let vgs safety.4) Vgg . BD = 5×106 ×1000×10-8 = 50V Max be the maximum allowable gate source voltage assuming 50% factor of 1.com Answer to practice problems 1. When vGS is above vgs (th) the inversion layer completely screens the depletion layer and the effective thickness of the gate-source capacitance becomes once again equal to the thickness of the oxide layer. These free electrons screen the depletion layer partially and the gate-source capacitance starts increasing again.

o dVDS g fs = ∴ dt R g CGD ∴ t ri = ∴ t fv = VD Vgg .9 energy loss during switching occurs during intervals tri . tfv2.jntuworld.v gs (th) . Io = dt CGD R g I But Vgs . During tri i D = g fs (vgs . For simplicity it will be assumed that tfv2 = trv2 = 0.Vgs (th) - Io R g CGD g fs Energy loss during tfv is E ON2 = 1 t fv Io VD 2 VD 2 Io = R g CGD I 2 ⎛ Vgg .v gs di D d = g fs v gs = g fs dt dt (CGS + CGD )R g g fs Vgg di D ≈ sinceVgg >> v gs during current rise dt (CGS + CGD )R g Io (CGS + CGD )R g g fs Vgg Energy loss during tri is V I2 1 E ON1 = t ri VD Io = D o (CGS + CGD )R g 2 2g fs Vgg During tfv dVDS Vgg . Also the rise and fall of iD and vDS will be assumed to be linear. 4. Io V ∴ t rr = t fv ≈ D R g CGD where VD = Load voltage.trv1.com Since Vgg >> Vgs.www.jntuworld.vgs (th)) ∴ ∴ Vgg . Referring to Fig 6. Io = o + vgs (th) g fs I Vgg . trv2.com . Kharagpur 29 www. Vgg ∴ I t ri t = fi = o t rr t fr VD CG S g fs CG D That is current rise and fall times are much shorter than voltage rise and fall times. and tfi.o ⎞ ⎜ g fs ⎟ ⎝ ⎠ ∴ Energy loss during Turn on is Version 2 EE IIT. tfv1.Vgs.vgs (th) .

www. tri = tfi.jntuworld. Kharagpur 30 www.jntuworld.com ⎤ VD Io R g ⎡ Io ( CGS + CGD ) VD CGD + ⎢ ⎥ 2 ⎢ g fs Vgg ( Vgg .Vgs (th) ) ⎥ ⎣ ⎦ From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.com . tfv = trv) E ON = E ON1 + E ON2 = E ON = EOFF ∴ Total switching energy lass is Esw = EON + EOFF = 2 EON ⎡ ⎢ VD Vgg I g ⎛ C ⎞ ∴ E sw = VD Io R g CGD ⎢ o fs ⎜1+ GS ⎟ + ⎢ Vgg ⎝ CGD ⎠ Vgs (th) Io g fs ⎢ Vgg Vgg ⎣ ⎤ ⎥ ⎥ ⎥ ⎥ ⎦ ⎡ ⎤ ⎢ ⎥ VD Vgg ⎛ C ⎞I g ⎥ ∴ Psw E sw = VD Io R g CGD f sw ⎢⎜1+ GS ⎟ o fs + v gs (th) Io g fs ⎥ ⎢⎝ CGD ⎠ Vgg 1⎢ ⎥ Vgg v gg ⎦ ⎣ Substituting the values given Psw = 32 mw.e. Version 2 EE IIT.

jntuworld. Kharagpur 1 www.com .jntuworld.www.com Module 1 Power Semiconductor Devices Version 2 EE IIT.

Kharagpur 2 www.jntuworld.jntuworld.www.com Lesson 7 Insulated Gate Bipolar Transistor (IGBT) Version 2 EE IIT.com .

com . Draw the operational equivalent circuit of an IGBT and explain its operating principle in terms of the schematic construction and the operational equivalent circuit. Version 2 EE IIT. Kharagpur 3 www. operating principle and characteristics of Insulated Gate Bipolar Transistors (IGBT) Instructional objects On completion the student will be able to • • • • • • Differentiate between the constructional features of an IGBT and a MOSFET.jntuworld. Interpret the manufacturer’s date sheet of an IGBT. Draw the switching characteristics of an IGBT and identify its differences with that of a MOSFET.jntuworld.www. Design a basic gate drive circuit for an IGBT. Draw and explain the steady state output and transfer characteristics of an IGBT.com Constructional features.

jntuworld. this approach required the use of a high voltage power MOSFET with considerable current carrying capacity (due to low current gain of the output transistor).www. MOSFETs have a higher on state resistance per unit area and consequently higher on state loss. since no path for negative base current exists for the output transistor. This device along with the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT completely. this device was also not a true replacement of a BJT since gate control was lost once the thyristor latched up. The IGT device has undergone many improvement cycles to result in the modern Insulated Gate Bipolar Transistor (IGBT). its turn off time also tends to get somewhat larger.1.2 Constructional Features of an IGBT Vertical cross section of a n channel IGBT cell is shown in Fig 7. 7. many researches began to look at the possibility of combining these technologies to achieve a hybrid device which has a high input impedance and a low on state resistance. The obvious first step was to drive an output npn BJT with an input MOSFET connected in the Darlington configuration. However. On the other hand. initial claims of infinite current gain for the power MOSFETs were diluted by the need to design the gate drive circuit capable of supplying the charging and discharging current of the device input capacitance. This is particularly true for higher voltage devices (greater than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg. This is especially true in high frequency circuits where the power MOSFET is particularly valuable due to its inherently high switching speed. However. Also.com 7.jntuworld. After several such attempts it was concluded that for better results MOSFET and BJT technologies are to be integrated at the cell level.com . Kharagpur 4 www. However. These devices have near ideal characteristics for high voltage (> 100V) medium frequency (< 20 kHZ) applications. Version 2 EE IIT. SMPS). With the discovery that power MOSFETs were not in a strong position to displace the BJT.1 Introduction The introduction of Power MOSFET was originally regarded as a major threat to the power bipolar transistor. This was achieved by the GE Research Laboratory by the introduction of the device IGT and by the RCA research laboratory with the device COMFET. An alternative hybrid approach was investigated at GE Research center where a MOS gate structures was used to trigger the latch up of a four layer thyristor. Although p channel IGBTs are possible n channel devices are more common and will be the one discussed in this lesson.

jntuworld. The n type drain layer itself may have two different doping levels. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J2) of the device. it does so at the cost of lower reverse break down voltage for the device. since the reverse break down voltage of the junction J1 is small.2) including the insulated gate structure and the shorted body (p type) – emitter (n+ type) structure. Important resistances in the current flow path are also indicated.jntuworld. Version 2 EE IIT.www.2(a). is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. The doping level and physical geometry of the p type body region however. The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This construction of the device is called “Punch Trough” (PT) design.1: Vertical cross section of an IGBT cell. A large number of basic cells as shown in Fig 7. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. n-p-n transistor and the driver MOSFET are shown by dotted lines in this figure. The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig 7. However.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT device. it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. The Non-Punch Through (NPT) construction does not have this added n+ buffer layer. The lightly doped nregion is called the drain drift region.com Emitter SiO2 (Gate oxide) J3 J2 J1 + - Gate SiO2 (Gate oxide) Body region Drain drift region Buffer layer Injecting layer n p nn+ p+ Collector n Fig.com . Kharagpur 5 www. However. This layer forms a pn junction with the drain layer and injects minority carriers into it. 7. The constituent p-n-p transistor. The rest of the construction of the device is very similar to that of a vertical MOSFET (Link to 6.

The modern IGBT is latch-up proof for all practical purpose.com Gate Emitter MOSFET n+ p J3 Body spreading resistance n-p-n Drift resistance p-n-p nn+ p+ J1 J2 (a) Drift region resistance Collector Collector Drift region resistance Collector Gate Body spreading resistance Gate (b) Emitter Emitter (c) Fig. The top p-n-p transistor is formed by the p+ injecting layer as the emitter. Version 2 EE IIT. the p type body and the n type drain as the emitter. the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower n-p-n transistor.3(a) and (b) shows the circuit symbol and photograph of an IGBT. Fig 7. the voltage drop across this resistance may forward bias the lower n-p-n transistor and initiate the latch up process of the p-n-p-n thyristor structure. 7.jntuworld. the n type drain layer as the base and the p type body layer as the collector. due to imperfect shorting.jntuworld. Kharagpur 6 www. A major effort in the development of IGBT has been towards prevention of latch up of the parasitic thyristor. (a) Schematic structure (b) Exact equivalent circuit. The base of the lower n-p-n transistor is shorted to the emitter by the emitter metallization. This has been achieved by modifying the doping level and physical geometry of the body region. However. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. If the output current is large enough. The lower n-p-n transistor has the n+ type source.2(b) shows the exact static equivalent circuit of the IGBT cell structure.www. base and collector respectively. (c) Approximate equivalent circuit Fig 7.com .2: Parasitic thyristor in an IGBT cell.

viii) body. The IGBT cell has a parasitic __________________ structure embedded into it.3: Circuit symbol of an IGBT.com . The forward blocking voltage of an IGBT is determined by the __________________ and __________________ of the drain drift layer. IGBT is suitable for __________________ voltage __________________ frequency applications. iv. latch up. Answers: i) hybrid. From the input side the IGBT behaves essentially as a Version 2 EE IIT.3 Operating principle of an IGBT Operating principle of an IGBT can be explained in terms of the schematic cell structure and equivalent circuit of Fig 7.jntuworld.com C G E (a) (b) Fig. vii. vii) thryistor. The doping level and physical geometry of the IGBT __________________ region is designed to be considerably different from that of a MOSFET to prevent its __________________. BJT . Kharagpur 7 www. ii) high. symmetrical . v) low. v. doping level . vi) thyristor. An IGBT is a __________________ device combining the advantages of a __________________ and a __________________. In an IGBT cell structure a __________________ type injecting layer is added on top of the drain of an n channel MOSFET. i. A “punch through” IGBT has __________________ reverse break down voltage while the “Non punch through” IGBT has __________________ voltage blocking capacity.1 Fill in the blank(s) with the appropriate word(s). (a) Circuit symbol. viii. 7. iv) thickness.2(a) and (c). Exercise 7. iii) p+ . iii. vi. latch up . (b) Photograph. MOSFET. ii.www.jntuworld. The parasitic __________________ structure of an IGBT cell can __________________ at large collector current due to imperfect body emitter shorting. 7. medium .

2 (b) and eliminate the possibility of static latch up of the IGBT. They appear qualitatively similar to those of a logic level BJT except that the controlling parameter is not a base current but the gate-emitter voltage. The next component of the voltage drop is due to the drain drift region resistance. From the above discussion it is clear that the n type drain drift region acts as the base of the output p-n-p transistor.jntuworld. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J2. Therefore.com . when the gate emitter voltage is less then the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The doping level and the thickness of this layer determines the current gain “∝” of the p-n-p transistor. This inversion layer (channel) shorts the emitter and the drain drift layer and an electron current flows from the emitter through this channel to the drain drift region. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization.4 (a). This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. When the gate emitter voltage exceeds the threshold. Version 2 EE IIT. This helps to reduced the voltage drop across the “body” spreading resistance shown in Fig 7. when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p transistor also remains off.4 Steady state characteristics of an IGBT The i-v characteristics of an n channel IGBT is shown in Fig 7. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET.com MOSFET. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The voltage drop across J1 follows the usual exponential law of a pn junction. an inversion layer forms in the p type body region under the gate. In terms of the equivalent current of Fig 7. The total on state voltage drop across a conducting IGBT has three components.jntuworld. Very small leakage current flows through the device under this condition. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. 7. Kharagpur 8 www.www. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET. This in turn causes substantial hole injection from the p+ type collector to the drain drift region.2(c).

is determined by the external load line ABC as shown in Fig 7.4(b). this break down voltage is independent of the collector current as shown in Fig 7.4 (a)) is determined by the avalanche break down voltage of the body – drain p-n junction.www. The device. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing vgE.4(a). In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. it is desirable to use the maximum permissible value of vgE in the ON state of the device.4(a)).com VCC RL ic + C VcE E - iC G VgE Increasing Saturation V VgE6 gE VCC Active RL VgE5 Load line A VgE4 VgE3 B VgE2 VgE1 iC F Fault Load line gfs C VCC VCES VCE VgE VRM Cut off VgE (th) (b) (a) Fig.com . Since vCE decreases with increasing vgE. However.jntuworld. IGBTs of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off mode. under this condition is said to be operating in the cut off region. The ratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is an important parameter in the gate drive circuit design. At one point vCE becomes less than vgE – vgE(th). 7. (b) Transfer characteristics When the gate emitter voltage is below the threshold voltage only a very small leakage current flows though the device while the collector – emitter voltage almost equals the supply voltage (point C in Fig 7. for Punch Through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer. As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation.4(a). Limiting VgE also helps to limit the fault current through Version 2 EE IIT. Under this condition the device is said to be in the saturation mode.2(c)) enters into the ohmic region and drives the output p-n-p transistor to saturation. This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. Under this condition the driving MOSFET part of the IGBT (Fig 7. on the other hand. As the gate emitter voltage is increased further ic also increases and for a given load resistance (RL) vCE decreases. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig 7. In this mode. vgE(Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the “latch-up” condition discussed earlier. The collector emitter voltage. Unlike a BJT. the collector current ic is determined by the transfer characteristics of the device as shown in Fig 7. however. Kharagpur 9 www.4: Static characteristics of an IGBT (a) Output characteristics.jntuworld.

In an IGBT most of the collector current flows through the __________________ and not through the __________________. When the gate-emitter voltage of an IGBT is below threshold if operates in the __________________ region. Electrons arriving through the drive MOSFET causes __________________ injection from the __________________ to the drain drift region. It is interesting to note that an IGBT does not exibit a BJT-like second break down failure. vi) transfer. Limiting vgE to vgE6 restricts the fault current corresponding to the operating point F. ii. i.jntuworld.www. When the gate emitter voltage is below __________________ no __________________ layer is formed in the p type body region. inversion. x.2 Fill in the blank(s) with the appropriate word(s). v) cut-off. An IGBT does not exhibit __________________ failure mode.com the device. v. The forward voltage drop of an IGBT in the saturation region remains approximately __________________. vii)saturation. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig 7. iv. ix) positive. collector. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device. viii. linear. x) second break down. viii) constant. iii. In the active region of operation the collector current of an IGBT is determined by the __________________ characteristics which is reasonably __________________ over most of the collector current range. From the input side the IGBT behaves essentially as a __________________. Exercise 7. Answers: i) MOSFET. vii.jntuworld. An IGBT has small __________________ temperature coefficient of on state voltage drop. ix. This helps to prevent second break down failure of the device and also facilitates paralleling of IGBTs. iv) MOSFET.4(a)) the fault load line is given by CF. Version 2 EE IIT.com . Kharagpur 10 www. vi. ii) threshold. For the same load resistance as the vgE of an IGBT is increased it enters __________________ region. Since. iii) hole. BJT. in an IGBT most of the collector current flows through the drive MOSFET with positive temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly positive.

particularly during turn off. However.com 7.jntuworld. Therefore. Also in a modern IGBT a major portion of the total device current flows through the MOSFET.jntuworld. similar to that of a Power MOSFET. Another important difference is in the gate drive requirement. This is expected.5: Inductive switching circuit using an IGBT (a) Switching circuit. (to be discussed later) the gate emitter voltage of an IGBT is maintained at a negative value when the device is off. (b) Equivalent circuit of the IGBT iD DF C E (b) G Q1 + VCE D CGD G CgE S E The switching waveforms of an IGBT is.www. the switching voltage and current waveforms exhibit a strong similarity with those of a MOSFET. 7.5(b).com . To avoid dynamic latch up.5(a). Kharagpur 11 www. VCC C iL iC Rg ig Vgg (a) Fig. Version 2 EE IIT.5 Switching characteristics of IGBT Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive switching circuit shown in Fig 7. the output p-n-p transistor does have a significant effect on the switching characteristics of the device. The equivalent circuit of the IGBT shown in Fig 7. in many respects. since the input stage of an IGBT is a MOSFET as shown in Fig 7.5 (b) will be used to explain the switching waveforms.

First the gate-drain capacitance Cgd will increase in the MOSFET portion of the IGBT at low drain-source voltages.6. the on state voltage of the device settles down to vCE(sat). Two factors contribute to the slowing down of voltage fall. The gate emitter voltage vgE follows Vgg with a time constant τ1. some amount of current continues of flow through the output p-n-p transistor due to stored charge in its base. During this period (tfi1) the device current falls rapidly.jntuworld. Thereafter.com . ic increases following the transfer characteristics of the device till vgE reaches a value vgEIL corresponding to ic = iL.jntuworld. The free wheeling diode current falls from IL to zero during this period.IL ∫∫ t τ1 = Rg(CGS+CGD1) VCE VCC VCE(sat) ∫∫ VCC t iC iD IL IL tfv2 ∫∫ IL ∫∫ IL tfi2 t tdON tri tfv1 trv1 trv2 tfi1 Fig. 7. Similarity of these waveforms with those of a MOSFET is obvious. The turn ON process ends here. The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th). However. To turn on the IGBT the gate drive voltage changes from –Vgg to +Vgg. Since there is no reverse voltage applied to the IGBT terminals that could generate a negative drain current. A long tfi2 is undesirable. After ic reaches IL. the pnp transistor portion of the IGBT traverses the active region to its on state more slowly than the MOSFET portion of the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays relatively slowly forming a current fail. Second. The only way these excess carriers can be removed is by recombination within the IGBT. Since the drain source voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1.6: Switching waveforms of an IGBT. when the drive MOSFET turns off. The turn off process of an IGBT follows the inverse sequence of turn ON with one major difference. vgE becomes clamped at vgE IL similar to a MOSFET. because the power dissipation Version 2 EE IIT.com Vgg VgE VgE(th) ∫∫ τ2 = Rg(CGS+CGD2) VgE(th) VgE. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns off. vCE also starts falling during this period. there is no possibility for removing the stored charge by carrier sweep-out. First vCE falls rapidly (tfv1) and afterwards the fall of vCE slows down considerably. Kharagpur 12 www.www.IL VgE. This period is called the current rise time tri. Once the pnp transistor is fully on after tfv2. The switching waveforms of an IGBT is shown in Fig 7.

jntuworld. Provide protection against short circuit fault. Control dvce dt during switching to avoid IGBT latch up. However. References [4] & [5] provide good discussion on this subject.7: IGBT gate drive circuit (a) Gate drive (b) Equivalent circuit of the gate drive during turn on and turn off. Kharagpur 13 www. Minimize switching loss. Apply a negative voltage during off period. tfi2 can be reduced by decreasing the excess carrier life time in the p-n-p transistor base. +Vcc RC +Vgg Ri Vi (Logic level) Opto isolator + RB Q1 Q2 R G IGBT E Level Shifting -Vgg Comparator RB β1 +1 -Vcc Totem pole gate drive amplifier (a) R G -Vgg R Vgg RB β2 +1 G To IGBT Gate E Turn on equivalent circuit To IGBT Gate E Turn off equivalent circuit (b) Fig. on state losses will increase. Fig 7. Version 2 EE IIT.com in this interval will be large due to full collector-emitter voltage.7(a) shows a simplified IGBT gate drive circuit. The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. in the process.jntuworld. Control dic dt during turn ON and turn off to avoid excessive Electro magnetic interference (EMI). • • • • • • Apply maximum permissible VgE during ON period. Therefore. judicious design trade offs are made in a practical IGBT to give minimum total loss. In particular.www. Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. it should.com . 7.

Maximum gate-emitter voltage (VgES): This is the maximum allowable magnitude of the gateemitter voltage (of both positive and negative polarity) in order to • • Prevent break down of the gate oxide insulation. Forward Transconductance (gfs): This is again specified at a low value of vCE. Gate-emitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES. This stage converts the unipolar (usually positive) out put voltage of the opto-isolator to a bipolar (±Vgg) signal compatible to the IGBT gate drive levels. Collector emitter saturation voltage (VCE(sat)): This is specified at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES. Conversely. Maximum continuous collector current (IC): This is the maximum current the IGBT can handle on a continuous basis during ON condition. This is specified at a given negative gate emitter voltage or a specified resistance connected between the gate and the emitter.com . If VCC > Vgg then both Q1 and Q2 will operate in the active region and reasonably constant value of β1 & β2 of these two transistors can be used for analysis purpose. Version 2 EE IIT. These equivalent circuits along with the model of the IGBT input MOSFET can be used to analyze the switching performance of the device.com The logic level gate drive signal is first opto-isolated and fed to a level shifting comparator. Maximum pulsed collector current (ICM): This is the maximum collector current that can flow for a specified pulse duration. Restrict collector current to ICM. It is specified at a given case temperature with derating curves provided for other case temperatures. This current is limited by specifying a maximum gate-emitter voltage. Collector leakage current (ICES): This is the leakage collector current during off state of the device at a given junction temperature.www. For more detailed data the output characteristics of the device for different vgE and expanded near the saturation zone is also provided.7(b). The output of the comparator feeds a totem pole output amplifier stage which drives the IGBT. 7. The equivalent circuit of the gate drive during turn on and off are shown in Fig 7. gate-emitter voltage and collector current. For more detailed data the transfer characteristics of the device (ic vs vgE) is also provided. Gate-emitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage and collector current.6 IGBT ratings and safe operating area Maximum collector-emitter voltage (VCES): This rating should not be exceeded even on instantaneous basis in order to prevent avalanche break down of the drain-body p-n junction.jntuworld. Kharagpur 14 www.jntuworld. for a desired switching performance a suitable gate drive circuit can be designed.

Like other devices the maximum power dissipation limit increases with reduction in the on pulse width. output and transfer capacitances (Cies. Variation of these parameters as functions of vCE are also supplied. tfi): These times are specified for inductive load switching as functions of gate charging resistance and collector current.8: Safe operating area of an IGBT (a) FBSOA. On the left side it is restricted by the forward voltage drop characteristics. The RBSOA for low values of dvCE dt is rectangular. i.3 Fill in the blank(s) with the appropriate word(s). However. for increased dvCE dt the upper-right hand corner is progressively cut out. In addition turn on and turn off energy losses per switching operation are also specified. at ICM this voltage starts increasing as the IGBT starts entering active region. iC ICM IC 10-5sec 10-4sec 10-3sec 10-2sec DC VCES VCE iC ICM 1000V/μS 2000V/μS 3000V/μS (a) (b) VCES VCE Fig. collectoremitter and gate-drain capacitances of the device respectively. Version 2 EE IIT. (b) RBSOA. specified at a given collectoremitter voltage. The device user can easily control dvCE dt by proper choice of Vgg and the gate drive resistance. The IGBT has robust SOA both during turn on and turn off. On the top the FBSOA is restricted by ICM. The reason for this restriction on the RBSOA is to avoid dynamic latch up.jntuworld. Kharagpur 15 www. gate-emitter.com . trv. tfv.www.com Input. Coes & Cres): These are.8 (a) shows the FBSOA. Fig 7. In a modern IGBT most of the collector current flows through the _________________ and not the _________________. Up to maximum continuous collector current this voltage remains reasonably constant at a low value.jntuworld. 7. Derating curve at other temperatures are also specified. Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in the device (both switching and conduction) on a continuous basis at a given case temperature. Exercise 7. The other two limits are formed by the maximum power dissipation limit and the maximum forward voltage limit. However. Switching times (td(ON) tri.

April 1991.com ii. of an IGBT during turn off should be controlled to prevent _________________ of the device. 2. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current during _________________ fault. “Power electronics. Converters. iii. Undeland. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing _________________ to avoid _________________ of the device. lower. negative.com . ix. slowly. al. During turn on of an IGBT the rate of fall of voltage slows down towords the end since the output p-n-p transistor traverses its _________________ region more _________________ compared to the drive MOSFET. x. Allen R. dvCE dt dic dt iv. Vol. [4] Version 2 EE IIT. (ii) latch up. The gate drive circuit of an IGBT should control _________________. (iii) active. BJT. The FBSOA of an IGBT is similar to that of a _________________ except that the on state voltage drop is much _________________. “Evolution of MOS Bipolar Power Semiconductor Technology”. No. 2003 B. (viii) decreases. “An Investigation of the drive circuit requirements for the Power Insulated Gate Bipolar Transistor”.www. (v) EMI. vol. Jayanta Baliga et. 4. 6 June 1984 pp 421-828. No. vii. (vii) short circuit. John Wiley & Sons. (iv) current tail. Collector emitter saturation voltage of an IGBT _________________ with increasing gate-emitter voltage. Reference [1] [2] [3] B. v. Answer: (i) MOSFET. 76. (x) dvCE dt .jntuworld. April 1988. pp 409-418. Jayanta Baliga. base. IEEE transaction on Electron Devices. Hefner. Kharagpur 16 www. Power Device”. Robbins. latch up. Applications and Design”. ED-31. (ix) MOSFET. To avoid _________________ the gate emitter voltage of an IGBT is maintained at a _________________ value when the device is off. to avoid excessive vi. viii. “The Insulated Gate Transistor: A new Three-Terminal MOSControlled Bipolar. Proceedings of the IEEE. (vi) Latch up.jntuworld. vol. IEEE Transactions on Power Electronics. Mohan. During turn off of an IGBT a _________________ is formed due to excess stored charge in the _________________ region of the output p-n-p transistor. 6 No.

The maximum allowable collector current in an IGBT is restricted by the static latch up consideration. The switching characteristics of an IGBT is similar to that of a MOSFET.jntuworld. Lesson Summary • • • • IGBT is a hybrid device which combines the advantages of MOSFET and BJT. the gate emitter voltage of the device is maintained at a negative value during it’s off period. During turn off. the collector current of an IGBT is determined by the gate-emitter voltage which can be limited to a given maximum value to limit the fault current through the device in the event of a load short circuit. To avoid dynamic latch up of the parasitic thryrstor in an IGBT. When the gate-emitter voltage of an IGBT is below threshold it operates in the cut off region. The operational equivalent circuit of an IGBT has an n channel MOSFET driving a p-n-p BJT.jntuworld. SEMIKRON International. al. Kharagpur 17 www. For a given load resistance the operating point of an IGBT can be moved from cut off to saturation through the active region by increasing the gate-emitter voltage. Germany. The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state voltage drop being much lower. Vol.www.com • • • • • • • • • • • • • . No-3 may 1995. Version 2 EE IIT. An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power MOSFET. From the operational point of view an IGBT is a voltage controlled bipolar device. In the active region. The IGBT cell structure embeds a parasitic thyristor in it. Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and ndrain drift layer. “SEMIKRON Power Electronics News 2001”. Like other semiconductor devices on IGBT can also operate in the cut off active and saturation regions. 10. An IGBT does not exhibit second break down phenomena as in the case of a BJT. “A New Driving circuit for IGBT Devices”.com [5] [6] Carmelo Licitra et. the collector current of an IGBT can exhibit “current tailing” due to stored base change in the base region of the output p-n-p transistor. IEEE Transaction on Power Electronics. They have significantly lower conduction loss. The IGBTs have a slightly positive temperature coefficient of the on-state voltage drop which makes paralleling of these devices simpler. Latching up of this thyristor is prevented by special structuring of the body region and increasing the effectiveness of the body shorting.

com • CE The RBSOA of an IGBT is rectangular for low values of dt . For higher dvCE dt the upper right half corner of the RBSOA is progressively cut-out to prevent “dynamic latch up of the device”. Kharagpur 18 www.jntuworld.www.com . dv • The IGBT can switch at moderately high frequency (<20 kHZ) and in this range is likely to replace the BJTs in all medium to high power applications. Version 2 EE IIT.jntuworld.

com .com Practice Problems and Answers Version 2 EE IIT.jntuworld.jntuworld. Kharagpur 19 www.www.

(a) In an IGBT a major portion of the collector current flow through the driver MOSFET section which has a voltage rating almost same as the device. Q4. Kharagpur 20 www. Find out the maximum current flowing through the IGBT in the event of a short circuit fault across the load.7 (a) following data are given Vgg = 15 V.www. β2 for Q2 = 50. R = 30Ω. CgD = 500pF. How can it be prevented? What steps are taken in the cell structure design of an IGBT to minimize the “tail current” during turn off operation. RB = 2.4 (a). Q3.2 KΩ. VgE (th) of IGBT = 4V.jntuworld. What effects do the width and doping level of the drain drift region of an IGBT have on its performance.com .com Q1. Then how does the on state voltage drop of an IGBT remain low compared to an equivalent MOSFET? (b) An IGBT is used to switch a resistive load of 5Ω from a DC supply of 350 volts as shown in the inset of Fig 7. For the IGBT.jntuworld. Q2. The ON state gate voltage is vgE = 15v. Vcc = 20 V. In the basic gate drive circuit of an IGBT shown in Fig 7. Find out maximum values of dic dt and dvCE dt during Turn on and Turn off of the IGBT. Version 2 EE IIT. Q5. Also find out the power dissipation inside the device. vgE (th) = 4 volts and gts = 25. β1 for Q1 = 50. What do you under stand by “dynamic latch up” of an IGBT. The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply. gfs = 40 CgE = 4nF.

the reduced voltage drop across a conducting IGBT is due to reduction of the drain drift region resistance by “conductivity modulation”. In this region iC = gfs ( vgE . • 2. the collector-emitter voltage drop across the device exhibits a slightly positive temperature coefficient. This eliminates the possibility of second break down failure in IGBTs and simplifies paralleling of these devices. the drain drift region constitutes the base of the upper p-n-p transistor. Thus the possibility of turning on this transistor and consequent latch up of the device is minimized. Referring to Fig 7. (a) The total voltage drop across a conducting IGBT has three components.2 (b). The consequent conductivity modulation reduces the resistance (and hence the voltage drop) in this region. The voltage drop across the emitter-base junction of the output p-n-p transistor follows the usual exponential low of a p-n junction.jntuworld.jntuworld.com Answers to Practice Problems 1. The width and the doping level of this layer determines the current gain “∝” of this transistor.4 ) = 275 Amps Power dissipation inside the device will be PD = vCE iC Max = 350 × 275 = 96. • • The width and doping level of the drain drift layer of an IGBT affects the performance of the IGBT in several ways. However. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector.www. The next component of the voltage drop is due to the drain drift region resistance. In a normal high voltage MOSFET this component of the voltage drop is large due to lower doping level (necessary for blocking high voltage) of this region.vgE (th) ) Substituting the given values iC Max = 25 (15 . in a conducting IGBT electrons arriving at the drain drift region through the MOSFET channel causes large minority carrier injection from the p+ collector. They determine the forward break down voltage of the IGBT. This helps to reduce the voltage drop across the body spreading resistance between the base and emitter of the lower p-n-p transistor. The third component of the IGBT voltage drop occurs across the channel of the driving MOSFET and is same as that of an equivalent high voltage MOSFET.com . Kharagpur 21 www. (b) In the event of a short circuit across the load the voltage across the device will be 350 volts and the IGBT will operate in the active region.25 kW Version 2 EE IIT. Since the major part of the device current flows through the MOSFET which has a positive temperature coefficient of drain source voltage drop. Therefore.

Q1 & Q2 operates in the active region.vgE (th) ) ∴ dic d = gfs vgE dt dt But from the equivalent circuit of the IGBT gate drive circuit during turn on Vgg . This n+ buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes from the drain drift layer.drain drift layer. the voltage across the driver MOSFET increases rapidly. During turn on and turn off the IGBT passes through the active region.vgE ) dic d = gfs vgE = B dt dt ( CgE + CgD ) R + βR+1 1 ( In the active region Vgg >> vgE Also since Vcc > Vgg.com . When vgE is greater than vgE(th) the collector current is given by iC = gfs ( vgE . Newer NPT IGBT designs have more than 90% of the total current carried by the MOSFET section of the device. under dynamic conditions. 4. 5. Non punch through IGBTs attack the current tailing problem by minimizing the magnitude of the current during the failing interval. This rapid increase in the depletion layer width temporally increases the current gain “∝” of the output p-n-p transistor and causes latch up of the device at a lower collector current than would have been necessary for static latch up.jntuworld.com 3.vgE d vgE = B dt ( CgE + CgD ) R + βR+1 1 ( ) ) ∴ gfs ( Vgg .jntuworld. Punch Through and Non-punch through IGBTs solve the problem of tail current by two different approaches. Kharagpur 22 www. Static latch up in an IGBT occurs when the continuous ON state current exceeds a critical value. This voltage is blocked by the drain-body p-n junction. Punch through IGBT s attempt to minimize the current tailing problem by shortening the duration of the tailing time. Thus the tail time is reduced. This is done by designing the IGBT so that the MOSFET section carries as much of the total current as possible. To block the rapid build up of the voltage the width of the depletion region in the drain drift layer also increases rapidly. During turn off. Substituting the given values Version 2 EE IIT. This is done by reducing the excess carrier life time in the n+ buffer layer compared to the n. However.www. when the IGBT is switching from on to off state if may latch up at drain current less than this value.

and β1 = β2 dvCE during turn off will be same dt So dvCE = 2.vgE IL dvCE 15 .82 × 109 A/Sec -12 2200 dt 4500 × 10 × ( 30 + 51 ) dic Since β1 = β2 .5. during turn off will also have the same value dt dic = 1.82 A/ns So dt Since load current is 50 Amps and gfs = 40 vge IL = vgE (th) + IL = 5. dt Version 2 EE IIT.67 × 108 V/Sec Since Vgg+ =Vgg.com .25 volts gfs Daring turn on CgD V -v I dvCE = ig IL = gg gEB L R dt R + β+1 ∴ dvCE during turn ON is dt Vgg .jntuworld.67 × 108 V/Sec or 267 V/μs.jntuworld.www. Kharagpur 23 www.25 = = RB dt 500 × 10-12 ( 30 + 2200 ) CgD R + β +1 51 ( 1 ) = 2.com dic 40 × 15 = = 1.

Kharagpur www.com Module 1 Power Semiconductor Devices Version 2 EE IIT.www.jntuworld.jntuworld.com 1 .

jntuworld.com 2 .jntuworld.com Lesson 8 Hard and Soft Switching of Power Semiconductors Version 2 EE IIT. Kharagpur www.www.

Power loss in the converter is the aggregate of these losses. The losses corresponding to each contribute to the temperature rise of the integrated module. Switching frequencies vary from 50 Hz in a SCR based AC-DC Phase Angle Controller to over 1. Special techniques are employed to obtain clean turn-on and turn-off of the devices. the uncontrolled device operates mainly as a slave to the former.com This lesson provides the reader the following (i) (ii) (iii) (iv) To highlight the issues related to device stresses under Hard switching. Enable the choice of the appropriate switching strategy Soft and Hard Switching Semiconductors utilised in Static Power Converters operate in the switching mode to maximise efficiency. For the SCRs’ the turn-off data helps to dimension the 'commutation components' or to set the 'margin angle'. Losses in Power Semiconductors A converter consists of a few controlled and a few uncontrolled devices (diodes).0 MHz in a MOSFET based power supply. A protective inductive snubber to limit the turn-on di/dt is usually utilised. While the first device is driven to turn-on or off. Occasionally the diode and the controlled device are housed in the same module. The switching or dynamic behaviour of Power Semiconductor devices thus attracts attention specially for the faster ones for a number of reasons: optimum drive. To suggest means of reducing such stresses with external circuitry. With SCRs’ 'forced commutation' and 'natural (line) commutation' usually described the type of switching. This chapter first examines the switching process. along with optimal control strategies and improved evacuation of the heat generated. estimates the device dissipation and indicates design procedures for the cooling system.jntuworld. Conduction losses account for the most significant part of total losses. This. permit utilisation of the devices with a minimum of deration. As a consequence. Both refer to the turn-off mechanism of the SCR. Present day fast converters operate at much higher switching frequencies chiefly to reduce weight and size of the filter components. Kharagpur www. the turn-on dynamics being inconsequential for most purposes.jntuworld. To propose alternative switching methods for stress reduction.www. power dissipation. EMI/RFI issues and switching-aidnetworks. switching losses now tend to predominate. causing the junction temperatures to rise.com 3 . Version 2 EE IIT.

This drop may be expressed as Vce (sat) (Ic) = V0 + R . To estimate if a power semiconductor rating is appropriate.com The losses can be segregated as follows: Total module dissipation Controlled device losses conduction Turn-off switching Turn-off Diode losses conduction Turn-off switching Turn-on Conduction Losses Conduction losses are caused by the forward voltage drop when the power semiconductor is on and can be described by (with reference to an IGBT) Fig. Version 2 EE IIT. The graph most accurately determines conduction losses. 3.jntuworld. usually the values valid for elevated temperature. Ic This relation defines the forward drop of an IGBT in a similar manner to a diode. The conditions in which the data are used should correspond to the application. The given data should be used as follows: Using the numerical value is the most simple way to determine conduction losses.Ic where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward voltage drop.data sheet numerical values are specified for typical application currents.www. The numerical value can be applied if the current in the device is equal or close to the specified current .1 Approximate forward voltage of IGBT and diode WC = Vce (sat)(Ic). should be used to calculate power losses because this is commonly the operating point at nominal load.jntuworld. Kharagpur www.com 4 . A part of the drop is constant while another part is collector current dependent. close to the maximum junction temperature TJmax .

However in general. Eon/off are the energy dissipated at turn-on/turn-off respectively. Data sheets indicates leakage current at certain blocking voltage and temperature. This means switching time intervals are short compared to the pulse duration at typical switching frequencies. be neglected. WB = Vb(I). but not always.2 Switching losses (appx) For IGBTs they are specified as an amount of energy. Eoff (IC)/(RG) with collector current IC and gate resistance RG are provided. Kharagpur www. Using the numerical value is again the most simple way to determine switching losses. The graphs permit the most accurate determination of switching losses. this means that using a data sheet value given for a blocking voltage higher than applied overestimates blocking losses. such as rise time tr and fall time tf in the data sheets. Switching losses occur during these switching intervals.jntuworld. The dependence between leakage current and applied voltage typically is exponential. Version 2 EE IIT. blocking losses are small and can often.jntuworld. 3. as can be seen from their switching times. given the parameters of the converter: RG and converter current IC.com Blocking Losses Blocking losses are generated by a low leakage current through the device with a high blocking voltage.IL Where IL is the leakage current and Vb(I) is the current dependemt blocking voltage. The numerical value can be applied if the switching operations are carried out at the same or similar conditions as indicated in the data sheet. Fig.com 5 . Switching Losses IGBTs are designed for use in switching converters and not for linear operation. Eon/off for a certain switching operation.www. Graphs for Eon(IC)/(RG ).

www. The off-state losses of the main device and the turn-on dissipation may be neglected for most cases. Eon / Eoff / Err ( working ) = Eon / Eoff / Err ( working ) • ⎡VCE ( working ) / VCE ( rated ) ⎤ ⎣ ⎦ Eon / Eoff / Err ( working ) = Eon / Eoff / Err ⎡ I C / I C ( rated ) ⎤ ⎣ ⎦ Where. However. the current in the free-wheel diode of the upper device decreases during the overlap period and the load current begins to commutate to the lower device. Version 2 EE IIT. a/b/c The power device in a converter mostly sees an inductive load. With an IGBT driven DC-DC chopper as an example. These diodes take a smaller time to quench the reverse recovery current compared to a soft recovery diode. Err are at the rated values only and have to be adjusted to the working values of voltage (DC bus). A simple circuit illustrating such a situation is shown in Fig. It becomes negative during reverse recovery of the upper free-wheel diode. Now if the lower device turns on. Kharagpur www. data for which is provided by the device manufacturer. This causes the transistor switching dissipation to increase. across the load is essential for clamping the induced voltages across the inductance when the device switches off. VCE (working) and load current. a. is the conduction duty ratio. Vs to appear across the transistor whenever it carries part of the inductor current in overlap mode with the FWD during both turn-on and turn-off modes. its presence causes the supply voltage. Eoff .jntuworld. FVF]+ [fc Err] where. The freewheeling diode FWD. fc the switching frequency and Eon .jntuworld. This di/dt is dictated by the recovery characteristic of the free-wheel diode. Fig 3. The values of Eon . Fast recovery “snappy” diodes can develop very high recovery di/dt when they are hard recovered by the rapid turn-on of a device in series with it in the same converter leg. Ic. Err are the respective energy losses.com 6 . the current in the circuit associated to the diode jumps to zero. When the free-wheel diode recovers. The lower device is off and that the load current is circulating through the free-wheeling diode of the upper device. Eoff .Vce(sat)Ic] +[fc(Eon + Eoff)] Watts Diode dissipation = Conduction losses + Reverse recovery losses = [ (1 . The parasitic line inductance Lp develops a surge voltage equal to Lp di/dt in opposition to the decreasing current. b and c are constants.3.2. 3.com Diode A surge voltage occurs when the free-wheel diode recovers. Corresponding ideal waveforms are also indicated. Consider a converter leg. the dissipation can be estimated as: IGBT dissipation = Conduction losses + Switching losses = [ .

toff being the turn on and turn-off times. Kharagpur www.com 7 . 3. 3. peak load current Im. The RCD does not also help reduce turn-on dissipation when the reverse recovery current of the diode and the SAN current add up with the load current with Vs again appearing across the device.t 0 T 2 M M f If actual waveforms are considered the dissipation is close to about double the above figure. turnoff energy is accumulated in the SAN. Example 3.IC plane is rectangular. which is ultimately dissipated in the resistor.1 Derive the expression for the power dissipation during turn-on and turn-off of a transistor unassisted by a SAN.jntuworld.2. VM.com Fig. similarly 1/2.www. Solution The transition of the swichings in the VC .V . However. The controlled rise of the collector voltage of the transistor aids this process. The energy dissipated in each turn-off switching cycle is t off 1 W = ∫ VT .jntuworld. I T dt = .ton. Assume idealised waveforms. Fig.3 Typical current and voltage transients during turn-on and turnoff of a clamped-inductive load and transitions in the V-I plane.I . Version 2 EE IIT. The dissipation at turn-on is. An RCD Switching-aid-network connected across the device reduces turn-off dissipation. The supply voltage is Vm.I M. and tr.

t 2 1 f .2 For a transistor carrying a collector current IM and having a turn--off time tf. Thus. 2 2 2C ⎛ t i = I M ⎜1 − ⎜ t f ⎝ The Transistor current can be written as: The dissipation in the transistor is WT = ∫ v.jntuworld. Watts ⎟ dt = ⎟ 2C 12 ⎠ 2 When the transistor switches off.www. Calculate the corresponding losses in the transistor and in the SAN.jntuworld.4 Current and voltage waveforms at the Main Terminals of the switch with an R-C-D SAN. and in the associated FWD and SAN diode Example 3. the nearly constant load current linearly charges up the capacitor till it reaches the supply voltage. The FWD is positively biased and there Version 2 EE IIT. Solution The action of the SAN in restricting the rise of transistor voltage till the current in it is extinguished is illustrated in Fig.com 8 .t ⎛ t ⎞ V = V0 ⎜ ⎟ = M f ⎜ ⎟ ⎜t ⎟ 2C ⎜ t f ⎟ ⎝ ⎠ ⎝ f ⎠ Where V0 is the voltage at the capacitor at the end of turn-off time tf.4.com Fig. Subsequently. 3.idt = ∫ 0 tf tf 2 I M . 3. find the details of a RCD SAN to restrict the voltage rise at the end of tf to half the supply voltage. Since the current is assumed to fall linearly during the period tf. Kharagpur www.t f ⎛ t ⎜1 − ⎜ tf 2C ⎝ V0 = IM t f ⎞ ⎟ ⎟ ⎠ 0 ⎞⎛ t ⎟⎜ ⎟⎜ tf ⎠⎝ 2 ⎞ I M . the collector voltage rises as: ⎛ t ⎞ I .

dt = t1 t2 1 IMt f 2 If this V0 is about 1/2 Vs.1. C≥ I M .jntuworld.www. The resistance should be able to limit the transistor current to its peak rating. the conduction losses in the IGBT would be Wc = δ .t f Vs − R. C≥ IM t f Vs The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the transistor during turn-off is 1 2 CVM F 2 Where F is the switching frequency.T ⎢ I cpVo + I cp .T ∫ I cVce ( sat ) dθ 0 π ⎡2 2 ⎤ 2 = 1 δ . 2 2 I cpVod + I cp Rd π 2 Version 2 EE IIT. During this period. Thus. PR = R≥ Vs − I M − I rr I CM Irr is the reverse recovery current of the FWD.R ⎥ 2 ⎣ π ⎦ Where Vo and R are as shown in Fig 3. If the capacitor has to discharge completely during the ON time. For the diode the dissipation is WF = 1 2 [1 − δ ].com is a short period of over-lap between the FWD and the SAN diode. the capacitor over-charges to some extent.jntuworld.com 9 .I M In a Sine-PWM controlled converter with a peak value of the fundamental current equal to Icp. If V0 is the capacitor voltage when the transistor current is extinguished. CV0 = ∫ i. Kharagpur www.

com Soft switching Fig. stresses on devices are heavily influenced by the switching frequencies accompanied by their switching losses. it would not be able to prevent the energy stored in the junction capacitance to discharge into the transistor at each turn-on. Soft switching techniques use resonant techniques to switch ON at zero voltage and to switch OFF at zero current.5 Basic topologies for a) Hard switch.jntuworld. Reduction of size and weight of converter systems require higher operating frequencies. The two basic configurations are as shown in Fig. 3. are rarely used. There is no transfer of dissipation to the resonant network which is non-dissipative.com .jntuworld. though there is a significant rise in conduction losses. Kharagpur 10 www.www. b) Zero-voltage switch and c) for a Zero current switch Hard switching and its consequences have been discussed above. which would reduce sizes of inductors and capacitors. It is obvious that switching-aid-networks do not mitigate the dissipation issues to a great extent. However. Even if used. There are negligible switching losses in the devices. Version 2 EE IIT. Turn-on snubbers though not discussed. 3.5.

Kharagpur 11 www. Version 2 EE IIT. Fig.jntuworld. the load current and the resonating current flows through the transistor. This current reaches a natural zero when the negative magnitude of the resonating current equals the load current. The peak voltage stress on the diode is also about twice the supply voltage. It is equivalent to the topology shown above. 3. On switching the transistor ON the current in it ramps up from zero but the diode continues conduction till this current reaches the load current Iout level. Both these stresses are significantly higher than that in a comparable Hard switched buck converter. with the SAN and for a Soft-Switched converter operation The switching trajectory in the voltage-current plane of a device is illustrated in Fig.6 comparing the paths for that of a Hard-switched operation without any SAN.com Fig.com .7 A ZCS resonant buck converter The ZCS converter is considered to be in stable operation with Load current Itrans flowing through the diode and the inductor Lf. It is indicatve of the stresses and losses. 3. The diode. 3. The transistor thus switches in the Zero Current mode for both turn on and turn off.jntuworld.www. on the other hand switches in the Zero Voltage mode under both situations. Subsequently. Consequently. The input capacitor and the one across the diode may be combined to arrive at this topology. The Capacitor Cr is charged to Vs. It must be noted that the peak current stress on the transistor is high . A Zero Current Switch based converter is provided as illustration to the soft switching mechanism. a Hard-switched with a R-C-D Switching-Aid-Network and a resonant converter. A designer would prefer the path to be as close as possible to the origin.6 Switching loci for a Hard-Switched converter without Switching-Aid-Networks.

The resonant converter reduces switching losses at the cost of higher voltage/current stresses on the devices. Objective type questions Qs#1 Which component of power dissipation in a Power Semiconductor device is reduced by an RCD Switching –Aid –Network? a) b) c) d) Ans: Off state losses Turn-on losses Turn-off losses On-state losses c) turn-off losses Qs#2 Does an RCD SAN reduce total switching losses? Ans: No. Kharagpur 12 www. Qs#3 Are resonant converters superior to the hard switched converter on all counts? Ans: No.jntuworld.com while switching losses are practically eliminated in this resonant converter. It transfers the losses from the device to itself. Version 2 EE IIT. conduction losses increase along with the device stresses.www.jntuworld.com . There is no scope of a SANs in resonant switching.

Kharagpur 1 www.com .com Module 2 AC to DC Converters Version 2 EE IIT.jntuworld.jntuworld.www.

jntuworld.www.jntuworld. Kharagpur 2 www.com Lesson 9 Single Phase Uncontrolled Rectifier Version 2 EE IIT.com .

jntuworld. Analyze the operation of single phase uncontrolled half wave and full wave rectifiers supplying resistive.jntuworld. capacitive and back emf type loads. Define and calculate the characteristic parameters of the voltage and current waveforms. Version 2 EE IIT. Kharagpur 3 www. Calculate the characteristic parameters of the input/output voltage/current waveforms associated with single phase uncontrolled rectifiers. inductive.com Operation and Analysis of single phase uncontrolled rectifiers Instructional Objectives On completion the student will be able to • • • • Classify the rectifiers based on their number of phases and the type of devices used.www.com .

Rectifiers are used in a large variety of configurations and a method of classifying them into certain categories (based on common characteristics) will certainly help one to gain significant insight into their operation. Power electronic devices used in the rectifier are ideal switches.www. • • The internal impedance of the ac source is zero.1 will be followed.com .com 9. power factor. Harmonic content in the output. • • • • • • Waveforms and characteristic values (average. no consensus exists among experts regarding the criteria to be used for such classification. reactive power requirement. harmonics etc. back emf type) will be presented. following simplifying assumptions will be made. Points of interest in the analysis will be. Unfortunately. Voltage and current ratings of the power electronic devices used in the rectifier circuit.1 Introduction One of the first and most widely used application of power electronic devices have been in rectification. Rectifier control aspects (for controlled rectifiers only) In the analysis. Kharagpur 4 www. unless specified otherwise. capacitive.jntuworld.jntuworld. In this lesson and subsequent ones the working principle and analysis of several commonly used rectifier circuits supplying different types of loads (resistive. the second assumption will remain in force. Reaction of the rectifier circuit upon the ac network. Rectifiers specially refer to power electronic converters where the electrical power flows from the ac side to the dc side. inductive. The first assumption will be relaxed in a latter module. However. Version 2 EE IIT. Influence of the load type on the rectified voltage and current. For the purpose of this lesson (and subsequent lessons) the classification shown in Fig 9. RMS etc) of the rectified voltage and current. In many situations the same converter circuit may carry electrical power from the dc side to the ac side where upon they are referred to as inverters. Rectification refers to the process of converting an ac voltage or current source to dc voltage and current.

jntuworld. can be defined.com This Lesson will be concerned with single phase uncontrolled rectifiers. 1 T 2 FRMS = f (t)dt ………………………….com .Fav Fav 2 2 = f FF -1 …………………….2) T ∫0 Form factor of f(fFF) : Form factor of ‘f ‘ is defined as F f FF = RMS …………………………………. Such commonly used terms are defined in this section.4) 2 Version 2 EE IIT. ˆ ˆ Peak value of f ( f ) : As the name suggests f = f max over all time. periodic over the time period T.jntuworld. characterizing the properties of “f”..(9. Average (DC) value of f(Fav) : Assuming f to be periodic over the time period T 1 T Fav = ∫ f(t)dt ………………………………. Kharagpur 5 www. …(9. Let “f” be the instantaneous value of any voltage or current associated with a rectifier circuit.1) T 0 RMS (effective) value of f(FRMS) : For f .2 Terminologies Certain terms will be frequently used in this lesson and subsequent lessons while characterizing different types of rectifiers.(9. then the following terms.www.(9.3) Fav Ripple factor of f(fRF) : Ripple factor of f is defined as f RF = FRMS . 9.

15) DFf 2 Version 2 EE IIT..(9.5) ( ) Fundamental component of f(F1): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency 1/T. 1 2 2 ∴ FK = f AK + f BK …………………………(9.(9.10) T 0 2 T f BK = ∫ f(t) sin2πK t T dt …………………(9..com . ˆ Peak to peak ripple of f f pp : By definition ˆ f pp = f max .7) T T 0 2 T f B1 = ∫ f ( t ) sin 2π t dt …………………….6) ∴ F1 = 2 T 2 where f A1 = ∫ f ( t ) cos 2π t dt ……………………(9.11) T 0 ( ) Crest factor of f(Cf) : By definition ˆ f ……………………………………(9. 1 2 2 f A1 + f B1 ……………………….jntuworld.com Ripple factor can be used as a measure of the deviation of the output voltage and current of a rectifier from ideal dc. Kharagpur 6 www.DFf THDf = ……………………………(9. By definition ⎛ Fk ⎞ THD f = ∑ ⎜ ⎟ ……………………….jntuworld.8) T T 0 ( ) Kth harmonic component of f(FK): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency K/T..14) K=0 ⎝ F1 ⎠ α K ≠1 2 From which it can be shown that 1..13) FRMS Total Harmonic Distortion of f(THDf): The amount of distortion in the waveform of f is quantified by means of the index Total Harmonic Distortion (THD).f min Over period T……………… …(9....www.9) 2 2 T where f AK = ∫ f(t) cos2πK t T dt ……………….(9.(9.12) Cf = FRMS Distortion factor of f(DFf) : By definition F DFf = 1 ………………………………….(9.

com . then the Displacement Factor of a rectifier is defined as. Commutation failure: Refers to the situation where the out going device fails to turn off at the end of commutation and continues to conduct current. Kharagpur 7 www.19) so. Mathematically. pulse number of a rectifier is given by Time period of the input supply voltage . However. Pulse number of a rectifier is always an integral multiple of the number of input supply phases.. The device from which the current is transferred is called the “out going device” and the device to which the current is transferred is called the “incoming device”.(9.. IiRMS In terms of THDii DPF PF = …………………………….jntuworld.20) 2 1+ THDii Majority of the rectifiers use either diodes or thyristors (or combination of both) in their circuits.16) Where φi is the phase angle between the fundamental components of vi and ii. Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a single time period of the input ac supply voltage. Classification of rectifiers can also be done in terms of their pulse numbers. p= Time period of the minium order harmonic in the output voltage/current. They are defined next. It refers to the time interval from the instant a thyristor is forward biased to the instant when a gate pulse is actually applied to it. While designing these components standard manufacturer’s specifications will be referred to.jntuworld.(9. certain terms are used in relation to the rectifier as a system.18) ViRMS IiRMS If the rectifier is supplied from an ideal sinusoidal voltage source then Vi1 = ViRMS I PF = i1 cosφi = DFi1 × DPF ……………….(9.www. Firing angle of a rectifier (α): Used in connection with a controlled rectifier using thyristors.. Power factor of a rectifier (PF): As for any other equipment. the definition of the power factor of a rectifier is Actual power input to the Rectifier ….com Displacement Factor of a Rectifier (DPF): If vi and ii are the per phase input voltage and input current of a rectifier respectively.17) PF = Apparent power input to the Rectifier if the per phase input voltage and current of a rectifier are vi and ii respectively then V I cosφi PF = i1 i1 ………………………………(9. The incoming device turns on at the beginning of commutation while the out going device turns off at the end of commutation. This time interval is expressed in radians by multiplying it with Version 2 EE IIT. DPF = cosφi …………………………………(9. Commutation in a rectifier: Refers to the process of transfer of current from one device (diode or thyristor) to the other in a rectifier.

expressed in radians. (vii) π 9. thyristors. The minimum frequency of the harmonic content in the Fourier series expression of the output voltage of a rectifier is equal to its _________. It should be noted that different thyristors in a rectifier circuit may have different firing angles.jntuworld. in the steady state operation. distortion. The extinction time (γ/ω) should be larger than the turn off time of the thyristor to avoid commutation failure. (iii) greater. they are usually the same. For any waveform “Form factor” is always _______ than or equal to unity.1 Fill in the blank(s) with the appropriate word(s). inductive and capacitive loads will be discussed. The output voltage and current of this rectifier are strongly influenced by the type of the load. Kharagpur 8 www.com the input supply frequency in rad/sec. (vi) Answers: (i) ac. During the period of commutation. operation of this rectifier with resistive. However.www. It is expressed in radians by multiplying the time interval with the input supply frequency (ω) in rad/sec.com . dc. “Extinction angle” and “overlap angle” of a controlled rectifier is always equal to _________. This period. dc. (v) ac. “THD” is the specification used to describe the quality of ___________ waveforms where as “Ripple factor” serves the same purpose for _________ for waveforms. Exercise 9. Input “power factor” of a rectifier is given by the product of the _________ factor and the ________ factor. (ii) diodes. (iv) pulse number.jntuworld. It refers to the time interval from the instant when the current through an outgoing thyristor becomes zero (and a negative voltage applied across it) to the instant when a positive voltage is reapplied. Uncontrolled rectifiers employ _________ where as controlled rectifiers employ ________ in their circuits.3 Single phase uncontrolled half wave rectifier This is the simplest and probably the most widely used rectifier circuit albeit at relatively small power levels. It is easily verified that α + μ + γ = π radian. Extinction angle of a rectifier (γ): Also used in connection with a controlled rectifier. In this section. both the incoming and the outgoing devices conduct current simultaneously. is called the overlap angle “μ” of a rectifier. The sum of “firing angle”. electrical power flows from the _________ side to the ________ side. i) ii) iii) iv) v) vi) vii) In a rectifier. displacement. Version 2 EE IIT. Overlap angle of a rectifier (μ): The commutation process in a practical rectifier is not instantaneous.

So in the interval π < ωt ≤ 2π ii = i0 = 0 v0 = i0R = 0………………………………. If the diode is assumed to be ideal then For 0 < ωt ≤ π v0 = vi = √2 Vi sin ωt ………………………(9. the diode D becomes forward biased in the the interval 0 < ωt ≤ π.24) 2π Vi 1 π 2 2 VDRMS = ∫0 2Vi sin ωtdωt = 2 ……………………. Kharagpur 9 www.22) R ii = i0 For ωt > π.(9..jntuworld..21) vD = vi – v0 = 0 Since the load is resistive 2V0 i0 = v0 R = sinωt ………………….com Fig 9. vi becomes negative and D becomes reverse biased..2 shows the circuit diagram and the waveforms of a single phase uncontrolled half wave rectifier.(9.com .www..25) 2π Version 2 EE IIT.jntuworld..23) vD = vi – v0 = vi = √2 Vi sinωt From these relationships 1 2π 1 π 2V V0AV = ∫0 v0dωt = 2π ∫0 2Visinωtdωt = π i ………. If the switch S is closed at at t = 0.(9.(9.

4 ………………………… (9. due to the load inductance i0 increases more slowly.27) for β ≤ ωt ≤ 2π Version 2 EE IIT. Both v0 and i0 remains zero till the beginning of the next cycle where upon the same process repeats. at ωt = 0. The ripple factor of output current can be reduced to same extent by connecting an inductor in series with the load resistance as shown in Fig 9. However. Because of such high ripple content in the output voltage and current this rectifier is seldom used with a pure resistive load.2 (b) that they contain significant amount of harmonics in addition to the dc component. Therefore.VDAV 1 2 v0RF = = π .com It is evident from the waveforms of v0 and i0 in Fig 9.26) VDAV 2 With a resistive load ripple factor of i0 will also be same.www.com . 2 2 From the preceding discussion For 0 ≤ ωt ≤ β vD = 0 v0 = vi i0 = ii…………………………………………(9. However. Beyond this point. Eventually at ωt = π.3 (a). Ripple factor of v0 is given by VDRM . v0 becomes zero again. As in the previous case. Kharagpur 10 www. the diode D is forward biased when the switch S is turned on. i0 is still positive at this point.jntuworld. D continues to conduct beyond ωt = π while the negative supply voltage is supported by the inductor till its current becomes zero at ωt = β.jntuworld. D becomes reverse biased.

φ) ……………………………………(9.com - β tanφ .(9.28) 2π 2Vi 1.34) Z ωL R 2 2 where tanφ = and Z = 2 R + ω L …………………………………………….φ ) ⎥ = 0 ⎢sinφe ⎣ ⎦ Z = sin ( φ .(9..32) All these quantities are functions of β which can be found as follows.33) ωt ⎤ 2Vi ⎡ tanφ i0 = + sin ( ωt ..30) 2π Form factor of the voltage waveform is V 2β .β ) …………………………………………..φ ) ⎥ ………………………………(9.www. Kharagpur 11 www.cosβ) 2 .35) Putting the initial conditions of (9.(9. v0RF = vOFF -1 = 2 π(2β .37.29) π 2 1 β 2 2 V0RMS = 2V sin ωtdωt 2π ∫0 i ( ) Vi 1 V β .33) i dt i0 (ωt = 0) = i0 (ωt = β) = 0 The solution is given by ωt tanφ i 0 = I0 e - + 2Vi sin(ωt .sin2β) 2(1.sin2β …………………….(9. Version 2 EE IIT..(9.com v0 = 0 i 0 = ii = 0 vD = vi – v0 = vi 1 2π 1 β V0AV = i ∫0 v0dωt = 2π ∫0 2Vsinωtdωt ………………… (9.jntuworld.cosβ) The ripple factor.jntuworld. For 0 ≤ ωt ≤ β dio vi = 2Vsinωt = L + Ri0 …………………………………….sin2β vOFF = 0RMS = π ………………………………….sin2β = i = 2π 2 2 2 ( ) 2β . (9.cosβ or V0AV = ……………………………………….37) or sinφe β as a function of φ can be obtained by solving equation 9.31) 2 V0AV 2π(1.1 ………………………………(9.36) ⎢sinφe ⎦ Z ⎣ β ⎤ 2Vi ⎡ tanφ i 0 (ωt = β) = + sin ( β .

with increasing φ (and hence increasing L) the form factor and the ripple factor of v0 worsens. Corresponding waveforms are shown in Fig 9.29).g.5 (b). Therefore. V0AV decreases with increasing β while V0RMS increases with β. the field supply of a dc motor) this configuration of the rectifier is preferred. Therefore.com . At this point the diode becomes Version 2 EE IIT. The output voltage follows the input voltage.jntuworld. Kharagpur 12 www. At ωt = β the sum of these two currents becomes zero and tends to grow in the negative direction. in certain applications. The problem of poor form factor (ripple factor) of the output voltage can be solved to some extent by connecting a capacitor across the load resistance of Fig 9.com It can be shown that β increases with φ. This single phase half wave rectifier supplying a capacitive load is shown in Fig 9. the ripple factor of i0 decreases with increasing L. The diode D carries both the capacitor charging current and the load current. However.5 (a).www. From Equation (9.jntuworld.2 (a). If the capacitor was initially discharged the diode “D” is forward biased when the switch S is turned on at ωt = 0. where a smooth dc current is of prime importance (e.

The same process repeats thereafter.com . The capacitor then discharges with the load current.39) = 1+ ω R C R 1 -1 where θ = tan ωRC Version 2 EE IIT. Diode D does not become forward biased till the input supply voltage becomes equal to the capacitor voltage in the next cycle at ωt = (2π + φ).jntuworld.com reverse biased and disconnects the load (along with the capacitor) from the supply.jntuworld..www.38) dv v ii = i c + i0 = c 0 + 0 dt R or ii = 2Vi [ ωRCcosωt + sinωt ] R 1 2Vi ( 2 2 2 2 ) cos(ωt . From the preceding discussion For 2π + φ ≤ ωt ≤ 2π + β v0 = vi = 2V1sinωt …………………………………….θ) ……………………..(9. Kharagpur 13 www.(9.

With an inductive load.43) ˆ As c → α. Exercise 9.(9. peak. The % THD of the input current of the rectifiers supplying capacitive loads is __________. large. C 0 + 0 = 0.(9.jntuworld.(9.2 1. (iii) unity. ii = 0 so β – θ = π/2 or β = θ + π/2 π 1 -1 or β = + tan ……………………………………….(9.sinϕ) ………………………………………….42) ⎦e From which φ can be solved. (ii) current. Answers: (i) greater. v0 = 2Vsinφ i 2Vi sinϕ = 2Vi cosθ e π -(2π+φ. Version 2 EE IIT. v D max = 2Vi + v 0M ≈ 2 2Vi ………………………………(9.39) the peak current through the diode increases proportionately. (v) high. Kharagpur 14 www. dt R -(ωt-β) tanθ ∴ v 0 = 2Vi cosθ e ………………………………….jntuworld. voltage. a very large capacitor helps to improve the ripple factor of the output voltage of this rectifier. In both single phase half wave and full wave rectifiers the form factor of the output voltage approaches _________ with capacitive loads provided the capacitance is ________ enough.com At ωt = β+ 2π. The PIV rating of the rectifier diode used in a single phase half wave rectifier supplying a capacitive load is approximately ________ the __________ input supply voltage. v 0 ( ωt = β ) = 2Vi cosθ .com . Peak to peak ripple in v0 is ˆ v 0pp = 2Vi (1.40) 2 ωRC Again for β ≤ ωt ≤ 2π + φ dv v ii = 0. However.-θ) tanθ 2 or sinφ = cosθ e -( 3π +φ-θ) tanθ 2 3π -( -θ) tanθ ⎤ -φ tanθ ⎡ or sinφ = ⎣ cosθ e 2 ……………………………. It is also interesting to observe that unlike the previous cases the peak reverse voltage appearing across D is given by... (iv) double. the ripple factor of the output __________ of the half wave rectifier improves but that of the output __________ becomes poorer. Fill in the blank(s) with the appropriate word(s).44) This is sometimes referred to as the peak inverse voltage rating (PIV) of the diode.41) at ωt = 2π + φ.www. θ → 0 and β and φ → π/2 and v0pp → 0 Therefore. as indicated by Equation (9.. i) ii) iii) iv) v) The ripple factor of the output voltage and current waveforms of a single phase uncontrolled half wave rectifier is ____________ than unity.

the output capacitance and the diode RMS current and PIV ratings.2V o ∴ Vi = 9. R = 50Ω.33V ∴ sin ϕ = 0. In addition. if no split supply is available the bridge configuration of the full wave rectifier is used. Some of these problems can be addressed using a full wave rectifier. These are called split secondary rectifiers and are commonly used as the input stage of a linear dc voltage regulator. Then from equation 9. Both these configurations are analyzed next.www.jntuworld. power supply of average value 12 V and peak to peak ripple of 20% is to be designed using a single phase half wave rectifier. ∴ Vomax = 2Vi = 12 + 2.9 = 0.8564 Amps.θ) tanθ or 0. Kharagpur 15 www.sinϕ ) = 0.4V . Diode current = V 1 β 2 1 92.4 2 = 13.035 1 ∴ tan θ = = 0.com 2.4 V. the input current contains a dc component which may cause problem (e. RMS.96 rad.g.43.818 or ϕ = 54.4 sin2(ϕ .818 e = cosθ From which θ ≈ 2.4 Single phase uncontrolled full wave rectifier Single phase uncontrolled half wave rectifiers suffer from poor output voltage and/or input current ripple factor. Version 2 EE IIT.035 2 2 2 2 ∫ϕ ii dωt = Ri 2 (1+ ω R C ) 2π ∫54. ˆ vopp = 2Vi (1. ⎦ 2π ⎣ -(3 π 2 + ϕ . This is the more commonly used full wave uncontrolled rectifier configuration.9o cos (ωt .818 = cosθ e (5.θ) tanθ 9.67 .θ) ⎥ = 0.com . Transformer saturation etc) in the power supply system.jntuworld. ∴ C = 1790 μF ωRC PIV of the diode = 2 2Vi = 26.42 0. Answer: From equation 9.2×12 = 2. There are two types of full wave uncontrolled rectifiers commonly in use.432 ⎢ 2 + 4 sin2(β . An unregulated dc. If a split power supply is available (e.03553. Find out the required input voltage. output from a split secondary transformer) only two diode will be required to produce a full wave rectifier. The output dc voltage is also relatively less. However.θ)dωt 2π 1 ⎡β -ϕ 1 1 ⎤ = 7. They use more number of diodes but provide higher average and rms output voltage.θ) . The equivalent load resistance is 50 ohms.g.

jntuworld. Kharagpur 16 www.com 9.www.jntuworld.com .4.1 Split supply single phase uncontrolled full wave rectifier. Version 2 EE IIT.

46) Since v0 is periodic over an interval π 1 π 2Vi π 2 2V V0AV = ∫ v 0 dωt = ∫0 sinωtdωt = π i ……………..(9. once started....50) 2 2 Both the form factor and the ripple factor shows considerable improvement over their half wave counter parts.. Beyond the negative going zero crossing of vi..e. When the switch is closed at the positive going zero crossing of v1 the diode D1 is forward biased and the load is connected to v1.jntuworld. When v1 reaches its negative going zero crossing both i0 and ii1 are positive which keeps D1 in conduction. From the above discussion For 0 ≤ ωt < π v0 = v1 i0 = ii1…………………………………….... This mode is called the “ discontinuous conduction mode” of operation.(9. The split power supply can be thought of to have been obtained from the secondary of a center tapped ideal transformer (i..47) 0 π π π 1 2 2 V0RMS = 2V sin ωt dωt = Vi ……………………….(9.www.49) ∴ v 0FF = 0RMS = V0AV 2 2 π -8 v 0RF = v -1 = ……………………………………. D2 becomes forward biased and the current i0 commutates to D2 from D1.6 shows the circuit diagram and waveforms of a single phase split supply. The current i0 however continues to increase through D2 till it reaches the steady state level after several cycles.com . This mode of operation of the rectifier is called the “Continuous conduction mode” of operation. The load voltage v0 becomes equal to v2 and D1 starts blocking the voltage vAB = v1 .com Fig 9.45) for π ≤ ωt < 2π v0 = v2 i0 = ii2…………………………………….v1 .. the voltage across D2 is vCB = v2 . always remains positive.v2 . Kharagpur 17 www. Therefore.(9... The currents i0 and ii1 start rising through D1. It should be noted that the current i0. uncontrolled full wave rectifier supplying an R – L load...3 (b) for the half wave rectifier where i0 remains zero for some duration of the input supply waveform.(9. This should be compared with the i0 waveform of Fig 9.6 (b) from ωt = 0 onwards.48) π ∫0 i V π ………………………………………..jntuworld. no internal impedance). Steady state waveforms of the variables are shown in Fig 9..(9. 2 0FF 2 Version 2 EE IIT...

Kharagpur 18 www.jntuworld.jntuworld.www.com .com Version 2 EE IIT.

The same process repeats thereafter. Peak to peak ripple in v0 is ˆ v 0pp = 2Vi (1. Version 2 EE IIT. From the discussion above For π + φ ≤ ωt ≤ π + β v0 = v2 = .sinφ) …………………………………………………. The capacitor then discharges through the load until at ωt = π + φ. D2 conducts up to ωt = π + β. If the capacitor was initially discharged. At this point the diode D1 becomes reverse biased and disconnects the load along with the capacitor from the supply.(9. v0 = 2sinφ 2Vsinφ = 2Vi cosθ e i or sinφ = cosθ e - ( π +θ-π-φ)tanθ 2 ( π +φ-θ )tanθ 2 π -( -θ ) tanθ ⎤ -φtanθ ⎡ or sinφ = ⎣cosθ e 2 ………………………………………(9.2Vsinωt i dv v ii2 = i c + i 0 = C 0 + 0 ………………………………………………(9.jntuworld. Kharagpur 19 www. considerable ripple current will flow into the load.(9. The output voltage follows the input voltage.52) = 1+ ω R C ωRC R π π π 1 -1 at ωt = π + β.θ = or β = θ + or β = + tan …………(9. The diode D2 remains reverse biased. At ωt = β the sum of these two currents becomes zero and tends to grow in the negative direction.57) is smaller than that given by Equation (9. This problem can be solved by connecting a capacitor across the load resistance just as in the case of a half wave rectifier.(9. D1 carries both the capacitor charging current and the load current.57) ˆ It can be shown that for the same R and C. ii1 = 0 so β .ωt ) where θ = tan -1 1 ….43) for the half wave rectifier.55) at ωt = π + φ.51) dt R 2Vi [ ωRCcosωt + sinωt ] or ii2 = R 1 2Vi ( 2 2 2 2 ) cos ( π + θ .53) 2 2 2 ωRC Again for β ≤ ωt ≤ π + φ dv v ii1 = 0 ∴ C 0 + 0 = 0 v0 ( ωt = β ) = 2Vsinβ = 2Vi cosθ ………. D1 now remains reverse biased.com The single phase full wave rectifier still does not offer a smooth dc voltage.jntuworld.com .(9. v2 becomes greater than v0 and forward biases D2.www.54) i dt R ∴ v 0 = 2Vi cosθ e -( ωt-β ) tanθ ……………………………………………. v0pp given by Equation (9.56) ⎦e From which φ can be solved. the diode D1 is forward biased when the switch S is turned on at ωt = 0. With resistive load. The diode PIV ratings remain equal to 2 2Vi however.

946316 e Or sin θ = 0.33° Vi = 9. R = 50 Ω.www.jntuworld. An unregulated dc power supply is built around a single phase split supply full wave rectifier using the same input voltage and output capacitor found in the problem 2 of Exercise 9.3 1. ˆ ∴ vopp = 2Vi (1. V0AV = V0Max - -0.6V = 13. Find out the average output voltage.com Exercise 9. 2. ⎦ 2π ⎣ Version 2 EE IIT.2 .jntuworld. Fill in the blank(s) with the appropriate word(s).6V .33 volts.sinϕ ) = 1. Answers: (i) π 2 2 .θ)dωt 2π 1 ⎡β -ϕ 1 ⎤ = 7.56 Sin θ = cos θ e-(π/2 + φ – θ) tan θ = 0.5% V 1 π 2+θ 2 1 β 2 2 2 2 RMS diode current = ∫ϕ ii dωt = Ri 2 (1+ ω R C ) 2π ∫ϕ cos (ωt .6V = 12. the peak to peak ripple in the output voltage and the RMS current ratings of the diodes. The output voltage of a single phase full wave rectifier supplying an inductive load is ___________ of the load parameters. i) ii) iii) The output voltage form factor of a single phase full wave rectifier is ___________.5353+ϕ ) -0.99937 e From which φ = 65.432 ⎢ 2 . Kharagpur 20 www. Answer: From the given data C = 1790 μF.2. The load resistance is 50 Ω. (ii) independent . (iii) smaller.4 sin2(ϕ .03553(1.0.θ) ⎥ = 0.0.com . The peak to peak output voltage ripple of a single phase split supply full wave rectifier supplying a capacitive load is ___________ compared to an equivalent half wave rectifier.533 Amps.035° From equation 9. ∴ θ = 2.20 volts. 2 ∴ % ripple = 9.03553ϕ ˆ v opp = 2Vi .

com 9.2 Single phase uncontrolled full bridge rectifier Version 2 EE IIT.jntuworld.4.www.com .jntuworld. Kharagpur 21 www.

jntuworld. These are • • They require a split power supply which is not always available.jntuworld. Version 2 EE IIT.www.com . Hence they are underutilized. They have a few disadvantages however. Each half of the split power supply carries current for only one half cycle.com The split supply full wave single phase rectifier offers as good performance as possible from a single phase rectifier in terms of the output voltage form factor and ripple factor. Kharagpur 22 www.

8 (a). It shows pictorially the conduction interval of different devices.4 (b) shows the waveforms for the third situation.58) (9.2Vi sin ωt ii = . The steady state waveforms of the rectifier under continuous conduction mode is shown to the right of the point ωt = 0 in Fig 9. Beyond this point.jntuworld. It should be noted that in this mode of conduction io always remain greater than zero.io ∴ VoAV = (9. However.59) VoRMS 1 π 2 2 2 ∫o 2Vi sin ωt d ωt = π Vi π 1 π = 2V 2 sin 2 ωt d ωt = Vi π ∫o i (9. D1 & D2 are forward biased by vi and current starts increasing through them till the point B. These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9. Kharagpur 23 www. • • • io may become zero before the negative going zero crossing of vi at point C.www. Fig 9. This is one of the most popular rectifier configuration and are used widely for applications requiring dc. io may still be non zero at point D. The current io continues to decrease up to the point D beyond which it again increases. L & E one of the following situations may arise. Now depending on the values of R. It should be noted that if io >0 either D1D2 or D3D4 must conduct.jntuworld. Current io commutates to D3 and D4 as shown in the associated “conduction Diagram” in Fig 9. In the other two situations the mode of operation will be discontinuous. After point B. io may continue to flow beyond C and become zero before the point D.com . When the switch S is turned on at the positive going zero crossing of vi no current flows in the circuit till vi crosses E at point A. These rectifiers are also very widely used with capacitive loads particularly as the front end of a variable frequency voltage source inverter. From this figure and preceding discussion For 0 < ωt ≤ π vo = vi = 2Vi sin ωt ii = io for π < ωt ≤ 2π v o = . motor or a storage battery.61) Version 2 EE IIT.8 (a) shows the rectifier supplying an R-L-E type load which may represent a dc.4 (b). Fig 9. power output from a few hundred watts to several kilo watts. If io >0 at point C the negative going input voltage reverse biases D1 & D2. Consequently. in this section analysis of this rectifier supplying an R-L-E load will be presented. vi falls below E and io starts decreasing.vi = .8 (b).com • The ratio of the required diode PIV to the average out put voltage is rather high. Its operation with a capacitive load is very similar to that of a split supply rectifier and is left as an exercise. this is called the continuous conduction mode of operation of the rectifier.60) (9.

jntuworld.www. Considerable.8 2 2 1 .8 2 2 (9.65) 2 2 π π2 . Kharagpur 24 www.com ∴ v OFF = VoRMS π = VoAV 2 2 v oRF = v OFF -1 = 2 π2 . From Fig 9. simplification is achieved (without significant loss of accuracy) by replacing the actual io waveform by its average value IoAV = VoAV / R.63) (9. Fig 9.66) Version 2 EE IIT.9 shows the approximate input current wave form and its fundamental component.com .9 Displacement angle φi = 0 ∴ Input displacement factor (DPF) = cos ϕi = 1 I 2 2 Distortion factor (DFil) = il = IoAV π Power Factor (PF) = DPF × DFil = % TH Dii = 100 × (9.jntuworld.64) (9.62) Finding out the characterizing quantities for ii will be difficult owing to its complicated waveform.DFii 2 = 100 × DFii 2 (9.

for continuous conduction io ≥ 0 for all 0 < ω t ≤ π hence io Min ≥ 0 or io ωt=θ ≥ 0 ∴ Condition for continuous conduction is 2 sinϕ .e (9.www. Kharagpur 25 www. Version 2 EE IIT.ϕ ) . for 0 < ωt ≤ π vi = 2Vi sin ωt = Ri o + io ωt=0 = io ωt=π Ldi o +E (9.71 is less than the right hand side conduction of the rectifier becomes discontinuous i.π 2Vi ⎡ sinθ ⎤ Io sin ϕ + = Io e tanϕ + Z ⎢ cosϕ ⎥ ⎣ ⎦ 2Vi 2 sinϕ Io = -π Z 1 .67) dt (steady state periodic boundary cond.e.69) (9.θ tanϕ sin θ e = sin (ϕ . L &E) are such that the left hand side of equation 9. Z = R 2 + ω2 L2 .ωt 2Vi ⎡ sinθ ⎤ i o = Io e tanϕ + ⎢sin ( ωt .com .com The exact analytical expression for io (and hence ii) can be obtained as follows.jntuworld.cosϕ ⎥ Z ⎣ ⎦ ωL E where tanϕ = .θ ) + -π tanϕ cos ϕ 1. the load current becomes zero for a part of the input cycle.jntuworld.e. R. Discontinuous conduction mode of operation of this rectifier is discussed next.) The general solution can be written as .e Z cosϕ ⎥ ⎣ ⎦ From which the condition for continuous conduction can be obtained.ϕ ) .70) ∴ io = .e tanϕ (9.68) 2Vi ⎡ sinθ ⎤ sin ϕ Z ⎢ cosϕ ⎥ ⎣ ⎦ (9.71) If the parameters of the load (i. sin θ = R 2Vi From the boundary condition .π tanϕ ⎢1 .ωt 2 Vi ⎡ 2 sinϕ sinθ ⎤ e tanϕ + sin ( ωt .

www.com . Kharagpur 26 www.jntuworld.com Version 2 EE IIT.jntuworld.

the load is connected to the input source through D1 D2 and io starts building up. Form the preceding discussion Version 2 EE IIT. 9. After ωt = θ.jntuworld.www. D1 D2 are reverse biased at this point. Beyond ωt = π . no current flows into the load till this time.com .10(b) shows the waveforms of different variables under discontinuous conduction mode of operation. D3 D4 are forward biased at ωt = π + θ when io starts increasing again. Consequently.jntuworld.com Fig. Thus none of the diodes conduct during the interval β < ω + ≤ π + θ and io remains zero during this period.θ. In this mode of operation D1 D2 are not forward biased till vi exceed E at ωt = θ. Kharagpur 27 www. io starts decreasing and becomes zero at ωt = β < π.

θ e.78) (9.79.2Vi sin ωt ii = . Fill in the blank(s) with the appropriate word(s). Version 2 EE IIT. sinθ = E ωt=θ (9. i) The average output voltage of a full wave bridge rectifier and a split supply full wave rectifier are __________ provided the input voltages are ___________.θ ) + sinθ ⎤ ⎢ cosϕ ⎥ ⎣ ⎦ ωt-θ ⎡sin ϕ . Kharagpur 28 www.77) 2Vi where tanϕ = ωL .θ ) e ⎥ cosϕ ⎢ ⎣ ⎦ Form which β can be solved.jntuworld.sinθ 1.e tanϕ ⎤ .79) ∴ io = Putting i o ⎡sin (ϕ .com .sin (ϕ .73) other wise π+θ 1 ⎡ β ∫θ 2Vi sin ωt + ∫β E d ωt ⎤ ⎦ π ⎣ (9. Z = R From the initial condition io Io = 2Vi Z 2Vi Z ωt = β = 0 (9. sin ( β .vi = .β ) sin θ ] π (9.ϕ ⎤ tanϕ ( ) ( )⎥ ⎢ cosϕ ⎣ ⎦ = 0 in Equation 9.72) for π < π + θ < ω + ≤ π + β < 2π v o = .φ ) .74) VoAV = 1 π ∫ π+θ θ vo d ωt = OR VoAV = 2Vi [ cos θ . ( ) θ-β sinθ ⎡ 1 .tanθ ϕ (9.4 1.www.cos β + ( π + θ .75) β can be found in the following manner for θ < ωt ≤ β Ldi o v = 2 sin ωt = R i o + +E dt i o ωt =θ = io ωt=β = 0 The general solution is i o = Io e ωt.76) + 2Vi ⎡ sin θ ⎤ ⎢sin ( ωt .e -ωt-θ + sin ωt .80) Exercise 9.com for θ < ωt ≤ β < π vo = vi = 2Vi sin ωt ii = i o (9.cos ϕ ⎥ Z ⎣ ⎦ R 2 + ω2 L2 .tanϕ .io vo = E ii = i o = 0 (9.jntuworld.ϕ ) = θ-β tanϕ (9.

Then assuming continuous conduction 2 2Vi 2 2 .415 volts.1I = 10.2 mH. the load impedance of a bridge rectifier should be __________.com ii) iii) iv) For the same input voltage the bridge rectifier uses ___________ the number of diodes used in a split supply rectifier with _________ the PIV rating.7 π π i ∴ 0. “Power Electronics”.5° ∴ tan ϕ = ωL = 16.0.635 ohms R ∴ L = 5. “Power Electronics.535° 2Vi From which φ = 86. Devices and applications” Prentice – Hall of India Private Limited. A battery is to be charged using a full bridge single phase uncontrolled rectifier. Kharagpur 29 www. θ = 38. (iv) continuous. Sen. References [1] [2] P.www.1Ω. In the ___________ conduction mode the output voltage of a bridge rectifier is __________ of load parameters.jntuworld. Find out the input voltage to the rectifier so that the battery charging current under full charge condition is 10% of the charging current under fully discharged condition. (iii) inductive. On full discharge the battery voltage is 10.jntuworld. Answer: Let the rectifier input voltage be Vi and the charging current under fully discharged condition be I. Second Edition.5 V ∴ I = 27. Rashid. Tata McGraw –Hill Publishing Company Limited. circuits. equal.35 or ωL = 1. and on full charge it is 12. 2.com . For continuous conduction.623. Assume continuous conduction under all charging condition and find out the inductance to be connected in series with the battery for this condition. 1995 Muhammad H. independent. The battery internal resistance is 0. If conduction is continuous at full charge condition it will be continuous for all other charging conditions.2 and V .7 volts.C. (ii) double.0. half.2 V.01I = 12. 1994 Version 2 EE IIT.78 Amps and Vi = 14. Answers: (i) equal.09I = 2. For continuous conduction 2sinϕ -θ tanϕ sinθ e = sin(ϕ .θ) + -π tanϕ cosϕ 1.e E From given data sinθ = = 0.

Single phase uncontrolled full wave rectifier have higher average output voltage and improved ripple factor compared to a half wave rectifier with resistive and inductive load. Performance of a rectifier is judged by the relative magnitudes of these harmonies with respect to the desired output. For a given input voltage and load.com Module Summary • • • • • A rectifier is a power electronic converter which converts ac voltage or current sources to dc voltage and current.jntuworld. the output voltage (current) of an uncontrolled rectifier can not be varied.jntuworld. number of phases and the control mechanism. where upon. Kharagpur 30 www. With a capacitive load the output voltage form factor approaches unity with increasing capacitance value for both the half wave and the full wave rectifiers. • • • • • • Version 2 EE IIT.www. the rectifier is said to be operating in the “inverter mode”. However it also uses more number of diodes. Rectifiers can be classified based on the type of device they use. the output voltage may vary considerably with load. the converter circuit topology. Single phase uncontrolled half wave rectifier with resistive or inductive load have low average output voltage. high from factor and poor ripple factor of the output voltage waveform. In many rectifier circuits. electrical power flows from the ac input to the dc output. power can also flow from the dc side to the ac side. However. In a rectifier. With highly inductive load the output voltage waveform of a full wave rectifier may be independent of the load parameters. However. THD of the input current also increases.com . A full wave bridge rectifier generates higher average dc voltage compared to a split supply full wave rectifier. All rectifiers produce unwanted harmonies both at the out put and the input.

www.com Practice Problems and Answers Version 2 EE IIT.jntuworld.com .jntuworld. Kharagpur 31 www.

Q3. The split supply of a single phase full wave rectifier is obtained from a single phase transformer with a single primary and a center tapped secondary. displacement factor.com .com Q1. The rectifier supplies a purely resistive load. 1500 rpm separately excited dc motor has an armature resistance of 1 Ω and inductance of 50 mH.jntuworld. A single phase split supply full wave rectifier is designed to supply an inductive load.www.jntuworld. 15 Amps. find out the no load speed of the machine. The average load current is 20 A. A 200V. Kharagpur 32 www. The motor is supplied from a single phase full wave bridge rectifier with input voltage of 230 V. Neglecting all no load losses. and the ripple current is negligible. Version 2 EE IIT. distortion factor and the power factor at the primary side of the transformer. Can the same rectifier be used with a capacitive load drawing the same 20 Amps average current? Justify your answer. Also find out the torque and speed at the boundary between continuous and discontinuous conduction. Q4. 50 HZ. Assuming the transformer to be ideal find out the. What will be the load voltage and current waveform when a single phase half wave uncontrolled rectifier supplies a purely inductive load? Explain your answer with waveforms. Q2.

cosωt) ∴ i0 = ωL 2 2Vi i0 = >0 at ωt = π.cosβ) for π ≤ β ≤ 2π the only solution is β = 2π ωt = β ωL ` Version 2 EE IIT. the volt-sec.com Answer 1 Without loss of generality it can be assumed that S is turned ON at ωt = 0. ωL ∴ D conducts beyond ωt = π until i0 is zero again.com .jntuworld. In the region 0 ≤ ωt < π D is forward biased and v0 = vi di ∴ L 0 = 2Vsinωt i 0 (0) = 0 i dt di i0 or ωL 0 = 2Vsinωt =0 i ωt = 0 dωt 2Vi 2Vi cosωt I0 = ∴ i 0 = I0 ωL ωL 2Vi (1.www. Let the extinction angle be ωt = β > π. Since. if it is turned ON anytime after ωt = 0.cosωt) ωL 2Vi i0 = (1. Then for 0 ≤ ωt ≤ β 2Vi i0 = (1. across the inductor will dictate that the current through it becomes zero before the next positive going zero crossing of vi . Kharagpur 33 www.jntuworld.

com .jntuworld. From the given data N vS1 = S 2VP sinωt NP N V iS1 = S 2 P sinωt NP R iS1 = 0 otherwise.S 2 P sinωt NP R iS2 = 0 otherwise for 0 ≤ ωt ≤ π for π ≤ ωt ≤ 2π From the MMF balance of an ideal transformer N Pi P .iS2 ) = sinωt 2 NP ⎛ NP ⎞ ⎜N ⎟ R ⎝ S⎠ ∴ At the input Displacement factor = Distortion factor = Power factor = 1. Kharagpur 34 www.www.jntuworld.0 Version 2 EE IIT.S 2VP sinωt NP N V iS2 = .NSiS1 + NSiS2 = 0 or iP = NS 2VP (iS1 .com ∴ v0 = vi for 0 ≤ ωt ≤ 2π and Answer 2 i0 = 2Vi (1. N vS2 = .cosωt) 0 ≤ ωt ≤ 2π ωL Figure shows the secondary voltage and current waveforms of the rectifier.

5 2Vi but E at 1500 RPM = 185 volts.With reference to Fig 9.θ) + sinθ ] e E -1 o from which θ = sin ∴ E = 202.6 (b) will be I D1RMS = I D2RMS = 20 Amps . zero average current will imply that the instantaneous value of the armature current at all time will be zero at no load. Therefore the same rectifier can not be used.com . Hence the motor speed and E will not increase any further. 185 0.e 2sinφ θ tanφ or = [ cosϕ sin(φ . However.1268 -3 where tanφ = ∴ 0.708 R 1 cosφ = 0.7 (b) and Problem 2 of Exercise 9. with reference to Fig 9.jntuworld. 2sinφ -θ tanφ sinθ e = sin(φ . Kharagpur 35 www. Thus at no load E = 2Vi = 325.507 rad.e ωL 100π ×50×10 = = 15.48 V = 38. The required RMS current rating of the rectifier diode.θ) + sinθ ] e -π tanφ 1.jntuworld.507 .www.06366 θ Version 2 EE IIT. ∴ Speed at the junction of continuous and discontinuous condition is 202. Answer 4 Since all no load losses are neglected the developed power at no load and hence the no load torque will be zero.6995 = [ 0. since a diode rectifier can not conduct instantaneous negative load current. and sin2φ = 0.θ) + -π tanφ cosφ 1.27 = 1500× = 2637 rpm . the average armature current will also be zero.27 volts .com Answer 3 If the load current is 20A with negligible ripple.0 = 185 volts.0635 sin(1. since once ia becomes zero when E = 2Vi there will be no developed torque to accelerate the motor. ∴ N = N rated × E rated 185 At the boundary between the continuous and discontinuous mode of conduction.10 this condition will require the rectifier diodes to remain reverse biased at all time. Therefore.0635 φ = 1. Hence at no load E ≥ 2Vi However E will not exceed 2Vi . E N Now = E rated N rated E 325. Under the rated condition at 1500 rpm Erated = 200 – 15 × 1.48 1500 × = 1642 RPM. 2 However from Fig 9.3 the required RMS current for a capacitive load will be much larger than 20 Amps.

∴ Torque = 15 Version 2 EE IIT.593 ×100 = 30.com . Kharagpur 36 www.jntuworld.www. ⎝ π ⎠ 4.593 Amps.jntuworld.com ⎛ 2 2Vi ⎞ Average armature current is ⎜ ⎟ R = 4.62% of rated torque.

www. Kharagpur 1 www.com .jntuworld.jntuworld.com Module 2 AC to DC Converters Version 2 EE IIT.

com Lesson 10 Single Phase Fully Controlled Rectifier Version 2 EE IIT.jntuworld. Kharagpur 2 www.jntuworld.com .www.

com Operation and Analysis of single phase fully controlled converter. voltage/currents. Explain the operating principle of a single phase fully controlled bridge converter.jntuworld. Analyze the converter operation in both continuous and discontinuous conduction mode and there by find out the average and RMS values of input/output.www.jntuworld. Identify the mode of operation of the converter (continuous or discontinuous) for a given load parameters and firing angle. Instructional Objectives On completion the student will be able to • • • • • • Differentiate between the constructional and operation features of uncontrolled and controlled converters Draw the waveforms and calculate their average and RMS values of different variables associated with a single phase fully controlled half wave converter.com . Kharagpur 3 www. Explain the operation of the converter in the inverter mode. Version 2 EE IIT.

jntuworld. Kharagpur 4 www. In most cases they are used to provide an intermediate unregulated dc voltage source which is further processed to obtain a regulated dc or ac output. These two disadvantages are the direct consequences of using power diodes in these converters which can block voltage only in one direction. Version 2 EE IIT. since the thyristor can block forward voltage. these two disadvantages are overcome if the diodes are replaced by thyristors.jntuworld. However. been proved to be efficient and robust power stages. they suffer from a few disadvantages.1 Introduction Single phase uncontrolled rectifiers are extensively used in a number of power electronic based converters. the output voltage / current magnitude can be controlled by controlling the turn on instants of the thyristors.com . The main among them is their inability to control the output dc voltage / current magnitude when the input ac voltage and load parameters remain fixed. such converters are rarely used in practice. Working principle of thyristors based single phase fully controlled converters will be explained first in the case of a single thyristor halfwave rectifier circuit supplying an R or R-L load. They are also unidirectional in the sense that they allow electrical power to flow from the ac side to the dc side only. Full bridge is the most popular configuration used with single phase fully controlled rectifiers.www. in general. the resulting converters are called fully controlled converters. Thyristors are semicontrolled devices which can be turned ON by applying a current pulse at its gate terminal at a desired instance. they cannot be turned off from the gate terminals. However. Analysis and performance of this rectifier supplying an R-L-E load (which may represent a dc motor) will be studied in detail in this lesson. However.com 10. Therefore. As will be shown in this module. However. the fully controlled converter continues to exhibit load dependent output voltage / current waveforms as in the case of their uncontrolled counterpart. They have.

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10.2 Single phase fully controlled halfwave rectifier 10.2.1 Resistive load

Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier supplying a purely resistive load. At ωt = 0 when the input supply voltage becomes positive the thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate pulse is applied at ωt = α. During the period 0 < ωt ≤ α, the thyristor blocks the supply voltage and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows during this interval. As soon as a gate pulse is applied to the thyristor at ωt = α it turns ON. The voltage across the thyristor collapses to almost zero and the full supply voltage appears across the load. From this point onwards the load voltage follows the supply voltage. The load being purely resistive the load current io is proportional to the load voltage. At ωt = π as the supply voltage passes through the negative going zero crossing the load voltage and hence the load current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load current remains clamped at zero till the thyristor is fired again at ωt = 2π + α. The same process repeats there after. From the discussion above and Fig 10.1 (b) one can write For α < ωt ≤ π v 0 = vi = 2 Vi sinωt (10.1)

i0 =

v0 V = 2 i sinωt R R

(10.2) Version 2 EE IIT, Kharagpur 5

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v0 = i0 = 0 otherwise. Therefore

1 2π 1 π v 0 dωt = ∫ 2 Vi sinωt dωt 2π ∫0 2π α V Or VOAV = i (1+ cosα) 2π 1 2π 2 VORMS = v0 dωt 2π ∫0 VOAV =

(10.3) (10.4)

(10.5)

=

1 π 2 2 2vi sin ωtdωt 2π ∫α

Vi2 = 2π
= Vi2 2π

π

α

(1- cos2ωt)dωt

sin2α ⎤ ⎡ ⎢π - α + 2 ⎥ ⎣ ⎦
1

V α sin2α ⎞ 2 = i ⎛ 1- + ⎜ ⎟ 2π ⎠ 2⎝ π

FFVO =

VORMS VOAV

α sin2α ⎞ 2 π ⎛ 1- + ⎜ ⎟ 2π ⎠ = ⎝ π (1+ cosα)

1

(10.6)

Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.

10.2.2 Resistive-Inductive load
Fig 10.2 (a) and (b) shows the circuit diagram and the waveforms of a single phase fully controlled halfwave rectifier supplying a resistive inductive load. Although this circuit is hardly used in practice its analysis does provide useful insight into the operation of fully controlled rectifiers which will help to appreciate the operation of single phase bridge converters to be discussed later.

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As in the case of a resistive load, the thyristor T becomes forward biased when the supply voltage becomes positive at ωt = 0. However, it does not start conduction until a gate pulse is applied at ωt = α. As the thyristor turns ON at ωt = α the input voltage appears across the load and the load current starts building up. However, unlike a resistive load, the load current does not become zero at ωt = π, instead it continues to flow through the thyristor and the negative supply voltage appears across the load forcing the load current to decrease. Finally, at ωt = β (β > π) the load current becomes zero and the thyristor undergoes reverse recovery. From this point onwards the thyristor starts blocking the supply voltage and the load voltage remains zero until the thyristor is turned ON again in the next cycle. It is to be noted that the value of β depends on the load parameters. Therefore, unlike the resistive load the average and RMS output voltage depends on the load parameters. Since the thyristors does not conduct over the entire input supply cycle this mode of operation is called the “discontinuous conduction mode”. From above discussion one can write. α ≤ ωt ≤ β For

v 0 = vi = 2 Vi sinωt v0 = 0 otherwise
Therefore VOAV = 1 2π v0 dωt 2π ∫0 1 β 2 Vi sinωt dωt = 2π ∫α

(10.7)

(10.8)

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=

Vi 2π

(cosα - cosβ)

VORMS = =

1 2π 2 v0 dωt 2π ∫0 1 β 2 2 2vi sin ωt dωt 2π ∫α
1

(10.9)

V β - α sin2α - sin2β ⎞ 2 = i ⎛ + ⎜ ⎟ 2π ⎠ 2⎝ π V Vi I OAV = OAV = (cosα - cosβ) R 2πR Since the average voltage drop across the inductor is zero.

(10.10)

However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0 will be required. The value of β in terms of the circuit parameters can also be found from the expression of i0.
α ≤ ωt ≤ β di Rio + L o = v0 = 2Vi sinωt dt The general solution of which is given by (ωt-α) 2Vi i 0 = I0 e tanϕ + sin(ωt - ϕ) Z ωL Where tanφ = and Z = R 2 + ω2 L2 R

For

(10.11)

(10.12)

i0

ωt =α

=0
∴ 0 = I0 +
2Vi sin(α - φ) Z

∴ i0 =

( ωt-α ) 2Vi ⎡ ⎤ ⎢sin(φ - α)e tanφ + sin(ωt - φ) ⎥ ⎣ ⎦ Z i0 = 0 otherwise.

(10.13)

Equation (10.13) can be used to find out IORMS. To find out β it is noted that i0 ωt=β = 0
∴ sin(φ - α)e
α-β tanφ

= sin(φ - β)

(10.14)

Equation (10.14) can be solved to find out β
Exercise 10.1

Fill in the blank(s) with appropriate word(s) Version 2 EE IIT, Kharagpur 8
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i) ii) iii) iv) v)

In a single phase fully controlled converter the _________ of an uncontrolled converters are replaced by ____________. In a fully controlled converter the load voltage is controlled by controlling the _________ of the converter. A single phase half wave controlled converter always operates in the ________ conduction mode. The voltage form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load. The load current form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load.

Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.

2) Explain qualitatively, what will happen if a free-wheeling diode(cathode of the diode shorted with the cathode of the thyristor) is connected across the load in Fig 10.2.(a)
Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till ωt = π since the positive load voltage across the load will reverse bias the diode. However, beyond this point as the load voltage tends to become negative the free wheeling diode comes into conduction. The load voltage is clamped to zero there after. As a result

i) ii) iii)

Average load voltage increases RMS load voltage reduces and hence the load voltage form factor reduces. Conduction angle of load current increases as does its average value. The load current ripple factor reduces.

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10.3 Single phase fully controlled bridge converter

Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is one of the most popular converter circuits and is widely used in the speed control of separately excited dc machines. Indeed, the R–L–E load shown in this figure may represent the electrical equivalent circuit of a separately excited dc motor. The single phase fully controlled bridge converter is obtained by replacing all the diode of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together while T3 and T4 are fired 180º after T1 and T2. From the circuit diagram of Fig 10.3(a) it is clear that for any load current to flow at least one thyristor from the top group (T1, T3) and one thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3 nor T2T4 can conduct simultaneously. For example whenever T3 and T4 are in the forward blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative voltage is applied across T1 and T2 commutating them immediately. Similar argument holds for T1 and T2. For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only possible conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is possible that at a given moment none of the thyristors conduct. This situation will typically occur when the load current becomes zero in between the firings of T1T2 and T3T4. Once the load current becomes zero all thyristors remain off. In this mode the load current remains zero. Consequently the converter is said to be operating in the discontinuous conduction mode. Fig 10.3(b) shows the voltage across different devices and the dc output voltage during each of these conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage across T3 and T4 becomes –vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over the negative half cycle of the input supply voltage. Similarly T1 and T2 can be fired only over the positive half cycle of the input supply. The voltage across the devices when none of the thyristors conduct depends on the off state impedance of each device. The values listed in Fig 10.3 (b) assume identical devices. Under normal operating condition of the converter the load current may or may not remain zero over some interval of the input voltage cycle. If i0 is always greater than zero then the converter is said to be operating in the continuous conduction mode. In this mode of operation of the converter T1T2 and T3T4 conducts for alternate half cycle of the input supply. Version 2 EE IIT, Kharagpur 10
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However, in the discontinuous conduction mode none of the thyristors conduct over some portion of the input cycle. The load current remains zero during that period.

10.3.1 Operation in the continuous conduction mode
As has been explained earlier in the continuous conduction mode of operation i0 never becomes zero, therefore, either T1T2 or T3T4 conducts. Fig 10.4 shows the waveforms of different variables in the steady state. The firing angle of the converter is α. The angle θ is given by sinθ = E 2V1 (10.15)

It is assumed that at t = 0- T3T4 was conducting. As T1T2 are fired at ωt = α they turn on commutating T3T4 immediately. T3T4 are again fired at ωt = π + α. Till this point T1T2 conducts. The period of conduction of different thyristors are pictorially depicted in the second waveform (also called the conduction diagram) of Fig 10.4.

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The dc link voltage waveform shown next follows from this conduction diagram and the conduction table shown in Fig 10.3(b). It is observed that the emf source E is greater than the dc link voltage till ωt = α. Therefore, the load current i0 continues to fall till this point. However, as T1T2 are fired at this point v0 becomes greater than E and i0 starts increasing through R-L and E. At ωt = π – θ v0 again equals E. Depending upon the load circuit parameters io reaches its maximum at around this point and starts falling afterwards. Continuous conduction mode will be possible only if i0 remains greater than zero till T3T4 are fired at ωt = π + α where upon the same process repeats. The resulting i0 waveform is shown below v0. The input ac current waveform ii is obtained from i0 by noting that whenever T1T2 conducts ii = i0 and ii = - i0 whenever T3T4 conducts. The last waveform shows the typical voltage waveform across the thyristor T1. It is to be noted that when the thyristor turns off at ωt = π + α a negative voltage is applied across it for a duration of π – α. The thyristor must turn off during this interval for successful operation of the converter. It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore, it can be expressed in a Fourier series as follows.
v 0 = VOAV + ∑ [ v an cos2nωt + v bn sin2nωt ]
n =1 α

(10.16) (10.17) (10.18) (10.19)

Where

1 π+α 2 2 ∫α v0 dωt = π Vi cosα π 2 π 2 2 ⎡ cos(2n +1)α cos(2n -1)α ⎤ v an = ∫ v 0 cos2nωt dωt = Vi ⎢ π 0 π ⎣ 2n +1 ⎦ 2n -1 ⎥ VOAV =

v bn =

2 π 2 2 ⎡ sin(2n +1)α sin(2n -1)α ⎤ ∫0 v0 sin2nωt dωt = π Vi ⎢ 2n +1 - 2n -1 ⎥ π ⎣ ⎦

Therefore the RMS value of the nth harmonic 1 2 VOnRMS = v an + v 2 bn 2 RMS value of v0 can of course be completed directly from. 1 π+α 2 VORMS = v0 dωt = Vi π ∫α

(10.20)

(10.21)

Fourier series expression of v0 is important because it provides a simple method of estimating individual and total RMS harmonic current injected into the load as follows: The impedance offered by the load at nth harmonic frequency is given by
Z n = R 2 + (2nωL) 2

(10.22)
1 2

VonRMS ⎡ α 2 ⎤ (10.23) ; IOHRMS = ⎢ ∑ IonRMS ⎥ Zn ⎣ n =1 ⎦ From (10.18) – (10.23) it can be argued that in an inductive circuit IonRMS → 0 as fast as 1/n2. So in practice it will be sufficient to consider only first few harmonics to obtain a reasonably accurate estimate of IOHRMS form equation 10.23. This method will be useful, for example, while calculating the required current derating of a dc motor to be used with such a converter. IonRMS =

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However to obtain the current rating of the device to be used it is necessary to find out a closed form expression of i0. This will also help to establish the condition under which the converter will operate in the continuous conduction mode. To begin with we observe that the voltage waveform and hence the current waveform is periodic over an interval π. Therefore, finding out an expression for i0 over any interval of length π will be sufficient. We choose the interval α ≤ ωt ≤ π + α. In this interval

di0 + Ri 0 + E = 2Vi sinωt dt The general solution of which is given by L
i 0 = Ie
( ) - ωt-α tanφ

(10.24)

sinθ ⎤ ⎡ (10.25) ⎢sin(ωt - φ) - cosφ ⎥ ⎣ ⎦ ωL Z = R 2 + ω2 L2 ; tanφ = ; E = 2Vi sinθ; R = Zcosφ Where, R Now at steady state i 0 ωt=α = i0 ωt =π+α since i0 is periodic over the chosen interval. Using this + 2Vi Z

boundary condition we obtain
i0 =
( ωt-α ) 2Vi ⎡ 2sin(φ - α) e- tanφ + sin(ωt - φ) - sinθ ⎤ ⎢ ⎥ π cosφ ⎥ Z ⎢ ⎣ 1- e tanφ ⎦

(10.26)

The input current ii is related to i0 as follows: ii = i 0 for α ≤ ωt ≤ π + α ii = - i0 otherwise. Fig 10.5 shows the waveform of ii in relation to the vi waveform.

(10.27)

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It will be of interest to find out a Fourier series expression of ii. However, using actual expression for ii will lead to exceedingly complex calculation. Significant simplification can be made by replacing i0 with its average value I0. This will be justified provided the load is highly inductive and the ripple on i0 is negligible compared to I0. Under this assumption the idealized waveform of ii becomes a square wave with transitions at ωt = α and ωt = α + π as shown in Fig 10.5. ii1 is the fundamental component of this idealized ii. Evidently the input current displacement factor defined as the cosine of the angle between input voltage (vi) and the fundamental component of input current (ii1) waveforms is cosα (lagging). It can be shown that
Ii1RMS = 2 2 I0 π

(10.28) Version 2 EE IIT, Kharagpur 15
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and

IiRMS = I0

(10.29) (10.30)

Ii1RMS 2 2 = IiRMS π VI cosα Actual Power = i i1RMS The input power factor = Apparent Power Vi IiRMS

Therefore the input current distortion factor =

=

2 2 cosα (lagging) π

(10.31)

Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the ‘α’ poorer is the power factor. The input current ii also contain significant amount of harmonic current (3rd, 5th, etc) and therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents can be obtained by Fourier series analysis of ii and is left as an exercise.
Exercise 10.2

Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v) A single phase fully controlled bridge converter can operate either in the _________ or ________ conduction mode. In the continuous conduction mode at least _________ thyristors conduct at all times. In the continuous conduction mode the output voltage waveform does not depend on the ________ parameters. The minimum frequency of the output voltage harmonic in a single phase fully controlled bridge converter is _________ the input supply frequency. The input displacement factor of a single phase fully controlled bridge converter in the continuous conduction mode is equal to the cosine of the ________ angle.

Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.

2. A single phase fully controlled bridge converter operates in the continuous conduction mode from a 230V, 50HZ single phase supply with a firing angle α = 30°. The load resistance and inductances are 10Ω and 50mH respectively. Find out the 6th harmonic load current as a percentage of the average load current.
Answer: The average dc output voltage is 2 2 VOAV = Vi cosα = 179.33 Volts π V Average output load current = OAV = 17.93 Amps RL From equation (10.18) Va3 = 10.25 Volts From equation (10.19) Vb3 = 35.5 Volts

∴ V03RMS = 26.126 Volts, Z3 = R 2 + (6× 2× π×50×50×10-3 ) 2 = 94.78 ohms L
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∴ I3RMS =

V03RMS = 0.2756 Amps = 1.54% of I OAV . Z3

10.3.2 Operation in the discontinuous conduction mode
So far we have assumed that the converter operates in continuous conduction mode without paying attention to the load condition required for it. In figure 10.4 the voltage across the R and L component of the load is negative in the region π - θ ≤ ωt ≤ π + α. Therefore i0 continues to decrease till a new pair of thyristor is fired at ωt = π + α. Now if the value of R, L and E are such that i0 becomes zero before ωt = π + α the conduction becomes discontinuous. Obviously then, at the boundary between continuous and discontinuous conduction the minimum value of i0 which occurs at ωt = α and ωt = π + α will be zero. Putting this condition in (10.26) we obtain the condition for continuous conduction as.
2sin(φ - α) 1- e
π tanφ

- sin(φ - α) -

sinθ ≥0 cosφ

(10.32)

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VORMS. During the period β ≤ ωt ≤ π + α none of the thyristors conduct. the output voltage v0 falls below the emf E and i0 decreases till ωt = β when it becomes zero.6 shows waveforms of different variables on the boundary between continuous and discontinuous conduction modes and in the discontinuous conduction mode.com . all the analysis of continuous conduction mode applies to this case as well. Therefore. After this.jntuworld. IOAV. These intervals are shown by hatched lines in the conduction diagram of Fig 10. However in the discontinuous conduction mode i0 remains zero for certain interval. It should be stressed that on the boundary between continuous and discontinuous conduction modes the load current is still continuous. In this conduction mode i0 starts rising from zero as T1T2 are fired at ωt = α.6(b). β and θ. For example Version 2 EE IIT. The load current continues to increase till ωt = π – θ. Since the thyristors cannot conduct current in the reverse direction i0 remains at zero till ωt = π + α when T3 and T4 are fired. Kharagpur 18 www.com Fig 10. During this interval none of the thyristors conduct.jntuworld. IORMS etc can be found in terms of α. Performance of the rectifier such as VOAV. During this period v0 attains the value E.www.

α and θ. Vd > 0. if an attempt is made to supply power to the ac side (by making α > π/2) the energy stored in the load inductor will be exhausted and the current will become discontinuous as shown in Fig 10. θ.39) 10. φ and Z) and α can be found as follows.φ) ⎥ ⎢ tanφ Z ⎣ cosφ 1.E VOAV . In fact.cosβ + sinθ(π + α .37) { } (10.ωt-α ⎤ 2Vi ⎡ ( ) sinθ . the value of β can be found by solving equation 10. ∴ sin(φ .3.e.e Given φ.β)] π Zcosφ (10. Hence P < 0. To supply power. The value of β in terms of the load parameters (i.ωt-α i0 = sin(φ .3 Inverter Mode of operation The expression for average dc voltage from a single phase fully controlled converter in continuous conduction mode was 2 2 (10. However the connection of this source in Fig 10. So it may be tempting to conclude that the same converter circuit may be operated as an inverter by just increasing α beyond π/2.36) It is observed that the performance of the converter is strongly affected by the value of β.38) Now i0 ωt=β =0 α-β tanφ α-β sinθ ⎡ ⎤ tanφ + sin(β . Since the thyristors conducts current only in one direction I0 > 0 always.40) Vi cosα π For α < π/2.jntuworld. V0 < 0. Kharagpur 19 www. This might have been true had it been possible to maintain continuous conduction for α < π/2 without making any modification to the converter or load connection.7 (a).e ⎦ (10. the load EMF source can be utilized.34) VOAV = [cosα .jntuworld. V0 = Version 2 EE IIT.α)e - (10.com VOAV = Or π+α 1 π+α 1 β v0 dωt = ⎡ ∫ 2Vi sinωt dωt + ∫ 2Vi sinθ dωt ⎤ (10.33) ⎥ β ⎣ ⎦ π ∫α π⎢ α 2Vi (10.com . In the interval α ≤ ωt ≤ β di L o + Rio + E = 2Vi sinωt dt i 0 ωt =α = 0 From which the solution of i0 can be written as ( ) .www.cosβ + sinθ(α .39. Therefore power flowing to the dc side P = V0I0 > 0 for α < π/2. However for α > π/2.2Vi sinθ (10.φ) = 0 ⎦ cosφ ⎣1.β)] π V .35) IOAV = OAV = R Zcosφ Or IOAV = 2Vi [cosα .α)e tanφ + sin(ωt . This may be interpreted as the load side giving power back to the ac side and the converter in this case operate as a line commutated current source inverter.3 is such that it can only absorb power but can not supply it.

8 (a) and (b) below shows the waveforms of the inverter operating in continuous conduction mode and discontinuous conduction mode respectively. Fig 10. Analysis of the converter remains unaltered from the rectifier mode of operation provided θ is defined as shown.com .com Therefore for sustained inverter mode of operation the connection of E must be reversed as shown in Fig 10.jntuworld. Kharagpur 20 www.7(b). Version 2 EE IIT.www.jntuworld.

Kharagpur 21 www. The load current ripple factor in the continuous conduction mode is _______ compared to the discontinuous conduction mode.3 Fill in the blank(s) with the appropriate word(s) i) ii) iii) In the discontinuous conduction mode the load current remains __________ for a part of the input cycle. For the same firing angle the load voltage in the discontinuous conduction mode is __________ compared to the continuous conduction mode of operation. Version 2 EE IIT.www.jntuworld.com Exercise 10.com .jntuworld.

A 220 V.18 Volts 183. (v) 90. (iii) lower.6(b) this situation can occur only when θ = π/2. Half wave controlled converters usually have poorer output voltage form factor compared to uncontrolled converter. Single phase fully controlled bridge converters are extensively used for small dc motor drives.27 ×1500 = 2380 RPM 205 At the boundary between continuous and discontinuous conduction modes from equation 10.www. 2. 1500 RPM separately excited dc motor has an armature resistance of 0. Under rated condition E b 1500 = 205 V 325.75Ω and inductance of 50mH. In a fully controlled converter the output voltage can be controlled by controlling the firing delay angle (α) of the thyristors.e-π/tanφ From the given data φ = 87. α = 25° ∴ sinθ = 0. 50Hz.α) 1. Answers: (i) zero. Kharagpur 22 www. 205 ∴ N no load = Summary • • • • • Single phase fully controlled converters are obtained by replacing the diodes of an uncontrolled converter with thyristors.27°.com iv) v) In the inverter mode of operation electrical power flows from the ________ side to the __________side. single phase supply through a fully controlled bridge converter. However. ac. since a converter carries only unidirectional current. (iv) dc.jntuworld. Find the no load speed of the motor and the speed of the motor at the boundary between continuous and discontinuous modes when α = 25°. inverter.com . Answer: At no load the average motor torque and hence the average motor armature current is zero. Therefore.e the back emf is equal to the peak of the supply voltage. Single phase fully controlled half wave converters always operate in the discontinuous conduction mode. zero average armature current implies that the armature current is zero at all time.18 ∴ Motor speed N = ×1500 = 1340 RPM . 20A. Version 2 EE IIT. (ii) higher. From Fig 10.jntuworld.32 1+ e -π/tanφ sinθ = cosφsin(φ . In the continuous conduction mode if the firing angle of the converter is increased beyond _________ degrees the converter operates in the _______ mode. The motor is supplied from a 230V.27 V.5632 ∴ E b = 2Vi sinθ = 183. i. E b no load = 2 × 230 V = 325.

Circuits. 1994. Version 2 EE IIT. 50 Hz. Applications and Design” Third Edition.Sen. Tata McGraw-Hill 1995 2) “Power Electronics. Mohan. Explain what will happen if a commutation failure occurs in any one of the thyristors. Prentice-Hall of India. Robbins. Find the load torque at which the dc motor of Q2 will operate at 2000 RPM with the field current and α remaining same. A separately excited dc motor is being braked by a single phase fully controlled bridge converter operating in the inverter mode as shown in Fig 10. Is it possible to operate a single phase fully controlled half wave converter in the inverting mode? Explain.jntuworld. Devices and Applications”. (ii) a dc power source of suitable polarity exists on the load side.C. In the discontinuous conduction mode the output voltage decreases with increasing load current. John Wileys and Sons Inc. Practice Problems and Answers Q1. 3) “Power Electronics. The motor is supplied from a single phase fully controlled converter operating from a 230 V.com • Depending on the load condition and the firing angle a fully controlled bridge converter can operate either in the continuous conduction mode or in the discontinuous conduction mode. Find the “power factor” of the converter as a function of the motor speed.jntuworld. Will the conduction be continuous under this condition? The speed of the dc motor in question Q2 is controlled by varying the firing angle of the converter while the load torque is maintained constant at the rated value.www. At what speed the motor will supply full load torque.Rashid. single phase supply with a firing angle of α = 30°. Q2.75Ω and inductance of 50 mH. • • • References 1) “Power Electronics” P. Muhammad H. Kharagpur 23 www. 2003. A 220V. Second Edition. 20A 1500 RPM separately excited dc motor has an armature resistance of 0. Q4. Converters. Q5. In the continuous conduction mode the load voltage depends only on the firing angle and not on load parameters. Assume continuous conduction and ripple free armature current. Undeland.7 (b). . The fully controlled bridge converter can operate as an inverter provided (i) α > π 2 . However the output voltage is always greater than that in the continuous conduction mode for the same firing angle.com Q3.

2 2 × 230 Assuming continuous conduction v 0 = cos30o = 179.jntuworld. Otherwise i0 will start increasing again and the thyristor T will fail to commutate.33 volts E = 0. 2. For the machine to deliver full load torque with rated field the armature current should be 20 Amps.75 = 164.3. ∴ sinθ = b 2Vi Version 2 EE IIT. the load circuit must contain a voltage source of proper polarity. However.33 volts. care should be taken such that i0 becomes zero before vi exceeds E in the negative half cycle.com . Figure shows that it is indeed possible for the half wave converter to operate in the inverting mode for some values of the firing angle.505 . Kharagpur 24 www.com Answers 1.www. As explained in section 10.3. π For 20 Amps armature current to flow the back emf will be Eb = Va – IaRa = 179. Such a load circuit and the associated waveforms are shown in the figure next.jntuworld.33 – 20 × 0.

31 is 2 2 pf = cosα = 5.2369. tanφ = ωL a = 20. 1.com .61+ . Now from equation 10.β ) ⎤ = 17.39 α -β tanφ = 0.α) .4 N + 0. 4.32) 2sin(φ .32 it can be shown that the conduction will be discontinuous.61 ⎣ ⎦ 18.0477(α . Kharagpur 25 www. At 2000 RPM.com For the given machine.φ ) .589 cosφ ∴ the conduction is continuous. φ = 87.4515 e.266o .β ) ⎤ + e ⎣ ⎦ or sinθ ⎡ sinθ ⎤ ⎢ cosφ + sin ( φ .sin ⎡( α .sin ⎡57.α) = 11. To maintain constant load torque equal to the rated value the armature voltage should be N Va = ra I a rated + E b rated N rated N = 0.75 × 20 + 205 × = 0.266 + ( α .75 = 205 volts.sin(φ .616 × 10.944.e-π/tanφ sinθ and = 10.9565 × 10.84.jntuworld.( α .jntuworld.33 is N r = ×1500 = 1202 RPM .0652 π This gives the input power factor as a function of speed. α = 30o sin ⎡( α .8412] .β) .www.266o ⎤ = 17.0724 Now the power factor from equation 10.33 volts 1500 2Vi From equation 10. At 1500 RPM the back emf is 220 – 20 × 0. ∴The speed at which the machine delivers rated torques 164. E b = ∴ sinθ = Eb 2000 × 205 = 273. Ra Now from equation (10.137 N + 15 V 1500 In a fully controlled converter operating in the continuous conduction mode 2 2 Va = Vi cosα = 207.0477(α .61 ⎣ ⎦ Solving which β ≈ 140° Version 2 EE IIT.073 cosα π ∴ cosα = 6. φ = 87.266o .α ) ⎥ = cosφ ⎣ ⎦ .β ) + 57.4 N + 0. 205 3.β) o e [17.

8 (a) let there be a commutation failure of T1 at ωt = α.com ∴ from equation 10.36 2Vi Ioav = [cosα .cosβ + sinθ(α .676 ∴ the load torque should be ×100 = 13.676 Amps πZcosφ 2. Referring to Fig 10. Version 2 EE IIT.www.jntuworld.38% of the full load torque.jntuworld. In that case the conduction mode will be T3 T2 instead of T1 T2 and v0 will be zero during that period.com . 20 5. However the converter will continue to operate in the inverter mode and the motor will be braked. Kharagpur 26 www. As a result average value of V0 will be less negative and the average armature current will increase.β)] = 2.

Kharagpur 1 www.com .com Module 2 AC to DC Converters Version 2 EE IIT.www.jntuworld.jntuworld.

com .www.jntuworld.com Lesson 11 Single Phase Half Controlled Bridge Converter Version 2 EE IIT.jntuworld. Kharagpur 2 www.

Identify the design implications of each topology. Version 2 EE IIT. Kharagpur 3 www. Analyze the operation of the converter in the continuous conduction mode to find out the average and RMS values of different system variables.www. Find out an analytical condition for continuous conduction relating the load parameters with the firing angle. Construct the conduction table and thereby draw the waveforms of different system variables in the continuous conduction mode of operation of the converter.jntuworld.com Operation and analysis of single phase half controlled converters Instructional Objectives On completion the student will be able to • • • • • • Draw different topologies of single phase half controlled converter.com .jntuworld. Analyze the operation of the converter in the discontinuous conduction mode of operation.

The resulting converters are called single phase half controlled converters.1 (c) the diodes carry current for a considerably longer duration than the thyristors. many of the industrial application do not utilize the inverter mode operation capability of the fully controlled converter. For that.www. As the input voltage passes through negative going zero crossing D4 comes into conduction commutating D2 in Fig 11.1 (b) both the thyristors and the diodes carry current for half the input cycle. However. In this lesson the operating principle and characteristics of a single phase half controlled converter will be presented with reference to the circuit in Fig 11.1 (b) and (c) are identical although the device designs differs. Single phase fully controlled converters have other disadvantages as well such as relatively poor output voltage (and current for lightly inductive load) form factor and input power factor. In such situations a fully controlled converter with four thyristors and their associated control and gate drive circuit is definitely a more complex and expensive proposition. The inverter mode of operation of a single phase fully controlled converter is made possible by the forward voltage blocking capability of the thyristors which allows the output voltage to go negative.com 11. The disadvantages of the single phase fully controlled converter are also related to the same capability.1 Introduction Single phase fully controlled bridge converters are widely used in many industrial applications. However. As far as the input and output behavior of the circuit is concerned the circuits in Fig 11. in Fig 11.1 (b). Version 2 EE IIT. two of the thyristors of a single phase fully controlled converter has to be replaced by two diodes as shown in Fig 11. however. Kharagpur 4 www. They can supply unidirectional current with both positive and negative voltage polarity.1(a).com . Of course this circuit will not be able to operate in the inverter mode.1 (c). The complexity of the circuit is not reduced. Thus they can operate either as a controlled rectifier or an inverter. the devices T1 and D2 conducts in the positive input voltage half cycle after T1 is turned on.jntuworld. The load voltage is thus clamped to zero until T3 is fired in the negative half cycle.1 (b) and (c).1 (b) or T1 in Fig 11. In Fig 11.jntuworld. As in the case of fully controlled converters. Here as the output voltage tries to go negative the diode across the load becomes forward bias and clamp the load voltage to zero. In order to improve the output voltage and current form factor the negative excursion of the output voltage may be prevented by connecting a diode across the output as shown in Fig 11.

Of course it is always possible that none of the four devices conduct.com .com 11. it can be stated that for any load current to flow one device from the top group (T1 or T3) and one device from the bottom group must conduct. Kharagpur 5 www.1 (b).1 (b).jntuworld. The load current during such periods will be zero. On the other hand T1 D4 and T3 D2 conducts simultaneously whenever T1 or T3 are on and the output voltage tends to go negative.www. there are four operating modes of this converter when current flows through the load.2 Operating principle of a single phase half controlled bridge converter With reference of Fig 11. T1 T3 or D2 D4 cannot conduct simultaneously. The operating modes of this converter and the voltage across different devices during these operating modes are shown in the conduction table of Fig 11. However.jntuworld. Therefore. Version 2 EE IIT.2. This table has been prepared with reference to Fig 11.

diodes. If at the negative going zero crossing of the input voltage load current is still positive it commutates from D2 to D4 and the load voltage becomes zero. different.www.jntuworld. v. iii. Otherwise the mode of conduction becomes discontinuous. The operation of the converter can be explained as follows when T1 is fired in the positive half cycle of the input voltage.1 Fill in the blanks(s) with the appropriate word(s) i. A half controlled converter has improved input ___________________ compared to a fully controlled converter. Load current flows through T1 and D2. ii. In a half controlled converter two ___________________ of a fully controlled converter are replaced by two ___________________. (ii) diodes. Kharagpur 6 www.com It is observed that whenever D2 conducts the voltage across D4 is -vi and whenever D4 conducts the voltage across D2 is vi. Since diodes can block only negative voltage it can be concluded that D2 and D4 conducts in the positive and the negative half cycle of the input supply respectively. The input/output waveforms of the two different circuit topologies of a half controlled converter are ___________________ while the device ratings are ___________________. (iii) same. Similar conclusions can be drawn regarding the conduction of T1 and T3. two. Depending on the positions of the ___________________ the half controlled converter can have ___________________ different circuit topologies. Exercise 11. iv. (iv) form factor.jntuworld. If the load current further continuous till T3 is fired current commutates from T1 to T3. This mode of conduction when the load current always remains above zero is called the continuous conduction mode. (v) power factor. A half controlled converter has better output voltage ___________________ compared to a fully controlled converter. Answer: (i) thyristors. Version 2 EE IIT.com .

com . Version 2 EE IIT.3 shows the circuit diagram and the waveforms of a single phase half controlled converter supplying an R – L – E load.com 2. 11. Since the load current is constant.1 Single phase half controlled converter in the continuous conduction mode From the conduction table and the discussion in the previous section it can be concluded that the diode D2 and D4 conducts for the positive and negative half cycle of the input voltage waveform respectively. Kharagpur 7 www. On the other hand T1 starts conduction when it is fired in the positive half cycle of the input voltage waveform and continuous conduction till T3 is fired in the negative half cycle.2. since the load current is constant.α radians while the diodes conduct for π + α radians. The ration of the thyristors to the diode RMS current ratings will be unity for the circuit of Fig 11. Find out an expression of the ration of the thyristor to diode RMS current ratings in the single phase half controlled converter topologies of Fig.www.1(b) & (c). Assume ripple free continuous output current.jntuworld. Fig. From the second conduction diagram the thyristors conduct for π . Thyristor RMS current rating 1− α / π = Diode RMS current rating 1+ α / π in this case 11.1 (b). 11.jntuworld. Answer In the first conduction diagram the diodes and the thyristors conduct for equal periods.

π sinθ) R πR Voav = (11. Where upon load current again free wheels through T3 and D2 while the load voltage is clamped to zero. From the discussion in the previous paragraph it can be concluded that the output voltage (hence the output current) is periodic over half the input cycle. Hence 2V 1 π 1 π ∫o vo dωt = π ∫α 2Vi sin ωt dωt = π i (1+ cosα) π V -E 2Vi Iov = oav = (1+ cosα .jntuworld. Kharagpur 8 www.1) (11. At ωt = π as vi tends to go negative D4 is forward biased and the load current commutates from D2 to D4 and freewheels through D4 and T1.3 (b) T1 D2 starts conduction at ωt = α. Output voltage during this period becomes equal to vi.com Referring to Fig 11.jntuworld.www. The output voltage remains clamped to zero till T3 is fired at ωt = π + α.com . The T3 D4 conduction mode continues upto ωt = 2π.2) Version 2 EE IIT.

7) Version 2 EE IIT.4) io α = I1 + io π ⎡ sinθ ⎤ ⎢sin(α . Kharagpur 9 www.jntuworld.jntuworld. the closed form expression of io can be found as explained next.α) 2Vi ⎡ sinθ ⎤ = I1 + ⎢sinφ .cosφ ⎥ ⎣ ⎦ (π . the output voltage (and current) contains a large number of harmonic components. In the period α ≤ ωt ≤ π dio + Rio + E = 2Vi sin ωt dt (ωt-α) 2Vi ⎡ sinθ ⎤ io = I1e tanφ + ⎢sin(ωt .com .6) In the period π ≤ ωt ≤ π + α L dio + Rio + E = 0 dt (11.3) (11.www. However. tanφ = Where sinθ = R 2Vi L (11. The Fourier series representation of the load current can be obtained from the load voltage by applying superposition principle in the same way as in the case of a fully controlled converter.com Clearly in addition to the average component.φ) .φ) .5) (11.cosφ ⎥ Z ⎣ ⎦ E ωL . Z = R2 + ω2 L2 . Magnitude of the harmonic voltages can be found by Fourier series analysis of the load voltage and is left as an exercise. The minimum harmonic voltage frequency is twice the input supply frequency.cosφ ⎥ tanφ Z ⎣ ⎦ 2Vi Z (11.

com .12) For π ≤ ωt ≤ π + α (ωt-α) ⎧ ⎫ α (ωt-π) ⎡ ⎤ e tanφ 2Vi ⎪ sinθ ⎪ tanφ tanφ io = + sinφ e ⎥ ⎨ ⎢sin(φ .www.5.jntuworld.i0 ii = 0 for α ≤ ωt ≤ π for π + α ≤ ωt ≤ 2π otherwise (11.e ⎥ Z cosφ ⎢ ⎥ ⎣ ⎦ (ωt-π) 2Vi ⎡ sinθ ⎤ tanφ + ⎢sinφ e ⎥ Z ⎢ cosφ ⎥ ⎣ ⎦ (11.14) However. Version 2 EE IIT.9) (11.α) + sinφ e 1.jntuworld.com io = io π e ∴ ∴ io = I1 e io - - (ωt-π) tanφ (ωt-α) tanφ (ωt-π) 2Vi sinθ ⎡ .10) π+α = I1e - π tanφ 2Vi + Z α ⎡ sinθ ⎤ tanφ ⎢sinφ e ⎥ cosφ ⎥ ⎢ ⎣ ⎦ Due to periodic operation io α = io π+α ∴ I1 = 2Vi Z sin(φ .α) + sinφe ⎬ π Z ⎪⎢ cosφ ⎪ ⎥ ⎣ ⎦ 1.11) ∴ For α ≤ ωt ≤ π (ωt-α) ⎧ ⎫ α ⎡ ⎤ e tanφ 2Vi ⎪ sinθ ⎪ tanφ io = + sin(ωt .13) The input current ii is given by ii = i0 ii = .e tanφ ⎩ ⎭ (11.e tanφ ⎩ ⎭ (11.tanφ ⎤ ⎢1.8) (11.φ) ⎥ ⎨ ⎢sin(φ .14 since the expression of i0 is considerably complex. Considerable simplification can however be obtained if the actual ii waveform is replaced by a quasisquare wave current waveform with an amplitude of Ioav as shown in Fig 11.α) + sinφe ⎬ π Z ⎪⎢ cosφ ⎪ ⎥ ⎣ ⎦ 1. it will be very difficult to find out the characteristic parameters of ii using equation 11. Kharagpur 10 www.e π tanφ - α tanφ (11.

α/π Ioav The displacement factor = cos α/2 ∴ ∴ Vi Ii1 cos α = Vo I oav = 2 Ii1 = 2 2 IOAV cos α 2 π 2Vi (1+ cosα)I OAV π (11.2 Fill in the blank(s) with the appropriate word(s).www.jntuworld.17) (11.jntuworld. For the same firing angle and input voltage the half controlled converter gives ___________________ output voltage form factor compared to a fully controlled converter.18) 2 cos α 2 π(π .20) Exercise 11. In a half controlled converter the output voltage can not become ___________________ and hence it can not operate in the ___________________ mode.α) ∴ ∴ Distortion factor = Ii1 IiRMS =2 (11. For ripple-free continuous output current the input current displacement factor of a half controlled converter is given by ___________________. . Version 2 EE IIT.5 IiRMS = 1.15) (11. For the same supply and load parameters the output current form factor of a half controlled converter is ___________________ compared to a fully controlled converter. ii.com iii. i. Kharagpur 11 www.19) Power factor = displacement factor × distortion factor 2 = (1+ cosα) π(π . iv.16) (11.com From Fig 11.α) (11.

(ii) lower. when T1 is fired at ωt = α the output voltage (instantaneous value) is larger than the back emf. Assume continuous conduction.2 Single phase half controlled converter in the discontinuous conduction mode.23 2 2 ∴ α = 57. (iv) lower. v. Now by (11. π Answer: (i) negative. the load current increases till vo becomes equal to E again at ωt = π – θ. Find the value of α which will increase the motor no load speed by 30%. Neglect lasses and saturation. 2 2. Such a condition exists however and can be found by carefully examining the way this converter works. Kharagpur 12 www.www. A single phase half controlled converter is used to supply the field winding of a separately excited dc machine. Now if io becomes zero before T3 is fired at ωt = π + α the conduction becomes discontinuous.21) Which in conjunction with the equation (11.α) ≥ sinθ cosφ Version 2 EE IIT.jntuworld. With the rated armature voltage the motor operates at the rated no load speed for a fining angle α =0°.e π tanφ - α tanφ .com The free wheeling operating mode of a half controlled converter helps to make the output current ___________________. Therefore the applied field voltage must by 23%.3 (b). So far we have discussed the operating characteristics of a single phase half controlled converter in the continuous conduction mode without identifying the condition required to achieve it. Answer: N NO load α 1 φf or φf α 1 N NO load In order to increase Nno load by 30% φf should be reduced by 23%.α) + sinφ e 1.jntuworld. So clearly the condition for continuous conduction will be io ωt =α≥0 (11. onwards the load current starts decreasing. (iii) cos . inverter. Referring to Fig 11. Therefore.com .4o 1 + cos α 2 11.2. There.sin(φ .1) Vf ( α ) = Vf ( α = 0 ) ∴ 1− 1 + cos α 1 − cos α = = 0. (v) continuous.12) gives sin(φ .

22) If the condition in Eq.e π tanφ ≥ sinθ cosφ (11. Fig.www. Clearly. For this case vo = vi vo = 0 vo = E for α ≤ ωt ≤ π for π ≤ ωt ≤ β for β ≤ ωt ≤ π + α (11.α)e - π tanφ + sinφ e - α tanφ 1. Of these two cases the second one will be analyzed in detail here.22 is violated the conduction will become discontinuous.com or sin(φ . In the second case io continuous beyond ωt = π but becomes zero before ωt = π + α. Kharagpur 13 www. io starts from zero at ωt = α.jntuworld.com . In both cases however. two possibilities exist.jntuworld.6 shows the wave forms in these two cases. In the first case the load current becomes zero before ωt = π. 11. 11.23) Version 2 EE IIT. The analysis of the first case is left as an exercise.

31) (11.com .29) (11.25) = 2Vi ⎡ π .26) However IORMS cannot be computed directly from VORMS.32) Version 2 EE IIT.30) (11. This will also help to find out an expression for the conduction angle β. Kharagpur 14 www.β) sin θ + 4 sin 2α ⎥ π ⎣ ⎦ 1 (11. tanφ = ωL .www.28) ⎤ 2Vi ⎡ sinθ ⎢ cosφ + sin(φ .E 2Vi = [1+ cosα + (α .jntuworld.27) 2Vi 2Vi sinθ sin(ωt .β)sinθ ] π IOAV = VORMS VOAV .α) ⎥ Z ⎣ ⎦ ωt-α ⎤ .tanφ 2Vi ⎧ ⎡ sinθ sinθ ⎫ ⎪ ⎪ io = + sin(φ . For this the closed form expression for io has to be obtained. For α ≤ ωt ≤ π 2Vi sin ωt = Ri o + L The general solution is given by di o +E dt (11.φ) Z Z cosφ Where Z = R 2 + ω2 L2 .α 1 ⎤2 2 ⎢ 2 + (π + α .α) ⎥ e + sin(ωt .α) ⎥ e tanφ + sinφ io at ωt = π = ⎨⎢ ⎬ Z ⎪ ⎣ cosφ cosφ ⎪ ⎦ ⎩ ⎭ ∴ Io = For π ≤ ωt ≤ β O = Ri o + L di o +E dt (11.φ) ∴ ⎨⎢ ⎬ Z ⎪ ⎣ cosφ cosφ ⎪ ⎦ ⎩ ⎭ α-π ⎤ 2Vi ⎧ ⎡ sinθ sinθ ⎫ ⎪ ⎪ + sin(φ . io = 0 io = Io e - (ωt-α) tanφ + (11.com Therefore VOAV = 1 π+α v o dωt π ∫α π+α 1 π 2vi sinθ dωt ⎤ = ⎡ ∫ 2vi sinωt dωt + ∫ ⎢ α ⎥ β ⎣ ⎦ π 2Vi = [1+ cosα + (π + α .β)sinθ] R π Z cosφ 1 π+α 2 = vo dωt π ∫α π+α 1 π 2 = ⎡ ∫ 2vi2 sin 2 ωt dωt + ∫ 2vi2 sin 2θ dωt ⎤ ⎢ α ⎥ β ⎣ ⎦ π 1 (11.24) (11.jntuworld. E = 2Vi sinθ R At ωt = α.

The Version 2 EE IIT.com . Answer: (i) zero.35) (11.38.36) gives closed from expression of io in this conduction mode. 50Hz single phase supply through a 50mH line inductor.α) e tanφ + e cosφ cosφ β π α (11.jntuworld. Exercise 11.α) ⎥ etanφ + sinφ = ⎨⎢ ⎬ cosφ ⎪ ⎦ ⎪ ⎣ cosφ ⎩ ⎭ α-π ⎫ ⎤ 2Vi ⎧ ⎡ sinθ ⎪ ⎪ I1 = + sin(φ . To find out β we note that at ωt = β.38) Given the values of ϕ. Single phase half controlled converters are most suitable for loads requiring ___________________ voltage and current. At the boundary between continuous and discontinuous conduction the value of the output current at ωt = α is ___________________. (ii) π. The battery has on interval resistance of 0.36) ∴ ∴ α-π ⎧ ⎡ sinθ ⎤ sinθ ⎫ ⎪ ⎪ + sin(φ .37) α sinθ tanφ sinθ tanφ e = sinφ e tanφ + sin(φ .34) (11.jntuworld.α) ⎥ e tanφ + sinφ ⎬ ⎨ Z ⎪ ⎢ cosφ ⎦ ⎪ ⎩⎣ ⎭ ωt-α ωt-π ⎤ . The output voltage and current waveform of a single phase fully controlled and half controlled converter will be same provided the extinction angle β is less than ___________________. iv. i.1Ω. (iv) unidirectional.www.tanφ 2Vi ⎧ ⎡ sinθ sinθ ⎫ ⎪ ⎪ io = + sin(φ .2) Fill in the blank(s) with the appropriate word(s).α) ⎥ e + sinφe tanφ ⎨⎢ ⎬ Z ⎪ ⎣ cosφ cosφ ⎪ ⎦ ⎩ ⎭ 2Vi Z Equations (11.33) = I1 - 2Vi sinθ Z cosφ (11. (iii) higher. A single phase half controlled converter charges a 48v 50Ah battery from a 50v. ii. io = 0.com ∴ io io = I1 e ωt = π - ωt-π tanφ - 2Vi sinθ Z cosφ (11. 2.30) and (11. Kharagpur 15 www. iii.3 (After section 11.36) ⎡ sinθ ⎤ tanφ sinθ + sinφ e tanφ =0 ⎢ cosφ + sin(φ . For the same value of the firing angle the average output voltage of a single phase half controlled converter is ___________________ in the discontinuous conduction mode compared to the continuous conduction mode. θ and α the value of β can be obtained from equation 11.2. So from equation (11.α) ⎥ e cosφ ⎣ ⎦ or α-β π-β (11.

1994.. “Power Electronics.jntuworld. Answer: From the given data assuming continuous conduction the output voltage of the converter to charge the battery at C/5 (10 Amps) rate will be Vo = E + Ib rb = 42 + 0. P.C.606 = 42. devices and applications”. Muhammad H.1×10 = 43volts φ = tan −1 ωL = 89. Rashid.08.22) one finds that the conduction will be continuous.99998 cos φ = 6. “Power Electronics.com . tan φ = 157.43o Putting these values in equation (11. Mohan. applications and design”.jntuworld. Therefore 2Vi sin α = E = 52 sin 52 ∴ α = 180o − = 132.63o .com firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is fully discharged at 42 volts. The conduction will remain continuous till sin θ = E = 2vi cos φ sin ( φ − α ) e − π tan φ −π −α tan φ 1 + sin 2φ e 2 1− e tan φ From the given value this gives. Undeland. Kharagpur 16 www.8V At E = 52 volts io is zero. Tata McGraw Hill Publishing Company Limited 1995. 2003.66o 2 × 50 References [1] [2] [3] “Power Electronics”. Second Edition. John Wiley and Sons Inc.www. Up to what battery voltage will the conduction remain continuous? If the charging current of the battery is to become zero when it is fully charged at 52 volts what should be the value of the firing angle. Version 2 EE IIT. Sen. Robbins. Third Edition. Find out whether the conduction will be continuous or discontinuous at this condition. sin φ = 0. E = 2 × 50 × 0. circuits. Prentice – Hall of India.3 × 10−3 R ∴ α = 24. converters.

and speed of 1400 RPM. In a half controlled converter the output voltage does not become negative and hence the converter cannot operate in the inverter mode. firing angle and load parameters the half controlled converter has better output voltage and current form factor compared to a fully controlled converter.www. 20A dc motor from a 230V 50HZ single phase supply. The thyristor T3 of Fig 1. A single phase half controlled converter supplies a 220V. Describe how this circuit will work in the presence of the fault.com Lesson Summary • • Single phase half controlled converters are obtained from fully controlled converters by replacing two thyristors by two diodes. 1500rpm. Half controlled converters are most favored in applications requiring unidirectional output voltage and current. The motor has a armature resistance of 1. Two thyristors of one phase leg or one group (top or bottom) can be replaced resulting in two different topologies of the half controlled converter. A single phase half controlled converter is used to boost the no load speed of a separately excited dc machine by weakening its field supply. For the same firing angle and load current the half controlled converter in the continuous conduction mode has better input power factor compared to a fully controlled converter. Version 2 EE IIT.com .jntuworld.1(b) fails to turn on at the desired instant. At α = 0° the half controlled converter produces the rated field voltage. From the operational point of view these two topologies are identical. • • • • • Practice Problems and Answers Q1. Kharagpur 17 www. For the same input voltage. If the field inductance is large enough to make the field current almost ripple face what will be the input power factor when the dc motor no load speed is bossed to 150%? Q3. Q2.0Ω and inductance of 50mH.jntuworld. For the same firing angle and input voltage the half controlled converter in the continuous conduction mode gives higher output voltage compared to a fully controlled converter. What will be the operating modes and torques for α = 30°.

The conduction periods T1 D2 & T1 D4 commences as usual. Thus the full positive half cycle of supply voltage is applied across the load followed by a entire half cycle of zero voltage.1 (c)] 2. It can be easily verified that this possibility does not existion the circuit shown in Fig 11.77. Hence T1 D2 conduction period starts right after ωt = 2π instead of at ωt = 2π + α. Kharagpur 18 www.5 Vf 1 + cos α 1 = = but Vf rated 2 1. Thus the load voltage becomes a half wave rectified sine wave and voltage control through fining angle is last. However at ωt = π + α when T3 is fired it fails to turn ON and as a consequences T1 does not commutate. This is the effect of the fault.jntuworld. since T1 does not stop conduction fining angle control on it is lost after words. Version 2 EE IIT. T1 is tired at ωt = α and the load current commutates from T3 to T1.5 ∴ α = 70.53o using equation 11. [Note: This phenomenon is known as “half cycle brusting”.20 the power factor will be 0.jntuworld.com Answer to practice problems Figure above explains the operation of the circuit following the fault. However.com . Now if the load is highly inductive T1 D4 will continue to conduct till ωt = 2π and the load voltage will be clamped to zero during this period. For a separately excited dc motor ωNO load α ∴ Vf = 1 1 α φf Vf Vf rated for boosting no load speed by 150% 1.www.

2V. tanφ = E 14 220 − 20 × 1.53 ∴ Motor torque will be ×100 = 32.7V V −E ∴ Ia = a = 6.53A ra 6. Kharagpur 19 www.22 it can be 2Vi 15 2 × 230 conducted that the conduction is continuous ωL = 15.0 = × = 0.www. sinθ = From the given data.67% of full load torque. 20 Version 2 EE IIT.jntuworld.36o R ∴ Va = 193.jntuworld.578 substituting these values in equation 11. φ = 86. E = 186.com 3.com .7.

Kharagpur 1 www.www.jntuworld.com Module 2 AC to DC Converters Version 2 EE IIT.jntuworld.com .

jntuworld. Kharagpur 2 www.jntuworld.www.com Lesson 12 Single Phase Uncontrolled Rectifier Version 2 EE IIT.com .

Instructional Objectives On completion the student will be able to • • • • • Draw the conduction table and waveforms of a three phase half wave uncontrolled converter supplying resistive and resistive inductive loads. Analyze the operation of a three phase full wave uncontrolled converter supplying a Capacitive – Resistive load. Version 2 EE IIT.com .www. Find out the harmonic components in the input / output voltage and current waveforms of a three phase uncontrolled full wave converter.com Operation and Analysis of three phase uncontrolled rectifier. Kharagpur 3 www. Calculate the average and RMS values of the input / output current and voltage waveforms of a three phase uncontrolled half wave converter. Analyze the operation of a three phase full wave uncontrolled converter to find out the input / output current and voltage waveforms along with their RMS and Average values.jntuworld.jntuworld.

Low frequency harmonic current is injected in the input ac line which is difficult to filter. Fig. 12.com 12.www. These topologies will be analyzed in detail in this section. In a way it is also natural that bulk loads are supplied by three phase converters since bulk electrical power is always transmitted and distributed in three phases and high power should load three phases symmetrically. conduction table and wave forms of a three phase half wave uncontrolled converter supplying a resistive inductive load. These can be placed in one of two groups according to whether three or six diodes are used. Above this power level three phase ac – dc power supplies are usually employed. Large low frequency harmonic ripple current causing harmonic power loss and reduced efficiency. Very large filter capacitor for obtaining smooth output dc voltage. as already discussed.1 shows the circuit diagram. Polyphase rectifiers produce less ripple output voltage and current compared to single phase rectifiers.jntuworld.1 Introduction Single phase rectifiers. Single phase ac – dc converters have several disadvantages such as • • • • Large output voltage and current form factor.com . Version 2 EE IIT. They are also found useful for supplying small dc loads rarely exceeding 5 KW. 12.jntuworld. Many of these disadvantages are mitigated to a large extent by using three phase ac – dc converters. Kharagpur 4 www. The situation becomes worse with capacitive loads. The efficiency of polyphase rectifier is also higher while the associated equipments are smaller. are extensively used in low power applications particularly for power supplies to electronic circuits. A three phase supply gives the choice of a number of circuits. Although not much used in practice it does provide useful insight into the operation of three phase converters.2 Operating principle of three phase half wave uncontrolled rectifier The half wave uncontrolled converter is the simplest of all three phase rectifier topologies.

com For simplicity the load current (io) has been assumed to be ripple free.com . 12. Fig.www.1 (a). Kharagpur 5 www.1 (c) second waveform) can be drawn easily from the conduction diagram. in a three phase half wave uncontrolled converter the anode of a diode is connected to each phase voltage source. The negative terminal of the load is connected to the supply neutral.1 (b) shows the conduction table of the converter. The conduction diagram for the diodes (as shown in Fig. 12. It should be noted that for the type of load chosen the converter always operates in the continuous conduction mode.jntuworld. As shown in Fig. Since the diodes can block only negative voltage it follows from the conduction table that a phase diode conducts only when that phase voltage is maximum Version 2 EE IIT. The cathodes of all three diodes are connected together to form the positive load terminal.jntuworld. 12.

All of them have a dc component which flows through the ac source.1 Fill in the blank(s) with the appropriate word(s).1 (c) deserve special mention. Three phase half wave uncontrolled rectifier requires ________ phase ______ wire power supply. i) ii) Three phase half wave uncontrolled rectifier uses ________ diodes. Kharagpur 6 www. 12. R IO 3 Ii RMS = I a RMS = I b RMS = I c RMS = (12.com of the three. 12.1 (a) is also known as the “maximum value” circuit).5) IO 3Vi Ii RMS 2π 3Vi 3 The harmonics present in vo and ii can be found by Fourier series analysis of the corresponding waveforms of Fig.4) 3 6 Vi IO 3 AV = 2π = ∴ Input power factor = (12.3) IO av = VOAV .com . Version 2 EE IIT. This may cause “dc saturation” in the ac side transformer.1) 1 VORMS (12.1 (c) and is left as an exercise. The phase current waveforms of Fig. From the waveforms of Fig.2) VORMS = 1.01 VOAV ∴ The output voltage form factor = (12. This is one reason for which the converter configuration is not preferred very much in practice. 12. 12.jntuworld.1 (c) are easily obtained from the supply voltage waveforms in conjunction with the conduction table. VO av IO Exercise 12. Once the conduction diagram is drawn other waveforms of Fig. 12.www.1 (c) VOAV = 3 5π/6 2Vi sin ωt d(ωt) 2π ∫π/6 3 6 Vi = 2π ⎡ 3 5π/6 ⎤2 = ⎢ ∫ 2Vi2 sin 2 ωt d(ωt) ⎥ ⎣ 2π π/6 ⎦ ⎡ 3 3 ⎤2 = ⎢1 + ⎥ Vi 4π ⎦ ⎣ 1 (12.jntuworld. (In signal electronics the circuit of Fig.

With reference to Fig 12. 2. (iii) 2π/3. Kharagpur 7 www. (v) dc. distortion factor and power factor of a three phase half wave rectifier supplying an R – L load. displacement factor.www. ∴ 2I a1 = B1 = R. Factor × Dist. The minimum frequency of the output voltage ripple in a three phase half wave uncontrolled rectifier is _________ times the input voltage frequency. Fundamental component of ia can be written as i a1 = 2 Ia1 sin(ωt + φ) where 2 2 2 Ia1 = A1 + B1 and φ = tan -1 A1 B1 A1 = 1 2π i a cosωt dωt π ∫0 1 2π B1 = ∫ i a sinωt dωt π 0 1 A1 = ∫π6 Id cosωt dωt = 0 π 6 5π ∴ B1 = 1 6 3 ∫π6 Id sinωt dωt = π Id π 5π 3 Id 3 ∴ Ia1 = Id 2 π π φ = 0 ∴ Displacement factor = cosφ = 1. The input line current of a three phase half wave uncontrolled rectifier contain ________ component.M.S value of ia = Ia = ∴ Distortion factor = Id 3 Ia1 3 = Ia 2π 3 2π Power Factor = Disp.com iii) iv) v) In a three phase half wave uncontrolled rectifier each diode conduct for _________ radians.jntuworld. (ii) three. Answers: (i) three.jntuworld. four.com . find out the. (iv) three. Factor = Version 2 EE IIT.1 the expression for phase current ia can be written as i a = Id ia = 0 π 5π ≤ ωt ≤ 6 6 otherwise. Assuming ripple free output current.

It will also be assumed in the following analysis that the load side inductance is large enough to keep the load current continuous. Compared to single phase converters the cases of discontinuous conduction in 3 phase bridge converter are negligible.3 Three phase full wave uncontrolled converter As has been explained earlier three phase half wave converter suffers from several disadvantages. Version 2 EE IIT. requirement of neutral connection and comparatively lower output voltage. Most of these disadvantages can be mitigated by using a three phase full wave bridge rectifier. Chief among them are dc component in the input ac current.com .3.jntuworld. This requirement has to be met by using a variable ac source (e. In this section the operation of a three phase full wave uncontrolled bridge rectifier with two different types of loads namely the R – L – E type load and the capacitive load will be described.com 12. This is probably the most extensively used rectifier topology from low (>5 KW) to moderately high power (> 100 KW) applications. 12.g a 3 phase variable) since the average output voltage of an uncontrolled rectifier is constant for a given ac voltage.www. The relevant condition for continuous conduction will be derived but analysis of discontinuous conduction mode will not be attempted. Usually for driving these loads a variable output voltage is required.jntuworld.1 Operation of a 3 phase full wave uncontrolled bridge rectifier supplying an R – L – E load This type of load may represent a dc motor or a battery. Kharagpur 8 www. In addition the input and output waveforms contain lower order harmonics which require heavy filtering.

jntuworld. Kharagpur 9 www.jntuworld.com Version 2 EE IIT.com .www.

Kharagpur 10 www. D4 and D6) must conduct at all time.www. Thus the converter Version 2 EE IIT.jntuworld.com .com Since the load current is assumed to be continuous at least one diode from the top group (D1. It can be easily verified that only one diode from each group (either top or bottom) conducts at a time and two diodes from the same phase leg never conducts simultaneously.jntuworld. D3 and D5) and one diode from the bottom group (D2.

D5D6 and D6D1. 12.io otherwise.2 (c) is constructed accordingly.com has six different diode conduction modes. D3D4.com .10) Ii1 RMS can be found as follows 3 VL Ii 1 = VOAV IOAV (12. This implies that D1D2 conducts in the interval 0 ≤ ωt ≤ π/3 as shown in Fig. For example for 0 ≤ ωt ≤ π/3 and 5π/3 ≤ ωt ≤ 2π ia = io for 2π/3 ≤ ωt ≤ 4π/3 ia = .2 (c). D4D5. The conduction diagram in Fig. The output dc voltage can be constructed from this conduction diagram using appropriate line voltage segments as specified in the conduction table. (12.6) ia = 0 The line current wave forms and their fundamental components are shown in Fig.e. 3 IOAV = VOAV − E R (12. 12.9) Ii RMS = 2 IOAV .2 (b) shows voltages across different diodes and the output voltage in each of these conduction modes.2 (c).jntuworld.jntuworld. D1D2 → D2D3 → D3D4 → D4D5 → D5D6 → D6D1 → D1D2 ---.11) Version 2 EE IIT.www. The diodes have been numbered such that the conduction sequence is D1 → D2 → D3 → D4 → D5 → D6 → D1---. The time interval during which a particular conduction mode will be effective can be ascertained from this table.8) VOAV = VORMS = ⎛ 3 3⎞ = ⎜1 + ⎟VL ⎜ 2π ⎟ ⎝ ⎠ (12. Kharagpur 11 www.2 (c) that the dc voltage output is periodic over one sixth of the input ac cycle. For π/3 ≤ ωt ≤ 2π/3 v o = 2VL sin ωt 3 2π/3 3 2 ∫π/3 2VL sin ωt dωt = π VL π 3 2π/3 2 2 ∫π/3 2VL sin ωt dωt π (12. When a diode stops conduction its current is commutated to another diode in the same group (top or bottom). D2D3. 12. These are D1D2. Fig. It is clear from Fig 12. 12. The input ac line currents can be constructed from the conduction diagram and the output current. Each conduction mode lasts for π/3 rad and each diode conducts for 120º. vca and vcb) are negative. For example the D1D2 conduction mode will occur when the voltage across all other diodes (i. vba. This way the sequence of conduction modes become.7) (12.

Version 2 EE IIT. Three phase full wave uncontrolled rectifier does not require ________ wire connection.e π 3tanφ (12.17) ∴ sinφ 1. R 2VL ⎡ sinθ ⎤ ⎢sin(ωt .13) for π/3 ≤ ωt ≤ 2π/3 di o L + Ri o + E = v o = 2VLsinωt dt The general solution is given by (12.14) io = I1e Where tanφ = - ωt .e ⎦ (12.φ ⎟ = I1e 3tanφ + sin ⎜ .2 Fill in the blank(s) with the appropriate word(s).12) ∴ Power factor = distortion factor = 3 Ii RMS π A closed form expression for io can be found as follows (12.www.jntuworld. Kharagpur 12 www.π/3 ⎡ ⎤ 2VL ⎢ sinφ .φ) .φ ⎟ ⎥ ⎢ ⎥ Z ⎢ ⎝ 3 ⎠ cosφ ⎦ ⎣ ⎝ 3 ⎠ cosφ ⎦ ⎣ (12.16) π ∴ 2VL I1 + Z I1 = 2VL Z ⎡ ⎛ π ⎞ sinθ ⎤ 2VL ⎡ ⎛ 2π ⎞ sinθ ⎤ sin ⎜ .3tanφ cosφ ⎥ ⎣1. In a three phase full wave uncontrolled rectifier each diode conducts for _______ radians.π/3 tanφ + ωL . i) ii) iii) Three phase full wave uncontrolled rectifier uses _________ diodes.com .19) Exercise 12.com Since input displacement factor is unity ∴ Ii1 = VOAV 6 IOAV = IOAV π 3VL Ii1 = (12.3tanφ sinθ ⎥ io = e + sin ( ωt .φ ) π Z ⎢ .cosφ ⎥ Z ⎣ ⎦ E sinθ = .jntuworld.18) ∴ ωt .15) Now since the current waveform is periodic over one sixth of the input ac cycle π⎞ 2π ⎞ ⎛ ⎛ i o ⎜ ωt = ⎟ = i o ⎜ ωt = ⎟ 3⎠ 3 ⎠ ⎝ ⎝ (12. Z = R 2 + ω2 L2 2VL (12.

The input ac line current of a three phase full wave uncontrolled rectifiers supplying an R – L – E load contain only ________ harmonics but no ________ harmonic or __________ component.34 :1 ∴ The required turns ratio = 94 V0 = Output voltage can be written as v 0 = V0 + ∑ v hn n =1 α Where vhn = nth harmonic voltage magnitude. (ii) neutral.jntuworld. tripler. 1500 rpm 20 A separately excited dc motor has armature resistance of 1Ω and negligible armature inductance. 3 Primary side is delta connected. The motor is supplied from a three phase full wave uncontrolled rectifier connected to a 220 V. A three phase full wave uncontrolled rectifier supplying an R – L – E load normally operates in the ________ conduction mode. 3 phase. vi) Answers: (i) six. This is the line voltage of the secondary side of the transformer. 2. What is the maximum torque as a percentage of the rated torque the motor will be able to supply without over heating.com iv) v) The minimum frequency of the output voltage ripple in a three phase full wave rectifier is _________ times the input voltage frequency. So 163 Secondary phase voltage = = 94 volts . (vi) continuous. (iv) six.E α v hn +∑ r n =1 r Where E = back emf and r = armature resistance ∴ i0 = ∴ I 0RMS 2 α ⎛ V -E⎞ ⎛V ⎞ =⎜ 0 + ∑ ⎜ hn ⎟ ⎟ ⎝ r ⎠ n=1 ⎝ r ⎠ 2 = I0AV - 2 2 2 2 V0AV V0AV α ⎛ Vhn ⎞ + 2 + ∑⎜ ⎟ r2 r n=1 ⎝ r ⎠ V2 V2 2 = I 0AV . So Primary phase voltage = 220 V. 50 Hz supply through a Δ/Y transformer. (iii) 2π/3.0AV + 0RMS r2 r2 2 Version 2 EE IIT. (v) odd.www.com . V0 . A 220 V. The secondary is star connected.jntuworld. Find out the transformer turns ratio so that the converter applies rated voltage to the motor. dc. 220 = 2. Answer: Average output voltage of the converter is 3 2 VL = 220V π ∴ VL = 163 Volts. Kharagpur 13 www. Assume ideal transformer and continuous conduction.

vcb and vac provided at least one diode from the top group and one from the bottom group conducts at that instant. 12. however if the output capacitor voltage is larger than the maximum line voltage. vbc.743 ×100 = 88.3 (b). D5D6 and D6D1 appear in that order. Therefore. Operation of the converter can be explained as follows. The top group diodes (D1. It is very widely used as the front end of a variable voltage variable frequency dc – ac inverter.www. Version 2 EE IIT. 12. At this instant the appropriate diodes from both the top and the bottom group starts conducting and continuous to do so till the sum of the capacitor charging current and the load current becomes zero. D4D5. D5) form a “Maximum value circuit” and therefore the maximum of the phase voltages van. D1D2. vbn.816 In a separately excited dc machine Te ∝ I0AV ∴ Maximum allowable torque = 17. vcn appears at the positive dc bus. D4. D2D3.00176 -1) 1 ∴ I0AV = 17.3. In addition an additional operating mode in which none of the diodes conduct appears in the conduction diagram as shown in Fig. the output voltage waveform at any instant is equal to the maximum of the six line voltages vab.3 (a) shows the power circuit diagram of such a converter.743 Amps. vbn and vcn appears at the negative dc bus. Fig. On the other hand.2 Operation of a three phase uncontrolled bridge rectifier supplying a capacitive load A three phase uncontrolled bridge rectifier supplying a capacitive load is a very popular power electronic converter.715 % of full load torque. During these periods the output capacitor discharges through the load. Kharagpur 14 www. D3D4. = 314. the bottom group diodes (D2. vba.com .jntuworld. Therefore the minimum of the phase voltages van. As the capacitor voltage decreases its voltage becomes equal to the incoming line voltage.jntuworld.00176 ⎝ V0AV ⎠ ∴ ∴ 2 202 = I 0AV + 2 I 0AV 2202 (1. None of the diodes will conducts. D3.com 2 = I 0AV + 2 V0AV ( FF2 -1) r2 To prevent over heating I0RMS = 20 A 2 ⎛ V0RMS ⎞ 2 For the given converter FF = ⎜ ⎟ = 1. D6) form a “Minimum value circuit”. 20 12. All the six operating modes of a 3 phase bridge rectifier namely. vca.

jntuworld.www.com Version 2 EE IIT.com . Kharagpur 15 www.jntuworld.

jntuworld. ii = 0 ∴ cos (β .⎟ 3 ⎠ ωt = α + π ⎝ 3 = 2VL sin α Version 2 EE IIT.jntuworld.α + φ ωRC (12.φ) = 0 in the interval β ≤ ωt ≤ α + π/3 c dvo v o + =0 dt R ωRC 1+ ω 2 R 2 C 2 (12.20) (12.22) (12.com .24) v o β = 2VL sinβ = 2VL cosφ = 2VL (ωt . 12.23) or β = π +φ 2 (12.β) ωRC (12.com From Fig.φ) R 1 Where tanφ = ωRC ∴ ic = c At ωt = β.3 (b) In the interval α ≤ ωt ≤ β v o = 2VL sin ωt dvo = 2VL ωc cos ωt dt v V i o = o = 2 L sin ωt R R VL ∴ ii = i o + i c = 2 [ ωRC cos ωt + sin ωt ] R V = 2 L 1+ ω2 R 2 C2 cos (ωt .21) (12. Kharagpur 16 www.β) ωRC (12.www.25) ∴ vo = vo β e = 2VL ωRC 1+ ω2 R 2 C 2 e - (ωt .26) at ωt = α + π/3 v o = 2VL ωRC 1+ ω2 R 2 C 2 e π/6 .27) Also at ωt = α + π/3 π⎞ ⎛ v o = 2VL sin ⎜ ωt .

2. However. Kharagpur 17 www. The input current distortion factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very ________. (iv) unity. (v) high.28) From which the value of α can be found. This is a major disadvantage of this converter.com ∴ sinα = ωRC 1+ ω R C 2 2 2 1 π/6 . Answers: (i) discontinuous. The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very high. The current ii can be made continuous by connecting an inductor of appropriate value between the rectifier and the capacitor.www.α + tan -1 ωRC e ωRC (12.3 Fill in the blank(s) with the appropriate word(s) i) ii) iii) iv) v) A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in the _________ conduction mode. π Exercise 12.3 (b). Answers: The following figure shows the circuit arrangement and the corresponding waveforms. Assuming the capacitor to be large enough so that the output voltage is almost ripple free. Analysis of such a converter is similar to a converter V supplying an R – L – E load where the value of E is 3 2 L . The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very low.jntuworld. A three phase full wave rectifier operates from 220 volts. (iii) current. (ii) voltage.jntuworld. It is observed that ii is discontinuous and contains large ripple. The input current displacement factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is ___________.23 gives the expression of the output current ii of the rectifier. Calculate the value of the inductor so that the rectifier output current is continuous.com . An inductor of negligible resistance is inserted between the rectifier and the capacitor. Version 2 EE IIT. This ripple is also reflected in the input current of the rectifier as shown in Fig 12. the displacement factor of the converter still remains unity. three phase 50 Hz supply and supplies a capacitive resistive load of 20 Amps. Equation 12.

Kharagpur 18 www.jntuworld.com .73º V0 = VL and sinθ = π 2VL π In the interval π 2π ≤ ωt ≤ 3 3 di v0 + L L = 2VL sinωt dt 3 2 VL π Since v0 is almost ripple free v0 = V0 = ∴ Now di 3 2 VL + ωL L = 2VL sinωt π dωt 2VL 3 2 i L = I0 cosωt VL ωt ωL πωL i L av = 20A Version 2 EE IIT.com Since the conduction is continuous V0 3 3 2 = or θ = 72.jntuworld.www.

The input ac current of a three phase full bridge rectifier contain only odd harmonics but no dc component or triplen harmonics.com ∴ ∴ I0 - 3VL 3 2 1 π2 3 VL × × × = 20A or I 0 = 20 + πωL 2 3 π 2ωL 2VL ⎡ 3 3 ⎤ ⎢ 2 . Applications and Design”. i L = 20 + References [1] [2] “Power Electronics”. John Willey and Sons Ine. The input displacement factor of the three phase bridge rectifier is always unity. Undeland. Sen. 1995. three phase bridge converter require smaller inductor to obtain the same output current ripple factor. Third Edition. Three phase full wave uncontrolled rectifier is most widely used in the medium power applications particularly as the input stage of the dc link inverter.C.www.π ωt ⎥ ωL ⎣ ⎦ For just continuous conduction iL = 0 at ωt = θ 2VL ⎡ 3 3 ⎤ 0 = 20 + ∴ ⎢ 2 . The output voltage of a three phase full bridge rectifier contains multiplies of 6th harmonic of input cycle. Version 2 EE IIT.28 mH. Three phase uncontrolled half wave rectifier require three phase four wire power supply. Converters.cosθ . 2003. Compared to single phase rectifiers. Full bridge rectifier does not require neutral connection. P.π θ ⎥ ωL ⎣ ⎦ or ωL = 1.0306 Ω or L = 3.com .jntuworld. Mohan. Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half wave rectifier. “Power Electronics. Tata MC Grawhill publishing company limited. The input ac line current in a three phase uncontrolled half wave rectifier contain dc component which may cause “dc saturation” of input transformer. Three phase full bridge converter supplying an R – L – E load usually operate in the continuous conduction mode.cosωt . Lesson Summary • • • • • • • • • • • Three phase uncontrolled rectifiers are available in half wave and full wave configuration. Robbins.jntuworld. Kharagpur 19 www.

A three phase full wave rectifier supplies a resistive capacitive load of 50 Amps from a 220 V. Q3.01 volts 3 4π Version 2 EE IIT. Find out the value of the load capacitance such that the load voltage ripple is less than 5 %. Practice Problems and Answers Q1.55 volts 2π 2π 2 2 V0AV ⎛ 148. 50 Amps separately excited dc motor. Find out the turns ratio of the transformer so that the motor operates at rated speed at full load.com • • Three phase bridge rectifier supplying a capacitive load has very good output voltage form factor but very poor input current THD. Since the load current is ripple free the power consumed by the load will be PL = I Now ∴ 2 0AV R LOAD 2 V0AV = R LOAD V0AV = 3 2VL 3 2 × 220 = = 148. 3 phase 50 Hz supply.jntuworld. Answers to practice problems 1.M. Kharagpur 20 www.P.2) V0RMS = 1 3 + VL = 151.5 Ω find out the inductance to be connected in series with the motor such that the rectifier operates in the continuous conduction mode at 50 % of the full load torque.55 ⎞ PL = =⎜ ⎟ ×1 KW = 551.7 watts R LOAD ⎝ 200 ⎠ When the inductor is shorted 2 V0RMS PL = R LOAD Now from Equ.jntuworld. (12. Q2. If the motor armature resistance is 0. 50 Hz supply and supplies a resistive load rated at 200 Volts 1 KW through an inductance large enough to make the load current ripple free.com . A three phase half wave rectifier operates from a three phase 220 V. Find out the power consumed by the load? What will be the load power if the inductor is shorted? A three phase full wave rectifier operates from a three phase 220 V 50 Hz supply through a three phase Δ/Y transformer and supplies a 200 V 1500 R.www. Compared to single phase converters three phase bridge rectifier require smaller capacitor to obtain a given output voltage form factor.

φ) - sinθ =0 cosφ ( π/3 . ∴ VL = 148.1 volts π Where VL is the secondary line voltage. Secondary is star connected. i0 = At the junction of continuous and discontinuous conduction i 0 Min = i 0 ωt = θ = 0 ∴ sinφ 1. 187.jntuworld.0.2φ) = sinθ π 2 2 2 1.5 volts 3 Primary is delta connected.5×50 At 50% of full load torque the motor operates in the continuous conduction mode.01 ⎞ PL = =⎜ ⎟ ×1 KW = 570 watts R LOAD ⎝ 200 ⎠ 2 2.2154 rad.5 ×1500 = 1607 RPM .5 Volts.jntuworld.e 3tanφ Version 2 EE IIT.θ ) 1 sin2φe tanφ 1 1 + sinθ .www.5 × 25 = 187. with reference to Fig. Kharagpur 21 www.9375 Where sinθ = 200 2VL θ = 69.2 and equation 12.64º = 1. So secondary phase voltage V0AL = V2 = VL = 85.e OR π 3tanφ e - ( θ-π/3) tanφ + sin(θ .sin(θ .19.e ⎦ E 187.φ) π z ⎢ cosφ ⎥ 3tanφ ⎣1. ∴ 3 2 VL = 200 volts.com . ωt-π/3 ⎡ ⎤ 2VL ⎢ sinφ . To run at rated speed at full load the motor terminal voltage must be 200 volts.com ∴ 2 V0RMS ⎛ 151.5 = = 0. So primary phase voltage V1 = 220 V V ∴ Required turns ratio = 1 = 1: 0. ∴ speed at 50% of full load torque = 200 . 12.38865 2 At 50% of the full load torque motor current is 25 Amps ∴ back Emf = 200 – 0.tanφ sinθ ⎥ e + sin(ωt .

e Solving which φ = 34.025 1+ V0Min /V0Max V0Min /V0Max = 0.2φ) = sinθ 1.47 V. 12.06116 1 ∴ R = 6.θ ) OR sin2φ e tanφ π 3tanφ .0694 Ω ωRC = = 16.28) ⎠ sinα = cosφ e ⎝ 6 1 where tanφ = ωRC from which φ = 3. Kharagpur 22 www.05 V0Max + V0Min V0AV 1.V0Min ∴ ˆ 2 ( V0Max + V0Min ) V0pp = = 0.6911 R ∴ ωL = 0.35 .943 Volts ∴ V0AV = 303.com .6938.jntuworld.V0Min /V0Max = 0.5º ∴ tanφ = 0.9512 or α = 72º But from Equation (12.sin(θ . tanφ ∴ ωC = 2. V0Min occurs at ωt = α ∴ V0Min = 2VLsinα = 295.jntuworld. ∴ R = 6.1 mH.0694 Ω. ∴ V0Min = 295.www.65º. I0AV = 50 Amps From Fig. ∴ ∴ V0Max = 2VL = 2 × 220 V = 311 volts From Fig. ωL ∴ = tanφ = 0.3456 Ω or L = 1.com ( π/3 . 3.943 ∴ sin α = 0. 12. Assuming linear ripple V0AV = ˆ V0pp V0Max + V0Min 2 = V0Max .3.3. ∴ C = 8575 μF.α+φ ⎟ Version 2 EE IIT.9512 . ⎛π ⎞ tanφ ⎜ .

jntuworld. Kharagpur 1 www.www.com Module 2 AC to DC Converters Version 2 EE IIT.jntuworld.com .

jntuworld.com Lesson 13 Operation and Analysis of the Three Phase Fully Controlled Bridge Converter Version 2 EE IIT. Kharagpur 2 www.com .www.jntuworld.

www. Design the triggering circuit of the three phase fully controlled bridge converter. distortion factor and the power factor of the input current as well as its harmonic spectrum.jntuworld. RMS valves and the harmonic spectrum of the output voltage / current waveforms of the converter. Find out the average. Find out the displacement factor.com . Analyze the operation of higher pulse number converters and dual converter. Version 2 EE IIT. Kharagpur 3 www.com Instructional Objectives On completion the student will be able to • • • • • • Draw the circuit diagram and waveforms associated with a three phase fully controlled bridge converter. Find out the closed form expression of the output current and hence the condition for continuous conduction.jntuworld.

Kharagpur 4 www. Since the frequency of the harmonic voltage is higher smaller load inductance leads to continuous conduction. 13. The control circuit become considerably complicated and the use of coupling transformer and / or interphase reactors become mandatory. In phase controlled rectifiers though the output voltage can be varied continuously the load harmonic voltage increases considerably as the average value goes down.com 13.jntuworld. The same circuit while operating in the inverter mode requires load side counter emf. 13. In this lesson the operating principle and characteristic of this very important converter topology will be discussed in source depth. Three phase circuits are preferable when large power is involved.2 Operating principle of 3 phase fully controlled bridge converter A three phase fully controlled converter is obtained by replacing all the six diodes of an uncontrolled converter by six thyristors as shown in Fig. cycloconverter drives. However in very high power application (such as HV dc transmission system. The displacement angle of the input current increases with firing angle. The frequency of the harmonic voltage and current can be increased by increasing the pulse number of the converter which can be achieved by series and parallel connection of basic 6 pulse converters. This method is known as phase control and converters are also called “phase controlled converters”.www. Since thyristors can block voltage in both directions it is possible to reverse the polarity of the output dc voltage and hence feed power back to the ac supply from the dc side. Under such condition the converter is said to be operating in the “inverting mode”. The thyristors in the converter circuit are commutated with the help of the supply voltage in the rectifying mode of operation and are known as “Line commutated converter”.1 (a) Version 2 EE IIT. With the introduction of high power IGBTs the three phase bridge converter has all but been replaced by dc link voltage source converters in the medium to moderately high power range. Control over the output dc voltage is obtained by controlling the conduction interval of each thyristor.jntuworld.com .) the basic B phase bridge converter block is still used. Input current wave shape become rectangular and contain 5th and higher order odd harmonics. static scherbius drives etc. The controlled rectifier is obtained by replacing the diodes of the uncontrolled rectifier with thyristors.1 Introduction The three phase fully controlled bridge converter has been probably the most widely used power electronic converter in the medium to high power applications. for commutation and are referred to as the “Load commutated inverter”. Of course the magnitude of harmonic voltage is lower in three phase converter compared to the single phase circuit. load commutated inverter synchronous motor drives. The controlled rectifier can provide controllable out put dc voltage in a single unit instead of a three phase autotransformer and a diode bridge rectifier.

Kharagpur 5 www.jntuworld.jntuworld.com .com Version 2 EE IIT.www.

T3. If the converter firing angle is α each thyristor is fired “α” angle after the positive going zero crossing of the line voltage with which it’s firing is associated. Fig. The next section will analyze the operation of this converter in more details. T6T1.1 (c). Once the conduction diagram is drawn all other voltage waveforms can be drawn from the line voltage waveforms and from the conduction table of fig. T4T5. 13. Kharagpur 6 www.1 (b). 13.1 (b) shows voltage across different devices and the dc output voltage for each conduction interval.1 (a)). Each of these line voltages can be associated with the firing of a thyristor with the help of the conduction table-1. T2T3.jntuworld. Version 2 EE IIT.2 shows the waveforms of different variables (shown in Fig. The phasor diagram of Fig. The input current on the other hand contains only odds harmonics of the input frequency other than the triplex (3rd.com . Therefore T1 is fired α angle after the positive going zero crossing of vac. The conduction table of Fig.jntuworld. Each conduction mode is of 60° duration and appears in the sequence mentioned.1 (c). 13. Therefore thyristors on the same phase leg are fired at an interval of 180° and hence can not conduct simultaneously. The phasor diagram of the line voltages appear in Fig. 13. During this period the voltage across T1 was vac.) harmonics. 9th etc. To arrive at the waveforms it is necessary to draw the conduction diagram which shows the interval of conduction for each thyristor and can be drawn with the help of the phasor diagram of fig. Then from symmetry consideration it can be argued that each thyristor conducts for 120° of the input cycle. It can be argued as in the case of an uncontrolled converter only one device from these two groups will conduct. T5T6. This leaves only six possible conduction mode for the converter in the continuous conduction mode of operation. 13. T5) and one from the bottom group (T2.1 (c) also confirms that all the thyristors are fired in the correct sequence with 60° interval between each firing. For example the thyristor T1 is fired at the end of T5T6 conduction interval. Similar observation can be made about other thyristors.www. T4. T6) must conduct. Similarly line currents can be drawn from the output current and the conduction diagram. It is clear from the waveforms that output voltage and current waveforms are periodic over one sixth of the input cycle. These are T1T2. Therefore this converter is also called the “six pulse” converter. Now the thyristors are fired in the sequence T1 → T2 → T3 → T4 → T5 → T6 → T1 with 60° interval between each firing. T3T4.com For any current to flow in the load at least one device from the top group (T1. 13. 13.

www. Version 2 EE IIT.jntuworld.1 Fill in the blank(s) with the appropriate word(s) i) The three phase fully controlled bridge converter is obtained by replacing six _________ of an uncontrolled converter by six __________.com Exercise 13.jntuworld.com . Kharagpur 7 www.

viii) The input ac current of a three phase fully controlled converter contains only _________ harmonics but no _________ harmonic. (ii) six.1) π α+ 3 α+ π 3 2 π⎞ ⎛ 3 v0 dωt = VL ∫ 3 sin ⎜ ωt + ⎟ dωt ∫α α π π 3⎠ ⎝ 3 2 VL cosα π (13.jntuworld. vi) The peak voltage appearing across any device of a three phase fully controlled converter is equal to the ________ input ac ________ voltage.www. (vii) six. (v) line. (iii) 120. Kharagpur 8 www. iv) In a three phase fully controlled converter operating in continuous conduction there are ________ different conduction modes. iii) In a three phase fully controlled converter each device conducts for an interval of __________ degrees. (viii) odd.1 Analysis of the converter in the rectifier mode The output voltage waveform can be written as v0 = V0 + V0 = = K=1. (x) rare. (iv) six. 13.2 ∑V α BK sin 6 Kωt (13. line. v) The output voltage of a three phase fully controlled converter operating in the continuous conduction mode consists of segments of the input ac ________ voltage. Answers: (i) diodes.3) Version 2 EE IIT. (vi) peak. ix) A three phase fully controlled converter can also operate in the _________ mode. vii) The input ac current of a three phase fully controlled converter has a ________ step waveform. thyristors.com .2 ∑V α AK cos 6 Kωt + K=1. (ix) inverting.com ii) The pulse number of a three phase fully controlled bridge converter is _________.jntuworld. tripler.2. x) Discontinuous conduction in a three phase fully controlled converter is _________.2) VAK 6 α+ π = ∫ 3 v0 cos6 Kωt dωt π α 6 α+ π π⎞ ⎛ = ∫ 3 2 VLsin ⎜ ωt + ⎟ cos6 ωt dωt π α 3⎠ ⎝ = 3 2 ⎡ cos(6K +1)α cos(6K -1)α ⎤ VL ⎢ π 6K -1 ⎥ ⎣ 6K +1 ⎦ (13.

Version 2 EE IIT.4) 1 V0RMS = 3 π ∫α α+ π 3 ⎡ 3 3 ⎤2 2 v0 dωt = VL ⎢1+ cos2α ⎥ 4π ⎣ ⎦ The input phase current ia is expressed as ia = i0 ia = . Kharagpur 9 www. i.7) ∴ I An = ( -1) 2 3I 0 π⎞ ⎛ sin ⎜ Kπ ± ⎟ cos ( 6K ±1) α 2⎠ ( 6K ±1) π ⎝ (13. the load is highly inductive. 1. IAn = 0 otherwise.2 it can be observed that i0 itself has a ripple at a frequency six times the input frequency. This approximation will be valid provided the ripple on i0 is small. However. considerable simplification in the expression of ia can be obtained if i0 is replaced by its average value I0.jntuworld. The closed from expression of i0.e. 2.i0 ia = i0 α ≤ ωt ≤ α + α+ π 3 ia = 0 2π 4π ≤ ωt ≤ α + 3 3 5π α+ ≤ ωt ≤ α + 2π 3 otherwise From Fig. 13.6) (13..jntuworld. The modified input current waveform will then be ia which can be expressed in terms of a fourier series as α α ˆ = I A0 + I cos nωt + I sin nωt i a ≈ ia ∑ An ∑ Bn 2 n=1 n=1 (13. 3 .com . K = 0. as will be seen later is some what complicated...5) Where I A0 = I An 1 α+2π i a dωt = 0 2π ∫α 1 α+2π = ∫ i a cos nωt n≠0 π α 4I nπ nπ = 0 cos sin cos nα nπ 6 2 K (13.8) for n = 6K ±1.com VBK = 6 α+ π ∫α 3 v0 sin6 Kωt dωt π 6 α+ π π⎞ ⎛ = ∫ 3 2 VLsin ⎜ ωt + ⎟ sin6 ωt dωt α π 3⎠ ⎝ = 3 2 ⎡ sin(6K +1)α sin(6K -1)α ⎤ VL ⎢ π 6K -1 ⎥ ⎣ 6K +1 ⎦ (13.www.

(13... 13. 2.α ) π v an = 2VL cos ωt 3 (13.com I Bn = 1 α+2π i a sin nωt dωt π ∫α 4I nπ nπ = 0 cos sin nα sin nπ 6 2 K (13.11) ( -1) 2 3I0 sin ⎛ Kπ ± π ⎞ cos ⎡ 6K ±1 ωt .α ⎤ ia = ∑ )( )⎦ ⎜ ⎟ ⎣( 2⎠ ⎝ K =0 ( 6K ±1) π in particular ia1 = fundamental component of ia = 2 3 I0 cos ( ωt .2) tanφ ( ωt . Kharagpur 10 www.10) for n = 6K ±1.9) ∴ I Bn = ( -1) 2 3I 0 π⎞ ⎛ sin ⎜ Kπ ± ⎟ sin ( 6K ±1) α 2⎠ ( 6K ±1) π ⎝ (13.14) (13.2 (13.15) 3 cosα π ∴ displacement angle φ = α. . E = 2VLsinθ (from Fig.α ) + (13. tanφ = R R = Zcosφ. IBn = 0 ∴ α K otherwise.17) (13.jntuworld. ∴ displacement factor = cosα ⎛ 6⎞ I distortion factor = a1 = ⎜ ⎟ Ia ⎝ π ⎠ I0 2 3 I0 = 3 π ∴ Power factor = Displacement factor × Distortion factor = (13.com .jntuworld. 1..12) From Fig.φ ⎟ Z 3 ⎠ R ⎝ ωL Z = R 2 + ω2 L2 .13) (13.www. K = 0. 13.19) Version 2 EE IIT.18) Where ∴ 2VL π ⎞ E ⎛ sin ⎜ ωt + .16) The closed form expression for i0 in the interval α ≤ ωt ≤ α + in this interval di π⎞ ⎛ Ri 0 + L 0 + E = v0 = 2VLsin ⎜ ωt + ⎟ dt 3⎠ ⎝ i 0 = I1e π can be found as follows 3 (13.

α ) . The converter in that case is said to be operating in the inverter mode. π then i0 is minimum at ωt = α.φ ⎟ .α ) + ⎡ ⎛ π ⎞ sinθ ⎤ ⎢sin ⎜ ωt + 3 .20) i 0 ωt=α = i 0 ωt =α+ π ∴ I1 + = I1e - (13.22) ∴ (ω t .com .jntuworld.3 shows the circuit connection and wave forms in the inverting mode of operation where the load current has been assumed to be continuous and ripple free.cosφ ⎥ ⎠ ⎣ ⎝ ⎦ + OR I1 = 2VL sin ( φ .2.e 3tanφ (13. 13.α ) ⎡ ⎤ 2VL ⎢ sin ( φ . In all the analysis presented so far it has been assumed that α < 90°.www. Version 2 EE IIT. It follows from equation 13.φ ⎟ π Z ⎢ 3 ⎠ cosφ ⎥ ⎝ 3tanφ ⎣ 1. This is the rectifier mode of operation of the converter.e ⎦ (13.φ ⎟ .α ) π Z 1.tanφ π ⎞ sinθ ⎥ ⎛ i0 = e + sin ⎜ ω t + .23) To find out the condition for continuous conduction it is noted that in the limiting case of continuous conduction. ∴ Condition i 0 min=0 .cosφ ⎥ ⎠ ⎣ ⎝ ⎦ 2VL Z ⎡ ⎛ 2π ⎞ sinθ ⎤ ⎢sin ⎜ α + 3 . However if α is made larger than 90° the direction of power flow through the converter will reverse provided there exists a power source in the dc side of suitable polarity. Kharagpur 11 www. 13.φ ⎟ . Now if θ ≤ α + 3 for continuous conduction is i0 ωt=α ≥ 0 .jntuworld.2 that the output dc voltage will be positive in this case and power will be flowing from the three phase ac side to the dc side.com ∴ 2VL Z Since i0 is periodic over π/3 i 0 = I1e tanφ ( ωt . However discontinuous conduction is rare in these conversions and will not be discussed any further. 13. Fig.2 Analysis of the converter in the inverting mode.1(a)] would have to be reversed for inverter mode of operator.21) 3 2VL Z π 3tanφ ⎡ ⎛ π ⎞ sinθ ⎤ ⎢sin ⎜ α + 3 . It has been explained in connection with single phase converters that the polarity of EMF source on the dc side [Fig.cosφ ⎥ ⎠ ⎣ ⎝ ⎦ (13.

com .jntuworld. Kharagpur 12 www.jntuworld.www.com Version 2 EE IIT.

The input supply current Fourier series is also identical to Equation 13. The same expressions hold for the dc and harmonic compounds in the output voltage and current.jntuworld.com .www.25) Version 2 EE IIT.α) π V0 = (13. Kharagpur 13 www.24) (13.com Analysis of the converter in the inverting mode is similar to its rectifier mode of operation.jntuworld.8. In particular 3 2 VL cosα π 2 3 i a1 = I0 cos(ωt .

For successful commutation of the outgoing thyristor it is essential that this interval is larger than the turn off time of the thyristor i. 50 Hz supply is used to charge a battery bank with nominal voltage of 240 V.jntuworld.www. 13.3(b)) after commutation is impressed with a negative voltage of duration β = π – α.com For values of α in the range 90° < α < 180° it is observed from Fig. 13.1 × VB Nom = 264 volts respectively. The battery bank has an internal resistance of 0.01 = 265 volts V0 Min = VB Min + 100 × RB = 216 + 100 × 0.88º α Max = 43. The range of charging efficiency.01 = 217 volts.α ≥ ωtq or α ≤ π . Assuming continuous conduction find out. Kharagpur 14 www.08º (ii) Input power factor is maximum at minimum α and vice versa Version 2 EE IIT.9 × VB Nom = 216 volts and VB Max = 1. Since the average charging current is constant at 100 A. β ≥ ωtq . Answer: The maximum and minimum battery voltages are.jntuworld. VB Min = 0. When the battery bank is charged with a constant average charging current of 100 Amps through a 250 mH lossless inductor. 13. Which imposes an upper limit on the value of α. (i) But V0 Max = 3 2 VL cos α Min π V0 Min = 3 2 VL cos α Max π ∴ ∴ α Min = 26. V0 Max = VB Max + 100 × RB = 264 + 100 × 0.3(b) that an outgoing thyristor (thyristor T6 in Fig. In practice this upper value of α is further reduced due to commutation overlap.com .2 1. It is observed form Fig.01 Ω and the battery bank voltage varies by ± 10% around its nominal value between fully charged and uncharged condition.3(b) that the average dc voltage is negative and the displacement angle φ of the fundamental component of the input ac line current is equal to α > 90°. tq is the thyristor turn off time Therefore π . (i) (ii) (iii) The range of firing angle of the converter.e. A three phase fully controlled bridge converter operating from a 3 phase 220 V. Therefore. power in the ac side flows from the converter to the source.ωtq . The range of ac input power factor. Exercise 13.

50 Hz supply through a Y/Δ transformer to supply a 220 V. ∴ P0 = I0 × VB Max = 26400 watts. Assume continuous conduction.017 Amps.jntuworld. The same converter is now used to brake the motor regeneratively in the reverse direction. If the thyristors are to be provided with a minimum turn off time of 100 μs.48 V.f. What should be the transformer turns ratio such that the converter produces rated motor terminal voltage at 0º firing angle.com .017) 2 = 10000.com ∴ p.f... Kharagpur 15 www. Answer: From the given question 3 2 V = 220 ∴ VL = 162. Version 2 EE IIT.jntuworld.15 V..697 π Max = 3 × cos α min = 0.073) 2 + (0.. 2 J 0RMs ≈ 1002 + (0. The motor has an armature resistance of 0. what is the maximum reverse speed at which rated braking torque can be produced. ∴ 2 2 I0RMs ≈ I 0 Ploss = 100 watts P0 = I0 × VB Min = 21600 watts. and I K ≈ 6KωL 6 2KωL 2 0 2 1 2 2 For α = α Min VA1 = 0..85 π (iii) 2 Power loss during charging = I0RMs R B But I 2 0RMs 2 2 VAK + VBK VK = = I + I + I + .02 Ω. ∴ ∴ VB1 = 48.00562 Ploss = 100 watts.. 26400 = 99. 500 A separately excited dc motor.9 V π L Where VL is the secondary side line and also the phase voltage since the secondary side is Δ connected. ∴ Charging efficiency = 21600 = 99.www. VB2 = 20. I1 = 0. max = Distortion factor × Displacement factor p.439 V.. VA2 = 10.6% 26400 + 100 Charging efficiency = Similarly for α Max.76. 600 rpm. Min = 3 × cos α Max = 0.54% 21600 + 100 2. At α Min. A three phase fully controlled converter operates from a 3 phase 230 V.073 Amps I2 = 0.

tq Min = 100μS ∴ β Min = ωtq Min = 1.2o = .229.89 × 600 = 656.www. ∴ Max reverse speed is 229. Kharagpur 16 www. 210 13.com . At 600 RPM Eb = 220 – 500 × 0.02 = 210 V.89 V π L For rated braking torque Ia = 500 A ∴ Eb = Va – Iara = .3 Higher pulse number converters and dual converter The three phase fully controlled converter is widely used in the medium to moderately high power applications. ∴ Turns ratio = 162.com Primary side phase voltage = 230 V = 132.219. 5th and 7th in the ac side) harmonic voltages and currents produced by this converter become unacceptable.2º ∴ Maximum negative voltage that can be generated by the converter is 3 2 V cos 178. Also the relatively low frequency (6th in the dc side.9 During regenerative braking in the reverse direction the converter operates in the inverting mode.8o ∴ α Max = 180 – β Min = 178.79 V 3 132.83 RPM . However in very large power applications (such as HV DC transmission systems) the device ratings become impractically large.79 = 1:1.89 V.jntuworld. Version 2 EE IIT.2267 . Therefore several such converters are connected in series parallel combination in order to increase the voltage / current rating of the resulting converter. Furthermore if the component converters are controlled properly some lower order harmonics can be eliminated both from the input and output resulting in a higher pulse converter.jntuworld.

4(a) schematically represents series connection of two six pulse converters where as Fig. Then one can write ∞ α 3 2 v 01 = VL cosα + ∑ VAK cos 6 Kωt + ∑ VBK sin 6 Kωt (13.jntuworld. In both these figures CONV – I and CONV – II have identical construction and are also fired at the same firing angle α.4(b) can be considered to be a parallel connection. Kharagpur 17 www. 13. The inductance in between the converters has been included to limit circulating harmonic current.www.jntuworld. Their input supplies also have same magnitude but displaced in phase by an angle φ.com .com Fig. 13.26) π K=1 K=1 Version 2 EE IIT.

36ω ……….φ ) ⎤ ⎣ ⎦ K=1 (13. Thus the two converters taken together can operate in all four quadrants and is capable of supplying a four quadrant dc motor drive.www. 24ω.5 (a). In particular if φ = 30° then cos 3Kφ = 0 for K = 1. 5……. 2. Which is the characteristic of a 12 pulse converter. This problem is easily mitigated by connecting another three phase fully controlled converter in anti parallel as shown in Fig.4(c).28) Now if cos 3Kφ = 0 for some K then the corresponding harmonic disappear from the fourier series expression of v0.com . One of the shortcomings of a three phase fully controlled converter is that although it can produce both positive and negative voltage it can not supply current in both directions. 23ω. Similarly it can be shown that the input side line current iABC have harmonic frequency of the form 11ω. 13ω. Version 2 EE IIT. Then v0 = α 6 2 VL cosα + 2∑ [ VAm cos 12mωt + VBm sin 12mωt ] π m=1 (13. In other words converterI operates in the first and fourth quadrant of the output v – i plane whereas converter-II operates in the third and fourth quadrant.29) It can be seen that the frequency of the harmonics present in the output voltage has the form 12ω. 37ω. In a similar manner more number of 3 phase 6 pulse converters can be connected in series / parallel and the φ angle can be adjusted to obtain 18 and 24 pulse converters.jntuworld.com v02 = α α 3 2 VL cosα + ∑ VAK cos 6 K ( ωt . some applications such as a four quadrant dc motor drive require this capability from the dc source. ………….27) Therefore for Fig 13. However. The combined converter is called the Dual converter. In this figure converter-I supplies positive load current while converter-II supplies negative load current. 35ω.φ ) + ∑ VBK sin 6 K ( ωt .φ ) π K=1 K=1 (13.jntuworld.4(a) v 0 = v01 + v02 = α 6 2 VL cosα + π 2∑ cos3Kφ ⎡ VAK cos3K ( 2ωt . 25ω.φ ) + VBK sin3K ( 2ωt . 13. This phase difference can be obtained by the arrangement shown in Fig.. 3. 13. Kharagpur 18 www.

This requires that the firing angles of these two converters be related as α2 = π – α 1 (13.jntuworld.30) Version 2 EE IIT.com Obviously since converter-I and converter-II are connected in antiparallel they must produce the same dc voltage.com .www. Kharagpur 19 www.jntuworld.

jntuworld. To overcome this problem an interphase reactor may be incorporated between the two converters.www.30 ensures that the dc voltages produced by these converters are equal the output voltages do not match on an instantaneous basis.31) (13.4 Gate Drive circuit for three phase fully controlled converter Several schemes exist to generate gate drive pulses for single phase or three phase converters. Therefore to avoid a direct short circuit between two different supply lines the two converters must never be gated simultaneously. With the interphase reactor in place both the converters can be gated simultaneously with α2 = π – α1.com . Version 2 EE IIT. Converter-I receives gate pulses when the load current is positive. The resulting converter is called the circulating current type dual converter. In either single or three phase converters V0 ∝ cosα or α = cos-1 V0 K1 To get V0 ∝ v c α = cos -1 Vc K (13. Thus there is no circulating current flowing through the converters and therefore it is called the non-circulating current type dual converter. This can be achieved as follows.jntuworld.com Although Equations 13. Kharagpur 20 www.32. 13. Gate pulses to converter-II are blocked at that time. For negative load current converter-II thyristors are fired while converter-I gate pulses are blocked.32) The following circuit can be used to generate “α” according to equation 13. It requires precise sensing of the zero crossing of the output current which may pose a problem particularly at light load due to possible discontinuous conduction. In many application it is required that the output of the converter be proportional to a control voltage.

jntuworld. Kharagpur 21 www.com . The phasor diagram of the phase shift circuit is shown in Fig.jntuworld.com In the circuit of Fig. The firing pulse is generated at the point when these two waveforms are equal. The output of the phase shift network is called carrier waveform.www. 13.6(b). Version 2 EE IIT.7.33) Therefore this method of generation of converter firing pulses is called “inverse cosine” control. Similar technique can be used for three phase converters.6(a) a phase shift network is used to obtain a waveform leading vi by 90º. Obviously at-this instant vc ∝ Vs cosα or α = cos-1 vc Vs (13. 13. However the phase shift network here consists of a three phase signal transformer with special connections as shown in Fig. 13. The output of the phase shift waveform (and its inverse) is compared with vc.

com Version 2 EE IIT.jntuworld. Kharagpur 22 www.www.jntuworld.com .

The primary windings are connected in delta while the secondary windings are connected in zigzag.com The signal transformer uses three single phase transformer each of which has two secondary windings. This waveform is obtained from zigzag connection of the winding segments a1a2 and c1c2 as shown in Fig.6 (a). The voltage across each zigzag phase can be used to fire two thyristors belonging to the same phase leg using a circuit similar to Fig. 13.www. Therefore. Version 2 EE IIT. The phase shift network will not be required in this case. Kharagpur 23 www. 13.jntuworld. From Fig. to implement inverse cosine the carrier wave for T2 must lead vbc by 90º. 13.com . The same figure also shows the zigzag connection for other phase.7(a).1 (c) T2 is fired α angle after the positive going zero crossing of vbc.jntuworld.

Answer: i) The output voltage = 3 2 × 400 cos 70o = 184. ix) To obtain a linear control relation between the control voltage and the output dc voltage of a converter ___________ control logic is used. (vii) non-circulating . (viii) inductor.jntuworld. (ix) inverse-cosine. (x) delta-zigzag.α. parallel. iv) The input supply to a 12 pulse converter can be obtained through a _________ connected transformer. (iii) equal. Assume continuous conduction. viii) In a circulating current type dual converter an __________ is used between the converters to limit the circulating current. Fill in the blank(s) with the appropriate word(s) i) Higher pulse number converters can be realized by __________ and _______ connection of six pulse converters. vi) In a dual converter if one converter is fired at an angle ‘α’ the other has to be fired at _________. ii) What should be the firing angle in the regenerative braking mode when the motor delivers half the rated torque at 600 rpm. (vi) π .7 V π Version 2 EE IIT. (iv) star – star – delta. A 220V. x) In a three phase fully controlled converter the carrier waves for firing pulse generation are obtained using three ___________ connected single phase transformers. The armature is fed from a three phase non circulating current dual converter. 750 RPM.com Exercise 13. 200A separately excited dc motor has an armature resistance of 0. ii) Constituent six pulse converters of a 12 pulse converter have _________ firing angles. (ii) same.www. Supply voltage is 400 V. 30.3 1. Answers: (i) Series. Kharagpur 24 www. v) Dual converters are used for supplying ________ quadrant dc motor drives.com . If the forward converter operates at a firing angle of 70º i) At what speed will the motor deliver rated torque.05 Ω. iii) The input supply voltages to the converters of a 12 pulse converter have ________ magnitudes and are phase shifted from one another by _________ degrees. (v) four.jntuworld. 2. vii) In ___________ current dual converter only one converter conducts at any time.

Hence inverse casine control law cannot be implemented.www. Robbins. 2003. Version 2 EE IIT.7 – 200 × 0.jntuworld. Operating speed = 174.600 × 210 = -168V1 Ia = 100A 750 Va = . References 1. Answer: With delta-double star connection of the signal transformers the carrier wave forms will be in phase with the line voltage waveforms. without a phase shift network it will not be possible to generate carrier waveforms which are in quadrature with the line voltages. “Power Electronics”. Mohan.Eb + Iara = – 173 r.jntuworld.67º Va = . Sen.05 = 174. Undeland.173 = 3 2 400 cos α π 3. John Willey and Sons Inc. What will happen if the signal transformers generating the carrier wave have delta – double star connection instead of delta-zigzag connection.com ∴ ∴ ii) E b ∴ Eb = Va – Iara = 184.05 × 200 600RPM = .75 × 750 = 624 RPM . “Power Electronics. 1995.0. 220 . Therefore. Third Edition. Converters. Kharagpur 25 www.C. ∴ α = 108. P. Tata-McGrawhill publishing company limited.com . Applications and Design”. 2.75 V.

jntuworld. Kharagpur 26 www.com Lesson Summary • • • • • • • • • A three phase fully controlled converter is realized by replacing the diodes of an uncontrolled converter with thyristors. The input current of a three phase fully controlled converter contains only odd harmonics other than tripler harmonics. The output voltage of a three phase fully controlled converter contains multiple of sixth harmonic of the input frequency in addition to the dc component. The input current displacement factor of a three phase fully controlled converter is cos α.www. A three phase fully controlled converter can operate either as a rectifier or as an inverter. In the continuous conduction mode a three phase fully controlled converter may operate in the inverting mode by increasing α beyond 90º. 18. Several units of three phase fully controlled converters can be connected in series parallel to form higher pulse number (12. In the inverting mode the firing angle should be less than 180º for safe commutation of the thyristors. a three phase delta/zig-zag connected signal transformer is used to generate the required carrier waves for this purpose. • • • Version 2 EE IIT. In higher pulse number converters all component converters are fired at the same firing angle while their input supplies are phase shifted from one another by a predetermined angle. 24 etc) converters.jntuworld. Fully controlled converters employ “inverse casine control” strategy for generating firing pulses which gives linear relationship between the output voltage and the control voltage. Dual converters can be of circulating and non circulating current type. In a three phase fully controlled converter. α being the firing angle.com . Two three phase fully controlled converter can be connected in anti parallel to form a dual converter which can operate in all four quadrants of the V-I plane.

A three phase fully controlled converter supplies a 220 V 1500 RPM. 3 phase. Kharagpur 27 www. Find out the power supplied to the load. 50 A separately excited dc motor from a 230 V. 3. The motor holds an overhauling load at 1000 RPM while producing full load torque.2 Ω. The motor has an armature resistance of 0. Answers 1. Since the load is resistive the load current becomes zero when the voltage becomes zero. The figure above shows the output voltage with α = 90º and a resistive load. A three phase fully controlled converter operates from a 3 phase 230 V. 2. Both the voltage and amount remains zero thereafter till the next thyristor is fired.jntuworld. 50 Hz supply and supplies a resistive load of 25 Ω at a firing angle 90º. 50 Hz supply. What precaution should be taken in the gate drive circuit so that a three phase fully controlled converter can continue to operate even when the load current becomes discontinuous. What should be the firing angle? Assume continuous conduction. Therefore for 5π ≤ ωt ≤ π 6 Version 2 EE IIT.www.com Practice problems and answers 1.com .jntuworld.

9º.65 V 2. T2). ∴ Supply voltage = Va = Eb + Iara = 140 + 50 × 0.2 ×1000 = 140 volts 1500 To supply full load torque.jntuworld. ∴ 3 2 VL cosα = . both the conducting thyristor (T1 and T2 in this case) turns off.cos2ωt ) dωt π 6 ∴ P0 = V0 2 RMS R π = VL 1 − 3 ∫5π cos2ωt dωt 2 π 6 = 183 Watts = VL 1 − 3 3 2 4π = 67.com v0 = Vbc = 2VL sinωt π ≤ ωt ≤ 7π 6 v0 = 0 π 2 ∴ V0 RMS = 3 ∫5π 2VL sin 2 ωt dωt π 6 π = VL 3 ∫5π (1 . the motor armature current = 50 A. To hold the overhauling load the motor must operate in the regenerative braking mode. At 1000 RPM Eb = 220 .www.50× 0.2 = 150 V in the reverse direction. Kharagpur 28 www. Similar explanation holds for all other thyristor firing. With reference to the conduction diagram of problem – 1 it can be seen that the load current becomes zero 30º after a new thyristor is fired (for example. Therefore. when T3 is fired the converter will be unable to resume operation from T2T3 mode unless T2 is fired simultaneously. 3.jntuworld. to ensure that the converter operates properly even under discontinuous load current condition the final gate pulse for a particular thyristors must be generated by logically “ANDing” the outputs of its own firing circuit with the output of the firing circuit of the thyristor in the commutation sequence as shown in the table next below To generate the gate pulse of : T1 T2 T3 T4 T5 T6 AND the outputs of : T1 & T2 T2 & T3 T3 & T4 T4 & T5 T5 & T6 T6 & T1 Version 2 EE IIT.150V π ∴ α = 118.com . Therefore. However.

com .jntuworld.jntuworld. Kharagpur 29 www.com Version 2 EE IIT.www.

www.com Module 2 AC to DC Converters Version 2 EE IIT. Kharagpur 1 www.jntuworld.jntuworld.com .

Kharagpur 2 www.com .com Lesson 14 Operation and Analysis of Three Phase Half Controlled Converter Version 2 EE IIT.jntuworld.jntuworld.www.

www. Kharagpur 3 www. Calculate the average and RMS value of the output dc voltage. distortion factor and power factor of the input ac line current.com Instructional Objectives On completion the student will be able to • • • • • • Draw the circuit diagram and waveforms of different variables associated with a three phase half controlled converter. Derive the closed form expression for output dc current and hence identify continuous or discontinuous conduction mode of the converter. Calculate the Fourier series components of the output voltage and input current waveforms.jntuworld. Identify the constructional and operational difference between a three phase fully controlled and half controlled converter.jntuworld.com . Version 2 EE IIT. Calculate the displacement factor.

this versatility of a three phase fully controlled converters are obtained at the cost of increased circuit complexity due to the use of six thyristors and their associated control circuit. Hence.jntuworld. The three phase half controlled converter has several other advantages over a three phase fully controlled converter.1(b). This complexity can be considerably reduced in applications where power regeneration is not necessary.jntuworld. For the same firing angle it has lower input side displacement factor compared to a fully controlled converter. Version 2 EE IIT. Kharagpur 4 www. However. Therefore the converter cannot operate in the inverting mode. It has one serious disadvantage however. It can handle reasonably high power and has acceptable input and output harmonic distortion. Although. its analysis is considerably more difficult. unlike fully controlled converter here both devices from the same phase leg can conduct at the same time. 14. In this lesson the operating principle and analysis of a three phase half controlled converter operating in the continuous conduction mode will be presented. 14. Replacing three thyristors by three diodes reduces circuit complexity but at the same time prevents negative voltage appearing at the output at any time. For this reason half controlled three phase converters are not as popular as their fully controlled counterpart. In that case three thyristors of the top group or the bottom group of a three phase fully controlled converter can be replaced by three diodes. 14.com . The configuration also lends itself to easy series and parallel connection for increasing voltage and current rating or improvement in harmonic behavior.1 Introduction Three phase fully controlled converters are very popular in many industrial applications particularly in situations where power regeneration from the dc side is essential. However.com 14. This implies both input and output harmonics are of lower frequency and require heavier filtering. The resulting converter is called a three phase half controlled converter. In the continuous conduction mode only one thyristor from top group and only one diode from the bottom group conduct at a time. there are nine conducting modes as shown in Fig.2 Operating principle of three phase half controlled converter Fig. from the point of view of construction and circuit complexity the half controlled converter is simpler compared to the fully controlled converter.1(a) shows the circuit diagram of three phase half controlled converter supplying an R-LE load. It also extends the range of continuous conduction of the converter.www. The output voltage is periodic over one third of the input cycle rather than one sixth as is the case with fully controlled converters.

com Now consider the conducting and blocking state of D2.. Similarly it can be shown that D4 and D6 will conduct during 2π/3 ≤ ωt ≤ 4π/3 and 4π/3 ≤ ωt ≤ 2π respectively. If the firing angle of T1 is α then T1 starts conduction at ωt = α . In the blocking state the voltage across D2 is either vac or vbc.jntuworld. Version 2 EE IIT.com . Kharagpur 5 www. Next consider conduction of T1. From this discussion the following conduction diagrams can be drawn for continuous conduction mode.π/3 . Therefore before T1 comes into conduction T5 conducts and voltage across T1 is v ac = 2VL sin (ωt + π/3) . Hence.e.π/3 and conducts upto α + π/3 .jntuworld. Similarly T3 and T5 conducts during α + π/3 ≤ ωt ≤ α + π and α + π ≤ ωt ≤ 2π + α . Taking vbc as the reference phasor (i. D2 can block only when these voltages are negative.www. v bc = 2VL sinωt ) D2 will block during 2π/3 ≤ ωt ≤ 2π and will conduct in the interval 0 ≤ ωt ≤ 2π/3 . The firing sequence of the thyristor is T1 → T3 → T5.

jntuworld. Unlike a three phase fully controlled converter the devices in the ________________ phase leg of a half controlled converter can conduct at a given time.1 Fill in the blanks(s) with appropriate word(s).www. A three phase half controlled converter can not operate in the ________________ mode. ii. iii. iv. A three phase half controlled converter has ________________ thyristors and ________________ diodes. A three phase half controlled converter has ________________ conduction modes as compared to ________________ of a fully controlled converter. These conduction modes are called ________________ modes. i. In a three phase half controlled converter only ________________ conduction modes appear at the same time.jntuworld. Version 2 EE IIT.com .com Exercise 14. v. Kharagpur 6 www.

Answer: (i) three. Therefore examining v0 for the conduction period of any one thyristor (for example T1) will be sufficient to deduce information regarding output voltage. In a three phase half controlled converter the diodes conduct in a manner similar to a ________________ converter where as the thyristors conducts similar to a ________________ converter. (ii) nine.jntuworld.2) Version 2 EE IIT. With T1 conducting there can be three conduction modes namely. controlled. T1D6.π 0 2π ⎣ 3 ⎝ 3⎠ 3⎠ ⎝ ⎦ ( ) (14.2 (a) and (b) also shows the waveforms of v0 and i0 (for α < π/3 and α > π/3 ) both of which are periodic over one third of the input voltage time period. Kharagpur 7 www. (vii) uncontrolled. (v) six.jntuworld.π ≤ ωt ≤ 0 3 v0 = vab = 2VL sin ωt + 2π 3 0 ≤ ωt ≤ α + π 3 v0 = vac = 2VL sin ωt + π 3 π α+ ⎤ 3 2VL ⎡ 0 π⎞ π⎞ ⎛ ⎛ V0 = sin ⎜ ωt + 2 ⎟ dωt+ ∫ 3 sin ⎜ ωt + ⎟ dωt ⎥ ⎢ ∫α . (iii) inverter. (viii) quarter. For example the average value of v0 can be found as follows. free wheeling.com . (iv) same. viii.1) ( ) (14. T1D2 and T1D4. The input current of a three phase half controlled converter does not have ________________ cycle symmetry.com vi. three. Now T1 conducts in the interval α . six.3 Analysis of three phase half controlled converters Fig. (vi) free wheeling. vii.π ≤ ω t ≤ α + π 3 3 D2 conducts in the interval 0 ≤ ωt ≤ 2 π 3 D4 conducts in the interval 2 π ≤ ωt ≤ 4 π 3 3 D6 conducts in the interval 4 π ≤ ωt ≤ 2π 3 ∴Conduction interval T1D6 exists only if α ≤ π 3 Conduction interval T1D4 exists only if α > π 3 So for α ≤ π 3 In the interval α . 60. ________________ modes appear only when the firing angle of the converter is greater than ________________ degrees. 14.www. 14.

From the waveforms of Fig.jntuworld.π ≤ ωt ≤ 2π α> π.5) (14.cos 2π + cos π .1 and 14. 3 3 3 v0 = vac = 2VL sin ωt + π 3 2π ≤ ωt ≤ α + π 3 3 v0 = 0 ( ) ( ) (14.sin ⎜ (3n -1)ωt .2.3n)ωt + 2 ⎟ dωt ⎬⎥ 3⎠ 3⎠ ⎝ 3 2VL ⎢ 3 ⎩ ⎝ ⎭⎥ = π 2π ⎢ α + 3 ⎧ ⎛ ⎫ ⎥ π⎞ π⎞ ⎛ ⎢+ ∫ ⎨sin ⎜ (3n + 1)ωt + ⎟ .jntuworld. 14.8) (14.9) (14. For for 3 2VL ⎡ cos α + π .⎟ dωt ⎬ ⎥ 3⎠ 3⎠ ⎢ 0 ⎩ ⎝ ⎝ ⎭ ⎥ ⎣ ⎦ Version 2 EE IIT. v0 is periodic over one third of the input cycle. Kharagpur 8 www.2 3 π 0 α+ ⎤ 3⎡ π⎞ π⎞ ⎛ ⎛ VAn = ⎢ 2VL ∫ π sin ⎜ ωt + 2 ⎟ cos3nωtdωt + 2VL ∫ 3 sin ⎜ ωt + ⎟ cos3nωtdωt ⎥ α0 π⎣ 3⎠ 3⎠ ⎝ ⎝ 3 ⎦ ⎡ 0 ⎧ ⎛ π⎞ π⎞ ⎫⎤ ⎛ ⎢ ∫α .π ⎨sin ⎜ (3n + 1)ωt + 2 ⎟ + sin ⎜ (1 .com .cos α + 2π ⎤ 2π ⎢ 3 3 3 3 ⎥ ⎣ ⎦ 3 2 V0 = VL (1 + cosα) 2π In the interval α .com = or.π sin ⎜ ωt + 3 ⎟ dωt ⎥ 2π ⎣ 3 ⎝ ⎠ ⎦ 3 2 = VL (1 + cosα) 2π RMS value of v0 can be found in a similar manner and is left as an exercise.3) (14.www. Therefore one can write v 0 = V0 + ∑ [ VAn cos 3nωt + VBn sin 3nωt ] VAn = VBn = 3 π∫ 3 π∫ n=1 π α+ 3 π α3 π α+ 3 π α3 α (14.4) ( ) (14.6) ∴ V0 = ⎤ 3 2VL ⎡ 2π π⎞ ⎛ ⎢ ∫α .10) v0 cos 3nωt dωt v0 sin 3nωt dωt For α ≤ π From equations 14.

www.jntuworld.com

π α0 ⎡ ⎤ cos {(3n + 1)ωt + 2π/3} 3 cos {(3n - 1)ωt - 2π/3} ⎢ ⎥ + ⎢ 3n + 1 3n - 1 π ⎥ 0 α3 2VL ⎢ 3 ⎥ = ⎢ π⎥ 2π 0 α+ ⎢ cos {(3n + 1)ωt + π/3} cos {(3n - 1)ωt - π/3} 3 ⎥ + ⎢+ ⎥ 3n + 1 3n - 1 π ⎢ ⎥ α+ 0 3 ⎣ ⎦

(14.11)

Therefore

⎡1 + cos [ (3n + 1)(α - π/3) + 2π/3] - cos [ (3n + 1)(α + π/3) + π/3] ⎤ ⎥ 3 2VL ⎢ 3n + 1 ⎢ ⎥ VAn = 2π ⎢ cos [ (3n - 1)(α + π/3) - π/3] - cos [ (3n - 1)(α - π/3) - 2π/3] -1 ⎥ ⎢+ ⎥ 3n - 1 ⎣ ⎦ ⎡1 - 2sin [ (3n + 1)α + π/2] sin [ π/6 - (3n + 1) π/3] ⎤ ⎥ 3 2VL ⎢ 3n + 1 ⎢ ⎥ = 2π ⎢ 1 + 2sin [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/3] ⎥ ⎢⎥ 3n - 1 ⎣ ⎦ 3 2VL ⎡1+ 2sin(6n + 1)π/6 cos(3n + 1)α 1- 2sin(6n - 1)π/6 cos(3n - 1)α ⎤ = ⎥ 2π ⎢ 3n + 1 3n - 1 ⎣ ⎦

=
Similarly,

3 2VL ⎡1+ (-1) n cos(3n + 1)α 1+ (-1) n cos(3n - 1)α ⎤ ⎥ 2π ⎢ 3n + 1 3n - 1 ⎣ ⎦

(14.12)

VBn =

π α+ ⎤ 3 2VL ⎡ 0 π⎞ π⎞ ⎛ ⎛ sin ⎜ ωt + 2 ⎟ sin3nωtdωt + ∫ 3 sin ⎜ ωt + ⎟ sin3nωtdωt ⎥ ⎢ ∫α - π 0 π ⎣ 3 ⎝ 3⎠ 3⎠ ⎝ ⎦

(14.13)

or,

⎡ 0 ⎧ ⎡ ⎤ π⎤ π ⎤⎫ ⎡ ⎢ ∫α - π ⎨cos ⎢ (3n - 1)ωt - 2 ⎥ - cos ⎢ (3n + 1)ωt + 2 ⎥ ⎬ dωt ⎥ 3⎦ 3 ⎦⎭ ⎣ 3 2VL ⎢ 3 ⎩ ⎣ ⎥ VBn = π ⎥ 2π ⎢ α + 3 ⎧ ⎡ π⎤ π ⎤⎫ ⎡ ⎢+ ∫ ⎨cos ⎢ (3n - 1)ωt - ⎥ - cos ⎢ (3n + 1)ωt + ⎥ ⎬ dωt ⎥ 3⎦ 3 ⎦⎭ ⎢ 0 ⎩ ⎣ ⎥ ⎣ ⎣ ⎦
0 ⎡ sin {(3n - 1)ωt - 2π/3} 0 ⎤ sin {(3n + 1)ωt + 2π/3} ⎢ ⎥ 3n - 1 3n + 1 π π ⎥ ⎢ αα3 2VL ⎢ 3 3 ⎥ = π π 2π ⎢ α+ α+ ⎥ ⎢ + sin {(3n - 1)ωt - π/3} 3 - sin {(3n + 1)ωt + π/3} 3 ⎥ ⎢ ⎥ 3n - 1 3n + 1 0 0 ⎣ ⎦

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⎡ sin [ (3n - 1)(α + π/3) - π/3] - sin [ (3n - 1)(α - π/3) - 2π/3] ⎤ ⎢ ⎥ 3 2VL 3n - 1 ⎢ ⎥ = 2π ⎢ sin [ (3n + 1)(α + π/3) + π/3] - sin [ (3n + 1)(α - π/3) + 2π/3] ⎥ ⎢⎥ 3n + 1 ⎣ ⎦ ⎡ cos [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/6] ⎤ ⎥ 3 2VL ⎢ 3n - 1 ⎢ ⎥ = π ⎢ cos [ (3n + 1)α + π/2] sin [ (3n + 1)π/6 - π/6] ⎥ ⎢⎥ 3n + 1 ⎣ ⎦ 3 2VL ⎡ sin(3n + 1)α sin(3n - 1)α ⎤ nπ = + ⎢ 3n + 1 ⎥ sin 2 π ⎣ 3n - 1 ⎦
∴ VBn = 3 2 nπ ⎡ sin(3n + 1)α sin(3n - 1)α ⎤ VL sin ⎢ + π 2 ⎣ 3n + 1 3n - 1 ⎥ ⎦ (14.14)

Similar analysis can be done for α > π 3 To find out the Fourier series of the input ac line current the load may be replaced by a constant current source having the same value as the average load current. This approximation will be valid provided the load current ripple is relatively small. With this assumption the last waveform of Fig. 14.2(b) can be redrawn as follows.

α - π ≤ ωt ≤ 2π 3 3 α + π ≤ ωt ≤ 4π 3 3 otherwise

ia = I0 ia = - I0 ia = 0

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i a = ∑ [ I an cos nωt + I bn sin nωt ]
n=1
2π I an = 1 ∫ i a cos nωt dωt π 0 ⎡ 2π = 1 ⎢ ∫ 3 π I 0 cos nωt dωt π ⎣ α- 3

α

(14.15)

⎤ I0 cos nωt dωt ⎥ ⎦ π 4π ⎤ I0 ⎡ sin nωt 2 3 sin nωt 3 ⎥ ⎢ = π ⎢ n α- π n α+ π ⎥ 3 3 ⎦ ⎣ I = 0 ⎡sin 2nπ - sin n α - π + sin n α + π - sin 4nπ ⎤ nπ ⎢ 3 3 3 3 ⎥ ⎣ ⎦ 2I0 ⎡ 2nπ = sin + cos nα sin nπ ⎤ nπ ⎢ 3 3⎥ ⎣ ⎦

α+ π 3

4π 3

( )

(

)

or,

Ian =

2I0 ⎡cos nα - (- 1) n ⎤ sin nπ ⎦ nπ ⎣ 3

(14.16)

2π I bn = 1 ∫ i a sin nωt dωt π 0 ⎡ 2π = 1 ⎢ ∫ 3 π I 0 sin nωt dωt π ⎣ α- 3

⎤ I0 sin nωt dωt ⎥ ⎦ α- π 4π ⎤ I ⎡ = 0 ⎢ cos nωt π 3 + cos nωt 3 π ⎥ 2 α+ nπ ⎣ 3 3⎦ I = 0 ⎡sin 4nπ - cos 2nπ + cos n α - π - cos n α + π ⎤ nπ ⎢ 3 3 3 3 ⎥ ⎣ ⎦ 2I = 0 sin nα sin nπ nπ 3

α+ π 3

4π 3

( )

(

)

(14.17)

For the fundamental component n = 1
i a1 = 3I 0 [ cosωt + cosα cosωt + sinα sinωt ] π 3I0 = [cosωt + cos(ωt - α)] π 2 3I0 = cos α cos ωt - α π 2 2

(

)

(14.18) (14.19)

∴ Displacement factor = cos α 2
I Distortion factor = a1 = Ia 6 I cos α π 0 2= I0 π - α π 6 cos α 2 π (π - α)

(14.20)

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∴ Power factor = Distortion factor × Displacement factor
6 cos 2 α = 2 π (π - α) 3 (1 + cosα) 2(π - α) π

(14.21)

A closed form expression for i0 can be found as follows v0 = vac In the interval 0 < ωt ≤ α + π 3 di π ∴ L 0 + Ri0 + E = vac = 2VL sin ωt + dt 3 ωt 2VL ⎡ π sinθ ⎤ ∴ i 0 = Ie tanφ + ⎢sin ωt + 3 - φ - cosφ ⎥ Z ⎣ ⎦ Where tanφ = ωL , Z = R 2 + ω 2 L2 and E = 2VL sinθ R At ωt = α + π 3 ( α + π/3) 2VL ⎡ 2π - sinθ ⎤ i 0 = I1 = Ie tanφ + ⎢sin α - φ + 3 cosφ ⎥ Z ⎣ ⎦

(

(

)

)

(14.22) (14.23) (14.24)

(

)

(14.25)

In the interval α + π ≤ ωt ≤ 2π 3 3 ∴ L

v0 = vbc

di 0 + Ri 0 + E = v bc = 2VL sinωt dt ( ωt - α - π/3) 2VL ⎡ ⎤ ∴ i 0 = I 2 e tanφ + sin ( ωt - φ ) - sinθ ⎥ cosφ ⎦ Z ⎢ ⎣ At
ωt = α + π 3 2VL ⎡ π sinθ ⎤ i0 = I2 + ⎢sin α + 3 - φ - cosφ ⎦ = I1 ⎥ Z ⎣

(14.26) (14.27)

(

)

(14.28) (14.29) (14.30) (14.31) (14.32)

2VL sin ( α - φ ) Z ( ωt ) ( ωt - α - π/3) 2VL ⎡ sinθ ⎤ tanφ ∴ i 0 = Ie + ⎢sin ( φ - α ) e tanφ + sin ( ωt - φ ) ⎥ Z ⎢ cosφ ⎥ ⎣ ⎦
∴ I2 = Ie
tanφ

( α + π/3)

-

i0

ωt = 2π 3

= Ie

-

2π 3tanφ

+

2VL Z

i0

ωt =

2π 3

= i0

ωt = 0

= I+

( α - π/3) ⎡ ⎤ sin ( φ - α ) e tanφ - sin φ - 2π - sinθ ⎥ ⎢ 3 cosφ ⎥ ⎢ ⎣ ⎦ 2VL ⎡ ⎤ sin π - φ - sinθ ⎥ Z ⎢ 3 cosφ ⎦ ⎣

(

)

(

)

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- 2π ⎞ ⎛ ∴ I ⎜1 - e 3tanφ ⎟ = ⎝ ⎠

( α - π/3) ⎤ 2VL ⎡ ⎢sin ( φ - α ) e tanφ + sinφ ⎥ Z ⎢ ⎥ ⎣ ⎦ π ∴ for 0 < ωt ≤ α + 3 ( ωt - α - π/3) - ωt ⎡ ⎤ 2VL ⎢ sinφ e tanφ e tanφ π - φ - sinθ ⎥ i0 = sin ( φ - α ) + + sin ωt + - 2π - 2π cosφ ⎥ Z ⎢ 3 3tanφ 3tanφ 1- e 1- e ⎢ ⎥ ⎣ ⎦ (14.33)

(

)

for

α + π ≤ ωt ≤ 2π 3 3
- ωt ⎤ ⎫ ⎪ sinφ e tanφ sinθ ⎥ + sin ( ωt - φ ) ⎬+ - 2π cosφ ⎥ ⎪ 1- e 3tanφ ⎭ ⎥ ⎦

i0 =

α - π/3 - ωt ⎡ ⎧ - ( ωt - α - π/3) 2VL ⎢ ⎪ e tanφ tanφ sin ( φ - α ) ⎨e + - 2π Z ⎢ ⎪ 1- e 3tanφ ⎩ ⎢ ⎣

(14.34)

Exercise 14.2
1. Fill in the blank(s) with the appropriate word(s).

i. In a three phase half controlled converter each thyristor and diode conduct for ________________ degrees. ii. The output voltage waveform of a three phase half controlled converter is periodic over ________________ of the input voltage cycle. iii. The output voltage waveform of a three phase half controlled converter operating with α > π/3 and α ≤ π/3 are ________________ and have ________________ formula for the average voltage. iv. The output voltage and current of a three phase half controlled converter contain ________________ harmonics of the input ac frequency. v. The ac input current of a half controlled three phase converter can be zero for larger than ________________ of the input ac cycle provided the value of α is ________________ than 60°. vi. The input ac current of a three phase half controlled converter contain ________________ harmonics but no ________________ harmonics. vii. For the same output load current and firing angle the three phase half controlled converter has better ________________ factor but poorer ________________ factor compared to a fully controlled converter.
Answer: (i) 120°; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even, triplen; (vii) displacement, distortion.

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2. A 200V, 1450 RPM, 100A separately excited dc machine has an armature resistance of 0.04Ω. The machine is driven by a three phase half controlled converter operating from a three phase 220V, 50Hz supply. The motor operates at the rated speed and rated load torque. Assuming continuous conduction find out (i) the firing angle of the converter; (ii) RMS fundamental component of the input current, (iii) Input current displacement factor and distortion factors.
Answer: (i) Under rated operating condition the motor must be supplied with rated voltage. 3 2 Therefore Vo = VL (1+ cosα ) = 200V 2π

Where VL = 230V ∴ α ≈ 70o (ii) Io = 100A From equation (14.18) 6 Ii1 = I o cos α = 63.87 amps 2 π (iii) From equation (14.19) Input displacement factor = cos α = 0.819 2 From equation (14.20) 6 cos α = 0.712 Input distortion factor = 2 π(π − α)

References
1. “Power Electronics”’ P.C. Sen, Tata McGrawhill publishing company limited, 1995. 2. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robins; John Willey and Sons Inc, Third Edition, 2003.

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Lesson Summary
• • • • • • • • Three phase half controlled converters are obtained by replacing three thyristors of either the top group or the bottom group of fully controlled converters by three diodes. Three phase half controlled converters can not operate in the inverting mode. Three phase half controlled converters have nine operating modes as compared to six of a fully controlled converter. The three free wheeling modes of a half controlled converters appears only when the firing angle is larger than 60º. The output voltage and current waveforms of a three phase half controlled converter consist of a dc component and triplen harmonics of the input voltage frequency. For the same input ac voltage and firing angle a half controlled converter has higher output average dc voltage compared to a fully controlled converter. The input ac line current of a three phase half controlled converter contains harmonics of all (odd and even) order except triplen harmonics. For the same average dc load current and firing angle the half controlled converter has better input current displacement factor but poorer distortion factor compared to a fully controlled converter. The triggering circuit of a three phase half controlled converter is similar to that of a fully controlled converter. However, only three are required.

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Practice Problems and Answers
1. If a free wheeling diode is connected across the output terminals of a three phase fully controlled converter will the performance of converter will be similar to a half controlled converter? Justify your answer. 2. A 220V, 1500 rpm, 50A, separately excited dc motor with armature resistance of 0.5Ω if fed from a 3 phase half controlled rectifier. The available ac source is 440V, 50Hz. A star delta connected transformer is used to feed the armature so that the motor terminal voltage equals rated voltage when converter firing angle is zero. (i) Calculate the transformer turns ratio (ii) Firing angle when (a) motor is running at 1200 rpm and rated torque; (b) 1500 rpm and half the rated torque. 3. A battery with a nominal voltage of 200V and internal resistance of 10mΩ has to be charged at a constant current of 20 amps from a 3 phase 220V 50 Hz power supply. Which of the following converters will give better performance with respect to input current displacement factor, distortion factor and power factor? (i) 3 phase fully controlled converter; (ii) 3 phase half controlled converter.

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Answers to Practice Problems
1) Connecting a diode at the output of a three phase fully controlled converter will not make it performs as a half controlled converter. For example i) When α ≤ π/3 the free wheeling diode will not come into conduction and therefore, the converter will continue to perform like a fully controlled converter which is very different from that of a half controlled converter for this range of α. For α > π/3 the output voltage will be clamped to zero for certain part of the input cycle. However, the output voltage will still have “six pulse” characteristics unlike a half controlled converter. Similarly the input current waveform will retain its quarter cycle symmetry which is not the case with a half controlled converter.

ii)

2)

For a half controlled converter i) at α = 0,

3 2 VL (1 + cosα) 2π V0 = 220 V, ∴ VL = 163 V, V0 =
∴ Primary phase voltage = 254 V

supply voltage = 440 V, ∴ Turns ratio = 1 : 0.64. ii)

(a) E b 1500 = 220 - 0.5 × 50 = 195V

12 = 156 V ∴ E b 1200 = 195 × 15 Torque is rated, ∴ Ia = 50 A, V1200 = 156 + 0.5 × 50 = 181 volts ∴ α = 49.87º ∴ 181 = 3 2 × 163(1 + cosα) 2π
(b) V1500 at half rated torque = 195 + 0.5 × 25 = 207.5V ∴ α = 27.7º 207.5 = 3 2 × 163(1 + cosα) 2π The output voltage of the converter should be V0 = 200 + 20 × 10 × 10-3 = 200.2 V (i) with a fully controlled converter ∴ α = 47.64º 200.2 = 3 2 × 220 cosα π ∴ Displacement factor = cos α = 0.674 Distortion factor = 3 = 0.955 π ∴ Power factor = Displacement factor × Distortion factor = 0.6436 Version 2 EE IIT, Kharagpur 17
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3)

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(ii)

with a half controlled converter ∴ α = 69.65º 200.2 = 3 2 × 220 (1 + cosα) 2π ∴ Displacement factor = cos α = 0.82 2 6 cos α = 0.8166 Distortion factor = π(π-α) 2 ∴ Power factor = 0.6695 ∴ Displacement factor and power factor of a half controlled converter are better compared to a fully controlled converter while the distortion factor is poorer.

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Module 2
AC to DC Converters
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Lesson 15
Effect of Source Inductance on the Performance of AC to DC Converters
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Instructional Objectives
On completion the student will be able to • • • • • Draw the voltage and current waveforms associated with a converter taking into account the effect of source inductance. Find the average output voltage of the converter as a function of the firing angle and overlap angle. Estimate overlap angles under a given operating condition and hence determine the turn off time available for the thyristors. Draw the dc equivalent circuit of a converter and parameterize it. Find out the voltage stress on the thyristors due to commutation overlap.

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The series impedance of the transformer can not always be neglected. It is assumed that the thyristors T3 and T4 were conducting at t = 0.2 Single phase inductance fully controlled converter with source Fig. The presence of source inductance does have significant effect on the performance of the converter. 15. for some interval all four thyristors continue to conduct as shown in Fig. In this lesson a quantitative analysis of these effects will be taken up in some detail. when T1 and T2 are turned ON T3 T4 does not commutate immediately.com 15. The converter output voltage and input current waveforms also change significantly. In most cases this impedance is predominantly inductive with negligible resistive component. Even if no transformer is used. 15.1(a) shows a single phase fully controlled converter with source inductance.jntuworld. Version 2 EE IIT.jntuworld.com . in most practical situations.1 Introduction In the previous lessons the input ac power sources supplying an ac to dc power converter have been assumed to be ideal with no source impedance. Fig. Although this assumption simplifies the analysis of the converters.www. For simplicity it has been assumed that the converter operates in the continuous conduction mode. T1 and T2 are fired at ωt = α. Kharagpur 4 www. However. This interval is called “overlap” interval. With source inductance present the output voltage of a converter does not remain constant for a given firing angle. if a source inductance is present the commutation and change of input current polarity can not be instantaneous. If there were no source inductance T3 and T4 would have commutated as soon as T1 and T2 are turned ON.1(b). the impedance of the feeder line comes in series with the source. Therefore. 15. 15. Most ac dc converters are supplied from transformers. it has been assumed that the load current ripple is negligible and the load can be replaced by a dc current source the magnitude of which equals the average load current. Instead.1(b) shows the corresponding waveforms. The input current polarity would have changed instantaneously. Instead it drops gradually with load current. Further. they are not fully justified.

www. The same process repeats during commutation from T1 T2 to T3T4 at ωt = π + α. Kharagpur 5 www.com . Version 2 EE IIT. T1 and T2 starts conducting the full load current. On the other hand.jntuworld.com During this period the load current freewheels through the thyristors and the output voltage is clamped to zero. the input current starts changing polarity as the current through T1 and T2 increases and T3 T4 current decreases.jntuworld. At the end of the overlap interval the current through T3 and T4 becomes zero and they commutate.

com .8) (15.com From Fig.4) (15.cosωt) .6) ii(ωt = α) = .3) (15.2) (15. Kharagpur 6 www.I0 ∴ 2Vi ii = I cosωt ωL ii ωt = α =I- 2Vi cosα = .7) (15.I0 ωL 2Vi (cosα .www.jntuworld.cos(α + μ)) .10) ∴ V0 = 2 2 vi 2vi cosα [ cosα − cos(α + μ)] π π = 2 2 vi cosα . In the following analysis an expression of the overlap angle “μ” will be determined.1(b) it is clear that. commutation overlap not only reduces average output dc voltage but also reduces the extinction angle γ which may cause commutation failure in the inverting mode of operation if α is very close to 180º.5) (15.9) cosα .11) Version 2 EE IIT. 15.jntuworld.I0 ωL ∴ ∴ ∴ ∴ I= ii = 2Vi cosα .I0 ωL 2Vi (cosα .I0 ωL 2ωL I Vi 0 at ωt = α + μ ii = I0 I0 = (15.1) (15. From the equivalent circuit of the converter during overlap period L dii = vi dt for α ≤ ωt ≤ α + μ (15.cos(α + μ) = or V0 = I π V0 = I π ∫ ∫ α+π α α+π vi dωt 2vi sinωt dωt α+μ = = 2vi [cos(α + μ) − cos(π + α)] π 2vi [cosα + cos(α + μ)] π (15.2 ωL I0 π π (15.

4(a) shows such a converter. 15.1(b) by the hatched portion of the v0 waveform. Therefore this resistance should be used carefully where power calculation is involved.3 Three phase inductance fully controlled converter with source In lesson 13 the three phase fully controlled converter was analyzed with ideal source with no internal impedance.11 can be represented by the following equivalent circuit The simple equivalent circuit of Fig. the qualitative effects on the performance of the converter is similar to that in the case of a single phase converter.jntuworld. The voltage drop across the internal resistance “RC” represents the voltage lost due to overlap shown in Fig. Therefore. 15.jntuworld. Version 2 EE IIT.com . Kharagpur 7 www. Fig. 15. this is called the “Commutation resistance”.com Equation 15. Although this resistance accounts for the voltage drop correctly there is no power loss associated with this resistance since the physical process of overlap does not involve any power loss.www. When the source inductance is taken into account. As in the case of a single phase converter the load is assumed to be highly inductive such that the load can be replaced by a current source. The open circuit voltage of this practical source equals the average dc output voltage of an ideal converter (without source inductance) operating at a firing angle of α.3 represents the single phase fully controlled converter with source inductance as a practical dc source as far as its average behaviour is concerned. 15.

T6 and T2 from the bottom group and T1 from the top group conducts.com As in the case of a single phase converter. 15. Version 2 EE IIT. It takes place over an overlap period of “μ1” instead. this situation is not very common and will not be discussed any further in this lesson.jntuworld. Current in the outgoing thyristor gradually decreases to zero while the incoming thyristor current increases and equals the total load current at the end of the overlap period. 15. The equivalent circuit of the converter during this period is given by the circuit diagram of Fig. The exact amount of this reduction can be calculated as follows. In the time interval α < ωt ≤ α + μ.jntuworld.5. Due to the conduction of two devices during commutation either from the top group or the bottom group the instantaneous output voltage during the overlap period drops (shown by the hatched portion of Fig. If the duration of the overlap period is greater than 60º four thyristors may also conduct clamping the output voltage to zero for sometime. Kharagpur 8 www. During the overlap period three thyristors instead of two conducts.4 (b)) resulting in reduced average voltage.com . However. commutations are not instantaneous due to the presence of source inductances.www.

jntuworld.17) (15.13) (15. Kharagpur 9 www. ib = 0 ∴ Or.16) (15.I0 ib = C - 2VL cosωt 2ωL ∴ C= ib = 2VL cosα .i ) v bc = L or.cos(α + μ) = 2ωL I VL 0 (15.π 3 2ωL ( ) (15.www.22) for α + μ ≤ ωt ≤ α + π ∴ 3 v0 = vac ⎡ α+μ V0 = 3 ⎢ ∫ 3 va dωt + π⎣ α 2 ∫ π 3 α+μ α+ ⎤ vac dωt ⎥ ⎦ Version 2 EE IIT.I0 2ωL 2VL (cosα .L c + vc dt dt d (i .21) To calculate the dc voltage For α ≤ ωt ≤ α + μ v0 = va . dt b c di b di =. in the interval α < ωt ≤ α + μ di b di .jntuworld. ∴ at ωt = α + μ.18) but ∴ at ωt = α.12) (15.v b + L di b = 3 va dt 2 (15.20 holds for μ ≤ 60º. It can be shown that for this condition to be satisfied I0 ≤ VL cos α .com .15) (15.com Therefore.cos(α + μ)) = I0 2ωL cosα .c ib + ic + Io = 0 ∴ dt dt 2L d i b = vbc = 2VL sinωt ∴ dt vb = L (15. ib = .14) (15.I0 2ωL 2VL (cosα .20) Equation 15.19) (15.cosωt) .

The average output voltage of a ac-dc converter ______________ as a result of commutation overlap. Exercise 15. vi. iv.cos(α + μ)] π 2π (15. In a three phase converter ______________ thryistors conduct during the overlap period provided the overlap angle is less than ______________ degrees. vii. ii. π It should be noted that RC is a “loss less” resistance. Version 2 EE IIT.23) or 3 2VL V0 = 3 2 VL cosα π 2π ∫α α+μ sinωt dωt 3 2VL = 3 2 VL cosα [cosα .com π α+ ⎡ α+μ ⎤ = 3 ⎢∫ vac + 3 va .24 V0 = 3 2 VL cosα . Due to the presence of source ______________ commutation in a converter is not ______________. 15.25 suggests the same dc equivalent circuit for the three phase converter with source inductance as shown in Fig.3 ∫ v bc dωt π 2π α ( ) (15.20 into 15. In a single phase converter ______________ thyristors conduct during the overlap period. Length of the overlap period depends on the valve of the source inductance and load ______________. The period over which the commutation process continues is called the ______________ period.1 1.jntuworld.24) Substituting Equation 15.3 with VOC = 3 2 VL cosα π and commutation resistance R C = 3 ωL . Fill in the blank(s) with appropriate word(s) The internal impedance of an ac source supplying a converter is largely ______________ in nature.jntuworld. i.www. v.com . since the overlap process does not involve any active power loss. iii.25) Equation 15. Kharagpur 10 www.3 ωL I0 π π (15.vac + ∫ 3 vac dωt ⎥ α+μ π⎣ α 2 ⎦ π α+μ ⎛ v ⎡ α+ ⎤ ⎞ = 3 ⎢ ∫ 3 vac dωt + ∫ ⎜ a + vc ⎟ dωt ⎥ α α π⎣ ⎝ 2 ⎠ ⎦ α+μ = 3 2 VL cosα .

3 2 3 VL .× . The line voltage is adjusted such that at α = 0. sixty. 100A separately excited dc motor has an armature resistance to 0. (v) four. instantaneous. (vi) three. (viii) commutation. Kharagpur 11 www. Answer: (i) inductive. (x) notches. What is the maximum braking torque the motor will be able to produce under this condition without causing commutation failure? Answer: Under rated operating condition. In the dc equivalent circuit of a converter the input ac source inductor appears as a loss less resistance called the ______________ resistance.5 Io cos α − cos ( α + μ ) = 198 At the limiting condition of commutation failure α + μ ≈ 180o ∴ cos α = Io −1 198 2 ∴ 3 3 2 ⎛3 ⎞ × 198 − ⎜ × 0. ix.jntuworld. x.1Ω.com viii.5×100 π π VL = 198 volts 220 = or Eb rated speed = 220 − 100 × 0.4 ∴ Io = 152. Version 2 EE IIT. The ac source has an inductive reactance of 0.377 Io = 57.5 + 0. the motor operates at rated speed and torque. Commutation overlap decreases the ______________ angle of a converter and may cause commutation failure during ______________ mode of operation.1⎟ Io = −210V π ⎝π ⎠ Also from equation 15. 15.com .5 + 0.24 Amps ∴ Maximum braking torque will be approximately 150% of the rated motor torque. Therefore from eqn. (vii) decreases. 1450 RPM. Commutation overlap introduces ______________ in the supply voltage waveform.1⎟ I o = −210 Io − π π ⎝π ⎠ or 0.20 2 × 0. 2. the motor terminal voltage is 220V and it draws 100 Amps current. (ii) inductance.www.jntuworld.25.1 = 210V Under regenerative braking in the reverse direction at rated speed 3 2 ⎛3 ⎞ ×198cos α − ⎜ × 0. (iv) current .5Ω at 50 Hz. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50 Hz ac source. (iii) overlap. (ix) inverter. The motor is to be braked regeneratively in the reverse direction at rated speed using the converter. A 220V.

www. The length of the overlap period increases with increasing source inductance and load current. three thyristors conduct during the overlap period provided it is less than 60º. Robbins. Due to the presence of the source inductance in the ac line the thyristors in a ac-dc converter can not commutate instantaneously. In a three phase converter. Third Edition. Prentice – Hall of India. Commutation overlap introduces “notches” in the ac supply voltage waveform which may affect other equipment connect to the same power source. Devices and Applications” Second Edition. “Power Electronics. Muhammad H.com . Converters. • • • Version 2 EE IIT. New Delhi. Lesson Summary • • • • • • • • • Ac power sources supplying an ac-dc converter have internal impedances which are not always negligible. Sen. The internal impedance of an ac source is predominantly inductive with negligible resistive component. The period over which the commutation process continuous is called the overlap period. Circuits. The voltage drop due to commutation overlap can be represented as a drop across a commutation resistance the value of which is proportional to the ac line reactance per phase. Undeland. Rashid. 3. In a single phase converter all four thyristors conduct during the overlap period. The commutation resistance is “loss less” since the actual process of overlap does not involve any real power loss. 1995.C. Kharagpur 12 www. Tata McGrawhill publishing company limited.jntuworld. “Power Electronics”. “Power Electronics. Mohan. 1994.jntuworld. John Willey and Sons Inc. Applications and Design”. The average output voltage of a converter decreases as a result of commutation overlap.com References 1. P. 2003. Commutation overlap reduces the margin angle (γ) of a converter and may cause commutation failure. 2.

www.jntuworld.jntuworld.com Module 2 AC to DC Converters Version 2 EE IIT.com . Kharagpur 1 www.

com . Harmonic Reduction. Filter Version 2 EE IIT. Kharagpur 2 www.jntuworld.jntuworld.com Lesson 16 Power Factor Improvement.www.

A gate turn-off thyristor (GTO) also may be used. and the current through thyristor switches. was presented. self-commutated devices. In this (last) lesson (#2. Types of filters used to obtain ripple free (dc) output voltage and currents. like a thyristor. and filters. and then turned off by forced commutation at ωt = ( π − β ) . Fig. output voltage. are replaced by the switches.and threephase. 16. α. which is lagging) decreases. switch. in brief. in which case.jntuworld. The thyristors. the circuit of a single phase full wave half (semi) controlled bridge converter (ac-dc) is used mostly as an example. The power transistor is turned on by applying a signal at the base. reducing the harmonics. Power Factor Improvement For phase-controlled operation in both single phase full wave half and full controlled bridge converters as discussed in this module (#2). the use of various filters to reduce the harmonics in the output voltage and current waveforms.1(b) shows the waveforms for input voltage. The output voltage is controlled by varying the extinction angle. both single. Then. it may be turned off by applying a short negative pulse to its gate.6) of this module (# 2). The switch. Lastly. the harmonic reduction techniques are taken up.jntuworld. T1 & T2.com Instructional Objectives Study of the following: • • • Schemes for the improvement of power factor in AC-DC converters. the inductance on the source (ac) side being taken into account.com . such as power transistor or equivalent. and then turned off at ωt = ( 2π − β ) .www. as the average value of output voltage (Vdc) decreases. are described. Methods for harmonic reduction in the current waveforms of the converters. are presented.7). the drop in the output voltage due to the commutation overlap in the converter. three important points – power factor improvement.8). β. 16. The three schemes used for power factor (pf) improvement are: • • • Extinction angle control Symmetrical angle control Pulse width modulation (PWM) control Extinction Angle Control The circuit diagram of a single phase full wave half-controlled (semi) force-commutated bridge converter is shown in Fig. S1 is turned on at ωt = 0 . with the increase in firing angle delay. Kharagpur 3 www.1(a). In all these cases.1-2. as applicable to converters. in the lessons (#2. In extinction angle control. This is also applicable for both three phase half wave and full wave (bridge) converters. the displacement factor (or power factor. The three schemes for power factor improvement are discussed. input current. and the Version 2 EE IIT.1 Introduction After the discussion of various types of ac to dc converters (rectifiers). 2. harmonic reduction.8. in the previous lesson (#2. and turned off by withdrawing the signal at the base. The fundamental component of input current leads the input voltage. but is turned on by a short positive pulse. S2 is turned on at ωt = π .

www.com displacement factor (and power factor) is leading. This feature may be desirable to simulate a capacitive load. Kharagpur 4 www.jntuworld.jntuworld. iT1 + S1 + vs D2 D1 iDF (a) Circuit is S2 iT2 DF i 0 = Ia v0 L O A D Version 2 EE IIT. thus compensating the line voltage drops.com .

1 1 2 This scheme of extinction angle control can also be used for single phase full wave full controlled bridge converter with four switches.β 2π .β 2π ωt ωt π-β π 2π 3π .β 0 .Ia Ia 0 io π-β π 2π 3π . as β varies from 0 to π .β ωt Ia 2π ωt is1 π 2π . instead of two needed in the earlier case. Vo varies from V to 0.β ωt Load current ωt (b) Waveforms for extinction angle control Fig.jntuworld.1 Single-phase forced-commutated semi-converter. The rms value of output voltage is 2 ⎡1 ⎛ 1 ⎡ 2 π-β ⎤ ⎞⎤ Vo = ⎢ ∫ 2V 2 sin 2 ωt d ( ωt ) ⎥ = V ⎢ ⎜ ( π − β ) + sin 2β ⎟ ⎥ 2 ⎣ 2π 0 ⎦ ⎠⎦ ⎣π ⎝ Here also.com vs Vm 0 v0 0 Ia Ia 0 iT2 iT1 vs = Vmsinωt π 2π β π-β π 2π . Kharagpur 5 www. The students are requested-to study this matter form text books.com . The average output voltage is 2 π-β 2 Vdc = ∫0 2Vsin ωt d ( ωt ) = π ⋅ V (1 + cos β ) 2π The value of Vdc is varied from (2 2 / π)V to 0.www.β ωt 0 iDF 0 is Ia π-β π 2π . but details are not included here. Version 2 EE IIT.jntuworld. 16.

16. and the dc signal being same as the peak of the triangular reference signal. In the second case. Version 2 EE IIT. The switch. The output voltage is varied by varying conduction angle. Kharagpur 6 www. S1 is turned on at ωt = ( π − β ) 2 and then turned off at ωt = ( π + β ) 2 . output voltage. 16.com Symmetrical Angle Control This control can be applied for the same half-controlled force commutated bridge converter with two switches. S1 and S2 as shown in Fig. when the dc signal is zero. the conduction angle varies linearly with the dc signals. 16.2(a) shows the waveforms for input voltage. the power factor is improved.2(c).www.1(a).e. but in inverse ratio.2(b). The half-sine waves can be obtained using a full wave diode (uncontrolled) bridge converter. β.0). 16. no conduction ( β = 0 ) takes place. full conduction (β = π ) takes place. S2 is turned on at ωt = ( 3π − β ) 2 and then turned off at ωt = ( 3π + β ) 2 .. Therefore. Fig. and the displacement factor is unity (1.jntuworld. The other switch. The fundamental component of input current is in phase with input voltage. i.jntuworld.com . input current and the current through the switches. The gate signals are generated by comparing half-sine waves with a dc signal as shown in Fig. The gate signals can also be generated by comparing triangular waves with a dc signal as shown in Fig.

Kharagpur 7 www. 2π 3π ωt π S2 2π S1 3π ωt vr vc π-β 2 π+β 2 vs = Vmsinωt π ωt β π 2π 3π ωt π /2 π 2π 5π /2 ωt π π 3π /2 2π is1 2π ωt ωt Load current ωt Version 2 EE IIT.www.jntuworld. 16.com vs Vm 0 v0 Vm 0 is1 Ia 0 is2 Ia 0 is Ia 0 .Ia i0 Ia 0 (a) v Ar -Ar 0 vg 0 S1 β π (b) Fig.com .jntuworld.2 Symmetrical angle control.

or inverter).com . In this case. the students are requested to study the two lessons (#5. Fig.4-5.3c. there is only one pulse per half cycle in the input current of the converter. which could easily be filtered out. 16. extinction angle or symmetrical. The lowest order harmonic can be eliminated or reduced by selecting the number of pulses per half cycle. The gate signals are generated by comparing a triangular wave with a dc signal as shown in Fig. the converter switches are turned on and off several times during a half cycle. However.3a shows the input voltage. In Pulse Width Modulation (PWM) control. and input current. For more details of PWM methods used.5) in module 5 (DC-AC converter. and the output voltage is controlled by varying the width of pulses. and as a result. Version 2 EE IIT.www.com The average output voltage is ⎛2 2 2 ( π+β ) / 2 ⎛ β ⎞⎞ Vdc = ∫ 2V sin ωt d ( ωt ) = ⎜ ⎜ ⎟⎟ ⎜ π V sin ⎝ 2 ⎠ ⎟ π ( π−β ) / 2 ⎝ ⎠ The value of Vdc varies from 2 2π V to 0 as β varies from π to 0.jntuworld. output voltage. 16. all the pulse widths obtained are equal. increasing the number of pulses would also increase the magnitude of higher order harmonics.jntuworld. The rms value of output voltage is 2 ⎡ 2 ( π+β ) / 2 2 2 ⎤ ⎡1 ⎤ Vo = ⎢ ∫ 2V sin ( ωt ) d ( ωt ) ⎥ = V ⎢ ( β + sin β ) ⎥ ( π-β ) / 2 ⎣ 2π ⎦ ⎣π ⎦ 1 1 2 ( ) Pulse Width Modulation (PWM) Control If the output voltage of single phase half-controlled converter is controlled by delay angle. It is difficult to filter out the lower order harmonic current. The earlier case of symmetrical angle control can be considered as single pulse PWM. Kharagpur 8 www. the lowest order harmonic is third.

Ia Ia 0 αm δm π 2π 3π ωt π δm π 2π 3π ωt 2π 3π ωt π δm αm π π + αm π + αm 2π 3π ωt 2π 3π ωt Load current (a) v Ar -Ac 0 vg2 S1 δm α1 αm (b) S1 δm ωt π S1 vr vc ωt π Version 2 EE IIT.com v 0 v0 δm 0 is1 Ia 0 is3 Ia 0 is Ia 0 i0 .jntuworld.jntuworld.com . Kharagpur 9 www.www.

.5. and ends at ωt = ( π + α1 + δ1 ) .. The output voltage (i. performance parameters) can be obtained in two steps: (i) by considering only one pair of pulses such that.www. the other pulse starts at ωt = π + α1 .jntuworld. and ends at ωt = α1 + δ1 . ∑ (a α n cos nωt + b n sin nωt ) Due to symmetry of the input current waveform. and (2) then by combining the effects of all pairs of pulse. The Fourier coefficients are obtained as 1 2π a n = ∫ is ( t ) cos nωt d ( ωt ) π 0 p 1 π+αm +δm ⎡ 1 α m +δm ⎤ I a cos nωt d ( ωt ) − ∫ I a cos nωt d ( ωt ) ⎥ = 0 = ∑⎢ ∫ αm π+α m π ⎦ m =1 ⎣ π bn = 1 2π is ( t ) sin nωt d ( ωt ) π ∫0 p 1 π+α m +δm ⎡ 1 α m +δm ⎤ Ia sin nωt d ( ωt ) − ∫ I a sin nωt d ( ωt ) ⎥ = ∑⎢ ∫ αm π+α m π ⎦ m =1 ⎣ π p 2I = a ∑ ⎡ cos nα m − cos n ( α m + δ m ) ⎤ ⎦ nπ m =1 ⎣ Version 2 EE IIT.. If mth pulse starts at ωt = α m and its width is δm .jntuworld. 16. and Idc is zero. the instantaneous input current is expressed in a Fourier series as is ( t ) = Idc + n =1.3 Pulse-width-modulation control. π S1 ωt ωt The details of output voltage and current waveforms of the converter are given.com v Ar -Ac vr vc π vg2 S1 S1 δm 0 αm (c) Fig. the average output voltage due to p number of pulses is found as p 2V p ⎡ 2 α m +δm ⎤ Vdc = ∑ ⎢ ∫ 2V sin ωt d ( ωt ) ⎥ = ∑ ⎡cos α m − cos ( α m + δm )⎤ ⎦ αm π m =1 ⎣ ⎦ m =1 ⎣ π If the load current with an average value of Ia is continuous and has negligible ripple. Kharagpur 10 www.3.com .e. if one pulse starts at ωt = α1 . even harmonics are absent..

The triangular waveforms are kept same. and then the pulse widths can be made uniform. The width are smaller at the centre of the carrier signal (sinusoidal). and I n = ( a 2 + b 2 ) n n 2 = bn 2 Sinusoidal Pulse Width Modulation (SPWM) Control Various types of modifications in PWM techniques have been proposed. the pulse widths are generated by comparing a triangular reference voltage vr of amplitude Ar and frequency fr. the lowest order harmonic is the fifth. Version 2 EE IIT.. One important method is sinusoidal pulse width modulation (SPWM) control.com . or text books on various PWM methods applied for inverters (dc-ac converters). It may be noted that. and increases as one goes to the start and end of the above signal.www..jntuworld.com So. the carrier signal is modified to care of this.jntuworld. It may be noted that the width of the pulses obtained are variable. For more on the matter as given earlier. with a carrier half sinusoidal voltage vc of variable amplitude Ac and frequency 2fs. ∑ α 2 I n sin ( nωt + φn ) 1 2 where φn = tan −1 ( a n b n ) = 0 . upto some point from the start and end of the cycle.4 shows the various waveforms.5 (module 5). 16. For different PWM methods used. the power factor is improved with various control methods discussed. the harmonic components of the voltage waveforms are also decreased or eliminated. The lower order harmonics one eliminated or reduced. the displacement factor is unity. In this type of control. The sinusoidal voltage vc is in phase with the input phase voltage vs and has twice the supply frequency fs. Fig.3. width four pulses per half cycle.. The widths of the pulses (and the output voltage) are varied by changing the amplitude Ar or the modulation index M from 0 to 1. the equation for is(t) is written as is ( t ) = n =1. For example. in the earlier case (multiple PWM control). The modulation index. the students can. 16. and so on. Different modifications have been suggested to take one such example. So. Kharagpur 11 www.4. and the power factor is improved. the pulse widths are uniform (equal). including the currents through thyristors and the input current and load current (assumed to be continuous). M is Ac/Ar. either study lesson #5. as the pulse width one small in the centre as shown in Fig.

16. but magnitudes vary. The function of the capacitor Version 2 EE IIT. the harmonics in the output voltage decrease. So. the harmonic frequency remains same. it is easier to filter it. the capacitor of higher value is needed to filter lower harmonic frequency. such that harmonics currents pass through it. The reactance of the capacitor should be low.Ia io Ia 0 Fig. say 100 Hz. For simple filter. Thus. a capacitor (C) is connected in parallel across the output of the diode converters with resistive (R) load. contains harmonics of 2f = 100 Hz. Kharagpur 12 www.4 Sinusoidal pulse-width modulation control.jntuworld. αm π δm π + αm π + αm + δ m 2π 3π π π + αm 2π 3π αm δm π 2π 3π ωt ωt ωt ωt Load current ωt Filters It is known that the output voltage waveform of a single phase full wave diode (uncontrolled) bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply.com v Ar Ac Reference signal Carrier signal vr vc 0 iT1 +Ia 0 iT2 +Ia 0 is +Ia 0 . The higher the harmonic frequency. whereas a lower value of C could be chosen for say. So. three phase converters. α is changed.jntuworld. . as the firing angle delay. The value of the capacitor chosen varies with the predominant harmonic frequency present. The harmonic frequency present in the output voltage waveforms of threephase half-wave and full wave (bridge) diode converters.www. it is necessary to filter out this and other harmonics from the output voltage to obtain dc component only.com . remain same. are 150 Hz (3f) and 300 Hz (6f) respectively. It may also be noted that the harmonics present in the output current waveforms of the converters with resistive (R) load. For phase-controlled thyristor converters.

one is the voltage level. These are all simple cases. known to those. also resulting in higher peak anode current and peak inverse voltage rating.jntuworld. It may be noted that. Version 2 EE IIT. which is the output voltage of the converter. fed to it. But two problems arise. The voltage across the capacitor changes as per the input voltage. with higher dc output voltage. As shown. Kharagpur 13 www.. A single stage filter (L-C) is used to reduce the harmonic components in both voltage and current waveforms of a single phase full wave diode bridge converter with resistive (RL) load as shown in Fig. such that nth harmonic ripple content passes through the filter capacitor (C). So. and the sign of it opposes the cause. Low Pass (L-C) Filter A passive low pass filter is the ideal choice. the impedance of the series path must be much greater than that of the capacitance. The reactance of the inductor increases. the capacitive reactance chosen is total load impedance divided by a factor of 10 The advantages are small ripple factor with just a single stage (L-C) used. thus reducing the harmonic component in the current waveform. when the current through it changes. The size also may be large. thus opposing the changes in current.e. needing an iron-cored coil. Same is the case with the filter used to reduce the harmonic content of the output current waveform for the above converters with resistive (R) load. by Faraday’s laws. C & R is needed to get an optimum filter needed to reduce or eliminate the harmonics in both output voltage and current waveforms. i.www. as the capacitor voltage decreases. Here. the value of the inductor needed is high. the current is not allowed to change much. In actual practice. The main advantage is poor voltage regulation. an inductor (L) is connected in series with the load. As stated earlier. a combination of L. Instead of a capacitor in parallel. for the lowest harmonic frequency of 100 Hz. if the power or current level is high. L C or R must be properly rated for the voltage or current level as needed. as an inductor is placed in series with the load. who have studied the circuit (network) theory. 1 2 2 ZL = ( R L ) + ( n ω L ) >> n ωC The condition to be satisfied is 10 ZL = or ZL 10 = 1 ( n ω C ) n ωC and the effect of load is negligible. Also.jntuworld. for example a three-phase bridge converter. and the capacitor voltage tries to stabilize at the overage value of the output voltage. 16. load resistance being connected across it.com may also be explained in the following way. the other is the power or current level. L. induced voltage (emf) appears across the inductor.5(a). All the elements used. a smaller value of the inductor is needed to filter higher harmonics.com .

Only a single stage (L-C) filter may be used. as given earlier.www. the ripple factor (RF) is RF = 1 ⎡ 2 ( 4fR L C1 − 1) ⎤ ⎣ ⎦ For a chosen ripple factor. Kharagpur 14 www. instead of a single stage one given earlier. if the values of rated output voltage and current for the converter are known or given. If a single capacitor (C1) is used as a single stage one.2). This circuit offers satisfactory operation at light loads. the value of C1 may be computed. instead of L-C. (b) Two-stage filter Two Stage Filter A two-stage filter (Fig. L L O A D C2 B (b) Fig. at heavy load. as the frequency in the output voltage in thus case is much higher than the harmonic frequency (100 Hz) for the single phase full wave ac-dc converter (rectifier) circuit described here.1-3. These filters may also be used at the output of the dc-dc converter circuits described in module 3 (lessons $3. but considerably poor voltage regulation due to drop in R. 16.com + A iL L D 1-φ + Supply (50Hz) - D1 G is D2 C H L O A D RL D4 - D3 B (a) + A R C1 E RL.5 (a) Low pass (L-C) filter.com . In this case. followed by second stage (R-C). Version 2 EE IIT.5(b)) may be used. The size may be reduced as the size of R is smaller than that of L. 16.jntuworld.jntuworld. the first one is only capacitive (C1) to reduce the harmonic content in voltage waveform. resulting in higher ripple content.

recently due to increasing use of power electronic units. a low pass (L-C) filter (Fig.6b) is used on the input (source) side to reduce the harmonic components in the input current. there are harmonic components present in it.com Harmonic Reduction The harmonic reduction schemes are presented in brief.www. The important point to be noted is that.jntuworld.6(a) Output and input currents. The inductors used tend both to improve the power factor and also reduce harmonics as given earlier.6a). so as to decrease the harmonic content in the input current.jntuworld.com . or make it sinusoidal. utility or electricity supply agencies (boards). are presented. in brief. though additional losses occur in the inductors. iL Ia 0 is Ia 0 -Ia π(T/2) 2π(T) ωt Fig. Kharagpur 15 www. Low pass (L-C) filter circuit on ac side Before going into the aspect. Assuming that output (load) current is constant (dc) without any ripple. but conduction losses in the diodes are reduced. improved load power factor is achieved. Two schemes – (a) passive (filter) circuits and (b) Active shaping of input line current. 16. 16. the ac input (source) current is square wave in nature (Fig. If a Fourier analysis of the above current is done.5a. let us take a rebook at the input current drawn in the circuit shown in Fig. as this current changes sign. The overall energy efficiency remains the same. have restricted that the power is drawn by the consumers. and at the same time. when the input voltage changes sign. 16. Version 2 EE IIT. 16. Just as filters have been used on the output (dc) side.

6 (b) Low pass (L-C) filter on source (AC) side Active Shaping of Input (line) Current By using a power electronic converter for current shaping. the current.7a. Version 2 EE IIT.com .1. it is possible to shape the input current drawn by the single phase bridge converter (rectifier) to be sinusoidal and also in phase with the input voltage. and also in phase with the voltage. at the full wave bridge converter output. vs. Based on the above. iL and vs have the same waveform as shown in Fig. The basic principle of operation is as follows. is desired to be sinusoidal.7b. as shown in Fig. At the input side. 16.jntuworld. Kharagpur 16 www. is used as the current shaping circuit. 16. Therefore. power losses and size of the circuit used should be small. is.www. The choice of the power electronic converter is based on the following considerations: • No need for electrical isolation between the input (dc) and output (dc) sides • the power flow is always unidirectional from the utility side to the equipment • the cost. 16.jntuworld.7c.com + iS + C L1 L2 G H A B Fig. a step-up (boost) dc-dc converter as described in next module (#3). lesson 3. as shown in Fig. 16.

The reference input. harmonic reduction and filters. Here.jntuworld. is made sinusoidal having L same (line) frequency. the switch. So. as only a brief discussion is presented here. L-C & R-C) used for the reduction in harmonic content of output voltage and current waveforms of the ac-dc Version 2 EE IIT.7 Active harmonic filtering: (a) step-up converter for current shaping. ωt The control used is constant tolerance-band one. (c) │vs│ and iL. S may be L a self-commutated switching device. 16.www. S. i* .com Step-up converter iL id + + vs │vs│ (a) vs is 0 Ld Cd ic Iload + ˆ vd (Vd > Vs ) - ωt (b) │vs│ iL 0 (c) Fig. which is sinusoidal. various types of filters (C. is controlled. are presented. the input current. Firstly. Then. the current. iL. With a pre-selected value of Irip.jntuworld. For detail. viz extinction angle control. iL is forced to be in tolerance band (iL + Irip/2) and (iL – Irip/2) by controlling the status of the switch. such that peak-to-peak ripple Irip in iL remains constant. (b) line waveforms. three important points – power factor (pf) improvement. In this lesson. iL. symmetrical angle control and pulse width modulation (PWM) control. any text book may be used by the student. last one in this module. i* . are described in detail with relevant waveforms. three methods. follows the reference input. Kharagpur 17 www. power transistor or MOSFET.com . As described later (module #3).

jntuworld. are discussed. in brief. all types of single-phase and three-phase converters. with the equations for the value of the filter components needed. with other relevant points. Version 2 EE IIT. In this module of ac-dc converter consisting of eight lessons. Kharagpur 18 www.com converters.www.com . harmonic reduction aspect is taken up.jntuworld. Lastly. have been thoroughly discussed.

jntuworld.com . Kharagpur 1 www.com Module 3 DC to DC Converters Version 2 EE IIT.www.jntuworld.

com Lesson 17 Types of Basic DC-DC Converters Version 2 EE IIT. Kharagpur 2 www.jntuworld.www.jntuworld.com .

or a reverse (negative) voltage is applied between anode and cathode terminals. So.com . Keywords: DC-DC converter circuits. boost and buck-boost The expressions for the output voltage in the above circuits. or a positive (forward) voltage is applied between anode and cathode terminals. firstly. MOSFETs are used as a switching device in low voltage and high current applications. one of the most important being Switched Mode Power Supply (SMPS). the thyristor is connected in series with load to a dc supply. three basic types of dc-dc converter circuits − buck. in dc-dc converters. Then. which is termed as self-commutated device. It may be noted that. whereas boost converter (dc-dc) is a ‘step-up chopper’. boost and buck-boost. This device (NPN transistor) is switched on by a positive current through the base and emitter. boost and buck-boost converters (dc-dc). and also half-controlled and full-controlled ones. unlike thyristors. as the turn-on and turn-off time of MOSFETs are lower as compared to other switching devices. the various types of circuits used in both single-phase and three-phase ac-dc converters. which can also be turned off by a negative current fed at its gate. are presented. where another thyristor is often used. load. In all of these circuits. Buck. the frequency used in GTObased choppers can be increased. a thyristor is to be force-commutated. instead of thyristor. where thyristors or GTOs are used. Earlier. Thyristor choppers. when application requires high voltage. The collector is connected to a positive voltage. The turnon and turn-off times of GTOs are lower than those of thyristors. dc-dc converters were called ‘choppers’. a power device is used as a switch. termed as buck. Later. This device earlier used was a thyristor.jntuworld. no buck-boost type was used. which is turned on by a pulse fed at its gate. DC-DC Converters There are three basic types of dc-dc converter circuits. In this lesson − the first one in this module (#3). requiring proper control circuit. Output voltage and current. thus reducing the size of filters. Similarly. the expressions for the output voltage in the above circuits. R-L-E. In all these circuits. the frequency used for the dc-dc converters using it (MOSFET) is high. It may be noted here that buck converter (dc-dc) is called as ‘step-down chopper’.e. i. This includes half-wave and full-wave. for which additional circuit is to be used. With the advent of bipolar junction transistor (BJT). GTO’s came into the market.www. These converters are now being used for applications. are derived. The different control strategies employed are briefly described.. and then switched off by withdrawing the above signal. Now-adays.com Instructional Objectives Study of the following: • • Three basic types of dc-dc converter circuits − buck. were discussed in detail.jntuworld. boost and buck-boost. Kharagpur 3 www. Insulated Gate Bi-polar Transistors (IGBT) are preferred over Version 2 EE IIT. So. with inductive (R-L) and battery (or back emf = E) load Introduction In the last module (#2) consisting of eight lessons. In the case of chopper. thus. it is used as a switch. The thyristor turns off. Step-down (buck) and step-up (boost) choppers. with inductive (R-L) and battery (or back emf = E). reducing the size of filters as stated earlier. assuming continuous conduction. when the current decreases below the holding current.

com . thus the frequency can be increased in the converters using them.1a.e.. a battery (or back emf) is connected in series with the load (inductive). which is provided by the diode. during the period. this dc-dc converter is termed as buck one. Similarly. 17. So.1(b): Output voltage and current waveforms The output voltage and current waveforms of the circuit (Fig.jntuworld. when the switch is ON. + S Switch + Vs DF Fig.1b.. 17. in the absence of the above diode. due to reason given later.1a) are shown in Fig. the high induced emf of the inductance. 17. In some cases. The output voltage is same as the input voltage.jntuworld. for which a device as described earlier belonging to transistor family is used.www.. otherwise. Buck Converters (dc-dc) A buck converter (dc-dc) is shown in Fig. If the switching device used is a thyristor. Kharagpur 4 www. 17. Due to the load inductance. Only a switch is shown.com BJTs.e. as the load current tends to decrease. 17. The switch is turned on at t = 0 . as the turn-on and turn-off times of IGBTs are lower than those of power transistors (BJT). a device) is turned off. i. the load current must be allowed a path.e. i.1(a): Buck converter (dc-dc) v0 Vs V0 TON t T i0 TOFF V0 L I0 L O A D t Fig. Also a diode (termed as free wheeling) is used to allow the load current to flow through it. may cause damage to the switching device. mostly self-commutated devices of transistor family as described are being increasingly used in dc-dc converters. TON ≥ t ≥ 0 . This is Version 2 EE IIT. The load is inductive (R-L) one. this circuit is called as a step-down chopper. and then turned off at t = TON . when the switch (i. v0 = Vs . as the output voltage is normally lower than the input voltage.

com . So. D F now conducts. for which a device belonging to transistor family is generally used. T ≥ t ≥ TON . due to turn-on delay of the device used. the duty ratio (k) is less than 1.jntuworld. 17. An inductance. The load current increases in the ON period. 17. but has some positive value. as it flows in the diode. During the next time interval. The load current is assumed to be continuous as shown in Fig. as the input voltage appears across the load. as compared to their position in the buck converter (Fig. + Is L D + I0 Vs S V0 Switch Fig.. With T kept as constant.jntuworld. due to requirement of turn-off time of the device.0. Kharagpur 5 www.com called ON period. the average value of the output voltage is.www. the range of duty ratio is reduced. So. its range being 1. T. the output voltage is zero. Boost Converters (dc-dc) A boost converter (dc-dc) is shown in Fig. the duty ratio (k) is not zero. The frequency is f = 1 / T . Similarly. L is assumed in series with the input supply. 17. i. but is positive at the end of the time period.2(b): Waveforms of source current (iS) Version 2 EE IIT. as the diode. The load is of the same type as given earlier. Also.1a). a variable dc output voltage is obtained from a constant dc input voltage. Only a switch is shown. as the duty ratio is increased. v0 = 0 . with the time period being T = TON + TOFF . and it (load current) decreases in the OFF period. 17.e. The OFF period is TOFF = T − TON . V0 = 1 1 ∫ v0 dt = T T 0 T TON ∫V 0 s ⎛T ⎞ dt = Vs ⎜ ON ⎟ = k Vs ⎝ T ⎠ The duty ratio is k = (TON / T ) = [TON / (TON + TOFF )] . 17. The position of the switch and diode in this circuit may be noted.0 . the average output voltage increases.1b.2(a): Boost converter (dc-dc) I2 I1 L O A D 0 TON TOFF T 2T Fig. It may be noted that the output voltage is lower than the input voltage.2a. Normally.0 ≥ k ≥ 0. Also. a diode is used in series with the load. The inductance of the load is small.

As the current through L increases.0 ≥ k ≥ 0. with ( d i s d t ) being negative. with ( d i d t ) being positive. if no battery (back emf) is connected in series with the load. So. TON . As the current through L decreases.2b. positive. di d i s (Vs − V0 ) Vs = V0 + L s = or. as contrasted with the previous case of buck converter (dc-dc). S (i.com . This is. So. the OFF period being TOFF = T − TON . as the output voltage is assumed to be nearly constant at v0 ≈ V0 . I 2 − I1 = I max − I min = [(V0 − Vs ) / L] TOFF . Similarly. Kharagpur 6 www. the current varies linearly from I 2 ( I max ) to I 1 ( I min ) during the time interval. The ON time interval is TON = k T .0). Equating the two equations. thus. and the duty ratio is. TOFF . ( T = TON + TOFF ) is the time period. the ON period being TON . because the minimum value is higher than the minimum (0. with its direction being in the same direction as shown (same as in the earlier case). Firstly. 17. dt dt L The source current waveform is shown in Fig. As stated in the previous case. dt dt L The switch. S is put OFF during the period. The expression for the output voltage can be obtained by using other procedures. the left hand side of L being -ve. In this case. the left hand side of L being +ve. from which the average value of the output voltage is. k = (TON / T ) = [TON / (TON + TOFF )] . di d i s Vs = Vs = L s or. being of the same polarity. the device) is put ON (or turned ON) during the period. the induced emf (taken as –ve in the equation given later) is added with the supply voltage. The current from the source ( i s ) flows in the inductance L. I 2 − I 1 = I max − I min = (Vs / L ) TON . So. (V s / L ) T ON = [(V 0 − V s ) / L ] T OFF . ⎛ T ⎞ ⎛ T ⎞ ⎛ ⎞ 1 ⎛ 1 ⎞ ⎟ = Vs ⎜ V0 = V s ⎜ ⎜T ⎟ ⎜ T − T ⎟ = Vs ⎜ 1 − (T / T ) ⎟ = Vs ⎜ 1 − k ⎟ ⎟ ⎜ ⎟ ⎠ ⎝ ON ⎠ ON ⎝ OFF ⎠ ⎝ ⎝ ⎠ The time period is T = TON + TOFF . the range of k is reduced. which is derived later. So. and the maximum value is lower than the maximum (1. as Vs < V0 . the polarity of the induced emf is taken as say. TON ≥ t ≥ 0 . As stated earlier. The equation for the circuit is. using the expression for d i s d t during this time interval. the load inductance is small. when a selfVersion 2 EE IIT. this is called boost converter (dc-dc). for reasons given there. TOFF . with its range as 1. The equation for the circuit is. the current varies linearly from I 1 ( I min ) to I 2 ( I max ) during the time interval.com The operation of the circuit is explained. The current ( is = i0 ) decreases linearly in the time interval.www.0). The output voltage is zero ( v0 = 0 ). As shown.e.jntuworld.jntuworld.0 . keeping the current ( is = i0 ) in the same direction. the induced emf reverses. T ≥ t ≥ TON . the switch.. which are also valid here. The value of current increases linearly with time in this interval. using the expression for d i s d t during this time interval. and also as stated earlier. the source current is assumed to be continuous. the output voltage is higher than the input voltage.

during the time interval. The inductor current tends to decrease. The variation (range) of the output voltage can be easily computed. 17. L is connected in parallel after the switch and before the diode. V0 being opposite to that of the input voltage. the supply current ( is ) flows through the path.3(b): Inductor current (iL) waveform Then. The inductor. with ( d i L d t ) being positive. 17.www. during the time interval. S is put OFF. TON . Also. S and L. Kharagpur 7 www. When the switch. di d i L Vs = Vs = L L or. Vs . parallel combination of load & C.3.jntuworld. Instead. The output voltage remains nearly constant. the switch. Buck-Boost Converters (dc-dc) A buck-boost converter (dc-dc) is shown in Fig. A capacitor. and diode D. for which a device belonging to transistor family is generally used. The connection of the diode may be noted. 17.2a). ( d i L d t ) is negative now. The polarity of the induced voltage is same as that of the input voltage. The polarity of the output voltage is opposite to that of input voltage here. with the polarity of the induced emf reversing. as the capacitor is connected across the load. TOFF . The load is of the same type as given earlier.jntuworld. this is termed as step-up chopper. as compared with its connection in a boost converter (Fig. Version 2 EE IIT. a diode is used in series with the load. The currents through both source and inductor ( i L ) increase and are same. The equation for the circuit is. C is connected in parallel with the load. Vs . if thyristor is used in its place. S is put ON.com .com commutated device is used as a switch. Only a switch is shown. 17. the polarity of the output voltage.3(a): Buck-boost converter (dc-dc) IL2 IL1 + TON TOFF T 2T Fig. dt dt L Is Switch I0 L O A D + S Vs L IL V0 C Fig. The path of the current is through L.

Control Strategies In all cases. using (V s / L ) T ON = (V 0 / L ) T OFF . the expression for d i L d t during this time interval. TON . For k = 0.com . Also it may be called as step-up/down chopper. the output voltage can be varied by varying ON time. Kharagpur 8 www. or time period T constant. from which the average value of k = (TON / T ) = [TON / (TON + TOFF )] . As stated earlier. dt dt L The inductor current waveform is shown in Fig.25 (25%). I L 2 − I L1 = (Vs / L ) TON . the output voltage is higher than the input voltage.4. The range of k is somewhat reduced due to the reasons given earlier. Note that I L1 and I L 2 are the minimum and maximum values of the inductor current respectively.jntuworld. 17. Two cases with duty ratios. it is shown that the average value of the output voltage can be varied. For the range 0. di d i L V0 L L = V0 = or. k as (a) 0. This is also called as pulse width modulation control (PWM). Time-ratio Control In the time ratio control the value of the duty ratio. thus.3b. TOFF .75 (75%) are shown in Fig. Constant Frequency Operation In this control strategy.5 . ⎛T ⎞ ⎛ T V0 = Vs ⎜ ON ⎟ = Vs ⎜ ON ⎜T ⎟ ⎜T −T ON ⎝ OFF ⎠ ⎝ The time period is T = TON Similarly. The two types of control strategies (schemes) are employed in all cases.jntuworld. thus. and (b) Current limit control. These are: (a) Time-ratio control. I L 2 − I L1 = (V0 / L ) TOFF .com The equation for the circuit is.5 > k ≥ 1. The ON time interval is TON = k T . and variable frequency operation. So. the output voltage is lower than the input voltage. TON is varied. and the duty ratio is. Hence. making it a boost converter (dc-dc). It may be noted that the inductor current is assumed to be continuous. So. this circuit can be termed as a buck-boost converter. TON . which are constant frequency operation. the output voltage is. the current varies linearly from I L 2 to I L1 during the time interval. using the expression for d i L d t during this time interval.0 .5 . keeping the frequency ( f = 1 / T ). 17. The expression for the output voltage can be obtained by using other procedures. Equating the two equations. It may be observed that. So. There are two ways. the current varies linearly from I L1 to I L 2 during the time interval. the ON time. ⎞ ⎛ (TON / T ) ⎞ ⎛ k ⎞ ⎟ = Vs ⎜ ⎟ ⎜ 1 − (T / T ) ⎟ = Vs ⎜ 1 − k ⎟ ⎟ ⎝ ⎠ ON ⎠ ⎝ ⎠ + TOFF . and (b) 0. making it a buck converter (dc-dc).www. k = TON / T is varied. for the range 0 ≥ k > 0. Version 2 EE IIT. the output voltage is equal to the input voltage.

k = TON / T .www. the frequency ( f = 1 / T ). TOFF constant. TOFF constant.jntuworld. Two cases with (a) the ON time.com . with the change in duty ratio.com Load-voltage v0 TON TOFF V0 k = 0. This is also called as frequency modulation control. TON constant. TON constant. are shown in Fig.jntuworld. The output voltage can be varied in both cases. keeping either (a) the ON time. or (b) the OFF time. with variable frequency or time period ( T ). or time period T is varied.5.75 t Fig.25 T t V0 v0 TON T TOFF k = 0. and (b) the OFF time. Kharagpur 9 www. Version 2 EE IIT.4: Pulse-width modulation control (constant frequency) Variable Frequency Operation In this control strategy. 17. 17.

in frequency modulation technique. (b) For the control of a duty ratio.www. the constant frequency system using PWM is the preferred scheme for dc-dc converters (choppers). such as signaling and telephone line. which is undesirable. These are: (a) The frequency has to be varied over a wide range for the control of output voltage in frequency modulation. As such.75 t v0 TOFF T v0 TOFF TON k = 0. may make the load current discontinuous. Version 2 EE IIT. Thus.75 t Fig.jntuworld. frequency variation would be wide. (c) The large OFF time in frequency modulation technique. therefore.25 t Load voltage TON T (b) Constant TOFF k = 0.com v0 TON k = 0.25 t v0 TON T TOFF (a) Constant TON k = 0. Filter design for such wide frequency variation is. there is a possibly of interference with systems using certain frequencies.5: Output voltage waveforms for variable frequency system There are major disadvantages in this control strategy. Kharagpur 10 www. quite difficult.jntuworld.com . 17.

Kharagpur 11 www. buck converter (dc-dc) through the diode. In this case. 17. In the current limit control strategy. the switch is turned OFF. This type of control is possible.com Current Limit Control As can be observed from the current waveforms for the types of dc-dc converters described earlier.jntuworld. This is shown in Fig. varying between I max and I min . When the current exceed upper (maximum) limit. This is used only. The ripple in the load current can be reduced. when the load has energy storage elements. 17. When it reaches lower (minimum) limit. boost and buckboost. either with constant frequency. and decreases exponentially.www. first one in this module (#3).jntuworld. or constant ON time.e. along with the operation and the derivation of the expressions for the output voltage in each case. the switch is turned ON. TON . This in turn increases the frequency. L. the current is continuous. In the next lesson − second one. of dc-dc converters (choppers) are presented. the expression for the maximum and currents for continuous conduction in buck dc-dc converter will be derived. The different strategies employed for their control are discussed. D F . the three basic circuits − buck. The reference values are load current or load voltage. so that the current is maintained between two (upper and lower) limits.com . the switch in dc-dc converter (chopper) is turned ON and OFF. assuming continuous conduction. thereby making it minimum. which decides the frequency used for switching. the current changes between the maximum and minimum values. I max i0 I min t v0 TON TOFF T Fig. if the difference between the upper and lower limits is reduced.6: Current limit control t In this lesson. if it (current) is continuous. inductance. During OFF period. Version 2 EE IIT.6. i. thereby increasing the switching losses. the current freewheels in say.

com .jntuworld.com Module 3 DC to DC Converters Version 2 EE IIT.www. Kharagpur 1 www.jntuworld.

com .www. Kharagpur 2 www.com Lesson 18 Analysis of Buck Converter (DC-DC) Circuit Version 2 EE IIT.jntuworld.jntuworld.

ripple factor. Lastly. the analysis of the buck converter (dc-dc) or step-down chopper circuit. were presented. the operation and the derivation of the expressions for the output voltage for the above dc-dc converters. assuming continuous conduction • • Derivation of the expressions for the maximum and minimum load currents Calculation of the following: (a) the duty ratio for the limit for continuous conduction (b) the average value and the ripple factor of the load current (c) the harmonic components of the output voltage waveform Introduction In the last lesson − first one in the module (#3). the procedure for the calculation of following expressions ─ the duty ratio for the limit of continuous conduction. and the harmonic components of the output voltage waveform. 18.www.com + V0 L + E R LOAD . Keywords: Buck converter (dc-dc). assuming continuous conduction. 18. Buck Converter (DC-DC) The circuit of the buck converter (dc-dc) or step-down chopper using thyristor. using thyristor as a switching device. L & E. is presented in detail.1a is replaced by a thyristor here. including current waveforms. Step-down chopper. with inductive (R-L) and battery (or back emf = E) load. with inductive (R-L) and battery (or back emf = E) load. In this lesson − the second one in this module. Kharagpur 3 www. 17. are described in detail. the different control strategies used were briefly discussed. of the output (load) current. The switch in Fig.jntuworld. the average value and the ripple factor. with inductive (R-L) and battery (or back emf = E) load.jntuworld. Starting with the derivation of the expressions for the maximum and minimum load currents. harmonic analysis.2. such as buck.1. Version 2 EE IIT. and (b) continuous conduction are shown in Fig. 18. Output (load) current – maximum and minimum values. boost and buck-boost. is shown in Fig.1: Step-down chopper circuit using thyristor. The output (load) voltage and current waveforms for both (a) discontinuous. i0 + A K Switch G Vs DF Fig. are also shown. Then. such as R. were described in detail. where the components of the load.com Instructional Objectives Study of the following in respect of the buck converter (dc-dc) circuit. average value. firstly the circuits of the various types of dcdc converters (choppers).

TOFF iD t t t Version 2 EE IIT. Kharagpur 4 www.jntuworld.www.2: Two modes operation of the chopper.com Ig 0 io 0 v0 VS E 0 TON T (a) Discontinuous load current Ig TOFF t t t 0 io Imax Imin 0 iT v0 VS V0 0 TON T (b) Continuous load current Fig. 18.com .jntuworld.

( ) ⎡ (V − E ) ⎤ I max = ⎢ s 1 − e −TON / τ + I min e −TON / τ R ⎥ ⎣ ⎦ ⎡ (V − E ) ⎤ −TON / τ or. The expression for the V S = R i0 + L load current is. VS − E = R i0 + L 0 dt dt The current is the load current. i.jntuworld. Then the cycle repeats. i. L changes polarity. D F turns ON at that time. Mode 1: The equation for the load (output) current in the circuit during this time interval.. I max − I min e −TON / τ = ⎢ s ⎥ 1− e ⎣ R ⎦ This is the first expression obtained for mode 1 between I max and I min . are I min and I max respectively. The values of the load current ( i0 ) at t = 0 and t = TOFF . i0 = A e − t / τ + B . 0 ≤ t ≤ TOFF is.e. assuming continuous conduction. Mode 2: The equation for the load (output) current in the circuit during this time interval. ⎡ (V − E ) ⎤ −t / τ i0 = ⎢ s + I min e −t / τ ⎥ 1− e ⎣ R ⎦ At t = TON . the second one will be derived for mode 2..com Maximum and Minimum Values of the Load Current The procedure for finding the maximum and minimum of the load current. D F during this time interval. Kharagpur 5 www. i0 = I max . as the load current starts decreasing. The induced emf in the load inductance L. the load current increases.1). During this time period. when the thyristor is turned OFF by auxiliary circuit (not shown in Fig. The values of the load current ( i0 ) at t = 0 and t = TON . when the thyristor is turned ON. Version 2 EE IIT. is described. − E = R i0 + L 0 dt dt It may be noted here that the time ( t = 0 ) is taken here from the start of mode 2. Mode 2 starts at t = TON . with the voltage across the diode now being positive. the end of mode 1. and continues till t = TON . are I max and I min respectively. Similarly. Mode 1 starts at t = 0 .e. This continues till t = T . is positive. and the diode. and the induced emf in the load inductance. 0 ≤ t ≤ TON is. opposing it. and time constant is. i0 = A e − t / τ + B where A and B are constants. having the same polarity as that of the input voltage. There are two modes of operation. τ = L / R . A = I min − [(Vs − E ) / R] Substituting the values of A & B. At t = 0 . The current is the load current.jntuworld. i0 = B = [(Vs − E ) / R] So. The operation of the chopper circuit has been discussed in the earlier lesson.com . 18. i0 = A + B = I min At t = ∞ .www. di di 0 = R i0 + L 0 + E or. d i0 di +E or. ( ) ( ) The expression for the load current is. and the current through the diode. with the diode. the expression for the load current is. So. same as the source current during this time interval. end of the time period. D F being OFF at that time.

when the minimum current. and −R T / L ⎥ ⎝ R ⎠ ⎣ 1− e ⎦ ⎝R⎠ RT / L ⎛ Vs ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞ I min = ⎜ ⎟ ⎢ R T / L ⎥−⎜ ⎟ −1 ⎦ ⎝ R ⎠ ⎝R⎠ ⎣ e Ripple content in the Load Current As given earlier. the ripple content of the current is.com At t = 0 .www. I max and I min are derived as. the expression becomes. or. time period. or duty ratio. T being kept constant. Therefore. 1 − e −T / τ ⎝R⎠ ⎣ ⎦ its per unit value being. I min goes to zero. So. So.com . depending on the circuit parameters. A = I max + (E / R ) Substituting the values of A & B. The Duty Ratio (k) for the Limit of Continuous Conduction The current waveforms for both continuous and discontinuous conduction are shown in Fig. ⎛E⎞ i0 = −⎜ ⎟ 1 − e −t / τ + I min e −t / τ ⎝R⎠ At t = TOFF . −T / τ ⎛ V ⎞ ⎡1 − e ON ⎤ ⎛ E ⎞ I max = ⎜ s ⎟ ⎢ −⎜ ⎟ −T / τ ⎥ ⎝ R ⎠ ⎣ 1− e ⎦ ⎝R⎠ T /τ ⎛ Vs ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞ I min = ⎜ ⎟ ⎢ T / τ ⎥−⎜ ⎟ ⎝ R ⎠ ⎣ e −1 ⎦ ⎝ R ⎠ or.0 pu (100%). the turn-off time. The output current. i0 = B = −(E / R ) So. ( ) ⎛E⎞ I min = − ⎜ ⎟ 1 − e −TOFF / τ + I max e −TOFF / τ ⎝R⎠ ⎛E⎞ or. i0 = A + B = I max At t = ∞ . i0 may go to zero during this interval. Using the duty ratio. From the waveforms. the currents. the expression for the load current is. Therefore. (I max − I min ) = ⎡ 1 − e − k T /τ 1 − e − (1−k ) T / τ ⎤ ⎥ (Vs / R ) ⎢ 1 − e −T / τ ⎣ ⎦ ( ( )( ) ) ( ( )( ) ) The current ( Vs / R ) is taken as 1. − RT / L ⎛ V ⎞ ⎡1 − e ON ⎤ ⎛ E ⎞ I max = ⎜ s ⎟ ⎢ − ⎜ ⎟ . k . ( ) ( ) From these two expressions. k = TON / T . 18.2. the limit of continuous conduction is reached. the load (output) current varies between the maximum and minimum values ( I max and I min ). i0 = I min . I max e −TOFF /τ − I min = −⎜ ⎟ 1 − e −TOFF / τ ⎝ R⎠ This is the second expression obtained for mode 2 between I max and I min . Version 2 EE IIT. for a low value of TON .jntuworld. −T / τ − (T −TON ) / τ ⎤ ⎛ Vs ⎞ ⎡ 1 − e −TON / τ 1 − e −TOFF / τ ⎤ ⎛ V ⎞ ⎡ 1 − e ON 1 − e I max − I min = ⎜ s ⎟ ⎢ ⎥=⎜ ⎟ ⎢ ⎥ 1 − e −T / τ 1 − e −T / τ ⎝R⎠ ⎣ ⎦ ⎝R⎠⎣ ⎦ The above expression for ripple content is independent of battery voltage or back emf (E). it is observed that. TOFF is large.jntuworld. ( ( )( ) ) ( ( )( ) ) − k T /τ 1 − e − (1−k ) T / τ ⎤ ⎛ Vs ⎞ ⎡ 1 − e I max − I min = ⎜ ⎟ ⎢ ⎥. Kharagpur 6 www.

k ′ .jntuworld. can also be computed by using the expressions for the currents separately. T is zero. This value can also be written as. if k is lower than the above duty ratio. the duty ratio for limit of continuous conduction is. This is. These two expressions are not included here. 18. The symbols. TON TOFF ⎤ ⎛ 1 ⎞ ⎡TON ⎤ ⎛ 1 ⎞ ⎡TOFF ⎤ ⎛ 1 ⎞⎡ I av = ⎜ ⎟ ⎢ ∫ i01 (t ) dt + ∫ i02 (t ) dt ⎥ = ⎜ ⎟ ⎢ ∫ i01 (t ) dt ⎥ + ⎜ ⎟ ⎢ ∫ i02 (t ) dt ⎥ = ( I T ) av + ( I D ) av . T a n & bn are the maximum values of the sine and cosine components of the harmonics of order n.2. including some described earlier. TON < t < 0 and TOFF < t < 0 (the time ( t = 0 ) is taken as the beginning of OFF period (mode 2)) respectively.2b) is obtained as I av = (k Vs − E ) / R .b.www. and it becomes discontinuous. but are available in text book. Kharagpur 7 www.com T /τ eTON / τ − 1 ⎛ E ⎞ ⎛ V ⎞ ⎡ e ON − 1⎤ ⎛ E ⎞ or. 18. The average values of the currents in the thyristor (I T )av and diode (I D )av . because the average value of L (di / dt ) over the time period. as the average value of the output voltage is k Vs . This voltage is periodic in nature and also independent of the parameters of the load. k ′ . i01 & i02 . if the actual duty ratio. are given here. Fourier Analysis of the Output Voltage Waveform The output (load) voltage waveform for continuous conduction is shown in Fig. =⎜ ⎟= g I min = ⎜ s ⎟ ⎢ T / τ −⎜ ⎟= 0 ⎥ e T / τ − 1 ⎜ Vs ⎟ ⎝ R ⎠ ⎣ e −1 ⎦ ⎝ R ⎠ ⎝ ⎠ where g = (E / Vs ) So. [ ( )] The Average Value of the Output Current The average value of the output (load) current for continuous conduction (Fig. If the expression is derived by substituting the currents.com .jntuworld. k is more than the above duty ratio. Version 2 EE IIT. ⎝T ⎠⎢ 0 ⎥ ⎝T ⎠⎢ 0 ⎥ ⎝ T ⎠⎢ 0 ⎥ 0 ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ where i01 and i02 are the output (load) currents in the time intervals. its value comes out to be the same as given earlier. k ′ = (TON / T ) = (τ / T ) log e 1 + g eT / τ − 1 The output (load) current is continuous. present in the output voltage waveform respectively. v0 = Instantaneous value of the output (load) voltage Vs = Source (input) voltage (constant) V0 = Average value of the output voltage T = TON + TOFF = Time period of the thyristor chopper (step-down)* TON = Time interval for which the thyristor is ON* TOFF = T − TON = Time interval for which the thyristor is OFF* f = 1 / T = Frequency (Hz) for the thyristor chopper (step-down)* ω = 2 π f = Angular frequency (rad/s) θ = ω t = Angle (rad) ω T = 2 π = Angle (rad) for time period. All these values of the currents can also be obtained by using other procedure.

∞ ⎛ 2V ⎞ v0 = V0 + ∑ ⎜ s ⎟ (sin π n k ) (sin (nθ + (π 2) − (π n k )) ) ⎜ ⎟ n =1 ⎝ n π ⎠ ∞ ∞ ⎛ 2V ⎞ ⎛ 2V ⎞ = V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos [ nθ − (n π k ) ]) = V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos[n (θ − π k )]) The n =1 ⎝ n π ⎠ n =1 ⎝ n π ⎠ maximum value of the fundamental component is. The rms value of nth harmonic component = cn / 2 * It may be noted that. and vice versa.1). Kharagpur 8 www. The output (load) voltage waveform for one time period T . The magnitude of the maximum (or rms) value of the harmonic components decreases as its order (n) increases. is. when the thyristor (device) in the step-down chopper (Fig. or conducting. the expression is. v0 = 0 for T < t < TON In terms of the Fourier components.e.jntuworld. D F is conducting (ON). Vor = (V0 ) 2 + ∑ (cn / 2 ) 2 = (V0 ) 2 + ( 1 ) ∑ (cn ) 2 2 n =1 n =1 ∞ ∞ The rms value is computed as. and its phase angle (rad) is. θ1 = (π 2) − (π k ) . when the thyristor (device) is OFF.jntuworld.com cn & θ n are the maximum value (amplitude). Substituting the above values of cn & θ n . c1 = ((2Vs ) π ) (sin π k ) . which has been derived in lesson #17 (module 3). or buck converter (dc-dc). 18. the diode.. the diode. Version 2 EE IIT. v0 = Vs for TON < t < 0 .com . and the other relationships are an = cn cos θ n and bn = cn sin θ n . and θ n = tan −1 (bn / an ) . 2 The relationships are cn = a n + bn2 . v0 = V0 + ∑ (an sin nθ + bn cos nθ ) = V0 + ∑ cn sin (nθ + θ n ) n =1 n =1 ∞ ∞ where. of nth harmonic component respectively. or not conducting.www. is ON. ωT ωT ⎛ Vs ⎞ 1 1 ON an = ∫ v0 sin (n θ ) dθ = ∫ Vs sin (n θ ) dθ = ⎜ n π ⎟ cos n θ ⎜ ⎟ π 0 π 0 ⎝ ⎠ ⎛V ⎞ ⎛ 2V ⎞ = ⎜ s ⎟ (1 − cos 2 π n k ) = ⎜ s ⎟ ( sin 2 ( π n k ) ) ⎜ nπ ⎟ ⎜ nπ ⎟ ⎝ ⎠ ⎝ ⎠ bn = 1 ωT 0 2π k π ∫v 0 0 cos (n θ ) dθ = 1 ω TON π ∫ 0 ⎛V ⎞ Vs cos (n θ ) dθ = ⎜ s ⎟ sin n θ ⎜ nπ ⎟ ⎝ ⎠ 2π k 0 ⎛V =⎜ s ⎜ nπ ⎝ ⎞ ⎟ (sin 2 π k ) ⎟ ⎠ ⎛V ⎞ ⎛ 2V ⎞ = ⎜ s ⎟ (sin 2 π n k ) = ⎜ s ⎟ (sin π n k ) (cos π n k ) ⎜ nπ ⎟ ⎜ nπ ⎟ ⎝ ⎠ ⎝ ⎠ ⎛ 2V ⎞ cn = ⎜ s ⎟ (sin π n k ) ⎜ nπ ⎟ ⎝ ⎠ θ n = tan −1 (cot π n k ) = (π 2) − (π n k ) The average value (dc) is V0 = k Vs . D F is not conducting (OFF). The rms value of the waveform is. and phase angle. i.

2 k = 0. the rms values of only a few harmonic components need be computed. at which the maximum value of the magnitude of the nth harmonic component of the output voltage occurs..0 . as the order of harmonic increases (having an inverse relationship with it). the results obtained is 2 cn = sin (3π / 2) = − sin (π / 2) = sin (−π / 2) = −1 . If the third harmonic ( n = 3 ) is chosen as another example. are computed as per the formula given earlier. are sin (π / 2) = 1 and sin (3π / 2) = − sin (π / 2) = −1 .75( 3 ) . ( k = 0. For second harmonic ( n = 2 ).0 . But if a close look at the formula of cn is taken.45 Vs = . The maximum value of the nth harmonic component occurs. when sin (π n k ) = 1 .. So. using the ascending order. it (rms value) is computed. ( 2 m + 0. i. are obtained. If these two values of k are substituted.. of the output (load) voltage. for even harmonics ( n = 2 m ). are sin (5 π / 2) = sin (π / 2) = 1 . using the expression for the rms value.e.0 ). the duty ratios obtained are. Finally. Version 2 EE IIT. for cn = +1 . π n k = (4m + 1) (π / 2) = 2 π m + (π / 2) . in this case. three values of the duty ratio – ( k = 0. 3π k = (3π / 2) or (− π / 2) . the value of cn is chosen as positive only. i. The value of duty ratio is ( k = 0. ( 2 m ± 0. the average value or dc component and the rms values of all harmonic components. n k = (4m ± 1) / 2 = 2 m ± 1 or. and for cn = −1 . k as given earlier. Earlier. the duty ratios can be computed. being square root of a +ve quantity.5( 1 ) ) as ( k < 1. the results obtained.e. as given earlier. cn = sin (π n k ) = ±1 . and its value (V) is. i. the case of fundamental frequency ( n = 1 ) is taken up. at which the magnitude of the output voltage is maximum at 2 the above frequency.833( 6 ) ). T 2 Vs 0.5( 1 ) ) is substituted. for any other odd harmonic ( n = 2 m + 1 ). for ( n = 3 ). It may be noted that. as k < 1.jntuworld. For fourth harmonic ( n = 4 ).167 ( 1 ) & 0. are obtained. or n k = (4m + 1) / 2 = 2 m + 1 or. n and also on the duty ratio. 4 4 using the ascending order. So. the set of values would be 3π k = (2 m π + (3π / 2)) or (2 m π − ( π / 2)) . as k < 1. it can be checked from the expression for the rms value given earlier. it can have both +ve and –ve values. because the rms values decrease. But.637 Vs 2 Vs 0.5( 1 ) ). θ n = 180° (π ) . It may also be observed that. assuming that its angle would take care of the sign. for the duty ratio of ( k = 0. For this value in this case. θ n = 0° .e. more than one 5 value.com ON T ⎛1⎞ V0 r = ⎜ ⎟ ∫ (Vs ) 2 dt = ON Vs = k Vs T ⎝T ⎠ 0 It can be observed that the amplitude of the harmonic component depends on the order of the harmonic.jntuworld.5( 1 ) ). Then. k. 2 the magnitudes of the output voltage at all odd harmonics are maximum. are obtained. As first example.www.com .25( 1 ) & 0.5 ) 2 Firstly. three values of 2 duty ratio. with its rms value (V) as = nπ n nπ n The value of the angle for the above condition. Now. Kharagpur 9 www. If first two values of k are substituted.5 ). The angle ( θ n ) can be obtained by using the sign of two components. if the value. the duty ratios for which the magnitude of the component of output voltage is maximum. Similarly. and also the 6 previous value of ( k = 0. two values of duty ratio obtained using the formula ( 2 k = 2 m ± 1 ) are. is. an & bn . 2 sin (π / 2) = 1 and the results obtained. The value would now be.

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3 5 k = 0.125( 1 ), 0.375( 8 ),0.625( 8 ) & 0.875( 7 ) , as k < 1.0 . Similarly, for the rms value of any other 8 8 even harmonic to be maximum (highest), the duty ratios can be computed. To obtain the maximum value of average or dc component as per formula given earlier, the duty ratio is ( k = 1.0 ), it being an ideal one. In this case, the switch or the device is always ON in the time period ( 0 − T ), with the output voltage being constant, and also same as the average value, which is equal to the input (source) voltage. In the ideal case, no harmonic component, including fundamental one, is present in the output voltage. But the duty ratio in normal case, for buck converter (dc-dc) or step-down chopper (thyristor) circuit is ( k ≈ 1.0 ), due to the turn-off time requirement of the switching device used. For this case, the rms and average values are nearly equal, but the rms value is slightly higher than the average value. Both the above values are also nearly maximum. The ripple content is very low, with the rms values of the harmonic components, starting from fundamental, also being very low. All these can be checked from the formula.

To eliminate a given harmonic or a set of harmonics in the output voltage waveform, the condition to be satisfied is, sin π n k = 0 , for which the value of the angle is π n k = m π , or n k = m . The case of even ( n = 2 m ) harmonics, starting from second ( n = 2 ), is taken up first. The duty ratio required is k = 0.5 , as k < 1.0 , for the elimination of second harmonic component. To eliminate fourth ( n = 4 ) harmonic component, two more values of duty ratio ( k = 0.25( 1 ) & 0.75( 3 ) ), including the earlier one ( k = 0.5 ), as k < 1.0 , are required. It may be 4 4 noted that, with the duty ratio (k = 0.5) , all even harmonic components are eliminated. To make the average value or dc component zero (0), the duty ratio required is ( k = 0.0 ). But this is an ideal case, in which the switch or the device is OFF. In normal case, duty ratio required is very small ( k ≈ 0.0 ), due to requirement of both turn-on and turn-off times of the switching device used. For this case, the rms and average values are nearly equal, but the rms value is slightly higher than the average value. Both the above values are also nearly minimum. The ripple content is very low, with the rms values of the harmonic components, starting from fundamental, also being very low. All these can be checked from the formula. Now, the case of the elimination of odd ( n = 2 m + 1 ) harmonic components is described. If third ( n = 3 ) harmonic is to be eliminated, two values of duty ratios required are ( k = 0.333( 1 ) & 0.667 ( 2 ) ), as k < 1.0 . 3 3 Similarly, for any other (odd or even) harmonic component to be eliminated, the duty ratios can be computed. The rms value of the nth harmonic component of the output (load) current is, c / 2 , where the load impedance for nth harmonic is Z n = R 2 + ( n ω L) 2 . In = n Zn As stated earlier, the rms value of the harmonic components of the output voltage decreases and also is inversely proportional to n, as the order of the harmonic (n) is increased. The impedance at the harmonic frequency ( n f ) increases, and also is nearly proportional to n, if the load resistance (R) is assumed to be much smaller than the inductive reactance ( 2 π n f L ), as the order of the harmonic is increased. So, the rms value of the nth harmonic component of the output current decreases at a faster rate, and also can be stated as being inversely proportional (nearly) to n 2 , with the increase in the order of the harmonic. If R is very small, and can be neglected, as compared to the inductive reactance, the rms value of the nth harmonic component of the output current is inversely proportional to n 2 , i.e. proportional to ( 1 / n 2 ).

(

)

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The harmonic content of the output voltage waveform is the ac ripple voltage ( V r ), which can be easily computed as shown here, without computing the harmonic components. Its rms value is defined as Vr = (V0 r ) 2 − (V0 ) 2 , the other symbols having been defined earlier. The average value of the output voltage ( V0 ) is shown in Fig. 18.2b. If the X-axis is shifted to the average value, the remaining part is the ac ripple voltage, having both positive and negative values in a cycle. The expression for ac ripple voltage is obtained as, after substituting the expressions of two voltages given earlier,
Vr = k (V s ) 2 − k 2 (Vs ) 2 = V s k − k 2

The ripple factor (RF) is defined as the ratio of ac ripple voltage to the average value, and is obtained as, V 1− k RF = r = V0 k It may be noted that the ac ripple voltage, in terms of rms values of all harmonic components, may also be computed as,
Vr =

∑ (c n / 2 ) 2 =
n =1

( 1 ) ∑ (c n ) 2 2
n =1

This value is same as computed by the expression given earlier. In this lesson ─ the second one in this module, the analysis of the analysis of the buck converter (dc-dc) or step-down chopper circuit, using thyristor as a switching device, with inductive (R-L) and battery (or back emf = E) load, is presented in detail The procedure for the derivation of following expressions ─ the maximum and minimum output (load) currents, assuming continuous conduction, the duty ratio for the limit of continuous conduction, the average value and the ripple factor, of the output current, and the harmonic components of the output voltage waveform, are described in detail. Starting with the next lesson ─ the third one in this module, the operation of the additional circuits needed for commutation in thyristor-based choppers, with relevant waveforms, will be taken up in detail.

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Module 3
DC to DC Converters
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Lesson 19
Commutation of Thyristor-Based Circuits Part-I
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This lesson provides the reader the following: (i) (ii) (iii) (iv) Requirements to be satisfied for the successful turn-off of a SCR The turn-off groups as per the General Electric classification The operation of the turn-off circuits Design of a SCR commutation circuit

A thyristor can be turned ON by applying a positive voltage of about a volt or a current of a few tens of milliamps at the gate-cathode terminals. However, the amplifying gain of this regenerative device being in the order of the 108, the SCR cannot be turned OFF via the gate terminal. It will turn-off only after the anode current is annulled either naturally or using forced commutation techniques. These methods of turn-off do not refer to those cases where the anode current is gradually reduced below Holding Current level manually or through a slow process. Once the SCR is turned ON, it remains ON even after removal of the gate signal, as long as a minimum current, the Holding Current, Ih, is maintained in the main or rectifier circuit.

Fig. 3.1 Turn-off dynamics of the SCR In all practical cases, a negative current flows through the device. This current returns to zero only after the reverse recovery time trr, when the SCR is said to have regained its reverse blocking capability. The device can block a forward voltage only after a further tfr, the forward recovery time has elapsed. Consequently, the SCR must continue to be reverse-biased for a minimum of tfr + trr = tq, the rated turn-off time of the device. The external circuit must therefore reverse bias the SCR for a time toff > tq. Subsequently, the reapplied forward biasing voltage must rise at a dv/dt < dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General Electric has suggested six classification methods for the turn-off techniques generally adopted for the SCR. Others have chosen different classification rules. SCRs have turn-off times rated between 8 - 50 μsecs. The faster ones are popularly known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available at higher current levels while the faster ones are expectedly costlier.

Classification of forced commutation methods
The six distinct classes by which the SCR can be turned off are: Class A Class B Class C Class D Self commutated by a resonating load Self commutated by an L-C circuit C or L-C switched by another load carrying SCR C or L-C switched by an auxiliary SCR Version 2 EE IIT, Kharagpur 3 www.jntuworld.com

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Class E An external pulse source for commutation Class F AC line commutation These examples show the classes as choppers. The commutation classes may be used in practice in configurations other than choppers.

Class A, Self commutated by resonating the load

Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms When the SCR is triggered, anode current flows and charges up C with the dot as positive. The L-C-R form a second order under-damped circuit. The current through the SCR builds up and completes a half cycle. The inductor current will then attempt to flow through the SCR in the reverse direction and the SCR will be turned off.

The current may be expressed as I ( s) = V 1 1 + RCs =V LRCs 3 + Ls 2 + Rs s ( Ls + R ) 1 + RCs

The solution of the above equation is of the form 2 ⎤ ω n −t RC V⎡ 1 e i (t ) = ⎢1 + sin( wt + φ )⎥ R⎢ ⎥ 1−ξ 2 ξ ⎣ ⎦ where,

ξ=
and

1 L , ω n = L , ω = ω n 1 − ξ 2 , φ = tan −1 2 RCω C 2R C

⎡ ω2 ⎤ n v(t ) = V ⎢ e −t 2 RC sin(ωt ) + 1⎥ ⎢ 1−ξ 2 ⎥ ⎣ ⎦

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The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into the resistance in an exponential manner. The SCR is reverse-biased till the capacitor voltages returns to the level of the supply voltage V.

Class B, Self commutated by an L-C circuit
The Capacitor C charges up in the dot as positive before a gate pulse is applied to the SCR. When SCR is triggered, the resulting current has two components. The constant load current Iload flows through R - L load. This is ensured by the large reactance in series with the load and the freewheeling diode clamping it. A sinusoidal current flows through the resonant L-C circuit to charge-up C with the dot as negative at the end of the half cycle. This current will then reverse and flow through the SCR in opposition to the load current for a small fraction of the negative swing till the total current through the SCR becomes zero. The SCR will turn off when the resonant–circuit (reverse) current is just greater than the load current. The SCR is turned off if the SCR remains reversed biased for tq > toff, and the rate of rise of the reapplied voltage < the rated value.

Fig. 3.3 Class B, L-C turn-off

Problem #1
A Class B turn-off circuit commutates an SCR. The load current is constant at 10 Amps. Dimension the commutating components L and C. The supply voltage is 100VDC.

Soln # 1
The commutating capacitor is charged to the supply voltage = 100 V The peak resonant current is, i peak = V C L Assuming,

i peak ~1.5.I load

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= (15 ) 2 = 0.0225 L 100 The SCR commutates when the total current through it reaches zero.This corresponds to 0.73 rads after the zero crossing of the resonant current. The capacitor voltage at that instant is 75 volts. After the SCR turns off, the capacitor is charged linearly by the load current. C If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turnoff time of 20 μsecs, (2.I load ).t = 75.C

20.20 μF 75 = 15.33 ≈ 15 C=
L= The reapplied forward voltage has a dV C = 667 ≈ 700 0.0225

μF μH

20 = = 1.33 volts/sec rise. dt 15 It can be observed that if the peak of the commutating current is just equal to the load current, the turn-off time would be zero as the capacitor would not be able to impress any negative voltage on the SCR.

Class C, C or L-C switched by another load–carrying SCR
This configuration has two SCRs. One of them may be the main SCR and the other auxiliary. Both may be load current carrying main SCRs. The configuration may have four SCRs with the load across the capacitor, with the integral converter supplied from a current source. Assume SCR2 is conducting. C then charges up in the polarity shown. When SCR1 is triggered, C is switched across SCR2 via SCR1 and the discharge current of C opposes the flow of load current in SCR2.

Fig. 3.4 Class C turn-off, SCR switched off by another load-carring SCR

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Class D, L-C or C switched by an auxiliary SCR
Example 1

The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is carried by only one of the SCR’s, the other acting as an auxiliary turn-off SCR. The auxiliary SCR would have a resistor in its anode lead of say ten times the load resistance.

Fig. 3.5 Class D turn-off. Class D commutation by a C (or LC) switched by an Auxiliary SCR. Example 2

SCRA must be triggered first in order to charge the upper terminal of the capacitor as positive. As soon as C is charged to the supply voltage, SCRA will turn off. If there is substantial inductance in the input lines, the capacitor may charge to voltages in excess of the supply voltage. This extra voltage would discharge through the diode-inductor-load circuit. When SCRM is triggered the current flows in two paths: Load current flows through the load and the commutating current flows through C- SCRM -L-D network. The charge on C is reversed and held at that level by the diode D. When SCRA is re-triggered, the voltage across C appears across SCRM via SCRA and SCRM is turned off. If the load carries a constant current as in Fig. 3.4, the capacitor again charges linearly to the dot as positive.

Problem # 2
A Class D turn-off circuit has a commutating capacitor of 10 μF. The load consists of a clamped inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter grade' SCR has a turn-off time of 12 μsecs. Determine whether the SCR will be satisfactorily commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.

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Soln # 2
The capacitor is initially charged to the supply voltage 220 V at the end of the conduction period of SCRA. When SCRM is triggered, the 25 Amps load current and the L-C ringing current flows through it. Peak current through SCR is Amps L Selecting L such that ipeak ~ 1.5 . load current,
C 25 = 0.0568 2.220 L = 3.1 mH L =

i peak = 25 + 220 C

Assuming that the capacitor charges to 70% of its original charge because of losses in the C- SCRM -L-D network, and it charges linearly when SCRA is again triggered, I load .t q = 10(0.7.220)10 −6 = 1540.10 −6 tq = 1540 / 25 = 61.6

μ sec s

The SCR can therefore be successfully commutated. The maximum current that can be commutated with the given Capacitor at the 220 V supply voltage is I load = 1540 / 12 = 128 Amps For the 25 Amps load current the capacitor just enough would have a rating of C = I load .t q /(0.7.220) = (25.12) / 154 = 1.95 ≈ 2.0

μF

If the supply voltage is reduced by a factor K, the required capacitor rating increases by the same factor K for the same load current.

Class E – External pulse source for commutation
The transformer is designed with sufficient iron and air gap so as not to saturate. It is capable of carrying the load current with a small voltage drop compared with the supply voltage. When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR1 off a positive pulse is applied to the cathode of the SCR from an external pulse generator via the pulse transformer. The capacitor C is only charged to about 1 volt and for the duration of the turn-off pulse it can be considered to have zero impedance. Thus the pulse from the transformer reverses the voltage across the SCR, and it supplies the reverse recovery current and holds the voltage negative for the required turn-off time.

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SCR

LOAD

Fig. 3.6 Class E, External pulse commutation

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Class F, AC line commutated
If the supply is an alternating voltage, load current will flow during the positive half cycle. With a highly inductive load, the current may remain continuous for some time till the

Fig. 3.7 Class F, natural commutation by supply voltage

energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turnoff period of the device. The duration of the half cycle must be definitely longer than the turnoff time of the SCR. The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation process involved here is representative of that in a three phase converter. The converter has an input inductance Ls arising manly out of the leakage reactance of the supply transformer. Initially, SCRs Th1 and Th1' are considered to be conducting. The triggering angle for the converter is around 600. The converter is operating in the continuous conduction mode aided by the highly-inductive load. When the incoming SCRs, Th2 and Th2' are triggered, the current through the incoming devices cannot rise instantaneously to the load current level. A circulating current Isc builds up in the short-circuited path including the supply voltage, Vs-Ls-Th1'- Th2 and Vs- Ls-Th2'-Th1 paths. This current can be described by: I sc = Vs sin(ωt − 90 0 ) Vs V cos(ωt ) Vs + cos α = s + cos α ωL s ωLs ωLs ωL s

where α the triggering angle and Isc and Vs as shown in Fig. 3.6.

This expression is obtained with the simplifying assumption that the input inductance contains no resistances. When the current rises in the incoming SCRs, which in the outgoing Version 2 EE IIT, Kharagpur 10
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ones fall such that the total current remains constant at the load current level. When the current in the incoming ones reach load current level, the turn-off process of the outgoing ones is initiated. The reverse biasing voltage of these SCRs must continue till they reach their forward blocking state. As is evident from the above expression, the overlap period is a function of the triggering angle. It is lowest when α ~ 900. These SCRs being 'Converter grade', they have a larger turn-off time requirement of about 30-50 μsecs. The period when both the devices conduct is known as the 'overlap period'. Since all SCRs are in conduction, the output voltage for this period is zero. If the 'fully-controlled' converter in Fig. 3.7 is used as an inverter with triggering angles > 900, the converter triggering can be delayed till the 'margin angle' which includes the overlap angle and the turn-off time of the SCR - both dependent on the supply voltages.

Rate of rise of forward voltage, dv/dt
The junctions of any semiconductor exhibit some unavoidable capacitance. A changing voltage impressed on this junction capacitance results in a current, I = C dv/dt. If this current is sufficiently large a regenerative action may occur causing the SCR to switch to the on state. This regenerative action is similar to that which occurs when gate current is injected. The critical rate of rise of off-state voltage is defined as the maximum value of rate of rise of forward voltage which may cause switching from the off-state to the on-state. Since dv/dt turn-on is non-destructive, this phenomenon creates no problem in applications in which occasional false turn-on does not result in a harmful affect at the load. Heater application is one such case. However, at large currents where dv/dt turn-on is accompanied by partial turnon of the device area a high di/dt occurs which then may be destructive. The majority of inverter applications, however, would result in circuit malfunction due to dv/dt turn-on. One solution to this problem is to reduce the dv/dt imposed by the circuit to a value less than the critical dv/dt of the SCR being used. This is accomplished by the use of a circuit similar to those in Figure 3.8 to suppress excessive rate of rise of anode voltage. Z represents load impedance and circuit impedance. Variations of the basic circuit is also shown where the section of the network shown replaces the SCR and the R-C basic snubber. Since circuit impedances are not usually well defined for a particular application, the values of R and C are often determined by experimental optimization. A technique can be used to simplify snubber circuit design by the use of nomographs which enable the circuit designer to select an optimized R-C snubber for a particular set of circuit operating conditions. Another solution to the dv/dt turn-on problem is to use an SCR with higher dv/dt turn-on problem is to use an SCR with higher dv/dt capability. This can be done by selecting an SCR designed specially for high dv/dt applications, as indicated by the specification sheet. Emitter shorting is a manufacturing technique used to accomplish high dv/dt capability.

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8 dv/dt supression circuits Questions #1 For a Class D turn-off SCR. Most of the above circuits are also called 'forced commutated' DC-DC chopper circuits.jntuworld. this inductor limits the maximum output current of the converter. the load consists of a resistance only. In fact.www.jntuworld. The overlap time is directly related to the commutating inductance. Ans: (Hints): The capacitor would now charge in an exponential manner. #3 Can the output DC voltage be controlled in the above circuits? Ans: Yes. #2 For a Class F converter. Kharagpur 12 www. Version 2 EE IIT. The time it takes to discharge from its reverse charged state once SCRA is triggered is the circuit turn-off time which must be in excess of the rated 12 μsecs. will the overlap period rise with the leakage inductance of the converter? What happens to the output voltage? Ans: Yes. 3. If the supply voltage and SCR turn-off ratings are as in Problem # 1 calculate the required value of the commutating capacitor.com Fig.com . The input current maximum would be as for a shorted network with the leakage inductance only present. The output voltage decreases.

Kharagpur 1 www.www.jntuworld.jntuworld.com Module 3 DC to DC Converters Version 2 EE IIT.com .

Kharagpur 2 www.com Lesson 20 Commutation of Thyristor-Based Circuits Part-II Version 2 EE IIT.com .jntuworld.jntuworld.www.

jntuworld.jntuworld.1 Introduction The commutation process plays an important role in the operation and control of both naturally commutated (or line commutated) and forced commutated SCR based converters. The AC-DC Phase Fig. These converters may be either AC-DC.com This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) Practical significance of commutation Limitations of line commutation Ability to determine commutation interval Insight to different methods of commutation Consequences of the commutating methods on device stresses 20. bottom: The input three-phase voltage waveforms Angle Converter. 20.com .www.1 Top: A three-phase Phase Angle Converter. DC-DC or DC-AC converters. The following section discusses commutation with respect to this application. (PAC) continues to be used in much high power and very high power converters where the application is non-critical or the non-state-of-the-art is preferred for operational advantages. Version 2 EE IIT. Kharagpur 3 www.

With no delay in triggering (as if the SCRs are all replaced by diodes) the SCRs. The triggering on this line voltage is delayed by the trigger angle αfrom this 600 point. which are capable of operating with trigger angles α between 00 to 1800 ideally. At any instant. 20. VY and VB are connected to the three legs of the converter via three inductances LS. There ensues an ‘overlap’ period when three SCRs conduct for a transient period.com . Fig. It is evident that with the simultaneous conduction of SCR2 and SCR6 there is a short circuit at the converter terminals with the short circuit current ISC being limited by the per-phase series inductances LS.2 Significant voltage and current waveforms of a single phase converter highlighting the overlap instants and the corresponding converter terminal and output voltages Subsequently. say SCR1 and SCR6 at the time instant indicated by the dashed line in Fig.2 Commutation in PAC A three phase PAC is shown in Fig. they would be triggered 600 after the zero crossing of the corresponding line voltage. The voltage waveforms at the output and at the converter input terminals reflect the commutation process.jntuworld. 20. Nominally balanced three phase voltages VR.jntuworld. at the crossover point. two devices are conducting. nor does the outgoing SCR turn-off immediately.1. All-SCR (fully-controlled) converters.www. phase voltage VR is most positive and VB most negative. 20. Version 2 EE IIT. This angle is of the order of 1600 and the output voltage is limited. There are a few significant effects of the commutation process when three devices conduct. bottom. VY becomes most negative and SCR2 is more forward biased with respect to SCR6. which can be considered to represent the leakage reactance of the supply transformer. Line voltage VYB drives this current. are restricted in the inverter mode to operate within the ‘margin-angle’. At that instant. The incoming SCR does not take the full load current IL.1.com 20. Kharagpur 4 www.

opposing the load current. Version 2 EE IIT. A four-SCR fully-controlled converter operates into a load. the SCR pairs 1.1 A single-phase converter.04 mH.1’ ISCR 2.1 The commutating voltage for a single phase converter is the supply voltage itself. 900.2 operates with an input inductance LS = 0. A short circuit of the supply voltage takes place via the SCRs. Kharagpur 5 www. The AC source includes the series (leakage) inductance LS. 50 Hz and the level load current is 15 Amps. The input distortion affects other equipment connected to the same bus and protection must be provided against this cross-talk between two converters through this type of line distortion.3 Short circuit currents between incoming and out going SCRs for various trigger angles Example 20. 2’ and reverse mode.com 20.Calculate the overlap times for each case and sketch the current waveform in the incoming SCR pair. ISC is initially zero and rises ultimately to load current level when SCRs 1. When the incoming SCRs (say 2 and 2’) are triggered. The input voltage is 230 V.jntuworld.jntuworld.2 is considered to illustrate this. Fig. 1’. It is evident from waveforms of ISCR 1. A short-circuiting current.com . 1600.3 Input voltage waveform distortion A single-phase converter. which draws a constant current. 1’ turn off and the overlap time is complete. The input voltage exhibits two notches in a singlephase converter both of which are identical and reach down to zero. Indicate the current waveforms of the outgoing and incoming phase for trigger angles α = 450.2’ that they take a finite time to rise and fall.www. 20. The current in the incoming device rises till it equals the load current IL while that in the out going one falls to zero. in the forward mode in 2. Fig. All conducting SCRs can be considered to be short circuits and consequently the output voltage and thus also the input voltage is zero during this period. IL in 1. Current. 2’ are all conducting. ISC flows through the SCRs. The output voltage is diminished and a ‘notch’ appears across the input. 230 V. 20. In the intervening period all four SCRs are ON. 1’ and 2. Solution 20. Fig 20. Waveforms are shown for (i) no overlap case (when LS = 0) and (ii) for a finite value of LS causing an overlap.

50 − 90) − 68.21) + 90 0 = 11.0. Since the transients are all level currents. the steady state component can be considered to just being shifted up or down by an amount equal to the transient component.21) + cos −1 (68.π .80. Transient component = 73. ISC can be separated into two components – the steady state part and the transient part. Transient component = 73. Transient component = 73.21sin( 2.com . there is no transient for α = 900.50 − 90) + 51. So equating each current expression to 15 Amps.77 Amps Forα = 90 0 .80 Amps In each case the transient current adds up with the steady-state component to give the net current. Kharagpur 6 www. 90 and 160 0 Steady − state component of short I SS = 230∠0 0 = 73.01 The transient current is a level current = − ( the magnitude of I SS at the instant of triggering ) (A current flowing in a short-circuited pure inductor does not decay – it is level) Forα = 45 0 .00 Amps Forα = 160 0 . Two other overlap Version 2 EE IIT. The expressions for each delay angle α is: I SC1 = 73. and forα = 1600 the shift is by – 68. Note the shape of the relevant portions of the current waveform lying between 0 to IL in each case.50 − 90) I SC3 = 73.21) so commutation is not possible for α = 160 0 It may be noted that the overlap time decreases and comes to a minimum when the trigger angle reaches 900.80 73.21sin(90 0 − 45 0 ) = 51.77 73.21∠ − 90 0 Amps 2.jntuworld.jntuworld.85 0 μ 2 = − cos −1 (15 73.π 50. VS = 230∠0 0 0 0 Volts circuiting current is Forα = 45 . The steady state component is for all cases the current that occurs when the voltage is applied to a pure inductance (LS).www.21sin( 2.21sin(2.π .com For all trigger angles.21sin(90 0 − 160 0 ) = −68.80 73. current. the shift is by +51.77.80 The overlap angle is the period over which the current in each case builds up from zero to the load current IL level.77 I SC2 = 73.21) = 14.82 0 μ 3 = − cos −1 (− 83.77 73. μ1 = − cos −1 (− 36. Thus for α = 450.21) + cos −1 (− 51.21sin(90 0 − 90 0 ) = 0.π . but again increases when the delay angle goes beyond 900.

4 Three-phase converters In a three phase six-pulse converter. The three-phase converter.jntuworld.50 − 90) + 73. the four other have different magnitudes. Fig. The peak of ISC occurs at this instant. which may supply other equipment of the plant too.21sin( 2. Example 20.4. each in series with each of the three phases. Fig. The triggering angle is α = 00 for the case illustrated. This commutating voltage magnitude is dictated by the trigger angle.21) + 180 0 = 37. Assuming zero turn-off time. Note at α = 1800 the Version 2 EE IIT.π .330 I SC 0 = 73.21) + cos −1 (− 73. This angle plus the time period required by the SCRs to complete their turn-off process (refer: turn-off dynamics of SCR) is called the Margin Angle. 20.jntuworld.com .4 The overlap time is dependent on the load current existing during the commutation period and also the voltage behind the short circuit current. However. Thus for α = 00 this voltage is minimum.21) 0 = 37.21 73. 20.com angles are also of interest. μ m arg in − angle = − cos −1 (− 58. Kharagpur 7 www. 20. There are six notches per cycle. They are the leakage inductances of the transformer.21 73. has three inductances LS.www. At α = 1800 too it would have been very low if successful commutation had been possible. without any allowance for an overlap time. the notches in the line voltage waveform are as shown in Fig 20.33 0 The two angles are numerically equal as is evident from Fig. the SCR current would just start to fall before it rises again. While two of the notches reach down to zero volts.1.1. First the overlap angle for α = 00 and when the delay angle just permits the overlap to be over before the commutating voltage reaches 1800.21 0 μ 0 = cos −1 (58.21 73.

ii) Current commutation and iii) Load commutation. mostly by an auxiliary SCR. The resulting ‘commutation failure’ can cause severe short circuits. 20.www. The current in the conducting SCR is immediately quenched. With a large reverse voltage turning it off. Kharagpur 8 www. the device offers the fastest turn-off time obtainable from that particular device.jntuworld.5 A voltage commutated DC-DC Chopper and most significant waveforms Version 2 EE IIT.com .jntuworld. 20.com converter operates in the ‘inverter’ mode and if the out going SCR fails to turn off it is effectively triggered at α = 00 which pushes the converter from peak inversion to peak rectification mode. Three types of commutation are identified: i) Voltage commutation. Thus the trigger angle must be restricted to values.1 Voltage Commutation In a voltage commutated thyristor circuit a voltage source is impressed across the SCR to be turned off. This voltage is comparable in magnitude to the operating voltages. 20. It is an exposition of ‘hard’ turn-off where the reverse biasing stress is maximum. however the reverse-biasing voltage must be maintained for a period greater than that required for the device to turn-off.5. Fig.5 Commutation in DC-DC Choppers DC-DC Choppers have also been categorised on the basis of their commutation process. which permit successful commutation of the SCRs.

Now the capacitor is progressively positively charged and the load voltage is equally diminished from the supply voltage.com . The half cycle capacitor current adds to the load current and is taken by the Main SCR.jntuworld. ThM is the main SCR and ThAux is the Auxiliary.jntuworld. which is held practically level by the large filter inductance. Capacitor C is charged with the dot as positive. Stresses on all the three semiconductors can be expected to be high here.www. With the positive at the dot the capacitor is again ready for the next cycle. The Load voltage peaks by the addition of the capacitor voltage to the supply when ThAux is triggered. L and D ending with a negative at the dot. Thereafter. When the Capacitor voltage returns to zero. Here the Capacitor is automatically charged through D-L-LF-Load with the dot as positive. Voltage commutation may be chosen for comparatively fast switching and it can be identified from the steep fall of the SCR current. 20. Additionally. LF and the Free-wheeling diode. the level load current charges the capacitor linearly to the supply voltage with the dot again as positive.6 can be converted into a current commuted one just by interchanging the positions of the diode and the capacitor. The turn-off time offered by the commutation circuit to the SCR lasts till this stage starting from the triggering of ThAux. The reverse voltage may be less than its positive value as some energy is lost in the various components in the path. 20. the load voltage equals supply voltage. As a consequence of the previous cycle. Version 2 EE IIT.5. There is no overlapping operation between the incoming and the outgoing devices and both currents fall and rise sharply. The voltage falls as the capacitor discharges both changes being linear because of the level load current. 20. it carries the load current. With the negative at the dot C-ThAux is enabled to commutate ThM. When ThAux is triggered the negative charge of the capacitor is impressed onto ThM and it immediately turns off. When the Main SCR is triggered.2 Current commutation The circuit of Fig. Here ThAux must be switched before ThM to charge C to desired polarity. the charged Capacitor swings half a cycle through ThM.5 illustrates voltage commutation. ThAux is naturally commutated when the capacitor is fully charged and a small excess voltage switches on the free wheeling diode. The SCR does take the reverse recovery current in the process. Kharagpur 9 www.com Fig. Any of the SCRs can thus be switched on first.

The low forward voltage appearing across the SCR causes it to turn-off slowly. The free-wheeling diode also turns on through a overlap with D when the capacitor voltage just exceeds the supply voltage and this extra voltage drives the commutating current through the path D-Supply-DF-L. A voltage spike appears across the load when the voltage across the commutating inductance collapses and the capacitance voltage adds to the supply voltage. Version 2 EE IIT. 20. it takes a half cycle of the ringing current in the L-C circuit and the polarity of the charge across the capacitor reverses. Turn-off process is consequently accompanied by an overlap between ThM and the diode D in the D-C-L path. Kharagpur 10 www. As it swings back. It ensures ‘soft’ turnoff by conducting the excess current in the ringing L-C circuit.jntuworld. Once the main SCR is turned off.jntuworld. Thus there is soft switching of all devices during this period. ThAux is turned off and the path through D-C-L shares the load current which may again be considered to be reasonably level. The Current-share of THM is thus reduced in a sinusoidal (damped) manner. Note that such a diode cannot be connected across the Main SCR in the voltagecommutated circuit.com If ThM is triggered first. the capacitor current becomes level and the voltage decreases Fig. it immediately takes the load current turning off DF. When ThAux is triggered. Further an additional diode may be connected across the main SCR.com . Consequently switching frequencies have to be low.7 A current commutated DC-DC Chopper and most significant waveforms linearly.www.

The capacitor has a symmetric trapezoidal voltage across itself. The load voltage is of triangular shape with a peak equal to double the supply voltage (average equal to supply voltage for the conduction interval).7 is called a load-commutated chopper.www. In fact it is chosen to satisfy the load current requirement. Any value of capacitor will suffice for commutation. Currents through Fig.com 20.jntuworld.jntuworld. The current thus automatically is extinguished when the capacitor achieves supply voltage level and the free-wheeling diode is turned on. This commutation method permits fastest switching of the SCRs. Conduction patterns of these two groups are symmetrical.5. Conduction paths are alternately through the diagonal SCR pairs.3 Load Commutation The circuit in Fig 20.7 A load-commutated DC-DC Chopper and most significant waveforms the SCRs rise and fall sharply without any inductance regulating it. Kharagpur 11 www. 20. Each pair of SCRs conduct with the capacitor in series. Version 2 EE IIT. The free wheeling diode current also behaves similarly and all devices are stressed by sharp di/dt.com .

200 = 8. The corresponding frequency is 31 KHz. A1 The capacitor charges linearly. This time should be a greater than or equal to the rated turn-off time of the SCR C dv c = 10 dt dt = (C / 10 ). The apparent frequency is 62 as the conduction of the SCR pairs is symmetrical.www.jntuworld. Sketch important waveforms specially the current through the Main SCR and its ant-parallel diode. Switching period is thus 4*8 = 32 μsecs. The load current is 10 amperes.com 20.com .4μF Each time the capacitor conducts a current it requires 2*8 μsecs to reverse charge. What is the minimum value of commutating capacitor necessary for successful commutation and what is the corresponding switching frequency? Supply voltage is 20 V DC.7 Practice Problems with Answers and Questions Q1 SCRs having turn-off times of 8 μsecs is connected in a load-commutated chopper. level.10 −6 sec s Therefore C = 0. Kharagpur 12 www.jntuworld. and the forward biasing ends when the capacitor discharges to zero. Version 2 EE IIT.  Q2 For the current commutated circuit with a diode connected anti-parallel to the Main SCR estimate the turn-off time permitted as a function of the commutating capacitor and inductor.

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www.com Lesson 21 Introduction to SwitchedMode Power Supply (SMPS) Circuits Version 2 EE IIT.jntuworld. Kharagpur 2 www.com .jntuworld.

jntuworld. It may not be unusual. This kind of unregulated dc voltage is most often derived from the utility ac source. In majority of the cases the required voltages are of magnitudes varying between -18 to +18 volts. to have a power supply working from any other voltage level which could be of either ac or dc type. For example. Some equipment may need multiple output power supplies.com . The digital ICs may need 3. then it is rectified using diode rectifier and filtered by placing a capacitor across the rectifier output. ±5 volt and ±12 volt power supplies. unless the capacitor is sufficiently large the capacitor voltage may have unacceptably large ripple.1 shows the basic block for a linear power supply operating from an unregulated dc input. However.3 volt. where a 100 volts (peak). The individual output voltages from the multiple output power supply may have different current ratings and different voltage regulation requirements. 50 Hz ac voltage is rectified and filtered using a capacitor of 1000 micro-farad and fed to a load of 100 ohms is shown in Fig. The input connection to these power supplies is often taken from the standard utility power plug point (ac voltage of 115V / 60Hz or 230V / 50Hz).www. The ripple in the capacitor voltage is not only dependent on the capacitance magnitude but also depends on load and supply voltage variations. 21. In some cases one may use a combination of switched mode and linear power supplies to gain some desired advantages of both the types. Kharagpur 3 www. Integratedcircuit (IC) chips used in the electronic circuits need standard dc voltage of fixed magnitude. Almost invariably these outputs are isolated dc voltages where the dc output is ohmically isolated from the input supply. Thus the ripple across the capacitor voltage (difference between the maximum and minimum instantaneous magnitudes) must not be large or else the minimum voltage level may fall below the required level for output voltage regulation. The filter capacitor size is chosen to optimize the overall cost and volume.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the basic elements in a regulated power supply Explain the basic principle of operation of linear and switched mode power supplies Compare the merits and demerits of SMPS vis-à-vis linear power supplies Interpret Power supply specifications 21.3volt supply and the hard disk driver or the floppy driver may need ±5 and ±12 volts supplies. 21. The representative rectifier and capacitor voltage waveforms. For proper operation of the voltage regulator.2. though. Many of these circuits need well-regulated dc supply for their proper operation. The magnitude of voltage-ripple across the input capacitor increases with increase in load connected at the output. in a Personal Computer one may need 3. the instantaneous value of unregulated input voltage must always be few volts more than the desired regulated voltage at the output.21.1 Introduction to regulated dc power supplies Power supply is a broad term but this lesson is restricted to discussion of circuits that generate a fixed or controllable magnitude dc voltage from the available form of input voltage. The utility ac voltage is first stepped down using a utility frequency transformer.2 Linear regulated power supply Fig. Version 2 EE IIT. In case of multiple output supplies ohmic isolation between two or more outputs may be desired. The unregulated capacitor voltage becomes the input to the linear type power supply circuit.jntuworld. There are two broad categories of power supplies: Linear regulated power supply and switched mode power supply (SMPS). The voltage across the capacitor is still fairly unregulated and is load dependent.

com . Efficiency of linear voltage regulator circuits will be quite low when supply voltage is on the higher side of the nominal voltage.jntuworld. Difference between the instantaneous input voltage and the regulated output voltage is blocked across the collector emitter terminals of the transistor.1: Schematic linear voltage regulator Version 2 EE IIT.www. a linear regulator circuit where a transistor is placed in between the unregulated dc voltage and the desired regulated dc output. The end user of the power supply will like to have a regulated output voltage (with voltage ripple within some specified range) while the load and supply voltage fluctuations remain within the allowable limit. The circuit in Fig.jntuworld. schematically.1 shows.21. The worst-case series voltage drop across the transistor may be quite large if the allowed variation in supply magnitude is large. Thus the transformer turns ratio is chosen on the basis of minimum specified supply voltage magnitude.com The step down transformer talked above should be chosen such that the peak value of rectified voltage is always larger than the sum of bare minimum voltage required at the input of the regulator and the worst-case ripple in the capacitor voltage. Series pass elements Unregulated DC voltage Regulated Output Fig. in such circuits the lowest instantaneous magnitude of the unregulated dc voltage must be slightly greater than the desired output voltage (to allow some voltage for transistor biasing circuit). To achieve this the unregulated dc voltage is fed to a voltage regulator circuit. Worst-case power dissipation in the transistor will correspond to maximum supply voltage and maximum load condition (load voltage is assumed to be well regulated).21. Kharagpur 4 www. As discussed previously. The power dissipation in the transistor and the useful output power will be in the ratio of voltage drops across the transistor and the load (here the control power dissipated in the base drive circuit of the transistor is assumed to be relatively small and is neglected).

⎧ 1 − ⎛ 25. Thus capacitor may be assumed to discharge under the influence of 25.com Power. fairly accurate value of capacitance may be found out.com . It may be assumed that in each half cycle the capacitor charges to the peak of supply voltage (= 18*1.414 =25. Answer: C = approx.] Version 2 EE IIT.electronic switch Unregulated DC source Duty ratio control Output voltage feedback + - Load Fig.jntuworld. However with some simplifying assumptions. 1350 microfarad. The ripple in the capacitor voltage may be neglected to calculate load current. Kharagpur 5 www. Next. [Hint: The exact solution will involve use of numerical technique or trial and error method. use the equality ⎨π − Cos ⎜ 2π ( freq. 21. 50 Hz supply is rectified using a full bridge diode rectifier and is followed by a capacitor filter.) ⎩ ⎝ 25.www.456/30 amp.456 − 5 ⎞ ⎫ ( I ) for a time duration (Δt) equal to ⎟⎬ .jntuworld.456 volts).456 ⎠⎭ C ΔV = I Δt and find C. The load connected across the capacitor is a simple resistor of 30 ohm.3: A schematic switched mode dc to dc chopper circuit Problem 1 An 18V (rms). What should be the value of filter capacitor to get only 5 volts peak to peak ripple across the load voltage? Neglect voltage drop across conducting diode.

[Answer: Turns ratio = L. Details of some popular SMPS circuits. turns = {1.11 (15+2) } / (190* 1. Most of the dc-to-dc converters used in SMPS circuits have an intermediate high frequency ac conversion stage to facilitate the use of a high frequency transformer for voltage scaling and isolation. always remains in the active region. followed by rectification and filtering. The utility voltage is first stepped down using a transformer. However in case of SMPS with input supply drawn from the ac mains.V. The high Version 2 EE IIT. The ON and OFF durations are suitably controlled such that the average dc voltage applied to the output circuit equals the desired magnitude of output voltage.jntuworld. In such SMPS circuits the unregulated input dc voltage is fed to a high frequency voltage chopping circuit such that when the chopping circuit (often called dc to dc chopper) is in ON state. The unregulated dc voltage across the capacitor is then fed to a high frequency dc-to-dc converter. Assuming peakto-peak ripple in the capacitor voltage to be 10% of the capacitor’s crest voltage. In contrast. During ‘ON’ mode the switch is in saturation mode with negligible voltage drop across the collector and emitter terminals of the switch where as in ‘OFF’ mode the switch is in cut-off mode with negligible current through the collector and emitter terminals. the unregulated voltage is applied to the output circuit that includes the load and some filtering circuit. The ratio of ON time to cycle time (ON + OFF time) is known as duty ratio of the chopper circuit. in linear power supplies with input voltage drawn from ac mains. On the contrary the voltageregulating switch. have been discussed in next few lessons. In fact there are several other switched mode dc-to-dc converter circuits that do not use a high frequency transformer. Kharagpur 6 www. in a linear regulator circuit. The input ac voltage (rms magnitude) varies from 190 volts to 260volts. In this lesson a simplified schematic switching arrangement is described that omits the transformer action.www. the mains voltage is first stepped down (and isolated) to the desired magnitude using a mains frequency transformer. consisting of a low pass filter circuit followed by the load. with provisions for incorporating high frequency transformer for voltage scaling and isolation.com Problem 2 It is desired to get a regulated 15 volts supply from the utility ac voltage of 50 Hz using a linear regulator circuit.com .jntuworld. turns/ H.3 Switched Mode Power Supply (SMPS) Like a linear power supply. The high frequency transformer used in a SMPS circuit is much smaller in size and weight compared to the low frequency transformer of the linear power supply circuit. The switch employed is turned ‘ON’ and ‘OFF’ (referred as switching) at a high frequency. zero magnitude of voltage is applied to the output side.V. The ‘Switched Mode Power Supply’ owes its name to the dc-to-dc switching converter for conversion from unregulated dc input voltage to regulated dc output voltage. When the chopper is in OFF state. find the turns ratio of the step down transformer. the input voltage is first rectified and filtered using a capacitor at the rectifier output. For proper operation of the linear regulator circuit the input voltage applied to it must always be 2 volts more than the desired output voltage (neglect diode drops).414) = 1 : 14] 21. A high switching frequency (of the order of 100 KHz) and a fast control over the duty ratio results in application of the desired mean voltage along with ripple voltage of a very high frequency to the output side. The stepped down voltage is rectified using a diode bridge and filtered by placing a capacitor after the rectified output. the switched mode power supply too converts the available unregulated ac or dc input voltage to a regulated dc output voltage.

[Hint: VA ratng for a single phase transformer = 2. Details of some of these circuits have been discussed in following lessons. 15V low frequency transformer and (ii) a 50 VA. Since there is no high frequency switching. 100 kHz. The switching losses in modern switches (like: MOSFETs) are much less compared to the loss in the linear element.4 SMPS versus linear power supply As discussed above. 50Hz.www. Assume sinusoidal voltages. Take identical values for window utilization factor and copper current density. Generally the control of the linear power supply circuit is much simpler than that of SMPS circuit.21. 21. One can more easily meet tighter specifications on output voltage ripples by using linear power supplies.] Answer: Volume (size) of Low frequency transformer will be 400 times higher than that of high frequency transformer. Kharagpur 7 www. In most of the switched mode power supplies it is possible to insert a high frequency transformer to isolate the output and to scale the output voltage magnitude. Version 2 EE IIT. AW : window area. Bmax is the peak flux density. Similarly the output voltage filtering circuit. A schematic chopper circuit along with the output filter is shown in Fig.3 tesla. as far as output voltage regulation is concerned the linear power supplies are superior to SMPS.jntuworld.22 f BmaxAC AW δ KW . Linear power supply though more bulky and less efficient has some advantages too when compared with the switched mode power supply. in a linear regulator circuit the excess voltage from the unregulated dc input supply drops across a series element (and hence there is power loss in proportion to this voltage drop) whereas in switched mode circuit the unregulated portion of the voltage is removed by modulating the switch duty ratio. where f is supply frequency.com . 15V high frequency transformer.3.com frequency ripple in voltage is effectively filtered using small values of filter capacitors and inductors. AC : core area. Some other switched mode power supply circuits work in a slightly different manner than the dc-to-dc chopper circuit discussed above.5 tesla and in high frequency transformer to be 0. in case of low frequency ripples is much bulkier than if the ripple is of high frequency. The switched mode circuit produces ripple of high frequency that can be filtered easily using smaller volume of filtering elements. δ : current density in copper and KW is the window utilization factor. In linear power supply the isolation and voltage-scaling transformer can be put only across the low frequency utility supply. Assume the peak flux density in low frequency transformer to be 1. Also. The low frequency transformer is very heavy and bulky in comparison to the high frequency transformer of similar VA rating. Problem 3 Estimate and compare the size (window area X core area) of the following two transformers: (i) a 50 VA.jntuworld. the switching related electro-magnetic interference (EMI) is practically absent in linear power supplies but is of some concern in SMPS circuits.

6 Multiple output SMPS A single power supply unit may need to output several different voltages. In case another output needs to have similarly tight regulation then that particular output may be passed through an additional linear regulator circuit as in the case of hybrid power supply circuit discussed in the previous section (Sec. Version 2 EE IIT. Kharagpur 8 www.com .com 21. Also the coupling between the different secondary windings and the primary winding may not be same causing different voltage drops across the respective leakage inductances. Let us consider a case where one needs an isolated and well-regulated 5 volts output while input power is drawn from utility supply that has large voltage fluctuation. The individual output voltages may have different ratings in terms of output current.jntuworld. Under the given condition it may not be difficult to see that the overall efficiency of this hybrid power supply will lie between that of a SMPS and a linear supply. including heat-sink ratings.5 volts input. The turns ratios are properly chosen to give fairly regulated individual output voltages (even if only one output voltage feedback is used for SMPS switch control). voltage regulation and ripple voltages. Linear power supply is highly inefficient if it has to work over large variations in input voltage. the control and filtering circuit may become more costly and complex (than the one used in the hybrid power supply unit). the linear power supply may be put in tandem with a switched mode supply.5 Hybrid (SMPS followed by linear) power supply A comparison of linear and switched mode power supplies tells about the advantages and disadvantages of the two. Similarly if the linear supply has to be designed for larger fluctuation in input voltage the component ratings. It may sometimes be required to have output voltage regulation similar to the one provided by linear supplies and compactness and better efficiency of a switched mode supply.jntuworld.5 volts input.5).www. The overall cost may or may not increase even though two supplies in tandem are used. 21. is more bulky because of the use of low frequency transformer and filter elements (inductors and capacitors). Barring this mismatch in the voltage drops across the resistances and leakage inductances of the secondary windings their output voltages are in proportional to their turns ratios. For this. Generally a common high frequency transformer links the input and output windings and in spite of output voltage feedback all the outputs can not have same regulation because of different loads connected to different outputs and hence different ohmic (resistive) drops in the output windings (loads are generally variable and user dependent). On the other hand linear power supplies give better output voltage regulation. The output that needs to have tighter voltage regulation may be used for output voltage feedback. The SMPS portion of the power supply efficiently performs the job of voltage isolation and conversion from widely varying utility voltage to fairly regulated 7. will be higher and may cost as much as the hybrid unit.5 volts dc. It can be seen that the linear power supply now does not have large input voltage variation in spite of large variations in the utility rms voltage. In such a situation one may generate an isolated 7. 21. These outputs may need isolation between them. It is to be kept in mind that to achieve the same output voltage specification by an SMPS circuit alone.5 volts from an SMPS and follow it by a 5 volts linear power supply set to work with 7. The input to linear power supply must be few volts more than the required output (for proper biasing of the switches) and hence SMPS tries to maintain around 7.

The fuse requirement (if any) on the input and the output side may need to be specified. Efficiency. USA) and 230 volts (common in India and many of the European countries). Some popular ones are: fly-back.com . It is quite common to have output voltage isolation and it is specified in terms of isolation breakdown voltage. short-circuit protection level of current (if any) and the nature of output volt-current curve during over-current or short circuit (the output voltage magnitude should reduce or fold back towards zero. In nonresonant mode SMPS circuits the switches are subjected to hard switching (during hardswitching. push-pull. The voltage levels commonly used are 115V (common in countries like. both the voltage and current in the switch are of considerable magnitude resulting in large instantaneous switching power loss). There may be short time ratings of higher magnitudes of current and continuous ratings of somewhat lower magnitudes. without having to pay much attention on the exact voltage and frequency levels of the utility supply. In case of multiple power supplies it needs to be specified whether all the outputs need to be isolated or not and what should be the acceptable ripple voltage range for each. In majority of the cases the available source of input power is the alternating type utility voltage of 50 or 60 Hz.com 21.jntuworld. In contrast some of the other power supplies have a selector switch and the user is required to adjust the switch position to match the utility voltage. gradually.7 Resonant Mode Power Supplies Resonant mode power supplies are a variation over SMPS circuits where the switching losses are significantly reduced by adapting zero-voltage or zero-current switching techniques. weight and volume are some other important specifications. One needs to specify the tolerable limits on the ripple voltages. 21. including their voltage and current ratings. Acceptable range of variation in input voltage magnitude. Most utility (mains) power supplies are expected to have ± 10% voltage regulation but for additional precaution the SMPS circuits must work even if input voltages have ± 20% variation. Version 2 EE IIT. C’uk.9 Some common types of SMPS circuits There are several different topologies for the switched mode power supply circuits. supply frequency (in case of ac input) are also to be specified.8 Power supply specifications Power supplies may have several specifications to be met. By electromagnetic compatibility it is meant that the level of EMI generation by power supply should be within tolerable limits and at the same time the power supply should have the ability to work satisfactorily in a limited noisy environment. These power supplies are very convenient for international travelers who can simply plug-on their equipments. One needs to specify the type of input supply (whether ac or dc) or whether the power supply can work both from ac or dc input voltages. the equipment attached may get damaged. forward.www. half bridge and H-bridge circuits. A particular topology may be more suitable than others on the basis of one or more performance criterions like cost. 21. Efficiency of resonant mode power supplies is generally higher than non-resonant mode supplies. Kharagpur 9 www. In case user forgets to keep the selector switch at correct position. Some of these configurations will be discussed in the coming lessons. Now-a-days universal power supplies that work satisfactorily and efficiently both on 115 V and 230 V input are quite popular.jntuworld. Some applications require the electro-magnetic compatibility standards to be met. depending on the severity of over-current). Sepic. like laptop computer and shaving machine.

overall weight and size. Problem 4 Which among the following power supplies will be most energy-efficient if operated under wide input voltage variation and at full load: (i) (ii) (iii) (iv) Linear power supply Switched mode power supply Switched mode followed by linear power supply Linear followed by switched mode power supply Answer: (ii) More Quiz problems on Chapter-21 (1) A regulated power supply should be able to maintain output voltage within specified limits in spite of (a) Unlimited variation in supply voltage (b) Unlimited variation in load at the output (c) Both (a) and (b) (d) Only for load and supply parameter. power supply specified to deliver regulated output for input supply (50Hz) variation from 180 volts to 270 volts will be different from another power supply with identical output rating but capable of outputting regulated voltage over input range of 90 volts to 270 volts in respect of:(a) Less cost (b) More bulky and more costly (c) Higher current rating of power-switch (d) None of the above Answers: (1-d).2V. output regulation.jntuworld. All the topologies listed above are capable of providing isolated voltages by incorporating a high frequency transformer in the circuit. Kharagpur 10 www.com . Most of these ICs are capable of driving MOSFET type of switches. 15V ± 0. output power. There are many commercially available power supply controller ICs that can readily be used to control the duty ratio of the SMPS switches so that the final output is well regulated.variations in the specified range (2) Linear isolated power supplies will generally be superior to switched-mode power supplies (outputting isolated voltage) in respect to the following (a) Higher efficiency in the entire range of load and supply variations (b) Better dynamic regulation of output voltage against supply variations (c) Less volume and weight for identical input and output ratings (d) All the above (3) High frequency transformers are used for output voltage isolation and scaling in the following type of power supplies:(a) Switched mode power supplies (b) Linear power supplies (c) Hybrid power supplies (d) Both (a) and (c) (4) A 60watt. voltage ripple etc. (4-a) Version 2 EE IIT.com efficiency.www. They also provide features like under voltage lock-out.jntuworld. (2-b). (3-d). output over-current protection etc.

Kharagpur 1 www.jntuworld.jntuworld.com Module 3 DC to DC Converters Version 2 EE IIT.www.com .

com Lesson 22 Fly-Back Type Switched Mode Power Supply Version 2 EE IIT. Kharagpur 2 www.jntuworld.com .www.jntuworld.

fly-back power supplies are inferior to many other SMPS circuits but its simple topology and low cost makes it popular in low output power range.com . As will be shown in the next section the primary and secondary windings of the fly-back transformer don’t carry current simultaneously and in this sense fly-back transformer works differently from a normal transformer. The present lesson is limited to the study of fly-back circuit of single switch topology. Since primary and Version 2 EE IIT. 22.1 Introduction Fly-back converter is the most commonly used SMPS circuit for low output power applications where the output voltage needs to be isolated from the input main supply. The circuit can offer single or multiple isolated output voltages and can operate over wide range of input voltage variation.22. 22. The ripple in dc voltage waveform is generally of low frequency and the overall ripple voltage waveform repeats at twice the ac mains frequency. Input to the circuit is generally unregulated dc voltage obtained by rectifying the utility ac voltage followed by a simple capacitor filter. like a MOSFET. Kharagpur 3 www.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the topology of a fly-back type switched mode power supply circuit. is used for voltage isolation as well as for better matching between input and output voltage and current requirements. may be considered to have a constant magnitude during any high frequency cycle. in spite of being unregulated. Primary and secondary windings of the transformer are wound to have good coupling so that they are linked by nearly same magnetic flux. The output power of fly-back type SMPS circuits may vary from few watts to less than 100 watts. In respect of energy-efficiency. The commonly used fly-back converter requires a single controllable switch like. A twoswitch topology exists that offers better energy efficiency and less voltage stress across the switches but costs more and the circuit complexity also increases slightly. MOSFET and the usual switching frequency is in the range of 100 kHz. under load.1 shows the basic topology of a fly-back circuit. Explain the principle of operation of fly-back SMPS circuit. Design a simple fly-back converter circuit. In a normal transformer. The overall circuit topology of this converter is considerably simpler than other SMPS circuits.1.jntuworld. is used with fast dynamic control over switch duty ratio (ratio of ON time to switching time-period) to maintain the desired output voltage.www.22.jntuworld. in Fig. primary and secondary windings conduct simultaneously such that the ampere turns of primary winding is nearly balanced by the opposing ampere-turns of the secondary winding (the small difference in ampere-turns is required to establish flux in the non-ideal core). A fast switching device (‘S’).2 Basic Topology of Fly-Back Converter Fig. The transformer. Input to the circuit may be unregulated dc voltage derived from the utility ac supply after rectification and some filtering. Since the SMPS circuit is operated at much higher frequency (in the range of 100 kHz) the input voltage. Calculate the ratings of devices and components used in fly-back converter for the specified input and output voltages and for the required output power.

The output section of the fly-back transformer. which consists of voltage rectification and filtering.jntuworld. a snubber circuit will be required to dissipate the energy stored in the leakage inductance of the primary winding when switch ‘S’ is turned off. Voltage across this filter capacitor is the SMPS output voltage. The input dc supply is also assumed to be ripple-free.1 is rather schematic in nature. Accordingly the magnetic circuit design of a fly-back transformer is done like that for an inductor. The magnetic circuit is assumed to be linear and coupling between primary and secondary windings is assumed to be ideal. some simplifying assumptions are made. It is quite common to have multiple secondary windings for generating multiple isolated voltages. are assumed loss-less. Thus the circuit operation is explained without consideration of winding leakage inductances.1 Fly Back Converter secondary windings of the fly-back transformer don’t conduct simultaneously they are more like two magnetically coupled inductors and it may be more appropriate to call the fly-back transformer as inductor-transformer. ON state voltage drops of switches and diodes are neglected. As can be seen from the circuit (Fig. Under this lesson. One of the secondary outputs may be dedicated for estimating the load voltage as well as for supplying the control power to the circuit.] Version 2 EE IIT. capacitors etc. The details of the inductor-transformer design are dealt with separately in some later lesson. the secondary winding voltage is rectified and filtered using just a diode and a capacitor.jntuworld. A more practical circuit will have provisions for output voltage and current feedback and a controller for modulating the duty ratio of the switch.1). is considerably simpler than in most other switched mode power supply circuits. 22. as will be discussed later.www.com N1:N2 Edc Primary Side D C Load VO Switch S Gate pulses Fig. the transformer core. It may be noted here that the circuit shown in Fig. Further.com . Kharagpur 4 www.22. for ease of understanding.22. The windings. [A brief idea of a more practical fly-back converter will be given towards the end of this lesson.

The following mathematical relation gives an expression for current rise through the primary winding: d EDC = LPr i × iPr i ------------------------------------------------------------(22. Each of these circuit configurations have been referred here as modes of circuit operation.3 Principle of Operation During its operation fly-back converter assumes different circuit-configurations. LPr i is inductance of the primary winding and iPri is the instantaneous current through primary winding. the fly-back circuit may have continuous flux operation or discontinuous flux operation.1.5(a) and Fig. Fig.2(b): Equivalent circuit in Mode-1 Under Mode-1.1). As may be seen from the circuit diagram of Fig. the conducting switch or diode is taken as a shorted switch and the device that is not conducting is taken as an open switch.2(b) shows the circuit that is functionally equivalent to the fly-back circuit during mode-1.22. The flux established in the transformer core and linking the windings is entirely due to the primary winding current. In the equivalent circuit shown.2(a) shows (in bold line) the current carrying part of the circuit and Fig.www. Kharagpur 5 www. when switch ‘S’ is on. As described later. the primary winding Version 2 EE IIT. the primary winding of the transformer gets connected to the input supply with its dotted end connected to the positive side. 22.com 22. having zero voltage drop during conduction and zero leakage current during off state. This representation of switch is in line with our assumption where the switches and diodes are assumed to have ideal nature. In case the circuit works in continuous flux mode.5(a) and Fig.5(b) correspond to circuit operations in continuous and discontinuous flux respectively.jntuworld.com . At this time the diode ‘D’ connected in series with the secondary winding gets reverse biased due to the induced voltage in the secondary (dotted end potential being higher). Vsec = Edc*N2/N1 + Edc VO + Edc Vpri Vsec VO N1 : N2 Fig.jntuworld. Since some flux is already present before ‘S’ is turned on. the magnetic flux in the transformer core is not reset to zero before the next cyclic turning ON of switch ‘S’. Linear rise of primary winding current during mode-1 is shown in Fig.5(b). The waveforms in Fig. Vpri = Edc . Thus with the turning on of switch ‘S’.22.22. 22. primary winding is able to carry current but current in the secondary winding is blocked due to the reverse biased diode. The complete operation of the power supply circuit is explained with the help of functionally equivalent circuits in these different modes. dt where EDC is the input dc voltage. the input supply voltage appears across the primary winding inductance and the primary current rises linearly. This mode of circuit has been described here as Mode-1 of circuit operation.22.2(a): Current path during Mode-1 of circuit operation Fig.22.22.22.

Fig.www.) Continuity of mmf. Vpri = VO*N1/N2 . the load connected to the output capacitor gets uninterrupted current due to the previously stored charge on the capacitor. in turn. Mmf. in magnitude and direction. During mode-1. in this case.22.com .jntuworld. voltage stress across the diode connected to secondary winding (which is now reverse biased) is the sum of the induced voltage in secondary and the output voltage ( Vdiode = VO + EDC × N 2 / N1 ). Vsec= VO + Edc VO + Edc Vpri Vsec VO N1: N2 Fig:22. the secondary winding voltage remains almost constant and equals to VSec = EDC × N 2 / N1 .3(a) : Current path during Mode-2 of circuit operation Fig. assuming a large capacitor. the voltage polarities across the windings reverse. Kharagpur 6 www. 22. is the algebraic sum of the ampere-turns of the two windings.3(b): Equivalent circuit in Mode-2 In mode-2. At the end of switch-conduction (i.e.3(a) abruptly rises to a finite value as the switch is turned on. Sudden change in flux will mean sudden Version 2 EE IIT. dotted end of secondary winding remains at higher potential than the other end.. end of Mode-1). though primary winding current is interrupted due to turning off of the switch ‘S’. the energy stored in the magnetic field of 2 the fly back inductor-transformer is equal to LPr i I P 2 .jntuworld. 22.3(a) shows the current path (in bold line) during mode-2 of circuit operation while Fig. Even though the secondary winding does not conduct during this mode. Current entering the dotted ends of the windings may be assumed to produce positive mmf and accordingly current entering the opposite end will produce negative mmf. 22. (mmf is magneto motive force that is responsible for flux production in the core. decides the energy stored in the magnetic field (energy per unit volume being equal to B 2 2μ . B being flux per unit area and μ is the permeability of the medium).3(b) shows the functional equivalent of the circuit during this mode. where I P denotes the magnitude of primary current at the end of conduction period. is automatically ensured as sudden change in mmf is not supported by a practical circuit for reasons briefly given below. The primary winding current path is broken and according to laws of magnetic induction. Under this condition.com current in Fig. the secondary winding immediately starts conducting such that the net mmf produced by the windings do not change abruptly. Mode-2 of circuit operation starts when switch ‘S’ is turned off after conducting for some time. During mode-1. [mmf is proportional to the flux produced and flux. Magnitude of the current-step corresponds to the primary winding current required to maintain the previous flux in the core. Reversal of voltage polarities makes the diode in the secondary circuit forward biased.

www. LSec and iSec are secondary winding inductance and current respectively. Under steady-state and under the assumption of zero on-state voltage drop across diode.5(a) and 22. Under this condition. switching frequency. The linear d decay of the secondary current can be expressed as follows: LSec × iSec = −VO ---------. The secondary winding current charges the output capacitor.5(b). some thing that a practical system cannot support. the energy output by the secondary winding equals the energy delivered to the load. Kharagpur 7 www.22. input dc supply. while charging the output capacitor (and feeding the load). The diode connected in the secondary circuit. switch duty ratio and the load at the output. if the off period of the switch is small. voltage stress across switch ‘S’ is the sum total of the induced emf in the primary winding and the dc supply voltage (Vswitch = EDC + VON1/N2). The circuit is then under continuous flux mode of operation. the secondary winding current abruptly rises from zero to I P N1 N 2 as soon as the switch ‘S’ turns off. like. 22. The steady-state magnitude of output capacitor voltage depends on various factors.5(b). The output capacitor however continues to supply uninterrupted voltage to the load. as shown in Fig.22.2). Alternately. 22.com .] For the idealized circuit considered here. This part of the circuit operation has been referred to as Mode-3 of the circuit operation.jntuworld. the secondary winding voltage during this mode equals VO and the primary winding voltage = VON1/N2 (dotted ends of both windings being at lower potential). N 1 and N 2 denote the number of turns in the primary and secondary windings respectively. dt Where. Flux linked by the windings remain zero until the next turn-on of the switch. the next turn on takes place before the secondary current decays to zero. The output capacitor is usually sufficiently large such that its voltage doesn’t change appreciably in a single switching cycle but over a period of several cycles the capacitor voltage builds up to its steady state value.jntuworld. As can be seen from the steady state waveforms of Figs. During discontinuous mode. allows only the current that enters through the dotted end. and the circuit is under discontinuous flux mode of operation. VO is the stabilized magnitude of output voltage.(22. The sudden rise of secondary winding current is shown in Fig.1. the secondary current gets sufficient time to decay to zero and magnetic field energy is completely transferred to the output capacitor and load. Capacitor voltage magnitude will stabilize if during each switching cycle. starts transferring energy from the magnetic field of the fly back transformer to the power supply output in electrical form. fly-back transformer parameters. It can be seen that the magnitude and current direction in the secondary winding is such that the mmf produced by the two windings does not have any abrupt change. Version 2 EE IIT. the secondary winding emf as well as current fall to zero and the diode in series with the winding stops conducting.com change in the magnetic field energy and this in turn will mean infinite magnitude of instantaneous power. after complete transfer of the magnetic field energy to the output. the secondary winding current decays linearly as it flows against the constant output voltage (VO). The secondary winding.5(a) and Fig. The + marked end of the capacitor will have positive voltage. If the off period of the switch is kept large.

com Mode-3 ends with turn ON of switch ‘S’ and then the circuit again goes to Mode-1 and the sequence repeats. Figs. Version 2 EE IIT.22.4(b) respectively show the current path and the equivalent circuit during mode-3 of circuit operation.22.5(b) show. the voltage and current waveforms of the winding over a complete cycle. Kharagpur 8 www.jntuworld.5(a) and 22. It may be noted here that even though the two windings of the fly-back transformer don’t conduct simultaneously they are still coupled magnetically (linking the same flux) and hence the induced voltages across the windings are proportional to their number of turns.4 (a) : Current flow path during Mode3 of circuit operation Fig.4(a) and 22.www. + Edc VO + Edc VO Fig:22.22.com .4(b): Equivalent circuit in Mode-3 Figs.jntuworld.

Kharagpur 9 www.com IP Io I pri 0 tON IP X N1 / N2 T Time Io X N1 / N2 I sec 0 tON EDC T Time V pri 0 MODE-1 VO X N1 / N2 tON MODE-2 T MODE-1 Time V load VO Time Fig.5(a): Fly-back circuit waveforms under continuous magnetic flux Version 2 EE IIT.jntuworld.22.jntuworld.com .www.

Vdiode = V0 + Edc (N2 / N1) -----------------------------------(22. the diode has to block a voltage (Vdiode) that equals to the sum of output voltage and reflected primary voltage during mode-1.4 Circuit Equations Under Continuous-Flux Operation The waveforms in Fig.3). Also. where V0 is the output voltage magnitude and ILoad denotes the load current. the primary winding voltage equals input supply voltage and when the switch is OFF the reflected secondary voltage appears across the primary winding.5(a).22.jntuworld.6a) Since the intended switching frequency for SMPS circuits is generally in the range of 100kHz. Similarly the secondary winding and the diode put in the secondary circuit must be rated to carry a repetitive peak current equal to the maximum expected load current. The switch and the transformer primary winding must be rated to carry a repetitive peak current equal to IP (related to maximum output power as given by Eqns. it has to block a voltage (Vswitch) that equals to the sum of input voltage and the reflected secondary voltage during mode-2.com 22. When the switch is ON.www. The magnetic core of the high frequency inductor-transformer must be chosen properly such that the core does not saturate even when the primary winding carries the maximum expected current. the transformer Version 2 EE IIT.. ‘tON’ denotes the time for which the fly-back switch is ON during each switching cycle. Under the assumption of ideal switch and diode.jntuworld.e. Equating energy input and energy output of the converter (the converter was assumed loss-less) in each supply cycle. Under steady state the energy input to primary winding during each ON duration equals: 0.4). i. In terms of input supply voltage (Edc) and the primary winding inductance ( LPr i ) the following relation holds: (IP . ‘T’ stands for the time period of the switching cycle.6). The mean (dc) voltage across both primary and secondary windings must be zero under every steady state.5). Edc δ = (N1 / N2) V0 (1-δ) ------------------------------------------(22.5Edc (IP + I0) δT and similarly the output energy in each cycle equals V0 ILoad T.I0) = (Edc / LPr i ) δT ------------------------------------------(22.5Edc (IP + I0) δ = V0 ILoad ------------------------------------------(22. 22. the primary winding current rises from I0 to IP in ‘δT’ time. When the switch is OFF. Vswitch = Edc + (N1 / N2) V0 -----------------------------------(22. the switch and the diode used in the fly-back circuit must be capable of operating at high frequency. Kharagpur 10 www. The ratio ( tON /T) is known as the duty cycle (δ) of the switch. Thus.3 to 22.com .22. where N1 and N2 are the number of turns in primary and secondary windings and (N1/N2)V0 is the reflected secondary voltage across the primary winding (dotted end of the windings at lower potential) during mode-2 of circuit operation. As can be seen from Fig.5). When the switch in ON. One needs to know the required ratings for the switch and the diode used in the converter. one gets: 0.5(a) correspond to steady state operation under continuous magnetic flux.

com . 2 Version 2 EE IIT. During mode-3 of the circuit operation. the eddy current related loss in the core is generally insignificant. continues to get a reasonably steady voltage due to the relatively large output filter capacitor. The load.com core (made of ferrite material) must have low hysteresis loss even at high frequency operation. the primary winding current starts building up linearly from zero and at the end of mode-1 the magnetic field energy due to primary winding current rises to 1 2 L pri I P . 2 Under the assumption of loss-less operation the output power (Po) can be expressed as: Po = 1 2 L pri I P fswitch -----------------------------------(22. 22.22.www. Kharagpur 11 www.5(b) shows some of the important voltage and current waveforms of the fly-back circuit when it is operating in the discontinuous flux mode.jntuworld.5(b): Fly-back circuit waveforms under discontinuous flux With the turning ON of the switch. IP I pri 0 tON IP X N1 / N2 T Time I sec 0 tON EDC T Time V pri 0 VO X N1 / N2 tON MODE-1 MODE-2 MODE-3 T Time MODE-1 V load 0 VO Time Fig. 22.7). however. Since the ferrite cores have very low conductivity. primary and secondary winding currents as well as voltages are zero. This entire energy is transferred to the output at the end of mode-2 of circuit operation.5 Circuit Equations Under Discontinuous-Flux Mode Fig.jntuworld.

8) will correspond to just-continuous case. The off duration of the switch.com .7 A Practical Fly-Back Converter The fly-back converter discussed in the previous sections neglects some of the practical aspects of the circuit.4).. will hold good in discontinuous mode also.jntuworld. However a practical converter will have device voltage drops and losses. The controller modulates the duty ratio of the switch to maintain the output voltage within a small tolerable ripple voltage band around the desired output value. which is the boundary between continuous and discontinuous mode of operation. Within this small ON time only a small amount of current builds up in the primary winding.5) gets modified under discontinuous flux mode of operation as follows: Edc δ ≤ (N1 / N2) V0 (1-δ) ------------------------------------------(22. 22. The expression for Vswitch and Vdiode. Thus.(22. the winding voltages are zero.com where fswitch (=1/T) is the switching frequency of the converter. This is achieved by keeping the ON duration of the switch low. The circuit operation changes from discontinuous to continuous flux mode if the output power from the circuit increases beyond certain value. The equality sign in Eqn.6) and (22. The designed input power (Pin) should be equal to Po/η. more output power can be transferred during continuous flux mode.(22. As the load increases the mode-3 duration.(22. A typical figure for η may be Version 2 EE IIT. A common design thumb rule is to design the circuit for operation at just-continuous flux mode at the minimum expected input voltage and at the maximum (rated) output power.6 Continuous Versus Discontinuous Flux Mode of Operation A practical fly-back type SMPS circuit will have a closed loop control circuit for output voltage regulation. where Po is the required output power and η is the efficiency of the circuit.www. However. the circuit is in mode-3 for significant duration. for the given transformer and switch ratings etc. discontinuous flux mode of operation is preferred. at light load.6a). Similarly if the applied input voltage decreases. resulting in low duty ratio (δ). very small amount of energy needs to be input to the circuit in each switching cycle. as given in Eqns. The volt-time area equation as given in Eqn. If the load is very light. The coupling between the primary and secondary windings will not be ideal. 22. keeping the load power and switching frequency constant. It may be noted that output power Po is same as ‘V0 ILoad’ used in Eqn. reduces and the circuit is driven towards continuous flux mode. Mode-2 duration of the circuit operation is also small as the magnetic field energy is quickly discharged into the output capacitor. which is (1-δ) fraction of the switching time period.22. For better control over output voltage.8) Average voltage across windings over a switching cycle is still zero. This zero voltage duration had been identified earlier as mode-3 of the circuit operation. during which there is zero winding currents and zero flux through the core.8 is due to the fact that during part of the OFF period of the switch [= (1-δ)T].(22. is relatively large.jntuworld. The loss part of the circuit is to be kept in mind while designing for rated power. Kharagpur 12 www. The simplified and idealized circuit considered above essentially conveys the basic idea behind the converter. the circuit tends to go in continuous flux mode of operation. The inequality sign of Eqn. the transformer shown will also have some losses.

Since the snubber capacitor voltage is kept higher than the reflected secondary voltage.www. Unless this energy finds a path. The tertiary winding voltage is rectified in a way Version 2 EE IIT. In order to maintain ohmic isolation between the output voltage and the input switching circuit the output voltage signal needs to be isolated before feeding back. Fig. for closed loop output voltage regulation.com taken close to 0. a Pulse Width Modulation (PWM) control circuit to control the duty ratio of the switch.6 for first design iteration. This can be achieved by proper choice of the snubber-resistor and by keeping the RC time constant of the snubber circuit significantly higher than the switching time period. The leakageinductance current of the primary winding finds a low impedance path through the snubber diode to the snubber capacitor.6 shows a practical fly-back converter. The power lost in the snubber circuit reduces the overall efficiency of the fly-back type SMPS circuit.22. To check the excessive voltage build up across the snubber capacitor a resistor is put across it. Kharagpur 13 www. the minimum steady state snubber capacitor voltage should be greater than the reflected secondary voltage on the primary side. In practical fly-back circuits. there will be a large voltage spike across the windings which may destroy the circuit. A popular way of feeding the isolated voltage information is to use a tertiary winding. The flux associated with the primary winding leakage inductance will not link the secondary winding and hence the energy associated with the leakage flux needs to be dissipated in an external circuit (known as snubber).jntuworld.22. one needs to feed output voltage magnitude to the PWM controller. A typical figure for efficiency of a fly-back circuit is around 65% to 75%. S N U B B E R N1:N2 D Edc RS C Load V (o/p) N3 PWM Control Block Current Feedback Fig. In order that snubber capacitor does not take away any portion of energy stored in the mutual flux of the windings.6 A Practical Fly Back Converter The circuit in Fig. Under steady state this resistor is meant to dissipate the leakage flux energy.com . in block diagram. It can be seen that the diode end of the snubber capacitor will be at higher potential. Due to the non-ideal coupling between the primary and secondary windings when the primary side switch is turned-off some energy is trapped in the leakage inductance of the winding. the worst-case switch voltage stress will be the sum of input voltage and the peak magnitude of the snubber capacitor voltage. The snubber circuit consists of a fast recovery diode in series with a parallel combination of a snubber capacitor and a resistor. Similarly one needs to counter the effects of the nonideal coupling between the windings. 22.6 also shows.jntuworld.

) (a) Output voltage varies directly with switching frequency. Else.www. it may not be possible to compensate exactly for the secondary winding resistance drop as the tertiary winding is unaware of the actual load supplied by the secondary winding. (iii) A fly-back converter has primary to secondary turns ratio of 15:1. (d) Output voltage is independent of switching frequency. how will the output voltage change with change in switching frequency? (Assume discontinuous conduction through out and neglect circuit losses. Less than 18 volts. Version 2 EE IIT. What should be the snubber capacitor voltage under steady state? (a) (b) (c) (d) More than 270 volts. multiple isolated output voltages are required. (c) Output voltage varies directly with square root of switching frequency. The rectified tertiary winding voltage also doubles up as control power supply for the PWM controller. For initial powering up of the circuit the control power is drawn directly from the input supply through a resistor (shown as RS in Fig. Assuming input voltage and the resistive load at the output to remain constant. The rectified tertiary voltage will be nearly proportional to the secondary voltage multiplied by the turns-ratio between the windings. Kharagpur 14 www. Each rectifier and filter circuit uses the simple diode and capacitor as shown earlier for a single secondary winding. In case. where a tertiary winding is used for voltage feedback. The input voltage is constant at 200 volts and the output voltage is maintained at 18 volts. one needs to improve the voltage regulation by adding a linear regulator stage in tandem (as mentioned in Chapter-21) or by giving a direct output voltage feedback to the control circuit. (ii) A fly-back converter operates in discontinuous conduction mode with fixed ON duration of the switch in each switching cycle. In the practical circuit shown above. the fly-back transformer will need to have multiple secondary windings. Each of these secondary winding voltages are rectified and filtered separately.com similar to the rectification done for the secondary winding. More than 200 volts but less than 270 volts. However for most applications the small voltage drop in the winding resistance may be tolerable.jntuworld. Quiz Problems (i) What kind of output rectifier and filter circuit is used in a fly back converter? (a) a four-diode bridge rectifier followed by a capacitor (b) a single diode followed by an inductor-capacitor filter (c) a single diode followed by a capacitor (d) will require a center-tapped secondary winding followed by a full wave rectifier and a output filter capacitor. (b) Output voltage varies inversely with switching frequency.6) connected between the input supply and the capacitor of the tertiary circuit rectifier.22.jntuworld.com . The resistor ‘RS’ is of high magnitude and causes only small continuous power loss. Not related to input or output voltage.

(iii-a).com .com (iv) A fly-back converter is to be designed to operate in just-continuous conduction mode when the input dc is at its minimum expected voltage of 200 volts and when the load draws maximum power. Version 2 EE IIT.jntuworld. (a) (b) (c) (d) 20 :1 30 :1 25 :2 50 :1 Answers to quiz problems: (i-c).jntuworld. (ii-c). The load voltage is regulated at 16 volts. (iv-d). Kharagpur 15 www. What should be the primary to secondary turns ratio of the transformer if the switch duty ratio is limited to 80%.www. Neglect ON-state voltage drop across switch and diodes.

com .www.jntuworld.jntuworld. Kharagpur 1 www.com Module 3 DC to DC Converters Version 2 EE IIT.

com Lesson 23 Forward Type Switched Mode Power Supply Version 2 EE IIT. Kharagpur 2 www.jntuworld.www.jntuworld.com .

The basic operation of the circuit is explained here assuming ideal circuit elements and later the non-ideal characteristics of the devices are taken care of by suitable modification in the circuit design. A Version 2 EE IIT. a transformer with its primary winding connected in series with switch ‘S’ to the input supply and a rectification and filtering circuit for the transformer secondary winding. especially the output filtering circuit is not as simple as in the fly-back converter. Fig. 23. a tertiary winding needs to be introduced in the transformer and the circuit topology changes slightly. is generally more energy efficient and is used for applications requiring little higher power output (in the range of 100 watts to 200 watts).jntuworld.1: Basic Topology of a Forward Converter The transformer used in the forward converter is desired to be an ideal transformer with no leakage fluxes. when compared with the fly-back circuit. As in the case of fly-back converter (lesson-22) the input dc supply is often derived after rectifying (and little filtering) of the utility ac voltage. However the circuit topology. due to the presence of finite magnetizing current in a practical transformer. Design a simple forward type switched mode power supply circuit. Kharagpur 3 www. 23. Calculate the ratings of devices. The forward converter. It consists of a fast switching device ‘S’ along with its control circuitry. The load is connected across the rectified output of the transformer-secondary. transformer turns ratio for the given input and output voltages and the required output power.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the topology of a forward type switched mode power supply circuit.jntuworld.1 shows the basic topology of the forward converter. zero magnetizing current and no losses.com .www.1 Introduction Forward converter is another popular switched mode power supply (SMPS) circuit that is used for producing isolated and controlled dc voltage from the unregulated dc input supply. NP : NS L Edc D1 D2 C Load V (o/p) Control Circuit Switch S Fig. Explain the principle of operation of a forward dc-to-dc power supply. In fact. 23. components.

When switch ‘S’ is turned off. [As per the circuit topology of Fig. Version 2 EE IIT. Dotted sides of both the windings are now having positive polarity. The following simplifying assumptions are made before proceeding to the detailed modewise analysis of the circuit: • ON state voltage drops of switches and diodes are neglected. as per the assumption of an ideal transformer. The required emf to maintain continuity in filter-inductor current and to maintain the forward bias voltage across D2 comes from the filter inductor ‘L’ itself.1 is basically a dc-to-dc buck converter with the addition of a transformer for output voltage isolation and scaling. Under steady state condition. 23.23. the circuit’s operation is divided in two different modes. mode-1 and mode-2. Needless to say. Similarly. Also.jntuworld. the ESR and ESL of a practical capacitor causes ripple in its dc output voltage due to flow of ripple current through these series impedances. The supply switching frequency is generally kept sufficiently high such that the next turn-on of the switch takes place before the filter inductor current decays significantly. connected in series with the secondary winding gets forward biased and the scaled input voltage is applied to the low pass filter circuit preceding the load. During freewheeling the filter inductor current will be decaying as it flows against the output voltage (Vop). For maintaining constant load current. Kharagpur 4 www. Since the output voltage is drawn from capacitor terminal the ripple in output voltage will be less if the capacitor is made to carry less ripple current. but the presence of relatively large filter capacitor ‘C’ still maintains the output voltage nearly constant.www.1. Diode ‘D2’ provides the freewheeling path for this current. The switching-on and switching-off times of the switch and diodes are neglected. Mode-1 corresponds to the ‘on’ duration of the switch and mode-2 corresponds to its ‘off’ duration. the inductor and the capacitor together share the load-current drawn from the output. The ripple in the output voltage must be within the acceptable limits. Current through the filter inductor and the load continues without any abrupt change.com .] For better understanding of the steady-state behavior of the converter. The primary winding current enters through its dotted end while the secondary current comes out of the dotted side and their magnitudes are inversely proportional to their turns-ratio. the primary as well as the secondary winding currents are suddenly brought down to zero. leakage currents through the off state devices is assumed zero. mean dc current supplied by the capacitor is zero but capacitor still supplies ripple current. 23. Diode ‘D1’. the net magnetizing ampere-turns of the transformer is zero and there is no energy stored in the transformer core. input dc gets applied to the primary winding and simultaneously a scaled voltage appears across the transformer secondary. Thus.com more practical type forward converter circuit is discussed in later sections. that the magnitudes of filter inductor and capacitor are to be chosen appropriately. The idea behind keeping filter inductor current nearly constant is to relieve the output capacitor from supplying large ripple current.2 Principle of Operation The circuit of Fig.jntuworld. Capacitors with higher ripple current rating are required to have much less equivalent series resistor (ESR) and equivalent series inductor (ESL) and as such they are bulkier and costlier. the inductor and capacitor currentripples must be equal in magnitude but opposite in sense. When switch ‘S’ is turned on.

diode D1 in the secondary circuit gets forward biased and the input voltage. 23.com . starts with turning off of the switch ‘S’. as defined in the previous chapters is assumed constant.23.com • • • • The transformer used in the circuit is assumed to be ideal requiring no magnetizing current. the output circuit consisting of L-C filter and the load gets a voltage equal N to S Edc during mode-1.jntuworld. inductors and capacitors are assumed loss-less.2 (b) shows the functional equivalent circuit of mode-1. the primary and the secondary winding currents of the transformer fall to zero. For the simplified steady-state analysis of the circuit the switch duty ratio (δ).23. Mode-1 of Circuit Operation Mode-1 of circuit starts after switch ‘S’ (as shown in Fig. L C Load L P NS Edc NP N C Load VO S Fig. as it remains reverse biased. to be called as freewheeling mode. the current carrying path of the circuit and Fig. scaled by the transformer turns ratio. to the primary winding. Both primary and secondary windings start conducting simultaneously with the turning on of the switch. Mode-2 of Circuit Operation As soon as switch ‘S’ is turned off. Diode D2 does not conduct during mode-1.23. This connects the input voltage. The input and output dc voltages are assumed to be constant and ripple-free.www.1) is turned ON. Edc. Mode-1 can be called as powering mode during which input power is transferred to the load. The primary and secondary winding currents and voltages are related to their turns-ratio (NP / NS). Diode ‘D1’ remains off during this mode and isolates the output section of the circuit from the transformer and the input.2(a): Current path during Mode-1 Fig. as in an ideal transformer.jntuworld.2(b) and it is NP the maximum achievable dc voltage across the load. Mode-2. Fig. Current through the filter inductor (L) is assumed to be continuous. D2 Off. 23. corresponding to δ = 1. As switch ‘S’ closes. However. Kharagpur 5 www. having no leakage inductance and no losses. The filter circuit elements like. This voltage is shown across points ‘P’ and ‘N’ in Fig. NP: NS D1 Edc D2 Switch ‘S’ and D1 ON.23.2(b): Equivalent circuit in Mode-1 As can be seen. Version 2 EE IIT. the secondary side filter inductor maintains a continuous current through the freewheeling diode ‘D2’. gets applied to the secondary circuit. in bold lines.2 (a) shows.

jntuworld.2(b): Equivalent circuit in Mode-2 Fig. It may not be difficult to see that to maintain load voltage within the desired tolerance band the filter inductor and capacitor magnitudes should be sufficiently large. As mentioned earlier.3(b) shows the equivalent circuit active during mode-2. L C Load P L C N Load VO S Fig. the stored energy of the filter inductor and capacitor will be slowly dissipating in the load and hence during this mode the magnitudes of inductor current and the capacitor voltage will be falling slightly. for faster dynamic control over the output voltage the filter elements should not be too large. the switch and the diodes have been assumed to be ideal.jntuworld. With the assumption of Version 2 EE IIT. The higher end limit on the switching frequency comes mainly due to the finite switching time and finite switching losses of a practical switch. The charged capacitor and the inductor provide continuity in load voltage. Points ‘P’ and ‘N’ of the equivalent circuit are effectively shorted due to conduction of diode ‘D2’.com NP: NS D1 Edc D2 Switch ‘S’ and D1 Off. Relation Between Input and Output Voltage The equivalent circuits of mode-1 and mode-2 can be used to derive a steady state relation between the input voltage. there is no power flow from source to load but still the load voltage is maintained nearly constant by the large output capacitor ‘C’. with no losses and zero switching time. switch duty ratio (δ) and the output voltage. The switching frequency of a typical forward converter may thus be in the range of 100 kHz or more. In order to keep the load voltage magnitude within required tolerance band. Control over switch duty ratio. High frequency operation of switch ‘S’ will help in keeping the filter and transformer size small.3(a) shows the current carrying portion of the circuit in bold line and Fig. 23. Under steady state. Also. During mode-2.com . However. [It may be pointed out here that the filter inductor.] One important factor that directly influences the size of the filter circuit elements and the transformer is the converter’s switching frequency. The inductor current continues to flow through the parallel combination of the load and the output capacitor. the converter-switch ‘S’ is turned on again to end the freewheeling mode and start the next powering mode (mode-1). transformer and the heat sinks for the switching devices together account for nearly 90% of the power supply weight and volume. loss in inductor current and capacitor voltage in mode-2 is exactly made up in mode-1. However since there is no input power during mode-2. Switch limitations have been ignored in the simplified analysis presented here. which is the ratio of ON time to (ON + OFF) time. capacitor.www.3(a): Current path during Mode-2 Fig.23. Kharagpur 6 www. D2 ON. in order to keep the filter cost and its physical size small these elements should not be unnecessarily too large. 23. 23. provides the control over the output voltage ‘VO’.

VO .4 shows the circuit topology of a practical forward converter.3). The inductor voltage during mode-2 may similarly be written as: eL (t) = . for δT ≤ t ≤ T.3(b) are no longer shorted. In fact. one gets: N [ S Edc .1) NP Where t = 0 is the time instant when mode-1 of any steady state switching cycle starts.VO ] (1-δ) = 0. averaged over a steady state cycle time. (23.3) is valid only under the assumption of continuous inductor current. For better control over output voltage discontinuous inductor current mode is generally avoided. the output voltage. Under discontinuous inductor current the relation between output voltage and switch duty ratio becomes non-linear and is load dependent. VO = δ S Edc ------------------------------. It may be noticed that except for transformer scaling factor the output voltage relation is same as in a simple dc-to-dc buck converter. Thus equation (23. the forward converter output voltage is directly proportional to the switch duty ratio.VO ] δ + [.VO . Once the inductor current becomes zero. Other non-idealities of the circuit elements like that of switch. 23. With prior knowledge of the load-range and for the desired switching frequency the filter inductor may be suitably chosen to keep the inductor current continuous and preferably with less ripple. Most common consequence of non-ideal nature of circuit elements is increase in looses and hence reduction in efficiency of the power supply. which is the average of voltage across points ‘P’ and ‘N’ will have a higher magnitude than the one given by Eqn.2) remains valid only for a part of (1-δ) T period. the output voltage ‘VO’ will appear across ‘P’ and ‘N’. NP N Or. Version 2 EE IIT. Once the efficiency figure has been considered the circuit may still be designed based on the simplified analysis presented here. It is to be noted that the output voltage relation given by Eqn. -------------------------------.(23.com constant input and output voltage. (23. diode ‘D2’ in Fig.3) NP Thus according to Eqn. must always be zero. diodes. 23.jntuworld.3(a) no longer conducts and the points ‘P’ and ‘N’ of the equivalent circuit in Fig. the inductor current may decay to zero in the midst of mode-2 resulting into discontinuous inductor current. It takes into account the nonideal nature of a practical transformer. inductor and capacitor are taken care of by modifying the circuit parameters chosen on the basis of ideal circuit assumption. A practical way to get around the consequence of circuit losses is to over-design the power supply. As a first order approximation.jntuworld. the instantaneous value of inductor voltage (eL) during mode-1 can be written as: N eL (t) = S Edc . T is the switching time period that may be assumed to be constant and δ is the duty ratio of the switch. -------------------------------.com . for 0 ≤ t ≤ δT. In case of discontinuous inductor current.3 Practical Topology of A Forward Converter Circuit Fig.3). where ‘ Po ’ is the required output power η and ‘ η ’ is the efficiency of the converter. Kharagpur 7 www.2) Now since voltage across an inductor. a typical efficiency figure of around 80% may be assumed for the forward converter. 23. 23.(23. (23. For an improperly designed circuit or for very light load at the converter output.(23. P The design should aim to achieve an output power of o . It can be seen that δT is the time duration of mode-1 and (1-δ) T is the time duration of mode-2.www.

the variation in input supply is taken care of by modulating the switch duty ratio in such a manner that it offsets the effect of supply voltage fluctuation and continues to give the required quality of output voltage. Any attempt to change flux suddenly results in generation of infinitely large magnitude of voltage (in accordance with Lenz’s law). Another common non-ideality is the low frequency ripple and fluctuation in input dc supply voltage. Thus. The forward-converter transformer works like a normal power transformer where both primary and secondary windings conduct simultaneously with opposing magneto motive force (mmf) along the mutual flux path.6 for a fly-back circuit (refer to lesson-22). Such a large voltage in the circuit will have a destructive effect and that should be avoided.com . The non-ideality of the transformer. The sudden rise in magnitude of negative potential across the windings is checked only by the conduction of current through the tertiary winding. reduces the power-supply efficiency considerably. The difference of the mmfs is responsible for maintaining the magnetizing flux in the core. 23. Current entering the dot through any of the magnetically coupled windings will produce magnetic flux in the same sense. The dot markings on the windings are to be observed. the magnetic coupling between these two windings must be very good.4. Kharagpur 8 www.jntuworld. As soon as switch ‘S’ is turned off. there must exist a convenient path for the trapped energy in the primary due to magnetizing current. as has been seen in connection with fly-back converter.www. In fly-back transformer’s flux path some air-gap is deliberately introduced by creating a gap in the transformer core (refer to lesson-22).22. however. as shown in Fig. turning off of switch ‘S’ will result in sudden demagnetization of the core from its previously magnetized state.com which neglects many of the non-idealities. As discussed earlier unless the continuity in transformer flux is maintained the voltages in the windings will theoretically reach infinite value. after switch ‘S’ is turned off. When primary winding current is interrupted by switching off ‘S’. This results in simultaneous opening of both primary and secondary windings of the transformer. as discussed above. As discussed in Lesson-22. Each time the switch ‘S’ is turned off the snubber circuit will dissipate the energy associated with the magnetizing flux. Similarly there will be some leakage inductance of the windings. In a practical circuit. However. When both switch ‘S’ and ‘D1’ turn-off together. Introduction of air gap in the mutual flux path increases the magnitude of leakage inductances. In the simplified analysis input supply has been assumed to be of constant magnitude. This.1. cannot simply be overcome by changing the circuit parameters of the simplified circuit shown in Fig. similar to the one shown in Fig. windings of the forward-converter transformer will have much smaller leakage inductances than those of fly-back converter transformer. A practical transformer will have finite magnetization current and finite energy associated with this magnetization current. 23. A more preferred solution is to recover this energy. For this the primary and tertiary winding turns Version 2 EE IIT. Thus turning off of switch ‘S’ and turn-on of diode ‘D3’ need to be simultaneous.jntuworld. Negative potential of the dotted end of secondary winding makes diode ‘D1’ reverse biased and hence it also stops conducting. Transformer of a forward converter should have no air-gap in its flux path. For this reason the practical forward converter uses an extra tertiary winding with a series diode. the dotted ends of the windings develop negative potential to oppose the interruption of current (in accordance with Lenz’s law). 23. Similarly fall in magnetizing current through primary winding must be coupled with simultaneous rise of magnetization current through the tertiary winding. the magnetization energy will cause a current flow through the closely coupled tertiary winding and the diode ‘D3’. the dotted end voltages of the windings will become negative in accordance with Lenz’s law. In order that the entire flux linking the primary winding gets transferred to the tertiary. a practical circuit cannot support sudden change in flux.1 is used along with a practical transformer. One solution could be a snubber circuit across the primary winding. In case the basic circuit of Fig.

many of the ideal circuit assumptions have been made. ‘IL’ is the current through filter inductor ‘L’. with dotted end at negative NT potential. 23. primary winding gets input dc voltage (with its dotted end positive). As switch ‘S’ turns on. known as bifilar windings. NT : NP : NS L Edc D1 D2 C Load V (o/p) D3 Switch S Fig. ‘VPr’ denotes the primary winding voltage.4: Circuit topology of a practical forward converter Fig.4.com are wound together. VD3 is the voltage across diode ‘D3’.com . 23. Primary and secondary windings have induced voltages due N to transformer action. The net volt-time area of the primary Version 2 EE IIT. Similarly the inductor current decays at a constant rate in mode-2 as it flows against the constant output voltage. In Fig. The transformer magnetization current is assumed to be negligibly small and hence the primary winding essentially carries the reflected inductor current.23. Average magnitude of inductor current equals the load current. once again. Kharagpur 9 www. Switch conducts only during mode-1 and carries the primary winding current (IPr) of the transformer. The wires used for bifilar windings of the primary and the tertiary need to withstand large electrical voltage stress and are costlier than ordinary transformer wires. 23.5 shows some of the typical current and voltage waveforms of the forward converter shown in Fig. Diode ‘D3’ of the tertiary N winding is reverse biased and is subjected to a voltage − Edc (1 + T ) . 23.jntuworld.1.5. primary and secondary winding currents fall to zero but diode ‘D3’ gets forward biased and the tertiary winding starts conducting to maintain a path for the magnetizing current. Primary winding voltage equals to Edc P .jntuworld.www. 23. For these waveforms. In Fig. ISW and VSW are respectively the switch current and switch voltage.5. NP As soon as switch ‘S’ is turned-off. Vload is the converter output voltage that is maintained constant at VO. The induced voltages in other windings are in proportion to their turns ratios. The inductor current rises linearly during mode-1 as its voltage is maintained constant as per Eqn. While ‘D3’ conducts the tertiary winding voltage is clamped to input dc voltage with its dotted end negative.

or δ ≤ ------------------------------.5 may be combined to t t show that T = P .(23. On the other hand. ----------------------------.6) ( N P + NT ) 1 − δ NT Thus if N P = NT . tP = δT = on-duration of switch ‘S’ and the tertiary winding conducts only during off duration of switch (during mode-2). Less duty ratio means less duration of powering mode (mode-1) and hence less transfer of power to the output N circuit. As a result. 23. Version 2 EE IIT. if P is increased for higher duty ratio.com . Now. Voltage across switch ‘S’ can be seen to be the N sum of primary winding voltage and the input voltage and equals Edc (1 + P ) .www. as described above. Φ m = flux through the transformer core. Hence. the switch NT voltage stress increases. When switch ‘S’ is again turned on.4) Where. (1-δ) T ≥ tT . Kharagpur 10 www. the transformer flux builds up d Φm = Edc . diode ‘D3’ turns off and voltage across transformer windings fall to zero.4 and 23.5) linearly given by the relation: N P dt Under steady-state the increase in flux during conduction of switch ‘S’ must be equal to fall in flux during conduction of tertiary winding and hence Eqns. The transformer remains de-magnetized for the remaining duration of Mode-2. NT As the tertiary winding current flows against the input dc supply. in the next switching cycle. the magnetization current decays linearly given by the following relation: NT d Φm = − Edc dt -------------------------------.(23. When the transformer is completely demagnetized. where tT and tP are the time durations for which tertiary and primary NT N P windings conduct during each switching cycle.jntuworld.(23. N NP δ ≤ P .com winding voltage must be zero under steady state. the duty ratio must be less than or equal to 50% or else the transformer magnetic circuit will not get time to reset fully during mode-2 and will saturate.jntuworld.

23.4 Selection of Transformer Turns Ratio The transformer-winding turns ratio is a crucial design factor. For the required output voltage N (VO). the turns ratio S is found after considering the minimum magnitude of input supply NP Version 2 EE IIT.com .jntuworld. The primary to secondary turns ratio of the transformer is decided in accordance with Eqn. 23.com V load 0 VO Imax Time IL 0 Imin tON Imax (NS / NP) T Time I Pr 0 tON Edc T Time V Pr 0 − Edc NP NT Time 0 Time − Edc NP ) NT Edc V D3 − Edc (1 + NT ) NP Edc (1 + V sw 0 tON = δ T MODE-1 MODE-2 T MODE-1 Time Fig.3. Kharagpur 11 www.www.5: Some Typical waveforms of a practical Forward converter circuit 23.jntuworld.

Imin) = δT ( S Edc . the switch voltage stress reduces but allowable duty ratio of switch and the power output of the converter becomes low and diode ‘D3’ voltage rating increases. In this section.1. The filter capacitor merely supplies the ripple (ac) current of switching frequency. 23. Higher voltage stress will mean higher cost of switch. as a thumb rule.23.(23. In many cases the minimum value of load current may not be specified or may be too low.com .3. some simple guidelines have been developed to arrive at the required filter size.5 Selection of Filter Circuit Inductor and Capacitor The transformer’s secondary voltage is rectified and filtered suitably to get the desired quality of output voltage waveform. (Imax .com voltage ( Edc ) and the maximum allowable duty ratio (δ). 23. If the load connected to the output is very light or if there is no load. Inductor current waveform during a typical switching cycle has been shown in Fig. N L = δT ( S Edc . Input supply voltage.7) NP Thus for Imin = 0 and Imax = 0. This gives a basis for choosing the inductor value as detailed below: With reference to the waveforms in Fig. the inductor current may be assumed to be just continuous. is assumed to have a fixed magnitude. the inductor current is desired to be continuous (refer to Eqn. under just continuous inductor current.5.jntuworld. mean (dc) value of inductor current equals the load current. N Again. If the tertiary winding turns is kept very high. The filter inductor and capacitor values need to be chosen optimally to arrive at a cost-effective. may itself be varying and the duty ratio is adjusted to keep VO constant in accordance with N Eqn.1 Irated. using Eqn. as discussed above.VO)/ (0.5 Imax = 0.3). As described earlier. In case the inductor current becomes discontinuous the linearity between switch duty ratio and output voltage is lost and the output-voltage controller circuit. the inductor current will not remain continuous.23. the filter inductor size may be chosen such that the inductor current remains continuous for more than 10% of the rated load current. 23.23.8) where VO. which is often designed using linear control theory. where Irated is the rated load current. Hence. is constrained by the primary to tertiary winding turns ratio (given by Eqn. The maximum duty ratio of the converter.VO)/L ------------------.5 (Imin + Imax) = 0.jntuworld.5. less bulky power supply.www. It has also been mentioned earlier that for linear relation between the output voltage and the switch duty ratio. Thus an optimum design needs to be arrived at to maximize the performance of the converter.(23.6) but the choice of primary to tertiary winding turns ratio is often governed by the voltage stress that the switch must withstand.2 Irated) NP -------------------------. the output voltage. is not able to maintain the desired quality of output voltage. Imin = 0 and Iload = 0. Kharagpur 12 www. Edc . the inductor current remains continuous.2 Irated. 23. Thus even though ‘ Edc ’ and ‘δ’ are varying. their product (δ S Edc ) will be constant NP Version 2 EE IIT. Hence filter inductor should be chosen to be sufficiently large such that under expected range of load current variation. At 10% of the load.

7) and (23.(23.min NP ⎥ -------------------------------.Imin) to 20% of rated current. [As mentioned earlier. Thus δ min = Edc . where ‘C’ is the output capacitance in farad.] Hence.www. Quiz 1).6) the maximum value of NP duty ratio may be taken as δ max = .min are maximum and minimum magnitudes of input dc voltage respectively.(23.max = .12) 20Cf SW .max and Edc .min .9) written as L = I rated f SW .(23.com and equal to VO. only low frequency variation in supply voltage has been considered. the inductor current ripple depends only on the duty ratio. For constant output voltage and constant current through load. the inductor ‘L’ magnitude should correspond to minimum value of duty ratio and may be 5VO (1 − δ min ) -------------------------------.where δ min is the minimum magnitude of duty ratio and f SW is the constant switching frequency of the converter switch.max NP and ( N P + NT ) L= ⎤ 5VO ⎡ Edc . in accordance with the above equation.11).(23. Even though the output capacitor voltage has been assumed constant in our analysis so far. Capacitance value should be chosen.min Edc .jntuworld.max ( N P + NT ) ⎥ ⎣ ⎦ The inductor magnitude given by Eqn. -------------------------------.jntuworld. Now in accordance with Eqn. p − p ) can be given as: vO . p − p = rated -------------------------------. which in turn depends on the magnitude of input dc voltage] Once inductor magnitude is chosen in accordance with Eqn. has been assumed to draw a constant magnitude of current. It may be noted here that as long as inductor current is continuous the peak-to-peak ripple in the inductor current is not affected by the dc value of load current. Kharagpur 13 www. what is the maximum duty ratio at which the converter can be operated? Corresponding to this duty ratio. [refer to Eqns. there will be a minor ripple in capacitor voltage too which however will have only negligible effect on the analysis carried out earlier. under steady state.10) δ min Edc .11) will limit the worst case peak to peak current ripple in the filter inductor (= Imax . Switching frequency and the switch control dynamics are assumed to be much faster.11) ⎢1 − I rated f SW ⎢ Edc .8). If the turns ratio of the primary and tertiary windings of the forward transformer are in the ratio of 1:2. peak to peak ripple in capacitor voltage I ( vO . This is so because the load.(23. The worst case.(23. what should be the minimum ratio of secondary to primary Version 2 EE IIT.(23. Again to maintain constant output voltage ( N P + NT ) δ max Edc . where Edc . based on the allowed ripple in the output voltage.com .(23. peak to peak ripple in the capacitor current will also be 20% of the rated current.

5 and 5 amps.5 micro Farad] (4) What function does the diode ‘D1’ of circuit in Fig.jntuworld. diode voltage stress = 750V] 3) Calculate the filter inductor and capacitor values for the forward converter described below: Maximum duty ratio = 0.jntuworld.5. [Answer: Switch voltage stress = 500V.www. primary to secondary turns = 10:1.4) have? (i) rectifies secondary voltage (ii) blocks back propagation of secondary voltage to transformer (iii) both (i) and (ii) (iv) protects diode ‘D2’ from excessive reverse voltage [Answer: (iii)] Version 2 EE IIT.com .5 amp load current. output dc (under steady state) = 10 volts ± 0. Take switching frequency = 100 kHz. [Answer: 1/3 and 9/80] 2) Find maximum voltage stress of the switch in the primary winding and diode in the tertiary winding if the converter-transformer has 10 primary turns and 15 tertiary turns and the maximum input dc voltage is 300 volts. [Answer: L = 50 micro Henry and C = 12. Kharagpur 14 www. Input dc remains constant at 200 volts.(23.1 volt.com turns if the input dc supply is 400 volts and the required output voltage is 15 volts? Neglect switch and diode conduction voltage drops. Assume just continuous conduction of inductor current at 0. The load current is expected to vary between 0.

jntuworld.www.com Module 3 DC to DC Converters Version 2 EE IIT.jntuworld. Kharagpur 1 www.com .

jntuworld.www. Kharagpur 2 www.jntuworld.com Lesson 24 C uK and Sepic Converter Version 2 EE IIT.com .

com Instructional objective On completion the student will be able to • • • • Compare the advantages and disadvantages of CuK and Sepic converters with those of three basic converters.com . Version 2 EE IIT. Draw the waveforms of the circuit variables associated with CuK and Sepic converters.www.jntuworld. Kharagpur 3 www. Calculate the capacitor voltage ripples and inductor current ripples in CuK converter.jntuworld. Draw the circuit diagrams and identify the operating modes of CuK and Sepic converters.

It does not require an explanation that a current source must be made to deliver its energy into a voltage sink and viceversa. (i) Buck converter 1 2 Vin S1 L iB C Fig. without causing any voltage or current amplification. Both can however discharge into a dissipative load. • Continuous output current results in lower output voltage ripple. The Canonical Cell forms the basis of analyzing switching circuits. the Buck-Boost as a Voltage-Current-Voltage and the CUK as a CurrentVoltage-Current converter. essentially a BOOST-BUCK converter. All other switching converter MUST fall into one of these configurations if it does not increase the switching stages further for example into a V-I-V-I converter which is difficult to realize through a single controlled switch.www. The Buck converter may consequently be seen as a Voltage to Current converter.jntuworld. Many consider the basic group to consist of the three: BUCK. This rule is analogous to the energy exchange between a source of Potential Energy (Voltage of a Capacitor) and a sink of Kinetic Energy (Current in an Inductor) and viceversa. but the energy transport mechanism forms the foundation of the building blocks of such converters. which however can be seen to be minor variations of a group of basic DCDC converters – built on a set of rules. Version 2 EE IIT. • Output voltage is always less than input voltage. The CUK. BOOST and BUCK-BOOST converters. may not be considered as basic converter along with its variations: the SEPIC and the zeta converters.jntuworld. A very large number of converters have been proposed. requires input filter. The first would cause current stresses while the latter results in voltage surges.com . Kharagpur 4 www.1 Introduction Switch Mode Power Supply topologies follow a set of rules. the Boost as a Current to Voltage converter. 24.com 24.2 Analysis of C uK converter The advantages and disadvantages of three basic non-isolated converters can be summerised as given below. A voltage source cannot discharge into a voltage sink and neither can a current source discharge into a current sink. 24. The resonant converters also have to agree to some of these basic rules.1: Circuit schematic of a buck converter Features of a buck converter are • Pulsed input current.

• Continuous input current. (iii) Buck . • Pulsed output current increases output voltage ripple • Output voltage can be either greater or smaller than input voltage. 24. It will be desirable to combine the advantages of these basic converters into one converter.com (ii) Boost converter L 2 Vin 1 S1 R C Fig.4: Circuit schematic of a boost-buck converter Version 2 EE IIT.Boost converter 1 S1 Vin L R C 2 Fig. It has the following advantages. • Output voltage is always greater than input voltage. L1 L2 2 S1 Vin 1 + C S2 1' Fig. CuK converter is actually the cascade combination of a boost and a buck converter. Kharagpur 5 www.jntuworld. 24. • Continuous output current.com 2' + C2 - R . • Output voltage can be either greater or less than input voltage.boost converter are • Pulsed input current.2: Circuit schematic of a boost converter Features of a boost converter are • Continuous input current.3: Circuit schematic of a buck boost converter Features of a buck . eliminates input filter. requires input filter.www.jntuworld. 24. • Pulsed output current increases output voltage ripple. CuK converter is one such converter.

Version 2 EE IIT. (i) 0 < t ≤ DT S1 & S2 to to (1) (1') The circuit configuration is given below L1 L2 L1 C1 Vin C1 C2 R C2 R (a) (ii) DT < t < T. Kharagpur 6 www.jntuworld.com S1 and S2 operate synchronously with same duty ratio.5: Circuit topology of a boost-buck converter during different switching intervals (a) 0 ≤ t < DT. L1 S1 to (2) & S2 to (2') L1 L2 Vin C2 R C2 R (b) Fig.com . (b) DT ≤ t < T These two topologies can also be obtained from the following circuit which is the so called CuK converter. 24.www.jntuworld. Therefore there are only two switching states.

Kharagpur 7 www. 24.1 Expression for average output voltage and inductor currents L1 iL1 Vin ic1 C1 + L2 iL2 ic2 + C2 i0 R V0 + V0 (b) DT < t ≤ T ˆ Fig.7: Equivalent Circuit of a CuK converter during different conduction modes.com . (a) Schematic diagram.www.jntuworld.6: Schematic and Circuit representation of CuK converter. (a) 0 < t ≤ DT (b) DT < t ≤ T + L1 iL1 Vin VC1 ic1 (a) 0 < t ≤ DT L2 iL2 + C2 ic2 + i0 R C1 . (b) Circuit diagram 24.2.com L1 1 Vin C1 2 L2 S R C2 (a) L1 iL1 Vin iB 1 + vc1 C1 2 L2 iL2 ic2 i0 + C2 R V0 (b) ˆ Fig. 24.L2 Version 2 EE IIT.jntuworld.

8.2.7) Vin I L1 2 2 v0 D 2 Vin = V0 I 0 = = R (1 − D )2 R (24.com Applying Volt-sec balance across L1 Vin DT + (Vin − VC 1 ) (1 − D ) T = 0 ∴ or (24. Kharagpur 8 www.7 are given in Fig.2 Current ripple and voltage ripple calculations The waveforms of different circuit variables of Fig.1) Vin (1 − D ) VC 1 = 0 VC1 = Vin 1− D (24.8) ∴ I L1 = D 2 Vin 2 (1 − D ) R (24. Version 2 EE IIT.3) (24.2) Applying Volt-sec balance across L2 (V0 + VC1 ) DT + V0 (1 − D ) T = 0 or or (24.4) V0 + DVC1 = 0 V0 = − DVC1 = − DVin 1− D (24.5) Expression for average inductor current can be obtained from charge balance of C2 I L 2 + I0 = 0 ∴ From power balance (24.jntuworld.6) I L 2 = − I0 = − V0 V = D in R 1− D R (24.jntuworld. 24.com .9) 24.www. 24.

jntuworld.8: Waveforms of circuit variables in a CuK converter.com .com iB DT T t IL1 MAX IL1 iL1 IL1 MIN t IL2 MAX IL2 iL2 IL2 MIN t1 ic1 IL2 MIN . 24.IL1 MAX vc1 VC1 MAX VC1 VC1 MIN t t2 IL2 MAX t t ic2 ˆ 1/2 I L2 p-p t1 Vc2 t2 ˆ -1/2 I L2 p-p t t Vc2 ˆ Fig.IL1 MIN .www. Version 2 EE IIT.jntuworld. Kharagpur 9 www.

14) (24.www.17) (24.20) (24.10) p− p = I L1MAX − I L1MIN = (24.com From the waveforms of Fig.8 I L1MAX = I L1 MIN + ˆ I L1 DVin T L1 Vin DT L1 (24.jntuworld.12) ∴ ⎡ ⎤ DVin I L1MAX = ⎢ D 2 + RT ⎥ 2 L1 ⎦ R ⎣ (1 − D ) ⎡ ⎤ DVin I L1MIN = ⎢ D 2 − RT ⎥ 2 L1 ⎦ R ⎣ (1 − D ) I L 2 MAX = I L 2 MIN − ˆ IL2 V0 V (1 − D )T = I L 2 MIN + in DT L2 L2 Vin DT L2 (24.com .22) Version 2 EE IIT.jntuworld.21) (24.7 p− p = I L 2 MAX − I L 2 MIN = (24. 24.11) From equation 24. Kharagpur 10 but for 0 < t ≤ DT ic1 = iL2 1 DT i dt = 1 DT i dt c1 ∫0 c1 c1 ∫0 L 2 www.18) (24.16) V I L 2 MAX + I L 2 MIN = −2 I 0 = 2 D in 1− D R ∴ ⎡ ⎤ DVin I L 2 MAX = ⎢ 1 + RT ⎥ ⎣1 − D 2 L2 ⎦ R ⎡ ⎤ DVin I L 2 MIN = ⎢ 1 − RT ⎥ ⎣1 − D 2 L2 ⎦ R For calculating voltage ripples it is noted that DT vc1 = 1 ∫ ic1 dt 0 c1 (24.19) (24.9 I L1MAX + I L1 MIN = 2 I L1 = 2 D 2 Vin (1 − D ) 2 R (24.13) (24.15) ∴ From equation 24.

www.11.16.com .com or + I L 2 MIN RT ⎤ DTI L 2 I 0 DT ⎡I ˆ = vc1 = DT ⎢ L 2 MAX + = c1 2 2 L2 ⎥ C1 ⎣ c1 ⎦ ˆ vc1 = D 2Vin T RC1(1 − D ) (24.24 and 24.jntuworld.jntuworld. 24. Kharagpur 11 www. 24.25) Equations 24.25 can be utilized to design a CuK converter of given specification Version 2 EE IIT. 24.8 c 2 t1 ∴ V DT Vin DT 2 ˆ vc = 1 × 1 × T × in = c1 2 2 2 L2 8 L2 C2 (24.23) or (24.24) t2 ˆ vc 2 = 1 ∫ ic 2 dt which is the hatched area under ic2 waveform in Fig.

TON = ( Vout − Vin ) .26) or.9(b).jntuworld. Equating the inductor voltages for the period when the switch T is ON with that when it is OFF.9 (a). 24. that appearing across the diode D is Vout – Vin. Here. the average voltage across the input inductor is zero. Fig. The basic SEPIC is a modification of the basic Boost and the CuK topologies. 24. Thus. 24.24.9(b): BOOST converter Fig.10 Modified Boost with load across Diode for Boost-Buck Operation. Now power flows in from the right.com .Vin 1− ∂ where. Vin-L-D-Vout. Vout = ( 1 ). (right) with filter. Fig. The Boost converter is realized if the positions of D and T are interchanged in Fig.jntuworld.9(a) is that of a basic Buck converter. the energy stored in the inductor during each ON period of switch T is transferred to the Capacitor during its OFF period. (left) without output filter. Consider the Boost converter in Fig 24. ∂ is the duty ratio of the switch. Kharagpur 12 www. The CUK converter as the dual of the Buck-Boost converter has current input and current output stages. the basic building block of DC-DC converters. Vin . in Fig. In the path. 24. This voltage from Eqn 1 is: Version 2 EE IIT. The current is further converted into voltage without a switching stage (amplification) at C2. the average voltages across all the elements are known.9(a): A basic converter: BUCK converter Fig. the converter charges the current sink constituted by the inductor-diode (L-D). 24.TOFF (24.com The SEPIC Converter The previous chapter discussed the single stage conversion Buck and Boost converters along with the two-stage Buck-Boost converter. The cell includes T-C-L-D. This chapter offers a few additional topologies.9(b). From the voltage source C1. At steady state. The canonical switching cell is approached if the capacitors C1 and C2 are combined to be represented by a single capacitor C.www.

Fig. Vc and writing TON = ∂ . the unofficial interpretation is more descriptive: “Secondary Polarity Inverted Cuk”. This is not acceptable for various reasons.but easily derivable from the previous topologies.com .jntuworld.TON = (VC − Vout − Vin )TOFF (24.TOFF (24.TOFF (24. the output stage must be capacitive (voltage sink) which is taken care of by C2-D.www.com V D = [(1 1 − ∂ ) − 1].Vout ). since the source is a current source. It is a I-V-I converter.jntuworld. T. The SEPIC results – not an entirely different one .27) or . If the link capacitor has a voltage Vc across itself (consider it to be reasonably constant). the two inductors are coupled with the polarities as indicated by dots in Fig. Now it is the turn of the Diode to be interchanged with the filter inductor. VC .K . Now. 1 ) TOFF For the output inductor. However.TON = V out . The inductor is thus converted to be part of the switching circuit and it not just a filter. (Vin . 24. the basic input–output relation can be derived by considering the two inductors to have average null voltage across themselves.10 (left). VC = Vout − Vin (.Vin = (∂ 1− ∂ )Vin A Boost-Buck converter is thus realized. The CUK converter is thus realized. 24.28) Eliminating. the volt-secs during the ON and OFF periods of the switch are: Vin . For such a coupled-transformer SEPIC. The turns ratio is and the coupling is very tight.29) Thus the SEPIC is also basically a BOOST-BUCK converter akin to the CUK converter. The SEPIC officially stands for “Single-Ended Primary Inductance Converter”.TON = (Vout + VC − Vin − K . Kharagpur 13 www.11(a). and Version 2 EE IIT. (The Boost stage comes first followed by the Buck stage and it is also I-V-I converter) In the practical SEPIC converter. A glaring drawback of this derived converter topology is that the polarity of the output is reversed. then for the input inductor.11(a): The basic SEPIC topology Again. This is the voltage that would appear in an unfiltered form at the load in Fig. Vout = ( ∂ 1− ∂ )Vin (24.VC ). equating the positive and negative volt-secs for the two inductors. 24. The voltage across D has high ripples.30) for the input inductor. which can be filtered much like the Buck converter with an L (and a C3).

VC into the primary. the capacitor C2 charges to the supply voltage Vin. By symmetry. The second voltage source. induces N. its inductance is effectively infinite. all variations in magnetizing current. VC.jntuworld. This effect can be desirable because.29) can be obtained from the above two by substituting both K and K’ to zero to have no coupling between the two coils. When the transistor is switched ON. Fig. setting n = k causes the secondary-winding current to become constant while the primary source supplies the magnetizing-current variations. neither the coupling between the inductors nor the effective turns ratio can be unity. This results in a circuit with the features of the uncoupled circuit and the circuit performs. where N is the turns ratio. Fig. Consequently. This can be explained by examining the operation of the circuit. Because the voltage at each end of this leakage inductance is the same.12. 24. common-mode power-line input-filter choke. thereby "bootstrapping" the leakage inductance of the input inductor. the resulting active circuit is shown in Fig 24. for n = 1/k. For the interesting case. However. Version 2 EE IIT. One simplification is to use a 1:1 transformer. then the voltage induced by Vin will increase the voltage at the Drain of the transistor to N. and add a small additional inductance in series with the primary winding. commodity. Noisy switching current does not appear at the converter input but is diverted instead to the secondary winding. 24. Kharagpur 14 www. if the turns ratio. Vin = VC = V1.www. V1. by 1/k (where k < 1 is the coupling coefficient between windings). which explains why the ideal circuit will not work. is increased slightly from unity. resulting in null emfs on either side.11(b) The practical SEPIC topology with coupled inductors The above two equations result in an identity to indicate that such a system cannot work. This effectively increases the leakage inductance so that the same secondary-winding dominance of magnetizing current is obtained with n = 1. such as a lowcost.31) Equations (24.Vin ).com (VC − K ' . (through M) due to a varying V1 is supplied from the secondary winding source. it results in constant (DC) primary current. However. typical values of k are slightly less than one.com .jntuworld. and turns ratios of nearly 1:1 may not be easy to wind.12: Active part of the circuit when transistor is switched with C2 charged toVin The circuits to the left and right of the transistor are identical and both the windings are induced with the supply voltages.TON = [Vout − K ' (Vout + VC − Vin )]. Initially when the transistor is OFF.28) and (24.TOFF (24. n.

13 show the voltage at the transistor Drain present on the fly back (Boost) and SEPIC circuits. In comparison. Version 2 EE IIT.www.13: Drain voltages of FLYBACK and SEPIC converters The waveforms in Fig. the SEPIC FET switching waveform is clamped.com The circuit is an alternative to the Boost converter and outputs an range which includes the input range also being a Boost-Buck converter.5 volt forward drop of the SEPIC’s Schottky diode relative to the one volt forward drop of the flyback's ultra-fast diode.jntuworld. output voltage noise and a power stage that can be operated at a much higher frequency than that of the fly back. This level is about 1. Fig. and shows very little overshoot. results in significant power savings for the SEPIC. A relatively high voltage (~200V) output diode is required for the fly back to handle the large negative ringing compared to the SEPIC’s 60V Schottky diode. It is superior to the other converters both in terms of the input current purity and efficiency. the fly back transformer leakage inductance also produces a significant voltage spike relative to the SEPIC at the output diode. This clamping results in less switchingloss. 24.jntuworld.5 times the supply voltage for inputs around 20 V. Kharagpur 15 www. The fly back transformer leakage inductance produces a voltage spike that adds an additional level to the "flat-top" voltage. 24. or ringing. Again. The 0.com .

jntuworld. Kharagpur 1 www.www.jntuworld.com .com Module 3 DC to DC Converters Version 2 EE IIT.

jntuworld.jntuworld.www.com Lesson 25 Design of Transformer for Switched Mode Power Supply (SMPS) Circuits Version 2 EE IIT.com . Kharagpur 2 www.

the switch in case (b) will be constrained to operate in a narrow range. The circuit in Fig. The currents and voltages of SMPS transformer are of very high frequency where as utility type transformers are subjected to low frequency supply voltages.1(b) need to withstand both input side voltage and output side current. 25. (ii) Do a preliminary design of a high frequency transformer for some popular configurations of SMPS circuits.www.com After completion of this lesson the reader will be able to: (i) Explain the underlying principles behind the design of a high frequency transformer and inductor.1(a) uses a step down transformer with proper turns ratio and has the advantages discussed above. Also. Transformers are required for galvanic isolation between input and output voltages and for voltage and current scaling. On the other hand the switch and diode and the filter inductor in Fig. NP: NS D1 Edc D2 L C Load + _ S L Edc D C L O A D S (a) (b) Fig. 25. 25.1: DC to DC buck converters: (a) Isolated type (b) Non-isolated type Transformers used in switched mode power supply circuits are significantly different from the power transformers that are used in utility ac supply system. It also helps in optimizing the device voltage and current ratings.jntuworld. (ii) (iii) Version 2 EE IIT. The dc-to-dc buck converter shown in Fig. diodes and other circuit elements on the high voltage side of the transformer are subjected to higher voltages but only lower currents. which is used to get a low voltage output from a high input dc voltage illustrates this point clearly. Kharagpur 3 www. SMPS transformers generally handle much smaller power than the utility transformer. which may cause lesser accuracy in output voltage control.1. Similarly the devices put on the low voltage side are subjected to less voltage stress but higher current stress. (iv) Estimate the size of an SMPS transformer of some given VA rating. (iii) Do a preliminary design of a high frequency inductor. 25. Following are the important differences: (i) The input and output voltages and currents of a SMPS transformer are mostly non-sinusoidal. whereas the transformers connected to utility ac supply are almost always subjected to sinusoidal voltages and currents.com . The switches.jntuworld.

25.3) . Some times the current densities through the two windings may differ depending on their physical ability to dissipate heat. A typical figure for the current density through copper conductors of naturally cooled transformers is 3X106 amps per square meter. As a result.4 Tesla) that are considerably less than that of silicon steel. Kharagpur 4 www.] The ferrites have low magnetic permeability (typical value of relative permeability is around 100) and low saturating value of flux density (typical value is around 0.e. Ferrites have very high ohmic resistance and the area enclosed under the hysteresis loop of their B-H magnetization curve is significantly lower than that of silicon steel.. is generally made of hard magnetic material like ferrites whereas the low frequency power transformers mostly use soft magnetic material like silicon steel.com SMPS transformer-core.2) The windings are placed around the core and are accommodated in the window of the transformer.jntuworld. Window utilization factor. may handle higher flux density and may be more rugged. they occupy equal window-space of the transformer. in SMPS-transformers and power transformers are identical and hence. in this lesson.jntuworld. the emf generated per turn of the winding will have a rms magnitude ‘Et’ given by: Et = 4. even at very high frequency operation. For a single-phase transformer the relation between them is given by: Aw kw δ = 2 N I ----------------------------------------------.6 and is dependent on the insulation requirements of the windings. The transformer window area (Aw) is related with the winding’s current rating and the number of turns.1) The peak flux through the core is the product of peak flux density (Bm) and the core area (Ac).where kw is the window utilization factor and δ is the current density through the crosssectional area of the transformer windings. The VA rating of a single phase transformer (= N Et I) can now be found from the above equations as: VA rating = 2.(25. the hysteresis and eddy current losses are low. φm = Bm Ac ----------------------------------------------. because of high frequency operation.www.(25.1 Recapitulation of Governing Equations for Utility Transformer In case of sinusoidal flux of peak magnitude ‘ φm ’ and frequency ‘f’ linking the transformer windings.44 f φm -----------------------------------------------(25. many concepts of conventional transformer design have been borrowed. [Low hysteresis loss is due to less B-H loop area and low eddy current loss is due to very high resistivity of the core material. i.22 f Bm δ kw Ac Aw ----------------------------(25. The efforts are on to search for alternatives to ferrites that may have higher permeability. Ferrites are also brittle and fragile.4) Version 2 EE IIT.com . The fundamental principles concerning emf generation etc. roughly varies between 0. If the current density through primary and secondary windings is taken identical.35 to 0.

equals the desired load voltage and can be assumed fixed to the output voltage ‘Vo’.com (ii) .2 with D=0. The worst-case current through the windings will correspond to maximum duty ratio (D=0. 25. under steady state and after accounting for voltage drops in the rectifier diode and filter inductor. The mean of the rectified secondary side voltage. output rectifier and filter circuit under maximum load condition. The actual number of turns in the windings will be found as shown below in step (v). The transformer turns ratio can thus be estimated to NP/ NS = Vmin /(Vo + VR).5 to regulate the output voltage. Now by simple integration of the square wave voltage waveform.This can be found from the knowledge of operating range over which the input dc voltage may vary. Kharagpur 5 www.2 shows the typical winding voltage and core-flux waveform produced by one of the popular SMPS topologies that utilizes a H-bridge converter to get high frequency ac voltage from the dc input. However under dynamic condition.0 f Bm Ac NP ---------------------------(25. The duty ratio ‘D’ of the switches is controlled within 0<D<0.www.5) and maximum magnitude of input voltage. the mean (dc) output voltage on the secondary side may be significantly higher than its steady state magnitude. For calculation of peak flux in the core.1 Transformer with Square-Wave Voltage and Bipolar Flux Fig. the worst-case condition will correspond to maximum duty ratio (D=0. the magnitude of square-shaped secondary side voltage should equal (Vo + VR). Moreover SMPS circuits of different topologies generate different kinds of winding voltages (and hence the flux-linked waveforms) and need to be considered separately. The transformer windings carry bi-direction current and the flux linking the windings is also bipolar.5. In this section some representative voltage and flux waveforms have been taken up and through them the transformer design procedure has been illustrated.jntuworld. With minimum input voltage ‘Vmin’ and duty ratio ‘D’ = 0. 25. 25. where VR is the estimated voltage drop in the transformer winding. Determination of peak magnitude of flux in the transformer core: As per above discussion. which may arise due to sudden change in load or supply voltage. The primary side of the SMPS transformer is connected to the H-bridge output and the secondary side voltage is rectified and filtered to get regulated dc output voltage of desired magnitude.5) Version 2 EE IIT. The frequency of voltage waveform ‘f’(=1/T) is same as the frequency at which the converter switches are turned on and is fixed beforehand. Vmax = 4. the peak flux ‘ φm ’ is related to the input voltage as. The input dc bus voltage is unregulated and often varies over a large range. Let the input voltage vary from Vmin to Vmax.com For the given operating frequency (f) the product ‘Ac Aw’. the maximum flux in the core will correspond to a square wave voltage of magnitude Vmax across the primary winding (refer to Fig.jntuworld. 25.5) and peak magnitude of output (load) current.2. Now the transformer may be designed as per the design steps given below: (i) Determination of primary to secondary turns ratio (NP/ NS):. known as area product is roughly proportional to the VA rating of the transformer as other parameters have nearly fixed magnitudes.0 f φm NP = 4.5).2 Derivation of Design Equations for SMPS Transformer The nature of voltage and flux waveforms in SMPS transformers is different from that of utility transformer.

jntuworld. Vo Iom is the peak output power from the SMPS. saving one diode drop can result in significant increase in the efficiency.25.H. where δ is the current density (as δ described in relation to Eqn.1). N Vmax S Iom 1 + 2 = 4fBm δk w A c A w --------------------------(25. The primary side carries the reflected secondary current and the δ NS Iom required copper area for primary would equal . the diodes used on the secondary side are Schottky diodes having low on-state voltage drop. (v) Selection of transformer core and determination of number of turns in the windings: Version 2 EE IIT. For SMPS with low output voltage.www. For this same reason. a factor allowing for input voltage variation and K 2 = 0 Vo Vmin a factor coming due to voltage drop in rectifier diode. with low magnitude of output voltage. Thus the I rms current rating of each half equals om and the net copper cross-sectional area 2 2NS Iom required for the secondary winding is .25.27. Expression for VA rating of the transformer: Combining Eqns. The factor 1 + 2 on the L.3). The total window area δ requirement for the transformer can now be given as: N I A w k w = S om 1 + 2 -----------. Each half of the center-tapped secondary winding requires NS turns as determined in (i) above and they carry the load (dc) current only in alternate half cycles.7 may be rewritten as: Vo Iom K1K 2 1 + 2 = 4fBm δk w A c A w --------------------------(25. If the secondary was not center-tapped. have a center-tapped secondary winding followed by a mid-point rectifier circuit realized using two diodes (instead of bridge rectifier having four diodes).7) NP ( ) (iv) ( ) Using relations derived in (i) above.0 if the secondary winding is not center-tapped. Most SMPS circuits.6) one gets.com .8 ( ) where K1 = ( ) will become 2. .(25. This results in only one diode voltage drop during rectification.jntuworld.25. Kharagpur 6 www. filter inductor etc.com (iii) Determination of winding current rating and requirement of window area: Let ‘Iom’ be the peak expected load current. The secondary winding of the transformer should be rated to supply this current. of Eqn. δ where Aw is the window area and kw is the window utilization factor (as discussed in Sec.6).S. unlike two diode drops for the bridge rectifier circuit. the rectifier used would be bridge type and the copper area for the secondary would have N I been just S om .8) V + VR Vmax . Eqn. (25.5) and (25.

5) or (25.5fBm δk w A c A w ------------------------------------------(25.jntuworld.10.4 of Lesson-23). Kharagpur 7 www.25.2.5fBm δk w A c A w .com Knowing the area product ‘Ac Aw’. the number of turns in the windings can be decided using Eqns.25. which may be rewritten as NP Vo Iom K1K 2 D max = 0. The maximum input voltage (Vmax).com . 25.6).11) Eqn.5 Iom ( D max ) = 0. Accordingly. Knowing the window area. Fig. The symbols used also denote the same.11 is similar to Eqn.9 and 25. The maximum duty ratio (Dmax) of the switch is also limited by the turns ratio between the primary and tertiary winding to allow resetting of the transformer flux (as given in Sec. when the forward converter switch is turned on the primary winding is subjected to input dc voltage.2 Transformer with Unipolar Flux Many switched mode power supply circuits use only one controlled switch (like the forward converter discussed in Lesson-23).23.5 for a typical value of Dmax = 0. the appropriate transformer core is to be selected from the core-manufacturer’s catalog. with the addition of tertiary winding the insulation requirement Version 2 EE IIT. The maximum rms current through the secondary winding can be equated to Iom D max and the window area (Aw) requirement is given by A w k w = From Vmax 2NS Iom D max δ -----------------(25.8. switching frequency ‘f’(=1/T) and the maximum duty ratio (Dmax) are related with the peak magnitude of core-flux is calculated as Vmax Dmax = f φm NP = f Bm Ac NP -----------------------------------------------(25. which is a quite small and even a thin gauge wire will serve the purpose.25. Like (25. the VA rating of the transformer NS 1. Because of unipolar nature of flux the utilization of core (in terms of emf generation) is poorer here. NP/ NS = Vmin Dmax /(Vo + VR). the details of other dimensions of the transformer core are found from the catalog. The primary to secondary turns ratio (NP/ NS ) for the forward converter can be estimated as done previously for the H-bridge converter. where Vo is the required output voltage and VR denotes the voltage drop in output rectifier and filter circuit. However. As soon as the primary winding is turned-off.25. Once the area product matches.www.3 shows the typical winding voltage along with the corresponding core-flux waveform for a forward converter. as given by Eqn.25.9) Eqn. 25. The winding current and core-flux for most of these transformers are unidirectional. Knowing window area (Aw) and core area (Ac). As shown in Lesson-23.25.9 may be compared with Eqn.5 (which corresponds to the case when primary and tertiary windings have identical number of turns).jntuworld. The extra tertiary winding of a forward converter transformer carries only magnetization current.10) is given as: Eqn. the transformer core selection and other designs are done as described above in connection with the H-bridge topology. the tertiary winding starts conducting and the voltage across primary goes negative with a magnitude that equals the product of input voltage and the turns ratio between the primary and tertiary windings.8 above.

3 Design of Inductor-Transformer The fly-back type SMPS circuits use a different kind of transformer.www. the inductance needs to have a finite magnitude so that current can build through it during each high frequency cycle and the inductor may store the desired magnitude of energy. Also.2. which as indicated in Lesson-22.jntuworld.com of the transformer increases significantly and hence the window utilization factor (kw) becomes low. The windings of an inductor-transformer facilitate energy storage in the magnetic field whereas the windings of an ideal transformer (having infinitely large permeability ‘μ’ of the core) cannot be used for storing energy as energy Version 2 EE IIT. 25. Such a transformer is more like two coupled inductors.jntuworld. unlike the two coupled-windings of a normal transformer. Kharagpur 8 www. These two coupled-inductors don’t conduct simultaneously.φm time Fig.2: Winding voltage and core-flux waveforms for a H-bridge type SMPS supply Voltage +VF DT time T 0 -VR Flux +φmax time 0 Fig. Voltage +V DT T/2 0 DT 3T/2 T -V time Flux 0 +φm . 25.com . may be more appropriately called as inductor-transformer.3: Winding voltage and core-flux waveforms for a forward type SMPS supply 25.

rms ------------------------------(25. reluctance (R) and the number of turns (N) of the inductor: N2 L= . A preferred way of creating air-gap may be to grind some length from only the central limb of the core.15 is indicative of the energy holding capacity of the inductor (some what like VA rating of the transformer discussed above). the following relation holds good between inductance (L).jntuworld. one gets LI p I p.25.rms = Bm δk w A c A w ------------------------------------------------------------.com .jntuworld.5 where Ac is the area of the core’s limb on which the windings have been placed and μ0 is the permeability of air-gap. For finite magnitude of flux density ‘B’.15. an appropriate length of air-gap is introduced in the flux path.www.25.14) determines the window area required as A w k w = δ Combining Eqns.(25. For a practical inductor the reluctance of its flux-path should not be zero.14. Should there be a couple winding (an inductor-transformer) the area product expression needs to be modified to include the window space requirement of the secondary winding as well. the magnitude of ‘μ’ should be μ small to have higher energy per unit volume.13 and 25. However a practical inductor still requires a good core with high permeability to R increase (i) coupling between the windings. paper) is inserted between the faces of the core and the two ‘E’s of the core are clamped together.25.com B2 . ‘μ’ and magnetic reluctance have inverse relation. If ‘lg’ is the length of air-gap in the core. However to keep the reluctance of the flux-path at the desired value.4 shows a double ‘E’ core with windings put around the central limb. Kharagpur 9 www. Version 2 EE IIT.(25. a non-magnetic material (like. In the above expression for inductance.12) lg density equals 0. one calculates its rms magnitude (Ip.rms) and NI p. the inductance (L) can be expressed as: N 2 A c μ0 L= -----------------------------------------------------------------------. The non-magnetic material acts like air-gap in the core.13) Knowing the current shape through the inductor. After the windings are placed in position. Fig. The peak flux density in the core (Bm) can be related with the peak magnitude of current as LI p = NA c Bm -----------------------------------------------------------------------.25. LHS of Eqn.(25. the fringing effect of the flux and the reluctance of the flux path through magnetic core have been neglected. as ‘μ’ decreases the reluctance increases. gives the area product from which rest of the design can be proceeded as in the case of transformer design shown above. The core material should not saturate with the peak expected current (Ip) in the inductor. working in the linear region of the core’s magnetization. For an inductor.15) Eqn. (ii) to guide the flux path and hence decrease the stray magnetic field lines and (iii) to keep the inductor size small.

3 Transformer Winding Often sandwiched type windings (as shown in Fig. There should be proper insulation between the shield and Quiz Problems (1) For a high frequency transformer the relation between the transformer size and frequency of voltage waveform can be given as: (a) (b) (c) (d) Size increases with frequency Size decreases with frequency Core size reduces but copper weight increases with increase in frequency Size is independent of frequency (2) The assembly of fly-back and forward type transformer cores may differ in the following sense: (a) (b) (c) (d) Air-gap is inserted in fly-back type but it is undesirable for forward type. where the secondary winding is sandwiched between two halves of the primary) are used to reduce leakage inductance of the windings. Sandwiching increases the insulation requirement between the windings.25.4: A typical SMPS transformer with a double ‘E’ type ferrite core and interleaved primary and secondary winding 25. This helps in better utilization of winding’s copper as high frequency current is effectively limited to the surface of the conductor. Kharagpur 10 www.com . For very high frequency applications.www. Many applications require grounded shields around the windings to reduce electro-magnetic interference (EMI) caused by the SMPS transformers.4. As discussed in this lesson the SMPS transformers often carry very high frequency ripples. it may be preferred to use ribbon-conductor or copper foil in place of solid circular conductors. 25.com H A L F P R I F U L L S E C H A L F P R I H A L F P R I F U L L S E C H A L F P R I Fig.jntuworld. These shields are essentially 3/4th turn of a metallic foil put around the windings.jntuworld. Air-gap in the flux path is undesirable for both types Only forward type must have a suitably length of air-gap Little air-gap is deliberately put for both transformers Version 2 EE IIT.

jntuworld. 2-a.www. 3-a.com . 4-a) Version 2 EE IIT.com (3) Transformers of forward type and H-bridge type SMPS circuits of identical VA rating and frequency differ in the following sense: (a) (b) (c) (d) The forward type transformer will be bigger The H-bridge circuit will require bigger transformer They will be of identical size Only the window area of H-bridge transformer will be bigger (4) The size of SMPS transformers operating over large input voltage range will compare with similar rated transformer operating over a narrower input voltage range in the following manner: (a) Larger input voltage range will require larger transformer (b) Larger voltage range requires smaller transformer (c) Size remains independent of voltage range (Answers: 1-b.jntuworld. Kharagpur 11 www.

com Module 4 AC to AC Voltage Converters Version 2 EE IIT.jntuworld.com .jntuworld.www. Kharagpur 1 www.

jntuworld.com Lesson 26 AC to AC Voltage Converters Version 2 EE IIT. Kharagpur 2 www.com .www.jntuworld.

jntuworld. Version 2 EE IIT. The regulators in Fig 26. Kharagpur 3 www.1 Introduction AC to AC voltage converters operates on the AC mains essentially to regulate the output voltage. (d) The SCR in (b) replaced by a transistor. Being bi-directionally conducting devices. (a) Back-to-back SCR. which has also got to be bidirectional. dv dt re −applied their ratings being poor. The 'Alternistor' was developed with improved features but was not popular. They are called Phase Angle Controlled (PAC) AC-AC converters or AC-AC choppers. It also requires a freewheeling path across the inductive load. The TRIAC is common only at the low power ranges.com This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) AC-AC power conversion topologies at fixed frequency Power converter options available for the conversion Ability to formulate equations describing the current waveform for the PAC Ability sketch the current waveform by observation of the circuit Ability to assess the performance of the converter of the topologies 26. (b) and (c) perform quite similarly. Several topologies have emerged along with voltage regulation methods.1 Some single phase AC-AC voltage regulator topologies. most of which are linked to the development of the semiconductor devices. (c) A bi-directionally conducting TRIAC. Fig 26. However. The (a) and (b) options are improvements on (c) mostly regarding current handling and turn-off-able current rating. they tend to turn-on in the opposite direction just subsequent to their turn-off with an inductive load. (b) One SCR in (a) replaced by a four-diode full wave diode bridge.1 (a).www. Consequently. only controlled freewheeling devices can be used. A transistorised AC-AC regulator is a PWM regulator similar to the DC-DC converters.com . they act on both polarities of the applied voltage. Portions of the supply sinusoid appear at the load while the semiconductor switches block the remaining portions. The TRIAC based converter may be considered as the basic topology.jntuworld.

26. Fig. In the diode-SCR topology.www. In the two-SCR topology. There is no scope for conduction overlap of the devices. one SCR is positively biased in each half of the supply voltage. two diodes are forward biased in each half.com 26.com .jntuworld.2 illustrates the operation of the PAC converter with a resistive load. Kharagpur 4 www.2 Operation with resistive loads Fig. The bi-directional TRIAC is also forward biased for both polarities of the supply voltage. A single pulse is sufficient to trigger the controlled devices with a resistive load. The SCR always receives a DC voltage and does not distinguish the polarity of the supply.2 Operation of a Phase Angle Controlled AC-AC converter with a resistive load The rms voltage Vrms decides the power supplied to the load. The current follows the voltage wave shape in each half and extinguishes itself at the zero crossings of the supply voltage. It is thus always forward biased. The device(s) is triggered at a phase-angle 'α' in each cycle.jntuworld. It can be computed as Vrms = ∫ 2V πα 1 π 2 sin 2 ωt dωt = V 1− α sin 2α + π 2π Version 2 EE IIT. 26.

which is useful. This is one of the main reasons why such controllers are today not acceptable. Kharagpur www. As is evident from the current waveforms.3 The rms output voltage and the most important harmonics versus triggering angle α. This ensures elimination of DC and even components in the output voltage.triggering is effected when the capacitor voltage reaches 32 V. The ideal waveform as shown in Fig 26. However it is to be achieved by the trigger circuits. 26.4 DIAC based trigger circuit for a TRIAC to ensure symmetrical triggering in the two halves of the supply. if can be represented as if = 2V ⎡ α sin 2α ⎢( π − 2 + 2 Rπ ⎣ ) sin ωt − ( 1 cos 2α − 2 2 ) cos ωt ⎤ ⎥ ⎦ 26. However.2 is half wave symmetric. the PAC introduces significant harmonics both into the load and the supply. Fig.jntuworld.com Fig.com 5 . The PAC operates with a resistive load for all values of α ranging from 0o The fundamental current.www. For the SCR based controllers.4 ensures this for the TRIAC based circuit. The corrupted supply current nevertheless is undesirable.a two terminal device. 26. 26.1 In machine drives it is only the fundamental component. identical comparators for the two halves of the AC supply. Version 2 EE IIT.jntuworld. in resistance heating type of application all harmonics are of no consequence. which generates pulses for the two SCRs ensures DC and even harmonic free operation. The controller in Fig. While the TRIAC has a differing characteristic for the two polarities of biasing with the 32V DIAC .

26.com 26. P drawn by the resistive load is distortion factor = 1 2π 1 P= ∫0 viL dωt = π 2π α sin 2α ⎤ 2V 2 ⎡ = ⎢π − 2 + 2 ⎥ Rπ ⎣ ⎦ ∫α π 2V 2 sin 2 ωt R dwt 26.jntuworld. Fig. Fig.1.jntuworld. Kharagpur www. Cosφ1 is also called the 'Displacement Factor'.3 Power Factor The power factor of a nonlinear deserves a special discussion. The rms load voltage can also be similarly obtained by integrating between α and π and the result can be combined with Eq..5 is identical to the first part of the expression within brackets in Eq. However this does not account for the total reactive power drawn by the system.2 shows the supply voltage and the non-sinusoidal load current.3 VI L1 cos φ1 VI L I L1 IL The Average Power. 'Fundamental Power Factor' angle. The fundamental load/supply current lags the supply voltage by the φ1.5 Variation of various performance parameters with triggering angle Version 2 EE IIT.4 26. Now power factor = = average power P = apparent voltamperes VI L 26. 26. 26.5 to give power factor = per − unit rms load − current B = per − unit 1 load power = B p. which is called the Fourier coefficient 'B1'.u.5 The portion within square brackets in Eq.2 26. This power factor is inspite of the actual load being resistive! The reactive power is drawn also y the trigger-angle dependent harmonics. 26. 26.www.com 6 .

The load current waveform is further explained in Fig.jntuworld. It quenches not at the zero crossing of the applied voltage as with the resistive load but after that instant.transient current component and iload . The current is composed of two components. as they do not have the supply voltage forward biasing them when the trigger pulse arrives.6. itr . The supply voltage thus continues to be impressed on the load till the load current returns to zero. Vs supply voltage. iss and the second. The current builds up from zero in each cycle.com 7 . A single pulse trigger will work till the trigger angle α > φ. A train of pulses is required here.load current (= iss + itr). The devices would fail to conduct when they are intended to.7 Load current for a single phase AC-AC converter with a R_L load. The output voltage is controllable only between triggering angles φ and 180o. where φ is the power factor angle of the inductive load.jntuworld.www. Kharagpur www. 26.6 Operation of a single phase PAC with an inductive load Fig 26.1 (c) or the antiparallel SCR (b) has no effect on the devices if it (or the anti-parallel device) is already in conduction in the reverse direction.4 Operation with inductive loads With inductive loads the operation of the PAC is illustrated in Fig 26. itr is the transient component. iss -steady state current component . The first is the steady state component of the load current.com 26. A single-pulse trigger for the TRIAC 26.5. 26. Version 2 EE IIT. Fig.

Kharagpur www. The 'transient component' of load current itr.jntuworld. However.1 and the corresponding load voltage and current waveforms for an inductive load. 26. The output voltage is shown to be about 50% for a 0. 26.1 has to be augmented with two additional controlled devices clamping the load as indicated in Fig. Fig. The load current I that case is perfectly sinusoidal. if the switch could have permanently kept the load connected to the supply the current would have become a sinusoidal one phase shifted from the voltage by the phase angle of the load. 26.5 AC-AC Chopper Fig. This condition sets the initial value of the transient component to that of the steady state at the instant that the SCR/TRIAC is triggered. A large capacitor across the supply terminals is also to be inserted.7. Version 2 EE IIT. iload = 0 and supply voltage vs = √2Vsinωt the solution is of the form The instant when the load current extinguishes is called the extinction angle β. 26.5 Duty Ratio chopping.com 8 . 26. again in each half cycle.www. When a device is in conduction. Mostly switching frequency harmonics are present in both the waveforms. The AC-AC converter shown in Fig 26. This current restricted to the half periods of conduction is called the 'steady-state component' of load current iss. These devices which are mostly transistors of the same variety as used for the chopper are necessary to clamp the voltages generated by the switching-off of the current carrying inductors in the load while the input capacitor takes care of the line inductances. It can be inferred that there would be no transients in the load current if the devices are triggered at the power factor angle of the load.jntuworld.8 A complete Transitorised AC-AC chopper topology of the version shown in Fig. The harmonics in the line current and load voltage waveforms are significantly different from those with the PACs. the load current is governed by the equation L di i load = 2V Z dt + Ri =v s − R α −t L ω [ sin (ω t − φ ) + sin (α − φ )e ( ) ] Since at t = 0.com With an inductance in the load the distinguishing feature of the load current is that it must always start from zero. must add up to zero with this iss to start from zero. φ.6 illustrates these relations.

com 26.7 Practice Questions and Problems with Answers Q1 A single-phase transformer. Sequence control can be two or multiple phase depending upon the application.8. the PAC is triggered by a single pulse at α = 60ο . Kharagpur www.com 9 . Version 2 EE IIT. requiring a wide pulse or a train of pulses.www. This device continues conduction into the next half of the supply voltage till the load current falls to zero. The inner TR2 starts conduction subsequently.6 PAC as a static switch Both single phase and three phase PACs are often used as static switches for applications like switching on of highly inductive loads without transients or for regulating output AC voltages by switching in tapings of a transformer. Such sequence control PACs while controlling the output voltage also permit improvement of the power factor as seen by the source. 26. Fig.jntuworld.jntuworld. TR1 can be however triggered by a single pulse. Sketch the load current waveform. At what trigger angle will the operation be free from transients? A1 For the transformer load φL ≈ 90ο Therefore for transient free operation α = 90ο Q2 For the load described in Q1. to realize the required load voltage. assumed to have a negligible resistance compared to its inductance is switched on via a PAC. Obviously this voltage is greater than that available at the low voltage terminal of the transformer. 26.9 Load voltage and current control with a two-stage sequence control 26. Typical load voltage and current waveforms are shown in Fig. The outer TRIACs connected to thwe higher voltage leads of the input transformer are triffered at the desired angle α.

Version 2 EE IIT. Fig. iL = iss + itr = 0. It fails to conduct.com . The load current and voltage waveforms are illustrated in Fig 26.jntuworld. A2. 26. A2 The load current waveform and its steady-state and transient components when a highly inductive load is switched using single narrow trigger pulses. Thus the first SCR conducts till that angle. the load current should have been continuous. The load thus sees only a unipolar current. say ≈ 360ο. Note that both the load voltage and current waveforms contain DC components. For this load which can be considered to be highly inductive β ≈ 360ο.jntuworld. Kharagpur 10 www. However.www. The anti-parallel SCR is triggered at α = 60ο corresponding to a β ≈ 180 + 60 = 240ο when it is still reverse biased.com A2 Since α < φL. the current in the SCR first triggered extinguishes at a β the total load current.

www.com Module 4 AC to AC Voltage Converters Version 2 EE IIT. Kharagpur 1 www.jntuworld.jntuworld.com .

jntuworld.jntuworld. Kharagpur 2 www.www.com Lesson 27 Three-phase AC Regulators Version 2 EE IIT.com .

Note that the output voltage is similar to phase-controlled waveform for a converter. In the basic circuit. is used for each phase in most of the circuits as described. Kharagpur 3 www.1. starting from 1 in ascending order. The operation of the above circuits with different types of loads − resistive (R) and inductive (R-L). both with balanced resistive (R) load Three-phase. Three-wire AC Regulator with Balanced Resistive Load The circuit of a three-phase. various circuits of the singlephase ac regulators. along with the waveforms. The three-phase loads (balanced) are connected in star or delta. one Triac. are used. are described. AC to AC voltage converter. including the above two. along with the waveforms. firstly. the important points of comparison of the performance with different types of circuits. thus needing a total of six thyristors. and then. which is same as that used in a three-phase full-wave bridge converter or inverter. Lastly. In this lesson − the second one in the first half.com Instructional Objectives Study of the following: • • • The circuits used for the three-phase ac regulators (ac to ac voltage converters) The operation of the above circuits with three-phase balanced resistive (R) load. or two thyristors. is then discussed. The current flow is bidirectional. 27. It may be noted that the resistance connected in all three phases are equal. the output voltage waveform is analysed. along with the waveforms The important points of comparison of the performance with different types of circuits Introduction In the last lesson − first one in the first half of this module. The thyristors are fired in sequence (Fig. Please note the numbering scheme. described in module 2 or 5. with T = 1 / f =20 ms. 27. The operation of the above circuits with three-phase balanced resistive (R) load. the circuits of the three-phase ac regulators. The two basic circuits are three-phase three-wire type with load connected in star and three-phase deltaconnected one.www. connected back to back. Lastly. The natural commutation point is the starting of a cycle with period.2). with the difference that it is an ac waveform in this case. or a triac.jntuworld. with the current in one direction in the positive half. The line frequency is 50 Hz. is then discussed. Two thyristors connected back to back. also termed as ac to ac voltage converters. in other (opposite) Version 2 EE IIT.and delta-connected loads Three-phase AC Regulators There are many types of circuits used for the three-phase ac regulators (ac to ac voltage converters). Two thyristors connected back to back are used per phase. with the angle between the triggering of thyristors 1 & 2 being 60° (one-sixth of the time period ( T ) of a complete cycle). if six thyristors are replaced by diodes.com . balanced three-phase star. ( 60° = T / 6 ) of output voltage waveform.jntuworld. also termed as ac to ac voltage converters. The thyristors are fired or triggered after a delay of α from the natural commutation point. unlike single-phase ones. three-wire ac regulator (termed as ac to ac voltage converter) with balanced resistive (star-connected) load is shown in Fig. are presented. are described. Keywords: Three-phase ac regulator circuits. Two circuits are first taken up.

is described.www. a triggering signal must be applied at its gate.jntuworld. So.com direction in the negative half. If E s is the rms value of the input voltage per phase. E AN as the reference. e AN = 2 E s sin ω t .jntuworld. 27. and also. the instantaneous input line voltages are. if its current falls to zero. e BC = 6 E s sin (ω t − 90°) and eCA = 6 E s sin (ω t + 150°) Version 2 EE IIT. e AB = 6 E s sin (ω t + 30°) . To turn the thyristor on. Kharagpur 4 www. two thyristors connected back to back are needed in each phase. A + EAN ECN IL + EL + B EBN T6 T3 ib b + T4 T1 ia + Ean R Ebn T2 T5 ic Ecn + R n R c a + C Fig. the anode voltage must be higher that the cathode voltage. The turning off of a thyristor occurs. e BN = 2 E s sin (ω t − 120°) and eCN = 2 E s sin (ω t + 120°) Then. three-wire ac regulator The procedure for obtaining the expression of the rms value of the output voltage per phase for balanced star-connected resistive load. which depends on range of firing angle.com . as shown later. the instantaneous input voltages per phase are.1 Three-phase. and assuming the voltage.

5 EAC 0.5 EAB (a) For α = 60° ωt 0. the conduction angles of thyristors and the output voltage of one phase. a thyristor turns off. For 0° ≤ α ≤ 60° (π / 6) . Kharagpur 5 www. The conditions alternate between two and three conducting thyristors.jntuworld. 27.jntuworld. As stated earlier.www.5 EAB (b) For α = 120° Fig. 5 & 6) conduct.2 Waveforms for three-phase three-wire ac regulator 0. when the current through it goes to zero.5 EAC The waveforms of the input voltages. 27. Version 2 EE IIT.com E 0 EAB π/6 EBC π ECA EAB EBC E ωt 0 EAB EBC π ECA EAB 2π ωt E 0 EAN EBN π ECN 2π EAN 3π ωt E 0 EAN π EBN ECN 2π ωt I g1 0 I g3 I g1 ωt ωt ωt 0 I g5 0 I g3 0 I g5 I g2 ωt ωt ωt ωt ωt 5 5 6 611 2 23 34 45 6 6 1 122 3 34 45 56 0 I g2 0 0 0 I g4 ωt I g4 0 I g6 ωt 5 6 6 1 1 2 2 3 3 4 4 5 5 6 6 1 0 I g6 0 4 5 ωt 0 Ean 0 ωt E EAB Ean 0 α EBC ECA EAB EBC ωt α 10. two thyristors (5 & 6) conduct.com . three thyristors (1. immediately before triggering of thyristor 1. Once thyristor 1 is triggered.2. for firing delay angles ( α ) of (a) 60° and (b) 120° are shown in Fig.5 EAB 0.

thus needing a total of six thyristors. Since the phase current in a balanced three-phase system is only ( 1 / 3 ) of the line current. Please note that θ = ω t .www. The range of delay angle is 0° ≤ α ≤ 150° . the numbering scheme may be noted.Although two thyristors conduct at any time for 90° ≤ α ≤ 150° . delta-connected ac regulator (termed as ac to ac voltage converter) with balanced resistive load is shown in Fig. there are periods.3. the current rating of the thyristors would be lower than that if the thyristors are placed in the line. Two thyristors connected back to back are used per phase. there is no period for which two thyristors are on. For α ≥ 150° . and the output voltage becomes zero at α = 150° (5 π / 6) . It may be noted that the resistance connected in all three phases are equal.com At any time only two thyristors conduct for 60° ≤ α ≤ 90° .jntuworld. 27.jntuworld. when no thyristors are on.com . The expressions of the rms value of the output voltage per phase for balanced star-connected resistive load are as follows. Kharagpur 6 www. As stated earlier. It may be observed that one phase of the balanced circuit is similar to that used for singlephase ac regulator described in the previous lesson (26) of the module. Version 2 EE IIT. For 0° ≤ α ≤ 60° : ⎡ 1 E0 = ⎢ ⎢ 2π ⎣ 2π ∫ (e 0 AN ⎤ ) 2 dθ ⎥ ⎥ ⎦ 2 1 2 ⎧ 2 ⎪ = 6 Es ⎨ ⎪ 2π ⎩ ⎡1 = 6 Es ⎢ ⎣π For 60° ≤ α ⎡ ⎢ ⎢ ⎣ π /3 ∫ α sin θ dθ + 3 π / 2 +α ∫ π 1 2 /2 sin θ sin θ dθ + ∫ dθ + 4 3 π / 3+α 2 2 2π / 3 π / 2 +α π /2 ∫ ⎤⎫ 2 sin θ sin θ ⎪ dθ + ∫ dθ ⎥ ⎬ 4 3 ⎥⎪ 2π / 3+α ⎦⎭ 2 π 1 2 ⎛ π α sin 2α ⎞⎤ ⎜ − + ⎟ 8 ⎠⎥ ⎝6 4 ⎦ ≤ 90° : 5π / 6 −π / 3 +α 2 ⎧ 2 ⎪ E0 = 6 Es ⎨ ⎪ 2π ⎩ ⎡ sin θ ⎢ ∫ / 3+α 4 dθ + ⎢ π / 2 −π ⎣ 5π / 6 −π / 3 +α π / 2 −π / 3 +α 1 ∫ ⎤⎫2 sin θ ⎪ dθ ⎥ ⎬ 4 ⎥⎪ ⎦⎭ 2 1 ⎡1 = 6 Es ⎢ ⎢π ⎣ For 90° ≤ α ⎡ ⎛ π 3 sin 2α 3 cos 2α ⎞⎤ 2 ⎜ − ⎟ ⎥ = 6 Es ⎢ 1 + ⎜ 12 ⎟ 16 16 ⎢π ⎝ ⎠⎥ ⎣ ⎦ ≤ 150° : π 2 ⎛π 3 sin (2α + 30° ⎞⎤ 2 ⎜ + ⎟⎥ ⎜ 12 ⎟ 8 ⎝ ⎠⎥ ⎦ 1 2 1 ⎧ 2 ⎪ E0 = 6 Es ⎨ ⎪ 2π ⎩ ⎡1 = 6 Es ⎢ ⎢π ⎣ ⎡ ⎤⎫ sin θ sin θ ⎪ dθ + ⎢ ∫ ∫ / 3+α 4 dθ ⎥ ⎬ ⎢π / 2 −π / 3+α 4 ⎥⎪ π / 2 −π ⎣ ⎦⎭ π 2 1 ⎛ 5π α sin 2α 3 cos 2α ⎞⎤ 2 ⎡ ⎤2 ⎜ ⎟⎥ = 6 Es ⎢ 1 ⎛ 5π − α + sin (2α + 60°) ⎞⎥ − + + ⎜ ⎟ ⎜ 24 4 ⎟ 16 16 8 ⎠⎦ ⎣ π ⎝ 24 4 ⎝ ⎠⎥ ⎦ 1 Three-phase Delta-connected AC Regulator with Balanced Resistive Load The circuit of a three-phase.

e BC = 2 E s sin (ω t − 120°) and eCA = 2 E s sin (ω t + 120°) It may be noted that E s is the rms value of the line voltage in this case.com A + IL + ia iab R a T2 EAB ECA EL T4 B + EBC + ib b ic R ibc T6 T1 T3 - T5 R ica c C Fig.www.jntuworld. for α = 120° are shown in Fig. 27. the instantaneous input line voltages are. e AB = 2 E s sin ω t .com . phase and line currents. Kharagpur 7 www.jntuworld. The waveforms of the input line voltages. and the thyristor gating signals.4. 27. Version 2 EE IIT.3 Delta connected three-phase ac regulator Assuming the line voltage E AB as the reference.

27.com .www.jntuworld. Kharagpur 8 www.jntuworld.4 Waveforms for three-phase delta-connected ac regulator Version 2 EE IIT.com E Em 0 I g1 EAB EBC ECA EAB EBC π 2π 3π ωt 0 I g2 ωt ωt ωt ωt ωt ωt ωt ωt ωt 0 I g3 I g4 0 0 I g5 0 I g6 0 iab 0 ibc 0 ica 0 ia 0 ib 0 ic 0 π 2π For α = 120° 3π ωt ωt ωt Fig.

RL Fig. are shown in Fig. 2 1 2 3 2 5 2 7 2 9 2 11 2 2 I a = 3 I 12 + I 52 + I 72 + I 11 + + I n 2 As a result.jntuworld. not resistive as shown. 27. The rms value of line and phase currents in this case can be determined by numerical solution or Fourier analysis.1 & 27. 27. The line currents. n = 3 m . and would not appear in the line.5(a) 3-wire delta load Version 2 EE IIT.3. those of order. being in phase in all three phases of the load.5a-c.3) is taken as inductive (R-L) one. the maximum value of the output voltage is obtained.www. RL B T6 T3 ZL.com The rms value of the output phase voltage is obtained as ⎤2 ⎡ 2 π ⎤2 ⎡ 1 2π ⎡1 ⎛ 1 ⎞⎤ 2 2 E0 = ⎢ (e AB ) dθ ⎥ = ⎢ 2 ( Es ) 2 sin 2 θ dθ ⎥ = Es ⎢ ⎜ π − α + sin 2α ⎟⎥ ∫ ∫ 2 ⎠⎦ ⎣π ⎝ ⎦ ⎦ ⎣ 2π α ⎣ 2π α 0 When α = 0 . the rms value of the phase current is obtained from I ab = I + I + I + I + I + I + + I For delta connection. it can be observed that the line currents depend on the delay angle. 27. As given in point #6.4. So. the rms value of the line current is. A T4 T1 ZL. RL C T2 T5 ZL. the balanced load for the circuits (Fig.1 & 27. where m is an odd integer) of the phase currents flow around the delta. are. the triplen harmonic components (i. From Fig. and may be discontinuous.e. the rms value of the line current would not follow the normal relationship of a threephase system such that I a < 3 I ab . Kharagpur 9 www. This is due to the fact that these harmonic currents are like the zero sequence component. and the control range of delay angle is 0° ≤ α ≤ 180° (π ) .jntuworld. 1 1 1 [ 1 2 2 n ] [ ] 1 Comparison of the Different Circuits used for Three-phase AC Regulators Besides the two circuits shown in figures 27. other circuits used for three-phase ac regulators (ac to ac voltage converters).com . The important points of comparison between the circuits are stated. If I n is the rms value of the nth harmonic component of a phase current. which can be determined from the phase current. ia = iab − ica .. 27. ib = ibc − iab and ic = ica − ibc .

27.1). RL T4 ZL. 27. Version 2 EE IIT.3 & 27. The peak voltages occur across thyristors at or near the fully off state.5(c) Control in delta 1.5(b) 4-wire star load ZL.5b).www. the method of firing and the presence of voltage-sharing resistors across the thyristors. the individual phase controllers control their own loads independently of the other. RL Fig. the maximum thyristor voltage will be somewhere between the peak of the phase and line voltages depending on the leakage currents of the thyristors. 27. RL T2 A T1 B T3 C T5 Fig. and they have to be studied as complete three-phase circuits. the maximum thyristor voltage is the peak of the line voltage.3 & 27. 27. the individual phase controllers affect the other phase loads also.jntuworld. 27.5a). Kharagpur 10 www. All the five circuits can be used under phase control. As stated earlier. in two circuits (Fig. 27. In case of two circuits (Fig.5c). as stated earlier in one case (Fig. it is the peak of the phase voltage. RL C T2 T5 ZL. they can. 2. whereas in the circuit (Fig. 27. RL T6 ZL. therefore be studied as three singlephase controllers. 4. In two circuits (Fig.com . 3.5b).1 & 27. RL B T6 T3 ZL.jntuworld.com N A T4 T1 ZL. In other circuits.

instead of thyristor. the thyristors connected back to back. uncontrolled output voltage. where only one thyristor per phase is used.e. same as input one. which are lower than the line currents. Version 2 EE IIT. The maximum current in the thyristors is decided from the fully on condition. The readers are requested to refer to text books. The peak. The range of phase angle required to achieve full output range from zero to maximum varies between the circuits. which can be converted into its equivalent star. Kharagpur 11 www. 8. with the load connected in the three lines. which are flowing in the thyristors in the first one. or if they are bidirectional. The operation with three-phase balanced resistive load. for three-phase ac regulator (ac to ac voltage converter) are taken up. It may be mentioned that other types of circuits for three-phase ac regulator can be used. but not two devices. 27.com 5. The difference between the two circuits (Fig. but in the second half. The load impedance per phase is equal in magnitude (Z) and angle ( ϕ ).1) are related to the rms value of the input (ac) current. 6. in one half. is obtained.1 summarises the current and voltage rating parameters associated with all these circuits used as three-phase ac controllers. In the next. as only one device. controlled output voltage as shown earlier is obtained. is used. mean and rms values of the thyristor currents (Table 27. in one half.5c) is that. the neutral point is available. 7. controlled output voltage is obtained.1. third and final lesson in the first half. including the above two.1 & 27. 27. E ac and I ac are the rms values of the line voltage and line current respectively. unidirectional. 27.1 & 27. 9.5a) are the line currents. 27.1 & 27.com . the control circuit for ac regulators will be described in detail.5a) is that in the second one.www. and are given in Table 27. are in delta. making it a 4-wire one. Also. the important points of comparison of the performance with different types of circuits. The difference between the two circuits (Fig. are presented.jntuworld. Also. along with waveforms. In this lesson – the second one in the first half. as it is mostly inductive (R-L). Lastly. but either the circuits are not bidirectional. the current in the thyristors in the second case (Fig. output voltage is zero.5b) is that in the second one. in the second one.1). the current in the thyristors in the second case (Fig. is then described. 27. only diode connected back to back per phase.jntuworld. which are higher than the phase currents. i.c) are the phase currents. making it identical to the first circuit (Fig. only in one half with the thyristor per phase. which should be found by applying the full supply voltage to the load circuit. 27. which are flowing in the thyristors in the first one. firstly the study of two basic circuits – one with star connection and the other with delta connection. i. In the second case. is used. and the size of the thyristors to be used should be chosen from this condition. which is taken as positive. the three-phase balanced loads are connected in delta. but in the other one. The difference between the two circuits (Fig. Table 27.e. In the first case.

45 0.) Delay angle.26 0. Kharagpur 12 www.rms) ( E ac 3Z 27.414 1.5b 27.414 Peak I ac 1.816 Mean I ac 0.225 1.www.26 RMS I ac 0.414 0.45 0.707 0.408 3 E ac Z 3 E ac Z E ac 3Z E ac 3Z 2 I ac R 2 I ac R 2 3 I ac R 2 3 I ac R Version 2 EE IIT.3 27.707 0.5c Maximum load power dissipation Thyristor Thyristor current 27.5a 27. α for full control (degrees) 150 180 150 180 150 Maximum input line current I ac .1 2 3 I ac R V RWm Vac 1.1 Rating of the Parameters used in Three-phase AC Regulators Circuits (Fig.816 1. No.jntuworld.816 1.com Table 27.225 0.jntuworld.408 0.414 0.414 1.45 0.com .707 0.

jntuworld.com Module 4 AC to AC Voltage Converters Version 2 EE IIT. Kharagpur 1 www.www.com .jntuworld.

com . Kharagpur 2 www.jntuworld.www.com Lesson 28 Phase Angle Control in Triac-based Single-phase AC Regulators Version 2 EE IIT.jntuworld.

along with the waveforms The harmonic analysis of the output voltage of a single-phase ac regulator with resistive load Introduction In the last lesson − second one in the first half of this module. TRIAC A Triac is equivalent to two thyristors connected back to back as shown in Fig. In this lesson − the third and final one in the first half. for the same reasons. The power circuit (also shown in Fig. harmonic analysis of the output voltage waveform. along with the waveforms. briefly discussed. fed from a single phase supply. Two basic circuits − star-connected and delta-connected. is briefly presented. having already been introduced in lesson #4 (module 1). as it is not frequently used. is presented. are presented. is shown in Fig. preventing the flow of current from Cathode to Anode. also termed as ac to ac voltage converters. which is a unidirectional device. with rated voltage of. 26.1c (lesson #26)) consists of a Triac in series with inductive (R-L) load.jntuworld. along with the waveforms. in contrast to the thyristor. In this case. the operation of the various blocks used in the above circuit. 26. the circuit used for the phase angle control in triac-based single-phase ac regulator. used in the ac circuit. DIAC (may have been introduced earlier). having reverse blocking characteristic. the load is balanced inductive (R-L) one. Finally. also termed as ac to ac voltage converter. say 220 V(rms). the important points of comparison of the performance with different types of circuits. is also briefly described. Similarly. Keywords: Phase angle controller circuit. with the circuit symbol shown in Version 2 EE IIT. it is a bidirectional switching device.com . Kharagpur 3 www. are described. or ac to ac voltage converter.jntuworld. some important points of the bidirectional controlled device (TRIAC). Before going into the operation of the phase angle controller circuit.com Instructional Objectives Study of the following: • • • The circuit used for the phase angle control in triac-based single-phase ac regulators (ac to ac voltage converters) The operation of the various blocks used in the circuit.www. This switching device is called as TRIAC (TRIode AC switch). being used here as an uncontrolled bidirectional device. 28. the harmonic analysis of the output voltage of a single-phase ac regulator with resistive load is. having rated frequency ( f = 50 Hz). Lastly. various circuits of the threephase ac regulators.1a.1. are first taken up. current flows in both directions (forward and reverse). The operation of the two circuits with threephase balanced resistive (R) load. Then. So. Phase Angle Controller Circuit for Triac-based Single-phase AC Regulator The phase angle controller circuit for a triac-based single-phase ac regulator (ac to ac voltage converter). Triac-based single-phase ac regulator. firstly. when it (triac) is in conduction mode. is then discussed. including the above two. is described. Thus.

if the current through it. is negative. Similarly. MT1 is taken as the reference point for the measurement of the voltages and currents at other two terminals. Since a triac can be triggered in either direction.com . MT2 (+) and MT1 (−).jntuworld. 3. speed control for fan motors (single-phase). Please note that the voltage between two terminals. Triacs are available in lower rating as compared to thyristors. This will be nearly valid. of the thyristor The terminal. G (gate) and MT2 . whereas anti-parallel thyristor pair needs two heat sinks of slightly smaller sizes. whereas it is to be replaced by two thyristors. have been discussed in lesson #4 (module 1). falls below holding current. the triac can conduct in both directions (positive and negative) as given here. the triac conducts in negative direction from MT1 to MT2 . 28. being connected in series with the load. MT1 (+) and MT2 (−). MT1 . A thyristor turns off (non-conducting mode). when a positive pulse is fed at the Gate terminal with respect to Cathode. if the load inductance is small. when a positive pulse is applied at the gate (G) terminal with respect to MT1 and at the same time. Advantages 1. The gate (G) is near to the terminal. Only one triac is needed. in this case. Disadvantages 1. etc. falls below holding current. 4. Triacs are triggered by positive or negative polarity voltages applied at the gate terminal. A triac needs a single heat sink of slightly larger size. a trigger circuit for triac needs careful consideration. The triac is a low power device. The V-I characteristics of both thyristor and triac.jntuworld. irrespective of its direction. the positive voltage is applied between two terminals. used in voltage control circuits. As a triac is connected in an ac circuit. but due to the clearance total space required is more for thyristors. Similarly. Triacs have low dv / dt rating as compared to thyristors. a triac turns off (non-conducting mode). So.www. The case of higher inductance in the load has been discussed in detail in lesson #26 (module 3). The thyristor conducts with the current direction from Anode to Cathode (positive). when a negative pulse is applied at the gate (G) terminal with respect to MT1 and at the same time. used as light dimmers. the triac turns off at the zero crossing points of the voltage in each half (the supply (input) voltage reaches zero at the end of each half cycle). shown in the same figure. after the zero crossing point is reached in each half. Kharagpur 4 www. as the current though it goes to zero. Some of the advantages and disadvantages of the triac vis-a-vis thyristor are given. and at that time. and if the load in the circuit is resistive. 2. the positive voltage is applied between two terminals. The three terminals of the triac are designated as MT1 . The reliability of triacs is lower than that of thyristors.1. though the triac in that case turns off. These are similar to the terminals – A (Anode). whereas the thyristor conducts in one (positive) direction only. with consequent change in the control circuit. MT2 and gate. K (Cathode) and G (Gate).com Fig. G . MT2 and MT1 . The triac conducts in the positive direction from MT2 to MT1 . with positive voltage applied between Anode and Cathode terminals. 2. if the magnitude of the current. Version 2 EE IIT.

the V-I characteristic of diac. The power circuit. So. The diac conducts.jntuworld. if the current through it.1) is presented. a diac can conduct in both directions (positive and negative). A (Anode) and K (Cathode). is used for the protection of the triac – the power switching device. The two terminals of the diac are designated as T1 and T2 . the operation of the phase angle controller circuit (Fig. and vice versa..com . as given in lesson #2 (module 1).1) can be connected in opposite direction. current flows in both directions (forward and reverse). falls below holding current. when the break-over voltage is reached in either polarity across its two terminals.1. 28. The diac is symmetrical. as it is not included here for obvious reason. V AK exceeds VBO (break-over voltage). having reverse blocking characteristic. and if at that time if the voltage. If the V-I characteristic of diode is known. A diode does not conduct in the negative direction. The students are requested to study the characteristic of diac from a text book. V12 exceeds VBO1 (break-over voltage). has been described earlier. This switching device is called as DIAC (DIode AC switch). Similarly.2. in contrast to the diode. with T1 in place of T2 . Now. falls below holding current. When T1 is positive with respect to T2 . though it conducts in both directions like diac. A diode turns off (non-conducting mode). when it (diac) is in conduction mode. if.www. is the controller for the triac. including the diac used for triggering of the triac. with the circuit symbol shown in Fig. T1 in place of T1 . and if at that time if the voltage. irrespective of its direction. Kharagpur 5 www. Gate (G). at that time.com DIAC A Diac is equivalent to two diodes connected back to back. The triac is not symmetrical. Similarly. So. and the gate signal to be fed between G & MT1 (reference) for triggering. the diac conducts in positive direction from T1 to T2 . if the magnitude of the current. preventing the flow of current from Cathode to Anode. the voltage. So. 28. shown in the same figure. which is a unidirectional device. it is a bidirectional device. of the diode. Two reasons are: the presence of third terminal. shown in the figure. whereas a diode conducts only in positive direction from Anode (A) to Cathode (K). with the waveforms at various points shown in Fig. i. if the voltage. T2 . The remaining part. 28. as described earlier. V AK is negative.e. a diac turns off (non-conducting mode). Also. These are similar to the terminals. But the operation here is described with the connection as in the figure. the main component of which is the triac.jntuworld. Version 2 EE IIT. unlike the triac. The snubber part ( Rs & C s ). V21 exceeds VBO 2 (break-over voltage). 28. on the lines of the triac can be developed. the diac (Fig. when T2 is positive with respect to T1 . the diac conducts in negative direction from T2 to T1 .

jntuworld.com .com RS TRIAC CS Snubber A MT2 MT1 G D l o a d Control Circuit 1-phase ac supply + ∼ Rpot.1: Phase angle controller circuit for a single-phase ac regulator using TRIAC Vm vi 0 π/2 π 3π/2 2π 5π/2 θ (ωt) -Vm (a) π+α1 π+α2 vc 0 α1 α2 π 2π 2π+α1 2π+α2 3π θ (Ver (b) 3π DIAC breaks down Version 2 EE IIT. 28. Kharagpur 6 www.jntuworld. T1 vc DIAC T2 C - R1 - + B Fig.www.

The capacitor voltage ( vC ) is shown in Fig.jntuworld.2b. The polarity of the voltage across the capacitor. As soon as the capacitor voltage. with the right hand side as negative. which is low. the triac is turned on at the angle. c(vc) (c) Output (load) voltage. the diac starts to conduct in the positive direction from T1 to T2 . vC reaches the break-over voltage ( VBO ) of the diac (about 30 V). 28.2a). At this point. vAB (b) Voltage across capacitor. 28. when the voltage changes from negative to positive.jntuworld.2: Waveforms at various points of the controller circuit (a) Input (source) voltage. the triac gets a positive pulse at its gate (G is now positive with respect to MT1 ) and also MT2 is at a higher potential than MT1 . the capacitor. vDB with Rput = R2 (lower) (d) Output (load) voltage. C is that the left hand side is positive. So.com Vm vL 0 π+α1 α1 π/2 π 3π/2 2π 5π/2 2π+α1 θ 3π -Vm (c) Vm vL 0 π+α2 α2 π 2π 2π+α2 θ 3π -Vm (d) Fig. The polarity of the input voltage is important. R pot = R2 . The triac is turned off at θ = π .www. when the input Version 2 EE IIT. the time needed for the capacitor voltage to reach the break-over voltage ( VBO ) is t1 ∝ α 1 . C starts getting charged through the potentiometer resistance. The point. So. The current through the triac is in the positive direction from MT2 to MT1 . the value of which is low and the load resistance. vDB with Rput = R3 (higher) As soon the input (supply) voltage is given to the circuit. Please note that the time constant of the charging circuit is related to the potentiometer resistance ( R2 ). 28.com . 28. A is now positive with respect to B (Fig. Kharagpur 7 www.1). The start of the input voltage is taken as the positive zero-crossing point (Fig. θ = α 1 = ω t1 = 2 π f t1 .

The resistance. the capacitor voltage (Fig. As in the earlier case. At this point. As the input voltage has to exceed at least the voltage drop in the triac. The input voltage (Fig. The charging starts from the negative zero-crossing of the input voltage (Fig. The polarity of the input voltage is now opposite. the triac gets a negative pulse at its gate (G is now negative with respect to MT1 ) and also MT1 is at a higher potential than MT2 . the time needed for the capacitor voltage (in magnitude. 28. Though the function of the diac could have been performed by using two diodes connected back to back.2b) starts decreasing at t = t1 . neglecting the voltage drop across the triac. Other conditions. the triac may not be Version 2 EE IIT. making the control circuit simple with few components only (Fig. The capacitor. The rms value of the output voltage also decreases. as it was earlier. but it is opposite in this (negative) half. in the ideal case. 28. the total resistance is quite low. So. 28. and the capacitor voltage (Fig. the resistance R1 . the triac is turned on at the angle.2b) also has to reach the break-over voltage of the diac as given earlier. To change the conduction period. The triac is turned off at the next positive zero-crossing point ( θ = 2 π ). But normally. The polarity of the capacitor voltage (Fig. The output (load) voltage ( v L = v DB ) waveform (Fig. The diac now starts to conduct in the negative direction from T2 to T1 .2b) starts decreasing. The discharge path is through diac. before the gate pulse can be withdrawn. as the time constant of the charging circuit also increases. The capacitor voltage (Fig. the total time in both half is ( π − α 2 ). which is higher. So. G & MT1 terminals of the triac. 28. with the right hand side as positive.com voltage reaches the negative zero-crossing point. Also.com . the potentiometer resistance is to be increased from R2 to R3 .2b) is also opposite. The charging time constant remains same (low). The capacitor voltage. with the point. the lower limit is higher than 0° . 29. So. 28. C starts charging in the opposite direction through the same path as given earlier. is not described. The conduction period decreases. is 0° < α < π . the conduction period (angle in rad) is from α 1 to π in the positive half. and reaches zero after some time.jntuworld. the normal range of phase angle delay is to be used. the time constant during discharge is quite low. and the left hand side as negative. the time being small.2a) is zero at the two limits ( 0° & 180° ) in the ideal case. 28. say during discharge of the capacitor voltage remaining same.2a). the control circuit would have to be modified. 28. 28. not the ideal ones. B being positive with respect to A. The current through the triac is in the negative direction from MT1 to MT2 .www. Kharagpur 8 www. the current in the triac has to exceed a threshold value. ( θ = π + α 1 ). R1 is used to decrease the capacitor current during discharge. as compared to that during charging.1). The output voltage waveform is identical. 28. vC (in magnitude) reaches the break-over voltage ( VBO ) of the diac after time t1 ∝ α 1 . and the gate. the diac helps in the turning on of the triac in both directions. or the start of conduction of the triac. and reaches zero after some time. the total conduction time ( π − α 1 ) being same in both half. The conduction period in the positive half (Fig. Thus. as both halves are considered) to reach the break-over voltage ( VBO ) of the diac is now ( t 2 ∝ α 2 ). The range of phase angle delay. The pattern is repeated in the negative half of the input voltage. Otherwise. So. The conduction period (Fig.2c) is from ( π + α 1 ) to ( 2 π ) in the negative half. if the load is inductive.2c) is nearly same as the input voltage ( vi = v AB ). while the upper limit is lower than π (180°) .jntuworld. 28. which is briefly described.2b as dotted line. The capacitor voltage waveform for this case is shown in Fig. measured from the negative zero-crossing of the input voltage ( θ = π ).2d) is from α 2 > α 1 to π . the discharge path remaining same.

This can be observed from the voltage waveforms given in the previous lessons (#26-27) in the first half of this module (#4). with the increase in delay angle. including some described earlier. The symbols. as the delay angle is increased. The rms value of nth harmonic component = cn / 2 Version 2 EE IIT. The harmonic analysis of the output voltage waveform (Fig. 28.2c-d.3) is briefly presented. the following points may be noted. which are nearly same as Fig. The output (load) voltage in ac regulators (both single-phase and threephase) decreases. and phase angle. These are mainly used to decrease the speed of the induction motor with fan type load ( TL ∝ N 2 ).com triggered. Kharagpur 9 www. being phasecontrolled ones. with inductive load in series with battery or back emf. for both types of ac regulators.jntuworld. of nth harmonic component respectively. are given. This point may have been described in the case of phasecontrolled single-phase (bridge) converters (ac-dc). Harmonic Analysis of the Output Voltage Waveform Before the harmonic analysis of the output voltage waveform is taken up. in lessons #10-11 (module 2).3) of a single-phase ac regulator with resistive (R) load (please see the waveforms given in figures 28. and θ n = tan −1 (bn / an ) .com . v0 = Instantaneous value of the output (load) voltage Vm = 2 V = Peak value of the input voltage V = Vm / 2 = RMS value of the input voltage f = 1 / T = Frequency (Hz) of the supply (input) ω = 2 π f = Angular frequency (rad/s) θ = ω t = Angle (rad) T = 1 / f = Time period (s) a n & bn are the maximum values of the sine and cosine components of the harmonics of order n. The application is in the low power range. present in the output voltage waveform respectively. and the other relationships are an = cn cos θ n and bn = cn sin θ n . 2 The relationships are cn = a n + bn2 . not for constant load torque operation. The harmonics are also present in the output (load) voltage waveforms. 28. of ac regulators.jntuworld. cn & θ n are the maximum value (amplitude). The major disadvantage of these regulators is that the power factor and also displacement factor decrease. returning to off state again.www.

say the expressions for the other. the first one is positive in the positive half cycle. 28. Kharagpur 10 www. θ = α . as the load is resistive (R).jntuworld. 5.3) consists of two parts. Also to be noted that the average value is zero. v0 = 0 for α < θ < 0 .com Vm vo π+α α π 2π θ(ωt) -Vm Fig.jntuworld. when the input voltage and also the output current goes to zero. v0 = Vm sin θ = 2 V sin θ for π < θ < α . The even ( n = 2 m ) harmonics are not present in this case. π π ⎛ 2V ⎞π 2 2 ⎟ a1 = ∫ v0 (θ ) sin θ dθ = ∫ 2 V (sin θ ) 2 dθ = ⎜ ⎜ π ⎟ ∫ (1 − cos 2θ ) dθ π 0 πα ⎝ ⎠α Version 2 EE IIT. It can be observed for the single-phase ac regulator circuit shown in lesson #26 in this module (#4) that the switching device (triac or two thyristors connected back to back) is turned on at the delay angle. of the output voltage are derived. while the second part is negative in the next (negative) half cycle. The waveform has half-wave asymmetry. bn = ∫ v0 cos ( n θ ) dθ π 0 π 0 Please note that two formulas given here. 7 . and then turns off at θ = π . The output (load) voltage waveform (Fig. v0 = n =1. This is repeated in the second (negative) half. The expressions for the components of the fundamental and third harmonic. 3. The output (load) voltage waveform for one cycle is. the expression is. This can also be computed by the formulas for the harmonic analysis of the output (load) voltage waveform of the buck converter (dc-dc) circuit. 3. 28. 5.com .3: Input and output voltage waveforms of a single-phase ac regulator with resistive load. ∑c ∞ n sin (nθ + θ n ) where. as the second part is cancelled by the first part. v0 = Vm sin θ = 2 V sin θ for (2 π ) < θ < (π + α ) In terms of the Fourier components.www. say fifth harmonic components. π π 2 2 an = ∫ v0 sin ( n θ ) dθ . v0 = 0 for (π + α ) < θ < π . with only odd ( n = 2 m + 1 ) harmonics being present. The students are requested to derive. ∑ (an sin nθ + bn cos nθ ) = ∞ n =1. 7 . given in lesson #18 in module 3. in the first (positive) half. differ from two formulas given in lesson #18 (module 3).

5. It may be stated that the rms values of the harmonic components of both output voltage and current decrease.jntuworld. can. and not repeated here.com ⎛ 2V ⎞ ⎛ 2V ⎞ ⎛ 2V ⎞ π ⎟ (θ − 1 sin 2 θ ) α = ⎜ ⎟ ((π − α ) + 1 sin 2 α ) = ⎜ ⎟ =⎜ 2 2 ⎜ π ⎟ ⎜ π ⎟ ⎜ π ⎟ ((π − α ) + 0. as this waveform has half-wave asymmetry (given earlier). it can be checked from the expression for the rms value (given in lesson #26). Kharagpur 11 www.5 sin 2 α ) ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎛ 2V ⎞ ⎟ =⎜ ⎜ π ⎟ ((π − α ) + sin α cos α ) ⎝ ⎠ π π ⎛ 2V ⎞π 2 2 ⎟ b1 = ∫ v0 (θ ) cos θ dθ = ∫ 2 V sin θ cos θ dθ = ⎜ ⎜ π ⎟ ∫ sin 2 θ dθ π 0 πα ⎝ ⎠α ⎛ 2V ⎞ ⎛ V ⎞ ⎛ V ⎞ 2 α ⎜ ⎟ ⎟ ⎜ ⎟ =⎜ ⎜ 2 π ⎟ (cos 2 θ ) π = −⎜ 2 π ⎟ (1 − cos 2 α ) = −⎜ π ⎟ (sin α ) ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ π π ⎛ 2V ⎞π 2 2 ⎟ a3 = ∫ v0 (θ ) sin 3θ dθ = ∫ 2 V sin θ sin 3θ dθ = ⎜ ⎜ π ⎟ ∫ (cos 2 θ − cos 4 θ ) dθ π 0 πα ⎝ ⎠α ⎛ 2V ⎞ 1 ⎛ 2V ⎞ π 1 ⎟ ⎜ ⎟ =⎜ ⎜ π ⎟ ( 2 sin 2 θ − 4 sin 4 θ ) α = ⎜ 4 π ⎟ (sin 4 α − 2 sin 2 α ) ⎝ ⎠ ⎝ ⎠ π π ⎛ 2V ⎞π 2 2 ⎟ b3 = ∫ v0 (θ ) cos 3θ dθ = ∫ 2 V sin θ cos 3θ dθ = ⎜ ⎜ π ⎟ ∫ (sin 4 θ − sin 2 θ ) dθ π 0 πα ⎝ ⎠α ⎛ 2V ⎞ 1 ⎛ 2V ⎞ α 1 ⎟ ⎜ ⎟ =⎜ ⎜ π ⎟ ( 4 cos 4 θ − 2 cos 2 θ ) π = ⎜ 4 π ⎟ (cos 4 α − 2 cos 2 α + 1) ⎝ ⎠ ⎝ ⎠ Using two sets of two expressions given earlier. are obtained. 7 . as given earlier. the rms values of the harmonic components of the output current are proportional to those (the rms values of the harmonic components) of the output voltage. It may be noted that. Version 2 EE IIT.jntuworld. the rms value ( cn / 2 ) and phase angle ( θ n ).com . V0 r = n =1. first. using the expression for the rms value. V0 is zero. 3. because the average value. including that of fundamental one. the rms values of only a few odd harmonic components need be computed. and the rms values of all even harmonic components are also zero. it (rms value) can be computed. V0r and the rms values of all odd harmonic components is. with only odd harmonic components being present. of the harmonic components of the output (load) voltage. be computed as per the formula given earlier. Then. The relation between the rms value. The rms values of all odd harmonic components. ∑ (c n / 2)2 It may be noted that this expression is different from that given in the section on the harmonic analysis of the output voltage waveform of a buck converter (dc-dc) in lesson #18 (module 3). This is. because the rms values decrease. as the order of harmonic increases. As there is no inductance in the load circuit. is given in lesson #26 of this module (4). though not in inverse proportion to ( n ) as given in lesson #18 (module 3). as the order of harmonic ( n ) increases.www. The expression for the rms value of the output voltage. Finally. as a function of phase angle delay α .

are presented. 7 . The power circuit using mostly thyristors.1. ∑ (c n / 2 ) 2 = (V0 r ) 2 − (c1 / 2 ) 2 From this expression. it can be observed that the rms values of all odd harmonic components. 5 . first. and is slightly higher than the rms value of its fundamental component. in normal case. are mostly described in detail. though it reaches maximum at α = 0° (ideal case).com . Also the rms value of the output voltage. the harmonic analysis of the output voltage of a single-phase ac regulator with resistive load is. V0r is maximum (nearly same as the rms value of input voltage) for α ≈ 0° . Starting with the next (fourth) lesson ─ first one in the second half.jntuworld. Then. Version 2 EE IIT. are very low. is described. it can be observed that the rms values of all odd harmonic components. but no odd harmonic components). ( c1 / 2 ) is maximum (highest) for α ≈ 0° with α > 0° . starting from third. From the expression.com The rms value of the fundamental ( n = 1 ) component of the output voltage. ∑ (c n / 2)2 This expression can also be written as. V0 r = (c1 / 2 ) 2 + n = 3. If the expression under the square root for the rms value is divided into two parts – the rms value of fundamental component and the rms values of other odd harmonic components. the resistive load is balanced one. The rms value of the fundamental component of the output voltage. and the various blocks of control circuit required (in brief). 7 . but no even harmonic and also dc components. unlike the case shown in Fig. along with the waveforms. Finally.jntuworld. 28. of the voltage waveform having half-wave asymmetry (with only odd ( n = 2 m + 1 ) harmonic components. as discussed in lessons #1011 & 13-14 in module 2. except fundamental one. ( c1 / 2 ) is minimum (lowest) for α ≈ π (180°) with α < π . using the rms value. has half-wave symmetry (having dc and only even ( n = 2 m ) harmonic components. This type of harmonic analysis can be performed for the output voltage of controlled (half/full) single/three-phase converters (ac-dc) with resistive load. with the second half of the periodic waveform being also positive. The voltage waveform in that case. and is slightly higher than the rms value of its fundamental component. are very low. the output voltage waveform obtained is of the same type. the various types of cyclo-converters. which also includes fundamental one in this case. V0r is minimum (not zero. and the rms value of fundamental component only. briefly discussed. n = 3.www. in normal case. Kharagpur 12 www. 5 . and other expressions given earlier. starting from third one. except that it is a dc one. and also from the expressions given earlier. presented. In the case of three-phase ones. the output voltage waveforms for both single-phase and three-phase ones. In this lesson − the third and final one in the first half of this module. the circuit used for the phase angle control in triac-based single-phase ac regulator or ac to ac voltage converter is. the operation of the various blocks used in the above circuit. unlike the case here. though it is minimum (zero) at α = π (ideal case). used as ac to ac voltage converters. Also the rms value of the output voltage. as given earlier). the new form is. Taking the case of a single-phase controlled bridge converter with resistive load. but nearly zero) for α ≈ π .

Kharagpur 1 www.com .jntuworld.com Module 4 AC to AC Voltage Converters Version 2 EE IIT.jntuworld.www.

com . Kharagpur 2 www.com Lesson 29 Introduction to Cycloconverters Version 2 EE IIT.jntuworld.jntuworld.www.

com . or thyristors connected back to back. Note that this is a two-stage process with an intermediate dc stage.jntuworld. so as to obtain an ac waveform (output) of low frequency. This type has been described in module 2. using either triac. Kharagpur 3 www. in the form of phase-controlled one. These devices are called forcecommutated ones. As will be shown in the last (fifth) module. the circuit of a single-phase to single-phase cyclo-converter using thyristors is presented.3). and ac to ac voltage controllers − both single-phase and three-phase. Then.4) − first one in the second half of this module. say line. the output voltage of the cyclo-converter circuit (single-phase) using thyristors. an alternating voltage at any frequency (output) is obtained using an inverter as a power controller from a dc voltage fed at its input. without any intermediate dc stage. when used in dc chopper circuits (described in module 3). the circuit and operation of ac to ac voltage controllers − both single-phase and three-phase. is synthesized from the above phase-controlled voltage waveforms. the basic principle of operation used in a cyclo-converter is discussed. i. 29. In the above cases. for obtaining dc output voltage from ac supply (#2. is again obtained using a rectifier (converter) with ac voltage (normally at supply frequency) fed at its input. The readers at this stage. the power switching devices used in the inverter circuit belong to transistor family (termed as self-commutated ones). the cyclo-converter is introduced as a type of power controller. The angle. converter circuits. were described in detail. Keywords: Single-phase to single-phase cyclo-converter using thyristors.1-4. dc voltage. This input. along with the voltage waveforms Introduction Earlier in the last three (4. Cyclo-converter Basic Principle of Operation The basic principle of operation of a cyclo-converter is explained with reference to an equivalent circuit shown in Fig.1-4. as can be observed from the waveforms shown in the above lessons. Each two-quadrant converter (phase-controlled) is Version 2 EE IIT.www. The devices used are either triac. Now-a-days. line commutation takes place. with the input being an ac voltage of higher frequency. i.e. along with voltage waveforms.3) lessons (first half) of this module. the output frequency of the cyclo-converter is limited to about one-third of supply (line) frequency of 50 Hz. Voltage waveforms. but in this case. In this lesson (4. starting with power transistors. have gone through the following lessons − single-phase fully controlled converter using thyristors.e. Initially. This is followed by describing the operation of the above cyclo-converter circuit.2). at which the thyristors are triggered. As stated earlier.1. where an alternating voltage at supply frequency is converted directly to an alternating voltage at load frequency (normally lower).com Instructional Objectives Study of the following: • • • The cyclo-converter circuits − basic principle of operation The circuit for the single-phase to single-phase cyclo-converter using thyristors The operation of the above cyclo-converter circuit. whereas thyristors are still being used in the converter (rectifier) circuits.jntuworld. In the present case. is controlled to obtain the desired waveform. the output voltage obtained is. or thyristors connected back to back (#4.

the associated converter Version 2 EE IIT. and it remains idle throughout the whole period in which its terminal voltage is in the inverting region of operation.2a). In Fig. The diodes connected in series with each voltage source. the associated converter operates in its rectifying region. 29. the displacement angle of the load is 60° lagging.1) have the same amplitude.com . and the voltage of the cyclo-converter is equal to the voltage of either of these generators.jntuworld. frequency and phase. Kharagpur 4 www. it is inherent that the positive half-cycle of load current must always be carried by the positive converter. are shown in Fig. 29.com represented as an alternating voltage source. the voltages of the two generators (Fig. and the negative half-cycle by the negative converter. In this case. Normally. are used in the two converters. but the direction of current is in the direction as shown in the circuit. when it operates in its rectifying region. show the unidirectional conduction of each converter. the ripple content in the output voltage is neglected.2b. Because of the uni-directional current carrying property of the individual converters. It is possible for the mean power to flow either ‘to’ or ‘from’ the output terminals. so that each produces the same sinusoidal (ac) voltage at its output terminals. This means that each twoquadrant converter operates both in its rectifying (converting) and in its inverting region during the period of its associated half-cycle of current. as only thyristors − unidirectional switching devices.2. The output voltage and current waveforms. 29. Thus. illustrating the operation of an ideal cycloconverter circuit with loads of various displacement angles. During the first 120° period of each halfcycle of load current. iP iN eP = Em sin ωot ∼ + eo ac load iO - ∼ eN = Em sin ωot Positive (P) converter Control Circuit er = Er sin ωot Fig. whose output voltage can be either positive or negative. and delivers power to the load. each converter carries the load current only. regardless of the phase of the current with respect to the voltage. 29.jntuworld. 29. During the latter 60° period in the half-cycle.1: Equivalent circuit of cyclovonverter Negative (N) converter The control principle used in an ideal cyclo-converter is to continuously modulate the firing angles of the individual converters.www. which corresponds to the fundamental voltage component obtained at its output terminals. and the cyclo-converter is inherently capable of operation with loads of any phase angle − inductive or capacitive. being a two-quadrant one. The displacement angle of the load (current) is 0° (Fig.

into the ac system at the input side. the load is regenerating power back into the cyclo-converter output terminals. Version 2 EE IIT. Kharagpur 5 www. Any other case. which can be studied from a standard text book.com operates in its inverting region. This is not shown in Fig. the operation changes with inverting region in the first period of the half-cycle as per displacement angle. and under this condition.2. say capacitive load. with the displacement angle as leading.com .jntuworld. and hence. These two are illustrative cases only.www. 29. and the latter period operating in rectifying region.jntuworld.

jntuworld. two thyristors come in series with each voltage source.jntuworld. the thyristors of bridge 2 are triggered by giving pulses at their gates. while the firing pulses to the thyristors of bridge 1 are inhibited at that time. Two fullwave fully controlled bridge converter circuits. as the input voltage at the end of each half cycle (both positive and negative) reaches zero (0). while the thyristors of bridge 1 are triggered by giving pulses at their gates at that time. if some amount of circulating current is allowed to flow between them. and inductive (R-L) loads is explained. Bridge 1 (P – positive) supplies load current in the positive half of the output cycle. The control is somewhat simplified. This circulating current by itself keeps both converters in virtually continuous conduction over the whole control range. When the load current is positive. The readers are requested to refer to any standard text book. i. Kharagpur 6 www. In this case. if the load current is discontinuous. a circulating current limiting reactor is connected between the positive and negative converters. using four thyristors for each bridge. the Version 2 EE IIT.com Single-phase to Single-phase Cyclo-converter The circuit of a single-phase to single-phase cyclo-converter is shown in Fig. 29. are connected in opposite direction (back to back). iP iN P1 1-phase ac supply P4 P2 eO + l o a d iO N1 N2 1-phase ac supply P3 N4 N3 Bridge 1 (Positive) Bridge 2 (Negative) Fig. the firing pulses to the thyristors of bridge 2 are inhibited. while bridge 2 (N – negative) supplies load current in the negative half. the control scheme is complicated. two fully controlled bridge converters connected back to back. when the load current is negative. In this case. This type of operation is termed as the circulating-current mode of operation. the firing angle control scheme must be such that only one converter conduct at a time. should be periodic according to the output frequency. the load current (instantaneous) goes to zero.com .3.www. However. Thus. The two bridges should not conduct together as this will produce short-circuit at the input. 29. The operation of the cyclo-converter circuit with both purely resistive (R). as is the case with dual converter. and the change over of firing pulses from one converter to the other.3: Single-phase to single-phase cycloconverter (using thyristor bridges) When a cyclo-converter operates in the non-circulating current mode. Similarly. Resistive (R) Load: For this load. Thus.e. the firing angles the thyristors in both converters should be the same to produce a symmetrical output. This is the circulating-current free mode of operation. with both bridges being fed from ac supply (50 Hz). in circulatingcurrent mode.

e. Similarly. having same frequency as given earlier. by triggering them after suitable phase delay from the start of zero-crossing. by triggering them after suitable phase delay from the zero-crossing. Both the output voltage and current are now negative. with the output voltage also remaining positive. The following points may be noted. along with one negative half cycle. one combined positive half cycle of output voltage is produced across the load resistance. or pulses are fed at respective gates.com . 3 The firing angle (α) of the converter is first decreased. the above process also continues for three consecutive half cycles of input voltage. with its frequency being one-third of input frequency ( f 2 = f1 / 3 = 16 2 Hz).www. the number of cycles is to be increased. This process continues for one more half cycle (making a total of three) of input voltage ( f 1 = 50 Hz). P1 & P3 is triggered after phase delay ( α 1 ). The pattern of firing angle − first decreasing and the increasing. the other thyristor pair (even-numbered). 29. The current flows through the load in the same direction. In the next (negative) half cycle. Following same logic. P2 & P4 in that bridge conducts. Kharagpur 7 www. in the next three half cycles of input voltage. 29. the odd-numbered thyristor pair. as current flows in the load. in this case for second cycle only. with the firing angle decreasing for some cycles. One positive half cycle. and assuming the top point of the ac supply as positive with the bottom point as negative in the positive half cycle of ac input. as shown in Fig. i. and then again increasing in the subsequent cycles.4b. such that current starts flowing through the load in this half cycle. as described earlier. is also followed in the negative half cycle. This is.jntuworld. Taking first bridge 1 (positive). only when the next thyristor pair in that bridge is triggered. constitute one complete cycle of output Version 2 EE IIT. If the output frequency needed is lower. the thyristors undergo natural commutation. So. From three waveforms. operation with discontinuous current (Fig. because only three cycles for each half cycle is used.jntuworld. and then again increased in the next (third) cycle. 29.4) takes place. bridge 2 is used. if the bottom point of the ac supply is taken as positive with the top point as negative in the negative half of ac input. the oddnumbered thyristor pair. As in the previous case. From three waveforms. N1 & N3 conducts. the even-numbered thyristor pair. es 0 5π π 2π Mean output voltage 0 α2 α1 π 2π α3 3π (b) α4 (a) 3π 4π 6π e0 4π α5 5π 6π α6 Fig. one combined negative half cycle of output voltage is produced.com conducting thyristor pair in one of the bridges turns off at that time. N2 & N4 conducts in the next half cycle.4: Input (a) and output (b) voltage waveforms of a cycloconverter with an output frequency of 16 2 Hz for resistive 3 (R) load To obtain negative output voltage.

29. 29.6 respectively. 29. and current (c) waveforms for a cyclo-converter with discontinuous Version 2 EE IIT. its frequency being 16 2 Hz as stated earlier. double of the input frequency. i.com (load) voltage waveform. The supply (input) voltage is shown in Fig. The ripple frequency of 3 the output voltage/ current for single–phase full-wave converter is 100 Hz.4b).www.4c). Only one of two thyristor bridges (positive or negative) conducts at a time. giving non-circulating current mode of operation in this circuit.e.5: Input (a) and output (b) voltage.. the load current may be continuous or discontinuous depending on the firing angle and load power factor. The load voltage and current waveforms are shown for continuous and discontinuous load current in Fig.com . es 0 π 2π 3π 4π (a) 5π 5π 6π 7π 8π e0 0 π Mean o/p output voltage 2π 3π 4π 6π 7π 8π Mean o/p output voltage i0 0 α1 α2 α3 (b) (c) Fig.jntuworld. as also load (output) voltage (Fig.5 and 29. 29. Kharagpur 8 www. It may be noted that the load (output) current is discontinuous (Fig.4a. 29.jntuworld. Inductive (R-L) Load: For this load.

or #2 (negative). f 1 = 4 ⋅ f 2 . Kharagpur 9 www. also non-circulating mode of operation takes place.6: Input (a) and output (b) voltage. and current (c.com . in the positive half cycle of ac input. taking bridge 1.. the output frequency is assumed as ( f 2 = 12. P1 & P3. But Version 2 EE IIT.www. are required to produce one positive half cycle of the output waveform. In this case. As in the previous case with resistive load. Here. (a) Discontinuous load current The load current in this case is discontinuous. conducting at a time. L in series with the resistance. but two bridges do not conduct at the same time.e. So.jntuworld. is triggered after phase delay ( θ = ω t = α 1 ). i. four positive half cycles. as the inductance.jntuworld. but difference also exists as described. 29. as the output frequency is one-fourth of the input frequency as given earlier. and assuming the top point of the ac supply as positive. R. such that current starts flowing the inductive load in this half cycle. is low. with only one of the bridges − #1 (positive). or two full cycles of the input to the full-wave bridge converter (#1). or f 2 = f 1 / 4 . the input frequency being same as ( f 1 = 50 Hz).5 Hz). d) waveforms for a cyclo-converter with continuous load current. the odd-numbered thyristor pair. This is somewhat similar to the previous case. as this will result in a short circuit.com es 0 π 2π 3π 4π 5π 6π 7π 8π e0 0 Mean o/p output voltage π α1 2π α2 3π α3 4π α4 (a) 5π α5 (b) 6π α6 7π α7 8π α8 i0 0 (c) i0 0 (d) Fig.

Both the output voltage and current are now negative. The pattern of firing angle − first decreasing and then increasing. 29. the current flows for about one complete half cycle. due to inductance being present in series with resistance. The current goes to zero at ( 4 ⋅ π + β 1 ). due to load being inductive as given earlier. by triggering them after phase delay ( θ = 4 ⋅ π + α 1 ). and the thyristors turn off. At that time. till it reaches zero at ( θ = β 1 ) with (π +α 2) > β 1 > π . is triggered at (π +α 2) . the even-numbered thyristor pair. 29. It may be noted that the thyristor pair is. and finally increased in the last (fourth) one. N1 & N3 conducts. the current flows even after the input voltage has reversed (after θ = π ).e. in the next four half cycles of output voltage. The ripple frequency remains also same at 100 Hz. the current Version 2 EE IIT. 29. naturally commutated. the odd-numbered thyristor pair. Taking bridge 1. i. one combined negative half cycle of output voltage is produced with same output frequency. along with one negative half cycle.. as described.jntuworld. with the output voltage also remaining positive. or #2 (negative). such that current starts flowing the inductive load in this half cycle. P2 & P4.5 Hz as stated earlier. P1/P3. P2 & P4. as also load (output) voltage (Fig. four half cycles of input supply are required. The firing angle (α) of the converter is first decreased. N2 & N4 conducts in the next half cycle..e. in this case for second half cycle only. Similarly. only one of the bridges − #1 (positive). the current will be continuous.e. Following same logic. reverse voltage is applied across each of the conducting thyristors. In the next (negative) half cycle.jntuworld. Also. whichever is higher. but two bridges do not conduct at the same time. P1 & P3. But here. Most of the points given earlier are applicable to this case. From these four waveforms. The current flows now in the opposite (negative) direction through the inductive load. So. with the output voltage also remaining positive. From these four waveforms. is triggered at (π +α 2) . The current flows through the load in the same direction. The current goes to zero at ( 5 ⋅ π + β 2 ).5b). i. 12. The output frequency is one-fourth of input frequency (50 Hz). in the positive half cycle of ac input. is also followed in the negative half cycle.5 Hz. if the bottom point of the ac supply is taken as positive in the negative half of ac input. with (π +α 3) > β 2 > π . its frequency being 12. with the ripple in load current being filtered by the inductance present in the load. one combined positive half cycle of output voltage is produced across the inductive load. i. This procedure continues for the next two half cycles. Also. The current goes to zero at (π + β 2) . ( π + α 1 ) or ( π + α 2 ). the load current is discontinuous. kept nearly same in the third one.com . due to the high value of load inductance. the odd-numbered thyristor pair. As in the previous case. One positive half cycle. 29. It may be noted that the load (output) current is discontinuous (Fig. making a total of four positive half cycles. for each half-cycle of output voltage waveform. after they are triggered at ( 5 ⋅ π + α 2 ). as this will result in a short circuit. as shown in Fig. The supply (input) voltage is shown in Fig. bridge 2 is used. even after the input voltage has reversed. Kharagpur 10 www. with the output voltage being also negative. making a total of four. the ripple frequency in the voltage and current waveforms remains same at 100 Hz.5c). the above process also continues for two more half cycles of input voltage. conducts at a time.www. If the inductance is increased. The current flows through the load in the same direction. the other thyristor pair (even-numbered). as the inductance of the load is low. is triggered after phase delay ( θ = ω t = α 1 ). (b) Continuous load current As given above. In the next (negative) half cycle. To obtain negative output voltage.com here. thus. and assuming the top point of the ac supply as positive. constitute one complete cycle of output (load) voltage waveform.5a. non-circulating mode of operation is used. the other thyristor pair (even-numbered).5b.. To repeat. up to the angle. its value being low.

Cyclo-converter is inherently capable of power transfer in either direction between source and load. N2 & N4 conducts in the next half cycle. and is also capable of regeneration over the complete speed range. under steady state condition. 29. From these four waveforms. But. as also load (output) voltage (Fig. both the conducting thyristors turn off. i. without auxiliary forced commutation circuits. kept nearly same in the third one.π + α 1 ) or ( 5 ⋅ π + α 2 ). 29. As in the previous case. 29. whichever is higher. is also followed in the negative half cycle. after they are triggered at ( 5 ⋅ π + α 2 ).com flows for about one complete half cycle. as reverse voltage is applied across each of them. by triggering them after phase delay ( θ = 4 ⋅ π + α 1 ). 29. The pattern of firing angle − first decreasing and then increasing. whichever is higher. in this case for second half cycle only. The firing angle (α) of the converter is first decreased. while the supply (input) voltage is shown in Fig. ( 5 ⋅ . if the bottom point of the ac supply is taken as positive in the negative half of ac input. the odd-numbered thyristor pair. One positive half cycle. It may be observed that the load (output) current is continuous (Fig. one combined negative half cycle of output voltage is produced with same output frequency of 12. ac power at one frequency is converted directly to a lower frequency in a single conversion stage. and cyclo-converter continues to function with somewhat distorted waveforms. making a total of four positive half cycles.com .e. ( 5 ⋅ π + α 2 ) or ( 5 ⋅ π + α 3 ). N1 & N3 conducts. whichever is higher. constitute one complete cycle of output (load) voltage waveform. if an individual fuse blows off. To obtain negative output voltage. bridge 2 is used. up to the angle. The power circuit is more compact. as shown in Fig. Following same logic. Advantages and Disadvantages of Cyclo-converter Advantages 1.6b.. i. down to standstill. up to the angle. with the output voltage being also negative.www. Also.jntuworld. one combined positive half cycle of output voltage is produced across the inductive load. 29.5 Hz. Similarly.e. as the load is inductive. making a total of four. A balanced load is presented to the ac supply with unbalanced output conditions. As described earlier. in the next four half cycles of output voltage. Version 2 EE IIT. The current flows for about one complete half cycle. The current flows now in the opposite (negative) direction through the inductive load. up to the angle. In a cyclo-converter. It can supply power to loads at any power factor. thus suited for metal rolling application. eliminating circuit losses associated with forced commutation. 4. 2. the even-numbered thyristor pair. the above process also continues for two more half cycles of input voltage. i. This procedure continues for the next two half cycles..e. This feature makes it preferable for large reversing drives requiring rapid acceleration and deceleration.6a. Cyclo-converter functions by means of phase commutation. along with one negative half cycle. From these four waveforms.jntuworld. Commutation failure causes a short circuit of ac supply.6b).6c). ( π + α 2 ) or ( π + α 3 ). The load (output) current is redrawn in Fig. a complete shutdown is not necessary.6d. 3. and finally increased in the last (fourth) one. Kharagpur 11 www. the current flows for about one complete half cycle. Both the output voltage and current are now negative.

which in this case is naturally commutated. For reasonable power output and efficiency. The power factor is low particularly at reduced output voltages. but is economical for units above 20 kVA. Large number of thyristors is required in a cyclo-converter.com . The number of devices. Cyclo-converter is extremely attractive for large power. to reduce the harmonics in voltage waveforms.jntuworld.7: DC link converter The cyclo-converter is normally compared with dc link converter (Fig.7). It may be noted that all features of a cycloconverter may not be available in a dc link converter.com 5. used in cyclo-converters depends on the types of connection. though thyristors using force commutation are also used. are used in uncontrolled ones. since it is fabricated from a large number of segments of the supply waveform. which are termed as self-commutated ones. The thyristors. connected back to back with the switching device. Similarly. the output frequency is limited to one-third of the input frequency. Advantages and Disadvantages of DC Link Converter Advantages 1. is needed for each device. Kharagpur 12 www. This is often preferable for very low speed applications. switching devices of transistor family are used in inverters. and the second one as inverter to obtain ac output at any frequency from the above dc input fed to it. may be a power transistor (BJT). 2.jntuworld. and its control circuitry becomes more complex. which is quite low due to the use of transistors in recent time. low speed drives. 3. The various circuits used and their operational aspects are discussed in detail in the next (last) module (#5) on DC to AC Converters termed as Inverters. or switching devices of transistor family.www. A diode. being decided by the turn-off time of the switching devices. with the upper frequency limit. 6. whose cost is low. It is not justified to use it for small installations. The number of switching devices in dc link converter depends upon the number of phases used at both input and output. certain features. where two power controllers. usually the former. 29. Converter 3-phase ac supply + - Inverter load Vdc 3-phase output Fig. Cyclo-converter delivers a high quality sinusoidal waveform at low output fre-quencies. such as thyristors. Version 2 EE IIT. are not applied in cyclo-converters. But now-a-days. like Pulse Width Modulation (PWM) techniques as used in inverters and also converters. 29. and also the number of phases at both input and output. first one for converting from ac input at line frequency to dc output. The diodes. as phase control is used with high firing delay angle. Disadvantages 1. The output frequency can be varied from zero to rated value. are used in controlled converters (rectifiers).

if the inductance is higher. power factor depends upon phase angle delay. In the next lesson. Version 2 EE IIT. The output waveform of the inverter is normally a stepped one. The conversion is in two stages. 2. 4.www.jntuworld. and also is involved to incorporate in a dc link converter.The control circuit here is simpler. . This can be reduced by using PWM technique as given earlier. 3. along with the basic principle of operation.jntuworld. Disadvantages 1. Forced commutation is required for the inverter. but can be continuous.com 2. 3. the first one in the second half of this module (#4). using two power controllers − one as converter and other as inverter. If phase-controlled thyristor converter is used. if diode rectifier is used in the first stage. the circuit and operation of three-phase to single-phase cyclo-converter. are described in detail. In this lesson. It has high input power factor. It is suitable for higher frequencies. Kharagpur 13 www. if thyristors are used. where natural commutation takes place. with both resistive and inductive loads. with resistive and inductive (with low value of inductance) loads.com . The circuit and the operation of singlephase to single-phase cyclo-converter. as compared to that used in cyclo-converter. 4. The current is discontinuous. The feature of regeneration is somewhat difficult. The distorted waveform also causes system instability at low frequencies. will be described in detail. as stated earlier. even though phase control is used in converter. as given earlier. with voltage and current waveforms. which may cause nonuniform rotation of an ac motor at very low frequencies (< 10 Hz). the cyclo-converter is first introduced. followed by three-phase to three-phase one.

jntuworld.www.jntuworld. Kharagpur 1 www.com .com Module 4 AC to AC Voltage Converters Version 2 EE IIT.

www.jntuworld.com . Kharagpur 2 www.jntuworld.com Lesson 30 Three-phase to Singlephase Cyclo-converters Version 2 EE IIT.

Similarly.e.com Instructional Objectives Study of the following: • • The three-phase to single-phase cyclo-converter circuit. the conducting thyristor (#5) in top half. using two threephase half-wave converters. The following are discussed in brief −. using two three-phase full-wave thyristorised bridge converters. Then.www. along with the voltage waveforms Introduction In the last lesson − first one in the second half of this module. Kharagpur 3 www. Three-phase full-wave bridge. The sequence of conduction of the thyristors is 1 & 6.jntuworld. Two full-wave bridge converters (rectifiers) connected back to back. one-third of one complete cycle. Three-phase to Single-phase Cyclo-converter The circuit of a three-phase to single-phase cyclo-converter is shown in Fig. 1 & 2.. i. being reverse biased at that time. Two thyristors in one leg are not allowed to conduct at a time. one-sixth of a cycle. low value of load inductance is needed to make the current continuous. where only one converter − bridge 1 (positive) or bridge 2 (negative). Keywords: Three-phase to single-phase cyclo-converter. and Circulating current modes of operation. in detail. turns off. but both converters do not conduct at the same time. and halfwave converters. the basic principle of operation of the cyclo-converter circuits has been presented. firstly. and also the cyclo-converter circuit. The ripple frequency here is 300 Hz. whereas a particular thyristor pair.jntuworld. which will result in short circuit at the output terminals. In this lesson − the second one in the second half.. Voltage waveforms. 30. This followed by the discussion of the circuit. along with its advantages and disadvantages. conducts at a time.4) with ripple frequency of 100 Hz. Non-circulating current.1. The mode of operation used is the non-circulating current one. when thyristor 2 is triggered. are used. six times the input frequency of 50 Hz. the three-phase to single-phase cyclo-converter circuit. i. Also. The thyristors conduct in pairs as stated. the operation of the above cyclo-converter circuit.e. along with voltage waveforms. Also described are the advantages and disadvantages of the cyclo-converter. being reverse biased at that time turns Version 2 EE IIT. with both resistive and inductive loads. say 1& 2 conduct for about 60° (π / 6) . one (odd-numbered) thyristor in the top half and the other (even-numbered) one in the bottom half in two different legs. 3 & 2. and the operation of the single-phase to single-phase cyclo-converter circuit with both resistive and inductive loads. and so on. the non-circulating current mode of operation is used. is presented. are used. with six thyristors for each bridge. with four thyristors as power switching device in each bridge. is described in detail. When thyristor 1 is triggered.com . So. the conducting thyristor (#6) in bottom half. as compared to one using single-phase bridge converters described in the previous lesson (#4. using two three-phase full-wave thyristorised bridge converters The operation of the above cyclo-converter circuit. firstly. Two threephase full-wave (six-pulse) bridge converters (rectifier) connected back to back.the circulating current mode of operation for the above. The dc link converter is introduced briefly. It may be noted that each thyristor conducts for about 120° (π / 3) .

of segments of near 60° (π / 6) is used. while bridge 2 is used for negative half cycle. Y is α = 90° . for positive half cycle of the output voltage waveform.2. its firing angle delay (α) is first decreased starting from the initial value of 90° to the final value of 0° .0 . The two quarter cycles form the positive half cycle of the output voltage waveform. as shown in Fig. W. N. When the firing angle delay is 0° . This can be observed from the points. 30.1: Three-phase to single-phase cycloconverter The procedure to be followed in the triggering of the thyristors in sequence in the two bridge converters has been briefly given earlier. using the segments starting from the points. or any standard text book. Also. is obtained. and also the firing angle is increased from 0° (T) to 90° (Y) in this interval. M. is obtained.jntuworld. bridge 1 is used. In this region.2). to form the sine wave at the output.5-2. O.jntuworld. i. It may be noted that the firing angle delay at the point. the bridge 1 (positive) is used. as the firing angle is decreased for each segment. iP iN P1 3-phase A ac B supply C P4 P3 P5 l o a d + N1 N3 N5 A 3-phase B ac C supply iO P6 P2 N4 N6 N2 Fig. 30. the other bridge converter (#2) termed negative (N) is used in the same manner as given earlier. shown in Fig. is zero.e. U. the average value of the segment is Vav ∝ cos α = cos 0° = 1. To obtain the negative half cycle of the output voltage waveform ( 180° − 360° ). Q. with its frequency also being reduced. and then again increased Version 2 EE IIT. R & S. From these segments.www. the output voltage waveform becomes near sinusoidal. The readers are requested to go through two lessons (#2. such the average value (dc) of the output voltage in this interval of near 60° (π / 6) [ Vav ∝ cos α 1 = cos 90° = 0. 30.4). As more no. The second quarter cycle of the above waveform from 90° to 180° . So. This sequence is repeated in cyclic order. 30. Otherwise. the procedure is similar to the one as discussed in the previous lesson.0 ].6) in module 2 (AC-DC Converters). and then again increased to the final value of 90° . the frequency being decided by the number of half cycles of input voltage waveform used for each half cycle of the output.com off. to obtain higher voltage Vav ∝ cos α 2 = +ve . It may be noted that the next thyristor in sequence is triggered at α 2 < 90° . As given in the earlier lesson (#4. V. the firing angle (α) of two converters is first decreased starting from the initial value of 90° to the final value of 0° .2. T. The two half cycles are combined to form one complete cycle of the output voltage. natural or line commutation takes place in this case. the first quarter cycle of the output voltage waveform from 0° to 90° . The initial value of firing angle delay is kept at α 1 ≈ 90° . P. Kharagpur 4 www.com . X &Y (fig.

P-converter acts as a rectifier. The load on the output of the cyclo-converter is assumed to be inductive (R-L). It can thus be inferred. The load power factor is also +ve ( cos φ ). It may be noted that the current is unidirectional in a thyristor converter.com . As the current.2 Output voltage waveforms for a three-phase to single phase cyclo-converter.e. The load can also be capacitive. The two half cycles (positive and negative) together give one complete cycle ( 0° − 360° ) of the output voltage waveform. and as an inverter.www. being alternating in nature.3) lags behind the voltage by its phase angle. and as an inverter. if these are of opposite polarity. i. Fabricated output voltage α = 90° e0 R P M N 0 Q ST U V W X θ = ωt α = 0° Mean output voltage α = 90° Y Fig. N-converter acts as a rectifier. as given earlier. when the output voltage is negative.com to the final value of 90° .jntuworld. 30. when the output voltage is positive. The positive (P) converter carries current during positive half cycle of output current. the output current (Fig. when the output voltage is negative (Fig. Version 2 EE IIT. in general. that one of two converters would operate as rectifier. flows in both directions in a complete cycle. Kharagpur 5 www. two converters are connected in antiparallel. and as an inverter. 30. when the output voltage is positive.jntuworld. while the other. if its output voltage and current have the same polarity. negative (N) one carries current in the negative half cycle. 30. φ (assumed to be positive). Similarly.3). For inductive load. As discussed in the previous lesson (#29).

e. It may be noted that. both for single-phase to single-phase and for single-phase to three-phase cyclo-converters. with an inter-group reactor (IGR) between the positive and negative groups as shown in Fig. acts in the rectifier mode. circulating current-free or non-circulating current mode of operation was described.3 Voltage (a) and current (b) waveforms for a three phase full-wave (sixpulse) cycloconverter. in this case. Version 2 EE IIT. of the output voltage being same. Due to this voltage. Thus. though the output voltages of two converters in the same phase have the same average value. The positive (P) converter conducts. 30.com Fabricated output voltage α = 90° α = 0° e0 Mean output voltage α = 90° θ = ωt (a) Inversion Rectification i0 Inversion Rectification Inversion Current in positive group Angle of load impedance (φ) (b) Current in negative group Fig. however.jntuworld. i. circulating current mode of operation of the cyclo-converter. and the other one acts in the inverter mode. if α p and α n are the firing angles for positive and negative group of converters. whereas the negative one conducts with the current flowing in the negative half. As described. in which case the converters would be shortcircuited. Kharagpur 6 www. the sum of their firing delay angle must be 180° (π ) . but their output voltage waveforms as a function of time are. the reactor is inserted to limit the circulating current. different. both the converters would conduct at a time.4. with the average value along with the sign. when the current is in the positive half of the cycle. In other words. the main converter − positive/negative. there is a net potential difference (voltage) across two converters. wherein only one of two bridge converters conducts at a time.com . and as a result.www. as the case may be. but not both. 30. Circulating Current Mode of Operation In all the cases described earlier (Lesson 29 and current one (#30)).jntuworld. But.

because six pulses are used in a cycle for the earlier one. At the higher levels of load current. 2 & 3.. Cyclo-converter. so that continuous load current with a better waveform can be maintained. This inductance acts as the filter for the output (load) current.e. The ripple frequency is 150 Hz.jntuworld. It may be noted that harmonic content. when the cyclo-converter is operating in the non-circulating current mode. circulating current one. the groups would be blocked to prevent circulating current. using two three-phase half-wave converters. allowing firing pulses to each group at low current level.com respectively. So. would only be used. as compared to one used in the earlier case. using two three-phase half-wave converters A three-phase to single-phase cyclo-converter. 1. 30. B & C. is higher than those present in the earlier case using two three-phase full-wave bridge converters. needing a total of 12 devices. Each thyristor conducts for around 120° ( 2 ⋅ π / 3) . 2 & 3 are connected to the phases.e. then these firing angles must be controlled so as to satisfy the condition (α p + α n ) = 180° (π ) . whether it is P-type or N-type. This means that the cost is much lower. 30. Also three thyristors are used in each converter.e. The principle of operation is same here as described earlier. It may be noted that the thyristors. A.5.4: Cycloconverter (circulating current mode) with Inter-group(IG) reactor The continuous current of each group in the circulating current mode imposes a higher loading on each group compared to the non-circulating current mode of operation. In practice. as shown in Fig. as also the control circuit in this Version 2 EE IIT. whereas earlier. when the load current is low. three times the input frequency of 50 Hz. but blocking firing pulses to one or the other group at the higher current levels. thus permitting a smaller one. 1. i.com . The mode of operation here is non-circulating current one.jntuworld. IG reactor iP a b P1 3-phase A ac B supply C P4 P6 P2 P3 P5 l o a d iN c N1 N3 N5 A 3-phase B ac C supply + iO - N4 N6 N2 Fig. both in the output voltage and current waveforms. respectively. The reactor would be designed to saturate at higher current levels. Control circuits would be used to sense the level of the load current. Kharagpur 7 www. This is. the ripple frequency being 300 Hz. in series with the load impedance. as this converter is a three-pulse one. is shown in Fig.www. the inductance in the inductive (R-L) load must be high. 30. to make the current continuous. with the thyristors in each converter triggered in sequence. this mode. six thyristors are used for each bridge converter. i. i.5. a total of only 6 devices for two converters are needed.

or may be drawn from the waveforms given in . firstly. is given. as only three pulses per each converter are needed. using two three-phase full-wave bridge converters. The non-circulating current mode of operation is presented in detail. Lastly. Other conditions. If it is used to drive ac motors. being same. stating briefly the differences for this case. with two threephase half-wave converters. 30.www. which is given in standard text book. so as to obtain sinusoidal output voltage waveform. as described in this lesson. the circuit for the same type of cyclo-converter. A B C 3-phase supply A B C 3-phase supply P1 P2 P3 + L o a d N1 N2 N3 Fig. the three-phase to three-phase cyclo-converter will be taken up first. as only the harmonic content is more. Version 2 EE IIT. the high impedance at the ripple frequency is expected to make the output current near sinusoidal one.5: Three-phase to single phase cycloconverter (two three-phase half-wave converter) In this lesson. with the circuit and various output voltage and current waveforms. are needed in this case. and the waveforms also not shown. are not described here. Lastly. This may be preferred. along the change in the circuit.jntuworld. which may not be a demerit in most of the applications. Three such circuits. the three-phase to single-phase cyclo-converter. the analysis of the cyclo-converter output wave-forms will be presented.jntuworld.com case is much simpler and cheaper.com . with the result that no additional filtering component is needed.the earlier case. The circulating current mode is briefly discussed. is described. In the next lesson. Kharagpur 8 www.

com .com Module 4 AC to AC Voltage Converters Version 2 EE IIT. Kharagpur 1 www.www.jntuworld.jntuworld.

jntuworld.jntuworld.com . Kharagpur 2 www.www.com Lesson 31 Three-phase to Threephase Cyclo-converters Version 2 EE IIT.

using six three-phase half-wave thyristorised converters The operation of the above cyclo-converter circuit The analysis of the cyclo-converter output waveform Introduction In the last lesson − second one in the second half of this module. and the same type of cyclo-converter. conduct at the same time. Keywords: Three-phase to three-phase cyclo-converter. The mode of operation is non-circulating current one. The total number of thyristors used is 18. using six three-phase half-wave thyristorised converters (two per each phase). The operation of the above cyclo-converter circuit is briefly discussed. In Fig. where the total cost may be justified. stating mainly the merits. in which only one converter is conducting at a time. 31. the reactors are not needed. firstly. Inter-group reactor in each phase as shown. firstly. if non-circulating current mode of operation is used. Kharagpur 3 www. three times the input frequency of 50 Hz. This has also been discussed in the last section of the previous lesson (#30). The following are briefly presented − the circulating current mode of operation with both converters conducting at a time. with three thyristors for each bridge. with six thyristors as power switching devices in each bridge.1. The ripple frequency is 150 Hz.jntuworld.1. 31. using two three-phase half-wave converters. are needed here. This may be used. is needed here. In this lesson − the third one in the second half. Two three-phase full-wave bridge converters (rectifiers) connected back to back. the circuit and the operation of the three-phase to single-phase cyclo-converter. The mode of operation is the non-circulating current one. the three-phase to three-phase cycloconverter circuit. The procedure for obtaining the expression for the output voltage (rms) per phase for cyclo-converter is described. is described. in which both (positive and negative) converters in each phase. as described later. Version 2 EE IIT.com Instructional Objectives Study of the following: • • • The three-phase to three-phase cyclo-converter circuit. are used. But. along with the merit stated. and also of control circuits needed to generate the firing pulses for the thyristors. the analysis of the cyclo-converter output waveform is presented.jntuworld.www. Two threephase half-wave (three-pulse) converters connected back to back for each phase. the circulating current mode of operation is used. Output waveform analysis Three-phase to Three-phase Cyclo-converter The circuit of a three-phase to three-phase cyclo-converter is shown in Fig. but is more costly. This may be compared to the case with 6 (six) threephase full-wave (6-pulse) bridge converters. where only one converter (positive or negative) in each phase. are described in detail. having six thyristors for each converter. Though this will reduce the harmonic content in both output voltage and current waveforms. Three-phase half-wave converters. Lastly. with both resistive and inductive loads. conducts at a time. with total devices used being 36. thus reducing the cost of power components.com .

com . but lag by the angle. respectively.120° and 240° . 30. each phase conducts for ( (2 ⋅ π ) / 3 = 120° ) radians in a cycle of Version 2 EE IIT. the neutral connection is not necessary.jntuworld. after which the next (incoming) thyristor is triggered. and may be omitted. to be fed to the three-phase load. The firing sequence of the thyristors for the phase groups. With a balanced load. a balanced three-phase voltage is obtained at the output terminals. This is necessary for obtaining reasonable power output.com A B C 3-φ supply P N Phase A P N Phase B P N Phase C 3-phase load Fig. 31. the output voltage waveform is improved.5. An m-phase converter circuit is assumed in which each phase conducts for ( (2 ⋅ π ) / m ) electrical radians in one cycle of supply (input) voltage. the harmonic distortion in the output voltage increases. half-wave (three-pulse) converter (m = 3). limited to about one-third of it ( f 0 = f i / 3 ). because its waveform is composed of fewer segments of the supply voltage. Kharagpur 4 www. thereby suppressing all triplen harmonics. efficiency and harmonic content. whereas its frequency is varied by changing the time interval ( T / 3 = 1 /(3 ⋅ f 0 ) ). Normally. Thus.1: Three-phase to three-phase cycloconverter It may be noted that the circuit in each of the three phases is similar to the cyclo-converter circuit shown in Fig. For example. If the output frequency is to be increased. By using more complex converter circuits with higher pulse numbers. the output frequency of the cyclo-converter is lower than the supply (input) frequency (step-down region). with the maximum useful ratio of output to input frequency is increased to about one-half. Thus.jntuworld. Analysis of the Cyclo-converter Output Waveform An expression for the fundamental component of the phase voltage (rms) delivered by the cyclo-converter is obtained by the procedure given here. the losses in cyclo-converter and also in ac motor become excessive. The average value of the output voltage is changed by varying the firing angles ( α ) of the thyristors. B & C are same as that for phase group A. in a three-phase.www.

the average voltage is E dc = E d 0 ⋅ cos α . 31. E dc has the maximum value of ⎛ m⎞ ⎛π ⎞ E d 0 = 2 ⋅ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟ ⎝π ⎠ ⎝ m⎠ If the delay angle in the cyclo-converter is slowly varied as given earlier.jntuworld. then the peak output voltage for firing angle of 0° is. ⎛ m⎞ ⎛π ⎞ 2 ⋅ E 0 r = E d 0 = 2 ⋅ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟ ⎝π ⎠ ⎝ m⎠ ⎛m⎞ ⎛π ⎞ or.www. Assuming continuous conduction. the conduction period is from ( − (π / m) + α ) to ( (π / m) + α ). When the firing delay angle is α = 0° . the total conduction period is ( (2 ⋅ π ) / m ). If E 0 r is the fundamental component of the output voltage (rms) per phase for the cycloconverter. E ph = Supply voltage per phase (rms). in a three-phase. is shown in Fig. Similarly. (. Kharagpur 5 www. or α p = 180° − α n .2: Output voltage waveform for m-phase converter with firing angle α From Fig. With the time origin. This ignores the rapid fluctuations superimposed on the average low frequency waveform. α p cannot be reduced to zero ( 0° ). the output phase voltage at any point of the low frequency cycle may be calculated as the average voltage for the appropriate delay angle. the conduction period of the periodic waveform is ( (2 ⋅ π ) / 6 = π / 3 = 60° ) radians in one cycle. it can be observed that the conduction period is from ( − π / m ) to ( π / m ). inverter firing cannot be delayed by 180° . It may be noted that the firing delay angles of the two (positive and negative) converters are related by ( α P + α n = 180° ).2. full-wave (six-pulse) converter (m = 6). because sufficient margin Version 2 EE IIT. E0 r = E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟ ⎝π ⎠ ⎝ m⎠ However. the firing angle of the positive group.com ( 2 ⋅ π ) radians.π/m + α) α Ec P′ Em . From the above cases. The average value of the output voltage is. ((π / m ) +α ) ⎛ m ⎞ ⎛ m⎞ ⎛π ⎞ E dc = ⎜ ⎟⋅ ∫m)+α2) E ph cos ω t d (ω t ) = 2 E ph ⋅ ⎜ π ⎟ ⋅ sin ⎜ m ⎟ ⋅ cos α ⎝ 2 ⋅ π ⎠ ( − (π / ⎝ ⎠ ⎝ ⎠ This expression is obtained for dc to ac converter in module 2. 31. PP′ taken at the peak value of the supply voltage. For the firing delay angle α .jntuworld.2. for this value corresponds to a firing angle of ( α n = 180° ) in the negative group.π/m P π/m 2π/m ωt (π/m + α) Fig. and also available in text book. 31. The output voltage waveform for an m-phase converter with firing delay angle α .com . the instantaneous phase voltage is given by e = E m cos ω t = 2 E ph cos ω t where. In practice. if the firing delay angle is α = 0° .

with circuits and waveforms. connected back to back. Consequently. Version 2 EE IIT. the output voltage is lower than the theoretical value obtained earlier. the maximum output voltage per phase is. and thereby reducing the range of variation of α about the value of 90° . firstly.www. Thus. Kharagpur 6 www. The procedure for obtaining the expression for the output voltage (rms) per phase for cyclo-converter is described. in brief. r = cos α min . Six three-phase half-wave converters are used in this case. Lastly. i. The functional blocks. E0 r can be reduced. will be presented. and a static method of voltage control is obtained. the circuit. A total of 18 thyristors are needed as power switching devices. where. of the three-phase to three-phase cyclo-converter. the output voltage. and the operation. E 0 r = r ⋅ ⎢ E ph ⋅ ⎜ ⎟ ⋅ sin ⎜ ⎟⎥ ⎝π ⎠ ⎝ m ⎠⎦ ⎣ Since α min is necessarily greater than zero. In the next. having three thyristors for each converter. the delay angle of the positive group cannot be reduced below a certain finite value.com .jntuworld. as given in module 2. By deliberately increasing α min . the expression for the output voltage (rms) per phase for a threephase to three-phase or a three-phase to single-phase cyclo-converter given earlier is obtained.com must be allowed for commutation overlap and thyristor turn-off time. and is called the ‘voltage reduction factor’. In this lesson. Thus. the complete control circuit for the three-phase to three-phase cyclo-converter. In practice. α min .jntuworld. will be described.e. due to the influence of the commutation overlap and the circulating current between the positive and negative groups. the voltage reduction factor is always lower than unity. is described. with two converters. Edc (max) = Ed 0 ⋅ cos α min = r ⋅ Ed 0 . per phase. last lesson of this module on ac to ac voltage converters. the analysis of the output waveform for the cyclo-converter is presented. Therefore. the expression for the fundamental component of the phase voltage (rms) delivered by ⎡ ⎛m⎞ ⎛ π ⎞⎤ the cyclo-converter is.

jntuworld. Kharagpur 1 www.www.com .jntuworld.com Module 4 AC to AC Voltage Converters Version 2 EE IIT.

Kharagpur 2 www.jntuworld.jntuworld.www.com Lesson 32 Control Circuit for Threephase to Three-phase Cyclo-converters Version 2 EE IIT.com .

are described in brief. the analysis of the output waveform is presented. The functional block diagram of the control circuit for the three-phase to three-phase cyclo-converter. properly shaped. 32. is presented in detail. functional blocks. using six such converters having a total of 18 thyristors. including the circuit and waveforms Introduction In the last lesson − third one in the second half of this module. but the block designated as converter group selection will not be present in this case. per phase.1.jntuworld. Control Circuit for Cyclo-converters The function of the control circuit used in this case is to deliver correctly timed. Keywords: The control circuit for the three-phase to three-phase cyclo-converter. The function of the various blocks. The mode of operation is non-circulating current one. is described. thus. Kharagpur 3 www. to generate the firing pulses for the thyristors The functional blocks. with their respective functions. Two threephase half-wave converters. with three thyristors as power switching devices in each converter.jntuworld. In this lesson − the fourth and final one in the second half. Lastly. firstly. in which only one converter is conducting at a time. 1. showing how the firing pulses are generated to trigger the thyristors.www. the circuit along with the operation of the three-phase to three-phase cyclo-converter.com Instructional Objectives Study of the following: • • The control circuits used for the three-phase to three-phase cyclo-converters using two threephase converters. is shown in Fig. The same control circuit is applicable to the cyclo-converter operating in circulating current mode.com . the complete control circuit for the three-phase to three-phase cyclo-converter. so as to generate a voltage of desired wave shape at the output terminals of a cycloconverter. are needed. firing pulses to the gates of the thyristors in the power converter (rectifier/inverter) circuits. 3. and also circuit diagrams as needed. 4. Synchronising circuit Reference voltage sources Logic and triggering circuit Converter group selection circuit Version 2 EE IIT. in the non-circulating current mode of operation. There are four functional blocks in the circuit as given here. 2.

f c & f d are mixed to Version 2 EE IIT. To determine the instants at which the firing signals are to be produced. wherein two signals having frequencies. the modulating signals are compared with the reference voltages. These low voltage signals must be synchronised to the voltages applied to the main power circuit. eOB & eOC . to be fed to the gates of the thyristors in the two converter groups.jntuworld. 32.1 Control circuit block diagram for a cycloconverter with non-circulating current mode Synchronising Circuit The main function of the synchronising circuit is to derive low voltage signals to the control circuit. variable voltage sine wave reference voltage can be designed in various ways.com Synchronizing and modulating signals e er P-converter e Reference signals Logic and trigger circuit e0 Load i0 N-converter er Converter group selection i0 Fig. the phase shifting network may also be required. The three-phase variable frequency. one-third of the 3 line frequency of 50 Hz (may be higher (25 Hz) in some case). In the case of three-phase to three-phase cyclo-converter.jntuworld.www. if the amplitude and frequency of the reference signal is varied. then the amplitude and frequency of the output voltage varies automatically. which operates at low voltages. normally limited to 16 2 Hz. if any. the reference signal does additional function of shifting eOA . one of the design approach as given here. As the frequency of the reference voltage signal is low. Reference Voltage Sources The reference signal is designed to control the output voltage in the sense that the output voltages tend to follow the reference signal. It means that. Step-down transformers may be used for this purpose with the filter circuit to avoid waveform distortion.com . Kharagpur 4 www. by phase shift of 120° . is to use a mixer. While deriving the modulating voltages at the supply frequency.

Em is the peak of the cosine modulating wave. where. i. Version 2 EE IIT. Kharagpur 5 www. erb = r ⋅ E m sin (2 π ( f c − f d ) t − 120°) . The fixed frequency oscillator ( f c ) produces three outputs ( φ1 . From the above equations. square wave ( φ A .2 Reference voltage generator block diagram. era = r ⋅ Em sin (2 π ( f c − f d ) t ) . φ B & φC ) of frequency f d . The reference voltage generator block diagram is shown in Fig. The details are as follows.fd era fc . and also eliminate the high frequency one ( f c + f d ). a low pass filter is used to obtain a signal of required frequency. 32. the output signal has only two frequencies. as given earlier. which is then fed to a threestage ring counter. ( f c − f d ). the three reference signals obtained are in the form. If all higher order higher harmonics are neglected.www. An astable multivibrator is used to generate a square wave with frequency.fd erc Mixer 2 fc ± fd fc ± fd Low pass filter Low pass filter fc . a low pass filter is used to select the low frequency signal ( f c − f d ). Then.2. Three mixers − one for each phase. 32. consisting of a fundamental and a series of odd harmonics. as stated earlier. ( 3 ⋅ f d ). The output of each mixer stage is a square wave with half-wave symmetry. The amplitude is varied by changing r from 0 to 1. whose output is three numbers of three-phase. erc = r ⋅ Em sin (2 π ( f c − f d ) t + 120°) .com . which may be taken as three-phase. are used to combine the fixed and variable frequencies. it can be observed that the amplitude and frequency of the reference waveforms are controlled by varying r and f d respectively. Then.com obtain frequencies ( f c ± f d ).jntuworld.jntuworld. while the phase sequence of the three-phase outputs is controlled by setting f d . sum or difference of the fixed and variable frequencies.e. φ 2 & φ 3 ). φA fd Mixer 1 Variable frequency Astable multivibrator Ring counter fc φB fd fc fd φC Mixer 3 fc ± fd Low pass filter fc . greater or lower than f c . at a phase shift of 120° . Finally. 1 ≤ r ≤ 0 .fd erb fc φ3 Fixed φ2 frequency φ1 oscillator (fc) Fig.

com .com era ea + Comp.C. 7 TP1 1' CPG 4' JK FF CLR AND DC 7' TN1 erb eb + Comp. and high frequency modulation. - 1 CPG 4 JK FF CLR AND D. - 2 CPG 5 JK FF CLR AND DC 8 TP2 CPG = clock pulse generator 2' CPG 5' JK FF CLR AND DC 8' TN 2 erc ec + Comp. - 3 CPG 6 JK FF CLR AND DC 9 TP3 3' CPG 6' JK FF CLR BC AND DC 9' TN 3 era = reference voltage for phase and output ea. amplification.www. BC = group selection and blanking circuit logic Fig.3 Block diagram of logic and trigger circuit Version 2 EE IIT.jntuworld. 32. ec = modulating signals Comp. Kharagpur 6 www. = comparator DC = driver circuit consisting of pulse isolation.jntuworld. eb.

com .www.3) are shown in Fig. The pulse output of the flip-flop is ANDed with the input coming from the blanking circuit. ea . With the circulating current mode of operation. The typical waveforms at different points of the logic and triggering circuit (Fig. eb and ec . erb . Kharagpur 7 www.3. These pulses drive clock-pulse generator ( c p ).com Logic and Triggering Circuit The block diagram of the main logic and triggering circuit for the output of phase A. This is taken care of by using an inverter at the output of each comparator (Fig. Version 2 EE IIT. Hence. no blanking circuit is needed. The comparators produce short pulses. This limits the presence of pulses only when that thyristor is supposed to conduct. are used for the other two phases. and the other with the reference voltage. For the negative converter. 32. Two similar blocks − one with the reference voltage. otherwise pulse is blocked. 4′ . The basic principle of the co-sinusoidal modulation is the same as that of cosine wave crossing-pulse timing control employed for firing of the thyristors in phase-controlled converters given in standard text books. 5. is shown in Fig. different modulating signals have to be taken into account. This clearing is done in the sequence. 6′ ). erc . The block diagram of the logic circuit is general in the sense that the reference signals and modulating signals could be of any wave-shape. these short pulses act as clock pulses to the flip-flops. The same procedure can be followed for developing the output voltage of the other half cycle of the positive converter. which amplifies and isolates the pulses and drives the respective thyristors. The reference voltage. 5′ . six pulses are obtained (4. 32. in the case of a three-phase to three-phase cyclo-converter circuit. Now. corresponding respectively to the supply voltages. which is a positive edge-triggered mono-stable multi-vibrator.jntuworld. the sinusoidal reference signals and co-sinusoidal modulating signals are commonly employed. e A . The output of the AND gate is given to the driver circuit. 6. this input may be set at the logic ‘1’ permanently. 32. In most applications. e B and eC . The clearing of the pulses is done. when they are not required. 6 → 5 → 4. era . era is compared with the modulating voltages.4. using the reference voltage.jntuworld.3). B & C of the output. The waveforms are drawn for one half cycle of the output voltage for the positive converter with load having unity power factor. 32. Therefore.

32. (a) supply voltage of a three-phase half-wave (three-pulse) cycloconverter showing output voltage of one half cycle. 32. (b) modulating signals for positive converter and reference voltage (100%).www.com .com eA eB eC eA eB eC eA eB eC eA eB 0 θ = ωt (a) 0 θ = ωt 1 2 3 0 0 0 4 5 6 0 0 0 7 8 9 0 0 0 (b) (c) (d) (e) Fig.jntuworld. (c) outputs of comparators used in 8 Version 2 EE IIT. Kharagpur the positive group.3) for one phase only. (d) clock pulse for positive group (e) gate pulses to thyristors. www.4 Various waveforms of logic circuit (Fig.jntuworld.

The result of this is to further distort the output voltage. The delays are not introduced in some control schemes. some distortion in the output voltage is to be tolerated. some operational difficulties. 32. where a small circulating current is permitted during the cross-over instants of the fundamental current only. There are. in the design of filter components specially. The fundamental component of the load current is extracted. when the cyclo-converter is required to operate over a range of the output frequency. 32. and the possible steady state discontinuous conduction within the fundamental period does not cause any erratic switching of converters. the envelope distortion of the output current and the output voltage are reduced. If the group selection and blanking circuit were to operate at each current zero instant. The load current is allowed to flow through the P-converter or the N-converter through suitable logic. however. and with variable load. if no circulating current is permitted to flow. when the load current is positive. Since the actual load voltage waveform itself is far from sinusoidal. and the negative converter is operated. In order to eliminate the waveform distortion. Version 2 EE IIT. The scheme is still recognized as the noncirculating current operation since during a major portion of the output cycle.com Circuit for Converter Group Selection The block diagram of the converter bank selection is shown in Fig. and the converter bank selection is made to occur at the zero crossings of this fundamental component of the current. D Logic D N-converter P-converter i0 Fig. The positive converter is operated. Depending upon load circuit parameters and converter pulse number. Because of filters. which operates satisfactorily over the desired range of frequency. However. will have to be used. Kharagpur 9 www. The converter group selection is not straight forward primarily due to non-ideal nature of the output current waveform.5. The presence of circulating current is a must in such a design. when the load current is negative. The function is to ensure that only one converter operates at a time depending upon the polarity of the current. One possible solution to this problem is to see that the blanking circuit operates at the zero crossing of the fundamental current.com . The filter. it operates in the non-circulating current mode. certain amount of circulating current may be allowed to flow during this short overlap period in some control schemes.www. certain amount of phase shift may be introduced between the zero crossings of the fundamental output current and actual load current.5 Converter group selection in non-circulating current scheme The circuit is an essential part of the control scheme of a cyclo-converter with the noncirculating mode of operation. the load current is also non-sinusoidal. D is the delay during which period the firing pulses to both the converters are inhibited. the load current may become zero before the fundamental half-period.jntuworld. it may cause erratic switching of converters. This distortion arises due to the delays introduced at the zero crossings of the load current to ensure turn-off of thyristors in the outgoing group before the thyristors in the incoming group are turned on.jntuworld. Thus.

com There may be other approaches. stating how the triggering signals for the thyristors are generated. This is not described here. the complete control circuit used for three-phase to three-phase cyclo-converter is discussed in detail. but may be studied from the text books.www. The functional blocks.com . with relevant points. i. last module of the course on Power Electronics.jntuworld. In the next.jntuworld. Version 2 EE IIT. Kharagpur 10 www. will be presented. also known as inverters. in one of which a closed loop control of the output voltage is used to automatically select the converter banks. In this lesson − last one in this module.e. the various types of dc to ac converters. with relevant circuits and waveforms. are described.

com . Kharagpur 1 www.com Module 5 DC to AC Converters Version 2 EE IIT.jntuworld.jntuworld.www.

www.com .jntuworld. Kharagpur 2 www.com Lesson 33 Introduction to Voltage Source Inverters Version 2 EE IIT.jntuworld.

Shape of voltage waveforms output by an ideal VSI should be independent of load connected at the output. the inverter is called a voltage source inverter (VSI). ‘inverter’ is referred as a circuit that operates from a stiff dc source and generates ac output. Even though input to an inverter circuit is a dc source.com . where the input to the circuit is a current source.jntuworld. Explain the principle behind dc to ac conversion.1 How to Get AC Output From DC Input Supply? Figs. which may consist of several cells in series-parallel combination. The achievable magnitude of ac voltage is limited by the magnitude of input (dc bus) voltage.] The simplest dc voltage source for a VSI may be a battery bank. In ordinary household inverters the battery voltage may be just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts (rms) only. Most of us are also familiar with commercially available inverter units used in homes and offices to power some essential ac loads in case the utility ac supply gets interrupted. [The nomenclature ‘inverter’ is sometimes also used for ac to dc converter circuits if the power flow direction is from dc to ac side. In order to have a single control signal Version 2 EE IIT. Kharagpur 3 www. using transistor-switches. If the input dc is a voltage source. say. Identify the basic topology of single-phase and three-phase inverters and explain its principle of operation. In such cases the inverter output voltage is stepped up using a transformer to meet the load requirement of. it is not uncommon to have this dc derived from an ac source such as utility ac supply. An ac voltage supply. In both the circuits. battery supply is used as the input dc voltage source and the inverter circuit converts the dc into ac voltage of desired frequency. for generation of ac voltage from dc input supply. A voltage source is called stiff.1(a) and 33. The word ‘inverter’ in the context of power-electronics denotes a class of power conversion (or power conditioning) circuits that operates from a dc voltage source or a dc current source and converts it into ac voltage or current. the transistors work in common emitter configuration and are interconnected in push-pull manner.jntuworld.www. One can similarly think of a current source inverter (CSI). Explain the gate drive circuit requirements of inverter switches. 33. for example. the primary source of input power may be utility ac voltage supply that is ‘converted’ to dc by an ac to dc converter and then ‘inverted’ back to ac using an inverter. the final ac output may be of a different frequency and magnitude than the input ac of the utility supply. after rectification into dc will also qualify as a dc voltage source. However in this lesson. 230 volts. All voltage source inverters assume stiff voltage supply at the input. The ‘inverter’ does reverse of what ac-to-dc ‘converter’ does (refer to ac to dc converters).1(b) show two schematic circuits. 33. Here.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the essential components of a voltage source inverter. irrespective of power flow direction. The VSI circuit has direct control over ‘output (ac) voltage’ whereas the CSI directly controls ‘output (ac) current’. adjustable speed drives (ASD) for ac motors. electronic frequency changer circuits etc. Thus. if the source voltage magnitude does not depend on load connected to it. Solar photovoltaic cells can be another dc voltage source. In such inverter units. Some examples where voltage source inverters are used are: uninterruptible power supply (UPS) units.

33. the load current can be seen to follow the applied base signal. 33. one transistor is of n-p-n type and the other of p-n-p type and their emitters and bases are shorted as shown in the figures.1(b) is rectangular with magnitude +E when the n-p-n transistor is on and –E when p-n-p transistor is on.1(a). which has been assumed resistive.www. is identical to the sinusoidal output voltage of Fig. Load. the transistors work in active (amplifier) mode and a sinusoidal control voltage of desired frequency is applied between the base and emitter points. Under the assumption of constant gain (hfe) of the transistor over its working range. A suitable resistor in series with the base signal will limit the base current and keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than the base to emitter conduction-voltage drop. 33.2(b). As can be seen.com for the transistor switches. shown in blue color. Collector of n-p-n transistor is connected to positive dc supply (+E) and that of p-n-p transistor is connected to negative dc supply of same magnitude (-E). the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by adopting proper switching pattern.com .2(a). Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains reverse biased. The fundamental sine wave in Fig.jntuworld. Accordingly the base magnitudes of current and power are E/R and E2/R respectively.2(b) shows one such waveform (in pink color). the amplifier circuit is not acceptable in power-electronic applications due to high switch power loss. This particular figure also shows the switch power loss for n-p-n transistor (in brown color). Both amplifier mode and switched mode circuits of Figs. 33.1(b) works in switched mode. the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the load resistance (R). These high frequency voltage harmonics can easily be blocked using small size filter and the resulting quality of load voltage can be made acceptable. When applied base signal is positive. Kharagpur 4 www. the switched mode circuit generates significant amount of unwanted harmonic voltages along with the desired fundamental frequency voltage. The quantities in Fig. As will be shown in some later lessons. 33. The other transistor will also be dissipating identical power during its conduction. As against the amplifier circuit of Fig. 33. is connected between the emitter shorting point and the power supply ground. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms. 33. The on and off durations of the two transistors are controlled so that (i) the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal) component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic voltages are much higher than that of the fundamental component.1(a). 33. On the other hand.1(a) and 33. 33. The conducting switch remains fully on having negligible on-state voltage drop and the non-conducting switch remains fully off allowing no leakage current through it. In Fig.jntuworld.1(b) are capable of producing ac voltages of controllable magnitude and frequency. the circuit of Fig. however. Fig. Fig. Both circuits require a symmetrical bipolar dc supply. Version 2 EE IIT. the power loss in switches is a considerable portion of circuit’s input power and hence such circuits are unacceptable for large output power applications. The load voltage waveform output by switched-mode circuit of Fig.

jntuworld.1 (a): A push-pull active amplifier circuit -E Fig. Kharagpur 5 www.com .1 (b): A push-pull switched mode circuit Version 2 EE IIT. 33.com +E +E S * LOAD (R) * S LOAD (R) -E Fig. 33.jntuworld.www.

Thus it turns out that for a non-resistive load the switches in the circuit of Fig. the mechanical switch can block both positive and negative voltage across its terminals. Thus.3(a)) suffices for the inverter application as pointed out in the following paragraphs. the current must enter the star (*) marked terminal of the load and this same terminal will get connected to the positive dc supply (+E). For a general load the instantaneous current polarity may be different from instantaneous load-voltage polarity. It may be noted that both IGBT and BJT type transistors. the combination can conduct a bi-directional current. 33. However. 33. 33. as shown in Fig. Transistors used in the circuit of Fig. the output voltage is essentially load-independent. As pointed out in section 33. The push-pull circuit operation is now revisited using bi-directional current carrying switches. and may not be suitable for present application. qualify as bi-directional current carrying switches.1(b) are meant to carry only unidirectional current (from collector to emitter) and thus if the upper (n-p-n) transistor is on. 33. The mechanical switch can be subjected to bi-directional voltage. The modified circuit is shown in Fig. When n-p-n transistor turns off and pn-p type turns on.com . in the range of kilohertz. the inverter switching-pattern fixes the output waveform irrespective of the load.] If an anti-parallel diode is connected across each transistor switch. 33. When applied voltage polarity is reversed the diode starts conducting and so the switch is not able to block the flow of reverse current.3(a). [A mechanical switch realized using an electromagnetic contactor is one example of the bi-directional current carrying controllable switch.com The magnitude. 33. The electronic switch of Fig. When off. Thus the magnitude. the load voltage and current polarities reverse simultaneously (p-n-p transistor can only carry current coming out of star marked end of load). phase and frequency of the fundamental voltage output by a VSI is independent of the nature of load. when bypassed by anti-parallel diode. 33. Under this polarity of voltage the switch can remain off as long as the base (or the gate) terminal is not given the turn-on signal. other load terminal being at ground potential.] In spite of unidirectional voltage blocking capability.www.3(b).1(b) should be able to carry bidirectional current and at the same time be controllable. phase and frequency of the fundamental voltage waveform in Fig. the new electronic switch (similar to the one shown in Fig.jntuworld. 33.1(b). Now the transistor in anti-parallel with the diode may be considered as a single switch.jntuworld. as long as the transistors work in the switch-mode (fully on or fully off). [A major difference exists between this bidirectional electronic switch and a bi-directional current carrying mechanical switch.1(b) will not be able to output proper voltage waveform for a non-resistive load for the reasons mentioned below. Kharagpur 6 www.1. 33. the one that keeps the diode reverse biased.2(b) is solely determined by the magnitude of supply voltage and the switching pattern of the push-pull circuit shown in Fig. However electromagnetic contactors are not capable of operating at high frequency. Such one to one matching between the instantaneous polarities of load voltage and load current can be achieved only in purely resistive loads.2 What If The Load Is Not Resistive? Circuit of Fig. 33. IGBT switch is controlled by gate voltage whereas the BJT Version 2 EE IIT.3(a) can block only one polarity of voltage.

given by its L (inductance) / R (resistance) ratio. As a result BJT switches are becoming obsolete. Thus it will be evident that diodes do not need a separate command to turn on and off. current through such loads cannot change abruptly. through transistor ‘Q1’. 33. 33. In fact turning on of ‘Q1’ will make ‘D2’ reverse biased. This results in ‘SW1’ turning off and ‘SW2’ turning on.] In the circuit of Fig.3(a): Bi-directional controlled switch switch is controlled using base current.3(b). are much faster and are available in higher voltage and current ratings. the upper switch is turned on. By applying positive base-to-emitter voltage of suitable magnitude to transistor ‘Q1’. In the following switching cycle when ‘Q1’ is turned on again (load current direction still unchanged) the load current path reverts back from ‘D2’ to ‘Q1’. when ‘Q1’ is turned-off and ‘Q2’ is turned on (but load current direction remaining unchanged) the load current finds its path through diode of lower switch (D2).3 (b): Modified push-pull circuit Fig. Now ‘SW1’ blocks a voltage of magnitude ‘2E’.jntuworld. Similarly lower switch (SW2) consists of p-n-p transistor (Q2) in antiparallel with diode (D2). As is well known. To illustrate this point some details of circuit operation with an inductive load. Transistor ‘Q2’ is also reverse biased due to application of positive base voltage to the transistors. It may be interesting to see how diodes follow the switching command given to the transistor part of the switches.com +E Input / Output Q1 SW1 D1 LOAD Analogous to Control S Q2 + Gate (control) * D2 SW2 _ Input / Output -E Fig. ‘Q1’ is reverse biased and ‘Q2’ is forward biased. switch ‘SW2’ is off and is blocking voltage of magnitude ‘2E’.3(b). The natural choice for load current is to move from ‘D2’ to ‘Q1’. Kharagpur 7 www.jntuworld. 33. may in general be large compared to the chosen switching time period of the transistor switches. n-p-n transistor (Q1) together with diode (D1) constitutes the upper switch (SW1). is considered. The electrical inertial time constant of the load. Let us consider the time instant when instantaneous load current is entering the star end of the load in Fig. It may not be difficult to see how this happens. voltage drop across ‘SW2’ is virtually zero and it can be considered as a closed or a fully-on switch. When ‘Q1’ conducts the positive (+E) emf supports the load current. Similarly when applied base voltage to the transistors is made negative. The reader may repeat a similar exercise when the instantaneous load current comes out of the star end of load. Thus while switch ‘SW1’is conducting current. Next. to load. Whether ‘D2’ or ‘Q2’ conducts. 33. [IGBT switches are easier to use.www. turning on of ‘Q1’ makes ‘SW1’ on and Version 2 EE IIT.com . Now with the assumed load current direction when ‘Q1’ is given turn-on signal current flows from positive dc supply. Thus the transistors ‘Q1’ and ‘Q2’ may turn-on and turn-off several times before the load current direction changes. Once the upper switch (diode ‘D1’or transistor ‘Q1’) is conducting star end of load is at ‘+E’ potential and diode ‘D2’ of lower switch gets reverse biased. While current flowed through ‘D2’ the load circuit got connected to negative emf (-E) of the supply. Irrespective of the load current direction. consisting of a resistor and an inductor in series.

The circuit in Fig. The second demerit of the push-pull circuit shown in Fig. Kharagpur 8 www. Fig. it needs a bipolar dc supply with identical magnitudes of positive and negative supply voltages. n-p-n transistors are preferred as they can operate at higher switching frequencies. The requirement of splitting a single dc source is eliminated if a full bridge circuit. there may be significant ripple in the capacitor voltages. more than compensated by the improved capability of the circuit that uses both n-p-n transistors or nchannel IGBTs. 33. For practical reasons it would have been simpler if only one (uni-polar) dc source was required. 33.] Two identical capacitors of large magnitude are put across the dc supply and the junction point of the capacitors is used as the neutral (ground) point of the bipolar dc supply.3(b) will work satisfactorily for a purely resistive load and a series connected resistorcapacitor load too. 33. often.3(b) is the requirement of two different kinds of transistors. 33.com similarly turning off of ‘Q1’ (with simultaneous turn-on of ‘Q2’) makes ‘SW2’on. In power electronic applications.www. Also.jntuworld. In such circuits the voltages across the two capacitors may not remain exactly balanced due to mismatch in the loading patterns or mismatch in leakage currents of the individual capacitors. The gate drive signals of the two transistors (IGBTs) now need to be different and isolated as the two emitter points are at different potentials. unless the capacitors are of very large magnitude. ‘Q1’ and ‘Q2’ are turned on in a complementary manner. 33. Version 2 EE IIT. Similarly n-channel MOSFETs and IGBTs are preferred over their p-channel counterparts. one n-p-n type and the other p-n-p type. The base signals for the individual transistors will then need to be separate and isolated from each other. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc voltage-source through capacitive potential divider arrangement. [A resistive potential divider will be terribly inefficient. The switching speeds of np-n and p-n-p transistors are widely different unless they are produced carefully as matched pairs. is used.jntuworld. The difficulty in using two n-p-n transistors in the above discussed pushpull circuit is that they can no longer have a common base and a common emitter point and thus it won’t be possible to have a single base drive signal for controlling both of them. as mentioned in the next section.3(c) shows identical transistors (n-channel IGBTs) for both upper and lower switches. especially at low switching frequencies. It may not be difficult to see that the circuit of Fig. The difficulty in providing isolated base signals for the two transistors is. 33.3(c) is better known as a half bridge inverter. The circuit in Fig.3(c) shows one such circuit where a single dc supply has been split in two halves. The push-pull circuit of Fig.3(b) has some technical demerits that have been discussed below.com . First.

are fast recovery diodes connected in anti-parallel with the switches. A practical dc voltage source may have some resistance as well as some inductance in series with its internal emf. average magnitude of the dc link current remains positive if net power-flow is from dc bus to ac load. [The dc link current may conceptually be decomposed into its dc and ac components.www.jntuworld.4(a) and 33.3 General Structure of Voltage Source Inverters Figs. D2.com . The dc part of bus current is supplied solely by the dc source. The current supplied by the dc bus to the inverter switches is referred as dc link current and has been shown as ‘idc’ in Figs 33.jntuworld. For dc component of bus current. ‘A’. under steady state.3(c): Topology of a 1-phase half bridge VSI 33. 33.5Edc Q1 D1 O + _ LOAD 0. Needless to say that physical layout of positive and negative bus lines is also important to limit stray inductances. The step change in instantaneous dc link current occurs even if the ac load at the inverter output is drawing steady power. As expected. Q3 etc. Capacitors and switches are connected to dc bus using short leads to minimize the stray inductance between the capacitor and the inverter switches. The net power-flow direction reverses if the ac load connected to the inverter is regenerating. For the dc component of current the capacitor acts like open circuit. the capacitor does not supply any dc current. These topologies require only a single dc source and for medium output power applications the preferred devices are n-channel IGBTs. D1.5Edc Q2 A D2 N Fig. D3 etc. Q1. However.com P + _ Edc + _ 0. But for ac component of current. Q2. The magnitude of dc link current often changes in step (and some times its direction also changes) as the inverter switches are turned on and off. A three-phase inverter has three load-phase terminals whereas a single-phase inverter has only one pair of load terminals. 33. Under regeneration.4 (a) and 33. Kharagpur 9 www. the mean magnitude of dc link current is negative. ‘Edc’ is the input dc supply and a large dc link capacitor (Cdc) is put across the supply terminals. are fast and controllable switches. The individual roles of the ‘dc voltage source’ and the ‘dc link capacitor’ may be clearly seen with respect to the dc and ac components of the dc link current.4(b) show the typical power-circuit topologies of a single-phase and a three-phase voltage source inverter respectively.4(b). the source voltage appears in series with its internal resistance (effect of source inductance is not felt). the internal dc emf of source appears as short and its series impedance (resistance in series with inductance) appears in parallel with the dc-link Version 2 EE IIT. ‘B’ and ‘C’ are output terminals of the inverter that get connected to the ac load.

The reason being that for some types of dc sources. in the absence of dc link capacitor. The step change in dc link current is associated with significant amount of high frequency components of current that essentially finds its path through the capacitor. unless this inductance is effectively bypassed by the dc side capacitor. However a practical voltage supply may have considerable amount of output impedance. if not bypassed by a sufficiently large dc link capacitor. It may be mentioned here that an inductance. For such cases it is advantageous if the dc source has some series inductance. it may also cause malfunction of the inverter switches as the bus voltage appears across the non-conducting switches of the inverter. Thus the ac component of current gets divided into these two parallel paths. in series with the dc supply. Also. with no series impedance. Similarly.com . the high frequency component of ac current mainly flows through the capacitor. Even the connecting leads from the dc source to the inverter dc bus may contribute significantly to the supply line inductance in case the lead lengths are large and circuit lay out is poor.] For an ideal input (dc) supply. may cause considerable voltage spike at the dc bus during inverter operation. However.jntuworld. The supply line impedance. The effect of ac line inductance is reflected on the dc side as well. Version 2 EE IIT. the dc link capacitor does not have any role. it is detrimental to carry high frequency ripple current. may at times be welcome. [It may not be possible to reduce supply line inductance below certain limit. This may result in deterioration of output voltage quality.com capacitor.] The dc link capacitor should be put very close to the switches so that it provides a low impedance path to the high frequency component of the switch currents. like batteries. Due to series inductance of the source. The overall layout of the power circuit has a significant effect over the performance of the inverter circuit. as the capacitive impedance is lower at high frequencies. The capacitor itself must be of good quality with very low equivalent series resistor (ESR) and equivalent series inductor (ESL).www. the ac supply line inductance will prevent quick change in rectifier output current. Kharagpur 10 www. the series inductance of the supply line will prevent quick build up or fall of current through it and the circuit behaves differently from the ideal VSI where the dc voltage supply is supposed to allow rise and fall in current as per the demand of the inverter circuit. The length of leads that interconnect switches and diodes to the dc bus must also be minimum to avoid insertion of significant amount of stray inductances in the circuit. for example a conventional dc generator will have considerable armature inductance in series with the armature emf.jntuworld. the high frequency ripple will prefer to flow through the dc link capacitor and thus relieve the dc source. Most dc supplies will inherently have rather significant series inductance. if the dc supply is derived after rectifying ac voltage.

jntuworld.4(a) and 33. 33. Thus the single phase ‘full-bridge’ (often. need to be provided with isolated gate (or base) drive signals. simply called as ‘bridge’) circuit has two legs of switches. when gate to source voltage is more than threshold voltage for turn-on. the switch turns on and when it is less than threshold voltage the switch turns off. each leg consisting of an upper switch and a lower switch.4(a) and 33. However it may be mentioned here that these circuits are essentially extension of the half bridge circuit shown in Fig. 33. The threshold voltage is generally of the order of +5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts Version 2 EE IIT. The gate control signals are low voltage signals referred to the source (emitter) terminal of the switch. are phase apart by 1200 each.4 Need For Isolated Gate-Control Signals For The Switches As already mentioned the switches in bridge configurations of inverters. the single-phase bridge circuit of Fig.3(c). as in Figs. 33. For example. the minimum distance between them being decided only by their voltage isolation requirement. 33.4(b).com .4(b) are discussed in later lessons. 33. Thus the positive and negative terminals of the dc bus should run close by.jntuworld. For n-channel IGBT and MOSFET switches. Voltage between output point of legs and the midpotential of the dc bus is called as ‘pole voltage’ referred to the mid potential of the dc bus.4(b): Topology of a 3-phase VSI [One of the thumb rules for good circuit layout is to put the conductor pairs carrying same magnitude but opposite direction of currents close by. One may think of pole voltage referred to negative bus or referred to positive bus too but unless otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus.4(b). Thus the load connected between these two pole outputs (between points ‘A’ and ‘B’) will have a voltage equal to twice the magnitude of the individual pole voltage.www. 33. Junction point of the upper and lower switches is the output point of that particular leg. 33.3(c). shown in Fig. A twisted wire pair may be an example of two closely running wires. The individual control signal for the switches needs to be provided across the gate (base) and source (or emitter) terminals of the particular switch. 33. Kharagpur 11 www. The two pole voltages of the single-phase bridge inverter generally have same magnitude and frequency but their phases are 1800 apart.4(a): Topology of a 1-phase VSI Fig. 33.com idc D1 D3 Edc LOAD D2 Q4 B D4 idc D1 D3 Q1 Edc Q3 Q1 Q3 Q5 D5 + Cdc _ A Q2 + Cdc _ Q2 A D2 B D4 C D6 Q4 Q6 Fig. The pole voltages of the 3-phase inverter bridge.] The details of the inverter circuits shown in Figs.4(a) may be thought of as two half-bridge circuits sharing the same dc bus.

com where as turn-off gate voltage is zero or little negative (around –5 volts). A signal comparator circuit senses this condition and outputs a high level signal.www. 33. Input stage of the IC is a light emitting diode (LED) that emits light when forward biased. the emitter of upper switch of that leg is virtually at the negative dc bus potential. Only the emitters of lower switches of all the legs are at the same potential (since all of them are solidly connected to the negative dc bus) and hence the gate control signals of lower switches need not be isolated among themselves. Emitters of all the lower switches are solidly connected to the negative line of the dc bus. A high level of the gate signal may be taken as ‘on’ command and a low level (at ground level) may be taken as ‘off’ command. Thus with upper switch ‘on’. In the figure the two grounds have been shown by two different symbols. Gate-signal isolation for inverter switches is generally achieved by means of optical-isolator (opto-isolator) circuits. The light output of the LED falls on reverse biased junction of an optical diode. the emitter of the upper switch is at positive dc bus potential. As a result magnitude of reverse leakage current of the diode increases appreciably. as shown in Fig. When input signal to LED is high. which is amplified before being output. Similarly with lower switch ‘on’.jntuworld. Irradiation of light causes generation of significant number of electron-hole pairs in the depletion region of the reverse biased diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to ensure that the light emitted by the LED falls on the photo-diode junction. The gate control pulses for the switch are applied to the input LED through a current limiting resistor of appropriate magnitude. This calls for isolation between the gate control signals of upper switches and between upper and lower switches. the gate voltages of all the upper switches must be floating with respect to the dc bus line potentials. Fig. is put between the output signal and the gate terminal of the switch). Since gate control signals are applied with respect to the emitter terminals of the switches. The circuit on the output (photo-diode) side is connected to a floating dc power supply.33.jntuworld. The circuit makes use of a commercially available opto-coupler IC. The resistor connected in series with the photo-diode now has higher voltage drop due to the increased leakage current. These gate pulses. generated by the gate logic circuit. When the upper switch of any leg is ‘on’. as suggested by the switch manufacturer. the corresponding lower switch remains ‘off’ and vice-versa. Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate terminal of the switch (often a small series resistor. Version 2 EE IIT. The schematic connection shown in the figure indicates that the photo-diode is reverse biased. Kharagpur 12 www.com . Under this assumption. It is to be remembered that the two switches of an inverter-leg are controlled in a complementary manner. the cathode of the LED is connected to the ground point of the gate-logic card and anode is fed with the logic card output.5. When a switch is ‘on’ its emitter and collector terminals are virtually shorted. shown within dotted lines in the figure. A resistor in series with the diode indicates the magnitude of the reverse leakage current of the diode.5 shows a typical optoisolator circuit. are essentially in the digital form. The control (logic card) supply ground is isolated from the floating-supply ground of the output. LED conducts and the emitted light falls on the reverse biased p-n junction. As should be clear from the above discussion. the isolation provided between upper and lower switches must withstand a peak voltage stress equal to dc bus voltage.

Inverters can also be classified according to their ability in controlling the magnitude of output parameters like.5 Classification of Voltage Source Inverters Voltage source inverters can be classified according to different criterions. Accordingly there are single-phase or three-phase inverters depending on whether they output single or three-phase voltages. in most ac motor loads. Kharagpur 13 www. A diode in anti-parallel with the controlled switch.33. 13th order of the desired (fundamental) frequency voltage.4(a) and 33. harmonic content etc. Higher order harmonic voltage distortions are. frequency. voltage. even if it is at the cost of increased high order harmonics.com +VCC (floating) Photo-diode L E D Signal comparator and power amplifier circuit Output Control Ground Floating Ground Fig. is used in VSI to: (a) prevent reversal of dc link current. (b) to minimize high frequency current ripple through the ideal dc source. is intended to: (a) allow a low impedance path to the high frequency component of dc link current.4(b) are two level inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. filtered away by the inductive nature of the load itself.com .3(c).5: A schematic opto-isolator circuit 33. 11th. For higher voltage applications it may not be uncommon to have three level or five level inverters. 2. They can be classified according to number of phases they output. It is also possible to have inverters with two or five or any other number of output phases. Some inverter topologies are suitable for low and medium voltage ratings whereas some others are more suitable for higher voltage applications. Some inverters can output only fixed magnitude (though variable frequency) voltages whereas some others are capable of both variable voltage. 33. put across dc bus of a voltage source inverter. (d) to protect against switch failure. The inverters shown in Figs.jntuworld. variable frequency (VVVF) output. 5th. Version 2 EE IIT. Output of some voltage source inverters is corrupted by significant amount of many low order harmonics like 3rd.www. (c) to maintain a constant dc link current. Some other inverters may be free from low order harmonics but may still be corrupted by some high order harmonics. Inverters used for ac motor drive applications are expected to have less of low order harmonics in the output voltage waveform.jntuworld. Quiz Problems 1. 7th. like IGBT. A large capacitor. 33. Inverters may also be classified according to their topologies.

jntuworld. (Answers to the quiz problems: 1-a. (b) switches to be connected in bridge fashion. (c) protect the circuit against accidental reversal of dc bus polarity. The inverter switches work in fully-on or fully-off mode to achieve: (a) easier gate control circuit for the switching devices. Gate (base) signals to the VSI switches. need to be isolated to allow: (a) protection of switches against short at the inverter output terminals. 4.jntuworld. 3-c. 4-b) Version 2 EE IIT. (d) none of the above. (c) lower losses in the gate drive circuit. (d) a dc link voltage higher than the switch voltage rating. using n-channel IGBTs. Kharagpur 14 www. 3. 2-b. (d) satisfactory operation for non-resistive load at the output. (c) reduced losses in the switches.www.com .com (b) allow a non-unity power factor load at the output. (b) minimum distortion in the output voltage waveform.

com Module 5 DC to AC Converters Version 2 EE IIT.jntuworld. Kharagpur 1 www.jntuworld.com .www.

Wave Voltage Source Inverter Version 2 EE IIT.jntuworld.jntuworld. Square .www.com . Kharagpur 2 www.com Lesson 34 Analysis of 1-Phase.

As pointed out in Lesson-26. Do harmonic analysis of load voltage and load current output by a single-phase inverter.5Edc Sw2 N Fig. 34.1(b): A 1-phase full-bridge VSI Sw4 A P idc Sw1 Sw3 + Cdc _ A LOAD B In this lesson. 34. it is assumed that the input dc voltage (Edc) is constant and the switches are lossless. The first generation inverters.1(b) for further discussions. In half bridge topology the input dc voltage is split in two equal parts through an ideal and loss-less capacitive potential divider. Kharagpur 3 www.www. Decide on voltage and current ratings of inverter switches. single-phase inverters mostly use half bridge or full bridge topologies.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Explain the operating principle of a single-phase square wave inverter.1(a): A 1-phase half bridge VSI Sw2 N Fig.1(a) these points are marked as ‘O’ and ‘A’ respectively).jntuworld.jntuworld. Power circuits of these topologies are redrawn in Figs. In contrast. P + C_ Edc + _ Sw1 0. 34. Such inverters have very simple control logic and the power switches need to operate at much lower frequencies compared to switches in some other types of inverters. the switches Sw1 and Sw2 may be assumed to Version 2 EE IIT. Accordingly. A single-phase square wave type voltage source inverter produces square shaped output voltage for a single-phase load. Each of these switches consists of an IGBT type controlled switch across which an uncontrolled diode is put in anti-parallel manner. discussed in later lessons. Compare the performance of single-phase half-bridge and full-bridge inverters. both the above topologies are analyzed under the assumption of ideal circuit conditions. the present day switches like IGBTs are much faster and used at switching frequencies of several kilohertz. 34. These switches are capable of conducting bi-directional current but they need to block only one polarity of voltage. For ease of understanding. were almost invariably square wave inverters because thyristor switches could be switched on and off only a few hundred times in a second. The half bridge topology consists of one leg (one pole) of switches whereas the full bridge topology has two such legs. In half bridge topology the single-phase load is connected between the mid-point of the input dc supply and the junction point of the two switches (in Fig. Voltage source inverters (VSI) have been introduced in Lesson-33. Each leg of the inverter consists of two series connected electronic switches shown within dotted lines in the figures.1(a) and 34.5Edc Edc O + C_ LOAD 0. The junction point of the switches in each leg of the inverter serves as one output point for the load. using thyristor switches.com .

jntuworld.5. 34.com be controlled mechanical switches that open and close in response to the switch control signal. 24. one of the switches must always conduct to maintain continuity of load current.1 Harmonic Analysis of The Load Voltage And Load Current Waveforms The load voltage waveform shown in Fig.com . the square wave load voltage consists of all the odd harmonics and their magnitudes are inversely proportional to their harmonic order.where ‘n’ is the harmonic order and w is the frequency (‘f’) of the square wave. For a general load. containing an inductance in series.. As can be seen from the expression of Eqn.2) it has been shown that the actual electronic switches mimic the function of the mechanical switches. Simultaneous turn-on of both the switches will amount to short circuit across the dc bus and will cause the switch currents to rise rapidly.jntuworld.5 Edc when Sw2 is turned on.2(a) can be mathematically described in terms of its Fourier’s components as: 2E VAO = ∑ nπdc sin(nwt ) ……………………………………… (34..2(a) shows a typical load voltage waveform output by the half bridge inverter. In fact in lesson-33 (section 33. if the switches Sw1 and Sw2 are turned on alternately with duty ratio of each switch kept equal to 0. ‘f’ also 2π happens to be the switching frequency of the inverter switches.5 Edc when Sw1 is on and the magnitude reverses to -0. The two switches of the inverter leg are turned on in a complementary π manner.∞ .. In Lesson-33 (section 33. For an inductive load.1.5.2 also shows the fundamental frequency component of the square wave voltage.7. 34. 34.1) n =1. VAO acquires a magnitude of +0. Accordingly. as explained in lesson-33. Such a situation. the fundamental Version 2 EE IIT. Fig. Kharagpur 4 www.. demands that the switches must have bidirectional current carrying capability. Now.www. its peak-to-peak magnitude being equal to 4 Edc . the load voltage (VAO) will be square wave with a peak-to-peak magnitude equal to input dc voltage (Edc).3. the switches should neither be simultaneously on nor be simultaneously off. Fig.2) a case of inductive load has been considered and it has been shown that the load current may not change abruptly even though the switching frequency is very high. 34.

The instantaneous current ‘i’ during the first half of square wave may be obtained by solving Eqn. The circuit equation valid during the positive half cycle of voltage can be written as below: di Ri + L = 0.5T < t < T …………………………………. −t −t 0.1 Time Domain Analysis The time domain analysis of the steady state current waveform for a R-L load has been presented here.(34. where T (=1/f) is the time period of the square wave. The Thus the next half cycle starts with an initial current = R circuit equation for the next half cycle may now be written as i(t ) = − 0. −T −T 0. Kharagpur 5 www. for comparison. In most applications. only the fundamental component in load voltage is of practical use and the other higher order harmonics are undesirable distortions.(34. The current at the end of the positive half cycle becomes the starting current for the negative half cycle. The negative half cycle of square wave starts at t=0.3) dt .………….5Edc .5Edc (1 − e R T −(t − ) 2 τ T −(t − ) −T −T ⎤ 2 ⎡ 0.jntuworld. The current waveforms in such loads have less higher order harmonic distortion than the corresponding distortion in the square-wave voltage waveform.5 Edc . integer) has a peak magnitude of 34. i (t ) = R .(34.5T ……………………….5 Edc (1 − e τ ) + I 0 e τ for 0 < t < 0. Let t=0 be the instant when the positive half cycle of the square wave starts and let I0 be the load current at this instant. where τ= L/R is the time constant of the R-L load. for 0 < t < 0. The magnitudes of very high order harmonic voltages nπ become negligibly small.5T …………….5T <t< T Simplifying the above equation one gets: Version 2 EE IIT. frequency domain analysis of the same load current has also been done. Later.. A simple time domain analysis of the load current for a series connected R-L load has been presented below to corroborate this fact.1.5 Edc (1 − e 2τ ) + I 0 e 2τ . Many of the practical loads are inductive with inherent low pass filter type characteristics.www.5T and extends up to T. Under steady state the load current waveform in a particular output cycle will repeat in successive cycles and hence only one square wave period has been considered.jntuworld.com frequency component has a peak magnitude of 2 π Edc and the nth harmonic voltage (n being odd 2 Edc .. for 0.4) Accordingly.2) and putting the initial value of current as I0.2) dt Similarly the equation for the negative half cycle can be written as di Ri + L = −0.(34.5E dc τ )+⎢ (1 − e 2τ ) + I 0e 2τ ⎥ e ⎢ R ⎥ ⎣ ⎦ for 0.com .

com i (t ) = − −t −t E 0. −t −T ⎡ 0.5 Edc R T ⎡ −(t − ) ⎢ 2 −T ⎢1 + e 2τ − 2e τ ⎢ −T ⎢ 1 + e 2τ ⎢ ⎢ ⎣ ⎤ ⎥ ⎥ ⎥ ..5T < t < T . Thus putting t=T in Eqn.(34.5Edc Edc ⎜ 1 ⎟ = − 0. for 0. I 0 = ⎟ −T −T ⎥ R R ⎜ R ⎢ ⎜ ⎟ ⎢1 + e 2τ ⎥ ⎝ 1 + e 2τ ⎠ ⎣ ⎦ Substituting the above expression for I0 in Eqn..5) Under steady state.7) ⎥ ⎦ It may be noted from Eqn.5E −T ⎞ ⎛ E ⎛ −T dc (1 − e τ ) + dc ⎜ e 2τ − 1⎟ or.. I 0 ⎜1 − e τ ⎟ = ⎟ ⎜ ⎟ R R ⎜ ⎠ ⎝ ⎠ ⎝ −T ⎤ ⎡ ⎛ ⎞ 0. ⎡ T ⎢ −(t − ) 2 ⎢ τ Edc ⎢ e + R ⎢⎛ −T ⎢ ⎜ 1 + e 2τ ⎢⎜ ⎣⎝ ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ i (t ) = − 0..5 Edc ⎢1 + e 2τ − 2e τ i(t ) = −T R ⎢ ⎢ 1 + e 2τ ⎣ ⎤ ⎥ ⎥ .6) or.5).jntuworld. (34..5Edc ⎢1 − e 2τ ⎥ − ………….5).5T ………... for 0..5Edc (1 + e τ ) + I 0 e τ + dc e 2τ I0 = − R R −T ⎞ 0. −T −T E −T 0.5 Edc (1 + e τ ) + I 0 e τ + dc e R R −(t − T ) 2 τ .5T < t < T …….. (34... This is expected from the symmetry of the load voltage waveform.5 Edc R ⎞ ⎟ ⎟ ⎠ . the instantaneous magnitude of inductive load current at the end of a periodic cycle must equal the current at the start of the cycle.. for 0 < t < 0.………. one gets the expression for I0 as.5T < t < T or.com ..7) that the load current at the end of the positive half cycle of square wave (at t=0.jntuworld.. i (t ) = − 0..8) ⎥ ⎥ ⎥ ⎦ Version 2 EE IIT. (34.(34. Kharagpur 6 www.www.5T) simply turns out to be –I0. (34.. for 0.4) one gets.(34. Load current expression for the negative half cycle of square wave can similarly be calculated by substituting for I0 in Eqn. Accordingly. (34.

To illustrate this the series connected R-L load has once again been considered here.2(e).5 dc . It can be seen that the load current waveform repeats at fundamental frequency and the higher order harmonic distortions reduce as the load becomes more inductive. the 3rd order harmonic distortion in the load current together with its fundamental component has been shown in Fig. 34.www. Kharagpur 7 www. The load current may be expressed in terms of these harmonic currents. For L/R ratio of 2.2(b) to 34. 34.com The current expressions given by Eqns.jntuworld. it can be seen that the relative harmonic distortion in load current waveform is much lower than that of the voltage waveform shown in Fig.8) have been plotted in Figs.1. First the expressions for different harmonic components of load current are calculated in terms of load parameters: R and L/R (or τ) and inverter parameters: dc link voltage (Edc) and time period of square wave (T).2(a). 34. The square wave voltage waveform.2 Frequency Domain Analysis The square shape load voltage may be taken as superposition of different harmonic voltages described by Eqn.5Edc has also been plotted together with the current waveforms. Version 2 EE IIT.7) and (34.1. The current waveforms have been E normalized against a base current of 0.com . normalized R against a base voltage of 0. (34.2(e) for different time constants of the R-L load. The basis for calculating the magnitude of different harmonic components of load current waveform has been shown in the next subsection that deals with frequency domain analysis. 34. 34. The load current may similarly be taken as superposition of harmonic currents produced by the different harmonic voltages. In this case.jntuworld.

(34.002sin(7 wt − 1..3.555) (Iload)5. Kharagpur 8 www.normalized = 2 7π 1 + 784π 4 sin(11wt − tan −1 44π ) = 0..11) nπ Z n π Z1 The algebraic summation of the individual harmonic components of current will result in the following expression for load current.0008sin(11wt − 1.jntuworld.(34. Zn = 2 2 2 R 2 + (4π n L 2) T ⎛ 2π nL ⎞ and φn = tan −1 ⎜ ⎟ …….…….011sin(3wt − 1.…….jntuworld.491) (Iload)1. I Load = 2 Edc sin(nwt − Φ n ) ……………………………….12 it may be seen that the contribution to load current from very higher order harmonics become negligible and hence the infinite series based expression for load current may be terminated beyond certain values of harmonic order ‘n’.normalized = 2 5π 1 + 400π 4 sin(7 wt − tan −1 28π ) = 0.normalized = 2 11π 1 + 1936π Version 2 EE IIT.normalized = 2 3π 1 + 144π 4 sin(5wt − tan −1 20π ) = 0.5 Edc have been calculated below: R 4 sin( wt − tan −1 4π ) = 0.normalized = 2 π 1 + 16π 4 sin(3wt − tan −1 12π ) = 0.7.1sin( wt − 1.5.12) n =1.∞ nπ Z n ∑ From Eqns.559) (Iload)7..10 and 34. the individual harmonic components of load current normalized against a base current of 0.004sin(5wt − 1.564) (Iload)11.544) (Iload)3.(34. (Iload)1 and (Iload)n respectively. can be found to be (Iload)1 = 2 Edc 2 Edc sin( wt − Φ1 ) and (Iload)n = sin(nwt − Φ n ) ………(34. For L/R ratio = 2T. 34.10) ⎝ TR ⎠ The fundamental and nth harmonic component of load current.www.9) ⎝ TR ⎠ The load impedance and load power factor angle for the nth harmonic component (Zn and φn respectively) will similarly be given by.com For the fundamental harmonic frequency the load impedance (Z1) and load power factor angle (φ1) can be calculated to be Z1 = 2 2 R 2 + ( 4π L 2) T ⎛ 2π L ⎞ and φ1 = tan −1 ⎜ ⎟ ……….com ..

Taking the phase shift angle ‘Φ’ into account.2(g) the load current waveforms of Fig..5. 34.3 shows these pole voltages staggered in time by ‘t’ seconds. the expressions for which have been given above. 34.5.com It may be concluded that for L/R = 2T. 34..7.3. It may be seen that the load current waveform of Fig.14. 34. have some phase difference.7. 7th and 11th) in the load current.∞ Difference of VAO and VBO gives the line voltage VAB... 34. 34.jntuworld.www. Taking difference of the voltage expressions given by Eqns.13) T . in general.14) n =1.3. the pole-B voltage may be written as 2E VBO = ∑ nπdc sin n(wt − Φ) ………………………………………(34..(34. In full bridge inverter the single phase load is connected between points ‘A’ and ‘B’ and the voltage of interest is the load voltage VAB. Kharagpur 9 www. one gets 2E VAB = ∑ nπdc [sin nwt − sin n(wt − Φ)] ………………………………………(34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics (fundamental.15) n =1. calculated using time domain analysis.2(f) calculated using truncated series of the frequency domain analysis very nearly matches with the exact waveform of Fig. Fig.. The full bridge circuit will have two pole-voltages (VAO and VBO). 34.2(e). where ‘t’ is the time by which the two pole voltages are staggered and ‘T’ is the time period of the square wave pole voltages. In Fig.……………………………….2 Analysis Of The Single-Phase Full Bridge Inverter Single-phase half bridge inverter has already been described above. It may be more convenient to talk in terms of the phase displacement angle ‘Φ’ defined as below: t Φ = (2π ) Radians.∞ Version 2 EE IIT. 34.1. 3rd..com ..2(f) have been superimposed for comparison.1 and 34. the contribution to load current from 13th and higher order harmonics are less than 1% of the fundamental component and hence they may be neglected without any significant loss of accuracy. 34. used earlier for the half bridge inverter. Fig. which are similar to the pole voltage VAO of the half bridge circuit. Both VAO and VBO of the full bridge circuit are square waves but they will.1(b)) can be thought of as two half bridge circuits sharing the same dc bus.jntuworld.2(e) and 34. The single-phase full bridge circuit (Fig. 5th. 34. The pole voltage VAO of the full bridge inverter may again be written as in Eqn.

1 it may be seen that the line voltage distortion due to higher order harmonics for pulse width modulated waveform (except for Φ = 1800) is less than the corresponding distortion in the square wave pole voltage.18) (VAB .16) 2 2 π π The nth harmonic component in VAB may similarly be written as 2 Edc 4E nΦ Φ ………….9 Edc .……………….jntuworld.1 ) rms = 0. Thus the fundamental voltage magnitude is controlled by pulse-width modulation. The peak load voltage magnitude corresponds to Φ = 180 degrees and the load voltage will be zero for Φ = 00. For Φ = 180 degrees.(34.16..(34. from Eqns. for some values of phase shift angle (Φ) many of the harmonic voltage magnitudes will drastically reduce or may even get eliminated from the load voltage. Kharagpur 10 www. the rms magnitude of the fundamental component of load voltage may be written as Φ …………………………………………. Also.com .9 Edc sin 2 The rms magnitude of load voltage can be changed from zero to a peak magnitude of 0.n = [sin nwt − sin n( wt − Φ)] = dc cos n( wt − ) sin nπ nπ 2 2 From Eqn.1 = [sin wt − sin( wt − Φ)] = dc cos( wt − ) sin …………………….17 and 34. for Φ = 600 the load voltage will be free from 3rd and multiples of third harmonic.. In fact. 34.jntuworld. As the phase shift angle changes from zero to 1800 the width of voltage pulse in the load voltage waveform increases.com The fundamental component of VAB may be written as 2 Edc 4E Φ Φ VAB . For example.. 34. the load voltage waveform is once again square wave of time period T and instantaneous magnitude E. Version 2 EE IIT..……(34.17) VAB .www.

www. Kharagpur 11 www. the thermal limit may be reached during half cycle of current itself.jntuworld. For this load how does the diode conduction loss compare with the IGBT conduction loss? Version 2 EE IIT. Quiz Problems 1. The semiconductor switches have very small thermal time constant and they cannot withstand overheating for more than a few milli seconds. The half bridge inverter can output only half the power but cost is less. uninterruptible power supply units and in circuits utilizing electrical resonance between an inductor and a capacitor.jntuworld. It may be pointed out that each inverter switch consists of a controlled switch in anti-parallel with a diode. How does the output power handling capacity of a single-phase half bridge inverter compare with that of a single-phase full bridge inverter when they are connected to same dc bus voltage and the peak current capability of the inverter switches is also same. The distribution of current between the diode and the controlled switch will depend on the load power factor at the operating frequency.3 Voltage And Current Ratings Of Inverter Switches Switches in each leg of the inverter operate in a complementary manner. Some examples of circuits utilizing resonance phenomenon are induction heating units and electronic ballasts for fluorescent lamps. the turn-on transient voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage may be the optimum switch voltage rating. Hence the switches must be rated to withstand the peak magnitude of instantaneous load current. 34. A single-phase full bridge inverter is connected to a purely resistive load. When upper switch of a leg is on the lower switch will need to block the entire dc bus voltage and vice versa. 3. A single-phase full bridge inverter with square wave pole voltages is connected to a dc input voltage of 600 volts. In practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case dc voltage to account for stray voltages produced across stray inductances. Thus the switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. Also compare their costs. 480 volts fundamental and 160 volts of 3rd harmonic voltage Approx. Each inverter switch consists of an IGBT in anti-parallel with a diode. In general both diode as well as the controlled switch should be rated to carry the peak load current. The half bridge inverter can output only half the power but cost is nearly same The output power capability is same but half bridge inverter costs less. (a) (b) (c) (d) The half bridge inverter can output double power but cost also doubles.com . What maximum rms load voltage can be output by the inverter? How much will be the corresponding rms magnitude of 3rd harmonic voltage (a) (b) (c) (d) Approximately 270 volts of fundamental and 30 volts of 3rd harmonic voltage Approx. 540 volts fundamental and 180 volts of 3rd harmonic voltage Approx. Thus even though the load current passes through the switches only in alternate half cycles.com 34.4 Applications Of Square Wave Inverter The square wave voltage-source inverter discussed in this lesson finds application in many low cost ac motor drives. Each switch of the inverter carries load current during half of the current cycle. 270 volts fundamental and 90 volts of 3rd harmonic voltage 2.

2-b. 4-a) Version 2 EE IIT.com (a) (b) (c) (d) Diode and IGBT will have nearly same conduction loss Diode conduction loss will be nearly half of the IGBT loss Diode will have no conduction loss IGBT will have no conduction loss 4. 3-c.jntuworld.www.jntuworld. Kharagpur 12 www.com . Using frequency domain analysis estimate the ratio of 5th and 7th harmonic currents in a purely inductive load that is connected to the output of a single phase half bridge inverter with square wave pole voltages. (a) (b) (c) (d) 5th harmonic current will be nearly double of the 7th harmonic current 5th harmonic current will be 40% more than the 7th harmonic current 5th harmonic current will be zero while 7th harmonic current will be present Both 5th and 7th harmonic currents will be zero (Answers to the quiz problems: 1-d.

www.com .jntuworld.com Module 5 DC to AC Converters Version 2 EE IIT. Kharagpur 1 www.jntuworld.

com Lesson 35 3-Phase Voltage Source Inverter With Square Wave Output Version 2 EE IIT.www.jntuworld. Kharagpur 2 www.jntuworld.com .

This circuit may be identified as three single-phase half-bridge inverter circuits put across the same dc bus. 35. Do harmonic analysis of load voltage and load current output by the three-phase sq. Kharagpur 3 www. Understand the limitations and advantages of square-wave inverters. 35. 35. wave inverter.jntuworld. 35. P idc Sw1 Sw3 Sw5 B Edc + Cdc _ A B C A 3-phase balanced load N Sw4 n Sw6 Sw2 C Fig.1 shows the power circuit of the three-phase inverter.2. 35. The individual pole voltages of the 3-phase bridge circuit are identical to the square pole voltages output by singlephase half bridge or full bridge circuits. The numbering of the switches in Fig. The horizontal axis of the waveforms in Fig. In this lesson a 3-phase bridge type VSI with square wave pole voltages has been considered. These pole voltages along with some other relevant waveforms have been plotted in Fig.www.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Explain the operating principle of a three-phase square wave inverter.1 has some special significance vis-à-vis the output phase sequence. 35.2 the phase sequence of the pole voltages is taken as VAO. Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages have been analyzed in Lesson 34. VBO and VCO. The three pole voltages of the 3-phase square wave inverter are shifted in time by one third of the output time period.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load Version 2 EE IIT. In Fig. The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33. Decide on voltage and current ratings of inverter switches. where ‘ω’ is the angular frequency (in radians per second) of the fundamental component of square pole voltage and ‘t’ stands for time in second.2 has been represented in terms of ‘ωt’. The output from this inverter is to be fed to a 3-phase balanced load.jntuworld. Fig.com .

0. Sw2. Identifying the switching cycle time as 360 degrees (2π radians). …. It may be seen that with the chosen numbering the switches turn on in the sequence:.com .com VAO 0. 35.5Edc Edc VAB 0 ωt -Edc VAN 0 2/3Edc 1/3Edc -1/3Edc -2/3Edc 2/3Edc 1/3Edc ωt VBN 0 -1/3Edc 0 π/3 2π/3 π 4π/3 5π/3 2π -2/3Edc 7π/3 8π/3 3π 10π/3 11π/3 3π ωt Fig. Kharagpur 4 www.5Edc 0 Sw1 Sw1 Sw4 Sw4 ωt .5Edc VBO 0 Sw3 Sw6 0.Sw1. 35.and so on.5Edc 0. Sw3.0.2 may be noted. The upper and lower switches of each pole (leg) of the inverter conduct in a Version 2 EE IIT.5Edc Sw6 ωt VCO Sw5 0 Sw2 Sw5 Sw5 Sw2 ωt .jntuworld. Sw1.2: Some relevant voltage waveforms output by a 3-phase square wave VSI To appreciate the particular manner in which the switches have been numbered.0. the conductionpattern of the switches marked in Fig.5Edc Sw6 Sw3 .www. Sw5. Sw2. it can be seen that each switch conducts for 1800 and the turning on of the adjacent switch is staggered by 60 degrees. Sw6.jntuworld. Sw4.

Version 2 EE IIT. According to the conduction pattern indicated in Fig. Considering the symmetry in the switch conduction pattern. 35. It could be two from the upper group of switches.(Sw5. in each phase.2. Sw6. (Sw6. For a balanced 3-phase load the instantaneous phase voltage waveforms have been derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii) when the load. Sw3).www. Sw3. Kharagpur 5 www.3(a) has been referred to derive the expression for load-phase voltage. 35. it may be found that at any time three switches conduct. Sw2). Sw1. The neutral point ‘N’ of the load is deliberately left open for some good reasons mentioned later. VBN and VCN can be determined from the conduction pattern of the inverter switches.1 Determination Of Load Phase-Voltages Fig. will be given by VAN = 1/3 Edc. Sw2.3(a): Schematic load circuit during conduction of Sw5. the switching sequence may simply be reversed. With reference to Fig.e. VCN = 1/3 Edc. 35. The load side phase voltages VAN. Sw6 and Sw1 conduct. Sw6 and Sw1 For case (i). Sw1 X Sw5 X + Edc _ Sw6 X B A VAN = 1/3 Edc VBN = -2/3 Edc VCN = 1/3 Edc C N Fig. (Sw2.jntuworld. (Sw4. Sw5. Sw1).jntuworld. (Sw3. Sw4). The load side phase voltage waveforms turn out to be somewhat different from the pole voltage waveforms and have been dealt with in the next section. Sw5)..f.com . and one from lower group or vice-versa (i. switches Sw5. C) of the inverter.3(a) will represent the equivalent inverter and load circuit during the time interval 0≤ωt≤π/3. C. 35. the following circuit relations hold good. it is very easy to see that the instantaneous phase voltages. 35. B. 35. for 0≤ωt≤π/3. In both the cases the equivalent circuit of Fig.com complementary manner. For case (ii). when the load is a balance resistive load.m. Sw6). In the equivalent circuit representation the nonconducting switches have been omitted and a cross (X) sign is used to represent a conducting switch. As will be shown later the fundamental component of the three output line-voltages will be balanced. Each of these combinations of switches conducts for 600 in the sequence mentioned above to produce output phase sequence of A. VBN = -2/3 Edc.2 there are six combinations of conducting switches during an output cycle:. Sw4. 35. To reverse the output phase sequence. Under the assumption of ideal switches Fig. B. one from upper group and two from lower group). The three load terminals are connected to the three output points (A. consists of a resistor in series with an inductor and a back e. (Sw1. which are connected to positive dc bus.1 shows a star connected balanced 3-phase load. it may be seen that for 0≤ωt≤π/3.

when the switches Sw6. 35. It may be seen that voltage VBN is similar to VAN but lags it by one third of the output cycle period. The instantaneous load phase voltages may be found to be VAN = 2/3 Edc. VCN waveform leads VAN by 120 degrees in the time (ωt) frame. 35..…. 35. EB and EC are the instantaneous magnitudes of load phase-emfs.. Accordingly. VCN = RiC + L C + EC .com VAN = RiA + L VAN − VBN di di di A + E A . the following may be deduced: d (i + i ) di VAN + VCN = R (i A + iC ) + L A C + ( E A + EC ) = −( RiB + L B + EB ) = −VBN . VCN = 1/3 Edc.2. Since the load is balanced (with its neutral point floating) the algebraic sum of the instantaneous phase currents and the phase emfs will be zero. It may also be recalled that by suitably changing the switching sequence the output phase sequence can be changed. Fig.2) where. it can be verified that the load phase voltage VCN also has a waveform identical to the two other phase voltages but time displaced by one third of the output time period.4 it can be easily found that VAN = 1/3 Edc. VAN and VBN . VBN = RiB + L B + EB . in case of a more general (but balanced) R-L-E load are same as in case of a simple balanced resistive load.. B. VBN = VCN = -1/3 Edc. C.2 and 35. The phase voltage waveforms of Fig. Further. B and C respectively. iB . Sw1 and Sw2 The load phase voltage waveforms for other switching combinations may be found in a similar manner.1 and 35. along with line voltage VAB have been plotted over two output cycles in Fig. Kharagpur 6 www.……………………………………………………….3(b): Schematic load circuit during conduction of Sw6.1) dt dt dt = Edc . 35. Thus the instantaneous magnitudes of load phase voltages.……(35. It should be obvious that the fundamental component of the phase voltage waveforms will constitute a balanced 3-phase voltage having a phase sequence A. 35. VBN = -2/3 Edc...3. R and L are the per-phase load resistance and inductance that are connected in series with the corresponding phase-emf. Two of the phase voltages.com . Sw1 and Sw2 conduct. iC are the instantaneous load-phase currents entering phases A. (35. iA .jntuworld.www.3(b) shows the equivalent circuit during π/3≤ωt≤2π/3.(35.jntuworld. Sw1 X + Edc _ Sw2 X Sw6 X A VAN = 2/3 Edc VBN = -1/3 Edc VCN = -1/3 Edc C N B Fig. iA + iB + iC = 0 and EA + EB + EC = 0………………………………………(35. EA .3) From Eqns. VAN = VCN .4) dt dt Now from Eqns.2 show six steps per output cycle and are also referred as the Version 2 EE IIT. 35..

2E 2π VBO = ∑ nπdc sin n(wt − 3 ) ……………………………………. For most practical loads only the fundamental component of the inverter output voltage is of interest. VAO = 2 Edc sin(nwt ) ……………………………………….2 Harmonic Analysis Of Load Voltage Waveforms The individual pole voltage waveforms output by the 3-phase square wave inverter are identical to the output waveform of a single-phase half bridge inverter.5) n =1.5. Accordingly the fundamental magnitude of line voltages VAB . Also...1 = sin( wt − ) .com six-stepped waveform.5 and 35. nearly 9% of VAB .7....5 and 35.2.(35.3.(35.www.5..com .6) ⎦ n =1.∞ nπ ∑ 2 Edc ⎡ 2π ⎤ ⎢sin nwt − sin n( wt − 3 ) ⎥ ……………………….….8) ⎣ ⎦ It may be verified that difference of VAO and VBO leads to the expression for VAB ..2. When expressed as a fraction of fundamental voltage magnitude..jntuworld.3.7.15 replaced by 2π/3 radians. 35.8 respectively. A more detailed analysis of the load voltage waveforms is done in the following section. Accordingly the expressions for pole voltage VBO and line voltage VBC are written below in Eqns.1 of Lesson 34 is valid here too.7 and 35.∞ nπ ∑ 2 Edc ⎡ 2π ⎤ 2 3Edc π sin( wt + ) ⎢sin wt − sin( wt − 3 ) ⎥ = π π ⎣ 6 ⎦ 2 3Edc 2 3Edc π 7π VBC . As a consequence.3.35.....∞ VAB = ∑ 2π 4π ⎤ ⎡ ⎢sin n( wt − 3 ) − sin n( wt − 3 ) ⎥ …………….….∞ nπ ⎣ Using equations 35..1 = Version 2 EE IIT.(35... 35. The expression for line voltage VAB is identical to the one given in Lesson 34 (Eqn. The expression for a particular harmonic component in the voltage waveforms is determined simply by substituting ‘n’ in above equations by the harmonic order. However the inverter output also contains significant amount of higher order harmonic voltages that cause undesirable distortion of the output waveform. VBC and VCA can be written as: VBC = 2 Edc n=1. VCA.5.. the line voltage distortions are mainly due to 20% of 5th harmonic. nearly 14% of 7th. the harmonic analysis of the voltage waveform presented in section 34.7.15).. be noted that there are no even harmonics and the line voltages are free from 3rd and multiples of 3rd order harmonics. For convenience the expressions for pole-A voltage ‘ VAO ’ and line voltage ‘ VAB ’ are reproduced below in Eqns.6. though.35.7) n =1. The relevant waveforms are shown in Fig.. with ‘Φ’ of Eqn. as the harmonic order (n) increases their magnitudes decrease inversely with the harmonic order.1 = sin( wt − ) π π 2 6 The three fundamental line voltages are balanced (have identical magnitudes and are phase apart by 1200).(35.7..jntuworld.6.35...34..3. the expressions for remaining pole and line voltages can be written simply by shifting the time (ωt) origin by the phase shift angle shown in Fig..5. Kharagpur 7 www.. It may... 34.

the line voltages are free from these distortions.7.10) nπ 3 n=1. is deliberately left floating. 2 Edc VAN = sin(nwt ) ………………………………………. For a simple threephase R-L load.11.04%..12 2π 2π by (ω t − ) respectively. By keeping the load neutral point floating.13..13.83% and 0.(35.5..∞ ∑ 2 Edc nπ R 2 + n 2ω 2 L2 sin[nwt − tan −1 ( nω L )] …………….2 are found to be free from triplen harmonics. the triplen harmonic distortions of the load current is totally eliminated.7. As a result the load current for highly inductive R-L load will have close to sinusoidal shape. not only the need for bringing out the mid-potential point of dc supply is done away with. 35...(35.. rather than being connected to the mid-potential point of the input dc supply (as in a single-phase half bridge inverter).12) R Phase-B and phase-C current expressions can be obtained simply by replacing ωt in Eqn. Kharagpur 8 www. the instantaneous magnitude of any phase current can be determined by superposition of different harmonic currents of the phase.11. 0.13.5.9) ∑ n =1...www.. Version 2 EE IIT. 35.∞ ∑ ∑ VCN = 2 Edc 2π sin n( wt + ) ………………………………….(35. the load-phase voltages are also free from triplen harmonic distortions. Accordingly the load-phase voltages may be expressed in terms of its harmonic contents as shown below.5..jntuworld..∞ nπ VBN = 2 Edc 2π sin n( wt − ) ………………………………….11) 3 n=1. Since most loads are inductive in nature with a low pass filter type characteristics the effect of very high order harmonics may be neglected.11..com 11th and nearly 8% of 13th harmonic. 2. It may be noted that though the pole voltages have 3rd and multiples of 3rd order harmonic distortions.. In fact the six-stepped load-phase voltages shown in Fig.59%. Hence the load neutral point. the phase-A current ( iA ) expression in terms of resistance (R) and inductance (L) of the load may be written as: iA = n=1.∞ nπ For a balanced three-phase load..11.(35. 11th and 13th harmonic distortion in the load current (as a percentage of fundamental component of current) will respectively be 4%.12 will reveal that for a ) and (ω t + 3 3 purely inductive 3-phase load the 5th.. A close look at Eqn.. It turns out that by removing all triplen harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding load-phase (six-stepped) voltage waveform. have identical instantaneous magnitudes in all the three phases and their algebraic sum needs to flow in or out of the load neutral point)... if present in the load phases.jntuworld..7.13.7.. 35.. The floating neutral point does not allow a closed path for the 3rd and multiples of 3rd harmonic currents to flow (3rd or multiples of 3rd harmonic current.com ..5. Since there are no triplen harmonic currents in the load. These distortions are much less than the corresponding distortions in the load voltage waveforms... 7th.

com 35.www. like in un-interrupted power supplies. Kharagpur 9 www. In spite of the inherent low-pass filtering property of the motor load. An extra safety margin over the worstcase dc voltage. These harmonic currents cause extra iron and copper losses in the motor. They also produce unwanted torque pulsations. In both these examples. A simple diode bridge rectifier followed by a filter capacitor is often the most costeffective method to get dc voltage from ac supply. the inverter input voltage will need to be varied using an additional dc-to-dc converter. In some applications. The example of a purely inductive load discussed in the previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic currents. the input dc magnitude is fairly constant. as discussed in Lesson-34. In such situations the inverter discussed in this lesson will not be a suitable choice. However harmonic voltages of 5th. the diode connected in anti-parallel with the switch will conduct part of the switch current. The distribution of current between the diode and the controlled switch will depend on the load power factor at the operating frequency.com . When upper switch of a leg is on the lower switch will need to block the entire dc bus voltage and vice versa. section 34. For a non-unity power factor load. the dc input may be coming from a bank of batteries. In order that ac output voltage magnitude is controllable.3 Voltage And Current Ratings Of Inverter Switches As in a single-phase square-wave inverter. The motor speed hardly changes in response to these torque pulsations. switches in each leg of the three-phase inverter operate in a complementary manner. Each inverter-switch carries load-phase current during half of the current cycle. 7th and other non-triplen odd multiples of fundamental frequency distort the output voltage. A special notch filter may then be required to remove these frequencies from the inverter output voltage. With fixed input dc voltage the square-wave inverter can output only fixed magnitude of load voltage. Thus the switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. 35.3.4 Use And Limitations Of 3-Phase Square Wave Inverter The three-phase square wave inverter as described above can be used to generate balanced threephase ac voltages of desired (fundamental) frequency. namely pulse width modulated (PWM) inverters. is recommended. notably ac motor type loads.jntuworld. The square wave inverter discussed in this lesson may still be used for many loads. Fortunately the torque pulsations due to harmonic currents are of high frequencies and their effect gets subdued due to the large mechanical inertia of the drive system. Fortunately there are some other kinds of inverters. However a better solution will be to use a PWM inverter (to be Version 2 EE IIT. In many cases such distortions in output voltages may not be tolerable and it may also not be practical to use filter circuits to filter out the harmonic voltages in a satisfactory manner.jntuworld. which can provide higher quality of output voltage. Hence the switches must be rated to withstand the peak expected magnitude of instantaneous load-phase current. However in some cases torque pulsations of particular frequencies may cause unwanted resonance in the mechanical system of the drive. discussed in the next lesson. The motor loads are inductive in nature with the inherent quality to suppress the harmonic currents in the motor. In general both diode as well as the controlled switch should be rated to carry the peak load current. These diodes also need to block a peak reverse voltage equal to worst case voltage across the switches. The input dc voltage to the inverter is often derived from an ac source after rectification and filtering. the load current may still contain some harmonics. This does not suit the requirement in many cases where the load requires a variable voltage variable frequency (VVVF) supply.

the 3-phase load may be electronically switched. 33.com discussed in the next lesson). The switch control circuit is very simple and the switching frequency is significantly lower than in PWM inverters. 30V and 0 respectively 45V. with a dc link voltage of 100 volts. the following harmonic currents: (a) (b) (c) (d) (2) All odd multiples of fundamental All odd and even multiples of fundamental All even multiples of fundamental except 6th and multiples of 6th All odd multiples of fundamental except 3rd and multiples of 3rd The six-stepped load phase voltage of a 3-phase square wave inverter.3V and 20V respectively 90V. to the output of the 3-phase square wave inverter. In spite of the limitations. is capable of producing the following type of ac (fundamental component) voltages: Version 2 EE IIT. An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to provide uninterrupted power to some critical load. Listed below are two applications where a 3phase square wave inverter could be used. Input dc supply of the inverter often comes from a battery bank.jntuworld. apart from the fundamental frequency current. Another advantage over PWM inverter is its ability to output higher magnitude of fundamental voltage than the maximum that can be output from a PWM inverter (under the given dc supply condition). convert 3-phase ac voltages of 50 Hz to 3phase ac voltages of 60 Hz. 0 and 9V respectively (3) A 3-phase square wave inverter. Such a circuit may. 30V and 50V respectively 100V.www. In case ac mains supply fails. which can provide a VVVF output with enhanced output voltage quality. for example. The input to this circuit could as well have come from a single-phase supply. The square wave inverter discussed in this lesson may be used for dc to ac conversion. fed from a fixed dc input. within few milliseconds. (ii) Problems (1) A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load. Here a critical load requiring 3phase ac supply of fixed magnitude and frequency has been considered. The switch cost may also be lower as one may do away with slower switching devices and slightly lower rated switches. in which case the single-phase ac is first converted into dc and then converted back to 3-phase ac of the desired frequency.jntuworld. Kharagpur 10 www.com . will have the following rms magnitudes of 1st. 3rd and 5th harmonic voltages: (a) (b) (c) (d) 10V. This results in low switching losses. The input ac is first converted into dc and then converted back to ac of new frequency. (i) A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac (input) voltages of one frequency to 3-phase ac (output) voltages of the desired frequency. discussed above. The load phase current will contain. the square wave inverter may be a preferred choice on account of its simplicity and low cost.

7A 424V.com . 2-d.jntuworld. 70. Kharagpur 11 www. 70.jntuworld. The diodes of the inverter will be subjected to the following peak voltage and current stresses: (a) (b) (c) (d) 600V.www. 100A (Answers: 1-d. 3-b. The worst-case load phase current (peak magnitude) is expected to be 100 amps and the worst-case dc input voltage is expected to be 600 volts.7A 424V. 4-a) Version 2 EE IIT.com (a) (b) (c) (d) (4) Variable voltage variable frequency type Fixed voltage variable frequency type Variable voltage fixed frequency type None of the above A 3-phase square wave inverter feeds a balanced 3-phase inductance type load. 100A 600V.

jntuworld. Kharagpur 1 www.www.com Module 5 DC to AC Converters Version 2 EE IIT.com .jntuworld.

jntuworld.jntuworld. Kharagpur 2 www.com .www.com Lesson 36 3-Phase Pulse Width Modulated (PWM) Inverter Version 2 EE IIT.

For wide variation in drive speed. The PWM inverters are very commonly used in adjustable speed ac motor drive loads where one needs to feed the motor with variable voltage. while discussing the 3phase square wave inverter it was shown that the magnitudes of fundamental components of the inverter pole voltage (voltage between the output of an inverter leg and the mid potential point of the input dc supply) and the load phase voltage are identical provided the load is a balanced 3phase load. Version 2 EE IIT. PWM inverters can be of single phase as well as three phase types.jntuworld.www. like motor loads have an inherent quality to suppress high frequency harmonic currents and hence an external filter may not be necessary. The pole voltage waveforms of 3-phase inverter are simpler to visualize and analyze and hence in this lesson the harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of the pole voltages. differing in their methods of implementation. a detailed harmonic analysis of the voltage waveform needs to be done. Their principle of operation remains similar and hence in this lesson the emphasis has been put on the more general. Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in practical applications. There are several different PWM techniques. In fact. The quality of output voltage can also be greatly enhanced.com . It is implicit that the load phase and line voltages will not be affected by the 3rd and multiples of 3rd harmonic components that may be present in the pole voltage waveforms. These inverters are capable of producing ac voltages of variable magnitude as well as variable frequency. In Lesson-35. To judge the quality of voltage produced by a PWM inverter.com After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Explain the philosophy behind PWM inverters. when compared with those of square wave inverters discussed in Lesson-35. The applied voltage also needs to vary almost linearly with the frequency. However in all these techniques the aim is to generate an output voltage. As will be discussed later in this chapter.jntuworld. would result in a good quality sinusoidal voltage waveform of desired fundamental frequency and magnitude. 3-phase type PWM inverter. the frequency of the applied ac voltage needs to be varied over a wide range. In the following discussions some of the results of harmonic analysis done in the previous lessons have been borrowed. it may not be possible to reduce the overall voltage distortion due to harmonics but by proper switching control the magnitudes of lower order harmonic voltages can be reduced. often at the cost of increasing the magnitudes of higher order harmonic voltages. which after some filtering. Kharagpur 3 www. variable frequency supply. Understand the advantages and disadvantages of PWM inverters. Compare the quality of output voltage produced by different PWM inverters Decide on voltage and current ratings of inverter switches. Such a situation is acceptable in most cases as the harmonic voltages of higher frequencies can be satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads. after removing 3rd and multiples of 3rd harmonics from the pole voltage waveform one obtains the corresponding load phase voltage waveform. for the inverter topology considered here.

f(π+ωt).5Edc α1 0 α2 α3 π/2 α4 π-α4 π-α3 π-α1 π+α1 π+α3 3π/2 2π-α3 2π-α1 π π+α4 2π-α4 2π-α2 2π π-α2 π+α2 SL SL SL SL SL SL SL SU SU SU SU SU SU SU SU ωt SL Fig. Compared to the square pole voltage waveform seen in Lesson-35.www. When upper switch (SU). repeating after every 2π/ω duration. the pole voltage waveform of the PWM inverter changes polarity several times during each half cycle.5 Edc and when the lower switch (SL). when upper switch is on the lower is off and vice-versa. the pole voltage is + 0. connected to the negative dc bus. In a three-phase inverter the other two pole voltages have identical shapes but they are displaced in time by one third of an output cycle. meant to feed an inductive type load.jntuworld. It is to be remembered that in voltage source inverters. Such a symmetry in the waveform amounts Version 2 EE IIT. 36. It may be noted that the instantaneous magnitude of pole voltage waveform remains fixed at half the input dc voltage (Edc). 36.5Edc SU 0 SL -0. The half wave odd symmetry of any repetitive waveform f(ωt).0.5 Edc.jntuworld. is defined by f(ωt) = . Both upper and lower switches Pole Voltage 0. On the other hand one of these two switches in each pole (leg) must always conduct to provide continuity of current through inductive loads. The time instances at which the voltage polarities reverse have been referred here as notch angles.1 Nature Of Pole Voltage Waveforms Output By PWM Inverters Unlike in square wave inverters the switches of PWM inverters are turned on and off at significantly higher frequencies than the fundamental frequency of the output voltage waveform. is on the instantaneous pole voltage is .1 over one cycle of output voltage.com 36.36. The switching transition time has been neglected in accordance with the assumption of ideal switches. The typical pole voltage waveform of a PWM inverter is shown in Fig.1 has half wave odd symmetry and quarter-wave mirror symmetry. 36. That is. the upper and lower switches of the inverter pole conduct in a complementary manner.2 Harmonic Analysis Of Pole Voltage Waveform The pole voltage waveform shown in Fig. connected to the positive dc bus is on. A sudden disruption in inductive load current will cause a large voltage spike that may damage the inverter circuit and the load.com .1: A typical pole-voltage waveform of a PWM inverter should not remain on simultaneously as this will cause short circuit across the dc bus. Kharagpur 4 www.

The peak magnitude of nth harmonic voltage is given as: 2E bn = (1 − 2 cos nα1 + 2 cos nα 2 − 2 cos nα 3 + 2 cos nα 4 ) …………………. Now. whereas by shifting time origin the sine wave may become cosine or may have some other phase-shift.(36. seventh. eleventh and other odd harmonics. 36. third. where α1 .(36.(36. Most of the industrial loads are inductive in nature with an b5 = Version 2 EE IIT. it merely simplifies the Fourier analysis of the pole voltage waveform.3) π 2E (1 − 2 cos 5α1 + 2 cos 5α 2 − 2 cos 5α 3 + 2 cos 5α 4 ) ……………….. Because of the half wave and quarter wave symmetry of the waveform. Most of the three phase loads of interest are of balanced type and for such loads one need not worry about triplen (3rd and multiples of 3rd) harmonic distortion of the pole voltages. This is quite expected.3. results in presence of only sine components in the Fourier series representation of the waveform. defined by f(ωt) = f(πωt).. The half wave odd symmetry followed by quarter wave mirror symmetry.. With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform shown in Fig...com to absence of dc and even harmonic components from the waveform. Kharagpur 5 www.jntuworld. as by just shifting the time origin new (even) harmonic frequencies will not creep up in the voltage waveform. α 2 ¸ α3 and α 4 are the four notch angles in the quarter cycle ( 0 ≤ ω t ≤ π 2 ) of the waveform. mentioned before.jntuworld... the third and multiples of third harmonics do not show up in the load phase and line voltage waveforms of a balanced 3-phase load. fifth..2) nπ .. ninth.(36. It may also be noted that the quarter wave symmetry is not achieved at the cost of compromising the inverter’s output capability (in terms of magnitude and quality of achievable output voltage).………………….1) where VAO is the instantaneous magnitude of the pole voltage shown in Fig. Thus the pole voltage will have fundamental.com .www. It may be verified that quarter wave symmetry may not hold good once the time origin is shifted arbitrarily.1 and bn is the peak magnitude of its nth harmonic component.4) 5π 2E b7 = (1 − 2 cos 7α1 + 2 cos 7α 2 − 2 cos 7α 3 + 2 cos 7α 4 ) ………………. All inverter output voltages maintain half wave odd symmetry to eliminate the unwanted dc voltage and the even harmonics.5.6) 11π It can be seen that the 3rd and 9th harmonics have been not considered. The peak magnitudes of fundamental ( b1 ) and three other lowest order harmonic voltages that matter most to the load can be written as: 2E b1 = (1 − 2 cos α1 + 2 cos α 2 − 2 cos α 3 + 2 cos α 4 ) ….1 may be decomposed in terms of its Fourier components as below:- VAO = n=1. However the half-wave odd symmetry is maintained in spite of shifting of time origin.5) 5π 2E b11 = (1 − 2 cos11α1 + 2 cos11α 2 − 2 cos11α 3 + 2 cos11α 4 ) …………. as described in the beginning of this lesson. The quarter wave symmetry talked above is not necessary for improvement of the output waveform quality.(36..(36.∞ ∑ bn sin nω t …………………………………………………….. as they will not appear in the load side phase and line voltages. the pole voltage has only odd harmonics and has only sinusoidal components in the Fourier expansion. 36..

(36. the switch must be capable of being switched on and off at the required frequency. The inverter operation can then be very quite. As such one would like to eliminate as many low order harmonics as possible.com . The switching frequency is directly proportional to the switching losses in the inverter switches.. Now. The root mean square (rms) of the pole voltage equals 0.5 Edc (the switching transition time has been neglected). seventh ( b7 ) and eleventh ( b11 ) harmonics may be set to zero.3 to 36. 36. 36. Thus if the switching frequency is 20 kHz or beyond. Kharagpur 6 www.www. Now a periodic function ‘ f (ω t ) ’ when expressed in terms of its Fourier components satisfies the following mathematical identity. Also.5 Edc and . Generally.………………………….. The switching frequency (fsw) of the inverter switches can be equated to fsw = 2 k f1 …………. only the fundamental frequency component in the output voltage is of interest and all other harmonic voltages are undesirable.7) .jntuworld. These voltage magnitudes when substituted in the expressions given by Eqns. the top and bottom switches of that particular pole undergo a switching transition (on to off or vice versa). In fact if there are ‘k’ notch angles per quarter cycle. If the inverter operates at low frequency. With a switching frequency of 20 kHz and the output (fundamental) frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output waveform... Thus after fundamental voltage.6 will lead to the solutions of the notch angles.jntuworld. Version 2 EE IIT.com inherent quality to attenuate currents due to higher order harmonic voltages. the connecting wires to the switches etc. Thus it can be seen that a better quality output waveform (in terms of elimination of more numbers of unwanted harmonic voltages) comes at the cost of increasing the switching frequency of the inverter. The humming or whistling type noise due to low switching frequency may at times be too annoying and unacceptable. the other significant voltages for the load are 5th.) and result in audible noise.. The load voltage can thus be made virtually free of low order harmonics and the load current (for an inductive load) can be expected to have a good quality sinusoidal waveform. ‘k’ is the number of notches per quarter cycle and f1 is the frequency of fundamental component in the output voltage.3 Trade Off Between Low Order And High Order Harmonics The 3-phase inverter with six switches connected in the bridge fashion is also known as a twolevel inverter because the inverter pole-voltage alternates between the two voltage levels of +0. where one turn-on and one turn-off has been taken as one switching cycle.0. The IGBT switches used in medium power inverters are generally switched at a frequency of 20 kHz or more.5 Edc. the switching frequency related audible noise will not be present when the inverter operates... each time a notch angle is encountered in the pole voltage waveform. 7th and 11th etc. One may like to eliminate many more unwanted harmonic frequencies from the load voltage waveform but this will require introduction of more notch angles per quarter cycle of the pole voltage. ‘k’ number of equations may be written each of which determines the magnitude of a particular harmonic voltage.. Similarly low frequency current through inductors and transformers also produce audible noise. The range of audible noise for human beings extends from few Hertz to 20 kHz. The switching frequency of 20 kHz is important in another sense too. also carry low frequency current producing low frequency vibrations (due to interaction of current with the stray magnetic field produced by other conductors etc. Accordingly the fundamental voltage magnitude ( b1 ) may be set at the desired value and the magnitudes of fifth ( b5 ).………….

rms ⎤ ⎣ ⎦ 2 + n = 2.∞ ∑ ⎡ f (ω t ) n . 36.. There are several other PWM techniques.. on its own.1.4.jntuworld.jntuworld. (36. ω t =0 ∫ { f (ω t ) sin ω t}dω t …………………………………….45Edc.rms and f (ω t )n. both f (ω t ) and sin ω t are positive during 0 ≤ ω t ≤ π but the sign of f (ω t ) in PWM waveform alternates between positive and negative values. The required size of the external filter will be small if the inverter output is free from low frequency harmonics. the rms magnitude of the fundamental pole voltage is always going to be less than 0.e. Space Vector based PWM technique.] In case of PWM inverter the magnitude of fundamental output voltage is fixed by suitable pulse width modulation (by selection of suitable notch angles for the waveform in Fig.com . The logic described to select notch angles is also specific to one particular PWM technique that is known as selective harmonic elimination technique. Kharagpur 7 www. is only representative in nature.. as given by Eqn.9) 36. (36.. the important ones are:. f (ω t )rms is the rms magnitude of the given periodic waveform where as f (ω t )1.(36. Further.8). the reduction in fundamental magnitude leads to increase in the rms magnitude of the unwanted ripple voltage.. However. Version 2 EE IIT. if the waveform ‘ f (ω t ) ’ has half wave odd symmetry and quarter wave mirror symmetry. (36.9) be replaced by the two-level pole voltage waveform of the PWM inverter.5Edc..rms = 2 π π Now let f (ω t ) in the above equations (36.8) equals (0. the fundamental magnitude (rms) of PWM inverter’s output pole-voltage will be less than 0.4 Brief Description Of Some Popular PWM Techniques The schematic PWM waveform shown in Fig.1). The term on the left hand side of Eqn. as can be seen from Eqn. it will be at the cost of increasing the magnitudes of higher order harmonics. In case the load.rms are the rms magnitudes of the fundamental component and nth harmonic component of the waveform respectively. its fundamental voltage can be expressed as f (ω t )1. The first term on the right hand side of Eqn. As can be seen.www.SINE-PWM technique. mean of square) magnitude of the fundamental component of pole voltage whereas the second term on the right hand side denotes the mean-of-square magnitude of the unwanted ripple in the pole voltage. 36..3.9). in detail in the next few lessons. after fixing the fundamental voltage magnitude if it is desired to eliminate some of the low order harmonics.. However considering the fact that most of the loads are inductive in nature with low pass filter type characteristics the load current quality effectively improves by eliminating lower order harmonics from the pole voltage waveform (even if the higher order harmonic magnitudes increase).rms ⎤ ………………………. Also.8 and 36. is not able to filter out the harmonic voltages satisfactorily the inverter output may be passed through some external filter before being applied to load. Also. [In case of square wave output. Thus. which is the rms magnitude of fundamental pole voltage of a 3-phase square wave inverter.5Edc)2. A few of these techniques have been dealt with.. Hysteresis current controller based PWM technique etc. (36.8) ⎣ ⎦ 2 In Eqn.8) is the square-of-rms (i.com [ f (ω t )rms ]2 = ⎡ f (ω t )1..8). as far as the quality of inverter pole voltage alone is concerned the PWM technique is not helping. (36.(36.

For example. Kharagpur 8 www. containing switching information is addressed sequentially after every 10 microsecond (this being the time step.6) will be different for different output frequencies. it may be desired to output a 3-phase balanced voltage in the frequency range of 5 Hz to 50 Hz with the constraint that the ratio between output voltage magnitude and output frequency should remain fixed to some predetermined value.jntuworld. 8 Hz. for example. If. whereas some other PWM controllers could be a hybrid between analog and digital circuits. each bit corresponding to one particular switch. For each of these output frequencies. to discretize the output cycle time period) the desired switching pattern for the inverter switches may be obtained. In contrast to the selective harmonic elimination technique discussed above. notably SINE-PWM and Space Vector-PWM techniques. Now switching information for successive output frequencies may be stored in successive memory blocks.3 to 36. there will be more notch angles (per quarter cycle) at low output frequencies and less number of notches at higher frequencies. …. The desired magnitudes of output voltage for all these discrete frequencies is found out and accordingly the notch angles are calculated to eliminate as many unwanted harmonics as possible (keeping in mind the constraint on switching frequency). the desired output voltage is a sinusoidal waveform of a given magnitude and of frequency ‘f1’.jntuworld. These transcendental equations are solved off-line and the information regarding notch angles (switching instances) is stored in digital memory. For example. The switching word combines the switching information for all three legs (all six switches) of the inverter and may be obtained in the form of a six bit binary word. Digital signal processor (DSP) or Personal Computer (PC). the selective harmonic elimination technique described above requires numerical solutions of the transcendental equations for arriving at the required notch angles. 1Hz. 49 Hz. 7 Hz. if the switching frequency is kept constant. Under this situation the output voltage range may be discretized in steps of.180 only). Similarly ‘0’ bit value may correspond to turn-off command of the switch. some other PWM techniques. 36. Thus the set of notch angles for one frequency may be different from the notch angles at some other frequency.com . 36. say. One may move from one memory block to another memory block (by suitably multiplexing the memory address-word) to obtain the inverterswitching pattern for some other output frequency. Also.7. The selective harmonic elimination technique described above is also known as stored-PWM technique. It may be realized that the notch instances may not occur at regular time intervals. The notch angles can thus be realized with a maximum time error of 10 microseconds (which for 50 Hz output corresponds to an error of 0. it may be convenient to discretize one complete output cycle time interval in small steps (say. in steps of 10 microseconds) and the inverter switching word (as described below) at these successive time intervals are then stored in the successive memory locations. The overall memory requirement may be large but since the memory cost has been reducing over the years the stored-PWM technique remains one of the most attractive techniques. like EPROM.com Some of the PWM techniques can be realized using analog circuits alone. then for Version 2 EE IIT. When a particular bit value is ‘1’ that particular switch may require being turned-on. some others are more easily realized with the help of digital processors like microprocessor. After completion of one output cycle the next cycle is simply repeated like the previous one. Now if the memory block. try to match the mean value of load voltage under the rectangular PWM waveform with the mean voltage of the desired output waveform over every small time interval of the output cycle. For satisfactory implementation of this technique.www. chosen above. Similarly fundamental output voltage requirement may not remain fixed for all output frequencies and hence the transcendental equations (similar to Eqns. generally the desired output frequency range is divided in few discrete frequencies. Thus the available output may vary from 5 Hz to 50 Hz through the following discrete values of intermediate frequencies: 6 Hz. as per Eqn.

namely. This technique is described below for a single-phase half bridge inverter shown in Fig. the three-phase bridge inverter consisting of six switches (shown in Lesson-35) can output pole voltages of only two levels +0. This can be verified simply by writing and analyzing the loop voltage equation. the two waveforms are matching. Kharagpur 9 www. The actual load current is sensed with the help of a current sensor and compared with its reference magnitude.2. Further details of these techniques may be found in later lessons.5Edc. The positive sense for the load current (IL) is taken along the direction of arrow in Fig.5Edc + _ N Fig. to match the desired current shape.5Edc IL SU A SL + _ O LOAD 0.5Edc).5Edc and -0. zero and -0. Here the instantaneous magnitude of load current is directly controlled. 36. within some tolerable error band. +0. The load could be a R-L load or a R-L-E load.5Edc. Thus the PWM waveform may be considered to be the superposition of the desired output waveform and ripple voltages of time period Δt. by proper switching of the inverter switches.jntuworld.2: 1-phase half bridge VSI for CCPWM control Another popular PWM technique is current controlled PWM (CCPWM) technique.2. 36.com every small time interval ‘Δt’ of the output cycle period (such that Δt << 1/ f1) the mean (dc) magnitude under desired sine wave and the mean dc voltage under the PWM pulses are made equal.com . In contrast to a twolevel inverter.5 Two-Level Versus Three-Level PWM Inverters As described in section 36. The circuit details of three-level inverter will not be discussed Version 2 EE IIT. Now barring the mismatch in the instantaneous magnitudes of the sine wave and the PWM wave within the small time period ‘Δt’. To increase the actual current along the direction of arrow (or to reduce the current flowing in a direction opposite to the arrow) upper switch ‘SU’ needs to be turned on. as described below. In case of R-L-E load. The ripple voltage waveform in each ‘Δt’ time interval may not be identical and hence ripple voltage may consist of a band of harmonics of high frequency. 36.36.5Edc. The error in load current can be controlled.www.3. In the frequency axis the high frequency harmonic voltages are far away from the desired voltage of fundamental frequency ‘f1’ and hence suitable low pass filter circuits may be used to block the unwanted harmonic currents without affecting the magnitude of the fundamental frequency current. it is assumed that the back emf (E) of the load has a peak magnitude lower than the magnitude of instantaneous pole voltage (0. whereas turning on of lower switch ‘SL’ will produce the reverse effect.jntuworld. a three-level inverter is capable of producing three different pole-voltage levels. P + _ Edc 0.

Since the pole voltage can now have zero level too. Generally molded blocks of six switches and six diodes. i. This is due to the increased switching losses in the PWM inverter.5Edc.3. connected in Version 2 EE IIT.6 Considerations On Switch Voltage And Current Ratings As in square wave inverter the switches of PWM inverter must also be rated for the maximum dc link voltage. +E. the rms magnitude of the pole voltage can be brought below 0. (Sw1 and Sw4) or (Sw2 and Sw3). be a significant difference in the switch current ratings of the square wave and PWM inverter for comparable magnitudes of inverters’ output current. any reduction in the fundamental output voltage magnitude of a two level inverter results in increased rms magnitude of unwanted ripple in the output waveform.e. conduct the load voltage will have two levels. For medium power rated inverters mostly IGBT switches (with fast acting antiparallel diodes) are used. Since the switches in PWM inverter operate at much higher frequencies than in square wave inverter. By suitably switching between one diagonal pair to another diagonal pair one can obtain a PWM waveform similar to the pole voltage waveform of a three-phase PWM inverter (only change is in the voltage magnitude).8) in section 36.8) be considered in relation to a three-level inverter. 36.36. P idc Sw1 Sw3 Edc + Cdc _ A LOAD B Sw2 N Fig. As described by Eqn. (36. For lower magnitude of fundamental pole-voltage. +E or –E.com in this course but it can easily be shown that the three-level inverter will have better harmonic spectrum in comparison to the two-level inverter. Now. (36.3. however. As with a three-phase inverter. For this circuit if all the time one of the two diagonal pair of switches. as given by Eqn. in case of three-level inverter.com . (36. There will. let Eqn. Thus the rms of the ripple voltage. suitable intervals of zero voltage level may be introduced such that with lowering of fundamental voltage the rms of the overall pole voltage also reduces. the switching losses in the former are comparable to the conduction losses. This calls for suitable de-rating of the switch current rating. Consider the single-phase full bridge circuit shown in Fig. Kharagpur 10 www. Now if the allowed switching combination includes conduction of Sw1 along with Sw3 (or Sw2 along with Sw4) the load voltage may have three-levels.www.jntuworld.9).. can be made lower than that of the two-level inverter. zero and –E.jntuworld.3: A 1-phase full-bridge VSI Sw4 The three-level versus two-level comparison can be applicable to a single-phase PWM inverter too. 36. the single phase PWM inverter too will have lower voltage distortion in case of three-level load voltage (than the corresponding distortion in two level output).

switch current and gate-to-emitter voltages. is used to feed a three-phase balanced R-L load with a load power factor of 0. fixed frequency (c) Fixed voltage.9. fixed frequency Answers to Quiz problems: 1-c. The peak magnitude of diode current and the IGBT current will have the following relation: (a) They will be equal (b) Peak diode current will be less than half of the peak IGBT current (c) Diode current will nearly be zero (d) Peak diode current will be less than one third of the peak IGBT current (4) A PWM inverter is capable of producing the following type of output voltage: (a) Variable in magnitude and frequency (b) Variable voltage. the load current frequently jumps from controlled switch (say. The worst-case diode losses also need to be determined for deciding on the de-rating factor for diode currents. The switch manufacturers provide the turn-on and turn-off loss data for the switches for different magnitudes of dc link voltage. The thermal resistance data (thermal resistance between case and semiconductor-junction) for the switches and diodes are also provided. Similarly conduction loss data for the switches and the diodes are also provided. It is to be kept in mind that in PWM inverters the load current polarity changes only according to the output frequency and not according to the switching frequency.www. IGBT) to diode and hence the diodes of the switches must also be rated to carry the peak magnitude of load current. because of large number of switching per output cycle. with very large number of (nearly) evenly distributed notches per output cycle. 2-c. are commercially available. For load power factor close to one. Quiz Problems (1) A PWM inverter is operated from a dc link voltage of 600 volts. variable frequency (d) Fixed voltage. In PWM inverters. 3-a. 4-a Version 2 EE IIT. These molded blocks come with isolated metallic case that need to be mounted on suitably sized heat sinks for dissipation of thermal losses in the switch. The heat-sink manufacturers provide data / guide lines for calculating the thermal resistance between heat sink and ambient. as the PWM inverter’s output voltage decreases the diode conduction duration increases.jntuworld. Kharagpur 11 www. The inverter designer needs to do a detailed analysis of the worst-case thermal losses and temperature rise and need to limit the switch current accordingly. The maximum rms line voltage (fundamental component) will be less than or equal to: (a) 600 volts (b) 300 volts (c) 467 volts (d) 582 volts (2) In the harmonic analysis of the pole-voltage waveform (produced by a three-phase PWM inverter feeding a balanced three-phase load) the 3rd and multiples of 3rd harmonics are ignored because: (a) They will not appear in pole voltage (b) They will not appear in load phase voltage (c) They will not appear in load phase and line voltage (d) They will appear in line voltage but not in phase voltage (3) An IGBT based PWM inverter.jntuworld.com .com bridge fashion with their power and control terminals brought out.

jntuworld.jntuworld.com .www. Kharagpur 1 www.com Module 5 DC to AC Converters Version 2 EE IIT.

www. Kharagpur 2 www.com Lesson 37 Sine PWM and its Realization Version 2 EE IIT.jntuworld.jntuworld.com .

3.jntuworld. 36. vary in a sinusoidal manner.com . It can be seen that the pole voltage consists of large number of rectangular pulses whose widths are modulated suitably to provide control over the output voltage (fundamental component) magnitude and. Explain the concept of sine-modulated PWM inverter Design a simple controller for the sine-PWM inverter Calculate output voltage magnitude from the inverter operating parameters Compare sine-modulated PWM inverter with square wave inverter The PWM inverter has been introduced in Lesson 36 and Fig.) Fig.1: A schematic circuit for comparison of Modulating and Carrier signals The comparator output signal ‘Q’ is used to turn-on the high side and low side switches of the inverter pole.com After completion of this lesson. the reader shall be able to: 1.www.5Edc and Version 2 EE IIT.1 shows a typical pole voltage waveform. Kharagpur 3 www. over one output cycle of the PWM inverter. When ‘Q’ is high. 37. Fig. thus obtained is a replica of the comparator output voltage.1 shows an op-amp based comparator output along with representative sinusoidal and triangular signals as inputs. in its simplified form. 37. the pole voltage (measured with respect to the mid potential point of the dc supply) is +0. involves comparison of a high frequency triangular carrier voltage with a sinusoidal modulating signal that represents the desired fundamental component of the pole voltage waveform. 37. the triangular and sinusoidal signals are fed to the inverting and the non-inverting input terminals respectively and the comparator output magnitudes for high and low levels are assumed to be +VCC and -VCC. over the output cycle. When ‘Q’= + VCC. 4. The scheme. 2. The peak magnitude of the modulating signal should remain limited to the peak magnitude of the carrier signal. upper (high side) switch of the particular pole is turned on and when ‘Q’ is low the lower switch is turned on. The pole voltage.jntuworld. The comparator output is then used to control the high side and low side switches of the particular pole. +VCC Modulating signal Q Q -VCC + Carrier signal - Time (mili sec. additionally. In Sine-PWM inverter the widths of the pole-voltage pulses.1. control over the harmonic spectrum of the output waveform. In the comparator shown in Fig.

com when ‘Q’= (-)VCC. The input dc voltage to the inverter (Edc) has been assumed to be of constant magnitude. Thus. The Fourier series decomposition of pole voltage waveform results into a mean (dc) voltage and harmonic voltages whose frequencies are integral multiples of carrier frequency.jntuworld.5Edc + Edc _ + _ Pole Voltage + _ SU O 0. A 0.jntuworld. Fig. +VCC 0.5Edc Fig. Kharagpur 4 www.5Edc.1 Analysis Of The Pole Voltage Waveform With A Dc Modulating Signal Before analyzing the sine-modulated pole voltage waveform. the high frequency triangular carrier waveform is compared with the dc modulating signal and the comparator output is used to control the high and low level switches (SU and SL respectively) of the inverter pole shown in Fig. can be found to be Version 2 EE IIT. 37.4 unit of voltage.2: Inverter pole voltage for a pure dc modulating waveform The figure also shows the comparator output (Q) and the pole voltage (VAO) waveforms for this case. 37. The magnitude of the dc modulating signal is constrained to remain between the minimum and maximum magnitudes of the triangular carrier signal.www.5Edc Q VAO SL -VCC .com .0 and +1. the pole voltage becomes (-0. with pure dc modulating signal the pole voltage consists of pulses of identical shapes repeating at carrier frequency. By using simple mathematics the high-duration of the pulses ( th ).5)Edc. 37.5Edc Time in m. on a normalized scale. during which the pole voltage magnitude is 0.sec.2 illustrates one such case where the triangular carrier signal varies between -1. it would be revealing to consider a pure dc signal (of constant magnitude) as the modulating wave.0.0 units of voltage and the magnitude of the modulating wave is kept at 0. As can be seen.2. 37. Now. the harmonic contents in the comparator output voltage and the pole voltage waveforms are identical.

5Edc and -0.com . As mentioned before.. Let now a slowly varying sinusoidal voltage.www.1). can be found as: tl = Tc V (1 − m ) …………………………………………………………………. When the modulating signal magnitude ( Vm ) is zero. A typical figure will be 50 Hz for the modulating signal and 20 Kilohertz for the carrier signal.3) The dc modulating signal could acquire any magnitude between + Vc and . The lowest order harmonic-frequency being same as the carrier frequency. (37.2 Pole Voltage Waveform With Sinusoidal Modulating Signal In the previous section a pure dc modulating signal was considered..jntuworld. 2 Vc where Tc is the time period of the triangular carrier waveform.jntuworld. the magnitude of modulating signal will be virtually constant over any particular carrier-signal time period. The pole voltage waveform thus has a low frequency component whose instantaneous magnitude is Version 2 EE IIT.5Edc. Kharagpur 5 www.Vc and accordingly the mean magnitude of pole voltage can vary within +0.. Because of the above assumptions some results of the previous section. Since the slowly varying modulating signal is virtually constant over a high frequency carrier time period. may be used...2) 2 Vc The dc component of the pole voltage ( V0 ) can be found to be V0 = 0.. Under such high frequency ratios.5 Edc Vm Vc …………………………………………………………………. the high and low durations of the pole output pulses will be identical and the mean pole voltage magnitude will be zero.com th = Tc V (1 + m ) …………………………………………………………………. (37. The peak magnitude of the sinusoidal signal is less than or equal to the peak magnitude of the carrier signal. The frequency of the modulating signal is several orders lower than the frequency of the carrier signal. 37. Thus the discretely averaged magnitude of pole voltage (averaged over successive high frequency carrier time period) is similar to the modulating signal. where a pure dc modulating signal was considered. 2. apart from the dc component.. the mean magnitude of the inverter pole voltage averaged over a carrier time period will be proportional to the mean magnitude of the modulating signal. the pole voltage consists of harmonics of integral multiples of carrier frequency. This ensures that the instantaneous magnitude of the modulating signal never exceeds the peak magnitude of the carrier signal. with the following constraints. Vm is the magnitude of the modulating signal and Vc is the peak (positive) magnitude of the carrier signal. (37. be considered as