Digital System Design

Introduction

Bassam Jamil
1

Course Administration
 Instructor: Bassam Jamil Mohammed  Instructor's e-mail: bassam@hu.edu.jo Text: • Advanced Digital Design with Verilog HDL , Michael Ciletti, Pearson Education Inc, 2003 or 2011 Slides : pdf on the course web page after lecture on Moodle (not BB)

2

Course Content

This course will discuss:
The   

hardware description language (Verilog)

Synthesis of digital circuits. Advanced digital design topics: FSM/Power/Area Download designs on FPGAs.

3

Course Outline (roughly)
Topic Introduction and review of Comb and sequential design Verilog Basics Modelsim Verilog Advanced Synthesis (FSM, Datapaths) Optimizations Book Chapter 1-3 Chapter 4 Notes Chapter 5 Chapter 6,7 Notes

4

Acknowledgement
 Based

my slides on notes from universities notes and book authors, e.g.
MIT

   

Virginia Tech Samir Panitkar (Verilog HDL) Morris Mano (Digital Design) Ciletti ( Verilog HDL) And others …

Grading Information

Grade determinates

Midterm Exam

~20% ~50% ~30%

Monday, Nov. 13th, in class.
•Final

Exam

TBD
•Project

Due to Dec. 15.

6

Introduction to Digital System Design

7

Outline
1.

Why Digital?

2.
3.

Device Technologies
System Representation

4.
5. 6.

Abstraction
Development Tasks Development Flow

Chapter 1

8

Advantages
 Advantage

• •

of digital devices

Reproducibility of information Flexibility and functionality: easier to store, transmit and manipulate information Economy: cheaper device and easier to design

 Moore’s
• • •

law

Chips double its density (number of transistor) in every 18 months Devices become smaller, faster and cheaper Now a chip consists of hundreds of million gates And we can have a “wireless-PDA-MP3-playercamera-GPS-cell-phone” gadget very soon
Chapter 1 9

Classification of device technologies
 Where
• •

customization is done:

In a fab (fabrication facility): ASIC (Application Specific IC) In the “field”: non-ASIC

 Classification:
• • • •


Full-custom ASIC Standard cell ASIC Gate array ASIC Complex field programmable logic device Simple field programmable logic device Off-the-shelf SSI (Small Scaled IC)/MSI (Medium Scaled IC) components
Chapter 1 10

What an FPGA?

A field-programmable gate array is a gate array that can be reprogrammed after it is manufactured  programmable logic device. FPGA vendors: Xilinx, Altera, Lattice Semiconductor, Actel, Cypress, Atmel and QuickLogic. - FPGAs are generally slower than their ASIC counterparts, - draw more power. + shorter time-to-market, + lower development costs. Applications of FPGAs include DSP, Aerospace and defense systems, ASIC Prototyping, Medical imaging, … VHDL is used to define the behavior of the FPGA.  When compiled, will generate a net list, that can be mapped to the actual FPGA architecture.  When done the binary file generated is used to (re)configure the FPGA device.
Chapter 1 11

      

Cost
 Types
• • •

of cost:

NRE (Non-Recurrent Engineering) cost: one-time, per-design cost Part cost: per-unit cost Time-to-market “cost” loss of revenue

 Standard

cell: high NRE, small part cost and large lead time low NRE, large part cost and small lead time
Chapter 1 12

 FPGA:

Graph of per-unit cost

Chapter 1

13

Summary of technology

 Trade-off

between optimal use of hardware resource and design effort/cost
single best technology Chapter 1
14

 No

Descriptions/abstractions levels:
 Behavioral/Algorithm
• •

:

Describe functionalities and i/o behavior Treat the system as a black box

 Register
 

Transfer Level (RTL)

Has an explicit clock. All operations are scheduled to occur in specific clock cycles, but there are no detailed delays below the cycle level.

 Structural
• •

view:

Describe the internal implementation (components and interconnections) Essentially block diagram Chapter 1
15

Descriptions/abstractions levels:

Gate level description

Consists of a network of gates and registers instanced from a technology library, which contains technology-specific delay information for each gate.

Chapter 1

16

Level of abstractions

Algorithms are unsynthesizable.
RTL is the input to synthesis.

gate level is the output from synthesis.
The difference between these levels of abstraction can be understood in terms of timing.

Chapter 1

17

data file

process

Development

Synthesis

Physical Design

Verification

Flow

RTL description

1

1

testbench

synthesis

3

simulation

2

netlist

delay file

placement & routing

5 4

simulation

4

configuration file

delay file

device programming

7

simulation/ timing analysis

6

FPGA chip

8

Chapter 1

18

Synthesis
A

refinement process that realizes a description with components from the lower abstraction level. resulting description is a structural view in the lower abstraction level of synthesis:
   

 The

 Type

High-level synthesis RT level synthesis Gate level synthesis Technology Chapter 1 mapping
19

Physical Design
 Placement

and routing

Refining from structural view to physical view Derive lay out of a netlist

 Circuit

extraction:

Determine the wire resistance of capacitance

 Others

Derivation of power grid and clock distribution network, assurance of signal integrity etc.

Chapter 1

20

Verification
 Check

whether a design meets the specification and performance goals.
the correctness of the initial design and the refinement processes aspects

 Concern

 Two

Functionality Performance (timing)

Chapter 1

21

Method of Verification
 Simulation
 

spot check: cannot verify the absence of errors Can be computation intensive

 Timing

analysis verification

Just check delay

 Formal
 

apply formal math techniques determine its property E.g, equivalence checking
Chapter 1 emulation 22

 Hardware

Testing
 Testing

is the process of detecting physical defects of a die or a package occurred at the time of manufacturing and verification are different tasks. for large circuit

 Testing  Difficult

Need to add auxiliary testing circuit in design

E.g., built-in self test (BIST), scan chain etc.

Chapter 1

23

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