Verilog Basics 5 Functions and Tasks

Digital System Design

Verilog: Functions and Tasks
Dr. Bassam Jamil

Topics
 Functions

 Tasks

2

Tasks and Functions

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Tasks and Functions Syntax
Task syntax:
task task_name;

May contain any number of inputs/outputs/inouts May contain timing control: @,#,wait

input, output, and inout declarations local variable declarations procedural_statement or statement_group
endtask

Function syntax:
function [size_or_type] function_name;
   

Must have at least one input No outputs/inouts No timing control

input declarations local variable declarations procedural_statement orstatement_group
endfunction
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size_or_type is optional

Tasks and Functions: Example
Task
task read_mem; //TASK DEFINITION // Declaration order ermines order of // arguments when task is called input [15:0] address; output [31:0] data; begin read_request = 1; wait (read_grant) addr_bus = address; data = data_bus; #5 addr_bus = 16'bz; read_request = 0; end endtask

Function
function [7:0] GetByte; DEFINITION //FUNCTION

// Declaration order ermines order of
// arguments when task is called input [63:0] Word; input [3:0] ByteNum;

integer Bit;
reg [7:0] temp; begin for (Bit=0; Bit<=7; Bit=Bit+1)

temp[Bit] = Word[((ByteNum-1)*8)+Bit];
//A function returns the value assigned GetByte = temp; end

endfunction
// Task call read_mem (PC, IR); // Function call this_byte = GetByte(data,4);

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More Function Example

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Function: local variable

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Function: local variable

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Task Example: Passing by Reference

endmodule
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Task Example

end endmodule 10

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