Digital System Design Verilog: Running The Simulator

Dr. Bassam Jamil

Outline
 What

is a Verilog simulator?
Issues the Tool

 Installing  Invoking  Main
 

Steps to run your first Verilog design

Directory Library


Compile Run

 Commands

and scripts
2

Verilog Simulator
 It

is a software package to run Verilog HDL
 

 Examples

Mentor ModelSim/SE Synopsys VCS


 

Cadence Incisive Enterprise Simulator Aldec Active HDL …etc

3

Installing Software
 First

Install the Software Correctly
the Licensing Issues

 Address
 

Install Software Save license file into your local disk

 

Update environment variables to point to the license file Start the license program

 Details

varies from tool to tool

And from version to version.

4

Before Running Modelsim
 The

following are very simple steps to get you started
more information, you should look at the lab exercise and help/manual pages

 For

 Be
  

careful
Modelsim (like any tool) has different versions. Most of the time the tool buttons/options change from version to version So, you might see might see in a manual/lab an option/window/button which does not exist in your version.
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Running Modelsim: Envoke The Tool
 Create
 Invoke

directory to have your work: WORK_DIR
Modelsim

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Modelsim

7

Running Modelsim: Change to WORK_DIR

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Running Modelsim: Create Lib

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Running Modelsim: Create Lib

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Running Modelsim: Compile

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Running Modelsim: Compile

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Running Modelsim: Compile
 If

compile is correct, you should get something like this message in the transcript window:

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Running Modelsim: Simulate

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Running Modelsim: Simulate

In the start simulation window, select the top design.
Then press OK.

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Running Modelsim: Simulate
 Once

simulation run links all complied modules correctly, should get in the transcript window:

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Running Modelsim: Simulate
 Now,

your simulator is ready to advance simulation time.
are multiple options to advance time. For example, the command that runs the sim to the end.

 There

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Running Modelsim: Simulate
 Pressing

the run button in the previous slide will cause the simulation to run to the end.

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Running Modelsim: Waveforms
 To

add waverforms:
After starting the simulation
• Simulation should be without optimization options


Before the run command You should select your waves

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Running Modelsim: Simulate
 Start

Adding Signals to Waveforms

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Running Modelsim: Simulate

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Script Commands
Function Command

Change Dir Create Lib

cd {Z:/HU/Courses/Digital System Design Using Verilog_VHDL/Verilog/Project/VerilogExa} vlib my_design vmap my_design my_design
vlog -reportprogress 300 -work my_design \ "Z:/HU/Courses/Digital System Design Using Verilog_VHDL/Verilog/Project/VerilogExa/my_design.v" vsim -voptargs=+acc \ my_design.my_design add wave -radix hexadecimal sim:my_design/c run 120 ns

Compile

Sim Add wave Run

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Final Remarks
 Experiment
 Read  In

with other examples

man/help pages

week, you might be a better expert than me.

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