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Edited by Bill Travis and Anne Watson Swager
D1 (MURS120) MBRS130 + + 100 F + 5V AT 1A 300 D2 MBRS130 (MURS120)
Push-pull driver provides isolated 5V at 1A
Ron Young, Maxim Integrated Products, Sunnyvale, CA
he circuit in Figure 1 converts a regulated 5V input to an Figure 1 isolated 5V output with 1A current-output capability. IC1, a pushpull transformer driver, powers a pair of cross-coupled power MOSFETs in a flipflop-like configuration. In turn, the MOSFETs toggle the primary winding of a forward transformer. The transformer’s secondary output, after rectification and filtering, provides the isolated 5V supply. Because the output voltage is unregulated, its voltage tolerance depends on the input-voltage range and the range of load current. With Schottky rectifiers, such as the MBRS130 for D1 and D2, the circuit delivers 5V 10% at 700 to 1000 mA from a 5V 5% input with 80% efficiency (Figure 2). Using ultrafast-recovery silicon rectifiers, such as the MURS120, the circuit delivers 5V 10% at 200 to 500 mA from a 5V 5% input, with 77% efficiency. (DI #2502)
T1 (COILTRONICS) CTX03-14439
5V 100 F
1 2 3 4 MAX253 IC1
8 7 6 5 0.1 F 5V
A simple circuit produces a 5V, 1A isolated output from a 5V regulated input.
To Vote For This Design, Circle No. 366
Push-pull driver provides isolated 5V at 1A ..........................................101 Circuit programs Atmel AVR Cs ............102 Circuit adds latch-off current limit to regulator ..........................................104 Dual power supply delivers 8A with no heat sinks..................................106 Power switch provides soft start ..............108 Circuit eliminates PC echoes ....................110 Clamping circuit dissipates minimal power..............................................112 Piezo crystal monitors liquid level............112 Switch intelligently controls current ........114
90 SCHOTTKY 80 ULTRAFAST 70 60 EFFICIENCY (%) 50 40 30 20 10 0 100 200 300 400 500 600 700 800 IOUT (mA) 900 1000 1100 1200 1300 MURS120 MBRS130
The efficiency of the circuit in Figure 1 depends directly on the forward drops of the output rectifiers.
March 30, 2000 | edn 101
and controls all programming tasks.ednmag. Note that you need pullup resistors for the AT89C4051 port pins P1. 2000 + 15 + 28 MISO2 27 MOSI2 26 25 24 23 22 21 MISO3 MOSI3 VCC3 SCK3 2 3 C8 4.and eight-pin Cs.design ideas Circuit programs Atmel AVR Cs Guo-Yin Xu. TX tmel AVR Cs feature an enhanced RISC architecture that purportedly offer the highest MIPS-per-milliwatt capability in the 8-bit C market.7 are for 40-pin Cs.2 to P3. and the signals from P3.or eight-pin Cs.6 P1.4 9 P3. The programmer uses only three chips. XuMicro. using this easy-to-build programmer. it uses one more resonator. 102 edn | March 30.4 to P1.7 P1. The AT89C4051 C (IC2) works with the 11. For instance. The circuit uses two 4-MHz ceramic resonators: CR2 for 20-pin Cs.0 and P1. you must first pull the Reset and SCK pins low (Reference 1). Jumper JP1 controls the 5V power supply for 20. the signals from P1. the C must execute a programming-enable instruction before it can execute any program of erase instructions.0592 MHz GND 10 Exploit the power of Atmel’s AVR Cs.3 are for 20- pin Cs.1 F 20 1 + R1 330 C3 4. Power comes from a 9V wall cube and the 78L05 linear regulator.5 are for eight-pin Cs.2 C7 4. and CR/CR3 for 40.7 F P1. CR2 that’s hard-wired to pins 4 and 5 of the VR1 5V 9V DC 78L05 + C1 10 F C2 0. Hence.2 RESET3 17 18 19 20 5V 5 XTAL1 7 P3.7 F LED1 P1. VR1.1 12 6 CR/CR3 4 MHz CR2 4 MHz VCC RST IC2 AT89C4051 19 18 17 16 MOSI MISO SCK RESET R2 10k R3 10k VCC 1 2 3 4 5 6 7 8 9 10 15 14 13 RESET2 11 12 13 14 15 16 P3. The circuit exploits the fact that all AVR Cs A have a built-in SPI (serial-peripheral-interface) port that you can use to effect serial programming. the control signals from the AT89C4051 port pins P1.7 F P1. You should remove the jumper when programming 40-pin Cs. Houston.7 11 5V P3. LED1 indicates the programmer’s status.0592-MHz oscillator. because these pins normally serve as analog-signal-input lines.com .7 F 16 2 4 + C5 10 F P1. Because the wires for the resonators should be as short as possible. master-output/ slave-input (MOSI). and master-input/ slave-output (MISO) pins. which use a hard-wired connection to the 5V power.3 8 P3.1 F JP1 Figure 1 TO PC SERIAL PORT COM1 2 3 IC1 3 MAX232 5 J1 7 8 9 10 6 5 OSC1 11.0 to P1.1. and the eight-pin AT 90S2323/2343. you need four pins to control the programming of a C. It connects to the host PC’s serial port via a MAX232 RS-232 transceiver.3 P1.5 P1. the 20-pin AT 90S1200/2313. to place a C in serial-programming mode.5 1 2 3 4 5 6 7 8 9 10 GND 1 2 3 4 8 7 6 5 20 19 18 17 16 15 14 13 12 11 40-PIN ZIF SOCKET 40 39 38 37 36 35 34 33 32 31 30 29 VCC2 SCK2 C9 0.4 C4 + 10 F 1 C6 + 4. Figure 1 shows an easy-to-build AVR C-programming circuit that can program the 40-pin AT90S4414/8515. the circuit uses no switching or jumping mechanisms. Then.0 RX TX www. IC1. Instead. The AVR data book requires that. The SPI port uses only the system-clock (SCK).
design ideas contains the host-PC communication program. 2000 www. 20-pin C pins 14 and 15 of the ZIF socket. the programmer also needs associated software. You can initiate a reset by applying a fast logic high to the reset line.” Circuit Cellar Magazine.3V 6. forcing a highcurrent power supply to latch off if a sustained fault condition exists can minimize the likelihood of damage to the pc-board traces and the power devices in the supply. AVRP1.com. R7. the latch-off circuit begins to take over. If an overcurrent condition exists.ednmag. www.” Atmel Corp. burned into the AT89C4051 C by using an 8X51 EPROM/flash C programmer (Reference 2). Xu. an LTC1430 PWM controller. Milpitas.EXE. After a time interval depending on the values of R5 and C12. 2.1 F E1 + C4 1 F C + 1 330 F 6. You can modify the circuit to work with any other controller. (DI #2504) References 1.3V AT 7A E2 C15 0.3V OUTPUT 3. 367 Circuit adds latch-off current limit to regulator Craig Varga. April 1998. which discharges C12. The currentlimiting feature of the IC operates by sensing the voltage across the high-side MOSFET and compares it with a threshold voltage developed across R3.com .BIN. 368 12V Figure 1 C1 330 F 6.ednmag. such as the LTC1553. Guo-Yin. holds the finished AVR-programmer software. In addition to the hardware in Figure 1. The only timing requirement is that the latch-off delay be greater than the soft-start rise time at turn-on. allowing the R1 10 regulator to restart. having the soft-start function. Q5 turns off and pulls the shutdown pin low.1 F R3 16k R2 51 Q1 IRF7801 R5 15k RESET C6 0. “8-bit RISC Microcontrollers Data Book.3V OVERCURRENT LATCH-OFF CIRCUIT C8 0. R10. This connection does not disturb the programming of 40-pin Cs. but the circuit in Figure 1 does. an internal current source starts to discharge the I soft-start capacitor. If you don’t need the reset function.3V 5V C2 C3 + 330 F + 330 F 6. Circle No. When the voltage across C9 decreases to a couple of volts below VCC. You can then initiate a restart by recycling the 5V input power. A binary file. thereby turning off the controller.3V + C8 330 F 6. To Vote For This Design.01 F R9 2N3904 20k C12 1 F C11 220 pF R8 13k C14 1500 pF + C13 22 F 35V R10 10k R11 10k You can add a latch-off current-limiting feature to a simple pulse-width-modulation controller by adding a few external components. C6 and C7 provide a differential pulse to the base of Q4. Linear Technology Corp. you can eliminate C6. A DOS file. CA n many applications. the circuit remains latched in the off state. Pulse-width-modulation (PWM)-control circuits provide no latch-off feature. Click on “Search Databases” and then enter the Software Center to download the file for Design Idea #2504.4 H + D1 MBRS130 C7 330 F C10 330 F 6. C9.3V IC1 LTC1430 15 PV CC2 14 VCC 11 FSET 12 IMAX 8 SD 10 COMP 9 SS 4 SGND PVCC1 G1 IFB G2 PGND SENS +SENS FB 2 1 13 16 3 5 7 6 R6 1k Q3 IRF7801 L1 2. AVRP1.01 F R7 10k Q5 Q4 2N3904 R4 10k Q2 TP0610T C9 0.3V 6. (DI #2503) To Vote For This Design. Circle No. Q2 turns on and begins to source current. the regulator can never start. August 1999. Otherwise. Because this action internally grounds the soft-start pin (to allow a normal soft-start cycle at turnon). “8X51 EPROM/flash microcontroller programmer. At this point. and Q4. 104 edn | March 30. You can download these routines from EDN’s Web site. The circuit is based on IC1. charging C12.
The internal current comparator senses inductor current by the voltage developed across the current-sense resistor.1 F C14 TO C16 + 330 F 35V 3 VIN2 5. current-mode synchronous-buckcontroller. Q1. Q2.7 F 10V LB0 C6.7k R4 11.2 H R6 0. To avoid shoot-through current.1 F 0. 106 edn | March 30. C1.0k 100 pF 1 F 10V VOUT2 3.1 F 914 C1 1000 pF 10 10 1 1000 pF 2 SENSE 1 3 4 5 82 pF 6 7 8 VOSENSE1 ITH1 POR2 COSC SGND LBI LBO SFB1 ITH2 VOSENSE2 SENSE 2 SENSE+2 IC1 LTC1438-ADJ SENSE+1 RUN/SS1 BOOST 1 TGL1 SW1 VIN BG1 INTVCC PGND BG2 EXTVCC SW2 TGL2 BOOST 2 RUN/SS2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.3V at currents as high as 8A. 1000 pF C7. C8 TO C10=KEMET T495X337M006AS.ednmag. inductor current flows through the commutating diode.3V outputs.8V CMDSH-3 0.01 R8 35. IC1. VOUT1.0k 1000 pF 100 pF VOUT1 5V/8A 1 F 10V 4.1 F CMDSH-3 Q2 L1 5.1 F 50V VIN1 5.1 F NOTES: C11 TO C13.1 F 10 0.design ideas Dual power supply delivers 8A with no heat sinks John Seago. The circuit uses separate regulator circuits for each output voltage. Q3=SILICONIX Si4420DY. 3 C8 TO C10 330 F 6V. During this dead time. Milpitas. Loop-compensation components R1. IC1 regulates the 5V output.7k 1000 pF 1 F + 0. L1.1 F Q4 L2 5. Q3 and Q4 are the top and bottom Figure 1 47k 0. The 3. and C2 control the frequency response of the error amplifier. to the load. a short dead time occurs before each MOSFET turns on. R2. both circuits are identical except for the lower feedback resistors. C3 TO C5. Q1.F capacitors in parallel—integrate and filter the energy pulses from Q1 to generate the dc output. which produces VOUT2. R6=IRC LRF2512-01-R010-J.2k POR2 C2 2200 pF C11 TO C13 + 330 F 50V 3 1M 280k R3 35.3V output voltages. by T controlling the duty cycle of the top MOSFET for VOUT1. is equal to the output voltage. 2200 pF R5 2. which determine the 5 and 3. After Q1 turns off. 2000 + www.3V outputs. R4 and R7.2k 47k 9 10 11 12 13 14 1000 pF MMSD914 10 R7 20. functions exactly like the 5V regulator. D2=MOTOROLA MBRD835L.com . 3 Q1 R2 0. two-output. The buck inductor and output capacitors C3 to C5— three 330. each output delivers 8A.3 regulator. the bottom MOSFET for VOUT1.3V/8A 0. C14 TO C16=SANYO 35CV330GX. L2=PULSE ENGINEERING PE-53700.5 TO 2. The circuit uses a fixed-frequency.01 10 0.5 TO 28V R1 2.2 H D1 Q3 D2 C3 TO C5 330 F + 6V. respectively. However. Q2. to regulate both 5 and 3. CA he circuit in Figure 1 is a high-current dual supply that provides 5 and 3.1 F MMSD0. R2. Feedback resistors R3 and R4 connect IC1’s internal error amplifier to the output. D1. D1. A single IC regulates both 5 and 3. turns on to conduct inductor current to the load. Q4=SILICONIX SUD50N03-10. L1. Linear Technology Corp. so that average input voltage to the buck inductor.
and on/off control. Pulling both RUN/SS pins low shuts down IC1. and limits the input current to 16 A. the collector voltage falls to 4V and triggers the delay timer. You must use a heat sink for the power MOSFETs. both at a rate of 0. C6. C8. CO n the circuit in Figure 1. C9. turns off all internal circuitry. Feedback resistors R7 and R8 connect the error amplifier to the output. load power is from 0 to 90% of maximum (600W). and C7 are the loop-compensation components. the POR2 pin is low. This smart switch provides a small initial current for loads with a normally high inrush current. When the emitter current approaches zero. At startup. The value of the capacitor connected to the RUN/SS pin determines the output voltage delay and the inductor-current ramp time.5% from nominal. The POR2 pin goes low if the output voltage falls 7.8k CW 10k 3W 2N3906 47k 3 8 4 50k 5 TLC555CP 47 F + 25V 1N5242B 100k 470k 2 1 6 7 0. The low-battery comparator in IC1 flags a low-input-voltage condition.com . IC1 includes a complete power-onreset circuit. 370 Figure 1 N 1N4005 1N4005 RLOAD L IRFP264 IRFP264 10 10 6. the limit for maximum delay is ap- proximately 7 msec.N=115V AC AT 60 Hz.ednmag. and R6 is the sense resistor. R5. Pulling a RUN/SS pin low turns off that output voltage. Normally. and L2 is the buck inductor. 369 MOSFETs.5 sec/ F. This pin goes high 65. and C10 make up the output capacitor. (DI #2506). 108 edn | March 30. respectively. Colorado State University. Circle No. 2000 www. Thus. Because the circuit generates the 12V operating voltage only during offtime. The bridge simultaneously delivers the crossing signal I to 2N2906 common-base comparator. Fort Collins. Circle No. The circuit in Figure 1 has some features that add versatility. To Vote For This Design.You trim the delay by selecting a resistance value from Pin 5 to raise (pins 5 to 8) or lower (pins 5 to 1) the upper comparator threshold at Pin 6. D2 is the commutating diode.design ideas high but goes low when the input voltage is low. (DI #2494) To Vote For This Design. series-connected MOSFETs turn on the line voltage near the zero-crossing point and off when the 555-timer delay lapses. output-current soft-start. 3W resistor. Positive-going pin 3 of the 555 also removes the trigger threshold by coupling to the diode OR gate. That delay ranges from 1 to 7 msec. Each output has a RUN/SS pin that provides output-voltage delay.1 F NOTE: VL.536 oscillator cycles after Channel 2’s output voltage reaches 95% of its programmed value. initiating gate drive to the switches. the LBO pin is Power switch provides soft start John Haase. The MOSFETs’ body diodes and the 1N4005 diodes form a full-wave bridge rectifier that provides a floating 12V-dc level via the 10-k .
22 F R8 360k R11 2. R1 and R2 provide biasing for both the electret microphone and the Q1 emitter follower. The absence of an input allows C6 to charge within approximately 40 msec to the IC1B threshold. Q3 compensates for the switching-circuit losses and buffers the output. The loudspeaker output of the PC serves to mute the microphone input.4k J2 R12 10k TO PC MIC INPUT 12V R15 10M J3 X R14 22k C5 0. passing the threshold of comparator IC1B. EEC. Loudspeaker voltage levels as low as 15 mV from the PC cause comparator IC1A’s open-collector output to discharge C6 via R18.ednmag. acts as a switch that opens with the application of a gate voltage greater than L To Vote For This Design.design ideas 6V and closes with a gate voltage of 0V. NY ong-distance-telephone services available via the Internet often require the PC user to wear headphones of a headset to prevent echo caused by the microphone’s picking up the loudspeaker outputs. 371 Figure 1 R1 27k Q1 2N3904 C2 0. The circuit in Figure 1 eliminates the echo while using the existing PC microphone and speakers for a comfortable conversation. The interface is between a standard electret condenser microphone and the microphone input of the PC. Circuit eliminates PC echoes Hans Krobath. Circle No. Any input from the PC’s loudspeaker output discharges C6.com . produces a high output that turns off Q2. LED D2 lights whenever no loudspeaker output is present. (DI #2508). The falling voltage of C6. controls the Q2 FET switch. 110 edn | March 30. IC1. producing a low-level output and turning on Q2.1 F R13 1k R19 IC1A 8 LM393N 2. which acts as low-level retriggerable monostable multivibrator. You should set R1 such that approximately a 100-mV p-p microphone input just triggers IC1. 2000 www.1 F Q3 2N3906 R10 2k R4 10k FROM PC MIC R2 20k R5 1M C4 0. as indicated by the LED’s extinguishing. D1 reduces the Q2 gate voltage to 0V when the IC1B output saturates.7k TALK D2 LED 7 D1 1N4148 IC1B 4 LM393N R25 150k C6 0.2M 3 + 1 2 R18 4 1k R16 20k R17 20k R20 220k R21 220k 5 + 6 8 R22 10M R23 10k R24 4. R9 and R10 provide an appropriate input impedance to Q3 and limit the output to 5V p-p.022 F FROM PC SPEAKER SET TO 100-mV P-P THRESHOLD Eliminate annoying echoes from loudspeaker-microphone feedback by using this simple circuit. Q2. a p-channel FET. This level prevents any noise from the PC’s loudspeaker output from falsely triggering the monostable multivibrator. thus preventing any possible damage to the PC’s microphone input.5k Q2 2N5460 S D R7 10k R6 1M C3 0. Nesconset. and the microphone input to the PC becomes enabled.1 F R3 1k 12V C1 + 150 pF J1 R9 1.
design ideas Q2). The charge pump generates a voltage equal to voltage of VR1. and C3. thereby reducing reference. the pressure acting on the surface of the crystal To Vote For This Design. The first counter of the 8254. The piezo crystal. IGCAR. India he simple and inexpensive circuit in Figure 1 monitors the liqFigure 1 LIQUID uid level in a container.com . The variation in the liquid level. consisting of Q1. the pass 8 R3 VR1 7 4 element. D2. The counts in the air medium serve as a reference. Tamil Nadu. The first counter allows the 0th counter to count CS WR RD A0 A1 for a period of 1 sec. the circuit functions as a source follower. on the height of the liquid level.medium reference gives you the height of Circle No. and the output voltage is approximately 3V lower than VR3’s breakdown voltage. operates as a + C2 6 3 saturated switch. (DI # 2507) clock frequency with respect to the air- T 112 edn | March 30. Torrance. Allied Signal Aerospace. R1. and R2. (DI #2499) Clamping circuit dissipates minimal power Carlisle Dolland. pro1k 1k OUT 1 FIRST COUNTER 56 pF grammed in Mode 0 as an event count8254 er. Depending By measuring frequency shifts.14 MHz) when it is in free air. In this mode. the load current determines the dissipation in Q2. C2. increases. 6. the output voltages greater than the breakdown put voltage is VOUT VIN IOUT (RON of T VOUT D3 To Vote For This Design. 2000 www. 373 crystal clock frequency. The crystal-based clock 0TH COUNTER GATE 0 drives the 0th counter in an 8254 programmable-counter/timer chip.ednmag. For input voltages lower the output of the linear regulator for in. drives a charge pump comprising This circuit clamps transient voltages and dissipates minimal power. CLOCK 1 programmed in Mode 1 as a retriggerable SECOND COUNTER one-shot whose time period is 1 sec. determined by VR3. 372 Piezo crystal monitors liquid level J Jayapandian. CA Q2 he circuit in Figure 1 D S is a quasi-linear regulator. Q2. controls the gate of the 0th counter. The linear Figure 1 regulator. It functions as a C3 Q1 G source follower for input VIN D2 R6 voltages greater than a preset VR3 level. this circuit provides a measure of liquid level.than VR1’s breakdown voltage. Circle No. R6 and VR3 dissipate the energy the charge pump supplies. For input voltages that exceed VR3’s breakdown voltage by approximately 3V.14 MHz CRYSTAL VCC Schmitt trigger. carefully mounted at the bottom surface of the container. D3. R1 R2 R4 For input voltages lower R5 than the preset level. a ICM7555MTV C1 1 charge pump. receives it activation from the 74HCT14 hex DATA BUS 6. The crystal generates stable clock pulses according to its specifiCONTAINER CLOCK 0 74HCT14 cation (for example. VR1. During transients. The circuit 2 _ IC1 comprises an oscillator. and a linear regulator. The circuit dissipates minimal power.
The concycles. EDN Magazine 275 Washington St. charging C1 to the peak ac or dc voltage. determined by vote of readers. the T Design Idea Entry Blank Entry blank must accompany all entries. serve as two legs of a diode bridge.current ratings.9%. but current does not flow through power control circuit. the con.troller can optionally synchronize to the biased. or editor gives written permission for publication elsewhere. control-block supply current continues to flow through the load when the load the MOSFET’s on-resistance. Additional $1500 Cash Award for annual Grand Prize Design. by circling the appropriate number on the reader inquiry card. Q2 Q1 VCC 2N7002 The switch uses the MOSFETs’ parasitic 2N7002 body diode to its advantage. The circuit has low inserWhile the load is turned on. The relatively small With a control circuit of your choice.2505) To Vote For This Design. and must have no patent pending. To: Design Ideas Editor. Maple Grove. conduct in either direction.) Design entered must be submitted exclusively to EDN. Current flows through the 0 load and the bridge.travis@cahners. Fully annotate all circuit diagrams. 374 loss is equivalent to the loss in two times and a control-circuit current of 1 mA. you can obtain intelligent control of ac or dc current. Name Title Phone E-mail Company Fax Entry blank must accompany all entries. For example.cuit must periodically recharge C1 by to control high-power loads. must not have been previously published (limited-distribution house organs excepted). selected among biweekly winners by vote of editors. along C1 C2 V AC with D1 and D2.ednmag.with a high-current load and a micro. The maximum ac zero-crossing point as shown. for example. Newton. The circuit “steals” its power by CROSSING INPUT turning off the load at a low duty cycle. The cir. Signed Country Design Idea Title Your vote determines this issue’s winner. Vote now.ing MOSFETs and diodes with higher tion loss because of the MOSFET’s bidi.99% and thermostats.com or send a disk. The control block con. Silent Knight LLC. On alternating low the duty cycle to go as high as 99. Exclusive publishing rights remain with Cahners Publishing Co unless entry is returned to author. $100 Cash Award for all published Design Ideas. I agree to abide by the rules of the Design Ideas Program. MN V DC he circuit in Figure 1 can intelligently control ac or dc current Figure 1 VZC D1 when connected in series with D2 D1N4002 OPTIONAL ZEROVDUTY D1N4002 a load. and must have been constructed and tested. Please submit text and listings by e-mail to b. Many apnects power to the load by turning briefly turning off the load .design ideas Switch intelligently controls current Jim Hartmann. The insertion TROL ILOAD). While the RLOAD VREG CONTROL + MOSFETs are off. the body diodes. An additional $100 Cash Award for the winning design of each issue. you can adapt the circuit rectional nature. MA 02458 I hereby submit my Design Ideas entry.plications are possible—lamp dimmers MOSFETs Q1 and Q2 on. You can al. www. (DI # the body diode because the MOSFET can duty cycle is approximately ILOAD/(ICON. Design must be original with author(s). 2000 .com Address ZIP Date Social Security Number (US authors only) 114 edn | March 30. with a 1A load Circle No. (A separate entry blank for each author must accompany every entry.trol block draws current from C1. must not be patented. In submitting my entry. either Q1 or Q2 becomes reverse. By choosis turned off. maximum duty cycle is 99.
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