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What is CRP (Clock Reconvergence Pessimism)? As the "convergence" means (dictionary) "the occurrence of two or more things coming together". So we can assume that its also related to 2 clock path coming together. (Please refer the another blog for understanding the Clock path- Static Timing Analysis Basic: Part1 "Timing Paths") Now lets assume 2 flip-flop circuit as shown in the figure.
Clock Reconvergence Pessimism As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path (Please refer Static Timing Analysis Basic: Part1 "Timing Paths" for defination of Launch and Capture Clock path) share a common segment in the clock tree till the point know as "common point" (in above fig you can see that "common point" is written as "The clock path common to both flops till this point"). The 2 clock path diverse from that point. As we know that every cell has two type of delay as a part of its specification, "Max Delay" and "Min delay". There are several scenario in the design where we use either max delay or min delay of a particular cell. Such as best case analysis (BC), worst case (WC) analysis, OCV (on chip variation) analysis during timing analysis. Lets consider that max delay and min delay of the common segment is as Max delay=1.2ns Min Delay=1.0ns. Now, if during timing analysis a condition arise where you have to use max delay for one timing path and min delay for another timing path (such as during OCV analysis), you have to use 2 different values for a common path. But practically same set of cells can't be behave different for different clock path. For example, for a setup check, it uses the maximum delay for the launch clock path (1.2ns + delay because of rest of the circuit in the launch path) and the minimum delay for the capture clock path (1.0ns + delay because of rest of the circuit in the launch path.
By default . 0. . but an analysis could consider both the shorter and longer paths for one setup or hold check. Different Tools have different variable for this. This conflicts with our timing analysis method described above since we utilise two sets of delay values at the common point. Lets discuss one of that. is the difference between max and min delay at the common point in the clock network.(minimum clock delay) Note: Above situation is identical for hold checks also.In a physical design.2 ns) is called "clock reconvergence pessimism". The amount of pessimism due to this effect (in this example. most of the tools (EDA tools for timing calculation) disable this feature (automated correction). The value of this pessimism. How to remove CRP ? Automated correction of this inaccuracy is called clock reconvergence pessimism removal (CRPR). Therefore our timing report contains artificially introduced pessimism that is derived from our usage of max and min delay for the launching and capturing paths along this common portion of the clock network. For that please refer the USER GUIDE or MANUAL of corresponding tool. Please see the following fig. Thus there will be a single value of delay to the common point that will be propagated to both the launching and capturing clock paths. Similar type of situation can arise in different type of circuit also. Schematic of a reconvergent clock The two clock paths that feed into the multiplexer cannot be active at the same time. however. By you can enable this feature by setting one/more variables during timing analysis. Clock reconvergence pessimism = (maximum clock delay) . This results in different launch and capture clock path delays and the consequent pessimism. the cells along the common portion of the clock tree cannot simultaneously achieve their maximum and minimum delay values.