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Assignment 2

Group K EE08B046 Chaitanya PRK EE08B051 Manoj Sukhavasi EE08B053 Vikas Chaganti 07/02/2012
Abstract This report is supplement to the verilog les submitted online. This report explains in detail about design strategy, test strategy and synthesis report of the the verilog codes submitted.

1. Extended Find Second One(EFSO):


a)
We synthesized the FSO in the previous assignment. It synthesized without any errors, but we got some warnings which were listed below. WARNING:Xst:646 - Signal <temp2> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <temp1> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <so> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal <fo> is assigned but never used. This unconnected signal will be trimmed during the optimization process. These warnings are due to temporary variables we used inside always block. Synthesis tool is going to trim all unnecessary variables for optimization.

b) FSO
Our design is synthesizable, so we didnt make any changes. Synthesis Report Summary: Number of 4 input LUTs : 25 Number of bonded IOBs : 10

Extra Logic 6-bit adder : 1 7-bit adder : 1 We intended 2 7-bit adders from the code but simulator optimized one 7-bit adder to 6-bit adder.

c) EFSO
Design Strategy: 1) Find logical AND between input and its twos compliment to get rst one position 2) Double the number obtained above and add it to negation of input 3) Find logical AND operation between input and number obtained above 4) Use an encoder to convert above number into 4.bit binary number that tells position of the second one. We intended two 15-bit adders and four 15to1 MUX. Test Strategy: We gave some random numbers to test the correctness of the code.

d) EFSO
Synthesis Report Summary: Same warnings are generated as in FSO. Number of 4 input LUTs : 76 Number of bonded IOBs : 20 Extra Logic 14-bit adder : 1 15-bit adder : 1 We intended 2 15-bit adders from the code but simulator optimized one 15-bit adder to 14-bit adder. Comparison of FSO and EFSO: No of IOBs in EFSO are doubled compared to FSO. It is expected as no of IOs doubled.No. of LUTs have increased more than double, since some LUTs are used in linking the 4 input LUTs.

2. Sequence Generator:
Design Strategy: The machine designed is a moore machine, as there is no combinational input. The design is a general circular loop for states as states change for every clock

cycle in a circular pattern. State Table: current state Next state output 0 1 2 1 2 9 2 3 0 3 4 7 4 5 13 5 6 15 6 7 11 7 8 5 8 0 1 We have a counter (state) which increments state value. Output changes according to the state value referring the value from ROM. Synthesis Report Summary: Number of 4 input LUTs: 10 Number of bonded IOBs: 6 Extra Logic 16x4-bit ROM : 1 4-bit up counter: 1 (4 Flip-ops were used for the counter) ROM is used to store the numbers required to generate sequence.Counter is used to increment the state value.

3. Pattern Detector:
Design Strategy:
We have to design a sequence detector that outputs a 1 whenever there is a 1101 pattern in the input sequence. Overlapping patterns are allowed. The design is a state machine with 5 states named 0,1,2,3,4. This is a mealy machine with the following state table :

current state 0 0 1 1 2 2 3 3 4 4 Test strategy:

input bit 0 1 0 1 0 0 0 1 0 1

next state 0 1 0 2 3 2 0 4 0 2

output 0 0 0 0 0 0 0 1 0 0

We gave a sequence as an input by changing the signal datain at negative clock (with time period of 10ns) edges so that the value can be seen at the positive edges. We checked the signal detected and it will be 1 for a clock cycle as soon as the input signal completes a 1101 pattern. Synthesis report Summary: Number of 4 input LUTs: 6 Number of Bonded IOBs: 4 Extra Logic: 1-bit registers: 1

4. Majority Spam Detector:


Design Strategy: 1) For every posedge of clock one mail is arrived. 2) I have designed a counter that counts no of clock cycles passed. 3) I have dened tot spam variable that counts total no of spam mails arrived at any point of time 4) Compare twice the tot sapm(ttot spam) with counter value, if value of counter is greater than ttot spam value then assign 0 to majority, else assign 1 to majority. Test strategy: At every positive clock edge i have assigned either zero or one randomly to spam nospambar then checked the output for correctness.

Synthesis Report Summary: No of LUTs : 48 No of IOBs : 4 Extra Logic: 12-bit adder: 1 13-bit adder: 1 12-bit counter: 1 13-bit comparator: 1