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Asynchronous FIFO

Feb-15-2012

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Verilog

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Verilog FPGA

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Asynchronous FIFO Note: This code is written in Verilog 2001.


1 //==========================================

: Asynchronous FIFO (w/ 2 asynchronous clocks). : Alex Claros F. 4 // Date : 15/May/2005. 5 // Notes : This implementation is based on the article 6 // 'Asynchronous FIFO in Virtex-II FPGAs' 7 // writen by Peter Alfke. This TechXclusive 8 // article can be downloaded from the 9 // Xilinx website. It has some minor modifications. 1 //========================================= 0
3 // Coder

2 // Function

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1 1 1 `timescale 1 s 1 s 2 n/p 1 3 1 module a i o 4 Ff 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 # parameter ( DT_IT AAWDH

=8 ,

A D E S W D H= 4 DRS_IT , FF_ET IODPH =( < ADESWDH) 1 < DRS_IT) //Reading port ( output reg [ A A W D H 1 0 DT_IT-:] Dt_u, aaot output reg Epyot mt_u, input wire RaE_n edni, input wire Rl, Ck //Writing port. input wire [ A A W D H 1 0 DT_IT-:] Dt_n aai, output reg Fl_u, ulot input wire Wieni, rtE_n input wire Wl, Ck

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input wire // 3 2 wire wire wire wire reg wire reg


[AAWDH10 DT_IT-:]

Ceri) la_n; Mm[IODPH10; e FF_ET-:] petodort,petodoed NxWrTWie NxWrTRa; Euldrse; qaAdess NxWiedrsE,NxRaAdesn etrtAdesn eteddrsE; StSau,RtSau; e_tts s_tts Sau; tts PeeFl,PeeEpy rstul rstmt;

[DRS_IT-:] ADESWDH10

// 4 1 //Data ports logic: //(Uses a dual-port RAM). //'Data_out' logic: always @ ( posedge R l ) Ck if ( e d n i & ! E p y o t RaE_n mt_u) D t _ u <= M m p e t o d o e d ; aaot e[NxWrTRa] //'Data_in' logic: always @ ( posedge W l ) Ck if ( r t E _ n& ! F l _ u ) Wieni ulot M m p e t o d o r t ] <= D t _ n e[NxWrTWie aai; //Fifo addresses support logic: //'Next Addresses' enable logic: assign N x W i e d r s E = W i e n i & ~F l _ u ; etrtAdesn rtE_n ulot assign N x R a A d e s n = R a E _ n & ~E p y o t eteddrsE edni mt_u; //Addreses (Gray counters) logic:
GaCutrGaCutrpr ryone ryone_W (GaCutotpetodort) .ryon_u(NxWrTWie, .nbei(etrtAdesn, Eal_nNxWiedrsE) .la_nCeri) Ceri(la_n,

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.la_nCeri) Ceri(la_n, .l(Ck CkWl) ) ; GaCutrGaCutrpd ryone ryone_R (GaCutotpetodoed, .ryon_u(NxWrTRa) .nbei(eteddrsE) Eal_nNxRaAdesn, .la_nCeri) Ceri(la_n, .l(Ck CkRl) ) ;

//'EqualAddresses' logic: assign E u l d r s e = ( N x W r T W i e == p e t o d o e d ; qaAdess petodort NxWrTRa) //'Quadrant selectors' logic: assign S t S a u = ( N x W r T W i e A D E S W D H 2 ~^ p e t o d o e d A D E S W D H 1 )& e_tts petodort[DRS_IT-] NxWrTRa[DRS_IT-] assign R t S a u = ( N x W r T W i e A D E S W D H 2 ^ p e t o d o e d A D E S W D H 1 )& s_tts petodort[DRS_IT-] NxWrTRa[DRS_IT-] //'Status' latch logic: always @ ( e _ t t s R t S a u , C e r i ) //D Latch w/ Asynchronous Clear & Preset. StSau, s_tts la_n if ( s _ t t s | C e r i ) RtSau la_n S a u = 0 //Going 'Empty'. tts ; else if ( e _ t t s StSau) S a u = 1 //Going 'Full'. tts ; //'Full_out' logic for the writing port: assign P e e F l = S a u & E u l d r s e ; //'Full' Fifo. rstul tts qaAdess always @ ( posedge W l , posedge P e e F l ) //D Flip-Flop w/ Asynchronous Preset. Ck rstul if ( r s t u l PeeFl) F l _ u <= 1 ulot ; else F l _ u <= 0 ulot ; //'Empty_out' logic for the reading port: assign P e e E p y= ~S a u & E u l d r s e ; //'Empty' Fifo. rstmt tts qaAdess always @ ( posedge R l , posedge P e e E p y //D Flip-Flop w/ Asynchronous Preset. Ck rstmt) if ( r s t m t ) PeeEpy E p y o t <= 1 mt_u ; else E p y o t <= 0 mt_u ;

8 1 8 4

19 0 10 1 1 1 endmodule 1

You could download file aFifo.v here

1 //========================================== 2 // Function 3 // Coder

: Code Gray counter. : Alex Claros F. 4 // Date : 15/May/2005. 5 //=======================================


6 7 `timescale 1 s 1 s n/p 8 9 module G a C u t r ryone 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 1 2 2 2 4 2 5 2 6 2 7 2 8 2 9 # parameter ( ( output C U T R W D H= 4 ONE_IT ) [ONE_IT-:] CUTRWDH10 GaCutot ryon_u, Eal_n nbei, Ceri, la_n Ck; l) [ONE_IT-:] CUTRWDH10 BnrCut iayon;

reg

//'Gray' code count output.

input wire input wire input wire // 2 0 reg

//Count enable. //Count reset.

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// 2 3 always @ ( posedge C k l) if ( l a _ n begin Ceri) B n r C u t <= { O N E _ I T { ' 0 }+ 1 //Gray count begins @ '1' with iayon CUTRWDH1b } ; G a C u t o t <= { O N E _ I T { ' 0 } ryon_u CUTRWDH1b }; // first 'Enable_in'. end else if ( n b e i ) begin Eal_n

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2 9 3 0 3 1 3 2

else if ( n b e i ) begin Eal_n B n r C u t <= B n r C u t+ 1 iayon iayon ; G a C u t o t <= { i a y o n [ O N E _ I T - ] ryon_u BnrCutCUTRWDH1,


BnrCutCUTRWDH20 ^BnrCutCUTRWDH11} iayon[ONE_IT-:] iayon[ONE_IT-:];

3 3 end 3 4 3 endmodule 5

You could download file GrayCounter.v here

Design and verification


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