The SPARC Hypervisor runs in the Hyper-Privileged execution mode, which was intr oduced in the sun4v

architecture. The sun4v processors released as of September 2011 are the UltraSPARC T1, the UltraSPARC T2, the UltraSPARC T2 Plus, the SPARC T3 [2] and the SPARC T4[3] Only systems based on those processors support Logical Domains. These include th e UltraSPARC T1-based: Sun / Fujitsu SPARC Enterprise T1000 and T2000 servers Sun Fire T1000 and T2000 servers Netra T2000 Server Netra CP3060 Blade Sun Blade T6300 Server Module UltraSPARC T2-based: Sun / Fujitsu SPARC Enterprise T5120 and T5220 servers Sun Blade T6320 Server Module Netra CP3260 Blade Netra T5220 Rackmount Server UltraSPARC T2 Plus systems: Sun / Fujitsu SPARC Enterprise T5140 and T5240 servers (2 sockets) Sun Blade T6340 Server Module (2 sockets) Sun / Fujitsu SPARC Enterprise T5440 (4 sockets) SPARC T3 systems [4]: Sun / Fujitsu SPARC T3-1 servers (1 socket) Sun SPARC T3-1B Server Module (1 socket) Sun / Fujitsu SPARC T3-2 servers (2 sockets) Sun / Fujitsu SPARC T3-4 servers (4 sockets) SPARC T4 systems [5] SPARC T4-1 Server (1 socket) SPARC T4-1B Server Module (blade) SPARC T4-2 Server (2 sockets) SPARC T4-4 Server (4 sockets) Logical Domains exploits the "Chip Multi Threading" (CMT) nature of the UltraSPA RC T1, T2, SPARC T3 and SPARC T4 processors. A single chip contains up to 16 CPU cores, and each core has either four hardware threads (for the T1) or eight har dware threads (for the T2, T2+, T3 and T4) that act as virtual CPUs. All CPU cor es execute instructions concurrently, and each core switches between threads typic ally when a thread stalls on a cache miss or goes idle within a single clock cycle . This lets the processor gain throughput that is lost during cache misses in co nventional CPU designs. Each processor can support as many as one domain per hardware thread up to 32 doma ins for the UltraSPARC T1, 64 domains for the UltraSPARC T2, and 128 domains for UltraSPARC T2+ and later servers with two physical processors or any number of SPARC T3 processors[6]. Alternatively, and in usual practice, a given domain can be assigned multiple CPU threads for additional capacity within a single OS ins tance. CPU threads, RAM, and virtual I/O devices can be added to or removed from a domain by administrator command in the control domain. This change takes effe ct immediately without needing to reboot the affected domain, which can immediat ely make use of added CPU threads or continue operating with reduced CPU threads . Domains can be securely live migrated between servers without outage, using th e hardware cryptographic accelerators of the server to encrypt memory contents b efore they are transmitted.

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