Code No: A7707, A6807 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech I- Semester Supplementary Examinations September, 2010 LOW POWER VLSI DESIGN (Common to Embedded Systems & VLSI Design, VLSI & Embedded Systems) Time: 3hours Max. Marks: 60 Answer any five questions All questions carry equal marks --1. a) b) 2. a) b) Compare CMOS, Bipolar and Bi CMOS technologies in all respects. What are the new technology trends? What are the constraints with low power design? [12] With the help of a sketch explain about short channel effect. Draw the cross sectional diagram of n-well CMOS process and explain the same. Compare this with standard buried collector Bi CMOS structure. [12] Explain how graded drain structure and Retrograde I-well CMOS structure are produced. What are the design considerations in the case of Base, Emitter and Collector in Bi CMOS process? [12] Explain about different steps involved in analog / digital Bi CMOS process. With the help of sketches explain about deep submicron process. [12] Explain about crumel- Poon model of BJT. What are the limitations of SPICE models? Explain. Compare VBIC, HICUM and Metram models of BJT in all respects. [12] Derive the expression for turn-OFF time of Rise Time and Turn- ON time or fall time considering Body effect parameter ‘m’. [12] Draw the circuits and compare CMOS, FSBICMOS, CCBICMOS and FS-CMBL logic circuits in all respects. What is short channel effect? Explain about the same. [12] Write notes on any TWO a) Quality measures for latches and flip flops. b) ESD-free BICMOS. c) Design perspective of flip-flops.


3. a) b)

4. a) b) 5. a) b) 6.

7. a) b) 8.









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