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Aneesh R Broadcast and communication group Centre for development of advanced computing Thiruvananthapuram

Main topics:
Circuit design based on VHDL VHDL basics Advanced VHDL language structures Circuit examples

VHDL is an acronym of VHSIC Hardware Description Language VHSIC is an acronym of Very High Speed Integrated Circuits A Formal Language for Specifying the Behavior and Structure of a Digital Circuit Allows Top-Down Design

Gajskis Y-chart YStructural Processors, memories Registers, FUs, MUXs Gates, flip-flops Behavior Sequential programs Register transfers Logic equations/FSM Transfer functions Cell Layout Modules Chips Boards Physical

Each axis represents type of description


Behavioral
Defines outputs as function of inputs Algorithms but no implementation

Transistors

Structural
Implements behavior by connecting components with known behavior

Physical
Gives size/locations of components and wires on chip/board

Design process is illustrated by travel route

Test Vector Generator

Executable Specification

Results, Errors

Test Vectors

A Series of Refined Models Final Chip Model

VHDL requirements for Simulation Creation of test benches =>


File I/O Detection of errors (function & timing) Multiple simultaneous models Combination of low & high level models (for efficiency)

VHDL requirements for HW Description Behavioral models =>


Combinatorial & Sequential Logic RTL models

Structural models Timing models

Requirements for VHDL Synthesis Tools Pre- & post synthesis behavior should be identical Synthesis should be efficient =>
Requires interaction with place & route tools Logic Synthesis FSM Synthesis Area & Timing Optimization

VHDL frees the designer from having to use von Neumann structures
(Neumann Jnos = John von Neumann)

It allows him to work with real concurrency instead of sequential machines This opens up completely new possibilities for the designer

Shorter development times for electronic design Simpler maintenance Traditional way: schematic design

VHDL originated in the early 1980s


The American Department of Defense initiated the development of VHDL in the early 1980s
because the US military needed a standardized method of describing electronic systems

VHDL was standardized in 1987 by the IEEE It is now accepted as one of the most important standard languages for
specifying verifying designing of electronics

IEEE standard specification language (IEEE 10761993) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level All the major tool manufacturers now support the VHDL standard VHDL is now a standardized language, with the advantage that it is easy to move VHDL code between different commercial platforms (tools) => VHDL code is interchangeable among the different tools

VHDL is an acronym of VHSIC Hardware Description Language VHSIC is an acronym of Very High Speed Integrated Circuits All the major tool manufacturers now support the VHDL standard VHDL is now a standardized language, with the advantage that it it easy to move VHDL code between different commercial platforms (tools) => VHDL code is interchangeable among the different tools

It was the American Department of Defense which initiated the development of VHDL in the early 1980s because the US military needed a standardized method of describing electronic systems VHDL was standardized in 1987 by the IEEE
IEEE Std-1076-1987

ANSI Standard in 1988 Added Support for RTL Design


VITAL: VHDL Initiative Towards ASIC Library

Revised version in 1993


IEEE Std-1076-1993

1995:
numeric_std/bit: IEEE-1076.3 VITAL: IEEE-1076.4

1999: IEEE-1076.1 (VHDL-AMS ) 2000:


IEEE-1076-2000 IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)

Added mixed-signal support to VHDL in 2001 ->


VHDL-AMS
IEEE Std-1076.1-2001

2002: IEEE-1076-2002

Good VHDL tools, and VHDL simulators in particular, have also been developed for PCs Prices have fallen dramatically, enabling smaller companies to use VHDL, too There are also PC synthesis tools, primarily for FPGAs and EPLDs

High-tech companies
Texas Instruments, Intel use VHDL most European companies use VHDL

Universities VHDL groups to support new users

IEEE is the Institute of Electrical and Electronics Engineers The reference manual is called IEEE VHDL Language Reference Manual Draft Standard version 1076/B It was ratified in December 1987 as IEEE 1076-1987 Important:
the VHDL is standardized for system specification but not for design

The design of VHDL components can be technology-independent or more-or-less technology independent for a technical family The components can be stored in a library for reuse in several different designs VHDL models of commercial IC standard components can now be bought, which is a great advantage when it comes to verifying entire circuit boards

VHDL has not yet been standardized for analog electronics Standardization is in progress on VHDL with an analog extension (AHDL) to allow analog systems to be described as well This new standard will be based wholly on the VHDL standard and will have a number of additions for describing analog functions

There are several other language extensions built to either aid in RTL construction or assist in modeling:
ParaCore - http://www.dilloneng.com/paracore.shtml RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml JHDL - http://www.jhdl.org/ Lava - http://www.xilinx.com/labs/lava/ HDLmaker - http://www.polybus.com/hdlmaker/users_guide/ SystemC AHDL http://www.altera.com
It is good for Altera-made chips only, which limits its usefulness But it

is easy to pick up and use successfully

The main purpose of a language -- programming, hdl, or otherwise -- is to ease the expression of design

Verifying Logic Phil Moorby from Gateway Design Automation in 1984 to 1987
Absorbed by Cadence
Cadence's

ownership of Verilog => others support VHDL

Verilog-XL simulator from GDA in 1986 Synopsis Synthesis Tool in 1988 In 1990 became open language
OVI: Open Verilog International

IEEE Standard in 1995


IEEE Std-1364-1995

Last revision in 2001


IEEE Std-1364-2001

Ongoing work for adding


Mixed-signal constructs: Verilog-AMS System-level constructs: SystemVerilog

VHDL
All abstraction levels Complex grammar Describe a system (everything) Lots of data types UserUser-defined package & library Full design parameterization Easier to handle large designs Very consistent language. Code written and simulated in one simulator will behave exactly the same in another simulator. E.g. strong typing rules. Easy language

Verilog
All abstraction levels Describe a digital system Few data types No user-defined packages userSimple parameterization Less consistent language. If you don't follow some adhoc methodology for coding styles, you will not get it right. It executes differently on different platforms unless you follow some adhoc coding rules.

It does seem that Verilog is easier for designing at the gate-level, but that people who do higher level simulations express a preference for VHDL VHDL places constraints on evaluation order that limit the optimizations that can be performed
Verilog allows the simulator greater freedom For example, multiple levels of zero-delay gates can be collapsed into a single super-gate evaluation in Verilog VHDL requires preserving the original number of delta cycles of delay in propagating through those levels

VHDL
In Europe the VHDL is the most popular language Based on Pascal language

Verilog

Based on C language

Most FPGA design in VHDL

Most ASIC design in Verilog

VHDL:
process (siga, sigb) begin ... end;

Verilog:
always @ (siga or sigb) begin . end

VHDL:
c <= a and b;

Verilog:
assign c = a & b ;

VHDL:
a <= transport b after 1 ns;

Verilog:
#1 assign a = b; a output is delayed by 1 time unit The # operator is the delay operator # N will delay for N simulation units Delays can assigned to both inputs and outputs #1 assign a = #1 b; b is delayed by 1 unit, then assigned to a, which is then delayed by 1 time unit

VHDL:
signal clk : std_logic := 0; process begin clk <= not (clk) after clkperiod/2; wait on clk; end;

Verilog:
initial clk = 0; always #(clkperiod/2) clk = ~ clk;

Not well suited for complex, high level modeling


No user defined type definition No concept of libraries, packages, configurations No generate statement - cant build parameterized structural models No complex types above a two-dimensional array

VHDL:
Configuration, generate, generic and package statements all help manage large design structures

Verilog:
There are no statements in Verilog that help manage large designs

VHDL:
allows concurrent procedure calls

Verilog:
does not allow concurrent task calls

VHDL:
The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately

Verilog:
There is no equivalent to the generate statement in Verilog.

SystemVerilog
Extending Verilog to higher levels of abstraction for architectural and algorithm design and advanced verification

VHDL 200x
Goal of VHDL Analysis and Standards Group (VASG):
Enhance/update VHDL for to improve performance, modeling capability, ease of use, simulation control, and the type system e.g.: Data types and abstractions:
variant records interfaces