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EMBEDDED SYSTEM DESIGN

UNIT 1

Course Contents EMBEDDED COMPUTING- Microprocessors, embedded design process, system description formalisms. Instruction sets- CISC and RISC; CPU fundamentalsprogramming I/Os, co-processors, supervisor mode, exceptions, memory management units and address translation, pipelining, super scalar execution, caching, CPU power consumption. EMBEDDED COMPUTING PLATFORM- CPU bus, memory devices, I/O devices, interfacing, designing with microprocessors, debugging techniques., Program design and analysis- models of program, assembly and linking, compilation techniques, analysis and optimization of execution time, energy, power and size. PROCESSES AND OPERATING SYSTEMS- multiple tasks and multiple processes, context switching, scheduling policies, inter-process communication mechanisms. HARDWARE ACCELERATORS- CPUs and accelerators, accelerator system design., Networks- distributed embedded architectures, networks for embedded systems, network-based design, Internet-enabled systems. SYSTEM DESIGN TECHNIQUES- design methodologies, requirements analysis, system analysis and architecture design, quality assurance.

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Reference Books: 1. Wolf, W. Computers as components- Principles of embedded computing system design. Academic Press (Indian edition available from Harcourt India Pvt. Ltd., 27M Block market, Greater Kailash II, New Delhi110 048.)

Logic Optimization and Technology Mapping. Performance Calculation and Design Verification. EPROM and EEPROM Programming Technology.Logic Blocks and Interconnection Resources.Segmented channel routing. Economics and applications of FPGAs. Logic Block Area and Routing Model and Results.RECONFIGURABLE COMPUTING UNIT 1 Course Contents Evolution of programmable devices: Introduction to AND-OR structured Programmable Logic Devices PROM. Multiplexer Technology Mapping . Strategy for routing in FPGAs.Multiplexer Technology Mapping in mis-pga. Technology Mapping for FPGAs: Logic Synthesis . Translation to XNF Format. Logic Block Architecture: Logic Block Functionality versus Area-Efficiency Logic Block Selection.Chortle-crf Technology Mapper. Place and Route. FPGA Based System Design by Wayne Wolf published by Pearson Education 2. 1-channel routing algorithm. Chortle-d Technology Mapper. Architecture of FPAD. FPGA Design Flow Example – Initial Design Entry. Lookup Table Technology Mapping in Asyl and Hydra Technology Mapper. Commercially available FPGAs . Implementation Process for FPGAs Programming Technologies – Static RAM Programming. Routing for FPGAs: Routing Terminology. Lookup Table Technology Mapping . Partitioning. II III IV V Reference Books: 1. FPLS and FPID devices. Digital System Design Using Programmable Logic Devices by Parag K Lala published by BS publications 3. Combinational and sequential circuit realization using PROM based Programmable Logic Element (PLE). PAL and MPGAs. Field-Programmable Gate Arrays by Stephen Brown published by Kluwer Academic Publishers .Xilinx FPGAs. Experimental Procedure. PLA. Anti Fuse Programming. Altera FPGAs. FPLA. K – channel routing algorithm and results. Routing for Row-Based FPGAs . FPGA Technology: FPGA resources . Lookup Table Technology Mapping in mis-pga.

Logic Minimization. Fundamental Architectural Synthesis Problems Temporal Domain Scheduling Spatial Domain Binding Hierarchical Models and Synchronization Problem. Compilation and Behavioral Optimization Techniques. Force Directed Scheduling. Clique covering and partitioning Algorithms Boolean Algebra and Representation of Boolean Functions. Signal Assignment and Wait Statements. Heuristic Scheduling Algorithms (List Scheduling). Heuristic. Exact Logic Minimization. Identifier.MICRO-ELECTRONICS UNIT 1 Course Contents INTRODUCTION TO VLSI. Circuits Specifications for Architectural Synthesis Resources and constraints. Functions with Multivolume inputs and list oriented manipulation. Microelectronic Design. case and next Statement Block and concurrent Assertion statements structural specifications of Hardware-inverter. Data flow and Sequencing Graphs. if. binary Decision diagrams. Graph. Assertion Loop. Algorithms Review of Graph Definitions and Notations Decision and Optimization Problems. four phases in creating Microelectronics chips computer Aided Synthesis and Optimization. Nand Gate Models. Algorithms for logic minimization. State Diagrams. Multiprocessor Scheduling. II III IV V . Basic Language Elements. Vertex Cover. TWO LEVEL COMBINATION LOGIC OPTIMIZATION: Logic Optimization Principles-Definitions. and Testability Properties Operations on Two level logic Cover-positional Cube Notation. Constrained Scheduling. Under Timing Constraints and Relative Scheduling with Resource Constraints Integer Linear Programming Model. Styles. Comparator and Test Bench Modeling. SCHEDULING ALGORITHMS: Model for Scheduling Problems. Data Types and Operator Behavioral Modelingprocess variable Assignment. Area and performance estimation-Resource Dominated circuits and General Circuits. circuits Asics and Moore's Law. Data objects. HARDWARE MODELING: Introduction to Hardware Modeling Language. Constraints-Unconstrained Scheduling ASAP Scheduling Algorithms Latency. Scheduling without Resource. Coloring. Satisfiability and cover problems. ALAP scheduling. Shortest and Longest Path Problems. Architecture and package Declarations. INTRODUCTION TO VHDL: VHDL History and capabilities program Structure of VHDL Entity.