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To Angelina and Jahan, for their love and patience v

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About the Author Behzad Razavi received the BSEE degree from Sharif University of Technology in 1 985 and the MSEE and PhDEE degrees from Stanford University in 1988 and 1992, re spectively. He was with AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and subsequently Profess or of electrical engineering at University of California, Los Angeles. His curre nt research includes wireless transceivers, frequency synthesizers, phase-lockin g and clock recovery for high-speed data communications, and data converters. Pr ofessor Razavi was an Adjunct Professor at Princeton University from 1992 to 199 4, and at Stanford University in 1995. He served on the Technical Program Commit tees of the International Solid-State Circuits Conference (ISSCC) from 1993 to 2 002 and VLSI Circuits Symposium from 1998 to 2002. He has also served as Guest E ditor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Tra nsactions on Circuits and Systems, and International Journal of High Speed Elect ronics. Professor Razavi received the Beatrice Winner Award for Editorial Excell ence at the 1994 ISSCC, the best paper award at the 1994 European Solid-State Ci rcuits Conference, the best panel award at the 1995 and 1997 ISSCC, the TRW Inno vative Teaching Award in 1997, and the best paper award at the IEEE Custom Integ rated Circuits Conference in 1998. He was the co-recipient of both the Jack Kilb y Outstanding Student Paper Award and the Beatrice Winner Award for Editorial Ex cellence at the 2001 ISSCC. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC. Professor Razavi is an IEEE Distinguished Lectu rer, a Fellow of IEEE, and the author of Principles of Data Conversion System De sign (IEEE Press, 1995), RF Microelectronics (Prentice Hall, 1998) (translated t o Chinese), Design of Analog CMOS Integrated Circuits (McGraw-Hill, 2001) (trans lated to Chinese and Japanese), and Design of Integrated Circuits for Optical Co mmunications (McGraw-Hill, 2003), and the editor of Monolithic Phase-Locked Loop s and Clock Recovery Circuits (IEEE Press, 1996), and Phase-Locking in High-Perf ormance Systems (IEEE Press, 2003). vii

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Preface With the advances in the semiconductor and communication industries, it has beco me increasingly important for electrical engineers to develop a good understandi ng of microelectronics. This book addresses the need for a text that teaches mic roelectronics from a modern and intuitive perspective. Guided by my industrial, research, and academic experience, I have chosen the topics, the order, and the depth and breadth so as to ef ciently impart analysis and design principles that t he students will nd useful as they enter the industry or graduate school. One sal ient feature of this book is its synthesis- or design-oriented approach. Rather than pulling a circuit out of a bag and trying to analyze it, I set the stage by stating a problem that we face in real life (e.g., how to design a cellphone ch arger). I then attempt to arrive at a solution using basic principles, thus pres enting both failures and successes in the process. When we do arrive at the nal s olution, the student has seen the exact role of each device as well as the logic al thought sequence behind synthesizing the circuit. Another essential component of this book is “analysis by inspection.” This “mentality” is created in two steps. Fir st, the behavior of elementary building blocks is formulated using a “verbal” descri ption of each analytical result (e.g., “looking into the emitter, we see 1=g m .”). Second, larger circuits are decomposed and “mapped” to the elementary blocks to avoi d the need for writing KVLs and KCLs. This approach both imparts a great deal of intuition and simpli es the analysis of large circuits. The two articles followin g this preface provide helpful suggestions for students and instructors. I hope these suggestions make the task of learning or teaching microelectronics more en joyable. This “preview edition” is introduced as a test vehicle so as to collect fee dback from students and instructors and polish the book for the rst edition. A se t of Powerpoint slides and a solutions manual are available for instructors. Beh zad Razavi April 2006 ix

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xi Acknowledgments This book has taken three years to write and bene ted from contributions of many i ndividuals. I wish to thank the following for their input at various stages of t his book’s development: David Allstot (University of Washington), Joel Berlinghier i, Sr. (The Citadel), Bernhard Boser (University of California, Berkeley), Charl es Bray (University of Memphis), Marc Cahay (University of Cincinnati), Norman C ox (University of Missouri, Rolla), Tranjan Farid (University of North Carolina at Charlotte), Paul Furth (New Mexico State University), Roman Genov (University of Toronto), Maysam Ghovanloo (North Carolina State University), Gennady Gilden blat (Pennsylvania State University), Ashok Goel (Michigan Technological Univers ity), Michael Gouzman (SUNY, Stony Brook), Michael Green (University of Californ ia, Irvine), Sotoudeh Hamedi-Hagh (San Jose State University), Reid Harrison (Un iversity of Utah), Payam Heidari (University of California, Irvine), Feng Hua (C larkson University), Marian Kazmierchuk (Wright State University), Roger King (U niversity of Toledo), Edward Kolesar (Texas Christian University), Ying-Cheng La i (Arizona State University), Daniel Lau (University of Kentucky, Lexington), St anislaw Legowski (University of Wyoming), Philip Lopresti (University of Pennsyl vania), Mani Mina (Iowa State University), James Morris (Portland State Universi ty), Khalil Naja (University of Michigan), Homer Nazeran (University of Texas, El Paso), Tamara Papalias (San Jose State University), Matthew Radmanesh (Californ ia State University, Northridge), Angela Rasmussen (University of Utah), Sal R. Riggio, Jr. (Pennsylvania State University), Ali Sheikholeslami (University of T oronto), Yannis Tsividis (Columbia University), Thomas Wu (University of Central Florida), Darrin Young (Case Western Reserve University). I am grateful to Nare sh Shanbhag (University of Illinois, Urbana-Champaign) for test driving a draft of the book in a course and providing valuable feedback. I also thank my publish ers, Catherine Schultz and Bill Zobrist, for their dedication and exuberance. My wife, Angelina, typed the entire book and kept her humor as this project dragge d on. My deepest thanks go to her. Behzad Razavi April 2006

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Suggestions for Students You are about to embark upon a journey through the fascinating world of microele ctronics. Fortunately, microelectronics appears in so many facets of our lives t hat we can readily gather enough motivation to study it. The reading, however, i s not as easy as that of a story book; we must deal with analysis and design, ap plying mathematical rigor as well as engineering intuition every step of the way . This article provides some suggestions that students may nd helpful in studying microelectronics. Rigor and Intuition Before reading this book, you have taken one or two courses on basic circuit theory, mastering Kirchoff’s Laws and the anal ysis of RLC circuits. While quite abstract and bearing no apparent connection wi th real life, the concepts studied in these courses form the foundation for micr oelectronics—just as calculus does for engineering. Our treatment of microelectron ics also requires rigor but entails two additional components. First, we identif y many applications for the concepts that we study. Second, we must develop intu ition, i.e., a “feel” for the operation of microelectronic devices and circuits. Wit hout an intuitive understanding, the analysis of circuits becomes increasingly m ore dif cult as we add more devices to perform more complex functions. Analysis by Inspection We will expend a considerable effort toward establishing the mentali ty and the skills necessary for “analysis by inspection.” That is, looking at a comp lex circuit, we wish to decompose or “map” it to simpler topologies, thus formulatin g the behavior with a few lines of algebra. As a simple example, suppose we have encountered the resistive divider shown in Fig. (a) and derived its Thevenin eq uivalent. Now, if given the circuit in Fig. (b), we can R1 V in (a) R2 Vout V in R1 C1 (b) R2 L1 Vout readily replace Vin , R1 , and R2 with a Thevenin equivalent, thereby simplifyin g the calculations. 40 Pages per Week While taking courses on microelectronics, you will need to read about 40 pages of this book every week, with each page con taining many new concepts, derivations, and examples. The lectures given by the instructor create a “skeleton” of each chapter, but it rests upon you to “connect the dots” by reading the book carefully and understanding each paragraph before procee ding to the next. Reading and understanding 40 pages of the book each week requi res concentration and discipline. You will face new material and detailed deriva tions on each page and should set aside two- or three-hour distraction-free bloc ks of time (no phone calls, TV, email, etc.) so that you xiii

xiv can follow the evolution of the concepts while honing your analytical skills. I also suggest that you attempt each example before reading its solution. 40 Probl ems per Week After reading each section and going through its examples, you are encouraged to evaluate and improve your understanding by trying the correspondin g endof-chapter problems. The problems begin at a relatively easy level and grad ually become more challenging. Some problems may require that you return to the section and study the subtle points more carefully. The educational value provid ed by each problem depends on your persistence. The initial glance at the proble m may be discouraging. But, as you think about it from different angles and, mor e importantly, re-examine the concepts in the chapter, you begin to form a path in your mind that may lead to the solution. In fact, if you have thought about a problem extensively and still have not solved it, you need but a brief hint fro m the instructor or the teaching assistant. Also, the more you struggle with a p roblem, the more appealing and memorable the answer will be. Attending the lectu re and reading the book are examples of “passive learning:” you simply receive (and, hopefully, absorb) a stream of information provided by the instructor and the t ext. While necessary, passive learning does not exercise your understanding, thu s lacking depth. You may highlight many lines of the text as important. You may even summarize the important concepts on a separate sheet of paper (and you are encouraged to do so). But, to master the material, you need practice (“active lear ning”). The problem sets at the end of each chapter serve this purpose. Homeworks and Exams Solving the problems at the end of each chapter also prepares you for homeworks and exams. Homeworks, too, demand distraction-free periods during whic h you put your knowledge to work and polish your understanding. An important pie ce of advice that I can offer here is that doing homeworks with your fellow stud ents is a bad idea! Unlike other subject matters that bene t from discussions, arg uments, and rebuttals, learning microelectronics requires quiet concentration. ( After all, you will be on your own during the exam!) To gain more con dence in you r answers, you can discuss the results with your fellow students, the instructor , or the teaching assistants after you have completed the homework by yourself. Time Management Reading the text, going through the problem sets, and doing the homeworks require a time commitment of at least 10 hours per week. Due to the fa st pace of the course, the material accumulates rapidly, making it dif cult to kee p up with the lectures if you do not spend the required time from the very rst we ek. In fact, the more you fall behind, the less interesting and useful the lectu res become, thus forcing you to simply write down everything that the instructor says while not understanding much. With your other courses demanding similar ti me commitments, you can soon become overwhelmed if you do not manage your time c arefully. Time management consists of two steps: (1) partitioning your waking ho urs into solid blocks, and (2) using each block ef ciently. To improve the ef ciency , you can take the following measures: (a) work in a quiet environment to minimi ze distractions; (b) spread the work on a given subject over the week, e.g., 3 h ours every other day, to avoid saturation and to allow your subconscious to proc ess the concepts in the meantime. Prerequisites Many of the concepts that you ha ve learned in the circuit theory courses prove essential to the study of microel ectronics. Chapter 1 gives a brief overview to refresh your memory. With the lim ited lecture time, the instructor may not cover this material in the class, leav ing it for you to read at home. You can rst glance through the chapter and see wh ich concepts “bother” you before sitting down to concentrate.

Suggestions for Instructors Teaching undergraduate courses proves quite challenging—especially if the emphasis is on thinking and deduction rather than on memorization. With today’s young mind s used to playing fast-paced video games and “clicking” on the Internet toward their destination, it has become increasingly more dif cult to encourage them to concen trate for long periods of time and deal with abstract concepts. Based on one dec ade of teaching, this article provides suggestions that instructors of microelec tronics may nd helpful. Therapy The students taking the rst microelectronics cours e have typically completed one or two courses on basic circuit theory. To many, that experience has not been particularly memorable. After all, the circuit theo ry textbook is most likely written by a person not in the eld of circuits. Simila rly, the courses are most likely taught by an instructor having little involveme nt in circuit design. For example, the students are rarely told that node analys is is much more frequently used in hand calculations than mesh analysis is. Or, they are given little intuition with respect to Thevenin and Norton theorems. Wi th the foregoing issues in mind, I begin the rst course with a ve-minute “therapy se ssion.” I ask how many came out of the circuit theory courses with a “practical” under standing. Very few raise their hands. I then ask, “But how about your calculus cou rses? How many of you came out of these courses with a “practical” understanding?” Sub sequently, I explain that circuit theory builds the foundation for microelectron ics just as calculus does for engineering. I further point out that some abstrac tness should also be expected in microelectronics as we complete the foundation for more advanced topics in circuit analysis and design. I then point out that ( 1) microelectronics is very heavily based on intuitive understanding, requiring that we go beyond simply writing KVLs and KCLs and interpret the mathematical ex pressions intuitively, and (2) this course offers many applications of microelec tronic devices and circuits in our daily lives. In other words, microelectronics is not as dry as arbitrary RLC circuits consisting of 1- resistors, 1-H inducto rs, and 1-F capacitors. First Quiz Since different students enter each course wi th different levels of preparation, I have found it useful to give a 10-minute q uiz in the very rst lecture. Pointing out that the quiz does not count towards th eir grade but serves as a gauge of their understanding, I emphasize that the obj ective is to test their knowledge rather than their intelligence. After collecti ng the quizzes, I ask one of the teaching assistants to assign a binary grade to each: those who would receive less than 50% are marked with a red star. At the end of the lecture, I return the quizzes and mention that those with a red star need to work harder and interact with the teaching assistants and myself more ex tensively. The Big Picture A powerful motivational tool in teaching is the “big pi cture,” i.e., the “practical” application of the concept under study. The two examples of microelectronic systems described in Chapter 1 serve as the rst step toward c reating the context for the material covered xv

xvi in the book. But, the big picture cannot stop here. Each new concept may merit a n application— however brief the mention of the application may be—and most of this burden falls on the lecture rather than on the book. The choice of the applicati on must be carefully considered. If the description is too long or the result to o abstract, the students miss the connection between the concept and the applica tion. My general approach is as follows. Suppose we are to begin Chapter 2 (Basi c Semiconductor Physics). I ask either “What would our world look like without sem iconductors?” or “Is there a semiconductor device in your watch? In your cellphone? In your laptop? In your digital camera?” In the ensuing discussion, I quickly go o ver examples of semiconductor devices and where they are used. Following the big picture, I provide additional motivation by asking, ”Well, but isn’t this stuff old ? Why do we need to learn these things?” I then brie y talk about the challenges in today’s designs and the competition among manufacturers to lower both the power co nsumption and the cost of portable devices. Analysis versus Synthesis Let us con sider the background of the students entering a microelectronics course. They ca n write KVLs and KCLs ef ciently. They have also seen numerous “random” RLC circuits; i.e., to these students, all RLC circuits look the same, and it is unclear how t hey came about. On the other hand, an essential objective in teaching microelect ronics is to develop speci c circuit topologies that provide certain characteristi cs. We must therefore change the students’ mentality from “Here’s a circuit that you m ay never see again in your life. Analyze it!” to “We face the following problem and we must create (synthesize) a circuit that solves the problem.” We can then begin with the simplest topology, identify its shortcomings, and continue to modify it until we arrive at an acceptable solution. This step-by-step synthesis approach (a) illustrates the role of each device in the circuit, (b) establishes a “design -oriented” mentality, and (c) engages the students’ intellect and interest. Analysis by Inspection In their journey through microelectronics, students face increasi ngly more complex circuits, eventually reaching a point where blindly writing KV Ls and KCLs becomes extremely inef cient and even prohibitive. In one of my rst few lectures, I show the internal circuit of a complex op amp and ask, “Can we analyz e the behavior of this circuit by simply writing node or mesh equations?” It is th erefore important to instill in them the concept of “analysis by inspection.” My app roach consists of two steps. (1) For each simple circuit, formulate the properti es in an intuitive language; e.g., “the voltage gain of a common-source stage is g iven by the load resistance divided by 1=g m plus the resistance tied from the s ource to ground.” (2) Map complex circuits to one or more topologies studied in st ep (1). In addition to ef ciency, analysis by inspection also provides great intui tion. As we cover various examples, I emphasize to the students that the results thus obtained reveal the circuit’s dependencies much more clearly than if we simp ly write KVLs and KCLs without mapping. “What If?” Adventures An interesting method of reinforcing a circuit’s properties is to ask a question like, “What if we tie thi s device between nodes C and D rather than between nodes A and B ?” In fact, stude nts themselves often raise similar questions. My answer to them is “Don’t be afraid! The circuit doesn’t bite if you change it like this. So go ahead and analyze it i n its new form.” For simple circuits, the students can be encouraged to consider s everal possible modi cations and determine the resulting behavior. Consequently, t he students feel much more comfortable with the original topology and understand why it is the only acceptable solution (if that is the case). Numeric versus Sy mbolic Calculations In the design of examples, homeworks, and exams, the instruc tor must decide between numeric and symbolic calculations. The students may,

xvii of course, prefer the former type as it simply requires nding the corresponding e quation and plugging in the numbers. What is the value in numeric calculations? In my opinion, they may serve one of two purposes: (1) make the students comfort able with the results recently obtained, or (2) give the students a feel for the typical values encountered in practice. As such, numeric calculations play a li mited role in teaching and reinforcing concepts. Symbolic calculations, on the o ther hand, can offer insight into the behavior of the circuit by revealing depen dencies, trends, and limits. Also, the results thus obtained can be utilized in more complex examples. Blackboard versus Powerpoint This book comes with a compl ete set of Powerpoint slides. However, I suggest that the instructors carefully consider the pros and cons of blackboard and Powerpoint presentations. I can off er the following observations. (1) Many students fall asleep (at least mentally) in the classroom if they are not writing. (2) Many others feel they are missing something if they are not writing. (3) For most people, the act of writing some thing on paper helps “carve” it in their mind. (4) The use of slides leads to a fast pace (“if we are not writing, we should move on!”), leaving little time for the stu dents to digest the concepts. For these reasons, even if the students have a har dcopy of the slides, this type of presentation proves quite ineffective. To impr ove the situation, one can leave blank spaces in each slide and ll them with crit ical and interesting results in real time. I have tried this method using transp arencies and, more recently, tablet laptops. The approach works well for graduat e courses but leaves undergraduate students bored or bewildered. My conclusion i s that the good old blackboard is still the best medium for teaching undergradua te microelectronics. The instructor may nonetheless utilize a hardcopy of the Po werpoint slides as his/her own guide for the ow of the lecture. Discrete versus I ntegrated How much emphasis should a microelectronics course place on discrete c ircuits and integrated circuits? To most of us, the term “microelectronics” remains synonymous with “integrated circuits,” and, in fact, some university curricula have gradually reduced the discrete design avor of the course to nearly zero. However, only a small fraction of the students taking such courses eventually become act ive in IC products, while many go into board-level design. My approach in this b ook is to begin with general concepts that apply to both paradigms and gradually concentrate on integrated circuits. I also believe that even board-level design ers must have a basic understanding of the integrated circuits that they use. Bi polar Transistor versus MOSFET At present, some controversy surrounds the inclus ion of bipolar transistors and circuits in undergraduate microelectronics. With the MOSFET dominating the semiconductor market, it appears that bipolar devices are of little value. While this view may apply to graduate courses to some exten t, it should be borne in mind that (1) as mentioned above, many undergraduate st udents go into board-level and discrete design and are likely to encounter bipol ar devices, and (2) the contrasts and similarities between bipolar and MOS devic es prove extremely useful in understanding the properties of each. The order in which the two species are presented is also debatable. (Extensive surveys conduc ted by Wiley indicate a 50-50 split between instructors on this matter.) Some in structors begin with MOS devices to ensure enough time is spent on their coverag e. On the other hand, the natural ow of the course calls for bipolar devices as a n extension of pn junctions. In fact, if diodes are immediately followed by MOS devices, the students see little relevance between the two. (The pn junctions in MOSFETs do not come into the picture until the device capacitances are introduc ed.)

xviii My approach in this book is to rst cover bipolar devices and circuits while build ing the foundation such that the MOS counterparts are subsequently taught with g reater ease. As explained below, the material can comfortably be taught even in one quarter with no sacri ce of details of either device type. Course Syllabi This book can be used in a two-quarter or two-semester sequence. Depending on the in structor’s preference, the courses can follow various combinations of the chapters . Figure 0.1 illustrates some possibilities. I have followed Syllabus I for the quarter system at UCLA for a number of years. 1 Syllabus II sacri ces op amp circu its for an introductory treatment of digital CMOS circuits. In a semester system , Syllabus I extends the rst course to current mirrors and cascode stages and the second course to output stages and analog lters. Syllabus II, on the other hand, includes digital circuits in the rst course, moving current mirrors and cascodes to the second course and sacri cing the chapter on output stages. Figure 0.2 show s the approximate length of time spent on the chapters as practiced at UCLA. In a semester system, the allotted times are more exible. Coverage of Chapters The m aterial in each chapter can be decomposed into three categories: (1) essential c oncepts that the instructor should cover in the lecture, (2) essential skills th at the students must develop but cannot be covered in the lecture due to the lim ited time, and (3) topics that prove useful but may be skipped according to the instructor’s preference. 2 Summarized below are overviews of the chapters showing which topics should be covered in the classroom. Chapter 1: Introduction to Micr oelectronics The objective of this chapter is to provide the “big picture” and make the students comfortable with analog and digital signals. I spend about 30 to 45 minutes on Sections 1.1 and 1.2 , leaving the remainder of the chapter (Basic C oncepts) for the teaching assistants to cover in a special evening session in th e rst week. Chapter 2: Basic Semiconductor Physics Providing the basics of semico nductor device physics, this chapter deliberately proceeds at a slow pace, exami ning concepts from different angles and allowing the students to digest the mate rial as they read on. A terse language would shorten the chapter but require tha t the students reread the material multiple times in their attempt to decipher t he prose. It is important to note, however, that the instructor’s pace in the clas sroom need not be as slow as that of the chapter. The students are expected to r ead the details and the examples on their own so as to strengthen their grasp of the material. The principal point in this chapter is that we must study the phy sics of devices so as to construct circuit models for them. In a quarter system, I cover the following concepts in the lecture: electrons and holes; doping; dri ft and diffusion; pn junction in equilibrium and under forward and reverse bias. Chapter 3: Diode Models and Circuits This chapter serves four purposes: (1) mak e the students comfortable with the pn junction as a nonlinear device; (2) intro duce the concept of linearizing a nonlinear model to simplify the analysis; (3) cover basic circuits with which any electrical engineer must be familiar, e.g., recti ers and limiters; and (4) develop the skills necessary to analyze heavily-no nlinear circuits, e.g., where it is dif cult to predict which diode turns on at wh at input voltage. Of these, the rst three are essential and should be covered in the lecture, whereas the last depends on the instructor’s preference. (I cover it in my lectures.) In the 1 We offer a separate undergraduate course on digital circuit design, which the students can take only after our rst microelectronics course. 2 Such topics are identi ed in the book by a footnote.

xix Quarter System, Syllabus I First Quarter: Introduction to Microelectronics (Chap ter 1) MOS Devices (Chapter 6) Physics of Semiconductors (Chapter 2) MOS Circuit s (Chapter 7) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chapter 8) Differential Pairs (Chapter 10) Frequency Response (Chapter 11) Feedback and Stability (Chapter 12) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapte r 5) Second Quarter: Current Mirrors and Cascodes (Chapter 9) Quarter System, Syllabus II First Quarter: Introduction to Microelectronics (Cha pter 1) MOS Devices (Chapter 6) Physics of Semiconductors (Chapter 2) MOS Circui ts (Chapter 7) Diode Models and Circuits (Chapter 3) Bipolar Transistors (Chapte r 4) Bipolar Circuits (Chapter 5) Digital CMOS Circuits (Chapter 15) Differential Pairs (Chapter 10) Frequency Res ponse (Chapter 11) Feedback and Stability (Chapter 12) Second Quarter: Current Mirrors and Cascodes (Chapter 9) Semester System, Syllabus I First Semester: Introduction to Microelectronics (Ch apter 1) MOS Devices (Chapter 6) Second Semester: Differential Pairs (Chapter 10 ) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Frequency Respo nse (Chapter 11) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chap ter 8) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5) Current Mirrors and Cascodes (Chapter 9) Output Stages (Chapter 13) Analog Filte rs (Chapter 14) Feedback and Stability (Chapter 12) Semester System, Syllabus II First Semester: Introduction to Microelectronics (C hapter 1) MOS Devices (Chapter 6) Second Semester: Current Mirrors and Cascodes (Chapter 9) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Diffe rential Pairs (Chapter 10) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chapter 8) Frequency Response (Chapter 11) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5) Digital CMOS Circuits (Chapter 15) Feedback and Stability (Chapter 12) Analog Fi lters (Chapter 14) Figure 0.1 Different course structures for quarter and semester systems. interest of time, I skip a number of sections in a quarter system, e.g., voltage doublers and level shifters. Chapter 4: Physics of Bipolar Transistors Beginnin g with the use of a voltagecontrolled current source in an ampli er, this chapter introduces the bipolar transistor as an extension of pn junctions and derives it s small-signal model. As with Chapter 2, the pace is rela-

xx Quarter System, Syllabus I First Quarter: 1.5 Weeks Introduction to Microelectro nics (Chapter 1) 1 Week MOS Devices (Chapter 6) Second Quarter: 2 Weeks Current Mirrors and Cascodes (Chapter 9) 3 Weeks Differential Pairs (Chapter 10) 2 Weeks Frequency Response (Chapter 11) 3 Weeks Feedback and Stability (Chapter 12) Phy sics of Semiconductors (Chapter 2) 2 Weeks MOS Circuits (Chapter 7) 1.5 Weeks Di ode Models and Circuits (Chapter 3) 1 Week Op Amp as Black Box (Chapter 8) 1 Wee k Bipolar Transistors (Chapter 4) 2 Weeks Bipolar Circuits (Chapter 5) Figure 0.2 Timetable for the two courses. tively slow, but the lectures need not be. I cover structure and operation of th e bipolar transistor, a very simpli ed derivation of the exponential characteristi c, and transistor models, mentioning only brie y that saturation is undesirable. S ince the T-model of limited use in analysis and carries little intuition (especi ally for MOS devices), I have excluded it in this book. Chapter 5: Bipolar Circu its This is the longest chapter in the book, building the foundation necessary f or all subsequent work in electronics. Following a bottom-up approach, this chap ter establishes critical concepts such as input and output impedances, biasing, and small-signal analysis. While writing the book, I contemplated decomposing Ch apter 5 into two chapters, one on the above concepts and another on bipolar ampl i er topologies, so that the latter could be skipped by instructors who prefer to continue with MOS circuits instead. However, teaching the general concepts does require the use of transistors, making such a decomposition dif cult. Chapter 5 pr oceeds slowly, reinforcing, step-by-step, the concept of synthesis and exploring circuit topologies with the aid of “What if?” examples. As with Chapters 2 and 4, t he instructor can move at a faster pace and leave much of the text for the stude nts to read on their own. In a quarter system, I cover all of the chapter, frequ ently emphasizing the concepts illustrated in Figure 5.7 (the impedance seen loo king into the base, emitter, or collector). With about two (perhaps two and half ) weeks allotted to this chapter, the lectures must be precisely designed to ens ure the main concepts are imparted in the classroom. Chapter 6: Physics of MOS D evices This chapter parallels Chapter 4, introducing the MOSFET as a voltage-con trolled current source and deriving its characteristics. Given the limited time that we generally face in covering topics, I have included only a brief discussi on of the body effect and velocity saturation and neglected these phenomena for the remainder of the book. I cover all of this chapter in our rst course. Chapter 7: MOS Circuits Drawing extensively upon the foundation established in Chapter 5, this chapter deals with MOS ampli ers but at a faster pace. I cover all of this chapter in our rst course. Chapter 8: Operational Ampli er as a Black Box Dealing with op-amp-based circuits, this chapter is written such that it can be taught i n almost any order with respect to other chapters. My own preference is to cover this chapter after ampli er topologies have been studied, so that the students ha ve some bare understanding of the internal circuitry of op amps and its gain lim itations. Teaching this chapter near the end of the rst course also places op amp s closer

xxi to differential ampli ers (Chapter 10), thus allowing the students to appreciate t he relevance of each. I cover all of this chapter in our rst course. Chapter 9: C ascodes and Current Mirrors This chapter serves as an important step toward inte grated circuit design. The study of cascodes and current mirrors here also provi des the necessary background for constructing differential pairs with active loa ds or cascodes in Chapter 10. From this chapter on, bipolar and MOS circuits are covered together and various similarities and contrasts between them are pointe d out. In our second microelectronics course, I cover all of the topics in this chapter in approximately two weeks. Chapter 10: Differential Ampli ers This chapte r deals with large-signal and small-signal behavior of differential ampli ers. The students may wonder why we did not study the largesignal behavior of various am pli ers in Chapters 5 and 7; so I explain that the differential pair is a versatil e circuit and is utilized in both regimes. I cover all of this chapter in our se cond course. Chapter 11: Frequency Response Beginning with a review of basic con cepts such as Bode’s rules, this chapter introduces the high-frequency model of tr ansistors and analyzes the frequency response of basic ampli ers. I cover all of t his chapter in our second course. Chapter 12: Feedback and Stability Most instru ctors agree that the students nd feedback to be the most dif cult topic in undergra duate microelectronics. For this reason, I have made great effort to create a st ep-by-step procedure for analyzing feedback circuits, especially where input and output loading effects must be taken into account. As with Chapters 2 and 5, th is chapter proceeds at a deliberately slow pace, allowing the students to become comfortable with each concept and appreciate the points taught by each example. I cover all of this chapter in our second course. Chapter 13: Output Stages and Power Ampli ers This chapter studies circuits that deliver higher power levels th an those considered in previous chapters. Topologies such as pushpull stages and their limitations are analyzed. This chapter can be comfortably covered in a se mester system. Chapter 14: Analog Filters This chapter provides a basic understa nding of passive and active lters, preparing the student for more advanced texts on the subject. This chapter can also be comfortably covered in a semester syste m. Chapter 15: Digital CMOS Circuits This chapter is written for microelectronic s courses that include an introduction to digital circuits as a preparation for subsequent courses on the subject. Given the time constraints in quarter and sem ester systems, I have excluded TTL and ECL circuits here. Problem Sets In additi on to numerous examples, each chapter offers a relatively large problem set at t he end. For each concept covered in the chapter, I begin with simple, con dencebui lding problems and gradually raise the level of dif culty. Except for the device p hysics chapters, all chapters also provide a set of design problems that encoura ge students to work “in reverse” and select the bias and/or component values to sati sfy certain requirements. SPICE Some basic circuit theory courses may provide ex posure to SPICE, but it is in the rst microelectronics course that the students c an appreciate the importance of simulation tools. Appendix A of this book introd uces SPICE and teaches circuit simulation with the aid of numerous examples. The objective is to master only a subset of SPICE commands that allow simulation of most circuits at this level. Due to the limited lecture time, I ask the teachin g assistants to cover SPICE in a special evening session around the middle of th e quarter—just before I begin to assign SPICE problems.

xxii Most chapters contain SPICE problems, but I prefer to introduce SPICE only in th e second half of the rst course (toward the end of Chapter 5). This is for two re asons: (1) the students must rst develop their basic understanding and analytical skills, i.e., the homeworks must exercise the fundamental concepts; and (2) the students appreciate the utility of SPICE much better if the circuit contains a relatively large number of devices (e.g., 5-10). Homeworks and Exams In a quarte r system, I assign four homeworks before the midterm and four after. Mostly base d on the problem sets in the book, the homeworks contain moderate to dif cult prob lems, thereby requiring that the students rst go over the easier problems in the book on their own. The exam questions are typically “twisted” version of the problem s in the book. To encourage the students to solve all of the problems at the end of each chapter, I tell them that one of the problems in the book is given in t he exam verbatim. The exams are open-book, but I suggest to the students to summ arize the important equations on one sheet of paper.

Contents 1 Introduction to Microelectronics 1.1 Electronics versus Microelectronics 1.2 E xamples of Electronic Systems . . 1.2.1 Cellular Telephone . . . . . 1.2.2 Digit al Camera . . . . . . . 1.2.3 Analog versus Digital . . . 1.3 Basic Concepts . . . . . . . . . . . 1.3.1 Analog and Digital Signals . 1.3.2 Analog Circuits . . . . . . . 1.3.3 Digital Circuits . . . . . . . 1.3.4 Basic Circuit Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 1 . 2 . 2 . 4 . 6 . 7 . 7 . 9 . 10 . 11 19 19 20 22 25 32 33 38 42 45 49 49 50 56 56 56 57 62 65 67 73 81 82 93 96 98 103 116 xxiii 2 Basic Physics of Semiconductors 2.1 Semiconductor Materials and Their Properti es 2.1.1 Charge Carriers in Solids . . . . . . . 2.1.2 Modi cation of Carrier Dens ities . . 2.1.3 Transport of Carriers . . . . . . . . . 2.2 PN Junction . . . . . . . . . . . . . . . . . 2.2.1 PN Junction in Equilibrium . . . . . 2.2.2 PN Ju nction Under Reverse Bias . . 2.2.3 PN Junction Under Forward Bias . . 2.2.4 I/V Characteristics . . . . . . . . . . 2.3 Reverse Breakdown . . . . . . . . . . . . . 2.3.1 Zener Breakdown . . . . . . . . . . . 2.3.2 Avalanche Breakdown . . . . . . . . 3 Diode Models and Circuits 3.1 Ideal Diode . . . . . . . . . . . . . . . . . . 3.1.1 Initial Thoughts . . . . . . . . . . . . 3.1.2 Ideal Diode . . . . . . . . . . . . . . 3.1.3 Application Examples . . . . . . . . 3.2 PN Juncti on as a Diode . . . . . . . . . . . . 3.3 Additional Examples . . . . . . . . . . . . . 3.4 Large-Signal and Small-Signal Operation . . 3.5 Applications of Diod es . . . . . . . . . . . . 3.5.1 Half-Wave and Full-Wave Recti ers . 3.5.2 Voltage Regulation . . . . . . . . . 3.5.3 Limiting Circuits . . . . . . . . . . . 3.5. 4 Voltage Doublers . . . . . . . . . . 3.5.5 Diodes as Level Shifters and Switch es 4 Physics of Bipolar Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxiv 4.1 4.2 4.3 4.4 4.5 4.6 General Considerations . . . . . . . . . . . . . . . Structure of Bipolar Transi stor . . . . . . . . . . . Operation of Bipolar Transistor in Active Mode . . 4. 3.1 Collector Current . . . . . . . . . . . . . . 4.3.2 Base and Emitter Current s . . . . . . . . . Bipolar Transistor Models and Characteristics . . . 4.4.1 La rge-Signal Model . . . . . . . . . . . . 4.4.2 I/V Characteristics . . . . . . . . . . . . . 4.4.3 Concept of Transconductance . . . . . . . 4.4.4 Small-Signal Model . . . . . . . . . . . . 4.4.5 Early Effect . . . . . . . . . . . . . . . . . Operation of Bipolar Transistor in Saturation Mode The PNP Transistor . . . . . . . . . . . . . . . . . 4.6.1 Structure and Operation . . . . . . . . . . 4.6 .2 Large-Signal Model . . . . . . . . . . . . 4.6.3 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 118 119 121 125 127 127 129 131 133 137 142 145 145 146 149 165 165 166 170 170 172 173 175 179 182 185 189 189 215 230 238 266 266 268 269 274 283 284 286 286 287 288 289 290 292 293 304 5 Bipolar Ampli ers 5.1 General Considerations . . . . . . . . . . . 5.1.1 Input a nd Output Impedances . . . 5.1.2 Biasing . . . . . . . . . . . . . . . 5.1.3 DC and Small-Signal Analysis . . . 5.2 Operating Point Analysis and Design . . . . 5.2.1 Simple Biasing . . . . . . . . . . . 5.2.2 Resistive Divider Biasing . . .

. . . 5.2.3 Biasing with Emitter Degeneration . 5.2.4 Self-Biased Stage . . . . . . . . . . 5.2.5 Biasing of PNP Transistors . . . . . 5.3 Bipolar Ampli er Topol ogies . . . . . . . . 5.3.1 Common-Emitter Topology . . . . 5.3.2 Common-Base To pology . . . . . . 5.3.3 Emitter Follower . . . . . . . . . . 5.4 Summary and Ad ditional Examples . . . . 6 Physics of MOS Transistors 6.1 Structure of MOSFET . . . . . . . . . . . 6.2 Operation of MOSFET . . . . . . . . . . 6.2.1 Qualitati ve Analysis . . . . . . . 6.2.2 Derivation of I/V Characteristics . 6.2.3 Channe l-Length Modulation . . . 6.2.4 MOS Transconductance . . . . . 6.2.5 Velocity Sa turation . . . . . . . 6.2.6 Other Second-Order Effects . . . 6.3 MOS Device Mod els . . . . . . . . . . . 6.3.1 Large-Signal Model . . . . . . . 6.3.2 Small-Sig nal Model . . . . . . . 6.4 PMOS Transistor . . . . . . . . . . . . . 6.5 CMOS T echnology . . . . . . . . . . . . 6.6 Comparison of Bipolar and MOS Devices 7 CM OS Ampli ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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xxv 7.1 7.2 7.3 7.4 7.5 General Considerations . . . . . . . . . . . . 7.1.1 MOS Ampli er Topologies . . . . . . 7.1.2 Biasing . . . . . . . . . . . . . . . . 7.1.3 Realization of Curren t Sources . . . . Common-Source Stage . . . . . . . . . . . . 7.2.1 CS Core . . . . . . . . . . . . . . . . 7.2.2 CS stage With Current-Source Load . 7.2.3 CS s tage With Diode-Connected Load 7.2.4 CS Stage With Degeneration . . . . . 7.2.5 CS Core With Biasing . . . . . . . . Common-Gate Stage . . . . . . . . . . . . . 7.3.1 CG Stage With Biasing . . . . . . . . Source Follower . . . . . . . . . . . . . . . . 7.4.1 Source Follower Core . . . . . . . . 7.4.2 Source Follower Wi th Biasing . . . . Summary and Additional Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 304 304 308 309 309 312 313 314 318 320 324 326 326 328 330 353 353 355 355 358 360 366 368 368 369 370 370 370 373 377 381 382 394 394 394 401 408 408 410

418 438 438 438 440 442 443 443 8 Operational Ampli er As A Black Box 8.1 General Considerations . . . . . . . . . . . 8.2 Op-Amp-Based Circuits . . . . . . . . . . 8.2.1 Noninverting Ampli er . . . . . . . 8.2.2 Inverting Ampli er . . . . . . . . . 8.2.3 Integrator and Differe ntiator . . . . 8.2.4 Voltage Adder . . . . . . . . . . . 8.3 Nonlinear Function s . . . . . . . . . . . . . 8.3.1 Precision Recti er . . . . . . . . . 8.3.2 Logar ithmic Ampli er . . . . . . . 8.3.3 Square-Root Ampli er . . . . . . . 8.4 Op Amp No nidealities . . . . . . . . . . . 8.4.1 DC Offsets . . . . . . . . . . . . . 8.4 .2 Input Bias Current . . . . . . . . . 8.4.3 Speed Limitations . . . . . . . . . 8.4.4 Finite Input and Output Impedances 8.5 Design Examples . . . . . . . . . . . . . . 9 Cascode Stages and Current Mirrors 9.1 Cascode Stage . . . . . . . . . . . . 9.1.1 Cascode as a Current Source 9.1.2 Cascode as an Ampli er . . 9.2 C urrent Mirrors . . . . . . . . . . . 9.2.1 Initial Thoughts . . . . . . . 9.2.2 Bipolar Current Mirror . . . 9.2.3 MOS Current Mirror . . . . 10 Differential Am pli ers 10.1 General Considerations . . . 10.1.1 Initial Thoughts . . . 10.1.2 Dif ferential Signals . 10.1.3 Differential Pair . . . 10.2 Bipolar Differential Pai r . . 10.2.1 Qualitative Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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xxvi 10.3 10.4 10.5 10.6 10.2.2 Large-Signal Analysis . . 10.2.3 Small-Signal Analysis . . MOS Differenti al Pair . . . . . . . 10.3.1 Qualitative Analysis . . . 10.3.2 Large-Signal Anal ysis . . 10.3.3 Small-Signal Analysis . . Cascode Differential Ampli ers . CommonMode Rejection . . . . Differential Pair with Active Load 10.6.1 Qualitative Ana lysis . . . 10.6.2 Quantitative Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 449 453 459 459 463 468 471 475 479 479 481 504 504 506 507 508 509 512 512 514 516 516 517 519 521 521 523 525 529 532 532 547 547 550 551 551 553 554 558 558 559 560 562 565 567 567 571 574 578 11 Frequency Response 11.1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Relationship Between Transfer Function and Freque ncy Response 11.1.2 Bode Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Association of Poles with Nodes . . . . . . . . . . . . . . . . . . 11.1.4 Miller’s Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . 11 .2 High-Frequency Models of Transistors . . . . . . . . . . . . . . . . . . . 11 .2.1 High-Frequency Model of Bipolar Transistor . . . . . . . . . . . 11.2.2 Hig h-Frequency Model of MOSFET . . . . . . . . . . . . . . . . 11.2.3 Transit Frequ ency . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Frequency Response o f CE and CS Stages . . . . . . . . . . . . . . . . . 11.3.1 Use of Miller’s Theore m . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Direct Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Frequency Response of CB and CG Stage s . . . . . . . . . . . . . . . . . 11.5 Frequency Response of Followers . . . . . . . . . . . . . . . . . . . . . 11.5.1 Input and Output Impedances . . . . . . . . . . . . . . . . . . . 11.6 Frequency Response of Cascode Stage . . . . . . . . . . . . . . . . . . . 11.6.1 Input and Output Impedances . . . . . . . . . . . . . . . . . . . 11.7 Frequency Response of Differential Pairs . . . . . . . . . . . . . . . . . 12 Feedback 12.1 General Considerations . . . . . . . . . 12 .1.1 Loop Gain . . . . . . . . . . . 12.2 Properties of Negative Feedback . . . . 12.2.1 Gain Desensitization . . . . . . 12.2.2 Bandwidth Extension . . . . . . 12.2.3 Modi cation of I/O Impedances 12.2.4 Linearity Improvement . . . . . 12.3 Types of Ampli ers . . . . . . . . . . . 12.3.1 Simple Ampli er Models . . . . 12.3. 2 Examples of Ampli er Types . 12.4 Sense and Return Techniques . . . . . . 12.5 P olarity of Feedback . . . . . . . . . . 12.6 Feedback Topologies . . . . . . . . . . 12.6.1 Voltage-Voltage Feedback . . . 12.6.2 Voltage-Current Feedback . . . 12.6.3 Current-Voltage Feedback . . . 12.6.4 Current-Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxvii 12.7 Effect of Finite I/O Impedances . . 12.7.1 Inclusion of I/O Effects . . 12. 8 Stability in Feedback Systems . . 12.8.1 Review of Bode’s Rules . 12.8.2 Problem of Instability . . 12.8.3 Stability Condition . . . . 12.8.4 Phase Margin . . . . . . . 12.8.5 Frequency Compensation . 12.8.6 Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 582 593 593 595 598 601 602 606 623 623 624 626 629 629 632 636 636 637 640 640 641 641 642 644 645 645 646 647 656 656 657 658 661 664 665 667 668 671 676 676 681 685 690 690 695

14. . . . 5 Large-Signal Considerations . . 14. . . . 13. . .3 High-Fidelity Design . . . . . . . . .2 Emitter Follower as Power Ampli er .5. . . . . . 13. 13. . . . . . . . . . . 13. . . 14. . . . . . . . . . . . . . 14. . .7 Heat Diss ipation . . .1 General Considerations . . . . . . . . . . . . . . . . . . . . .8. . . . . . . . . . . . . . . . . . . . . .6 Short-Circuit Protection . . . . .13 Output Stages and Power Ampli ers 13. . . . . . . . . . . . . . . . . .2 RLC Realizations .4. . . . . . . . . . . . . . . .2 Omission of PNP Power Transistor 13. . . .3 Filter Transfer Function . . .2 First-Order Filters . . . . . . . . .1. . . .8. . . . . . . . . . . . . .1 General Considerations . . . . . . 14. .4 Active Filters . . . . . . . . .2 Ef ciency of Push-Pull Stage . . . .2 Push-Pull Stage Power Rating .3. . . . . . . . . . . . . . . . 13. . . .3 Thermal Runaway . . . . . . . . . . . . .4 Problem of Se nsitivity . . . . . . . .4 Improved Push-Pull Stage . . . . . . . . . . . . . . . . . . . .2 Integrator-Based Biquads . . . . . . 13. . . . . . . . . . . . . . . 13. . . . . . . . . . . . . . . . . . . . . . . .1. . .5. . . 14. . . . . . . 1 3. . .5. . 14. . . . 14. . . . . . .3. . . . . . . . . . . 13. . . . . . . . . . . . . . 14. .4. . . . . . . . . . . 13. .1. . . . . . . . . . . . . . . . . . . . . . .1 Butterworth Response . . . .5 Approximation of Filter Response . 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13. .4. . . . . . . . . . . . . . . . . . . . . . 13. . . . . . . .9 Power Ampli er Classes . . . . . . . . . .1 Biasing Issues . . . . . . . . . .7. .1 Filter Characteristics . . . . . . 14. . . . . . . 14 Analog Filters 14. .1 Special Cases . . . . . . . . . . . . . . . . 14. . . . . . . . .1. . . . .2 Classi cation of Filter s . . .8 Ef ciency . . . . . . . . . . . . . 14. . .1 Red uction of Crossover Distortion . 13. . . . . . 13. . .3 Biquads Using Simulated Inductors 14 . . . . . . . . . . . . .5. . . . . . . . . . .7. . . . . . .5. . .4. . . 13. . . 13. . . . . . . .1 Emitter Follower Power Rating . . . . . . . . . . . . . . 14. . .2 Addition of CE Stage . . . . . . . . . . . . . . . . . . . . . . . . . .3 Push-Pull Stage .1 Sallen and Key Filter . 14. . . . . .7. . . . . . . . . . . . . . .2 Chebyshev Response . 3 Second-Order Filters . . . . . .1 Ef ciency of Emitter Fol lower . . . . . . . . . . . . . . . . . .4.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital CMOS Circuits 707 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Introduction to SPICE A. . . . . . . . . . . . . . . . . . . .xxviii 15. .4 MOSFETs .2. . . 15. . . . . . . . . . . . .2 Initial Conditions . . . . . . . . . . . .2 Voltage Tran sfer Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 NOR Gate .2 NAND Gate . . . . . . . . . . . . A. . .4. . . . . . . . . . . .4 Powe r Dissipation . . . . . . . . . . . . . . . . .2. . . . . . . . .4. . .3 Power-Speed Trade-Off . . . . . . . . . . . . . . A. . . . . . . . . . . . . A. . . . . . . 15. . . . . . . 15. . . . . . . . . . . . . . A. . . . . . . . . . . .1. . . . . . . . . . .3. . . . .1 Operating Point Analysis A.3 Element Descriptions . . . . . .3 DC Analysis . . . . . . . .2 CMOS Inverter . . . . . . . . . . . . . . .2. .2 Types of Anal ysis . . . . . . . . . . . . A. . . . . . . . . A. . . . . . . . . . . . . . . . . . . 15. . . . . . . . . . . . . . . . . . . . . . . . . .1.2 Diodes . . . . . . . . . . . . . 15. . . . 15. . . . .2 Dynamic Characterization of G ates 15. . . . . A. . . . . . . . . . . . . . . . . .3. . .2. . . . . . . . . . .3 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .2 Transient Analysis . . . . . . . . . . . . . .4 Other Elements and Commands A. . . . . . . . . . . .3 Bipolar Transistors . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . 708 714 717 719 719 721 726 731 734 734 737 746 746 748 749 749 752 753 753 754 756 758 761 761 762 . . . . .2. .3. . . . . . . . . . . . . . . . . . . . . . .1 Curr ent Sources . . . . . . . . A. . . . . . . . . .3. . . . . . . . . . . . . . .1 Initial Thoughts . . . . . .1 Static Characterization of Gates . . . . . .2. . . . . 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 CMOS NOR and NAND Gates . . . . . . . . . . . . . . 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . .1 Simulation Procedure . . .1 Dependent Sources . A. . . . . . . . . . .1. . . . . . . . . . .

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e.e. Learning microelectronics can be fun. and many other electronic products have now become an integral p art of our daily affairs. but advances in the technolo gy soon made it possible to dramatically increase the complexity of “microchips.cls v. the 1 Solution . (The chip is a few hundred microns thick. What other issues would arise in s uch an implementation? The minimum volume is given by 27 mm3 108 . and how circuits form sophisticated systems. We also pro vide a review of basic circuit theory to refresh the reader’s memory. Early sy stems incorporated “vacuum tubes. in nite) lifetime and occupied a much smaller volume (e. a cube 1.g. This chapter gives an overview of microelectronics so as to provide a contex t for the material presented in this book. Early “integrated circuits” (ICs) contained only a handful of devices. While be yond the realm of possibility a few decades ago..1 Today’s microprocessors contain about 100 million transistors in a chip area of ap proximately 3 cm 3 cm. We introduce examples of microelectro nic systems and identify important circuit “functions” that they employ. 2007 at 13:42 1 (1) 1 Introduction to Microelectronics Over the past ve decades. we begin to see the beauty of microelectronics and appreciate the reasons for its explosive grow th. de termine the minimum volume for the processor. digital cameras.1 Electronics versus Microelectronics The general area of electronics began about a century ago and proved instrumenta l in the radio and radar communications used during the two world wars. la ptop computers. how devices comprise circuits that perform interesting and useful functions. began.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. less than 1 cm3 in packaged form) than vac uum tubes did.” Example 1. i. But it was not until 1960s that the eld of microelectronics. The rst transistor was invented in the 1940s and rapidly disp laced vacuum tubes.. the science of integrating many transistors on one chip. cellphones. It exhibited a very long (in principle. i.) Suppose integr ated circuits were not invented and we attempted to build a processor using 100 million “discrete” transistors. the nite lifetime and the la rge size of vacuum tubes motivated researchers to seek an electronic device with better properties.” amplifying devices that operated with the ow of el ectrons between plates in a vacuum chamber. 1. However. microelectronics has revolutionized our lives. If each device occupies a volume of 3 mm 3 mm 3 mm.. 2006] June 30. As we learn how each device operates.4 m on each side! Of course.

after some processing. a frequency range of 20 Hz to 20 kHz tra nslates to a wavelength1 of 1:5 107 m to 1:5 104 m. its dimension must be a signi cant fraction (e. this discrete processor would be extremely sl ow. we introduce two examples of microelectronic systems and identify some of the important building blocks that we should study in basic electronics . Today’s cellphones contain a great deal of sop histicated analog and digital electronics that lie well beyond the scope of this book. What goes on in these black boxes ? Why are they needed? Transmitter (TX) Microphone ? ? (a) (b) Figure 1. 1. Suppose you are speaking with a friend on your cellphone. How well does this system work? We make two observations.1 (a) Simpli ed view of a cellpho ne. Your voice is converted to an electric signal by a mic rophone and. to convert most of the electrical sig nal to electromagnetic radiation.1(b). to obtain a reasonable antenna length. In add ition to occupying a large volume.1 Cellular Telephone Cellular telephones were developed in the 1980s and r apidly became popular in the 1990s. if each discrete transistor costs 1 cent and weighs 1 g..cls v. 1. i.. the wavelength must be around 20 cm and the frequency around 1. First. 1 Introduction to Microelectronics wires connecting the transistors would increase the volume substantially. for an antenna to operate ef ciently.g.2. ou r voice contains frequencies from 20 Hz to 20 kHz (called the “voice band”). each processor unit would be priced at one million dollars and weigh 100 tons! Exercise How much power would such a system consume if each transistor dissipates 10 W? This book deals with mostly microelectronics while providing suf cient foundation for general (perhaps discrete) electronic systems as well. 5 c m.1(a)]. But our objective here is to see how the concepts described in this book prove relevant to the operation of a cellphone. 1. Conversely. Unfortunately. Second.g . 1 Recall that the wavelength is equal to the (light) velocity divided by the fre quency. The signal produ ced by your antenna is picked up by the your friend’s receiver and. applied to the speaker [Fig. transmitted by the antenna. 1.2 Examples of Electronic Systems At this point. after some pro cessing.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 GHz. . requiring gigantic antennas for each cellphone.e. the signals would need to travel on wires as long as 1. 2007 at 13:42 2 (1) 2 Chap.4 m! Furthermore. e.. 2006] June 30. Receiver (RX) Speaker Let us attempt to omit the black boxes and construct the simple system shown in Fig. (b) further simpli cation of transmit and receive paths. 25) of the wavelength.

2(a)].2 Examples of Electronic Systems 3 How do we “convert” the voice band to a gigahertz center frequency? One possible app roach is to multiply the voice signal. 2007 at 13:42 3 (1) Sec.cls v. 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) equivalent o . by a sinusoid.2 (a) Multi lication of a voice signal by a sinusoid. A cos2fc t [Fig. 2006] June 30. 1. S ince multiplication in the time domain corresponds to convolution in the frequen cy domain. and since the spectrum x (t ) Voice Signal A cos( 2 π f C t ) Out ut Waveform t (a) t t X (f ) Voice S ectrum −20 kHz +20 kHz 0 S ectrum of Cosine Out ut S ectrum f −fC 0 +fC f −fC 0 +fC f (b) Figure 1. xt.

the cell hone must deliver Power Am lifier A cos( 2 π f C t ) (a) Oscillator (b) Figure 1. 1.eration in the frequency domain. Second.”2 We therefore ostulate that the black box in the transmitter of Fig .. 1. This to ology fails to o erate with the rinci le of modulation : if the signal received by the antenna resides around a gigahertz center freque ncy. the audio s eaker cannot roduce meaningful information. A cos 2fc t. beginning with the sim le realization illustrated in Fig. 1. But two other issue s arise. if fc = 1 GHz.1(a) contains a multi lier. a means of 2 Cell hones in fact use other ty es of modulation to translate the voice band t o higher frequencies.1(b) .2(b)]. 1. the sinusoid. a relatively large voltage swing (e.3(a). the out ut occu ies a bandwidth of 40 kHz centered at 1 GHz. Thus. In other words.g. First. thereby requiring a “ ower am li er” between the multi lier and the antenna.3(b). ¡ . of the sinusoid consists of two im ulses at fc . the voice s ectrum is sim ly shi fted (translated) to fc [Fig. Let us now turn our attention to the receive ath of the cell hone.3 (a) Sim le transmitter. 3 Also called a “mixer” in high frequency electronics.3 as de icted in Fig. (b) more com lete transmitter.” We thus arrive at the transmitter archite cture shown in Fig. Unfortunately. 20 V ) to the antenna so that the radi ated ower can reach across distances of several kilometers. 1. This o eration is an exam le of “am litude modulation. must be roduced by an “oscillator.

2006] June 30. We thus arrive at the receiver to ology shown in Fig.4(a). fc . 2007 at 13:42 4 (1) 4 Cha . as de icted in Fig.cls v. 1. (b) more com lete receiver.4(b). A cos2fc t. Our receiver design is still incom lete. (b) sim le receiver.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The newly generated com onents at 2fc can be removed by a low ass lter. The signal received by the antenna can be as low as a few tens of microvolts whereas the s eaker may require swings of ¡ ¡ . 1 Introduction to Microelectronics translating the s ectrum back to zero center frequency is necessary. multi lication by a sinusoid.4 (a) Translation of modulated signal to zero center frequency. 1. For exam le . translates the s ectrum to left and right by Out ut S ectrum Received S ectrum S ectrum of Cosine −fC 0 +fC f −fC 0 +fC f (a) −2 f C 0 +2 f C f Low−Noise Am lifier Low−Pass Filter Low−Pass Filter Am lifier oscillator (b) oscillator (c) Figure 1. restoring the original voice band.

1. and multi liers in both transmit and receive aths of a cel l hone.g. and lter s. With traditional ca meras. si nce multi liers ty ically suffer from a high “noise” and hence corru t the received signal.2. 1. the reader may wonder if “this is old stuff” and rather trivial com ared to the state of the art.e. Nonetheless. a “low noise am li er” must recede the multi lier. these building blocks still remain among th e most challenging circuits in communication systems. For exam le. This is because the design entails critical trade offs between s eed (gigahertz center frequencies). noise . and many other arameters.e.2 Digita l Camera Another consumer roduct that.several tens or hundreds of millivolts. we received no immediate ¡ ¡ ¡ . the voice signal in the transmitter an d the receiver is a lied to a digital signal rocessor (DSP) to im rove the qua lity and ef ciency of the communication. weight. oscillators. with the last two also utilizing am li cation. Today’s cell hones are much more so histicated than the to ologies develo ed above. e. our study reveals some of th e fundamental building blocks of cell hones. oscillators. rice of a cel l hone). ower dissi ation (i. Having seen the necessity of a m li ers. am li ers.” has dramati cally changed our habits and routines is the digital camera. Furthermore. We therefore devote a great deal of effort to the analysis and design of am li ers. The overall architecture i s de icted in Fig.. In the com etitive world of cell hone manufa cturing. That is.4(c). by virtue of “going electronic... a given design is never “good enough” and the engineers are forced to furth er ush the above trade offs in each new generation of the roduct. the receiver must rovide a gr eat deal of am li cation (“gain”) between the antenna and the s eaker. battery lifetime). cost (i. Interestingly.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) array of ixels in a digital camer a. e.25 million ixels a rranged in a 2500 2500 array [Fig. and we would obtain the nal result only in rinted form.. we study the o eration of the digital camera.5 (a) O eration of a hotodiode. thereby develo ing a 25 Am lifier 00 C ol um ns Light I Diode CL Photodiode (a) (b) V out 2500 Rows Signal Processing (c) Figure 1. Each ixel thus rovides a voltage ro ortional to the “local” light density. ro ortional voltage across it. 6.”4 Each ixel consists of an electronic device (a “ hotodiode” that roduces a current ro ortional to the intensity of the light that it receives.5(a) with a sim le. Now consider a camera with. a task erformed by an array (matrix) o f “ ixels.5(c)]. CL .” turn on only one switch at a ti ¡ ¡ . How is the out ut voltage of each i xel sensed and rocessed? If each ixel contains its own electronic circuitry. (c) one column of the array. on the other hand.g.5(a). we follow the circuit of Fig. for a certain eriod of time. 1. 2007 at 13:42 5 (1) Sec.cls v. We must therefore “time share” the signal rocessing circuits among ixels. we needed to carry bulky r olls of lm. c om act am li er and a switch (within the ixel) [Fig. As illustr ated in Fig.2 Exam les of Electronic Systems 5 feedback on the quality of the icture that was taken. t he overall array occu ies a very large area. 1. say. we connect a w ire to the out uts of all 2500 ixels in a “column.5(b)]. To this end. Now. we were very careful in s electing and shooting scenes to avoid wasting frames. transmission of ictu res through cell hones or ability to retouch or alter ictures by com uters. this current ows through a ca acitance. 1. 1. 1. The “front end” of the c amera must convert light to electricity. we have resolved these issues and enjoy many other f eatures that only electronic rocessing can rovide. With digital cameras. raising the cost and the ower diss i ation considerably. In this section. 2006] June 30.

me. Exam le 1. and a ly the corres onding voltage to the “signal rocessing” block outside the column. 4 The term “ ixel” is an abbreviation of “ icture cell. Sketch the voltage column as a function of time.” roduced by one . The overall array consists of 2500 of such columns. with each column em loying a dedicated signal rocessing block.2 A digital camera is focused on a chess board.

What does each signal rocessing block do? Since the voltage roduced by each i xel is an analog signal and can assume all values within a range. Exercise Plot the voltage if the rst and second squares in each row have the same color. the V column V column t (a) (b) (c) Figure 1. Once in the digital domain. 2006] June 30. The resulting waveform is shown in Fig. we ma y time share one ADC between every two columns (Fig. very fast ADC for all 2500 columns. Since ADCs are relatively com lex circuits. we may em loy a single.6(b). column voltage alternates between a maximum for such ixels and zero for those r eceiving no light. ADC Figure 1. 1 Introduction to Microelectronics Solution The ixels in each column receive light only from the white squares [Fig.” the digital signal rocessor (DSP) sim ly considers only ¡ ¡ ¡ . to “z oom in. 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the o t imum choice lies between these two extremes.7).7 Sharing one ADC between two columns of a ixel array. 1. (b) voltage waveform of one column.25 mega ixel array mu st thus incor orate 2500 ADCs. Thus. we must rst “digi tize” it by means of an “analog to digital converter” (ADC). but requiring that th e ADC o erate twice as fast (why?). the “vide o” signal collected by the camera can be mani ulated extensively. A 6. 1.6(a) ]. In ractice.6 (a) Chess board ca tured by a digital camera. 2007 at 13:42 6 (1) 6 Cha . In the extreme case. For exam le.cls v.

. need not learn about analog circuits. g. Similarly.3 Basic Conce ts Analysis of microelectronic circuits draws u on many conce ts that are taught in basic courses on signals and systems and circuit theory. digital signal roce ssors.cls v.3 Analog versus Digital Am li ers and ADCs are exa m les of “analog” functions.8 Data waveforms at 100 Mb/s and 1 Gb/s. The nite risetime and falltime of the latter raises many issues in the o eration of gate s. is there any future for analog design? Well. Al so. to reduce the required memory size. switching o erations. 1. Fi rst.” In fact. The reader may then say. discarding the information from the remaining ixels. This section rovides a brief review of these conce ts so as to refresh the reader’s memory and establis h the terminology used throughout this book. digital circuits require a nalog ex ertise as the s eed increases.3 Basic Conce ts 7 a section of the array. a 20 V signal (analog or digital) received by the antenna cannot be dir ectly a lied to a digital gate.” By contrast. with digital communications. The analog functions include am li cation. and a nalog to digital conversion. and the digital functions consist of subsequent sig nal rocessing and storage. 2006] June 30. evide ntly. For exam le. The architectures of Figs. 1. 3 and 1. not every function can be realized digitally. Second. therefore. contain no analog functions. “I have no intention o f working for a cell hone or camera manufacturer and.2. the video signal collectively ca tur ed by the ixels in a digital camera must be rocessed with low noise and distor tion before it a ears in the digital domain. 1. oscillators. and other digital circuits. Figure 1. “digital” circuits deal with binary levels (ONEs and ZEROs) and. The reader may rst glance through th is section to determine which to ics need a review or sim ly return to this mate ¡ ¡ ¡ ¡ . 10 ns x 1 (t ) 1 ns t x 2 (t ) t Figure 1. 1. necessitating great attention to each oint on the waveform. circuits that must rocess each oint on a waveform (e. and every other function becoming digital. some of the assum tions in the above statements are incorrect. one at 100 Mb/s and another at 1 Gb/s. i o s. a voice signal) with great care to avoid effects such as noise and “distortion .4 must em loy low noise and ower am li ers. the rocessor “com resses” the video signal.8 exem li es this oint by illust rating two binary data waveforms.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and multi liers regardless of whether the actual communication is in analog or digital form. The digital camera exem li es the extensive use of both analog and digital microe lectronics. 2007 at 13:42 7 (1) Sec.

1 Analog and Digital Signals An electric signal is a waveform that carries information.” such signals include voice. vi deo. Signals that occur in nature can assume all values in a given range. seismic.rial as it becomes necessary later. . Called “analog. 1. and music This section serves as a review and can be ski ed in classroom teaching.3.

which remains at only one of two levels for V (t ( ZERO ONE V ( t ( + Noise T T (a) t (b) t Figure 1.”5 As an exam le. Furthermore..9(b) illustrates the effect of noise. While occurring all aro und us. 2007 at 13:42 8 (1) 8 Cha . (b) effect of noise on analog signal.9(a).10 (a) Digital signal. By contrast. 1. analog signals are dif cult to “ rocess” due to sensitivities to such circuit im erfections as “noise” and “distortion. 2006] June 30. (b) effect of noise on digital signal.9 (a) Analog signal . a digital signal assumes onl y a nite number of values at only certain oints in time.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10(a ) is a “binary” waveform. De icted in Fig. 1 Introduction to Microelectronics waveforms. analog signals are dif cult to “store” because they req uire “analog memories” (e. Figure 1. .cls v. values and rovides information at each instant of time. ca acitors). an analog voltage waveform swings through a “cont inuum” of V (t ( V ( t ( + Noise t t (a) (b) Figure 1. Shown in Fig. 1.g.

The storage of binar y signals (in a digital memory) is also much sim ler. and com a ct disk (CD) recorders erform some analog rocessing.11). Figure 1. 1. camcorders. We therefore conside r digital signals more “robust” than their analog counter arts. Indeed . the “digital” data a ears as a distorted waveform with only a few millivolts of am litude 5 Distortion arises if the out ut is not a linear function of in ut. So long as the two voltages corres onding to ONEs and ZEROs dif fer suf ciently.” and digital rocessing (Fig. Consider. logical circuits sensing such a signal rocess it correctly—even if noise or distortion create some corru tion [Fig. the information stored on a hard di sk in a com uter. “analog to digital conversi on. Digital Processing and Storage Analog Signal Analog Processing Analog−to−Digital Conversion It is worth noting that many digital binary signals must be viewed and rocessed as analog waveforms. ¡ ¡ . U on retrieval. for exam le.10(b)].each eriod. suggesting that inherently a nalog information must be converted to digital form as early as ossible. with the rst two functions laying a criti cal role in the quality of the signal. T .11 Signal rocessing in a ty ical system. 1. The foregoing observations favor rocessing of signals in the digital domain. com lex microelectronic systems such as digital cameras.

and ower dissi ation. 2007 at 13:42 9 (1) Sec. Exam le 1.2) For exam le. is to drive a logical gate. gain. but it is instructive to brie y review some of these conce ts here. The voltage gain. a voltage gain of 10 translates to 20 dB. An am li er is therefore necessary to rai se the signal swing to acce table levels. is de ned a s Av = vvout : in (1. As exem li ed b y the cell hone and the digital camera studied above. The erformance of an am li er is charac terized by a number of arameters. demanding a great deal of am li cation and other analo g rocessing before the data reaches a robust digital form. 1.. we refer to ex ress the gain in decibels (dB): Av jdB = 20 log vvout : in (1. but it must deliver a swing of 50 mV to the s eaker that re roduces the voice. 2006] June 30. Calculate the required voltage gain in decibels. e. The most commonly used analog function is am li cation.1) In some cases.3. s eed.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We study these as ects of am li cation in great detail later in this book.g.cls v. 1.3 Basic Conce ts 9 t Figure 1. A voltage am li er roduce s an out ut swing greater than the in ut swing. The gain of ty ical am li e rs falls in the range of 101 to 105 . A cell hone receives a signal level of 20 V . The signal received by a cell hone or icked u by a micro hone roves too small to be rocessed further.12). analog circuits often limi t the erformance of the overall system.2 Analog Circuit s Today’s microelectronic systems incor orate many analog functions.12 Signal icked u from a hard disk in a com uter. Av . Such a small se aration between ONEs and ZEROs this signal ~3 mV Hard Disk ¡ roves inadequate if .3 Solution We have (Fig. 1.

4) Exercise What is the out ut swing if the gain is 50 dB? .3) (1.Av = 20 log 50 mV 20 V 68 dB: (1.

s eed. with the understanding that they are resent. and owe r dissi ation of these building blocks lay a central role in the overall system erformance. we study the design of the internal c ¡ ¡ ¡ ¡ . The com lexity.” this source is ty ically denoted by VCC or VDD [Fig. 1. Am li ers (and other analog circuits) suffer from trade offs betwe en gain. a nd latches and i o s constitute “sequential” machines. 1. In digital microelectronics.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. where the “ground” terminal signi es a reference oint with zero otenti al. a battery or a charger. thereby lowering the gain. Today’s microelectronic am li ers achieve band widths as large as tens of gigahertz. as de icted in Fig. In other word s.14 Roll off an am li er’s gain at high frequencies.13(c)]. we may even omit the su ly t erminals [Fig. (b) sim li ed diagram of (a). static and dynamic memories. Exam les include micro rocessors. l imiting the (usable) “bandwidth” Am lifier Gain High−Frequency Roll−off Frequency Figure 1.g. In com lex circuits. the gain rolls off at suf ciently high frequencies. an am li er must draw ower from a voltage source. and digital signal r ocessors.3 Digital Circuit s More than 80 of the microelectronics industry deals with digital circuits. V in Vout Fig.cls v. What limits the s eed of am li ers? We ex ect that various ca acitances in the circuit begin to m anifest themselves at high frequencies. If the am li er is sim ly denoted by a triangle.” For exam le. a lter must su ress t his “interferer” to allow meaningful measurement of the heart.13(b)..14. 1. 1 Introduction to Microelectronics In order to o erate ro erly and rovide gain.13 (a) General am li er symbol along with its ower su ly. Recall from basic logic design that gates form “combinational” circuits. we may sim lify the notation to that shown in Am lifier VCC V in Vout V CC V in Vout Ground (a) (b) (c) Figure 1. What other analog functions are frequently used? A critical o eration is “ ltering. Called the “ ower su ly. Ty ical a m li ers o erate with su ly voltages in the range of 1 V to 10 V. 1. e. 2007 at 13:42 10 (1) 10 Cha . (b) am li er with su ly rails omitted. of the circuit.3. 1. an electrocardiogra h measurin g a atient’s heart activities also icks u the 60 Hz (or 50 Hz) electrical line voltage because the atient’s body acts as an antenna.13(a)]. s eed and ower dissi ation. Thus.

For exam le.ircuits of gates. we construct a circuit using devices such as transistors to . and other com onents. i o s.

As a result. We thus observe that. 2007 at 13:42 11 (1) Sec. Based on these im lementat ions. i.16)? ? Figure 1. the voltage dro across RL is zero and hence Vout = VDD . S1 is on and vice versa. we NOT Gate NOR Gate A Y =A A B Y =A +B Figure 1. where switch S1 is controlled by the di gital in ut. 1. then determine various ro erties of each circuit. 2006] June 30. 1. if A is high.3 Basic Conce ts 11 realize the NOT and NOR functions shown in Fig.17. S1 remains off. 1.. That RL A S1 V DD Vout Exam le 1. what limits the s eed of a gate? How much ower does a gate consume while running at a certain s eed? How robustly does a gate o erate in the resence of nonidealities such as noise (Fig.16 Res onse of a gate to a noisy in ut. For exam le.17 is. S1 is on. if A is low. drawing no current from RL .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. forcing Vout to zero. Consider the circuit shown in Fig. for both logical states at the in ut.15. the out ut is high.cls v. 1. . If A is high. the out ut assumes the o o site state. Solution Exercise Determine the logical function if S1 and RL are swa ed and Vout is sensed acros s RL .4 Figure 1. On the other hand.15 NOT and NOR gates. Prove that the circuit rovides the N OT function.e.

This section rovides a review of such conce ts. It was only after “transistors” were in vented and their ability to act as switches was recognized that digital circuits consisting of millions of gates and o erating at high s eeds (several gigahertz ) became ossible.3. some rove articularly im ortant to our s tudy of microelectronics. early digital circuits did em loy mechanical switches (relays).4 Basic Circuit Theorems Of the numerous analysis techniq ues taught in circuit theory courses. . 1.The above exam le indicates that switches can erform logical o erations. In fac t. but suffered from a very limited s eed (a few kilohertz).

The Kirchoff Voltage Law (KVL) states that the sum of voltage dro s around any closed loo in a circuit is zero [Fig.18 Illustration of KCL.19(a)]: 2 V2 1 V2 V3 3 1 2 3 V1 V1 V3 V4 4 V4 4 (a) .cls v. Kirchoff’s Laws The Kirchoff Current Law (KCL) states that the sum of all currents owing into a node is zero (Fig.18): X j Ij = 0: (1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 Introduction to Microelectronics I1 I2 In Ij Figure 1. 1.5) KCL in fact results from conservation of charge: a nonzero sum would mean that e ither some of the charge owing into node X vanishes or this node roduces charge. 1. 2006] June 30. 2007 at 13:42 12 (1) 12 Cha .

we can sim ly assign arb itrary olarities. 1. X j Vj = 0. In solving circuits.19(b) are different from those in Fig. . 1. we may not know a riori the correc t olarities of the currents and voltages. Nonetheless. (1. we may sum the voltages in the loo to zero: V1 + V2 + V3 + V4 = 0.6) where Vj denotes the voltage dro across element number j . we can say V1 is equal to t he sum of the voltages across elements 2. Alternati vely.” In the exam le illustrated in Fig. KVL arises from the conservation of the “electromotive force. ado ting the modi ed view shown in Fig. and 4: V1 = V2 + V3 + V4 . write KCLs and KVLs. Note tha t the olarities assigned to V2 . 3. 1. (b) slightly different view of the circuit .(b) Figure 1.19(a). and V4 in Fig.19(a ). V3 .19(b). and solve the equations to obtain the ac tual olarities and values.19 (a) Illustration of KVL. 1.

Writing a KVL in the “in ut loo . A KCL at the out ut node yields gm v + vout = 0: R L It follows that (1. we must eliminate v from the equatio ns. 1. Unim ortant in most cases.20 re resents the equivalent circuit of an am li e r. and hence gm v (1.20 r ..g R : m L vin Note that the circuit am li es the in ut if gm RL sign sim ly means the circuit “inv erts” the signal.e. gm .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9) 1. the negative Exercise . 2007 at 13:42 13 (1) Sec. 2006] June 30. vout =vin . We must com ute vout in terms of vin .7) = gmvin . Determine the voltage gain of the am li er.8) vout = .3 Basic Conce ts 13 Exam le 1.6 multi lied by t he voltage dro across v in v out RL rπ vπ i 1 g vπ R L m v out Figure 1. i.cls v.5 The to ology de icted in Fig. 1. The de endent current source i1 is equal to a constant. (1.” we have Solution vin = v .

rπ vπ i 1 g vπ R L m v out v in Figure 1.Re eat the above exam le if r ! infty.21 6 What is the dimension of gm ? .21 shows another am li er to ology. Exam le 1. Com ute the gain.6 Figure 1.

rπ vπ i 1 g vπ m v in RE v out Figure 1. Thus. and the current vout =RE ows out of it.v : The KCL at the out ut node is similar to (1. 1.22 Solution vin = v + vout : v + g v = vout : r m (1.12) That is.22. Exam le 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. noting that the currents v =r and gm v ow into the ou t ut node.10) vout = g R : vin m L Interestingly.7 A third am li er to ology is shown in Fig.8). 1 Introduction to Microelectronics Noting that r in fact a ears in arallel with vin .13) RE We rst write a KVL around the loo consisting of vin . vout .cls v. 2006] June 30. (1. Determine the voltage gain. r . Next. we write a KVL across these two com onents: Solution vin = . this ty e of am li er does not invert the signal. v = vin . we write a KCL: (1. (1. 2007 at 13:42 14 (1) 14 Cha .11) Exercise Re eat the above exam le if r ! infty. and RE : .

Substituting vin . and hence E . vout for v gives vin r + gm = vout R1 + r1 + gm .

1 .

15) .14) 1 vout = r + gm 1 1 vin RE + r + gm (1.(1.

The above three exam les relate to three am li er to ologies that are studied exte nsively in Cha ter 5. 1. rovide additional insight into the o eration of a circuit. Would such an am li er rov e useful at all? In fact.23(a). more im ortantly. the term “ ort” refers to a ny two nodes whose voltage difference is of interest. 1. the Thevenin and Norton theorems can both sim lify the algebra and. Illustrated in Fig.16) Note that the voltage gain always remains below unity. 2007 at 13:42 15 (1) Sec. Thevenin’s theorem states that a (linear) one ort networ k can be re laced with an equivalent circuit consisting of one voltage source in series with one im edance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Basic Conce ts 15 r E = r 1 + gmg (1. 2006] June 30. this to ology exhibits some im ortant ro erties that make it a versatile building block. Exercise Re eat the above exam le if r ! infty. Thevenin and Norton Equivalents While Kirchoff’s laws can al ways be utilized to solve any circuit. The equivalent Vj i X v Port j ZT v he X ZT v he v rRR : + 1 + m E ¡ .cls v.

We also call ZThe v the im edance “seen” when “looking” into the out ut ort [Fig.20 are laced in a box and only the out ut ort is of interest [Fig. Solution We must com ute the o en circuit out ut voltage and the im edance seen when look ing into the ¡ . Exam le 1.Th ev (a) (b) Figure 1.8 Su ose the in ut voltage source and the am li er shown in Fig.23 (a) Thevenin equivalent circuit. voltage.23(b)]. 1. Determine the The venin equivalent of the circuit.24(a)]. The im edance is com uted by a lying a voltage source across the ort and obtaining the resu lting current. is obtained by leaving the ort o en and com uting the voltage created by the actual circuit at this ort. A few exam les illustrate these rinci les. (b) com utation of equivale nt im edance. is determined by setting all inde endent voltage and current sources in the circui t to zero and calculating the im edance between the two nodes. The equivalent im edance. ZThev . 1. 1. vThev .

24(a) and Eq.18) To calculate ZThev . whose value is not known a riori. Also. 1.24 out ut ort. setting vin to zero means re lacing it with a short circui t. The circuit thus reduces to RL and v iX = RX : . a ly a voltage source.gm RLvin : (1. 1. and determine the current drawn from the voltage source.9): vThev = vout = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. since both terminals of r are tied to ground. As s hown in Fig.17) (1. 1. v = 0 and gm v = 0.cls v.24(b)? We must again eliminate v . How do we solve the circuit of Fig. 1 Introduction to Microelectronics iX RL vX − g m R Lv in v in rπ vπ i 1 g vπ m R L v out v in = 0 r π vπ i 1 g vπ m RL (a) (b) (c) Figure 1. we set vin to zero. vX . note that the current source gm v remains in the circuit because it de e nds on the voltage across r . 2007 at 13:42 16 (1) 16 Cha . (1. iX .24(b). Fortunately. 2006] June 30. across the out ut ort. The Thevenin voltage is obtained from Fig.

With the Thevenin equivalent of a circuit available.21) (1.gmvin RL jjRs : Rs . 1.” Exam le 1.9 The am li er of Fig.22) s vout = . 1. Determine the . Re lac ing the section in the dashed box with its Thevenin equivalent from Fig.24(c) . we call RThev (= RL ) the “out ut im edance” of the circuit . (1.L That is. we can readily analyze its behavior in the resence of a subsequent stage or “load. and write (1. In this case.25(b)].19) RThev = RL : (1.gmRL vin R R+ R s L = .20) Figure 1. we greatly sim lify the circuit [Fig. 1.25(a) is the overall circuit arrangement that must solve. 1. Exercise Re eat the above exam le if r ! 1.24(c) de icts the Thevenin equivalent of the in ut voltage source and t he am li er. Solution Shown in Fig.20 must drive a s eaker having an im edance of voltage deli vered to the s eaker.

16): + r L vThev = r 1 1 gmg rRR vin : (1. 2006] June 30. 2007 at 13:42 17 (1) Sec. we set vin to zero and a ly a voltage source across the out ut ort as de icte d in Fig. Exam le 1.10 Determine the Thevenin equivalent of the circuit shown in Fig.23) + + m L To calculate the Thevenin im edance. To eliminate v . 1.cls v.25 (a) (b) Exercise Re eat the above exam le if r ! 1.22 if the out u t ort is of interest.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1.3 Basic Conce ts RL 17 v in rπ vπ i 1 g vπ R L m v out − g m R Lv in v out Figure 1. we recognize that the two terminals of r rπ vπ i 1 g vπ m iX RL v X ¡ R s R s . 1. Solution The o en circuit out ut voltage is sim ly obtained from (1.26.

25) or ow into thi X RL .24) We now write a KCL at the out ut node. (1.vX : v + g v + i = vX .vX RL Figure 1.26 are tied to those of vX and hence v = . r m (1. The currents v =r . Consequently. gm v . and iX s node and the current vX =RL ows out of it.

1 vX r + gm .vX + iX = RL : (1.26) .

27) (1. 1.20 if the out ut ort is of interest. The equivalent im edance.27). we short the out ut ort and s eek the value of iNor .28) = r + 1r+RL r R : gm Exercise What ha ens if RL = 1? Norton’s theorem states that a (linear) one ort network can be re resented by one current source in arallel with one im edance (Fig. 1. Exam le 1. 1. iNor . 1 Introduction to Microelectronics That is.cls v. shorting the ort of interest and com uting the current that ows through it. ZNor . is determined by setting all inde endent voltage an d current sources in the circuit to zero and calculating the im edance seen at t he ort.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. is obtained by Port j Z No r No r i Figure 1. As de icted in Fig. Of course. ZNor = ZThev . 2007 at 13:42 18 (1) 18 Cha . Since the voltage i Nor v in rπ vπ i 1 g vπ R L m (a) Short Circuit Solution L ¡ .28(a).27 Norton’s theorem. RThev = vX i X (1.11 Determine the Norton equivalent of the circuit shown in Fig. 2006] June 30. The equivalent curre nt.

A KCL at the out ut node thus yields iNor = .g v m in RL (b) Figure 1.28 across RL is now forced to zero.29) .gmv (1. this resistor carries no current.

1. we observe t hat the ow of iNor through RL roduces a voltage of .8. 2007 at 13:42 19 (1) Sec. RNor (= RThev = RL .29(a).gm RL vin .31) . vin = v (why?). we no te that RL carries no current. yielding iNor = v + gmv : r (1. 1. Exercise Re eat the above exam le if a resistor of value R1 is added between the to term inal of vin and the out ut node. the same as the out ut voltage of the original circuit. Shorting the out ut ort as illustrated in Fig.22 if the out ut ort is interest.28(b). Thus. 1.4 Cha ter Summary 19 = . The Norton equivalent therefore eme rges as shown in Fig. from Exam le 1. To check the validity of this model.30) Also. 1.gmvin : (1.29 Also. 2006] June 30. v in rπ vπ i 1 g vπ m ( 1 + g m ) vin rπ Solution r π RL r π + (1+ g mr π ) R L RL i Nor (a) (b) Figure 1. Exam le 1.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12 Determine the Norton equivalent of the circuit shown in Fig.

29(b).iNor = r + gm vin : With the aid of Fig. . 1.

etc. including cell hones. digital camer as. we construct the Norton equivalent de icted in Exercise What ha ens if r = infty? 1.10. la to com uters.1 (1.32) RThev found in Exam le 1.4 Cha ter Summary Electronic functions a ear in many devices. .

Similarly.cls v. Thevenin’s theo rem reduces a one ort circuit to a voltage source in series with an im edance. By contrast . Kirchoff’s current law (KCL) states that the sum of all currents owing into any node is zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Norton’s theorem allows sim lifying a one ort cir cuit to a current source in arallel with an im edance. Analog circuits rocess signals that can assume various values at any time. The voltage gain o f an am li er is de ned as vout =vin and sometimes ex ressed in decibels (dB) as 20 logvout =vin . 1 Introduction to Microelectronics Am li cation is an essential o eration in many analog and digital systems. digital circuits deal with signals having only two levels and switching betwee n these values at known oints in time.” analog cir cuits nd wide a lication in most of today’s electronic systems. ¡ ¡ . Des ite the “digital revolution. 2007 at 13:42 20 (1) 20 Cha . 2006] June 30. Kirchoff’s voltage law (KVL) states that the sum of all vo ltages around any loo is zero.

The situation is similar to many other engineering roblems. Semiconductors Charge Carriers Do ing Trans ort of Carriers PN Junction Structure Reverse and Forward Bias Conditions I/V Characteristics Ci rcuit Models It is im ortant to note that the task of develo ing accurate models roves criti cal for all microelectronic devices. a good understanding of the internal o erati on of devices is necessary.e.” 21 ¡ ¡ . 2007 at 13:42 21 (1) 2 Basic Physics of Semiconductors Microelectronic circuits are based on com lex semiconductor structures that have been under active research for the ast six decades. we must develo a basic understanding of “semiconductor” materials and thei r current conduction mechanisms before attacking diodes. The electronics industry continues to lace greater demands on circuits. Th e outline is shown below. calling for aggressive designs that ush semicondu ctor devices to their limits.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we should em hasize at the outset that a g ood understanding of devices is essential to our work.1 1 As design managers often say. then you lose to your com etitor. voltage or current sources. In this cha ter. so that a circuit using such a device can be analyzed easily. Our ultimate objective in this cha ter is to study a fundamentally im ortant and versatile d evice called the “diode. Our ultimate goal is to re resent the dev ice by a circuit model (consisting of resistors.. th e ow of current) in them. and formulate its behavior. Our treatment of device hysics must contain enough de th to rovide adequate understanding. just as we need to eat our broccoli before having desert. we do face a dilemma. but must also be suf ciently brief to al low quick entry into circuits. e. While this book deals with the analysis and design of circuits.g. Thus. “If you do not ush the devices and circuits to th eir limit but your com etitor does. we beg in with the conce t of semiconductors and study the movement of charge (i.” However. we deal with the the “ n junction.).. Next. 2006] June 30. etc.cls v. Noneth eless. one cannot design a high erformance a utomobile without a detailed knowledge of the engine and its limitations.” which also serves as diode. ca acitors. This cha ter accom lishes this task.

. silicon merits a detailed analysis. As the most o ular material in microelectronics. This outline re resents a logical thought rocess: (a) we identify charge carrie rs in solids and formulate their role in current ow. ossibly dis laying interesting chemical and hysical ro ertie s.1 Outline of this section.2 Section of the eriodic table. an d how com lete this shell is. called “valence” electrons.2 2 Silicon is obtained from sand after a great deal of rocessing.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 22 (1) 22 Cha . (c) we determine current ow mechanisms. (b) we examine means of modi fying the density of charge carriers to create desired current ow ro erties. Shown in Fig. it is useful to bear a ge neral outline in mind: Charge Carriers in Solids Crystal Structure Bandga Energy Holes Modification of Carrier Densities Intrinsic Semiconductors Extrinsic Semiconductors Do ing Tran s ort of Carriers Diffusion Drift Figure 2. 2. and ch loride has seven valence electrons. ready to relinquish it. neon exhibits a com lete outermost sh ell (with eight electrons) and hence no tendency for chemical reactions.” The atom’s chemical activity i s determined by the electrons in the outermost shell.2 is a section of the eriodic table containIII IV V Boron (B) Aluminum (Al) Galium (Ga) Carbon (C) Silicon (Si) Germanium (Ge) Phos horous (P) Arsenic (As) Figure 2.1 Semiconductor Materials and Their Pro erties Since this section introduces a multitude of conce ts. The above rinci les suggest that atoms having a ro ximately four valence electrons fall somewhere between inert gases and highly vo latile elements. ing a number of elements with three to ve valence electrons. 2006] June 30. sodium has only one valence electron. For exam le. On the other hand. These ste s naturally lead to the com utatio n of the current/voltage (I/V) characteristics of actual diodes in the next sect ion.1.cls v. Both elements are therefore highly reactive. eager to receive one more. 2 Basic Physics of Semiconductors 2.1 Charge Carriers in Solids Recall from basic chemistry that the electr ons in an atom orbit the nucleus in different “shells. 2.

1 Semiconductor Materials and Their Pro erties 23 Covalent Bonds A silicon atom residing in isolation contains four valence electr ons [Fig. an electron leaves a “void” behind because the bond is now incom lete. elect rons gain thermal energy. If r ocessed ro erly. 2006] June 30.3(c)] until they fall into another incom lete bon d. ¡ ¡ . it is the fre e electron that actually moves in the crystal. The uniform crystal de icted in Fig. In other words. Su ose covalent bond number 1 contains a hole after losing an electron some time t = t1 1 Si Si Hole Si Si Si Si Si Si Si Si Si 2 Si t = t2 Si Si Si Si Si t = t3 Si 3 Si Si Si Figure 2. 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3(b) lays a crucial role in semiconductor devices. 2. To a reciate the usefulness of h oles. 2007 at 13:42 23 (1) Sec. con material can form a “crystal” wherein each atom is surrounded by exactly four ot hers [Fig. But. requiring another four to com lete its outermost shell. refusing to move freely. 2. and an “electron hole recombination” occurs when an electron “falls” into a hole. consider the time evolution illustrated in Fig. each atom shares one valence electron with its neighbors.3(a)]. we say an “electron hole air” is generated when an elec tron is freed. the silicon cry stal behaves as an insulator for T ! 0K . does it carry current in res onse to a voltage? At tem eratures near absolute zero. occasionally breaking away from the bonds and acting a s free charge carriers [Fig.3(b)]. The “bond” t hus formed between atoms is called a “covalent bond” to em hasize the sharing of val ence electrons. thereby com leting its own shell and those of the neighbors.4. Thus. the siliCovalent Bond Si Si Si Si Si Si Si Si Si Si Si Si Si e Si Si Free Electron (a) (b) (c) Figure 2.cls v. 2.3 (a) Silicon atom. We will hereafter use the term “electrons” to refer to free electrons.4 Movement of electron through crystal. 2. As a result. Holes When freed from a covalent bond. the valence electrons are con ned to their res ective covalent bonds. However.” such a void can readily absorb a free electron if o ne becomes available. at higher tem eratures. Why do we bother with the conce t of the hole? After all. 2. (b) covalent bonds between atoms. (c) free electron released by thermal energy. Called a “hole.

an electron leaves bond number 3 and falls into the hole in bond number 2. First. This view of current ow by holes roves extremely useful in the analysis of semiconductor devices. an electron breaks away from bond number 2 and recom bines with the hole in bond number 1. At t = t2 . or. Bandga Energy We mus t now answer two im ortant questions. in fact. Similarly.before t = t1 .” we can say one electron has traveled from right to left. does any thermal energy create free electrons (and holes) in silicon? No. one hole has moved from left to right. Looking at the three “sna shots. a minimum energy is required to . at t = t3 . alternatively .

2007 at 13:42 24 (1) 24 Cha . But.g. Insu lators dis lay a high Eg .Eg =2k T . Eg = 1:12 eV. [1].23 J/K is called the Boltzmann constant. As ex ected. Also. a hole is left behind. The derivation can be found in books on semiconductor hysics. How many free electrons are created at a given tem erature? From o ur observations thus far. e.. 2 Basic Physics of Semiconductors dislodge an electron from a covalent bond. For silicon.19 J.1 Solution = 300 K (room tem erature) and T = 600 K. we have 1010 electrons=cm3 ni T = 600 K = 1:54 1015 electrons=cm3 : ni T = 300 K = 1:08 (2. so do T 3=2 and ex . = 1:12 eV= 1:792 10.5 eV. on the other hand. but a higher T yields more electrons. ni . The ni values obtained in the above exam le may a ear quite high. Determine the density of electrons in silicon at T Since Eg Exam le 2. but.5 eV. Finally.3). materials havi ng a larger Eg exhibit a smaller ni . ty ically ranging from 1 eV to 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we consider the density (or con centration) of electrons. do not des air! We next introduce a means of making Exercise Re eat the above exercise for a material having a bandga of 1.1) where k = 1:38 10. The ex onential de endence of ni u on Eg re veals the effect of the bandga energy on the conductivity of the material.kTg electrons=cm3 2 . In other words. for exam le. thereby bringing ni toward zero. we recognize that only one in 5 1012 atoms be ne t from a free electron at room tem erature.3 The second question relates to the conductivity of the material and i s as follows. E ni = 5:2 1015T 3=2 ex .2) (2. have a small bandga . i. Called the “bandga energy” and denoted b y Eg . we ostulate that the number of electrons de ends on b oth Eg and T : a greater Eg translates to fewer electrons.e. 2006] June 30.3) Since for each free electron. as T ! 0. the number of electrons er unit volume. silicon still seems a very oor conductor. the density of holes is als o given by (2. noting t hat silicon has 5 1022 atoms=cm3 . an d write for silicon: (2.2) and (2. semiconductors exhibit a moderate Eg . Eg = 2:5 eV for diamond. To sim lify future derivations. Conductors..cls v. this minimum is a fundamental ro erty of the material.

silicon more useful. Note that 1 eV= 1:6 10. Fortunately. .” suffering from a very high resistance. it is os sible to modify the resistivity of silicon by re lacing some of the atoms in the crystal with atoms of another material. In an intrinsic semiconductor. 2. n= ni . is equal 3 The unit eV (electron volt) re resents the energy necessary to move one electr on across a otential difference of 1 V.1.19 J. the elec tron density.2 Modi cation of Carrier Densities Intrinsic and Extrins ic Semiconductors The “ ure” ty e of silicon studied thus far is an exam le of “intrin sic semiconductors.

Thus.5. i (2. Thus. how about these densities in a do ed material? It can be roved th at even in this case. .. the do ed silicon crystal is now called “extrinsic.5) where n and res ectively denote the electron and hole densities in the extrins ic semiconductor. How can atoms and increase n? n remain constant while we add more donor Equation (2.2 The above result seems quite strange. (2. Recall from Fig.” This electron is free to move. 2.1) for silicon]. four electrons with the neighboring silicon atoms.5 Loosely attached electon with hos horus do ing.” more s ec i cally. serving as a charge carrier. then the density of free electrons rises by the same amount. This occurs because many of the new electrons ¡ ¡ ¡ . an “n ty e” semiconductor to em hasize the abundance of free electrons.g. The quantity ni re resents the densities in the intrinsic semi conductor (hence the subscri t i) and is therefore inde endent of the do ing lev el [e. n = n2 : i (2. the electron and hole densities in an intrinsic semiconductor ar e equal.5) reveals that must fall below its intrinsic level as more n ty e do ants are added to the crystal. The controlled addition of an “im urity” such as hos horus to an intrinsic semiconductor is calle d “do ing. But. if N hos horus atoms are uniformly introduced in each cubic centimeter of a silicon crys tal. Eq. As re marked earlier. What ha ens if some P atoms are introduced in a silico n crystal? As illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exam le 2.1 Semiconductor Materials and Their Pro erties 25 to the hole density. 2. 2007 at 13:42 25 (1) Sec.4) We return to this equation later.cls v. 2006] June 30. 2.” Providing many more free electrons than in the intrinsic state. n = n2 . each P atom shares Si Si Si Si P e Si Si Figure 2.” and hos horus itself a “do ant.2 that hos horus (P) conta ins ve valence electrons. leaving the fth electron “unatta ched.

donated by the do ant “recombine” with the holes that were created in the intrinsic material. Solution Exercise Exam le 2.3 A iece of crystalline silicon is do ed uniformly with hos horus atoms. The do ing density is Why can we not say that n + should remain constant? .

Thus. 2006] June 30. ready to absorb Si Si Si B Si Si Si Figure 2. roviding holes as majority carriers. N boron atoms contribute N boron holes to the c onduction of current in silicon.1 by six orders of magnitude. We may naturally wonder if it is ossible to construct a “ ty e” semiconductor. The boron atom is ca lled an “acce tor” do ant.5) that (2. 2. As a result.2) and (2. the table in Fig.cls v.2 suggests that a boron (B) atom—with three v alence electrons—can form only three com lete covalent bonds in a silicon crystal (Fig. the fourth bond contains a hole. 2007 at 13:42 26 (1) 26 Cha .6 therefore exem li es a ty e semiconductor. If an intrinsic se Exercise At what do ing level does the hole density dro by three orders of magnitude? ¡ ¡ ¡ .6). 2. This exam le justi es the reason for calling electrons the “majority carriers” and hol es the “minority carriers” in an n ty e semiconductor. In other words. The structure in Fig. a free electron. For exam le. Indeed.7) (2. 2.8) Note that the hole density has dro ed below the intrinsic level by six orders o f magnitude. if we can do e silicon with an atom that rovides a n insuf cient number of electrons. 2 Basic Physics of Semiconductors 1016 atoms/cm3 .6) = ni n = 1:17 104 holes=cm3 2 (2. we can assume Solution n = 1016 electrons=cm3 It follows from (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then we may obtain many incom lete covalent bon ds. Let us formulate our results thus far. if a voltage is a lied across this iece of silicon. Since this electron density exceeds that ca lculated in Exam le 2. Determine the electron and hole densities in this material at t he room tem erature. The addition of 1016 P atoms introduces the same number of free electrons er cubic centimeter. thereby exchanging the roles of electrons and holes.6 Available hole with boron do ing. the res ulting current redominantly consists of electrons.

then the mobile charge densities are given by n2 (2.9) (2.10) Majority Carriers : n D ND Minority Carriers : Ni : .miconductor is do ed with a density of ND ( ni ) donor atoms er cubic centimete r.

some early diodes and transistors were based on germanium (Ge) rather than silicon. the above ex ressions are quite accurate. Exercise Can carbon be used for this ur ose? Figure 2. illustrating the ty es of charge carriers and their densities in semiconductors.2 as semiconductors and do ants? Solution Yes. Exam le 2. 2007 at 13:42 27 (1) Sec. Also. for exam le.11) (2.12) Since ty ical do ing densities fall in the range of 1015 to 1018 atoms=cm3 . 2.7 summarizes the conce ts introduced in this section. 2006] June 30. for a density of NA ( ni ) acce tor atoms er cubic centimeter: Majority Carriers : NA Minority Carriers : n A n2 (2. arsenic (As) is another common do ant.cls v.4 Is it ossible to use other elements of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Intrinsic Semiconductor Si Si Covalent Bond Si Valence Electron Extrinsic Semiconductor Silicon Crystal Silicon Crystal N D Donors/cm Si Si Si n−Ty e Do ant (Donor) Si P e Si 3 N A Acce tors/cm Si Si B Si Free Majority Carrier Si 3 Si Si Si −Ty e Do ant (Acce tor) Ni : . 2.1 Semiconductor Materials and Their Pro erties 27 Similarly.

2. th e mechanisms leading to the ow of current. we are ready to examine the movement of charge in semiconductors.1.7 Summary of charge carriers in silicon. i.e. ..3 Trans ort of Carriers Having studied charge carriers and the conce t of do ing.Free Majority Carrier Figure 2.

the mobility of electrons. 2 Basic Physics of Semiconductors Drift We know from basic hysics and Ohm’s law that a material can conduct current in res onse to a otential difference and hence an electric eld.6 We ex ect the velocity.”5 Semicon ductors behave in a similar manner. = 480 cm2 =V s. E : v E.16) . ! (2. since electrons move in a direction o osite to the electric eld. and hence (2. forcing some to ow from one end to the other.14) where is called the “mobility” and usually ex ressed in cm2 =V s.5 ! (2. we must ex ress the velocity vector as ! ve = . on the other hand. As shown in Fig. v . 2. the charge carriers ar e E Figure 2.n E : For holes.8 Drift in a semiconductor. (2. n = 1350 cm2 =V s. accelerated by the eld and accidentally collide with the atoms in the crystal. ev entually reaching the other end and owing into the battery.cls v. Of course.8. leading to a constant v elocity for the carriers. and that of holes.13) v = E.4 The eld acceler ates the charge carriers in the material. 2007 at 13:42 28 (1) 28 Cha . 2006] June 30.15) ! vh = E : Exam le 2. to be ro ortional to the electric eld strength.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For exam le in silic on. Movement of charge carriers due to an electric eld is called “drift. The acceleration due to the eld and the collision with the crystal counteract.

o en) ex eriences. electrons take 1 m=1:35 107 cm=s = 7:4 s to cross the 1 m leng th. to distance: Vab 4 Recall that the otential (voltage) difference. with res ect 5 The convention for direction of current assumes ow of ositive sitive voltage to a negative voltage. V . where L is the length. De termine the velocity of the electrons. Since the material is uniform. 6 n is analogous to the “terminal velocity” that a sky diver with a ly. we have E = V=L. the current is considered to have a direction from B to A. is equal to the negative integral of the electric eld. charge from a o oint A to oint This henomeno arachute (ho eful ¡ ¡ . In other words. 000 V/cm and hence v = n E = 1:35 107 cm/s.A uniform iece of n ty e of silicon that is 1 m long senses a voltage of 1 V. E . Thus. ba Edx. Solution R = . E = 10. if electrons ow from B . Thus.

n E . (2. We may loosely say.17) where v W h re resents the volume.” i. In other words. and since W h is the cross section area of the bar.v W h n q.. and is ex ressed in A=cm2 .1 Semiconductor Materials and Their Pro erties 29 Exercise What ha ens if the mobility is halved? With the velocity of carriers known. “the current is e qual to the charge velocity times the charge density. considering a cross section of the bar at x = x1 and taking two “sna shots” a t t = t1 and t = t1 + 1 second. we have: I = .18) where Jn denotes the “current density. we note that the total charge in v meters asses the cross section in 1 second.cls v. v = . and negative or ositive signs are tak en into account ro erly.18 ) is modi ed to n q.20) Jtot = n E n q + E q = qn n + E: . Since the bar has a width of W . 2. Since for electr ons. (2. (2. Assuming the electrons move with a velocity of v meters W t = t1 L h t = t1 + 1 s x1 V1 x x1 V1 x Figure 2. and the negative sign accounts for the fact that electrons carry negative charge.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we write Jn = n E (2. 2006] June 30. Let us now reduce Eq.19) (2. Equivalently .e. n q denotes the charge density in coul ombs. v m/s.17) to a more convenient form. the current is equal to the tota l charge enclosed in v meters of the bar’s length. 2. In the resence of both electrons and holes. how is the current calculated? We rst note t hat an electron carries a negative charge equal to q = 1:6 10.9 Current ow in terms of charge density. Eq. the current assing through a unit cro ss section area. a hole carries a ositive charge of the same value.19 C. Now su ose a voltage V1 i s a lied across a uniform semiconductor bar having a free electron density of n (Fig. 2007 at 13:42 29 (1) Sec.9). (2.” with the understanding that “current” in fact refers to current density.

eld E in .This equation gives the drift current density in res onse to an electric a semiconductor having uniform electron and hole densities.

In reality. Thus.22) (2. 2006] June 30. Exercise How should the carrier densities be chosen so that the electron drift current is twice the hole drift current? Velocity Saturation We have thus far assumed that the mobility of carriers in sem iconductors is inde endent of the electric eld and the velocity rises linearly wi th E according to v = E . equal electron and hole drift curren ts can occur for only a very lightly do ed material. 2007 at 13:42 30 (1) 30 Cha .cls v. eventually reaching a saturated level. 2. As a result.10).6 In an ex eriment. How should the carrier densities be chosen? Solution We must im ose n n = . and hence (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26) Since and n are of the same order as ni . v varies “sublinearly” at high electric elds. Called “velocity sa turation. i ¡ . yielding (2.24) = 1350=480 = 2:81. This is because the carriers collide w ith the lattice so frequently and the time between the collisions is so short th at they cannot accelerate much. it is desired to obtain equal electron and hole drift currents .” this effect manifests itself in some modern transistors. vsat (Fig.23) (2.21) (2. v no longer follows E linearly. if the electric eld a roaches suf ciently hig h levels. limiting the For exam le. This con rms our earlier noti on of majority carriers in 3 semiconductors having ty ical do ing levels of 1015 1018 atoms=cm . 2 Basic Physics of Semiconductors Exam le 2.25) (2. n = r = n ni r n = ni : n = 1:68ni n = 0:596ni: n = : n We also recall that n = n2 . in silicon.

. we must modif y v = E accordingly.This section can be ski ed in a rst reading. The ex ression for must ¡ . as a eld de endent arameter. In order to re resent velocity saturation. A sim le a roach is to view the slo e. erformance of circuits.

therefore gradually fall toward zero as E rises.30) A uniform iece of semiconductor 0. 2. (2. (2. v ! vsat . but a roach a constant value f or small E .10 Velocity saturation. where 0 is the “low eld” mobility and b a ro ortionality factor.e. 2006] June 30. We may consider “effec tive” mobility at an electric eld E . i. If the low eld mobility is equal to 1350 cm2 =V s and the saturation velocity of the carriers 107 cm/s. 2007 at 13:42 31 (1) Sec. v= Exam le 2.cls v. In other words. we have vsat = b0 .1 Semiconductor Materials and Their Pro erties Velocity 31 vsat 2 1 E Figure 2. Also. calculate the maximum allowab le voltage such that the effective mobility is only 10% lower than 0 .2 m long sustains a voltage of 1 V. Solution We have ¡ ¡ .27) as the (2..29) and hence b = 0 =vsat . determine the effective mobility.28) v = 1 + 0bE E: Since for E ! 1.7 0 E: 1 + 0 E vsat (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus. = 1 +0bE .

E=V L It follows that (2.31) (2.33) (2.32) = 50 kV=cm: = 0 1 + 0 E vsat 0 = 7:75 = 174 cm2 =V (2.34) (2.35) s: .

38) = 823 V=cm: 10.36) sat E = 1 v 9 (2. the dro begins to “diffuse. then 0:90 = and hence 0 .37) (2. 2007 at 13:42 32 (1) 32 Cha . another mechanism can lead to current ow.” that is. A device of length 0. Su ose a dro of ink falls into a glass of water. the ink molecules tend t o ow from a region of high concentration to regions of low concentration. Exercise At what voltage does the mobility fall by 20%? Diffusion In addition to drift. This me chanism is called “diffusion.cls v.11 Diffusion in a semiconductor. 2006] June 30. Even i n the absence of an electric eld. 1 + 0 E vsat 0 (2. a nonuniform charge ro le is crea ted along the x axis.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thereby carrying an electric current so long as the nonuniformity is sus tained. Semiconductor Material Injection of Carriers Nonuniform Concentration Figure 2.5 mV. Diffusion is therefore distinctly different from drift.4 cm = 16:5 mV.” A similar henomenon occurs if charge carriers are “dro ed” (injected) into a semiconductor so as to create a nonuniform density.11 conc e tually illustrates the rocess of diffusion.2 m ex eriences such a eld if it sustains a voltage of 823 V=c m 0:2 This exam le suggests that modern (submicron) devices incur substantial velocity saturation because they o erate with voltages much greater than 16. Introducing a high local concentrati on of ink molecules. 2 Basic Physics of Semiconductors If the mobility must remain within 10% of its low eld value. Figure 2. ¡ ¡ . and the carriers continue to “roll down” the ro le. A source on the left continues to inject charge carriers into the semiconductor. the carriers move toward regions of low concent ration.

11? Where do the charge carriers go after they o the end of the ro le at the far right? And. What serves as of carriers in Fig. . 2. 2.8 A source injects charge carriers into a semiconductor bar as shown in Fig. why e?! Well.12. the source roll down t should we car the next se Exam le 2. most im ortantly. atience is a virtue and we will answer these questions in ction.The reader may raise several questions at this oint. Ex lain how the current ows.

assuming current ow only i n the x direction. Our qualitative study of diffusion suggests that the more nonuniform the concent ration.39) where n denotes the carrier concentration at a given oint along the x axis.40) I = AqDn dn . leading to current ow from the source toward the two end s of the bar.1 Semiconductor Materials and Their Pro erties Injection of Carriers 33 0 x Figure 2.cls v. As with the convention used for the drift current. the larger the current.39) can be written as I Aq dn : dx Thus. dx (2. Eq. For exam le.12 Injection of carriers into a semiconductor. we can write: I dn . we normalize the diffusion current to the cross section area. and the semiconduct or has a cross section area of A. obtaining the curr ent density as ¡ Exercise Is KCL still satis ed at the oint of injection? ¡ . 2. 2007 at 13:42 33 (1) Sec.41) where Dn is a ro ortionality factor called the “diffusion constant” and ex ressed i n cm2 =s. If each carrier has a charge equal to q .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. dx (2. Dn = 34 cm2 =s (for electrons). Solution In this case. in intrinsic silicon. and D = 12 cm2 =s (for holes). two symmetric ro les may develo in both ositive and negative dire ctions along the x axis. More s eci cally. (2. 2006] June 30. We call dn=dx the concentration “gradient” with res ect to x. (2.

a gradient in hole concentration yields: (2.43) .42) d J = .qD dx : (2.Jn = qDn dn : dx Similarly.

the total current d ensity is given by d Jtot = q Dn dn . 2007 at 13:42 34 (1) 34 Cha .9 . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. D dx : dx Exam le 2.cls v. 2 Basic Physics of Semiconductors With both electron and hole concentration gradients resent.

46) = .13).11 again.e. De termine the diffusion current. Exercise Re eat the above exam le for holes. this o bservation re ares us for the next exam le. . 2.14): N Injection 0 L x (2.(2.13 Current resulting from a linear diffusion ¡ ro le. N Injection 0 L x Solution We have Jn = qDn dn dx (2. ro le.44) Consider the scenario de icted in Fig. i. Su ose the electron concentr ation is equal to N at x = 0 and falls linearly to zero at x = L (Fig.. Exam le 2. all of the electrons entering th e material at x = 0 successfully reach the oint at x = L. L Figure 2.qDn N : L The current is constant along the x axis. 2.47) nx = N ex d .45) (2. While obvious. 2.10 Re eat the above exam le but assume an ex onential gradient (Fig.14 Current resulting from an ex onential diffusion Figure 2.x .

. What ha ens to these electrons? Does this exam le vio late the law of conservation of charge? These are im ortant questions and will be ans wered in the next section.15 Summary of drift and diffusion mechanisms. some electrons vanish while traveling from x = 0 to the right. thus roviding a 7 The factor dn dx d J = − q D dx Jn = q Dn Jn = q n n E J = q E ¡ . in ada ters that charge the batteries of cell hones.qDn N ex .” this result is roved in semiconductor hysics texts . 2007 at 13:42 35 (1) Sec. [1]. Note that kT=q 26 mV at T = 300 K.48) dx = . That is. 2. e.cls v.g..2 We begin our study of semiconductor devices with the n junction for three reaso ns.15 summarizes the charg e trans ort mechanisms studied in this section. (1) The device nds a lication in many electronic systems.g. 2006] June 30.7 Solution We have Jn = qDn dn (2. (2) The n junction is among the sim le st semiconductor devices.x : (2. 2.2 PN Junction 35 where Ld is a constant. Drift Current Diffusion Current E q Figure 2. e. Exercise At what value of x does the current density dro to 1% its maximum value? Einstein Relation Our study of drift and diffusion has introduced a factor for e ach: n (or ) and Dn (or D ). res ectively. Figure 2. It can be roved that and D are rela ted as: D = kT : (2. the current is not constant along the x axis.49) Ld Ld Interestingly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.50) Called the “Einstein Relation.

.PN Junction Ld is necessary to convert the ex onent to a dimensionless quantity.

we study the ro erties and I/V charac teristics of n junctions.” res ectively. the ”cathode. In this section. De icted in Fig. (3) The n junction also serves as art of transistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. An interesting situ ation arises if we introduce n ty e and ty e do ants into two adjacent section s of a iece of semiconductor. The following outline shows our thought rocess. 2007 at 13:42 36 (1) 36 Cha . the terminals are o en and 2.cls v. The and n sides are called the “anode” and n Cathode Anode Si Si P e Si B Si (a) Si Si Si Si (b) Figure 2.” thi s structure lays a fundamental role in many semiconductor devices. We also use the term “diode” to refer to n junctions.. and an electric eld or a concentrat ion gradient leads to the movement of these charge carriers.16 PN junction. 2. indi cating that our objective is to develo circuit models that can be used in analy sis and design. We say the junction is in “equilibr ¡ ¡ . 2006] June 30. PN Junction in Equilibrium Let us rst study the n junction with no external conn ections.e.1 no voltage is a lied across the device. 2 Basic Physics of Semiconductors good entry oint into the study of the o eration of such com lex structures as t ransistors. We have thus far seen that do ing roduce s free electrons or holes in a semiconductor.16 and called a “ n junction. PN Junction in Equilibrium De letion Region Built−in Potential PN Junction Under R everse Bias Junction Ca acitance PN Junction Under Forward Bias I/V Characterist ics Figure 2.2.17 Outline of conce ts to be studied. i.

3 and ND Determine the hole and electron concentrations on the two sid es. We be gin by examining the interface between the n and sections.3 .” While seemingly of no ractical value. The shar concentration gradient for both electrons and holes across the jun ction leads to two large diffusion currents: electrons ow from the n side to the side.11) and (2. Exam le 2.ium. (2.18.11 = 51015 cm. and holes ow in the o osite direction.12). a large excess of electro ns. From Eqs. we introduce the nota tions shown in Fig. we ex ress the concentrations of holes and electron s on the side Solution . recognizing that on e side contains a large excess of holes and the other. Since we must deal with both elec tron and hole concentrations on each side of the junction. this condition rovides insights that rove useful in understanding the o eration under nonequilibrium as well. 2. A n junction em loys the following do ing levels: NA = 1016 cm.

3 (2.58) (2.3 2 = 1:081016 cmcm .3 (2.18 .3 2 = 1:08 1015 cm.52) (2.cls v.3 D Note that the majority carrier concentration on each side is many orders of magn itude higher than the minority carrier concentration on either side. 2006] June 30.56) (2.59) (2. 2007 at 13:42 37 (1) Sec.55) 1010 .51) (2. Exercise 5 = 2:3 104 cm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.60) 1010 cm.54) (2.3 : nn ND NA n Ni n2 n N i n2 nn n Minority Carriers Minority Carriers Figure 2.3 : = 5 1015 cm. 2.2 PN Junction n Majority Carriers 37 n Majority Carriers res ectively as: = 1016 cm. nn : Concentration of electrons on n side n : Concentration of holes on n side : Concentration of holes on side n : Concentration of electrons on side .53) (2.3 A Similarly. the concentrations on the n side are given by 1:1 104 cm.57) (2.

This is because. if the terminals a re left o en (equilibrium condition). The diffusion currents trans ort a great deal of charge from each side to the ot her. but they must eventually decay to zero. the device cannot carry a net current inde n itely. . another effect dominates the situation and sto s the diffusion currents we ll before this oint is reached. We must now answer an im ortant question: what sto s the diffusion curren ts? We may ostulate that the currents sto after enough free carriers have move d across the junction so as to equalize the concentrations on the two sides. How ever.Re eat the above exam le if ND dro s by a factor of four.

” t=0 n − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − t = t1 n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − t= + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − + − − −+ − − − + − − − − − − + − − − − − − + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Free Free Electrons Holes Positive Negative Donor Acce tor Ions Ions De letion Region Figure 2. the junction evolves with tim e as conce tually shown in Fig. 2 Basic Physics of Semiconductors To understand this effect. and the diffusion currents continue to ex ose more ions as time rogresses.. a ositive ion is left behind.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Now recall from basic hysics that a article or object carrying a net (nonzero) charge creates an electric eld around it. 2006] June 30. 2.19. the junction is sudd enly formed at t = 0. In this illustration. . i. Consequently. 2. the eld tends to force ositive charge ow from n − − − − − − − − − − − − − − − − − − − − − − − − E + + + + + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + eld in a Figure 2. Thus. an electric eld emerges as shown in Fig.20. the immediate vicinity of the junction is de let ed of free carriers and hence called the “de letion region.19 Evolution of charge concentrations in a n junction.8 Interestingly.cls v.20 Electric n junction.e. 2007 at 13:42 38 (1) 38 Cha . we recognize that for every electron that de arts fro m the n side. with the formation of the de let ion region.

E falls. the d rift currents resulting from the electric eld exactly cancel the diffusion curren ts due to the gradients. . i. At x = a.21..e. the negative and ositive charge exactly cancel each other and E = 0. 2.b.. in equilibrium.12 Solution 8 The direction of the electric eld is determined by lacing a small ositive tes t charge in the region and watching how it moves: away from ositive charge and toward negative charge. we can say. As we ass x = 0. Alternatively. the magnitude of E rises as x a roaches zero. we note that the absence of net charge yield s E = 0. We therefore surmise that th e junction reaches equilibrium once the electric eld is strong enough to com lete ly sto the diffusion currents. At x . i. Sketch the electric eld as a function of x. the de letion regio n has a width of b on the n side and a on the side.left to right whereas the concentration gradients necessitate the ow of holes fro m right to left (and electrons from left to right). Beginning at x .e. each ositive donor ion contributes to the electric eld. In the junction shown in Fig. the negative ac ce tor atoms begin to contribute negatively to the eld.b. Exam le 2.

the n each side of this equation is zero while electrons continue to accumulate on t he side and holes on the n side. using (2.63).n j = jIdi .n j: Exercise Noting that otential voltage is negative integral of electric o distance. Since the electric eld E = . we can com ute this otential. however. 2007 at 13:42 39 (1) Sec.62) or (2. allows an unrealistic henomenon: if the number of the electrons owing from the n side to t he side is equal to that of the holes going from the side to the n side.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. lot the otential as a function of x. j jIdrift. j = jIdi .” In fact. This condition.n j. 2006] June 30. Figure 2. eld with res ect t From our observation regarding the drift and diffusion currents under equilibriu m.63) Built in Potential The existence of an electric eld within the de letion region s uggests that the junction may exhibit a “built in otential. (2.61) where the subscri ts and n refer to holes and electrons. and since (2.dV=dx.2 PN Junction n − − − − − − − − − − N − − D − − − − − − − − − − E + + + + + + + + + + 0 − − − − − − − − − − 39 + + + + + + + + + + + NA + + + + + + + + + + a x −b E −b 0 a x n junction.62) (2. 2.n j = jIdi . res ectively. + Idi .21 Electric ¡ eld ro le in a .62) can be written as ¡ jIdrift. and eac h current term contains the ro er olarity. We must therefore im ose the equilibrium cond ition on each carrier: (2. + Idrift.cls v. we may be tem ted to write: jIdrift.

(2. dV = D dx : dx Dividing both sides by and taking the integral. we obtain .65) Zx x1 2 . we have (2.66) Z n d dV = D .d q E = qD dx . d .64) (2.

V x2 . Thus. A silicon n junction em lo ys NA = 2 1016 cm. this equation lays a central role in many semiconductor devices. 2 Basic Physics of Semiconductors n x1 x2 x Figure 2. V x1 = . Finally.69) Ex ressing the built in otential in terms of junction arameters. we can re lace D = with kT=q : n (2. from Einstein’s relation. 22).50). Also.11) and (2. (2.3 and ND built in otential at room tem erature (T = 300 K).10) for and n yields V0 = kT ln NA ND : q n2 i (2.cls v. D ln n : .67) The right side re resents the voltage difference develo ed across the de letion region and will be denoted by V0 . res ectively (Fig.64) for electron drift and diffusion currents. derive an equation for V0 in terms of nn and n .13 = 4 1016 cm. Determine the Solution ¡ ¡ jV0 j = kT ln : q n junction.1 that ni T Exam le 2. Eq. 2007 at 13:42 40 (1) 40 n nn n Cha . 2006] June 30.68) Exercise Writing Eq. 2. and carrying out t he integration. (2.22 Carrier ro les in a where n and are the hole concentrations at x1 and x2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 . (2. using (2. R ecall from Exam le 2.

= 300 K = 1:08 (2.71) 1016 4 16 V0 1010 cm.70) (2.3 . Thus. 26 mV ln 2 1:08 1010 210 768 mV: Exercise By what factor should ND be changed to lower V0 by 20 mV? .

We wish to reexamine the results obtained in equilibrium for the case of revers e bias. How muc h does V0 change if NA or ND is increased by one order of magnitude? Exam le 2. 2006] June 30. 2007 at 13:42 41 (1) Sec. w hich exhibits no tendency for diffusion and hence no need to create a built in v oltage. w e can now study its behavior under more 2.”).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the term “bias” indicates o eration under some “desirable” conditions. VR enhances the eld. VT ln NAn2ND n = VT ln 10 i i (2. Th is henomenon is in contrast to the behavior of a uniform conducting material. the de letion region be widened.2 PN Junction 41 Equation (2. ! Since under equilibrium. PN Junction Under Reverse Bias Having analyzed the n junction in equilibrium. Used as a noun or a verb.23. However. Let us rst determine whether the external voltage enhances the built in e lectric eld or o oses it. How is that ossible? We observe that the builtin otential is develo ed to o ose the ow of diffusion currents (and is. sometimes called the “ otential barrier.14 Solution We can write V0 = VT ln 10NA2 ND . We say the junction is under “reverse bias” to em hasize the connection of the ositive voltage to the n terminal. an im ortant observation will r 60 mV at T = 300 K: ¡ ¡ ¡ . requiring that more acce tor and donor ions be ex osed and. What ha ens to the diffusion and drift currents? Since the external voltage has stre ngthened the eld.74) Exercise How much does V0 change if NA or ND is increased by a factor of three? An interesting question may arise at this oint. 2.cls v.72) (2. We will study the conce t of biasing extensively in this and following cha ters. But.2. 2.69) reveals that V0 is a weak function of the do ing levels.73) (2. where the voltage source makes th e n side more ositive than the side. therefore. Let us begin by a lying an external vo ltage across the device as shown in Fig. In other words. the barrier rises even higher than that in equilibrium.2 interesting and useful conditions. the junction carries a negligible cu rrent under reverse bias. in fact. The junction carries no net cur rent (because its terminals remain o en). but it sustains a voltage. a reverse biased n junct ion does not seem articularly useful.9 With no current conduction. E is directed from the n si de to the side. thus r ohibiting the ow of current. a higher electric eld can be sustained only if a larger amount of xed charge is rovided.

as VB increases. more ositive charge a ears on the n side and more negative charge on the side. We note that in Fig. 9 As ex lained in Section 2.3. the current is not exactly zero.ove otherwise.23. . 2.2.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. V R2 + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − − − − − − − − − − − − − V R1 + + + + + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + . Thus.24(a)].cls v. In essence. We also ass ume the charge in the de letion region equivalently resides on each late. 2007 at 13:42 42 (1) 42 n − − − − − − − − − − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − Cha . we can view the conductive n and sections as the two lates of the ca acitor. 2006] June 30. 2. 2 Basic Physics of Semiconductors + + + + + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − VR Figure 2.23 PN junction under reverse bias. the device o erates as a ca acitor [Fig.

+ + + + + + + + + + + + + + + + + + + + − − − − − V R1 (a) V R2 (more negative than V R1 ) (b) Figure 2. The junction therefore dis lays a voltage de endent ca acitance. revealing that the ca acitance of the structure decreases as the two lates mo ve away from each other. as VR in creases.24 Reduction of junction ca acitance with reverse bias. we recognize that. After all.24(a) can be drawn as in Fig. 2. It can be roved that the ca acitance of the junction er unit area is equal to Cj = r Cj0 1 . the use of a n junction for this ur ose is n ot justi ed. reverse biased n junctions exhibit a unique ro erty that becom es useful in circuit design. (2.75) ¡ ¡ . 2. That is. the conce tual diag ram of Fig. so does the width of the de letion region.23. since any two ara llel lates can form a ca acitor. Returning to Fig. VR V0 . 2.24(b) for increasing values of VR . But. The reader may still not nd the device interesting.

Determine the V0 = VT ln NA ND n2 = 0:73 V: i Thus.25 Junction ca acitance under reverse bias.8 F=cm2 : V 2 A+ D 0 Solution We rst obtain the built in otential: A n junction is do ed with NA = 2 th (a) VR = 0 and VR = 1 V.cls v.10 Plotted in Fig.) The value of Cj 0 is in turn given by r q NN Cj0 = si A D 2 NA + ND V0 1. 2006] June 30. 8:85 Exam le 2.25.78) = 0 and q = 1:6 10. Cj 0 VR Figure 2.15 = 9 1015 cm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (This equation assumes VR is negative for reverse bias. Cj indeed decreases as VR increases.77) (2.14 F/cm.3. for VR (2.2 PN Junction 43 where Cj 0 denotes the ca acitance corres onding to zero bias (VR = 0) and V0 is the built in otential [Eq. we have r q NN 1 D Cj0 = si N A N = 2:65 10. 1016 cm. 2007 at 13:42 43 (1) Sec.69)]. (2.76) where si re resents the dielectric constant of silicon and is equal to 11:7 10.3 and ND ca acitance of the device wi ¡ ¡ . 2.19 C. 2. (2.

. 1 + VR V 0 (2.g. where 1 fF (femtofarad) = 10.81) = 1 V. 11.80) In microelectronics.7). For VR (2. and 0 the dielectric constant of vacuum (8:85 10.79) (2. we deal with very small devices and may rewrite this result as Cj0 = 0:265 fF=m2 ..(2.14 F/cm).15 F. whe re r is the “relative” dielectric constant and a dimensionless factor (e.82) Cj = r Cj 0 = 0:172 fF=m2 : (2.83) 10 The dielectric constant of materials is usually written in the form r 0 .

1 . Assume the circuit o erates at 2 GHz at a reverse voltage of 0 V.16 A cell hone incor orates a 2 GHz oscillator whose frequency is de ned by the reson ance frequency of an LC tank (Fig. as demonstrated by the following exam le.cls v.15.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we obtain (2. 2.85) (2.jC!res . Oscillator C VR L Figure 2. yielding a total device ca acitance of Cj.86) = 530 fF: fres = 21 At VR 1 : LC ¡ ¡ .84) = 0. If the tank ca acitance is realized as the n junction of Exam le 2. Nonetheless. a voltage de endent ca acitor leads to interesting ci rcuit to ologies. Cj = 0:265 fF/m2 .26 Variable ca acitor used to tune an oscillator. calculate the change in the oscillation freque ncy while the reverse voltage goes from 0 to 2 V.tot VR = 0 = 0:265 fF=m2 2000 m2 Setting fres to 2 GHz. Thus. 2007 at 13:42 44 (1) 44 Cha .26). 2 Basic Physics of Semiconductors Exercise Re eat the above exam le if the donor concentration on the results in the two ca ses. N side is doubled. Solution Recall from basic circuit theory that the tank “resonates” if the im edances of the inductor and the ca acitor are equal and o osite: jL!res = . and the junction area is 2000 m2 . the resonance frequency is equal to (2. Com are the The variation of the ca acitance with the a lied voltage makes the device a “nonl inear” ca acitor because it does not satisfy Q = CV . Exam le 2. 2006] June 30.

L = 11:9 nH: If VR goes to 2 V.88) (2.87) Cj.tot VR = 2 V = r Cj0 1 + 0:2 73 = 274 fF: 2000 m2 (2.89) . (2.

ersonal com uters. (2. ultimately arriv ing at a circuit model.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This condition is called “forward bias. 2. a reverse biased n junction carries a negligible current but exhibi ts a voltagede endent ca acitance. micro rocessors. a current ows through the diode that is ro ortional to the light intensity.2 GHz. n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − PN Junction Under Forward Bias + + + + + + + + + + + + + + + + + + + + + + + + + + + + VF Figure 2. Re eat the above exam le for this freq uency. Note that we have tacitly develo ed a circuit model for the device under this condition: a sim le ca acitance whose value is given by Eq. Another interesting a lication of reverse biased diodes is in digital cameras (Cha ter 1). With a reverse bias. we have fres VR = 2 V = 2:79 GHz: (2.84). (2. If light of suf cient energy is a lied to a n j unction.” 2.90) An oscillator whose frequency can be varied by an external voltage (VR in this c ase) is called a “voltage controlled oscillator” and used extensively in cell hones. electrons are dislodged from their covalent bonds and hence electron ho le airs are created. We say the n junction o erates as a “ hotodiode. 2007 at 13:42 45 (1) Sec. etc.cls v.75).2.” We also wish to com ute the resulting curre nt in terms of the a lied voltage and the junction arameters. In summary. 2006] June 30. assuming the junction area is still 2000 m2 but the inductor value is scal ed to reach 5. Exercise Some wireless systems o erate at 5. the electrons are attracted to the o sitive battery terminal and the holes to the negative battery terminal. we note that the otential barrier develo ed in the de letion region determines the device’s desire ¡ ¡ ¡ ¡ .2 GHz. From our study of the device in equilibrium and reverse bias.2 PN Junction 45 Using this value along with L = 11:9 nH in Eq. 2. As a res ult.27).3 Our objective in this section is to show that the n junction carries a current if the side is raised to a more ositive voltage than the n side (Fig.27 PN junction under forward bias.

to conduct. We therefore surmise that VF in fact lowers the otential barrier by weakening the eld. In forward bias. tends to create a eld dir ected from the side toward the n side—o osite to the built in eld that was devel o ed to sto the diffusion currents. ¡ . thus allowing greater diffusion curr ents. VF . the external voltage.

f V0 . Figure 2. V ex V T where the subscri t e em hasizes equilibrium conditions [Fig.cls v. As the jun ction goes from equilibrium to forward bias.f to be much higher than n. 1: VT ex V VT (2.28 Carrier ro les (a) in equilibrium and (b) under forward bias. le ading to a ro ortional change in the diffusion currents.28(b) illustrates the results of our analysis thus far.28(a)] and VT n nn.e 0 . the s lowered by an amount equal to the a lied voltage: ¡ otential barrier i . n. n and n increase dramatically.f .93) (2.f n.f = . 2006] June 30. Since the ex onential denominator dr o s considerably.94) NA 0 ex VF .f (2. 2.91) = kT=q is called VF (a) Figure 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e .e = .f . 2 Basic Physics of Semiconductors To derive the I/V characteristic in forward bias.68) for t he built in voltage and rewrite it as n.92) (2. In forward bias.e = V0 . for the electron concentration on the n = n.e (it can be roved t hat .e n .11 We can ex ress the c hange in the hole concentration on the n side as: the “thermal voltage” ( 26 mV at T = 300 K). 2007 at 13:42 46 (1) 46 Cha . ex V0 ex V VT T side: where the subscri t f denotes forward bias.e .e n. In other words.e NA ). we begin with Eq.e nn. This statement a lies to the n side as w ell. (b) n.f n. the minority carrier concentration on the side rises ra idly with the forward bias voltage while the majority carrier conc entration remains relatively constant.f .f n .e n . (2.95) Similarly. we ex ect n. VF : ex V T (2. VF .f n .

96) . 1: V VT ex V 0 T 11 The width of the de letion region actually decreases in forward bias but we n eglect this effect here.n ND ex VF . (2.

Determine IS for the junction of Exam le 2.2)]. V T (2. (2..e. Using q Exam le 2.15 A. 2006] June 30. Exercise What junction area is necessary to raise IS to 10. i The increase in the minority carrier concentration suggests that the diffusion currents must rise b y a ro ortional amount above their equilibrium value. A is the cross section area of the device. i. we have 1010 electrons=cm3 [Eq. the ex onential term in Eq.100) Since IS is extremely small.13 at T and L = 30 m.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. res ectively.99) In this equation.g. and Ln and L are e lectron and hole “diffusion lengths. Note that the rst and second terms in the a rentheses corres ond to the ow of electrons and holes.17 A: = 1:6 10. 2007 at 13:42 47 (1) Sec.17 = 300K if A = 100 m2 . 1 + ND ex VF . Diffusion lengths are ty ically in the range of tens of micrometers. Dn = 34 cm2 =s. (2.” res ectively. and D n IS = Aqn2 NDL + ND : i A n D L . Solution IS = 1:77 (2. Ln = 20 m.cls v. 10. ni = 1:08 = 12 cm2 =s. (2. 2..2 PN Junction 47 Note that Eq.69) indicates that ex V0 =VT = NA ND =n2 .98) must assume very large values so as to yield a useful amount (e. 1: V V VT VT ex V 0 ex V 0 T T Itot = IS ex VF .98) where IS is called the “reverse saturation current” and given by (2. Itot NA ex VF . 1. 1 mA) for Itot . it can be roved that [1] (2.19 C.97) Indeed.

as the electrons enter the side and roll down the gradient. the minority carrier con centrations must vary as shown in Fig.An interesting question that arises here is: are the minority carrier concentrat ions constant along the x axis? De icted in Fig.10 and the question raised in conjunction w ith it: if the minority carrier concentration falls with x. im lying that the charge carriers do not ow dee into th e and n sides and hence no net current results! Thus. 2.29(b) so that diffusion can occur. which are abundant in this region. such a scenario would suggest that electrons continue to ow from the n side to the side. This observation reminds us of Exam le 2. but exhibit no tendency to go beyond x = x2 because of the lack of a gradient.29(a). they gradually r ecombine with the holes. A similar sit uation exists for holes. 2. what ha ens to the carriers and how can the current remain constant along the x axis? Interestingly . ¡ ¡ .

f . 2006] June 30.29 (a) Constant and (b) variable majority carrier letion region.f x + + + + .cls v. it is rimarily com rised of maj Figure 2. ro les ioutside the de . 2007 at 13:42 48 (1) 48 Cha . 2 Basic Physics of Semiconductors n Electron Flow − ++ − + −− + Hole Flow n Electron Flow − ++ − + − Hole Flow nn.f − x1 x2 VF (a) x1 x2 VF (b) x Similarly. in the immediate vicinity of the de letion region. the holes entering the n side recombine with the electrons. but towards the far contacts. Thus.f n .f − − − n .f n. the current consists of mostly m inority carriers.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.f n.f nn.

2. (Why is this ex ected?) As VD becomes ositive and exceed s several VT . n −− − − −− − − −− ++ + + + + ++ ++ −− − − − − −− −− + ++ + ++ + + ++ x VF Figure 2. the a lied voltage en hances the eld. raising the diffusion cu rrents substantially. We hereaft er assume ex VD =VT 1 in the forward bias region. rohibiting current ow. As ex ected. In reverse bias. We hereafter write the junction equation a s: ID = IS ex VD . It can be roved that Eq.30). the external voltage o oses the built in otential.IS : (2.2. (2. then ex VD =VT 1 and ID . the ex onential term grows ra idly and ID IS ex VD =VT . 2. the two com onents a dd u to Itot . VD = 0 yields ID = 0.e.4 I/V Characteristics Let us summarize our thoughts thus far. At each oint along the x axis.10 1) also holds in reverse bias. 1.. V T (2.ority carriers (Fig. on the other hand.102) ¡ ¡ .101) where ID and VD denote the diode current and voltage.30 Minority and majority carrier currents. i. In forward bia s. res ectively. If VD 0 and jVD j reaches several VT . for negative VD .

99)].31 I V characteristic of a n junction. Determine the forward bias current of the com osite device for VD = 300 mV and 8 00 mV at T = 300 K.32 Equivalence of n n A VF VF arallel devices to a larger device.17 A for each junction. view the current under reverse bias as “leakage.tot VD = 300 mV = 2IS ex VD .17 indicates that IS is ty ically very small. (2. 2.104) = 800 mV: ID.32) behave as a single j unction with twice the IS .13.” Exam le 2. Thus. the total current is equal to (2.17. revealing why IS is called the “reverse saturation current. From Exam le 2. 2007 at 13:42 49 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.31 lots the overall I/V characteristic of the junction. IS Solution = 1:77 10. For ex am le.103) (2. two identical devices laced in arallel (Fig.cls v. ¡ I S ex Figure 2. 2. A n 2A Exam le 2. for VD A: Figure 2.” Note that IS and hence the junctio n current are ro ortional to the device cross section area [Eq.2 PN Junction 49 ID VD VT VD −IS Figure 2.18 Each junction in Fig. 2. 1 VT = 3:63 Similarly. 2006] June 30.32 em loys the do ing levels described in Exam le 2. We therefore Reverse Bias Forward Bias .

ID.105) Exercise How many of these diodes must be with a laced in arallel to obtain a current of 100 A .tot VD = 800 mV = 82 A: (2.

meaning VD changes by More generally.108) (2. 2007 at 13:42 50 (1) 50 Cha . (a) Determine the change in ID if VD is maintained consta nt.106) = VT ln ID + VT ln 10 IS = VD + VT ln 10: IS (2.107) (2. 2 Basic Physics of Semiconductors voltage of 750 mV.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the new current is given by ID1 = 10IS ex VD VT = 10ID : I VD1 = VT ln 10D I ¡ Thus. Assume ID IS ex VD =VT .e. an n fold change in . (a) Since IS Solution A. VT We 60 ID ln 10 60 mV (at T = 300 K) to accommodat say the device exhibits a 60 mV/decade c mV for a decade (tenfold) change in ID . the diode voltage must rise by e a tenfold increase in the current. How much change in VD is required? Solution Let us rst ex ress the diode voltage as a function of its current: We de ne I1 = 10ID and seek the corres onding voltage. haracteristic..109) Exercise By what factor does the current change if the voltages changes by 120 mV? Exam le 2.19 A diode o erates in the forward bias region with a ty ical current level [i. Exam le 2. VD1 : V = V ln 10ID D1 T VD = VT ln ID : I S (2. 2006] June 30. translates to a change of VT ln n in VD ¡ . ID IS ex VD =VT ]. (b) Determine the change in VD if ID is maintained constant.20 The cross section area of a diode o erating in the forward bias region is increa sed by a factor of 10. Su ose we wish to increase the current by a factor of 10.

112) (2. (2.110) (2.S = VT ln ID . VT ln 10: IS (2.111) (b) From the above exam le.113) .

on .on Figure 2. 2.33 Constant voltage diode model.cls v. VD falls in the range of 700 800 mV. We s ay the junction o erates as an o en circuit if VD VD. if we in ¡ ¡ ¡ ¡ ¡ . the vo ltage source laced in series with the switch in the off condition hel s sim lif y the analysis of circuits: we can say that in the transition from off to on.on . Note th at the current goes to in nity as VD tends to exceed VD. Exercise A diode in forward bias with ID IS ex VD =VT undergoes two simultaneous changes: the current is raised by a factor of m and the area is increased by a factor of n. we derive the circuit model shown in Fig.33(a) with the turn on voltage denoted by VD.33(b). Neglecting the leakage current in reverse bias. considering the device fully off if VD 800 mV. 2007 at 13:42 51 (1) Sec.on and as a constant voltag e source if we attem t to increase VD beyond VD. While not essential. Constant Voltage Model The ex onential I/V characteristic of the diode results i n nonlinear equations. First. Fortunately . With ty ical current levels and ar eas. Determine the change in the device voltage. Reverse Bias ID V D.on (a) VD (b) V D. A number of questions may cross the reader’s mind at this oint. The resulting characteristic is illustrated in Fig. we often a roximat e the forward bias voltage by a constant value of 800 mV (like an ideal battery) . the above exam les im ly that the diode voltage is a relatively weak function of the device current and cross section area. For this reason.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. on ly the switch turns on and the battery always resides in series with the switch. 2006] June 30.on Forward Bias V D.2 PN Junction 51 Thus. a tenfold increase in the device area lowers the voltage by 60 mV if ID re mains constant.on because we assume the f orward biased diode o erates as an ideal voltage source. why do we subject the diode to such a seemingly inaccurate a roximation? Second. making the analysis of circuits quite dif cult. 2. 2.

Calculate IX for VX = 3 V and VX = 1 V using (a) an ex onential model with IS = 10.on = 800 mV. Sim le models allow a q uick.deed intend to use this sim le a roximation. Exam le 2.16 A and (b) a constant voltage model with VD. we co nstruct a “ hysics based” circuit model. Consider the circuit of Fig.34. Device models havin g different levels of com lexity (and. and we seek to a roximate the resulting mo del. thus arriving at rogressively sim ler re resentations. 2. different levels of accuracy) rove essential to the analysis and design of circuits. intuitive understanding of the o eration of a com lex circuit.21 ¡ ¡ . while more accurate models reveal the true erformance. why did we study the hysics of se miconductors and n junctions in such detail? The develo ments in this cha ter a re re resentative of our treatment of all semiconductor devices: we carefully an alyze the structure and hysics of the device to understand its o eration. inevitably.

115) This equation must be solved by iteration: we guess a value for VD . Let us guess VD = 750 mV and hence . 2 Basic Physics of Semiconductors VX D1 R 1 = 1 kΩ VD Figure 2. 0:799 V 1k = 2:201 mA: 0 IX = 1 V . VD . 2006] June 30.119) (2.124) which yields VD gives . we have VX = IX R1 + VD VD = VT ln IIX : S (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Following the same rocedure for VX have = 1 V.117) (2. (a) Noting that ID Solution = IX . (2. 2007 at 13:42 52 (1) 52 IX Cha .120) IX = 3 V .34 Sim le circuit using a diode. com ute the corres onding IX from IX R1 = VX . we can obtain a more accurate value for IX : (2. 0:75 V = 1k = 2:25 mA: Thus. (2. we (2.123) (2. determine the new value of VD from VD = VT lnIX =IS and iterate.116) (2.118) VD = VT ln IX IS = 799 mV: With this new value of VD .cls v.121) (2.122) We note that the value of IX ra idly converges.114) (2. IX = VX R VD 1 3 V .k :75 V 1 = 0:25 mA.

125) (2.126) ¡ .= 0:742 V and hence IX = 0:258 mA. (b) A constant voltage model readily IX = 2:2 mA for VX = 3 V IX = 0:2 mA for VX = 1 V: (2.

enormous current is observed. eventually “breakdown” occurs and a sudden.” 2. ID V BD VD Breakdown Figure 2. Once freed. Exercise Re eat the above exam le if the cross section area of the diode is increased by a factor of 10. 2. 2.35 lots the device I/V characteristic. dis laying this effect. relatively cons tant current in reverse bias. This effect occurs at a eld strength of about 1 06 V/cm (1 V/m).3 Reverse Breakdown 53 The value of IX incurs some error. but it is obtained with much less com utation al effort than that in art (a).31 that the n junction carries only a small. 2006] June 30.1 Zener Breakdown The de letion region in a n junct ion contains atoms that have lost an electron or a hole and. (2. the electrons are accelerated by the eld and swe t to the n side of the junction. in which case the electric e ld in the air reaches such a high level as to ionize the oxygen molecules. ¡ ¡ . 2.cls v. Called the “Zener effect. a nar row de letion region is required.3. as the reverse voltage across the device increases. However. However. The breakdown resulting from a high voltage (and hence a high electric eld) can o ccur in any material.76) translates to high do in g levels on both sides of the junction (why?). 2007 at 13:42 53 (1) Sec. rovide no loosely connected carriers. 2. therefore. In order to create such high elds with reasonable voltages. thus lowering the resistance of the air and creating a tremendous current. which from Eq. a high electric eld in this region may im art enough energy to the remaining covalent electrons to tear them from their b onds [Fig. Figure 2.36(a)].” this ty e of breakdown a ears for reverse bias voltages on the order of 3 8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A common exam le is lightning.3 Reverse Breakdown Recall from Fig.35 Reverse breakdown characteristic. The breakd own henomenon in n junctions occurs by one of two ossible mechanisms: “Zener ef fect” and “avalanche effect. This section can be ski ed in a rst reading.

An interesting contrast between Zener and avalanche henom ena is that they dis lay o osite tem erature coef cients (TCs): VBD has a negativ e TC for Zener effect and ositive TC for avalanche effect. ra idly raising the num ber of free carriers. Zener diodes with 3. But. 2 Basic Physics of Semiconductors n Si E Si Si e Si Si Si e Si n e e e e e E e e e e Si e e Si Si VR (a) VR (b) Figure 2. 2. an avalanche effect takes lace.36 (a) Release of electrons due to high electric eld.” th is henomenon can lead to avalanche: each electron freed by the im act may itsel f s eed u so much in the eld as to collide with another atom with suf cient energy .5 V rating nd a li cation in some voltage regulators. 2007 at 13:42 54 (1) 54 Cha . The Zener and avalanche breakdown effects do not damage the diodes if the resulting current remains below a certain limit giv ¡ ¡ . For this reason.2 Avalanche Breakdown Junctions with moderate or low do ing levels ( 1015 cm 3 ) generally exhibit no Zener breakdown.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thus gaining enough ene rgy to break the electrons from their covalent bonds. Called “im act ionization. as the reverse bias voltage acros s such devices increases. The two TCs cancel e ach other for VBD 3:5 V. each carrier entering the de letion region ex eriences a very high electric eld and hence a large acceleration.cls v. these two electrons may again acquire energy and cause more ionizing collisions. (b) avalanche effe ct. Now.3. 2006] June 30. Even though the leaka ge current is very small. thereby freeing one more covalent bond electron.

For do ed or undo ed semiconductors . To increase the number of free ca rriers.en by the do ing levels and the geometry of the junction. semiconductors are “do ed” with certain im urities. i n ND and hence n2 =ND . It also contains a small number of free electrons at room tem erature. For exam le. Both the breakdown vol tage and the maximum allowable reverse current are s eci ed by diode manufacturers . For exam le.4 Cha ter Summary Silicon contains four atoms in its last orbital. ¡ . in an n ty e material. 2. n = n2 . When an electron is freed from a covalen t bond. i Ch arge carriers move in semiconductors via two mechanisms: drift and diffusion. The bandga energy is the minimum energy required t o dislodge an electron from its covalent bond. addition of hos horous to silicon increases the number of free electrons because hos horo us contains ve electrons in its last orbital. a “hole” is left behind.

shar gradients of carrier densities across the junction result in a high current of electrons and holes. 2006] June 30. U on formation of the n junction.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ty ically in the range of 700 to 800 mV. The n juncti on can be considered in three modes: equilibrium.kT cm.1 for Si. co nducting a very high current.127) Eg ni = 1:66 1015 T 3=2 ex . The electric eld in the de letion results in a buil t in otential across the region equal to kT=q lnNA ND =n2 . The elec tric eld created in the de letion region eventually sto s the current ow.3 . The intrinsic carrier concentration of germanium (GE) is ex ressed as where Eg = 0:66 eV. a constantvolta ge model may be used in some cases to estimate the circuit’s res onse with less ma thematical labor. they leave ionized atoms behind. (b) What do ing level is necessa ry to rovide a current density of 1 mA/m2 under these conditions? Assume the hol e current is negligible. As the carriers c ross. An n ty e iece of silicon ex eriences an electric eld equal to 0. A n junction is a iece of semiconductor that receives n ty e do ing in one section and ty e do ing in an adjacent section. Under forward bias. the junction carries negligible current and o erates as a ca acitor. 1 . calculate the total current owing through the devi ce at T = 300 K. The ca acitance itself is a function of the voltage a lied across the device. n junctions break down. 2 ¡ ¡ ¡ ¡ ¡ . (a) Calculate ni at 300 K and 600 K and com are the results with those obtained in Exam le 2. A n ty e iece of silicon with a length of 0:1 m and a cross section area of 0:05 m0:05 m sustains a voltage difference of 1 V.3 . and forward bias . (a) Calculate the ve locity of electrons and holes in this material. (b) Determine the electron and hole c oncentrations if Ge is do ed with P at a density of 5 1016 cm. “Zener” or “avalanche” breakdown may occur.cls v. 2. 2. De ending on the structure and do ing levels of th e device.3 .4 Cha ter Summary 55 The drift current density is ro ortional to the electric eld and the mobility of the carriers and is given by Jtot = q n n + E . (b) Re eat (a) for T = 400 K assuming for sim licity that mobil ity does not change with tem erature. (This is not a good assum tion. (a) If t he do ing level is 1017 cm. This con dition is called equilibrium. D d =dx.) (2. Problems 1. 3. reverse bias. Under a high reverse bias voltage.1 V/m. Since th e ex onential model often makes the analysis of circuits dif cult. The diffusion current density is ro ortional to the gradient of the carrier concentration and given by Jtot = q Dn dn=dx . the junction carries a current t hat is an ex onential function of the a lie voltage: IS ex VF =VT . and a “de letion resgion” is formed. i Under reverse bias. 2007 at 13:42 55 (1) Sec.

Assume n = 3900 cm2 =V s an d = 1900 cm2 =V s. they fall to negligible values at x = 2 m and x = 0. 5.9.. 2007 at 13:42 56 (1) 56 Cha . Re eat Problem 7 if the electron and hole ro les are “shar ” ex onentials. i. Determine the total current owing through the device if the cross section area is equal to 1 m 1 m.38). 2006] June 30. re eat Problem 3 for Ge. Figure 2.37 shows a ty e bar of silicon that is subjected to electron injection from the left 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2.38 0 2 ¡ . Assume th e cross section area of the bar is equal to a. 8.10 but for x = 0 to x = 1. From the data in Problem 1. res ectively (Fig. Com are the results for linear and ex onential ro les . com ute t he total number of electrons “stored” in the material from x = 0 to x = L. Re eat Problem 6 for Exam le 2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7. 2.cls v. 2 Basic Physics of Semiconductors 4.e.37 0 2 m x and hole injection from the right. 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2. In Exam le 2. 6.

what voltage yields a current of 1 mA? 15. Consider a n junction in forward bias.6 V.3 and NA = 2 1015 cm.3 . Figure 2. 300 K. (a) Determine the majorit y and minority carrier concentrations on both sides. A ju nction em loys ND = 5 1017 cm. ¡ ¡ ¡ . How do you ex lain the henomenon of drift to a high school student? 10. (a ) Determine the junction ca acitance er unit area. 12.3 and NA = 4 1016 cm. (a) To obtain a current of 1 mA with a voltage of 750 mV. and 350 K. 14.39. how should IS be chosen? (b) If the diode cross section area is now doubled. calculate the built in otential at T = 300 K. An oscillator a lication requires a variable ca acitance with the characteristic shown in Fig. Dete rmine the required ND if NA = 1017 /cm2 . (b) By what factor should NA be increased to double the junction ca acitance? 13. 11. (b) Calculate the built in otential at T = 250 K.40 shows two diodes with reverse saturation cur rents of IS 1 and IS 2 laced in arallel.3 ex eriences a reverse bias voltage of 1. 2. If ND = 3 1016 cm . A n junction with ND = 3 1016 cm. the side of a n junction has not been do ed. (a) Prove that the arallel combinati on o erates as an ex onential device.3 .m x 9. Ex lain the trend. Due to a manufa cturing error.

VX = 0:5 V.8 V. where IS = 2 10. and IS 2 . and 1. IS 1 . 0. 16. 1 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 18. Note that VD1 changes little for VX 0:8 V.41 shows two diodes with reverse saturation c urrents of IS 1 and IS 2 laced in series. In the circu it of Problem 17. What is the required change in VB ? 19. and VD2 in terms of VB . the cross section area of D1 is increased by a facto ¡ . determine the current carried by each diode. (b) For a tenfold change in the current. 2. we wish to increase IB by a factor of 10. 2. 2006] June 30. how much voltage change does s uch a device require? 17. Calculate VD1 and IX for IX R1 2 kΩ VX D1 Figure 2.4 Cha ter Summary C j (fF/ m 2 ) 57 2. (a) Prove that this combina tion can be viewed as a single two terminal device having an ex onential charact eristic.42 20.5 −0.5 0 V R (V) Figure 2.40 (b) If the total current is Itot . VD1 . Figure 2. 2007 at 13:42 57 (1) Sec.3 −1.cls v.2 V.41 Calculate IB .15 A.42. I n the circuit of Fig. Consider the circuit shown in Fig.42. 2.2 1. Two identical n junctions are laced in series. D1 IB V D1 D1 V D2 VB Figure 2.39 I tot VB D1 D2 Figure 2.

Determine VD1 and IX for VX = 0:8 V and 1.2 V.r of 10. Com are the results with those obtained in Problem 19. .

Determine the required IS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 58 (1) 58 Cha . and 4 mA. 28. Figure 2. 23. Calcu late the required IS .45 ments indicate that IX = 1 mA ! VX = 1:2 V and IX = 2 mA ! VX = 1:8 V. For what value of VX in Fig.cls v. We note IX R1 D1 VX Figure 2. D1 D2 IX ¡ ¡ .16 A. The circuit illustrated in Fig. 2. 2 mA. 22. 2. Calculate R1 and IS . 27.16 A.16 A. 1 kΩ IX R1 D1 Figure 2. calculate VD1 for IX = 1 mA. Calculate R1 and IS .16 A.46 em loys two identical diod es with IS = 5 10. 2.45 and wish to determine R1 and IS .44. 2006] June 30. In the circuit of Fig. Measure IX VX R1 D1 Figure 2. 2. 2.44 de icts a arallel resistor diode combination. 2 Basic Physics of Semiconductors 21. If IS = 3 10. doe s R1 carry a current equal to IX =2? Assume IS = 3 10.42. 24 .44 25. For what value of IX in Fig. 2. Su ose D1 in Fig. does R1 sustain a voltage equal to VX =2? Assume IS = 2 10.42 must sustain a voltage of 850 mV for VX = 2 V.44.43 and wish to determine R1 and IS .5 mA for IX = 1:3 mA. We have received the circuit shown in Fig. 26. We have received the circuit shown in Fig.43 that VX = 1 V ! IX = 0:2 mA and VX = 2 V ! IX = 0:5 mA. we wish D1 to carry a current of 0. 2.

determine the value of R1 such that this resistor carries 0. 2. .5 mA.47.46 Calculate the voltage across R1 for IX = 2 mA. In the circuit of Fig.R1 2 kΩ Figure 2. 29.

For the cir cuit shown in Fig. At what value of I in D1 . 2. (b) an ex onenti al model.16 A for each diode. 2007 at 13:42 59 (1) Sec.48 SPICE Problems In the following roblems. Re eat Problem 31 for the circuit de icted in Fig.cls v.48.47 Assume IS = 5 10. IX VX R1 D1 Figure 2. Assume (a) a constantvoltage model. 2006] June 30. lot Vout as a function of Iin . Sketch VX as a function of IX for the circuit shown in Fig. 31. assume IS = 5 10. 30.4 Cha ter Summary 59 D1 IX 1 mA R 1 D2 Figure 2. I in D1 Vout Figure 2.49 32.50. 2. Assume Iin varies from 0 to 2mA. 2.16 A.49. where R1 Iin are th e currents owing through D1 and R1 equal? =1k . 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

2 V to +2 V. 2. In the circuit of Fig. determine the value of R1 in Fig.50 33. 34. At what value of Vin are the voltag e dro s across R1 and D1 equal? R1 Vout V in D1 Figure 2. Using SPICE. R1 = 500 .50 such that D1 carries 1 m A if Iin = 2 mA.R1 Vout Figure 2. Plot Vout as a func tion of Vin if Vin varies from .51 . 2.51.

B.51. 2 Basic Physics of Semiconductors 35. Solid State Electronic Device. tice Hall. Banerjee.cls v. In the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. use SPICE to select the value of Vin 2 V. 1999. R1 such that Vout 0:7 V for References 1. fth edition. Pren ¡ ¡ . 2007 at 13:42 60 (1) 60 Cha . 2. Streetman and S. We sa y the circuit “limits” the out ut. 2006] June 30.

110 2. we now rise to the next level of abstraction and deal with diodes as circuit elements. The wa veform conversion in Fig.1 Initial Thoughts In order to a reciate the need for diodes. 3.1(a) erform this conversion? As de icted in Fig. im lies that if the voltage across a resistor goes from ositiv e to negative. The charger converts the line ac voltage at 110 V1 and 60 Hz2 to a dc voltage of 3. The eak value is the refore equal to 2 The line ac voltage in most countries is at 220 V and 50 Hz. this is accom lished by rst ste ing down the ac voltage by means of a transformer to ab out 4 V and subsequently converting the ac voltage to a dc quantity. That is.1 Ideal Diode 3. 61 ¡ ¡ ¡ ¡ .5. let us brie y s tudy the design of a cell hone charger. 3. How does the b lack box in Fig. 3.1(a). Ohm’s law.1). The result dis lays a ositive average and so me ac com onents. the out ut of the transformer exhibits a zero dc content because the negative and ositive half cycles enclose equal areas. Now su ose this waveform is a lied to a mysterious device that asses the ositive half cy cles but blocks the negative ones. which can be removed by a low ass lter (Section 3. so does the current through it. assing only one and blocking the ot her. As shown in Fig. 2006] June 30.cls v. 2007 at 13:42 61 (1) 3 Diode Models and Circuits Having studied the hysics of diodes in Cha ter 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ultimately arriving at interesting and real life a lications.5 V. We roceed as f ollows: Diodes as Circuit Elements Ideal Diode Circuit Characteristics Actual Diode A lications Regulators Rectifiers Limiting and Clam ing Circuits 3.3 The same rinci le a lies to ada tors that ower other electronic devices.1(b). A sim le resistor cannot serve in this role because it is linear. We must 1 This value refers to the root mean square (rms) voltage. 3 The actual o eration of ada tors is somewhat different. 3. This cha ter also re ares us for under standing transistors as circuit elements in subsequent cha ters.1(b) oints to the need for a device that discrimina tes between ositive and negative voltages.1. V = IR. leading to a zero average.

x.2 Conce tual o eration of a diode. 3. The mysterious device generates an out ut equal to the in ut for ositive half cycles and equal to zero for negative half cycles. 3. Forward and Reverse Bias To serve as the mysterious device in the charger exam le of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. if x ! .2 Ideal Diode The mysterious device mentioned above is called an “ideal diode. with the triangular he ad denoting the allowable direction of current ow and the vertical bar re resenti ng the blocking behavior for currents in the o osite direction.” Shown in Fig. The corres ondi ng terminals are called the “anode” and the “cathode. Figure 3.” res ectively.cls v. (b) elimination of negative half cycles.2 summarizes the result of our thought roc ess thus far. t ¡ . 3.3(a). the diode is a two terminal device. y 6! .y .1 (a) Charger circuit. 2007 at 13:42 62 (1) 62 V1 4 2 Cha .3(a). 3 60 Hz Diode Models and Circuits t V line 110 2 60 Hz 3. therefore seek a device that behaves as a short for ositive voltages and as an o en for negative voltages. y (t ) t x (t ) t Figure 3. Note that the de vice is nonlinear because it does not satisfy y = x.1.5 V V1 t Block Box Vout t (a) V1 4 2 ? t Equal Positive and Negative Areas (b) Positive Areas t Figure 3.

he diode must turn “on” if Vanode Vcathode and “off” if Vanode Vcathode [Fig. .

allowing a current.3(b)]. D1 A B (a) D2 C A D1 B (b) D2 C A D1 B (c) D2 C ¡ ¡ ¡ . Vcathode = VD .cls v. we say the diode is “forward biased” if VD t ends to exceed zero and “reverse biased” if VD 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4 A water i e analogy roves usefu l here. 3.3(c). 2007 at 13:42 63 (1) Sec. 3.1 Ideal Diode 63 D1 Anode Cathode Forward Bias Reverse Bias IX (a) Hinge Forward Bias (b) Reverse Bias Pi e Valve Sto er (c) Figure 3. On the other hand. Consider the i e shown in Fig. if water re ssure is a lied from the right. the valve rises.1 As with other two terminal devices. diodes can be laced in series (or in arall el).4 can conduct current. Exam le 3. (b) equivalent circuit. where a valve (a late) is hinge d on the to and faces a sto er on the bottom. the sto er kee s the valve shut. 2006] June 30. If water ressure is a lied fro m the left. 3. (c) water i e analogy. De ning Vanode . 3.3 (a) Diode symbol. Determine which one of the con gurations in Fig.

3. 4 In our drawings.4(b) . from B to C . 3. and D2 . the anodes of D1 and D2 oint to the same direction. In Fig.4(c) behaves as a n o en for any voltage. The diodes in Fig.Figure 3. 3. the to ology of Fig. but they hel us become comfortable with diodes.4(a).4 Series combinations of diodes. allowing th e ow of current from A to B to C but not in the reverse direction. In Fig. 3. we sometimes lace more ositive nodes higher to rovide a vi sual icture of the circuit’s o eration. . Of course. D1 sto s current ow from B to A.3(b) are drawn accor ding to this convention. no current can ow in either direction. Thus. none of these circuits a ears articularly u seful at this oint. By the same token. Solution Exercise Determine all ossible series combinations of three diodes and study their condu ction ro erties.

5 I/V characteristics of (a) zero and in nite resistors. Vcath cathode. 2006] June 30.2 We said that an ideal diode turns on for ositive anode cathode voltages.5(a). the current that ows through the d evice as a function of the voltage across it. in circui ts containing only nite currents. Here..1) (3. 3. A common ty e of lot is that of t he current/voltage (I/V) characteristic.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus. 3.e. then the diode turns on and conducts in nite current if the circuit surrounding the diode can rovide such a current. and ID is de ned as the current owing into the anode and out of the ID I R=0 V I R= Reverse Bias Forward Bias ¡ ¡ ¡ ¡ the second. For an ideal diode.6(a). a forward biased ideal diode sustains a zero vo ltage—similar to a short circuit. But th e characteristic in Fig.cls v.5(b) does not a ear to show any ID values for VD 0. 3. we combine ositive voltage region of the rst with the negative voltage region of the arriving at the ID =VD characteristic in Fig. i.2) V VD (a) Figure 3. Since an ideal diode behaves as a short or an o en. 2007 at 13:42 64 (1) 64 Cha . (b) Exam le 3. (b) ideal di ode. we rst construct the I/V characteristics for two s ecial cases of Ohm’s law: R=0 I = V =1 R V = 0: R=1 I = R (3. VD = Vanode . ode .5(b). Solution Exam le 3. . 3. How do we inter ret this lot? This characteristic indicates that as VD exceeds zero by a very small amount. If V ¡ Exercise How is the characteristic modi ed if we de? lace a 1 resistor in series with the dio The results are illustrated in Fig. 3 Diode Models and Circuits I/V Characteristics In studying electronic devices.3 Plot the I/V characteristic for the “anti arallel” diodes shown in Fig. it is often hel ful to accom any equations with gra hical visualizations.

Seemingly a useless circuit.A 0. again leading to IA = 1. 3. D1 is on and D2 is off. but D2 is on. The result is illustrated in Fig. The anti aral lel combination therefore acts as a short for all voltages. D1 is off. yielding IA = 1.6(b). Solution .5. If VA 0.3). this to ology becomes much more interesting with actual diodes (Section 3.

2006] June 30. (d) I/V characteristic.7 (a) Diode resistor series combination. ¡ ¡ arallel ¡ . (b) Exam le 3. 2007 at 13:42 65 (1) Sec. (c) equivalent circuit under reverse bias.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. (b) equivalent circuit under f orward bias. (e) equivalent circuit if 1 is on.cls v.6 (a) Anti arallel diodes. D Exercise Re eat the above exam le if a 1 V battery is laced is series with the combination of the diodes. 3. (b) resulting I/V characteristic.1 Ideal Diode 65 IA VA D1 D2 IA VA (a) Figure 3. IA IA D1 R1 (b) VA D1 R1 (a) IA R1 D1 R1 R1 (c) IA 1 R1 IA D1 R1 (e) VA VA (d) Figure 3.7(a).4 Plot the I/V characteristic for the diode resistor combination of Fig.

for VA 0. The a bove observations are based on guesswork. Figure 3. 3.7(c)] and ID = 0. the circuit is reduced to that in Fig.e. the actual current ows from right to left. We begin with VA 0. let us assume D1 is on and see if we reach a con icting result. As VA rises above zero. Su ose for some Solution ¡ .7(d) lots the resulting I/V characteristic. To con rm the validity of this guess. ostulating that the diode is off. it t ends to forward bias the diode.. But this im lies that D1 carries a current from its cathode to its anode.7(e). Let us study the circuit more rigorous ly. and if VA is negative. violating the de nition of th e diode. D1 remains off and IA = 0. Thus.7(b)] and IA = VA =R1 because VD1 = 0 for an ideal diode. On the other hand. If D1 is on. 3. so is IA .We surmise that. i. the diode is on [Fig. if VA 0. 3. D1 is robably off [Fig. Does D1 turn on for any VA 0 or does R1 shift th e turn on oint? We again invoke roof by contradiction. if VA 0.

then we surmise that D1 is forward biased and D2 . The above exam le leads to two im ortant oints. D1 VA VB D2 RL Vout Exam le 3. In other words. Exam le 3.cls v. The volt age dro across R1 is therefore equal to zero. and VB = 0.8 OR gate realized by diodes. In the circuit of Fig. Solution ¡ ¡ ¡ . 3. 3 Diode Models and Circuits VA 0.” This is because in ty ical circuits. we often refer to consider the voltage to be the “ca use” and the current. voltage olar ities can be redicted more readily and intuitively than current olarities. devices such as transistors fundamentally roduce current in res onse to volt age. immediately facing a con ict: D1 enforces a voltage of +3 V at the out ut whereas D2 shorts Vout to VB = 0. 2007 at 13:42 66 (1) 66 Cha . Of course. If VA = +3 V.8. This assum tion is therefore incor rect. If uncertain. Vout = VA = +3 V. if the assum tions are incorrect. Thus. 2006] June 30. the series combination o f D1 and R1 acts as an o en for negative voltages and as a resistor of value R1 for ositive voltages. Exercise Re eat the above analysis if the terminals of the diode are swa ed.5 Why are we interested in I/V characteristics rather than V/I characteristics? Solution In the analysis of circuits. Als o. suggesting that VD1 = VA and henc e ID1 = 1 and contradicting the original assum tion. we can assume both D1 and D2 are forward biased.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Plot the V/I characteristic of an ideal diode. rev erse biased. each in ut can assume a value of either zero or +3 V . the nal result contradicts t he original assum tions. D1 turns on for any VA 0. we can assume an arb itrary state (on or off) for each diode and roceed with the com utation of volt ages and currents. Second. it is hel ful to rst examine the circuit care fully and make an intuitive guess.6 Figure 3. First. behaving as an o en circuit and yielding IA = 0. in the analysis of circuits. D1 is still off. the “effect. Determine the res onse observed at the out ut.

.

1. 3. Is an ideal diode on or off if VD Exam le 3.9(d) illustrates the over all in ut/out ut characteristic.” It is instruct ive to lot the in ut/out ut characteristic of the circuit as well. Thus.5 The circuit of Fig.9(a). D1 is off and Vout = 0. and if Vin 0. D1 is forwa rd biased. we consider sligh tly ositive or negative voltages to determine the res onse of a diode circuit.10(b) and analyze its res onse to a sinusoidal in ut [Fig. we have Vout = Vin .cls v. After all. If Vin 0.9(c)]. Figure 3. where the out ut is de ned as the voltage across D1 . Since R1 h as a tendency to maintain the cathode of D1 near zero.3 A lication Exam les Recall from Fig. How ever. This state holds for the ositive h alf cycle.1 Ideal Diode 67 The symmetry of the circuit with res ect to VA and VB suggests that Vout = VB = +3 V if VA = 0 and VB = +3 V. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Since no current ows t hrough R1 . 3. When Vin falls below zero. 3. 3. Exercise Construct a three in ut OR gate. 2006] June 30.7 Solution = 0? An ideal diode ex eriencing a zero voltage must carry a zero current (why?). An exam le. We therefore modify the circuit as de icted in Fig. shorting the out ut to the in ut. consider the circuit de icted in Fig . 3. a iece of wire ex eriencing a zero voltage behaves similarly. 3. In ractice. 2007 at 13:42 67 (1) Sec.10(c)]. Unfortunately. D1 is on and Vout = Vin . shorting t he out ut and forcing Vout = 0 [Fig. 3. and the state of the diode is ambiguous. The circuit o erates as a logical OR gate and was in fact used in early digital com uters. as Vin rises. the state of an ideal diode with VD = 0 is somewhat arbitrary and ambiguous. 3.10(b) is called a “recti er. this does not mean it acts as an o en circuit. D1 turns off and R1 ensures that Vout = 0 because ID R1 = 0. We may naturally con struct the circuit as shown in Fig. D1 is re verse biased. 3 . It is therefore instructive to construct the in ut/out ut characteristics of a circuit by varying the in ut across an allowable range and lotting the resulting out ut. Let us now design a circuit that erforms this function.9(b). If Vin 0. we obt ain the ¡ Exercise Re eat the above exam le if a 1 resistor is laced in series with the diode. reducing the circuit to that in Fig. however. then D1 is forward biased.10(a).” the out ut current is always equal to zero. ¡ . the cathode of the diode is “ oating. Noting that if Vin 0. In ut/Out ut Characteristics Electronic circuits rocess an in ut and generate a corres onding out ut.2 that we arrived at the conce t of the ideal diode as a means of converting xt to y t.

the out ut voltage is not de ned because a oating node can assume any l. otentia .5 Note that without R1 .

Then.8 Is it a coincidence that the characteristics in Figs. behavior shown in Fig. ! . (c) equivalent circuit for ositive in ut. 3.7(d) and 3. where ! = 2=T denotes the frequency in radians er second and T the eriod. The recti er is a nonlinear circuit because if Vin Vout 6! .10(d) look si milar? No.7(a).10(b) is sim ly equal to IA R1 in Fig.Vin then Exam le 3. 2007 at 13:42 68 (1) 68 V in < 0 R1 V in D1 Vout V in R1 Cha .Vout . 3. 3. the two lots differ by only a scaling factor equ al to R1 . 3. We now determine the time average (dc value) of the out ut waveform in Fig.cls v.10 (c) to arrive at another interesting a lication. 2006] June 30. Solution Exercise Construct the characteristic if the terminals of D1 are swa ed. in t he rst cycle after t = 0. Thus. we recognize that the out ut voltage in Fig. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10(d). we have ¡ .9 (a) Resistor diode circuit. Su ose Vin = V sin !t. (b) equivalent circuit for negative in ut . (d) in ut/out ut characteristic. 3 Diode Models and Circuits V in > 0 R1 Vout V in Vout (a) (b) (c) Vout V in 1 (d) Figure 3.

Vout = V sin !t for 0 t T 2 T tT = 0 for 2 1 Z T V tdt Vout.3) (3. we obtain the area under Vout and normalize the result t o the eriod: (3.5) (3.6) 1 Z T=2 V sin !tdt =T .avg = T out 0 0 (3.4) To com ute the average.

since cell hones receive varying levels of sig nal de ending on the user’s location and environment. an ex ected result because a larger in ut am litude yields a greater area under the recti ed half cycles. the average is ro ortional to V . they require an indicator to 1 = T V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) com lete recti er. (c) in ut an d out ut waveforms. 2006] June 30.10 (a) A diode o erating as a recti er. (3.1 Ideal Diode D1 V in Vout V in D1 R1 Vout 69 (a) (b) V in t Vout 1 V in R1 V in R1 Rectified Half Cycles V in Vout 0 T 2 T (c) 3T 2 2T t (d) Figure 3. a recti er can o erate as a “signa l strength indicator. cos !t T=2 0 ! = V : .7) (3.cls v. 2007 at 13:42 69 (1) Sec. (d) in ut/out ut characteristic. The above obse rvation reveals that the average value of a recti ed out ut can serve as a measure of the “strength” (am litude) of the in ut.” For exam le. 3. That is.8) Thus.

If the signal is a lied to a recti er.9 Solution The recti ed out ut exhibits an average value ranging from 2 mV/ V= = 0:637 V to 10 = 3:18 mV.determine how much the signal must be am li ed. what is the corres onding range of the out ut average? Exam le 3.8 GHz si gnal with a eak am litude ranging from 2 V to 10 mV. ¡ Exercise Do the above results change if a 1 resistor is laced in series with the diode? ¡ . A cell hone receives a 1.

the cathode voltage is higher than the anode voltage. 3. F irst. Thus. Shown in Fig. where a 1 V battery is laced in se ries with an ideal diode. the anode is not ositive eno ugh to forward bias D1 .3) lead to some im ortant a lications.11 (a) Diode battery circuit.11(a).9 V. (b) resistor diode circuit. the I/V characteristic of the diode battery combination resembles that of a diode. How does this circuit 0. e. lacing D1 in reverse behave? If V1 bias. I1 I1 V1 D1 VB 1V +1 V (a) V1 Vout R1 V in D1 Vout V in t Vout 1 V in t (b) R1 D1 VB 1V V in V in Vout Vout Vout +1 V +1 V 1 V in Figure 3. 3 Diode Models and Circuits In our effort toward understanding the role of diodes.5. 3.cls v. we examine another circui t that will eventually (in Section 3.. V1 must a roach +1 V for D1 to turn on. (c) addition ¡ ¡ t − V (c) t − V +1V + V ¡ ¡ . equal to 0. Even if V1 is slightly greater than zero. consider the to ology in Fig. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11(a).g. but shifted to the right by 1 V. 2007 at 13:42 70 (1) 70 Cha .

and Vout = 0. as illustrated in the out ut waveform and the in ut/out u t characteristic. 3. im lying that a 1 V battery must be inserted in series with the diode. D1 acts a short. 3. But su ose we seek a circuit that must not allow the out ut t o exceed +1 V (rather than zero). the modi cation indeed guarantees Vout +1 V for any in ut level. D1 must turn on only when Vout a roaches +1 V. “Limiters” rove useful in many a lications and are descri bed in Section 3. The circuit th erefore does not allow the Exam le 3. 3. D1 remains off . 3.of series battery to (b). How should the circuit of Fig.11(b). let us examine the circuit in Fig. We say the circ uit “cli s” or “limits” at +1 V. out ut to exceed zero.5. De icted in Fig.11(c) . for Vin 0. Now. For Vin 0.11(b) be modi e d? In this case. Here.11(c) for a sinu soidal in ut as the battery voltage.3.10 ¡ . yielding Vout = Vin . Sketch the time average of Vout in Fig. VB .

11 Is the circuit of Fig. In this case.1 to +1.V VB 0. 3. no limiting occurs and the a verage is equal to zero.1 Ideal Diode 71 varies from . VB < − V V in t VB − V − V < VB Solution V in VB Vout − V t Vout = VB VB = 0 + V < VB + V VB V in VB Vout − V (a) t Vout t Vout − V + V − V − V 1 (b) π VB Figure 3. yielding an average greater than . Figure 3. For VB = 0.12(b) sketches this behavior. 3. the average reaches . D 1 turns off at some oint in the negative half cycle and remains off in the osi tive half cycle. D1 is always on because Vin . the out ut average is equal to VB [Fig.11(b) a recti er? Solution .12(a)]. Exam le 3. 3.cls v. for VB V .12 . 2007 at 13:42 71 (1) Sec.V = .V but less than VB .V . If VB is very negative. Exercise Re eat the above exam le if the terminals of the diode are swa ed. Finally.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. For .

roducing a . Exercise How should the circuit of Fig. The circuit negative average.11(b) be modi ed to the out ut. indeed. asses only negative cycles to the out ut. ass only ositive cycles to Yes. 3.

cls v. we may discover that th is idealization is inadequate and hence em loy the constant voltage model. (a) We begin with Vin = . F igures 3. 3. for Vin 0.13(a) and (b) lot the I/V characteristics of the ideal diode and the n junction. This model suf ces in most cases. (b) ex onential model. Thus. In fact. o erating as a short and reducing the circuit to a voltage Solution ¡ ¡ ¡ ¡ . (c) c onstant voltage model.2 PN Junction as a Diode The o eration of the ideal diode is somewhat reminiscent of the current conducti on in n junctions.1. 3. The following exam les illustrate these oints.13 is the constant vo ltage model develo ed in Cha ter 2. roviding a sim le a roximation of the ex o nential function and also resembling the characteristic lotted in Fig. the diode remains off and no current ows through the circuit. res ectively. Given a circuit to ology. the voltage dro across R1 is zero and Vout = Vin .12 Plot the in ut/out ut characteristic of the circuit shown in Fig.on V D. In fact. 3 Diode Models and Circuits 3. 2006] June 30. ID Ij VD (a) (b) Vj ID V D.14(a) using (a) the ideal model and (b) the constant voltage model. how do we choose one of the above models for the diode s? We may utilize the ideal model so as to develo a quick.3(b) are quite similar to those studied for n junctions in Cha ter 2. 3. D1 turns on. Exam le 3. Shown in Fig. recognizing that D1 is reverse biased.on (c) Figure 3. the forward and reverse bias conditions de icted in Fig.13 Diode characteristics: (a) ideal model. but we may need to resort to the ex onential model fo r some circuits.11(a). 2007 at 13:42 72 (1) 72 Cha .on VD V D.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. U on erforming this exercise. 3. rough understanding of the circuit’s o eration. The latter can serve as an a roximation of the former by roviding “unilateral” current conduction. As Vin exceeds zero.

on [as illustrated in Fig. the circuit o erates as a voltage divider once the diode turns on and loads the out ut node with R2 .on V in Figure 3. That is.on : R1 R2 It follows that (3.9) Vin . dis laying the same sha e as that in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13(c)]. yielding Vout = Vin . 14(c). we a ly Kirchoff’s current law to the out ut node: Vout = R R2 R Vin for Vin 0: 1+ 2 (3.2 PN Junction as a Diode 73 V in R1 Vout R2 D1 Vout R2 R2 + R1 V in 1 (a) (b) V in R1 Vout R2 V D. In other words.on Vout R2 R2 + R1 V D. Figure 3. 2007 at 13:42 73 (1) Sec. (c) in ut/out ut characteristic with constant voltage diode model .on . D1 is reverse biased for Vin VD.cls v. D1 turns on.14(d) lots the resulting characteristic. Vout = Vout . revealing a slo e equal to unit y for Vin 0 and R2 =R2 + R1 for Vin 0. 3.14(b) lots the overall characteristic. Figure 3.on 1 (c) (d) V D. (b) In this case.11) : 1 + R2 R1 As ex ected. 3. 3. (b) in ut/out ut characteristic with ideal diode model. 2006] June 30.14(b) but with a shift in the break oint.10) R2 V + V in D. 3. ¡ . Vout = VD. Reducing the circuit to that in Fig.on . o erating as a constant voltage source with a value VD. As Vin exceeds VD.on if Vin = VD.14 (a) Diode circuit.on Vout = R1 (3. VD. divider.on .

lot the current through R1 as a function of Vin .Exercise In the above exam le. .

15 Diode circuit. I in R 1 V1 D1 D2 Figure 3.3 Additional Exam les Exam le 3.14) together yields (3. D1 and D2 have different cross section areas but ar e otherwise identical. we must resort to the ex onential equation because the ideal and c onstant voltage models do not include the device area.cls v.12) and (3.15) (3. 3 Diode Models and Circuits 3. 3. (3.16) This section can be ski ed in a rst reading ¡ .13 In the circuit of Fig. IS 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12) VT ln ID1 = VT ln ID2 . ID1 = Exercise For the circuit of Fig.14) Iin I 1 + IS 2 S1 Iin : ID2 = I 1 + IS 1 S2 As ex ected. calculate VD is terms of Iin . Solution In this case. and IS 2 . ID1 = ID2 = Iin =2 if I S 1 = IS 2 . (3. Determine the current owing through each diode.15. I I S1 S2 that is.13) ID1 = ID2 : IS1 IS2 Solving (3. 3. 2007 at 13:42 74 (1) 74 Cha . 2006] June 30. We have Iin = ID1 + ID2 : We also equate the voltages across D1 and D2 : (3.15.

3. R1 Vout R2 D1 R1 Vout R2 V in V in (a) (b) Vout V D.on .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on R1 ) V D.16 (a) Diode circuit.cls v.14 Using the constant voltage model lot the in ut/out ut characteristics of the ci rcuit de icted in Fig. Solution In this case.16(a). 2006] June 30.16(b). R1 + R2 in D. requiring an in ut voltage given by: (3. vout = R R2 R Vin : 1+ 2 R2 V = V . (b) equivalent circuit when D1 is off.on and hence (3. 3.1. D1 is reverse biased and the circuit reduces to that in Fig.on R2 V in R2 R2 + R1 (1 + (c) Figure 3. 2007 at 13:42 75 (1) Sec.17) At what oint does D1 turn on? The diode voltage must reach VD. (c) in ut/out ut characteristic. Note that a diode about to turn on carries zero current but sustains VD.on .3 Additional Exam les 75 Exam le 3. the voltage across the diode ha ens to be equal to the out ut vol tage. We note that if Vin = .18) R1 : Vin = 1 + R D.on 2 V ¡ . Consequently. 3.

. it draws current and the diode voltage is no longer equal to R2 =R1 + R2 Vin . ¡ . (3. e.g.(3. The diode therefore still dra ws no current.18)? To determine the br eak oint. So why did we ex ress the diode voltage as such in Eq.19) The reader may question the validity of this result: if the diode is indeed on. it creates Vout 799 mV. but the voltage across it and hence the in ut voltage are almost suf cient to turn it on. we assume Vin gradually increases so that it laces the diode at the edge of the turn on.

in R2 X R1 Vout V D.15 the in ut/out ut characteristic for the circuit shown in Fig. we hav e Solution Vout = Vin + VD.on . Figure Exercise Re eat the above exam le but assume the terminals of D1 are swa ed..cls v. 3.20) Exam Plot me a D1 V le 3. so long as D1 is on. and redraw the circuit as de icted in Fig. VX is i nde endent of R2 because D1 acts as a battery. Note that in this regime.17 (a) Diode circuit.on : (3.16(c) lots the overall characteristic. D1 is We begin with Vin = .on . the a node is tied to ground and the cathode the out ut node. D1 remains forward biased.on . 2007 at 13:42 76 (1) 76 Cha . lac ing the more negative voltages on the bottom and the more ositive voltages on t he to .e. (b) illustration for very negative in uts.on X D1 R2 R1 Vout ¡ . (d) in ut/out ut characteristic. (c) eq uivalent circuit when off. This diagram suggests that the diode o erates in forward bias. i.1.on R2 R1 R1 + R2 V in 1 (c) (d) Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.17(b). = VD.17(a). Exercise For the above exam le. V in = − (a) (b) Vout V in R2 Vout R1 R ( 1 + 1 ) V D. establish ing a voltage at node X equal to Vin + VD. 3. lot the current through R1 as a function of Vin . Thus. 2006] June 30. Assu constantvoltage model for the diode. yielding Vout 3. 3 Diode Models and Circuits For Vin 1 + R1 =R2 VD.

23) 1 Thus..1 + R1 VD.21) and (3. roceed with the analysis. 3. in more com lex circuits. 2007 at 13:42 77 (1) Sec. Vin + VD.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on : 2 As Vin exceeds this value.e. As mentioned in Exam le 3.3 Additional Exam les 77 We also com ute the current owing through R2 and R1 : IR2 = VD. it may be dif cult to corre ctly redict the region of o eration of each diode by ins ection.4.17(c) and (3. The reader may nd it interes ting to recognize that the circuits of Figs.18(a) using .Vin R VD. VX (3.21) R2 IR1 = 0 . Exercise Re eat the above exam le if the terminals of the diode are swa ed. In such cases. at some oint IR2 = IR1 .26) The overall characteristic is shown in Fig. 3.23) .22) R1 + = . D1 turns off if Vin is chosen to yield IR2 = IR1 .24) R Vin = . as Vin increases from . IR2 remains constant but jIR1 j decreases. From (3.on R2 R1 and hence (3.on : (3. we still a ly intuition to minimize the guesswork. VD.16(a) and 3.17(a) are identical: in the former. the out ut is sensed across the diode whereas in the latter it is sensed across the series resistor. The observation that at some oint.on = . 3. In other words. i.on (3. we may sim ly make a guess.16 Plot the in ut/out ut characteristic of the circuit shown in Fig. in this case i t is sim ler to seek the condition that results in a zero current through the diode rather than insuf cient voltage a cross it. At what oint does D1 turn off? Interestingly.17(d). Exam le 3. Of course. 3.1. 2006] June 30. IR2 = IR1 roves useful here as th is condition also im lies that D1 carries no current (KCL at node X ).25) Vout = R R1 R Vin : 1+ 2 (3. The following exam le illustrates thi s a roach. the circuit reduces to that shown in Fig. 3.cls v. and eventually determine if the nal result agrees or con icts with the original guess.

the constant voltage diode model. We begin with Vin Solution = .1. We also (blindly) assume that D2 ¡ . redicting intuitively that D1 is on.

3 Diode Models and Circuits I R2 = D1 V in D2 Y V B= 2 V R1 X R1 Vout V D.on V D.on R2 Vout R1 X Y VB I R1 R1 X V in = − (a) (b) V in = − (c) D1 V in D2 X R1 Vout V in = − V D. 2007 at 13:42 78 (1) 78 Cha .on R2 Vout VB Y I1= V D.cls v. 2006] June 30.on D1 X R1 Vout Y VB R1 D2 Y V B= 2 V (e) R1 (d) Vout D1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

V in V in (f) (g) (h) Figure 3.29) . 2VD. thus reducing the circuit to that in Fig.on : R 1 (3. i. V = . This voltage difference also a ears across the branch consistin g of R1 and VD. IR1 is inde endent of Vin .e.on + VB . The ath through VD.18(b). 3.on V in D 1 turns off.28) That is.on . (c) sim li ed circuit..on = . ( f) com lete in ut/out ut characteristic.on . VD.on + VB between Vin and Vout . (d) equivalent circuit.VB .on . VR 2 (3.27) IR1 = . (b) ossible equivalent circuit for very negative in uts. (f) section of in ut/out ut characteristic.on and VB creates a difference of VD. Vout = V in . (g) equivalent circuit. and hence (3. We must now analyze these results to determ ine whether they agree with our assum tions regarding the state of D1 and D2 .on Vout X R1 Vout D2 Y V B= 2 V R1 − V D. C onsider the current owing through R2 : out IR2 = .V is on.18 (a) Diode circuit.VB + VD. yielding R1 IR1 + VD.− V D. (e) equivalent circuit for in D.

18(f) lots the in ut out ut characteristic to the extent com uted thus far. At what oint does D2 turn on? The in ut voltage must excee d VY by VD. In summary. Since D2 is assumed off..18(h) lots the overall result. Thus.31) We now raise Vin and determine the rst break oint.e. Conse quently. We must now verify the assum tion that D2 remains off. 2007 at 13:42 79 (1) Sec. VX = Vout = 0. we have observed that the forward bi as assum tion for D2 translates to a current in a rohibited direction. Assuming that D1 is still slightly on.on .VD. Before D2 turns on.on [Fig. Redrawing the circuit as in Fig. 3. D2 o erates in reverse bias for Vin = .32) Exercise In the above exam le.18(g). i.VD. VX = Vin + VD. 3.30) Vout = Vin + VD. Fig. Vin .e.on . The diode therefore turns off at Vin = . the voltage at node Y is equal to +VB whereas the cathode of D2 is at .cls v. and VY = VB . we recogni ze that at Vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the oint at which D1 t urns off or D2 turns on. we draw the cir cuit as shown in Fig. i. Vout = Vin .VD. VD. The large value of IR2 and the constant value of IR1 indicate that the branch consisting of VB and D2 carries a large current with the direction shown.on a roaches zero. summarizing the regions of o eration.18(e)]. D2 must conduct current from its cathode to i t anode.on . 2006] June 30. revealing that Vout = 0 after the rst break oint because the current owing through R1 and R2 is equal to zero. 3..4 Large Signal and Small Signal O eration R R2 R : 1+ 2 . ¡ ¡ ¡ ¡ ¡ . assume D2 turns on before D1 turns off and show that the r esults con ict with the assum tion. Since at this break o int. Which one occurs rst? Let us assume D1 turns off rst and obtain the corres onding value of Vin . In other words. yielding a zero curren t through R1 . That is.1.18(c) and noting that VX = Vin + VD. (3. Vin must reach VB + VD.on .on . 3. we have D. Vout = 0. VR .18(d). D2 is indeed off.on . after which the circuit is con gured as shown in Fig. which is not ossible.1.on (3. 3. VB : Figure 3. VB 2 (3. 3. R2 . and hence D1 . 3.4 Large Signal and Small Signal O eration 79 which a roaches +1 for Vin = .on = .

The ideal and constant v oltage diode models resolve the issues to some extent.Our treatment of diodes thus far has allowed arbitrarily large voltage and curre nt changes. this model often com licates the analysis. making it dif cult to develo an intuitive understanding of the cir cuit’s o eration. “manual” analysis eventually becomes im ractical. as seen in revious exam les. We call this regime “largesignal o eration” and the ex onential characterist ic the “large signal model” to em hasize that the model can accommodate arbitrary si gnal levels. Furthermore. thereby requiring a “general” model such as the ex onential I/V characte ristic. However. as the number of nonlinear devices in the circuit i ncreases. but the shar nonlinearit y at the turn on oint still roves roblematic. ¡ ¡ ¡ . The following exam le illustrat es the general dif culty.

4 V cell hone charger.cls v. 2006] June 30.19 Ada tor feeding a cell hone. He then deci des to ut his knowledge of electronics to work and constructs the circuit shown in Fig. the current owing through R1 is equal to . where three identical diodes in forward bias roduce a total volt age of Vout = 3VD 2:4 V and resistor R1 sustains the remaining 600 mV.33) (3. IX = Vad R Vout 1 = 6 mA: We note that each diode carries IX and hence (3.6 (a) Determine the reverse IX 600 mV R 1 = 100 Ω Vad = 3 V Ada tor Vout Cell hone Figure 3. (a) With Vout = 2:4 V. (b) Com ute Vout if the ada tor voltage is in fact Solution = 2:4 V.17 Having lost his 2. Neglect t he current drawn by the cell hone.34) IX = IS ex VD : V T It follows that (3. saturation current. an electrical engineering student tries several stores but does not nd ada tors with out uts less than 3 V.35) mV 6 mA = IS ex and 800mV 26 ¡ . IS 1 so that Vout 3.1 V. 3 Diode Models and Circuits Exam le 3. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 80 (1) 80 Cha .19.

1 V. (2.1 V must dro across R1 . 7 Reca ll from Eq. Since the voltage acros s each diode has a logarithmic de endence u on the current.(3.37) (b) If Vad increases to 3.109) that a tenfold change in a diode’s current translates to a 60 mV change in its voltage.38) ¡ 6 Made for the sake of sim licity here. raising IX to 7 mA. .7 To examine the circuit quantita tively. the ad ditional 0. rst su ose Vout remains constant and equal to 2. Then.4 V.16 A: (3. this assum tion may not be valid.36) IS = 2:602 10. the change from 6 mA to 7 mA indeed yields a small change in Vout . we ex ect that Vout increases only slightly. To u nderstand why. we begin with IX = 7 mA and iterate: Vout = 3VD (3.

39) (3. 2006] June 30.40) . 3. IX = Vad R Vout 1 = 6:88 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. But. which sustains a voltage VD1 and carries a current ID1 [ oint A in Fig. The constant voltage diode model would not be us eful in this case. Now su ose a erturbation in the circuit changes the diode voltage by a small amount VD [ oint B in Fig. circuits conta ining com lex devices such as transistors may indeed become im ossible to analyz e if the nonlinear equations are retained. the reader may wonder if a sim ler a roach is really necessary. The sim licity arises because such models are linear. ID ? We can begin with the nonlinear characteristic: Vad from 3 V to 3. How do we redict the change in the diode c urrent. allowing standard circuit analysis and obviating the ne ed for iteration.cls v.20(c)].41) (3. since the above exam le does no t resent an overwhelmingly dif cult roblem. To develo our und erstanding of small signal o eration.35 is desired.42) Vout = 3VD = 2:411 V: (3. which translates to a new Vout : (3. 3. Of course. motivating The situation described above is an exam le of small “ erturbations” in circuits.44).4 Large Signal and Small Signal O eration 81 = 3VT ln IX I = 2:412 V: This value of Vout gives a new value for IX : S (3. The de nition of “small” will become clear later. 2007 at 13:42 81 (1) Sec.43) (3. let us consider diode D1 in Fig. we conclude that Vou t = 2:411 V with good accuracy. as seen in subsequent cha ters.20(a).20(b)] . us to seek a sim ler analysis method that can re lace the nonlinear equations an d the inevitable iterative rocedure. These thoughts lead us to the extreme ly im ortant conce t of “small signal o eration. Th ¡ ¡ ¡ ¡ ¡ ¡ .44) Noting the very small difference between (3. 3.40) and (3.” whereby the circuit ex eriences on ly small changes in voltages and currents and can therefore be sim li ed through t he use of “small signal models” for nonlinear devices. Exercise Re eat the above exam le if an out ut voltage of 2. 3.1 V results in a small change in the circuit’s voltages and curr ents.

47) + ID2 = IS ex VD1V V T VD1 ex V : = IS ex 2 = IS ex VD1 + V IS ex VD1 VT VT VT V VT T VT .e change in If V (3.46) (3.45) (3. then ex V=VT 1 + V=VT and ID .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49) The key observation here is that I is a linear function of V .21 Approximation of characteristic by a straight line. with a slope equal to the local slope of the cha racteristic. 2006] June 30. V 1 . with a proportiona lity factor equal to I 1 =VT . In other words. (c) change in I as a result (3. B Figure 3. (Note that larger values of I 1 lead to a greater I for a given V .20(c) between points A and B can be approximated by a straight line (Fig.48) = I 1 + V I 1 : V T That is. I = V I 1 : V T (3.cls v.) The above r esult should not come as a surprise: if the change in V is small. The signi cance of this trend becomes clear later. the section o f the characteristic in Fig.21). 3. (b) operating point of of ch ange in . 3 Diode Models and Circuits ID V D1 D1 I D1 I D1 A V D1 (a) (b) ID I D2 I D1 VD ? B A V D1 V D2 (c) Figure 3. 2007 at 13:42 82 (1) 82 Cha .20 (a) General circuit containing a diode. ¢ ∆I ¢ ¢ ¢ ¢ ¢ I 2 I I 2 I 1 A V 1 V 2 V B I 1 A ∆V ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ∆V V ¢ ¢ ¢ ¢ ¢ ¢ . 3.

49).51) (3. ¢ ¢ ¢ I dI V = dV jV =V 1 ¢ ¢ ¢ ¢ ¢ .45) to obtain the change in equiva lent to taking the derivative. (3.52) which yields the same result as that in Eq.(3. Writing Eq. I for a small change in V is in fact ¢ ¢ I = VS exp V 1 VT T T = IV 1 .8 8 This is also to be expected.50) (3. (3.

( a) etermine the current change if V changes by 1 mV. 3. then the change in the current is given by Eq. 2007 at 13:42 83 (1) Sec. (b) etermine the voltage change if I changes by 10%. Equivalently. we can assume the operation is at a point such as A in Fig. Point A is call ed the “bias” point or the “operating” point.9 A diode is biased at a current of 1 mA.49). 2006] June 30.4 Large-Signal and Small-Signal Operation 83 Let us summarize our results thus far. it moves on a straight line to point B with a slope equal to the local slope of the char acteristic (i..e. 3.21 and. Example 3. If the voltage across a diode changes by a small amount (much less than VT ). dI =dV calculated at V = V 1 or I = I 1 ).18 Solution (a) We have I I = V V T (b) Using the same equation yields (3. for small-signal analysis.53) (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.54) = 38:4 A: V = VT I I = 1 mA 0:1 mA = 2:6 mV: ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . (3.cls v. due to a small perturbation.

22(c) if only small changes in V1 and Vout a re of interest. Note that v1 and vout in 9 Also called the “quiescent” point. For bias calculations.on . the device behaves as a linear resistor. ¢ ¢ ¢ (3. t he diode is replaced with an ideal voltage source of value V . In the above example. For example. 3. and for small changes.57) Exercise In response to a current change of 1 mA.56) (3.22(a) summarizes the results of our derivations for a forward-biased diode. 3. In analogy with Ohm’s Law. Equation (3. rd = 26 .26 mV (3.55) in the above example reveals an interesting aspect of small-sign al operation: as far as (small) changes in the diode current and voltage are con cerned.55) (3. Figure 3.22( b) is transformed to that in Fig. Calculate the bias current of the diode. we de ne the “small-signal resistance” of the diode as: rd = VT : I This quantity is also called the “incremental” resistance to emphasize its validity for small changes. a diode exhibits a voltage change of 3 mV. the circuit of Fig.58) . with a resistance equal to rd .

As shown in Fig.23(a).on Model (a) R1 1 Vout v1 rd v out rd Small−Signal Model V1 (b) (c) Figure 3. I0 .19 Solution The signal waveform is illustrated in Fig. Exam le 3. ID ID I V (t ) V0 I0 V VD t t V0 t ¢ Fig.22(c) represent changes in voltage and are called small-signal quantities general. It follows that. 3. A sinusoidal signal having a eak am litude of V and a dc value of V0 can be ex ressed as V t = V0 + V cos !t. If this signal is a lied across a diode and V V T . we denote small-signal voltages and currents by lower-case letters . .22 Summary of diode models for bias and signal calculations.cls v. determine the resulting diode current. (c) smallsignal model. R1 V Bias ¢ ¢ . 3 iode Models and Circuits 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In . we rotate this diagram by 90 so that its vertical axis is aligned with the voltage axis of the diode characteristic. With a signal swing much less than VT . 2007 at 13:42 84 (1) 84 Chap. as the bias oint of the diode and V as a small erturbation.23(b). we ca n view V0 and the corres onding current. 2006] June 30. 3. (b) circui t exam le.

(b) res onse of a diode to the sinusoid.(a) (b) Figure 3.23 (a) Sinusoidal in ut along with a dc level.60) .59) rd = VT : I 0 (3. T and (3. V I0 = IS ex V 0 .

Calculate IS . 3.63) (3. investigate t he reverse case. 2006] June 30.e.61) (3. the eak current is sim ly equal to I = V =rd I = V0 V . V T a task much more dif cult than the above linear calculations. we have Exam le 3.62) (3. Denoting the change in VD by VD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.20 Solution VD1 + VD = VT ln ID1 + ID I = VT ln IID1 1 + ID I S S The above exam le demonstrates the utility of small signal analysis. 2007 at 13:42 85 (1) Sec.65) In the derivation leading to Eq. ID changes by a small amount and we wish to com ute the c hange in VD . we would need to solve the following equation ¡ ID t = I0 + I cos !t V I = IS ex V 0 + V0 V ¡ ¡ cos !t: T T were . i.10 (3. Beginning with VD = VT lnID =Is . Exercise = 800 mV ID t = IS ex V0 + V cos !t ..49).1 mA in res onse to V0 and V = 1:5 mV. we assumed a small change in VD and obt ained the resulting change in ID .64) The diode in the above exam le roduces a eak current of 0.4 Large Signal and Small Signal O eration 85 Thus. If V large.cls v. (3. T yielding (3.

.

66) (3.68) if = VT ln IID1 + VT ln 1 + ID : I S For small signal o eration. we assume ID ¡ .D1 (3.67) (3.

D1 ID1 and note that ln1 + 1.69) which is the same as Eq.49). Figure 3. (3. (3. distingu ishing between the cause and the effect. Thus. ID1 . 10 The function ex a sin bt can be a roximated by a Taylor ex ansion or Bessel functions.24 illustrates the two cases. VD = VT ID .

With our understanding of small-signal operation. (As mentioned earlier. 2007 at 13:42 86 (1) 86 Cha .25. we can construct the small-signal model shown in Fig. the voltages shown in t his model denote small changes. 3 Diode Models and Circuits ∆I = = ∆I I 1 VT 1 VT I 1 Figure 3. Example 3. 3.cls v.) We can thus write: R1 ¢ ¢ ¢ ¢ ¢ ∆I ¢ ∆V ¢ ¢ ∆V = ¢ ∆V (b) ¢ ∆V rd = ∆ I ¢ ∆I ∆V 1 (a) ¢ ¢ ¢ ¢ ¢ ¢ r d .21 Repeat part (b) of Example 3. 2006] June 30.17 with the aid of a small-signal model for the dio des. Since each diode carries I 1 = 6 mA with an adaptor voltage of 3 V and V 1 = 800 mV.17. we now revisit Example 3.24 Change in diode current (voltage) due to a change in voltage (curren t).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Repeat the above example by taking the derivative of the diode voltage equation with respect to I . where vad = 100 mV and rd = 26 mV=6 mA = 4:33 .

5-mV change in Vout .17) and (3.21) if the value of R1 in Fig. r vout = R 3+d3r vad 1 d = 11:5 mV: (3.71) That is.19 is changed to 200 .70) (3. 17. .Solution v ad rd rd rd v out Figure 3. solution of nonlinear diode equations predicted an 11-mV change in Vout . 3. Exercise Repeat Examples (3. a 100-mV change in Vad yields an 11.25 Small-signal model of adaptor. Th e small-signal analysis therefore offers reasonable accuracy while requiring muc h less computational effort. In Example 3.

3. Solution Since the current owing through the diodes decreases by 0. calculate rd ).cls v. (2) develo the small signal model for each dio de (i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26 Ada tor feeding a cell hone. 3.22 In Examples 3. on th e other hand. the load pulls a current of 0. A bad circuit designer.21. 2006] June 30. we write the change in the out ut voltage as: Vout = ID 3rd = 0:5 mA3 4:33 = 6:5 mV: (3. (3) re lace each diode with its small signal model and com ute the effect of the in ut change. A good circuit designer analyzes and understands the circuit before givin g it to the computer for a more accurate analysis. ¡ ¡ ¡ .e.5 mA11 and determi ne Vout . we utilize sophisticated sim ulation tools in the design of integrated circuits today. the current drawn by the cellphone is neglected. Now suppose.4 Large-Signal and Small-Signal Operation 87 Considering the power of today’s computer software tools. as shown in Fig.5 mA and since this cha nge is much less than the bias current (6 mA). In summary. allows the computer to think for him/her.72) (3. Indeed.5 mA V ad Vout Cell hone Figure 3. Example 3.74) Exercise Re eat the above exam le if R1 is reduced to 80 .. the reader may wonder if the smallsignal model is really necessary. but the intuition gain ed by hand analysis of a circuit proves invaluable in understanding fundamental limitations and various trade-offs that eventually lead to a compromise in the d esign. 2007 at 13:42 87 (1) Sec. the analysis of circuits containing diodes (and other nonlinear devi ces such as transistors) roceeds in three ste s: (1) determine— erha s with the a id of the constant voltage model— the initial values of voltages and currents (bef ore an in ut change is a lied).73) (3.26.17 and 3. ~6 mA R 1 = 100 Ω 0.

.11 A cell hone in reality draws a much higher current.

on V in R1 Vout t V D. th e circuit still o erates as a recti er but roduces a slightly lower dc level. As illustrated in Fig.23 Prove that the circuit shown in Fig. 3.28 Sim le recti er. allowing R2 to maintain Vout = 0.5. Half−Wave and Full−Wave rectifiers Limiting Circuits Voltage Doublers Level Shifters and Switches Figure 3.27 A lications of diodes. Vout remains equal to zero until Vin exceeds VD.29.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. at which oint D1 turn s on and Vout = Vin .28. 3. De icted in Fig. In articular. A brief outline is shown below.VD. D1 remains on for negative values of Vin . we no longe r assume D1 is ideal. 3.10(b) and study it more closely. but use a constant voltage model. on .29(a) is also a recti er. D1 V D. In this case.on . For Vin VD.1 Half Wave and Full Wave Recti ers Half Wave Recti er Let us return to the rect i er circuit of Fig. 3 . D1 turns off. Solution Exercise Plot the out ut if D1 is an ideal diode.on V in V out Figure 3.on . but the effect is negligible. D1 V in R1 Vout V out (a) (b) V in t Figure 3. but it blocks the ositive cycles.VD.29 Recti cation of ositive cycles. for Vin . s eci cally. D1 is off12 and Vout = 0.on . 3. the resulting out ut reveals that this circuit is also a rec ti er. 2006] June 30.5 A lications of Diodes The remainder of this cha ter deals with circuit a lications of diodes. 3 Diode Models and Circuits 3. Exam le 3. 12 If Vin 0.on . D1 carries a small leakage current. Thus. VD. As Vin exceeds .cls v. ¡ ¡ ¡ ¡ . 2007 at 13:42 88 (1) 88 Cha .

Assumi ng a constant voltage model for D1 in forward bias.on .24 Called a “half wave recti er. Interestingly. (b) in ut and out ut waveforms. Here. dio des used in recti ers must withstand a reverse voltage of a roximately 2V with n o breakdown. V V − V D.30(b)]. VD1 is similar to Vin but with t he 13 The water i e analogy in Fig. at which oint D1 begins to act a s a battery and Vout = Vin .on t1 t2 t3 t4 t5 t Continuing our analysis. As Vin begins to fall. as a functi on of time. Fortunately. Vin = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As Vi n rises from zero. Vin = V = Vout + VD. For this reason. ¡ ¡ ¡ .31(a). 3.cls v. Vin = V . Vin falls below Vout . but Vout exhibits no tenden cy to change because the situation is identical to that at t = t1 . What ha ens as Vin asses its eak value? At t = t1 . 3. After t = t1 . Vout . D1 turns on as Vin exc eeds zero and Vout = Vin . At t = t2 . We must therefore attem t to create a constant out ut. 2006] June 30. the recti er generates an out ut that varies considerably wi th time and cannot su ly ower to electronic devices. D1 is off until Vin VD. Vin Vout and the diode ex e riences a negative voltage. Vin just exceeds Vout but still cannot turn D1 on. Unlike a battery. 3. 3. i. (b) The voltage across the diode is VD1 = Vin . (a) With a zero initial condition across C1 . Figure 3. At t t2 . 3.on V in D1 V in C1 Vout Maximum Reverse Voltage (a) (b) Figure 3. the diode sustains a zero voltage difference. VD. we begin with a zero initial condition across C1 and study the behavior of the circuit [Fig. VD.31(b). 2007 at 13:42 89 (1) Sec. Thus.on across the diode. Vout must remain constant. Using the lots in Fig.V . Does Vout change after t = t1 ? Let us consider t = t4 as a otenti ally interesting oint.on. a lying a maximum reverse bias of Vout . (b) Plot the voltage across D1 .5 A lications of Diodes 89 V out V D. which is im ossible.3(c) roves useful here. and D1 is on. Assuming an ideal diode model. The o eration of this circuit is quite different from that of the above recti er. VD. a sim le modi cation solves the roblem . Vout remains equal to V .on . VD1 . VD.on . the resistor is re laced with a ca acitor. we readily arrive at the waveform in Fig. Vout reaches a eak value of V .31(a) shows the in ut and out ut waveforms. 3.o n .on inde nitely. ( a) Re eat the above analysis. we have Vin = V and Vout = V . VD. Exam le 3.13 The diod e therefore turns off after t1 . turning D1 off. then C1 would need to be discharged by a current owin g from its to late through the cathode of D1 .e.28 does not roduce a useful out ut. This is be cause if Vout were to fall.” the circuit of Fig.on = Vout .30(a). Vin = 2V . As de icted in Fig.. At t = t5 . 3. we note that at t = t3 . VD.30 (a) Diode ca acitor circuit. In other wor ds.

Solution .

(b) voltage across the diode. 3. we consider a more r ealistic a lication where this circuit must rovide a current to a load. . The circuit of Fig. 2006] June 30.V . We will ex loit this result in the design of voltage Exercise Re eat the above exam le if the terminals of the diode are swa ed.14 But how is the value of C1 chosen? To answer this question.3 V. 3.cls v.5. Solution Exercise What ower dissi ation does a 1 load re resent for such a su ly voltage? 14 This circuit is also called a “ eak detector. Since P = V I . Exam le 3. then RL = V=I = 0:436 .25 A la to com uter consumes an average ower of 25 W with a su ly voltage of 3.31 (a) In ut and out ut waveforms of the circuit in Fig.30(a) achieves the ro erties required of an “ac dc converte r. 2007 at 13:42 90 (1) 90 V out Cha .” generating a constant out ut equal to the eak value of the in ut sinusoid. we have I 7:58 A.” ¡ ¡ −2 V (b) . RL .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4). If the la to is modeled by a resistor.30 with an i deal diode. average value shifted from zero to doublers (Section 3. 3 Diode Models and Circuits t1 V in (a) t t1 t V D1 Figure 3. Determine the average current drawn from the batteries or the ada ter.

The out ut voltage continues to decrease while Vin goes through a negative excur sion and returns to ositive values. since changes in Vout are undesirable. the current drawn by RL when D1 is off creates only a small ch ange in Vout . thereby turni ng D1 on and forcing Vout = Vin . VD.” Also.on V in D1 V in t1 C1 RL Vout t3 t2 t V out VR (a) (b) Figure 3.33 Out ut waveform of recti er for different values of smoothing ca acito r.32 as values.32(a)]. the circuit a roaches that in F ig. C1 is cal led the “smoothing” or “ lter” ca acitor. 3. C1 varies from very large values to very small C1 is very large. From the waveforms in Fig. Exercise . we recognize that Vout behaves as b efore until t = t1 . VD.33 illustrates several cases. 2006] June 30. the circuit behaves as in t he rst cycle.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VD. The resulting variation in Vout is called the “ri le.26 Sketch the out ut waveform of Fig. 3. If V in V out Very Small C 1 Large C1 Small C1 Solution t Figure 3.5 A lications of Diodes 91 As suggested by the above exam le. Exam le 3. the load can be re resented by a sim le resis tor in some cases [Fig.32 (a) Recti er driving a resistive load. With such a choice of C1 . t = t2 . V V − V D. so does Vout because RL rovides a discharge ath for C1 . (b) in ut and out ut wa veforms. 3. if C1 is very small. Hereafter. We must therefore re eat our analysis with RL resent. still exhibiting a value of Vin . However. Vin exceeds Vout by VD. 3. as Vin begins to fall af ter t = t1 . Of cours e.on .32(b). C1 must be so large that the current d rawn by RL does not reduce Vout signi cantly.on . Figure 3. Conversely.on if the diode voltage is assumed relatively constant.on = V . 2007 at 13:42 91 (1) Sec. at t = t3 . exhibiting large variations in Vout .28. At some oint. Vin and Vout become equal and slightly later. Vout fall s slowly and D1 remains reverse biased.cls v. 3.

Re eat the above exam le for different values of RL with C1 constant. .

3 Diode Models and Circuits (a) Figure 3. To ensure a small ri le.cls v. L 1 where we have chosen t1 = 0 for sim licity.76) (3. thus. the value of C1 is chosen lar ge enough to yield an acce table ri le. in Fig. Since Vout = V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VR . VD. greater th an t3 .34). 3. t1 . 2007 at 13:42 92 (1) 92 Cha .on 1 . R tC L 1 t V . VD.C 0 t t3 .on at t = t1 . VD. for 1. To this end.on .on C : RL 1 Ri le Am litude In ty ical a lications. VD.77) Vout t V . 3. the ( eak to eak) am litude of the ri le. the discharge of C1 throu gh RL can be ex ressed as: V − V D. If the maximum current drawn by the load is known. noting that ex .on ex R.on D1 V in C1 RL Vout V V in t1 t3 t4 t2 t V out VR ¡ ¡ .75) RL C1 must be much (3.32(b) must remain below 5 to 10% of the in ut eak voltage.34 Ri le at out ut of a recti er. (3. VD. 1 . (b) t Vout t = V . we must com ute VR analyti cally (Fig. 2006] June 30. V .

a falling ram —as if a constant current equal to V . L 1 fin ¡ ¡ . t3 denotes the time during which D1 is on.The rst term on the right hand side re resents the initial condition across C1 an d the second term.on . VR V .78) Recognizing that if C1 discharges by a small amount.80) This section can be ski ed in a rst reading. Since t4 . where T = t4 . we write t3 . VD.on =RL .CVD. VR = V . t3 is equal to the in ut eriod.on =RL d ischarges C1 . V D. T . we can assume T Tin and hence (3. Thus. .79) (3. The eak to eak am litude of the ri le is equal to the amount of dis charge at t = t3 . VD.15 This result should not come as a sur rise because the nearly co nstant voltage across RL results in a relatively constant current equal to V . t1 = Tin . then the diode turns on for only a brief eriod. VD.on Tin C T : R L 1 (3.on Tin RL C1 15 Recall that VR . Tin . I = CdV=dt and hence dV = I=C dt.

on = 0:8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and cost of the ada tor may dictate a much greater ri le. 0.82) C1 = V . we can write VR = CIL : f 1 in (3. Another im ortant arameter of the diode i s the maximum forward bias current that it must tolerate.5 V. 2007 at 13:42 93 (1) Sec. assuming the transformer still roduces a eak to eak swing of 9 V. 2006] June 30.25. For a given junction d ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ .83) Diode Peak Current We noted in Fig. Thus. Determine the minimum value of the lter ca acitor that maintains the ri le below 0. A halfwave recti er follows the transformer to su ly the ower to the la to com uter of Exam le 3. eriodic variation. Re eating the above analy sis with the load re resented by a constant current source or sim ly viewing V . RL = 0:436 . In fact. and cost of the ca acitor.81) (3. 3.on Tin VR RL = 1:417 F: This is a very large value. e. VD. The designer must trade the ri le am litude with th e size. = Tin1. VD. thereby demanding that the circuit following the recti er tolerate such a large.g.cls v. Exam le 3. limitations on size. Assume VD.80) as the load current. 3. and Tin = 16:7 ms. 50 Hz line voltage. (3.. IL . (3. Exercise Re eat the above exam le for 220 V.30(b) that the diode must exhibit a reverse breakdown voltage of at least 2 V .5 A lications of Diodes 93 where fin . We have V Solution = 4:5 V. weight. 60 Hz line voltage to a eak to eak swing of 9 V. the current drawn by the load is known. weight. Which mains frequency gives a more desirable choice of C1 ? In many cases.1 V.on =RL in Eq.27 A transformer converts the 110 V.

V sin !in t1 = V . a roximately equal to V . the ower dissi ated in the diode (= VD ID ) may raise the junction tem erature so much as to d amage the device. and (2) the current su lied to RL . we note that the oint at which D1 tur ns on is given by Vin t1 = V . . We recognize from Fig. i.on V for sim licity.o ing ro le and geometry. VD.35. that the diode current in forward bias consists of two com onents: (1) the transient current drawn by C1 .e. C1 dVo ut =dt. 3. if the current exceeds a certain limit. VR . Assuming VD.84) rst reading. This section can be ski ed in a (3. at the oint D1 turns on because the slo e of the out ut waveform is m aximum. Thus..on =RL . VR . for Vin t = V sin !in t. The eak diode current therefore occurs when the rst com onent reaches a maxim um.

86) (3. obtaining the diode current as . reduces to V D1 V in C1 RL V out V − VR Vin t. 2007 at 13:42 94 (1) 94 Cha . 3 Diode Models and Circuits V in Vout t1 t Figure 3. we also have Vout t (3.85).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.85) V ID1 t = C1 dVout + R dt This current reaches a eak at t = t1 : V = C1 !in V cos !in t + R : L L (3.35 Recti er circuit for calculation of ID .on neglected. V L s 2 V V = C1 !in V 2V R .cls v. VR + R L Since VR V I = C1 !in V cos !in t1 + R L which. 2006] June 30. from (3. VR + R : V 2 . 1 .88) 2 V I = C1 !in V 1 . and hence sin !in t1 = 1 .87) (3. VR : V With VD.

s .

!in = 260 Hz.on We have V V . = 4:5 V. I = 517 A: (3. and VR = 0:1 V.(3.93) V V R RLC1 !in 2V R + 1 : L Determine the eak diode current in Exam le 3.89) (3.27 assuming VD.92) Exam le 3. Thus. we neglect the second term under the square root: V V I L C1 !in V 2V R + R . RL = 0:436 .91) s ! (3.28 Solution 0 and C1 = 1:417 F.90) s (3.

Full Wave Recti er The half wave recti er studied above blocks the negative half cyc les of the in ut. Note the olarity of Vout in the two diagrams. 3.5 A lications of Diodes 95 This value is extremely large. 3.37(b). i. multi lied by . allowing the lter ca acitor to be discharged by the load for al most the entire eriod. both diodes are off.37(c): we must rst d esign a half wave recti er that inverts. Consider the two half wave recti ers shown in Fig. 3. where one blocks negat ive half cycles and the other. if Vin 0. ositive half cycles. We rst im leme nt a circuit that erforms this function [called a “full wave recti er” (FWR)] and nex t rove that it indeed exhibits a smaller ri le..37(e) for sim licity. Note that the current drawn by C1 is much greater than that owing through RL . 2006] June 30.cls v.37(a). Shown in Fig. Conversely. if Vin 0.1). Can we combine these circui ts to realize a full wave recti er? We may attem t the circuit in Fig. Exercise Re eat the above exam le if C1 = 1000 F. Figure 3. 2007 at 13:42 95 (1) Sec. no recti cation is erformed because the negative half cycles are not inverted .e. unfortunately.36( a). It is ossible to reduce the ri le voltage by a factor of two through a sim le modi cation. the roblem is reduced to that illustrated in Fig..36 (a) In ut and out ut waveforms and (b) in ut/out ut characteristic o f a full wave recti er. both D2 and D1 are on and Vout = . We begin with the assum tion t hat the diodes are ideal to sim lify the task of circuit synthesis.V in . bu t with the negative half cycles inverted (i. Here. The circuit therefore suffers from a large ri le in the resence of a heavy load (a high current). the out ut contains both ositive and negative half cycles. Illustrated in Fig. 3. yielding a zero current through ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ . the idea is to ass both ositive and negative half cycles to the out ut.36( b) de icts the desired in ut/out ut characteristic of the full wave recti er. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. bu t. 3. y (t ) t V in t (a) Vout Vout t x (t ) t (b) Figure 3. e. 3.37(d) is such a to ology. which can also be redrawn as in Fig.

which sim ly blocks the negative in ut half cycles..” Let us summarize our thoughts with the aid of the circuit shown in Fig. D2 and D1 are on and D3 and D4 are off. In analogy with this circuit. 3.RL and hence Vout = 0.37(f)]. 3.e. we also com ose that in Fig . If Vin 0. reducing the circuit to that shown in Fig.38(b).38(b) and called a “bridge recti er. 3. we can now co mbine the to ologies of Figs. This con guration is usually drawn as in Fig. De ict ed in Fig. i. 3.3 8(c) and ¡ .37(d) and (f) to form a full wave recti er. the resulting circuit asses the negative half cycles throug h D1 and D2 with a sign reversal [as in Fig.37(d)] and the ositive half cycl es through D3 and D4 with no sign reversal [as in Fig.38(a). With the foregoing develo ments. 3. Vout = 0 fo r Vin 0 and Vout = Vin for Vin 0. 3. 3. 3.37(f).

(c) recti cation and inversion. (f) ath for ositive half cycles. D2 Vin RL Vout Vin D4 (a) (b) Vout RL D3 D1 D2 Vin D4 (c) D3 Vin D1 D2 .37 (a) Recti cation of each half cycle. (e) ath for negative ha lf cycles. 3 Diode Models and Circuits RL (a) (b) D2 D2 ? D3 Vout Vin RL D4 Vout RL Vin D1 RL Vout Vin RL D1 (c) (d) (e) (f) Figure 3. 2007 at 13:42 96 (1) 96 D1 RL D2 RL Cha .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) no recti cation . (d) realization of (c). 2006] June 30.cls v.

38(c) and (d) reveal that the circuit introduces two for ward biased diodes in series with RL .29 Assuming a constant voltage model for the diodes. The dro of 2VD.D3 D4 D1 (d) Figure 3.38 (a) Full wave recti er. How do these results change if the diodes a re not ideal? Figures 3.28 roduces Vout = Vin . By contrast.38(d). and Vout = Vin . the bridge is sim li ed as sho wn in Fig. 3. the half wave recti er in Fig.on for Vin 0.on may ose dif culty if V is relatively small and the out ut voltag e must be close to V . yielding Vout = . The out ut remains equal to zero for jVin j Solution 2VD. if Vin 0.on . On the other hand. 2VD. 3.Vin .on ¡ ¡ ¡ ¡ ¡ . yielding Vout = . lot the in ut/out ut characte ristic of a full wave recti er.on and “tracks” the in ut for jVin j VD. Exam le 3.Vin . (d) current ath for ositive in ut. (b) sim li ed diagram. (c) current ath for nega tive in ut. VD.

on t Figure 3.39 In ut/out ut characteristic of full wave recti er with nonideal diodes .39 lots the result.94) of 2VD. 2007 at 13:42 97 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Since the ca acitor discharge occurs for abo ut half of the in ut cycle.on VR 2 V . the ri le is a roximately equal to half of that in Eq.cls v.CVf .40(a)]. 3. 2006] June 30. 3. Exercise What is the slo e of the characteristic for jVin j 2VD.on D1 RL C 1 Vout D3 (b) Figure 3. 1 2 D.on due to the bridge. R L 1 in where the numerator re ects the dro (3. (b) equivalent circuit.on ? We now redraw the bridge once more and add the smoothing ca acitor to arrive at the com lete design [Fig. Figure 3. (3.5 A lications of Diodes 97 with a slo e of unity. Vout Vout V in t −2 V D.on +2V D. ¡ ¡ .80): V in t D4 D1 RL C 1 Vout V out t (a) D2 Vin D3 A D2 Vin B D4 V D.40 (a) Ri le in full wave recti er.

3. we have Vout = .cls v.41. Assume no smoothing ca acitor is connected to the out u t. whereas the latter does not. ¡ ¡ ¡ ¡ ¡ . 2VD.38(c) and (d).28). From Figs. 3. 3 Diode Models and Circuits In addition to a lower ri le.on for Vin +2VD. full wave recti ers exhibit a lower ri le and require only half the diode brea kdown voltage.on I D1 = I D2 RL t I D3 = I D4 t − V − 2V D.41 Currents carried by diodes in a full wave recti er. In Problem 38.42. VD.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exam le 3. the voltage across D2 . the diode curre nts a ear as shown in Fig.on for Vin .on. well justifying their use in ada tors and chargers. The results of our study are summarized in Fig. Another oint of contra st between half wave and full wave recti ers is that the former has a common termi nal between the in ut and out ut orts (node G in Fig. A similar argument a lies to the other diodes. we study the effect of shorting the in ut and out ut g rounds of a fullwave recti er and conclude that it disru ts the o eration of the c ircuit. Thus. 3. 3. Exercise Sketch the ower consumed in each diode as a function of time.40(b).on .on and Vout = Vin . VAB . 2007 at 13:42 98 (1) 98 Cha .on + Vout = V . As illustrated in Fig.2VD.16 16 The four diodes are ty ically manufactured in a single ackage having four te rminals. the full wave recti er offers another im ortant adv antage: the maximum reverse bias voltage across each diode is a roximately equa l to V rather than 2V . two of the diodes carry a current equal to Vout =RL and the other two remain off. Solution V in t V − 2V D. 3. In each half cycle. is sim ly equal to VD. 2006] June 30.30 Plot the currents carried by each diode in a bridge recti er as a function of time for a sinusoidal in ut. While using two more diode s.on RL Figure 3.Vin + 2VD. when Vin is near V an d D3 is on.

5 A lications of Diodes 99 D2 D3 D4 D1 RL C1 Vout V in t V in V out t Reverse Bias (a) Reverse Bias (b) Figure 3.96) Exam le 3. ¡ V 2 V V − 2V D.42 Summary of recti er circuits. 2007 at 13:42 99 (1) Sec.2 V.on D1 V in C1 RL V − V D.31 Design a full wave recti er to deliver an average a voltage of 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. Since the out ut voltage is a roximatel y equal to V .cls v. Solution We begin with the required in ut swing. = 3:6 V + 2VD. 2006] June 30.6 V and a ri le of 0.on 5 :2 V : (3.on Vin ower of 2 W to a cell hone with . we have Vin.on .95) (3. 2VD.

97) (3.Thus. (3. C1 = 23. Next.83) for a f ull wave recti er gives VR = 2CILf For VR W = 32:6 V 2C1f : 1 in 1 in (3. Rewriting Eq. we determine the minimum valu e of the smoothing ca acitor that ensures VR 0:2 V. 000 F: The diodes must withstand a reverse bias voltage of 5. the transformer receding the recti er must ste the line voltage (110 Vrms or 220 Vrms ) down to a eak value of 5.2 V. (3.99) Exercise If cost and size limitations im ose a maximum value of 1000 F on the smoothing ca acitor.98) = 0:2 V and fin = 60 Hz. what is the maximum allowable ower drain in the above exam le? ¡ .2 V.

2 Voltage Regulation The ada tor circuit studied above generally roves inade quate. a cell hone). O eratin g in the reverse breakdown region. Exercise What if a constant voltage of 0.8)]. (3. 2006] June 30. Unfortunately. Owing to its small am litude. thus roviding a relatively constant out ut des ite in ut variations if rD R1 . if the ada tor su lies ower to a stereo. the nite out ut im edance of the transformer leads to changes in Vout if the current drawn by the load varies. resulting in a zero out ut. Is it ossible to use the half wave or full wave recti ers studied abo ve? Solution No.32 A radio frequency signal received and am li ed by a cell hone exhibits a eak swin g of 10 mV. Figure 3. Moreover. as studie d in Exam le 3.17 rovides a voltage of 2.44(a) shows another regulator circuit em loying a Zener diode. 44(b): This section can be ski ed in a rst reading. For these rea sons. 3 Diode Models and Circuits Exam le 3. i n the range of 1 to 10 . This can be seen from the small signal model of Fig.43 as a more ver satile ada tor having a nominal out ut of 3VD.4 V. ¡ ¡ ¡ ¡ ¡ ¡ ¡ . the circuit of Fig. For such signal levels. rD .8 V is added to the desired signal? 3. 3. We may therefore arrive at the circuit shown in Fig.g. the signal cannot turn actual diode s on and off. We wish to generate a dc voltage re resenting the signal am litude [ Eq.cls v.5. 3. the out ut voltage varies with the load current. Due to the signi cant variation of the line voltage. “ recision recti c ation” is necessary. ossibly exc eeding the maximum level that can be tolerated by the load (e.40(a) is often followed by a “voltage regulator” so as t o rovide a constant out ut. the ri le may become seriously objectionable in many a lications. Diode Bridge R1 Vin C1 Load Figure 3. For exam le. a subject studied in Cha ter 8.43 Voltage regulator block diagram.on 2:4 V. the 120 Hz ri le can b e heard from the s eakers. Furthermore. it is not. incurring only an 11 mV change in the out ut for a 100 mV variation in th e in ut. the eak am litude ro duced by the transformer and hence the dc out ut vary considerably. We have already encountered a voltage regulator wit hout calling it such: the circuit studied in Exam le 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. D1 exhibits a small signal resistance..22. 2007 at 13:42 100 (1) 100 Cha . 3.

.

and the stability of the out ut with res ect to load c urrent variations. then changes in Vin are attenuated by a r oximately a factor of 200 as they a ear in Vout .cls v. oor stability i f the load current varies signi cantly.” de ned as Vout =Vin . 2007 at 13:42 101 (1) Sec.” de ned as Vout =IL . 3. D vout = r r+ R vin : D 1 (3. V in has a nominal value of 5 V.on VDz v in R1 v out r d1 r d2 v in R1 r d1 r d2 v out iL Exam le 3.5 A lications of Diodes R1 Vout D1 R1 v out rd 101 V in v in (a) (b) Figure 3. (b) small signal equivalent of (a ). (c) load regu lation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. namely. 3. 2006] June 30. We rst determine the bias current of D1 and hence its small signal resistance: ¡ ¡ ¡ ¡ .7 V and a small signal resistance of 5 .43. Assuming VD. Our brief study of regulators thus far rev eals two im ortant as ects of their design: the stability of the out ut with res ect to in ut variations. 3.44 (a) Regulator using a Zener diode. In the circuit of Fig. (b) small signal equivalent.100) For exam le. The former is quanti ed by “line regulation.on 0:8 V for D1 . if rD = 5 and R1 = 1 k . and D2 has a reverse breakdown of 2. determine t he line and load regulation of the circuit.45 Circuit using two diodes. V in R1 Vout D1 D2 VD. The Zener regulator nonethele ss shares the same issue with the circuit of Fig. and the latter by “load regulation.45(a).33 Constant (a) (b) (c) Figure 3. R1 = 100 .

Solution ID1 = Vin .103) (3.104) .on .101) (3. VD2 R1 = 15 mA: Thus. VD. (3.102) rD1 = IVT D1 = 1:73 : (3.

iL: That is. Exercise Re eat the above exam le for R1 = 50 and com are the results. Figure 3.44(b).109) This value indicates that a 1 mA change in the load current results in a 6.5. 3. As the distance decreases from kilom ¡ ¡ ¡ ¡ .46 summarizes the results of our study in this section. we have vout rD1 + rD2 jjR1 = .46 Summary of regulators.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.31 mV change in the out ut voltage.cls v. we com ute the line regulation as vout = rD1 + rD2 vin rD1 + rD2 + R1 = 0:063: (3.105) (3. 3. 3. we assume the in ut is constant and study the effect of loa d current variations.3 Limiting Circuits Consider the signal received by a cell hone as the user comes closer to a base station (Fig. Using the small signal circuit shown in Fig.47).108) (3.45(c) (wher e vin = 0 to re resent a constant in ut). 3 Diode Models and Circuits From the small signal model of Fig. (3.107) vout = r + r jjR D1 D2 1 iL = 6:31 : (3. D1 Vin C1 Load Vin Load Vin Load Figure 3.106) For load regulation. 2007 at 13:42 102 (1) 102 Cha . 2006] June 30. 3.

” the out ut must remain constant. Vout = Vin . As illustrated in Fig.eters to hundreds of meters. a signal a lied to the in ut em erges at the out ut with its eak values “cli ed” at VL . We now im lement a circuit that exhibits the above behavior. In ¡ . translating to the in ut/out ut characteristic shown i n Fig.48(b). 3. How should a l imiting circuit behave? For small in ut levels. The nonlinear in ut out ut characteristic sug gests that one or more diodes must turn on or off as Vin a roaches VL . 3. It is therefore desirable to “limit” the signal am litude at a suitable oint in the receiver. This behavior must hold for both osi tive and negative in uts..48(a). the signal level may become large enough to “saturate” the circuits as it travels through the receiver chain. and as the in ut level exceeds a “thresho ld” or “limit. e.g. the circuit must sim ly ass the in ut to the out ut.

3. First.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the above to ology must satisfy two other conditions. To serve as a more general limiting circuit.5 A lications of Diodes 103 Base Station Receiver Base Station Receiver (a) Figure 3. e. res ectively. where the ositive half cycles of the in ut are cli ed at 0 V and +1 V. Vout is equal to Vin for Vin VD. the limiting level. we ostulate that a constant voltage source in series wit h D1 shifts the limiting oint. accom lishing this objective. fact. As illustrated in Fig.47 Signals received (a) far from or (b) near a base station. 2007 at 13:42 103 (1) Sec.on . De icted in Fig. (b) res onse to a sinusoid. 3. 3.. 3.11(c). 3 ¡ . Ins ired by the ci rcuit of Fig. (b) Vout Vout + VL − VL + VL − VL Vout + VL − VL + VL V in V in − VL t t (a) (b) Figure 3. We r eexamine the former assuming a more realistic diode. VL .cls v.48 (a) In ut/out ut characteristic of a limiting circuit. we have already seen sim le exam les in Figs.on thereafter. must be an arbitrary voltage and not necessarily equal to VD.49(a).g.11(b) and (c).on and eq ual to VD. the constant voltage model. 2006] June 30.

on . A signal must be limit ed at 100 mV. Assuming VD. Seco nd. Thus. as shown i n Fig. the negative values of Vin must also ex erience limiting.on [Fig. 3. . then the circuit limits at Vin = . 3. Figure 3. Similarly. we recognize that if the anode and cathode of D1 are s wa ed.50(b). Finally. the resulting circuit limits at VL = VB 1 + VD.VD.49(b).52(b) shows the resu lt.on .52(a) illustrates how the voltage sources must shift the break oints. the source in se ries with D2 must be ositive and equal to 700 mV.49(a).34 = 800 mV. Note that VB 1 can b e ositive or negative to shift VL to higher or lower values.50(a)]. res ectively. Exam le 3. Beginning with the circuit of Fig. 3. 3. inserting constant voltage sources in series with the diodes sh ifts the limiting oints to arbitrary levels (Fig.. the voltage source in series with D1 must be negative and equal to 700 mV. design the required limiting Solution Figure 3.on circuit.51). Since the ositive limiting oint must shift to the left. two “anti arallel” diodes can create a characteristic that limits at VD.

Thus.cls v. e. we make two observations.17 Nonetheless. This is because. However. Exercise Before concluding this section.54(a). (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the voltage across C1 cannot change e ven if Vin changes because the right late 17 Recall that 18 Voltage doublers are an exam le of “dc dc converters. to charge one late of a ca acitor to +Q. This section can be ski ed in a rst reading.109) im lies that this effect is ty ically negligible. it is hel ful to review some basic ro erties of ca acitors. Se cond.on V D.VL Vin +VL.5. ¡ ¡ ¡ . in the circuit of Fig. the 60 mV/decade ru le ex ressed by Eq.Q.53).1:1 V. so does the current through the diode that i s forward biased and hence the diode voltage. 6 V. Vout = Vin . 2007 at 13:42 104 (1) 104 Cha ..on t t (a) Vout R1 D1 VB1 V D. 3 Diode Models and Circuits Vout R1 V in D1 Vout V D. the other late must be charged to . 3. requiring tha t the discrete and integrated circuits o erate with such a value.on + V B1 Vout V D.on + V B1 t V in t (b) Figure 3. the circuits st udied above actually dis lay a nonzero slo e in the limiting region (Fig.g..18 Before stu dying doublers. “Voltage doublers” may serve this ur ose.49 (a) Sim le limiter. 3.on V in Vout V D. 3 V. 3.g. Fir st. we have thus far assumed Vout = Vin for . as Vin increases. (b) limiter with level shift. 2006] June 30.on + V B1 V in Vout V D. Re eat the above exam le if the ositive values of the signal must be limited at +200 mV and the negative values at . the d esign of some circuits in the system is greatly sim li ed if they run from a highe r su ly voltage.” VD = VT lnID =IS . e.4 Voltage Doublers Ele ctronic systems ty ically em loy a “global” su ly voltage. First. but it is ossible to realize a non unity slo e in the region.

2006] June 30.on 105 Vout V in t V in D1 Vout t (a) R1 V in − V D. 3. 2007 at 13:42 105 (1) Sec.on − V D. (b) limiter for both half cycles.on − V B2 V D.on + V B1 V in Vout t V in D1 VB1 D2 VB2 Vout ¡ .50 (a) Negative cycle limiter.on Vout + V D. Vout R1 − V D.on + V D.on + V B1 V D.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on − V D.5 A lications of Diodes R1 Vout − V D.on Vout V in t D1 D2 Vout t (b) Figure 3.cls v.

a ca acitive voltage divider such as that in Fig. thus requiring that the right late absorb negative charge of the same magnitude from the to late of C2 . Thus. the t o late of C2 equivalently holds more ositive charge. the left late of C1 receives ositive charge from Vin . the voltage change acr oss C1 is equal to C2 Vout =C1 . and hence the bottom la te absorbs negative charge from ground.51 General limiter and its characteristic. Note that all four lates receive or rel ease equal amounts of charge because C1 and C2 are in series.− V D. resulting from Vin . Since VC 1 remains constant.54(b) o erates a s follows.on − V B2 t Figure 3. If Vin becomes more ositive. This is an im ortant observati on. a n in ut change Vin directly a ears at the out ut. 3. Adding these two voltage changes and equating th e result to Vin . Vout . Having lost negative charge. of C1 cannot receive or release charge (Q = CV ). we have Vin = C2 Vout + Vout : C 1 (3. Second.110) . we write the change in the charge on C 2 as Q2 = C2 Vout . which also holds for C1 : Q2 = Q1 . To determine the c hange in Vout .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.53 Effect of nonideal diodes on limiting characteristic.on −100 mV + V D. 3 Diode Models and Circuits Vout + V D. . V C1 ∆V in V in C1 Vout ∆V in V in C1 C 2 Vout (a) (b) Figure 3.cls v. 2006] June 30. (b) voltage division . (b) in ut/out ut characteristic.54 (a) Voltage change at one plate of a capacitor. 2007 at 13:42 106 (1) 106 Cha . Vout V in Figure 3.52 (a) Exam le of a limiting circuit.on +100 mV (a) R1 D1 D2 V in V in Vout 700 mV (b) Figure 3.

30(a). we derive the output waveform from a different persp ective so as to gain more insight. Assuming an ideal diode and a zero initial co ndition across C1 . we note that as Vin exceeds zero. 3. As our rst step toward realizing a voltage doubler. Interestingly. For further investigation. 3.111) This result is similar to the voltage division expression for resistive dividers . recall t he result illustrated in Fig. Vout = C C1 C Vin : 1+ 2 (3. except that C1 (rather than C2 ) appears in the numerator.55. While Vout in this circuit behaves exactly the s ame as V 1 in Fig.54(a) is a special case of the capacitive divider with C2 = 0 and hence Vout = Vin . more importantly. a peak value of .That is. the input tends to place p ositive charge on the left plate of C1 and hence draw negative ¢ ¢ .31: the voltage across the diode in the peak det ector exhibits an average value of . where the diode and the capacitors are exchanged and the volt age across 1 is labeled Vout .2 Vp (with respect to zero).Vp and. we redraw the circuit as s hown in Fig. 3. 3. the circuit of Fig.

5 Applications of iodes t1 V out V in −V 107 0 t V in C1 D1 Vout V in V in t1 (a) Figure 3..e.56 if the initial condition across C1 is zero. the out ut goes from zero to . Consequently. 2006] June 30.V . 3.54(a).31(b). The out ut wave form is thus identical to that obtained in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2V . 3. and the cycle re eats inde nitely. reducing the circuit to that in Fig. the voltage across C1 remains equal to Vin because its right lat e is “ inned” at zero by D1 . 3.35 V out V in C1 t D1 Vout V in t2 V in V in V in ¡ t −2 V −V (b) ¢ . In articular. After t = t1 .55 (a) Ca acitor diode circuit and (b) its waveforms. Vin begins to fall and tends to dischar ge C1 . 3. charge from D1 . The d iode therefore turns off. 2007 at 13:42 107 (1) Sec. Plot the out ut wavefor m of the circuit shown in Fig. draw ositive charge from the left late and hence from D1 . +2 V Exam le 3. forcing Vout = 0.cls v. i. D1 turns on. as Vin varies from +V to . From thi s time.19 As the in ut ris es toward V . the out ut sim ly tracks the changes in the in ut while C1 sustains a co nstant voltage equal to V .

then the circuit resembles that in Fig.56 Ca acitor diode circuit and (b) its waveforms. 3. ¡ t4 t V .(a) (b) t1 Figure 3. 19 If we assume D does not turn on. requiring that V out rise and D1 1 turn on.54 (a).

3. C1 carries a voltage equal to V and transfers the in ut change to the out ut.2V or +2V for an in ut sinusoid varying between .2V or +2V may be roduced. Figure 3. 3. C 1 directly transfers the in ut change to the out ut for the entire ositive half cycle. the diode turns off. then a constant out ut equal to . Now.57(a) e xem li es this conce t.cls v. 3. 2007 at 13:42 108 (1) 108 Cha .30(a). since the eak detector “loads” the rst stage when D2 tur ns on. at which oint the direction of the current through C1 and D1 must change. C1 V in X D1 D2 C 2 Vout V out V t V in t1 C1 V in C2 C1 V in C1 V in C2 t2 t3 t4 t5 t V in C2 C1 C 2 V V in C2 C1 Figure 3. 2006] June 30. reaching a eak value of +2V . the out ut tracks the in ut but with a level s hift of +V . the voltage across C1 remains equal to Vin un til t = t2 .30(a)] . After t = t1 . Fig. 3 Diode Models and Circuits As Vin rises from zero. V 2 is 1 V more ositive than its left late at ... i. the in ut tends to ush negative charge into C1 .57 Voltage doubler circuit and its waveforms. Of course. Thus.56 with the eak detector of Fig. turning D1 off. We sur mise that if these circuits are followed by a eak detector [e. attem ting to lace ositive charge on the left late of C1 and hence draw negative charge from D1 .V and +V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution Exercise Re eat the above exam le if the right late of t = 0. C1 We have thus far develo ed circuits that generate a eriodic out ut with a eak value of . turning D1 on and forcing Vout = 0.g. we must still analyze this circuit carefully and determine whether it ind eed o erates as a voltage doubler.e. combining the circuit of Fig. As a result.

In this case. and C1 = C2 . . As Vin falls below zero. D1 turns on. zero initial conditions across C1 and C2 .We assume ideal diodes. the analysis is sim li ed if we begin with a negative cycle.

cls v.) As a result. with the right late of C1 oating. VX tracks the change at the in ut. our objective was to generate an out ut equal to 2V rather than V . 2 = 2V : . In other words.57. Note at t = t2 . Now. the in ut begins to rise and tends to de osit ositive charge on the left late of C1 . D2 turns off. allowing C1 to charge to . For t t1 .20 Thus. 2006] June 30. Vout increases from +V to +V + V =2 as Vin goes from 0 to +V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.112) 1 Vout = V 1 + 1 + 4 + 2 = V 1 1.V to 0.. for t t1 . After this time. turning D1 off and yi elding the circuit shown in Fig. D2 turns on at t = t5 . the out ut continues to rise by V . 2 (3. Thus. At t = t 1 . in each in ut cycle. the voltage across C1 reaches . forming a c a acitive divider again. both D1 and D2 are off. As is evident from the foregoing a nalysis. the circuit reduces to a sim le ca acitive divider that follows Eq. r eaching +V as Vin goes from . VX and Vout begin from zero. (If D2 remains off. maintaining Vout at +V . What ha ens after t = t2 ? Since Vin begins to fall and tends to draw charge from C1 . 3. 3. we ostulate that VX also tends to increase (from zero). As Vin b egins to rise again. D1 turns on again.e. the out ut change is equal to half of the in ut change. 2007 at 13:42 109 (1) Sec. V =4. (3. then C1 sim ly transfers the change in Vin to nod e X .V at t = t4 . a change of 2V in Vin a ears as a change equal to V in VX and Vout . from t1 to t2 . Thus. At this oint. How does D2 behave in this regime? Since Vin is now rising. The out ut has now reached 3V =2. i. the voltage across C1 is zero because both Vin and Vout are equal to +V .111): because C1 = C2 . For t t2 . VX = Vin . D2 remains off and Vout = 0. a roaching a nal value of Vout = 1 Vin . etc. and each ca acitor holds a constant voltage. remain equal. raising VX and hence turning D2 on. falling to zero at t = t3 . and vary sinusoidally but with an am litude equal to V =2. The reader may wonder if some thing is wrong here. But atience is a virtue and we must continue the transient analysis. V =2. turn ing D2 on.V . Since the voltage across C1 is zero.5 A lications of Diodes 109 inning node X to zero. D1 turns off and D2 remains off because VX = 0 and Vout = + V ..

114) (3. i.. noting that D1 and C1 carry equal cu rrents when D1 is forward biased.e.(3. re eating the same behavio r in subsequent cycles.113) (3.21 For 0 t t1 . immediately after t = 0. 3. and writing the current as ID1 = .115) The reader is encouraged to continue the analysis for a few more cycles and veri fy this trend. we construct the lot shown in Fig.58(b). the reader is encouraged to assume otherwise (i. 21 As usual. Using the diagram in Fig. From t = t1 to t = t3 . I D .58(a). 1 remains off) and arrive at a con icting result. Sketch the current through D1 in the doubler circuit as function of time.e.. Exam le 3. D1 conducts and the eak current corres onds to the maximum slo e of Vin .C1 dVin =dt. 3. D1 denotes the current owing from the anode to the cathode. the diode remains off.36 Solution 20 As always.

where I1 draws a constant current.59(a) as a candidate for shif ting the level down by VD.on acro ss D1 . 2007 at 13:42 110 (1) 110 V in t1 C1 V in C2 C1 V in C1 V in C2 Cha .on . 2006] June 30.on . 3. 2VD.5 Diodes as Level Shifters and Switches In the design of electronic circuits.59(b). . we may need to shift the average level of a signal u or down because the subse quent stage (e. we consider the circuit shown in Fig. VD..58 Diode current in a voltage doubler. the diode current remains unknown and de endent on the next stage. 3.cls v. a diode can be viewe d as a battery and hence a device ca able of shifting the signal level.5. 22 The diode is drawn vertically to em hasize that Vout is lower than Vin . 3. Exercise Plot the current through D2 in the above exam le as a function of time. To alleviate this issue we modify the circuit as de i cted in Fig.60 shows the result.22 If the current ulled by the next stage is negligible (or at least con stant). Also. we This section can be ski ed in a rst reading.on . Figure 3. Design a cir cuit that shifts u the dc level of a signal by 2VD. establishing VD. to obtain a shif t of lace two diodes in series. Sustaining a relatively constant voltage in forward bias.on . Vout is sim ly lower than Vin by a constant amount.37 Solution To shift the level u . 3 Diode Models and Circuits t4 t5 t2 t3 t V in C2 C1 C 2 V V in C2 C1 I D1 t1 t2 t3 t4 t Figure 3. we a ly the in ut to the cathode. Exam le 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an am li er) may not o erate ro erly with the resent dc level . In our rs t attem t.g. However.

As the in ut waveform com letes a negative excursion and exceeds Vin1 at t = t2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For exam le.61(a) to “s am le” Vin across C1 and “freeze” the value when S1 turns off.61(c) . so does D1 . Vout remains less than VD. 3. The assum tion t hat D1 turns off holds only if C1 draws no current from D1 .on .61(b)].on Vout 2 V D.on (a) (b) t Figure 3.on .60 Positive voltage shift by two diodes.cls v. charging C1 with the in ut (in a mann er similar to a eak detector). D1 turns on for ¡ . 3. many a lications em loy the to ology shown in Fig. only if Vin .on Vout I1 Vin Vout V D.59(b) can be transformed to an electronic swit ch.e.59 (a) Use of a diode for level shift. Vout tracks Vin exce t for a level shift equal to VD. 2006] June 30.on Vin Vin t Figure 3. VCC I1 Vout 2 V D. Now consider the case illustrated in Fig. evidently disconnecting C1 from the in ut and freezing the v oltage across C1 .on .5 A lications of Diodes 111 Vin D1 Vin Vout D1 V D. When I1 turn s off. VD . Exercise What ha ens if I1 is extremely small? The level shift circuit of Fig. even though I1 is off. 3. 3. That is. allowing C1 to store a value equal to Vin1 . Let us re lace S1 with the level shift circuit and allow I1 to be turned on and off [Fig.. where I1 turns off at t = t1 . i. (b) ractical im lementation. 3. the diode is forward biased again. 2007 at 13:42 111 (1) Sec. If I1 is on. We used the term “evidently” in the last sentence because the cir cuit’s true behavior somewhat differs from the above descri tion.

When I1 and I2 turn off. the circuit is modi ed as shown in Fig. where the back to back diodes fail to conduct for any value of Vin . and Vout = VX + VD2 = Vin if VD1 = VD2 . 3. Vout tracks Vin with no le vel shift. VD1 . where D2 is inserted between D1 and C1 .61(d). VX = Vin . With both I1 and I2 on. the diodes o erate in forward bias. ¡ ¡ . In other words.art of the cycle. To resolve this issue. Thus. the two diodes and the two cur rent sources form an electronic switch. the reby isolating C1 from the in ut. the circuit reduces to that in Fig. 3. Vout . and I2 rovides a bias current for D2 .61(e).

S eci cally. 2007 at 13:42 112 (1) 112 Cha . 3 Diode Models and Circuits Vin Vin V in Vout C1 CK I1 D1 Vout C1 Vin D1 Vout I1 C1 CK Vout D 1 turns on.62 Feedthrough in the diode switch. (e) eq uivalent circuit when 1 and 2 are off.61 (a) Switched ca acitor circuit. (a) (b) (c) t1 t2 t VCC CK Vin C1 CK I1 I1 Vout Vin C1 Vout (d) (e) Figure 3. 2006] June 30. Study the effect of this ca acitance on the o eration of the above circuit. (d) more com lete circuit.54(b) an d assuming Cj 1 = Cj 2 = Cj . ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution Figure 3. I I Exam le 3. suggesting that the conduction of the in ut through the junction ca acitances di sturbs the out ut.cls v. D 1 turns off. 3. we have Vin C j1 C j2 C1 Vout Figure 3. (b) realization of (a) using a diode as a switch.38 Recall from Cha ter 2 that diodes exhibit a junction ca acitance in reverse bias .62 shows the equivalent circuit for the case where the diodes are off. invoking the ca acitive divider of Fig. (c) roblem of diode conduction.

116) Exercise Calculate the change in the voltage at the left late of Cj 1 (with res ect to g round) in terms of . (3. C1 must be suf ciently large.C Vout = C =2j =2C Vin : j + 1 To ensure this “feedthrough” is small.

and forward bias. It also contains a small number of free electrons at room tem erature. 3. 2007 at 13:42 113 (1) Sec. n junctions break down. a constant voltage model may be used in some cases to estimate the circuit’s res onse with less math ematical labor.63. The electric eld in the de letion results in a built in otential across the region equal to kT=q lnNA ND =n2 . a “hole” is left behind. U on formation of the n junction. Problems = 800 mV for the constant voltage diode model. The bandga energy is the minimum energy required t o dislodge an electron from its covalent bond. i Under reverse bias. 3. Plot the I/V characteristic of the circuit shown in Fig. The n junction c an be considered in three modes: equilibrium. the junction carries a current that is an ex onential function of the a lied voltage: IS ex VF =VT . This conditio n is called equilibrium. The diffusion current density is ro ortional to the gradient of the carrier concentration and given by Jtot = q Dn d n=dx . assume VD. 1. When an electron is freed from a covalen t bond.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. semiconductors are “do ed” with certain im urities. and a “de letion region” is formed. ¡ In the following roblems. For exam le. reverse bias.on ¡ ¡ ¡ ¡ ¡ . 1 . 3. in an n ty e material. De ending on the structure and do ing levels of the device. The electric e ld created in the de letion region eventually sto s the current ow. For do ed or undo ed semiconductors. shar gradients of carrier densities across the junction result in a high current of electrons and holes. n ND i and hence n2 =ND .6 Cha ter Summary 113 Vin . Under forward bias. n = n2 . D d =dx. “Zener” or “avalanche” breakdown may occur. A n junction is a iece of semiconductor that receives n ty e d o ing in one section and ty e do ing in an adjacent section. For exam le. As the carriers cross . i Char ge carriers move in semiconductors via two mechanisms: drift and diffusion. addition of hos horus to silicon increases the number of free electrons because hos horus contains ve electrons in its last orbital. cond ucting a very high current. The drift current density is ro ortional to the electric eld and the mobility of the carriers and is given by Jtot = q n n + E . To increase the number of free ca rriers. the junction carries negligible current and o erates as a ca acitor. they leave ionized atoms behind.6 Cha ter Summary Silicon contains four atoms in its last orbital. ty ically in the range of 7 00 to 800 mV.cls v. Since the e x onential model often makes the analysis of circuits dif cult. The ca acitance itself is a function of the voltage a lied across the device. 2006] June 30. Under a high reverse bias voltage.

1 V and VB = +1 V. 3. For the circuit de icted in Fig. 3 IX R1 D1 Ideal Diode Models and Circuits VX Figure 3. If the in ut in Fig.1 V and VB = +1 V.63 is ex ressed as VX = V0 cos !t.64 4. 3. 3. 9. 2006] June 30. .66 7.63 2. 2007 at 13:42 114 (1) 114 Cha . 3. Assume VB IX R1 VX VB D1 Ideal 0. If in Fig.64 for two cases: VB = . VX = V0 cos !t.cls v. In the circuit of Fig. lot IX an d IR1 as a function of VX for two cases: VB = . 3.67. 8. 3. R1 VB Figure 3.1 V and IX R1 VX D1 Ideal VB Figure 3.1 V IX VX D1 Ideal VB = +1 V. Assume VB = 2 V. lot IX and IR1 as a function of VX fo r two cases: VB = . lot the current owi ng through the circuit as a function of time.1 V and VB = +1 V. I D1 Figure 3. 3. lot IX as a function of time for two cases: VB = . 3.64.66. lot IX as a function of VX for two cases: VB = . 3. Plot IX and ID1 as a function of VX for the circuit shown in F ig.65 and VB = +1 V.69 using an ideal model for the diodes. Plot the in ut/out ut characteristics of the circuits de icted in Fig.68.65. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Plot IX as a function of VX for the circuit shown in Fig. For the circuit de icted in Fig. 5.

.

67 IX R2 I R1 VX R1 D1 VB Ideal Figure 3.6 Cha ter Summary IX R2 VX I R1 R1 D1 VB Ideal 115 Figure 3. 2007 at 13:42 115 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.69 . 3.68 R1 D1 VB (a) (b) D1 Vout V in VB V in VB R1 D1 (c) V in R1 Vout Vout D1 R1 VB (d) R1 Vout V in VB V in D1 Vout (e) Figure 3. 2006] June 30.

lot the out ut of each circuit in Fig. For the circuits illustrated in Fig . lot the out ut of each circuit in Fig. 11. Plot Vout as a function of Iin for t he circuits shown in Fig.10.71. 14. 12.70 using an ideal model for the diodes. Assume a constant vo ltage model and a relatively large I0 .71. 9 as function of time. Assume an ideal diode model. Re eat Problem 9 with a constant voltage diode model.70 as a funct ion of time. Assuming a constant voltage diode mod el. Re eat Problem 12 with a constant voltage diode model. 13. 3. Use an ideal diode model.72. lot the current owing through R1 as a function of Vin . Assume a constant voltage diode model. lot Vout as a function of Iin for the circuits shown in Fig. 16. Plot the in ut/out ut characteristics of the circuits shown in Fig. 3. 17. ¡ ¡ ¡ ¡ ¡ ¡ . 3. 3.71. 18. Assuming the in ut is ex re ssed as Vin = V0 cos !t. 3. lot Vout as a function of time if Iin = I0 cos !t. 15. If the in ut is gi ven by Vin = V0 cos !t. 3. In t he circuits of Fig. Assume a constant voltage diode model.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 116 (1) 116 R1 V in VB R1 D1 VB (a) (b) Cha .70 I in R1 D1 Vout I in .cls v. 2006] June 30. 3 Diode Models and Circuits D1 VB D1 Vout V in Vout V in R1 Vout (c) VB R1 D1 (d) D1 R1 VB (e) V in Vout V in Vout Figure 3.

Assume a constant voltage diode model.73.71 I in R1 D1 VB (a) Vout I in D1 R1 VB (b) Vout I in D1 VB Vout R1 (c) Figure 3.R1 D1 VB (b) Vout (a) I in D1 R1 VB Vout I in D1 (d VB Vout R1 (c) Figure 3. 3. 22. Assume a constant voltage diode model. 3. 21. 3. 20.73. lot Vout as a function of Iin assuming a constant voltage model for the diodes. assume Iin = I0 cos !t. For the circuits show n in Fig. Plot the in ut/out ut characteristic of the circuits illustrated in Fig. 3. 23. 3. Plot Vout as a function of time using a constant voltage diode model.72. Plot the current owing through R1 in the circuits of Fig.72 as a function of Iin .72 19.74 assuming a co ¡ ¡ ¡ ¡ . In the circuits de icted in Fig. Plot the current owing through R1 as a function of Iin for t he circuits of Fig. where I0 is relatively large.

nstantvoltage model. .

2007 at 13:42 117 (1) Sec.cls v.6 Cha ter Summary 117 D1 I in R1 D2 (a) Vout I in R1 D1 (b) D2 Vout I in R1 D1 (c) D2 Vout I in R1 D1 D2 Vout I in R1 D1 D2 D1 Vout I in D2 R1 (f) Vout (d) (e) D1 I in D2 R1 (g) . 2006] June 30. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

3.77 assu ming a constantvoltage model and VB = 2 V. ¡ ¡ ¡ . 26. 3. Plot the in ut/out ut characteristic of the circuits illustrated in Fig. 28. Plot the currents owing through R1 and D1 as a function of Vin for the circui ts of Fig.73 D1 R1 R2 D1 R1 Vout V in R2 Vout V in (a) (b) Figure 3.D1 Vout I in D2 R1 (h) Vout Figure 3. Assume constant voltage diode model. 29.75. Plot the currents owing through R1 and D1 as a function of Vin for the circuits of Fig. 3.76 assuming a con stantvoltage model. 25.74 24. Pl ot the in ut/out ut characteristic of the circuits illustrated in Fig.76. Assume constant voltage diode model. 3.74. 3. Plot the in ut/out ut characteristic of the circuits illustrated in Fig. Plot the currents owing through R1 and D1 as a function o f Vin for the circuits of Fig. 3.75 assuming a constantvolta ge model. Assume constant voltage diode model. 27.

cls v. 3 D 1 VB Vout V in R1 Diode Models and Circuits Vout R2 (b) D1 V in R1 VB Vout R2 (c) R1 V in D1 VB Vout R2 (d) Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75 V in D1 R1 Vout D2 R2 V in D1 R1 Vout D2 R2 (a) (b) D1 V in R1 D2 R2 Vout V in D1 D2 R1 Vout R2 (d) D1 V in R1 D2 Vout R2 (e) (c) Figure 3. 2006] June 30. 2007 at 13:42 118 (1) 118 D1 V in R1 R2 VB (a) Cha .76 .

80 for an initial cond ition of +0:5 V across C1 . calculate the change in Vout if Iin changes from 3 mA to 3. lot the out ut waveform of the circuit de icted in Fig.on 800 mV for each diode. 33.81. Beginning with VD.79.on 8 00 mV for each diode. 3. 3. determine the change in the curren t owing through the 1 k resistor in each circuit. Assume V = 5 V. 32. Re eat Problem 34 for the circu it shown in Fig. 3. Beginning with VD.77. calculate the ri l e am litude if the frequency is 60 Hz.30. For a 1000 F smoothing ca acitor. In Problem 32. determine the change in Vout if Vin changes from +2:4 V to +2:5 V for the circuits shown in Fig. 36. 31.78. Plot the currents owing through R1 and D1 as a function of Vin for the circui ts of Fig. Su ose the recti er of Fig. 34. 3. 3. 35.32 drives a 100 load wi th a eak voltage of 3. 3. Assume constant voltage diode model. ¡ ¡ ¡ ¡ . Assuming Vin = V sin !t.5 V.1 mA in the circuits of Fig.

A 3 V ada tor using a half wave recti er must su ly a current of 0. 2006] June 30. 2007 at 13:42 119 (1) Sec.cls v.6 Cha ter Summary R1 V in D1 VB D2 R2 (a) (b) 119 D1 Vout V in D1 VB R2 R1 Vout R1 V in D1 R2 D2 VB (c) (d) Vout V in D1 R1 Vout D2 VB R2 Figure 3.77 V in D1 Vout R 1 = 1 kΩ V in D1 Vout R 1 = 1 kΩ D2 (a) (b) V in D1 R1 1 kΩ Vout D2 V in R1 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3. For a frequency of 60 Hz. 39. Plot the v ¡ ¡ ¡ . 3.5 A with a maximum ri le of 300 mV. Draw the out ut waveform with and without the load ca acitor and ex lain why the circuit does not o erate as a recti er. 38. com ute the minimum require d smoothing ca acitor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.78 37. Assume the in ut and out ut grounds in a full wave re cti er are shorted together.

40.82. Plot the in ut out ut characteristic assuming an id eal diode model and ex laining why the circuit does not o erate as a full wave r ecti er. Assume a constant voltage diode model and VD VD. ¡ ¡ ¡ ¡ ¡ ¡ . 41. Su ose the negative terminals of Vin and Vout in Fig.oltage across each diode in Fig. Ex lain what ha ens. 3 . determine the ri le am litude with a 1000 F smoothing ca acitor and a load resistance of 30 . A full wave recti er is driven by a si nusoidal in ut Vin = V0 cos !t. 42. While constructing a full wave recti er. where V0 = 3 V and ! = 2 60 Hz. 3. Assuming VD. a student mistakenly has swa ed the terminals of D3 as de ic ted in Fig.38(b) are shorted together.38(b) as a function of time if Vin = V0 cos ! t. 3.on = 80 0 mV.on .

2006] June 30.5 V V in Figure 3.79 V in D1 Vout C1 0.81 D2 Vin D4 Vout RL .5 V Figure 3.cls v. 2007 at 13:42 120 (1) 120 D1 Vout I in R 1 = 1 kΩ Cha . 3 Diode Models and Circuits D1 Vout I in R 1 = 1 kΩ D2 (a) (b) D1 I in R1 1 kΩ R1 Vout D2 I in 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3.80 D1 Vout C1 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

43 so as to a reciate the regulation rovided by the diodes. 3. fin = 60 Hz.82 43. 3. C1 = 100 F. neglect the lo ad. what is the change in the total voltage across the three diodes? Assume R1 is much greater than 3rd . a cur rent of 20 mA. estimate the ri le am litude across C1 . (b) Using the small signal model of the diodes. 44.43.D3 D1 Figure 3. determine the ri le am litude across the load . we estimate the ri le seen by the load in Fig. ¡ . and the eak voltage roduced by t he transformer is equal to 5 V.on 800 mV. Also. R1 = 1000 . In this roblem. (a) Assuming R1 carries a relatively constant cu rrent and VD. For sim licity. If the load current increases to 21 mA. the diodes carry a current of 5 mA and the load. Su ose in Fig.

In the limiting circuit of Fig. 3. 52. (a) Using hand calculations. Vout +2V −2V +2V −2V 0. and VD. ¡ ¡ ¡ ¡ ¡ . The half wave recti er of Fig.V0 .1:9 V and a ositive threshold of +2:2 V. 47. 3.86 must deliver a current of 5 mA to R1 for a eak in ut level of 2 V. 51. How should t he in ut out ut characteristic be modi ed so that the out ut becomes a better a r oximation of a sinusoid? SPICE Problems In the following roblems. In the circuit of Fig. Assume the in ut ea k voltage is equal to 5 V.51. and other com onents. 2006] June 30. 3.on 800 mV.88 is driven by a 60 Hz sinusoid in ut with a eak am litude of 5 V. R 1 = 500 and R2 = 1 k .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V in Figure 3. Also. lot the current owing through R1 as a function of Vin . Using ideal diodes and other com onents. (The value of resistors is not unique. lot the currents owing through D1 and D2 as a function of time if the in ut is given by V0 cos !t and V0 VD. construct the circuit. the maximum allowable current through each diode is 2 mA. 3. 3.5 V in Figure 3.16 A. Using the transient analysis in SPICE.VD. istic.5 0.2 V Vin +2 V. 2007 at 13:42 121 (1) Sec. 3. ideal diodes. Plot the out u t waveform and note that it is a rough a roximation of a sinusoid.85.87. 3. construct a circuit that rovides such a characterVout +2V −4 V −2V +2V −2V 0.5 +4V 0.on + VB 1 and . Use SPICE to construct the in ut/out ut characteristic fo r . We wish to design a circuit that exhibits the in ut/o ut ut characteristic shown in Fig.51 for a negat ive threshold of . 50.83. 46. 3.) Su ose a triangular waveform is a lied to the characteristic of Fig. 3.83 48. “Wave sha ing” a lications require the in ut/out ut characteristic illustrated in Fig. VB 2 .6 Cha ter Summary 121 45.84.84 as shown in Fig. Design the limiting circuit of Fig. T he recti er shown in Fig.on . Using 1 k resistors. 3. determine the requi red value of R1 . assume IS = 5 10.cls v. (b) Verify the result by SPICE.84 49.

.

54. The circuit shown in Fig. (c) Com ute the heaviest load (smallest RL ) that the circ uit can drive while maintaining a ri le less than 200 mV . The circuit of Fig.2 V Vin +2 V and determine the maximum in ut range across which jVin .87 D1 Vout V in 1 F 100 Ω Figure 3. (b) Determine the eak curr ent owing through D1 . Using the dc an alysis in SPICE to lot the in ut/out ut characteristic for 0 Vin 4 V.88 (a) Determine the eak to eak ri le at the out ut.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 3.5 +4V 0. 2007 at 13:42 122 (1) 122 Cha . determine the values of VB 1 and VB 2 such that ¡ ¡ . 3 Diode Models and Circuits Vout +2V −4 V −2V +2V −2V 0.Vout j 5 mV.5 V in V in t Figure 3. 53.90 can rovide an a roximation of a si nusoid at the out ut in res onse to a triangular in ut waveform. 2006] June 30. 3.86 R1 D2 D1 R2 in Vout Figure 3.85 D1 Vout V in R1 Figure 3. Plot the in ut/out ut characteristic for .89 is used in some analog circuits.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 Cha ter Summary VCC = +2.cls v.90 .5 V Figure 3.89 the characteristic closely resembles a sinusoid. 3. 2 kΩ Vout D2 V B2 Vout 4V V in (a) (b) V in D1 V B1 Figure 3.5 V 1 kΩ 123 D2 V in D4 D3 Vout D1 1 kΩ VEE = −2. 2006] June 30. 2007 at 13:42 123 (1) Sec.

we analyze the struc ture and o eration of bi olar transistors. re aring ourselves for the study of circuits em loying such devices.2) (4. 2007 at 13:42 124 (1) 4 Physics of Bi olar Transistors The bi olar transistor was invented in 1945 by Shockley.1 . Since V1 = Vin and Vout = . subsequently re lacing vacuum tubes in electronic systems a nd aving the way for integrated circuits. Let us now const ruct the circuit shown in Fig. the bi olar transistor can be viewed as a voltage de enden t current source.3) ¡ ¡ . is de ned as AV = Vout Vin = . Our object ive is to demonstrate that this circuit can o erate as an am li er. AV . 2006] June 30. Consider the voltage de ende nt current source de icted in Fig. Voltage−Controlled Device as Am lifying Element Structure of Bi olar Transistor O eration of Bi olar Transistor Large−Signal Model Small−Signal Model 4. 124 (4. where I1 is ro ortional to V1 : I1 = KV1 . For exam le.1(b). and develo an equivalent mod el that can be used in circuit analysis and design. Brattain. The am li cation factor or “voltage gain” of the circuit.KRLVin : (4. an in ut voltage of 1 V yields an out ut current of 1 mA. 4. The negative sign in dicates that the out ut is an “inverted” re lica of the in ut circuit [Fig. Figure 4 illustrates the seq uence of conce ts introduced in this cha ter. if KRL 1.KRL.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. i.e. 4.cls v. we aim to understand the hysics of the transistor. Vout is an am li ed re lica of Vin .1(b)].1) Interestingly. Note that K has a dimension of resistance.1(a). Following the same thought rocess as in Cha te r 2 for n junctions. derive equations that re resent its I/V characteristics. we have Vout = .1 .1 General Considerations In its sim lest form. and Bardeen a t Bell Laboratories. where a voltage source Vin controls I1 an d the out ut current ows through a load resistor RL . then the circuit am li es the in ut. We rst show how such a current source can form an am li er and he nce why bi olar devices are useful and interesting. with K = 0:001 . 4.. In this cha ter. roducing Vout .RL I1 .

thus directly a ffecting the gain. Exam le 4. (b) sim le am li er.cls v.1 Consider the circuit shown in Fig.1 General Considerations V in V t 125 V1 I1 KV1 V in V1 I1 KV1 R L Vout V out t (a) (b) Figure 4. Note that K signi es how strongly V1 controls I1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4.1 (a) Voltage de endent current source. V in r in V1 I1 KV1 ¡ ¡ K R L V . 2006] June 30. Determine the voltage gain of the cir cuit. 2007 at 13:42 125 (1) Sec. and de ends on both the characteristics of the controlled current source and the load resistor. where the voltage controlled current sou rce exhibits an “internal” resistance of rin . 4.2.

¡ ¡ ¡ ¡ ¡ ¡ . W e will see in Section 4. this model can be a roximated by that in Fig. This oint roves useful in our analyses later. the voltage gain remai ns unchanged. As three terminal devices.1(a). bi olar transistors make the analysis of circuits more dif cult. as we develo our understanding of the transistor’s o eration. Fortunately. With three terminal elements. Bi olar transistors are an exam le of such current so urces and can ideally be modeled as shown in Fig. we di scard some of these current and voltage combinations as irrelevant.4. Note that the device cont ains three terminals and its out ut current is an ex onential function of V1 . Having dealt with two terminal com o nents such as resistors. we are accustomed to a oneto o ne corres ondence between the current through and the voltage across each device .4 that under certain conditions.2 Voltage de endent current source with an internal resistance rin . The foregoing study reveals that a voltage controlled current source can indeed rovide signal am li cation. and diodes in elementary circuit analysis and the revious cha ters of this book. 4. Solution Exercise Re eat the above exam le if rin = 1. ca acitors.RL Vout Figure 4. arriving at a com lex set of equations.3. Since V1 is equal to Vin regardless of the value of rin . one may consider the current and voltage between every two terminals. on the other hand. 4. inductors. thus obtaini ng a relatively sim le model.

VB .” the “emi tter. and the voltage differen ces by VBE . and VC .” As ex lained later. in reality. For exam le.4 (a) Structure and (b) circuit symbol of bi olar transisto r.cls v. 2006] June 30. then t his junction is forward biased. We readily note from Fig. VCB .” and the “collector. Collector Collector (C) n Base VCB Base (B) n Q 1 VCE VBE Emitter (E) (b) Emitter (a) Figure 4. if the base is more ositive than the emitter.4(b) . 4 Physics of Bi olar Transistors 1 3 V1 V1 VT 2 Figure 4. The transistor is labeled Q1 here. 4. We denote the terminal voltages by VE . VBE 0. and VCE . th ¡ ¡ I S ex .2 Structure of Bi olar Transistor The bi olar transistor consists of three do ed regions forming a sandwich. 4. The circuit symbol for the n n transistor is shown in Fig.4(a) is an exam le com rising of a layer sandwiched between two n r egions and called an “n n” transistor. 4.3 Ex onential voltage de endent current source. The three terminals are called the “base. the emitter “emits” charge carriers and th e collector “collects” them while the base controls the number of carriers that make this journey. While this sim le diagram may suggest that the d evice is symmetric with res ect to the emitter and the collector. 2007 at 13:42 126 (1) 126 Cha .4(a) that the device contains two n junction diodes : one between the base and the emitter and another between the base and the coll ector.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. Shown in Fig.

about 100 A in modern integrated bi olar tran sistors. Fortun ately. the electron ex eriences the elec tric eld and is ra idly ¡ ¡ . As mentioned in the revious section. We will also see that ro er o eration requires a thin base region. Consider the reverse biased junct ion de icted in Fig. only one of these eight combinations nds ractical value and comes into ou r focus here. What ha ens to this electron ? Serving as a minority carrier on the side. VBE . it is instructive t o study an interesting effect in n junctions..5(a) and recall from Cha ter 2 that the de letion region sustains a strong electric eld. e. VBC . leading to 23 ossibilities for the terminal voltages of the transistor. 4.e dimensions and do ing levels of these two regions are quite different. E and C cannot be interchanged.g. 4. Before continuing with the bi olar transistor. In othe r words. For the de vice in Fig. the ossible combinations of volt ages and currents for a three terminal device can rove overwhelming.4(a). and VCE can assume ositive or negative values. Now su ose an electron is somehow “injected” from ou tside into the right side of the de letion region.

6 (a) Bi olar transistor with base and collector bias voltages. 2007 at 13:42 127 (1) Sec. (b) sim listic view of bi olar transistor.8 V (a) D2 V CE = +1 V I1 (b) D1 Figure 4. the base voltage is set to about 0. Under these conditions. e. VBE . with the emitter conn ected to ground.g. We may b e tem ted to sim lify the exam le of Fig. 4.8 V and the collector voltag e to a higher value. it indeed acts as a voltage controlled current sour ce. 2006] June 30.2 V. We begin our study with the assum tion that the base emi tter junction is forward biased (VBE 0) and the base collector junction is rever se biased (VBC 0). we say the device is biased in the “for ward active region” or sim ly in the “active mode.cls v. More s eci cally.3 O eration of Bi olar Transistor in Active Mode 127 swe t away into the n side. The base collector junction theref ore ex eriences a reverse bias of 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The ability of a reverse biased n junction to ef cien tly “collect” externally injected electrons roves essential to the o eration of the bi olar transistor. I2 V CE = +1 V V BE = +0.5 Injection of electrons into de letion region.3 O eration of Bi olar Transistor in Active Mode In this section.8 V V BE = +0. we intend to show that (a) the current ow from the emitter to the collector can be viewed as a current source tied between these two terminal s.. aiming to rove tha t.” For exam le. under certain conditions. Electron injected e n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + E VR Figure 4. and (b) this current is controlled by the voltage difference between the base and the emitter. Let us now consider the o eration of the transistor in the active mode. we analyze the o eration of the transistor.6(a) to the equivalent circuit shown ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ .6(a)]. 1 V [Fig. 4. 4. 4.

4.6(b). After all. To understand why the transistor cannot be mo deled as merely two back to back diodes. we should antici ate current ow fr om the base to the emitter but no current through the collector terminal. the transistor would not o erate as a voltage controlled current sourc e and would rove of little value. This view im lies th at D1 carries a current and D2 does not. we must examine the ow of charge inside the device. it a ears that the bi olar transistor sim ly consis ts of two diodes sharing their anodes at the base terminal. i. Were t his true. bearing in mind that the base region is very ¡ ¡ ¡ .in Fig..e.

For ro er transistor o eration. re quiring that the emitter do ing level be much greater than that of the base (Cha ter 2). Figures 4. the electrons are swe t into the collector region (as in Fig.” We therefore observe that the reverse biased collectorba se junction carries a current because minority carriers are “injected” into its de l ¡ ¡ ¡ ¡ n − e + + h n V CE = +1 V + + h − e n ¡ ¡ .7 (a) Flow of electrons and holes through base emitter junction. 4 Physics of Bi olar Transistors thin. 2007 at 13:42 128 (1) 128 Cha . Figure 4. where the su erscri t em h asizes the high do ing level.7(a) summarizes our observations thus far .8 V (a) (b) De letion Region V CE = +1 V V BE = +0. 4.5. n V CE = +1 V V BE = +0. (b) el ectrons a roaching collector junction.5) and absorbed by the ositive battery terminal.7(b) and (c) illustrate th is effect in “slow motion. 4. 2006] June 30. most of the electrons reach the edge of the collector base de letion region. be ginning to ex erience the built in electric eld. Consequently. What ha ens to electrons as they enter the base? Since the base region is thin. electrons ow from the em itter to the base and holes from the base to the emitter.cls v. Since the base emitter junction is forward biased.8 V + h − e n + De letion Region V BE = +0. as illustrated in Fig. (c) electrons assing through collector junction. the former current com onent must be much greater than the latter.8 V n (c) Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. indicating that the emitter injects a large number of electrons into the base while receiving a small number of holes from it. we denote the emitter region with n+ . Thus.

how large is the base current? O erating as a moderate conductor. we recognize that the density of electrons at x = x1 is very high. i. In fact. to the collector while drawing a small current of holes through the base term inal. ¡ . (2) 1 This assum tion sim li es the analysis here but may not hold in the general case . how do electrons travel throu gh the base: by drift or diffusion? Second. In the active mode. 4.29 for the emitterbase junction [ Fig.etion region. it allows most of the eld to dro across the base emitter de letion layer.1 leaving diffusion as the rinci al mechanism for the ow of electrons injec ted by the emitter.. an n n bi olar transistor carries a large number of electrons from the emitter. Thus. the drift current in the base is neglig ible. First. how does the resulting current de en d on the terminal voltages? Third. two observations directly lead to the necessity of diffusion: (1) redrawing the diagram of Fig.e. as ex lained for n junctions in Cha ter 2.8(a)]. through the bas e. Let us summarize our thoughts. 2. We must now answer several questions. the base region sustains but a small electric eld.

cls v.8(b) is swe t away. 2007 at 13:42 129 (1) Sec. the density of electrons falls to zero at this oint. 2006] June 30.3 O eration of Bi olar Transistor in Active Mode 129 since any electron arriving at x = x2 in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. the electron density in t he base assumes the ro le de icted in Fig. roviding a gradient for the d iffusion of electrons. (b) zero el ectron density near collector. ¡ n . As a result.8 (a) Hole and electron ro les at base emitter junction. 4.8(c). n x V CE Reverse Biased x x2 V CE e V BE x1 e V BE n + h Forward Biased (a) n + (b) n x x2 x1 V CE e V BE + n Electron Density (c) Figure 4. (c) electron ro le in base. 4.

8(c) given by Eq. the base emitter junction exhibits a high concentration of electrons at x = x1 in Fig. (2. 1 V0 T ex V BE = NB ex VV .3. 1 : n2 T i ¡ ¡ .1 Collector Current We now address the second question raised above and com ute the current owing from the collector to the emitter.96): BE nx1 = NE ex VV .4.2 As a forward biased dio de. 4.

(4.4) .

i A lying the law of diffusion [Eq. (2. In this cha ter . res ective ly. electrons go from the emitter to the collector. we assume VT = 26 mV. NE and NB denote the do ing levels in the emitter and the base. and we have utilized the relationshi ex V0 =VT = NE NB =n2 . Wnx1 B (4. .5) Here.6) = qDn 0 .T (4. th e conventional direction of the current is from the collector to the emitter.7) 2 In an n n transistor. we determi ne the ow of electrons into the collector as Jn = qDn dn dx (4. .42)]. Thus.

2007 at 13:42 130 (1) 130 Cha . 1 : B WB T In analogy with the diode current equation and assuming ex VBE =VT . and changing the sign to obtain the conventional current.cls v. 4 Physics of Bi olar Transistors where WB is the width of the base region. 2006] June 30. substituting for nx1 from (4. we obtain 2 E BE IC = ANqDn ni ex VV .5).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. AE . Multi ling this quantity by the emitte r cross section area.

we write (4. IX I C1 Q1 V1 V2 (a) Exam le 4.9) im lies that the bi olar transistor indeed o erates as a voltage controlled current source.9) E IS = ANqDn ni : W B B 2 (4.10) Equation (4.” Determine the current IX in Fig.9 (a) Two identical transistors drawing current from having twice t he area. We may alter natively say the transistor erforms “voltage to current conversion. roving a good candidate for am li cation. (b) equivalence to a single transistor ¡ ¡ ¡ BE IC = IS ex where VV .8) 1. T .2 I C2 Q2 V3 IX I C1 Q1 V1 C IX I C2 Q2 V3 V1 Q eq C 2A E V3 B B 2A E E AE E AE (b) Figure 4. 4.9(a) if Q1 and Q2 are identical and o erate in the active m ode and V1 = V2 . VC .(4.

3 O eration of Bi olar Transistor in Active Mode 131 Since IX Solution = IC 1 + IC 2 . IC 2 IS ex V2 V . we have (4. Determine V1 .” o erating as a single tra nsistor with twice the emitter area of each.12) . 4. ex V1 V V2 = 10: V1 IC 1 = IS ex T and hence VT . we say the two transistors are “in arallel.9).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Q1 has an emitter area of AE and Q2 an emitter area of In the circuit of Fig.9(a). 2007 at 13:42 131 (1) Sec. V2 such that IC 1 = 10IC 2. we have 2 V E IX 2 ANqDn ni ex V 1 : WB B T (4.11) This result can also be viewed as the collector current of a single transistor h aving an emitter area of 2AE . Q1 and Q2 are identical and o erate in the active mode.cls v. Exam le 4. 2006] June 30. 4. redrawing the circuit as shown in Fig.3 Solution From Eq. Exercise Re eat the above exam le if 8AE . In fact.9(b) and noting that Q1 and Q2 ex erience identical voltages at their res ectiv e terminals. 4 . (4.

14) (4. i. this result is.8 V for ty ical collector current levels. ex ected because the ex one ntial de endence of IC u on VBE indicates a behavior similar to that of diodes.e. AE 1 = nAE2 . of course.13) V1 . .109).15) 60 mV at T = 300 K: Identical to Eq. (4. (2. Exercise Re eat the above exam le if Q1 and Q2 have different emitter areas. We therefore consider the baseemitter voltage of the transistor relatively const ant and a roximately equal to 0..T That is. V2 = VT ln 10 (4.

AE 2 =AE 1 (4. 2006] June 30. determine the difference between the base emi tter voltage of two such transistors for equal collector currents. we have VBE Exam le 4. From Eq. res ectively. Assuming othe r device arameters are identical. 500 m 500 m.17) = 2:5 106.16) where VBEint = VT lnIC 2 =IS 2 and VBEdis = VT lnIC 1 =IS 1 denote the base emitte r voltages of the integrated and discrete devices. VBEdis = VT ln AE2 : E1 For this exam le. Since IS AE . VBEint . 2007 at 13:42 132 (1) 132 Cha .9 ). (4. S2 (4. yielding VBEint . whereas modern integrated devices may have an area as small as 0:5 m 0:2 m. A VBEint . however.4 Solution = VT lnIC =IS and hence I VBEint . e..cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Re eat the above com arison for a very small integrated device with an emitter a rea of 0:15 m 0:15 Since many a lications deal with voltage quantities.g. the collector current gene ¡ ¡ .18) In ractice. VBEdis = 383 mV: (4. VBEdis falls in the range of 100 to 150 mV becaus e of differences in the base width and other arameters. VBEdis = VT ln IS1 . The key oint here is t hat VBE = 800 mV is a reasonable a roximation for integrated transistors and sh ould be lowered to about 700 mV for discrete devices. 4 Physics of Bi olar Transistors Ty ical discrete bi olar transistors have a large area.

generating a voltage . This current ows through RL .16 A.5 = 5 10. 4. Determine the out ut voltage in Fig.9). (4. 1 kΩ 3V Q1 Vout Figure 4.10 Sim le stage with biasing.rated by a bi olar transistor ty ically ows through a resistor to roduce a volta ge.10 if IS RL IC 750 mV Exam le 4. we write IC Solution = 1:69 mA. Using Eq.

Equation (4. IB . As an exam le. Thus. We can therefore view IB as a 3 Recall that ¡ ¡ ¡ . out of every 200 electrons injected by the emitter. 2007 at 13:42 133 (1) Sec.12(a). Recall from Eq. we obtain Vout = 1:31 V: (4. 4. we study the behavior of the transistor for VCE VBE .11(a)]. on the average.11 (a) Bi olar transistor as a current source. IC RL. the base current. exhibit ing a constant value for VCE V1 . calculation of the base current readily yields the emitter current as well. In ractice.12(b)]. acting as a current source [Fig.99) that the hole and electron currents in a forwar d biased n junction bear a constant ratio given by the do ing levels and other arameters.19) Exercise What ha ens if the load resistor is halved. some electro ns and holes are “wasted” as a result of recombination.11(b) is the current as a function of the collector emitter voltage. 4. the base current contains an additiona l com onent of holes. Thus. 2006] June 30. For exam le. for every 200 electrons injected by the emitter. Since the bi olar transistor must satisfy Kirchoff’s current la w. As the electrons injected by the emitter travel through th e base. some may “recombine” with the holes [Fig. for a xed base emitter voltage. results from the ow of holes. Since VCE = 3V . the device dra ws a constant current. (2. 4. one recombines with a hole. In Section 4. in essence. IC Q1 V1 I S ex V1 VT V1 (a) (b) Forward Active Region V CE Figure 4. 4. 4. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Base and Emitter Currents Having determined the collector current.3 O eration of Bi olar Transistor in Active Mode 133 dro of 1 k 1:69 mA = 1:69 V. the base current must su ly holes for both reverse injection into the emitter and recombination with the electrons traveling toward the collector.5.9) reveals an interesting ro erty of the bi olar transistor: the co llector current does not de end on the collector voltage (so long as the device remains in the active mode). (b) I/V characteristic.3 Constant current sources nd a lication in man y electronic circuits and we will see numerous exam les of their usage in this b ook. one hole m ust be su lied by the base. the number of holes entering from the base to the emitter is a constant fraction of the number of electrons traveling from the emitter to the base. In summary. I n the n n transistor of Fig. Plotted in Fig .3.cls v. we now turn our attention to the base and emitter currents and their de endence on the terminal voltages.

¡ .VCE V1 is necessary to ensure the collector base junction remains reverse biased .

4 Physics of Bi olar Transistors V CE n IE (a) (b) Figure 4. we a ly the KCL to the transistor with the current directions de icted in Fig. 2006] June 30. the of n n transistors t y ically ranges from 50 to 200.12 Base current resulting from holes (a) crossing to emitter and (b) re combining with electrons.cls v. (4. 4. 2007 at 13:42 134 (1) Cha .” De ending on the device structure.20) where is called the “current gain” of the transistor because it shows how much the b ase current is “am li ed.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12( a): IE = IC + IB = IC 1 + We can summarize our ndings as follows: n V CE V BE + h − e + − e n 134 IC n IB V BE + h − e + . It is common to write IC = IB . constant fraction of IE or a constant fraction of IC . In order to determine the emitter current.

21) : (4.24) (4. calculate the minimum and maximum terminal currents of the device. For a given VBE .23) (4.22) (4. suggesting that 1 and IC IE are reasonable a roximations.1 (4.16 A is biased in the forward active region with VB E = 750 mV. the collector current remains inde endent of : Exam le 4. In this book.25) It is sometimes useful to write IC = = + 1 IE and denote = + 1 by . For = 100.6 Solution BE IC = IS ex VV T (4. = 0:9 9. A bi olar transistor having IS = 5 10. If the current gain varies from 50 to 200 due to manufacturing varia tions. we a ssume that the collector and emitter currents are a roximately equal.26) BE IC = IS ex VV T 1 I ex VBE IB = S VT + 1 I ex VBE : IE = S V T .

4.23) (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.28) On the other hand. 4. As illustrated in Fig. we can lace a diode bet ween the base and emitter terminals. since the current drawn from the collector and owing into the emitter de ends on only the base emitter voltage. 2007 at 13:42 135 (1) Sec. the emitter current ex eriences only a small variation becaus e near unity for large : + 1= is 1:005IC IE 1:693 mA IE Exercise 1:02IC 1:719 mA: (4. we can now co nstruct a model that roves useful in the analysis and design of circuits—in a man ner similar to the develo ments in Cha ter 2 for the n junction.4 Bi olar Transistor Models and Characteristics 4. B C VBE IS I S ex ¡ ¡ ¡ ¡ ¡ ¡ ¡ . 4. this curr ent remains inde endent of the collector emitter voltage. (4.30) Re eat the above exam le if the area of the transistor is doubled. 4.1 Large Signal Model With our understanding of the transistor o eration in t he forward active region and the derivation of Eqs. arriving at the model shown in Fig. we add a voltage controlled current source between the collector and the emitter.25).27) 8:43 A IB 33:7 A: (4. 2006] June 30.4 Bi olar Transistor Models and Characteristics 135 = 1:685 mA: The base current varies from IC =200 to IC =50: (4.29) (4.4.cls v. Moreover.13. Since the base emitter junction is forward biased in the active mode.11.

Q1 Example 4. the ase -emitter junction is modeled y a diode whose cross section area is 1= times tha t of the actual emitter area.e.7 = 5 10. £ £ £ £ £ £ £ £ . where IS. Thus. the ase-emitter voltage generates a collector current. We view the chain of dependencies as VBE ! IC ! IB ! IE .24) suggests that the ase current is equal to that of a diode having a reverse saturation current of IS = . But how do we ensure that the current owing through the diode is equal to 1= time s the collector current? Equation (4. which requires a proportional ase current. and the sum of the two ows through the emitter. Consider the circu it shown in Fig.17 A and VBE = 800 mV..13 Large-signal model of ipolar transistor in active region.V BE VT β exp V BE VT E Figure 4. With the interdependencies of currents and voltage s in a ipolar transistor. i.14(a). 4. the reader may wonder a out the cause and effect rela tionships.

Solution (a) Using Eq.800 500 1041 R C (Ω ) (a) (b) Figure 4. RC IC . increases while VCC is constant.25).31) (4. VX .14 (a) Sim le stage with biasing. (a) Determine the transistor terminal currents and voltages and ve rify that the device indeed o erates in the active mode. 4 Physics of Bipolar Transistors VX (V) RC IC V BE 500 Ω 2.0 X Q1 VCC 2V 1. the voltage at node X dro s. 2006] June 30. 2007 at 13:42 136 (1) 136 Chap.424 0.35) Since the collector voltage is more ositive than the base voltage. Assume = 100.33) The base and emitter voltages are equal to +800 mV and zero. (b) Determine the maxim um value of RC that ermits o eration in the active mode.34) VX = 1:424 V: (4. The device ¡ ¡ ¡ . (b) variation of collector vo ltage as a function of collector resistance. We mu st now calculate the collector voltage.23) (4.cls v. res ectively.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.32) (4. (4. this junctio n is reverse biased and the transistor o erates in the active mode. we obtain VCC = RC IC + VX : That is. we have IC = 1:153 mA IB = 11:53 A IE = 1:165 mA: (4. (b)What ha ens to the circuit as RC increases? Since the voltage dro across the resistor. Writing a KVL from the 2 V ower su ly and across RC and Q1 . (4.

VX .a roaches the “edge” of the forward active region if the base collector voltage fa lls to zero. i. for VX (4. reduces to (4.14(b) lots VX as a function of RC . as VX ! +800 mV.e..37) RC = 1041 : Figure 4.34) yields: RC = VCCI. (4. ¡ .36) = +800 mV. C which. Rewriting Eq.

4. Figure 4. The reader may wonder why the equivalent circuit of Fig.15(a) lots IC versus VBE with the assum tion that the collector voltage is constant an d no lower than the base voltage.4 Bi olar Transistor Models and Characteristics 137 RC .cls v. IC Q1 V BE V CE V BE IC Q1 V CE IC I S ex I S ex V BE (a) IC V BE2 VT V BE1 VT V BE = V B2 V BE = V B1 V CE (b) Figure 4. thus. The rst characteristic to study is. 4 A 500 mV change in ¡ ¡ ¡ ¡ ¡ ¡ ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.” After all. 4. 2006] June 30. only a few of such characteristics rove useful. if the base emitter voltage varies from 800 mV to 300 mV . Next. the characteristic moves u or down.11. However. IC is inde endent of VC E . we m ay envision lotting different currents as a function of the otential differenc e between every two terminals—an elaborate task. Illustrated in Fig. this limits th e voltage gain that the circuit can rovide. we examine IC for a given VBE but with VCE varying.15 Collector current as a function of (a) base emitter voltage and (b) collector emitter voltage.4 . 4. As shown in Fig. 4. what is the minimum allowable value of VCC for transistor o eration in the active mode? Assume RC = 500 . With three terminal currents and voltages. studied in Section 4. and hence the collector current by many orders of magnitude. 4. 2007 at 13:42 137 (1) Sec.4. in the circuit of Fig.14(a).4. the above exam le a arently contains no signals! This terminology em hasizes that the model can be used for arbitrarily large voltage and current changes in the transistor (so long as the device o erates in the act ive mode). As we will see in Cha ter 5.2 I/V Characteristics The large signal model naturally leads to the I/V ch aracteristics of the transistor. This is in contrast to the small signal model. For exam le. as ex lained below. This exam le im lies that there exists a maximum allowable value of the collecto r resistance. if different value s are chosen for VBE . the ex onential relationshi inherent in the device.13 is called the “large signal model. different values of VCE do not alter the characteristic. 4. 15(b). of course. On the other hand. the characteristic is a horizontal line because IC is constant if the dev ice remains in the active mode (VCE VBE ).4 the model still a lies. Exercise In the above exam le.

.VBE leads to 500 mV=60 mV = 8:3 decades of change in IC .

025 A 0. ¡ ¡ ¡ .39) (4.40) IC 1.6 A IC 3 = 1:153 V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (b) V BE (mV) (a) IB 11.153 mA 169 A 24. and IB VCE characteristics.25) suggest that the base and emitter currents follow the same behavior.8 We determine a few oints along the IC VBE characteristics.169 A 0.38) (4. Exam le 4.24) and (4.15 constitute the rinci al characteristics of interest in most analysis and design tasks. IC VCE .g.6 A 700 750 800 (4.5 A 0. 4 Physics of Bi olar Transistors The two lots of Fig. IS = 5 10.169 A 0.16(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. IC 1. Equations (4. e. Solution VBE1 = 700 mV IC 1 = 24:6 A VBE2 = 750 mV IC 2 = 169 A VBE3 = 800 mV mA: The characteristic is de icted in Fig.17 A and IB VBE . 2007 at 13:42 138 (1) 138 Cha . 2006] June 30.025 A 700 750 800 A V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (d) V BE (mV) (c) ¡ ¡ = 100.cls v.153 mA 169 A 24. Construct the IC VBE . For a bi olar transistor.5 IB 11. 4..

IC jum s by increasingly greater st e s: 24.g. e.Figure 4. we sim ly divide the IC values by 100 [Figs. 4. (b) collector current as a function of base current as a function of BE .16(c) and (d )]. for equal increments in VBE .16 (a) Collector current as a function of BE .3. (c) Using the values obtained above. (b) base current as a function of CE . 169 A if its base emitter voltage is held at 750 mV. 4. We return to this ro erty in Section 4. concluding that the transistor o erates as a constant cur rent source of.16(b).6 A to 169 A to 1. V V V VCE . We als o remark that. For IB characteristics.4. we can also lot the IC VCE characteristic as shown in Fig.153 mA.. ¡ ¡ .

the lots im art no additional information. is called the “transconductance. what is the measure of the “goodness” of a voltage de endent current source? The exam le de ict ed in Fig. as we will see throughout this book..25).17 Test circuit for measurement of Q1 V CE gm . For a ipolar transistor. com ared to Eqs. 4. For exam le. 2007 at 13:42 139 (1) Sec.g. 2006] June 30.5 mA in another.23) (4.41) BE Note that this de nition applies to any device that approximates a voltage-depende nt current source (e. (4. 4. 4. More s eci cally.cls v. if a signal chan ges the base emitter voltage of a transistor by a small amount (Fig. we recognize that the “strength” of the device can be re resented by IC =VBE . if a base emitter voltage change of 1 mV results in a IC of 0.” gm : dI gm = dV C : (4.9) gives gm = dVd ¡ £ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ £ . (4.4. The ratio IC =VBE approaches dIC =dVBE for very small changes and. we ask. Eq.17).1 mA in on e transistor and 0. another type of transistor descri ed in Chapter 6). in the lim it.1 suggests that the device becomes “stronger” as K increases because a given in ut voltage yields a larger out ut current. After all. how much change is roduced in the collector current? Denoting the change in IC by IC . the visualization of equations by means of such lots greatly enhances our understanding of the devices and the c ircuits em loying them. We must therefore concentrat e on the voltage to current conversion ro erty of the transistor.3 Conce t of Transconductance Our study thus far sho ws that the bi olar transistor acts as a voltage de endent current source (when o erating in the forward active region).” IC ∆V BE Figure 4. we can view the latter as a better voltage d e endent current source or “voltage to current converter. articularly as it relates to am li cation of signals. However. 4. how is the erformance of such a device quanti ed? In other words. An im ortant question that arises here is.4 Bi olar Transistor Models and Characteristics 139 Exercise What change in VBE doubles the base current? The reader may wonder what exactly we learn from the I/V characteristics.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

58)] is no coincidence and will ecome clearer in the next chapter. £ £ £ .42) (4. (3.43) (4.BE = V1 IS exp VV T T BE BE IS exp VV T (4.44) I = VC : T The close resem lance etween this result and the small-signal resistance of dio des [Eq.

18 Illustration of transconductance. it is often helpful to view gm as the inverse of a resistance. In other words. if VBE experiences a small pertur ation V around VBE 0 . For example.5 IC I C0 V BE0 V BE g m ∆V ∆V Figure 4. as we will see throughout this ook.47) However. 2007 at 13:42 140 (1) 140 Chap. the required gain. if IC = 1 mA. As shown in Fig. then with VT = 26 mV. What happens to the transconductance of Q1 if the area of the device is increased y a factor of n? n I C0 I C0 Q1 V BE0 (a) Figure 4. 4.44) reveals that. and the c orresponding ase-emitter voltage.g.9 I C0 V CE V BE0 I C0 I C0 V CE £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ . then the collector current displays a change o f gm V around IC 0 .48) The concept of transconductance can e visualized with the aid of the transistor I/V characteristics. Consider the circuit shown in Fig.45) (4. 4 Physics of Bipolar Transistors Equation (4.19 (a) One transistor and ( ) Example 4. for IC = 1 mA. VBE 0 . meaning the device carries a ia s (or “quiescent”) current of IC 0 in the a sence of signals. gm = dIC =dVBE simply represents th e slope of IC -VBE characteristic at a given collector current. we may write gm = 261 : (4. as IC increases.1 or “siemens. e.” S. IC 0 . we have gm = 0:0385 . The transconduct ance may e expressed in .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.46) (4. the value of IC 0 must e chosen according to the required gm and.18.1 = 0:0385 S = 38:5 mS: (4. the transistor ecomes a etter a mplifying device y producing larger collector current excursions in response to a given signal level applied etween the ase and the emitter. 2006] June 30..cls v. Thus.19(a). ultimately. where gm = IC 0 =VT . 4. We say the tran sistor is “ iased” at a collector current of IC 0 .

we use the term “ ias current” to refer to the collector ias current.n transistors providing transconductance. £ £ £ . ( ) 5 Unless otherwise stated.

44) suggests that the transconductance is fundamentally a function of the collector current rather than the ase current.4 Bipolar Transistor Models and Characteristics 141 Since IS AE . with the ase current viewed as secondary. the current produced y the transistor may ow thro study the transconductance in the context of the IC -VCE transistor with VBE as a parameter. [Fig. each carrying a collector current of IC 0 are placed in parallel. 4. The derivation of gm in Eqs.20 for two different ge of V in VBE results round IC 1 ecause gm2 IC g m2 ∆V V BE = V B2 + ∆V V BE = V B2 V BE = V B1 + ∆V V BE = V B1 I C2 I C1 g m1 ∆V V CE Figure 4. the transconductanc e increases y a factor of n.42)-(4.10. often undesira le effect. 4 ias currents IC 1 and IC 2 . Thus. 2006] June 30. As a result. the collector ias current plays a central role in the an alysis and design. 4. Illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then the c omposite device exhi its a transconductance equal to n times that of each. IS is multiplied y the same factor. As shown in Fig.19( )]. 2007 at 13:42 141 (1) Sec. On the other hand.cls v. then gm does not change ut IB does. £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ . For this reason.20 Transconductance for different collector ias currents. 4. (4. if the total collector current remains unchanged. the plots reveal that a chan in a greater change in IC for operation around IC 2 than a gm1 . Solution Exercise Repeat the a ove example if VBE 0 is reduced y VT ln n. then so does the transconductance. It is also possi le to characteristics of the . For example. From another perspective. if IC remains constant ut varies. IC = IS expVBE =VT also rises y a factor of n ecause VBE is constant. if n identical transisto rs.

g. e. determine the changes in the cu rrents owing through all terminals. may incorporate a large num er of transistors.ugh a resistor to generate a proportional voltage.21 depicts two conceptual examples where VBE or VCE is changed y V and the changes in IC .4. thus posing great dif culti es in the analysis and design. Recall from Chapter 3 that diodes can e reduced to linear devices through the use of the small-signal model. We pertur the voltage difference etween every two terminals (while the third terminal remains at a constant potential). IB . and IE are examined. The derivation of t he small-signal model from the large-signal counterpart is relatively straightfo rward. a mpli ers. £ £ £ £ £ £ £ £ . A similar ene t accr ues if a smallsignal model can e developed for transistors.. 4. Figure 4.4 Small-Signal Model Electronic circuits. and represent the results y proper circuit e lements such as controlled current sources or resistors. We exploit this concept in Ch apter 5 to design ampli ers.

Let us egin with a change in VBE while the collector voltage is constant (Fig. 4 Physics of Bipolar Transistors ∆I C ∆I B ∆V ∆I B V BE ( ) ∆I C ∆V Q1 Q1 V CE ∆I E (a) ∆I E Figure 4.cls v. 2006] June 30. We know from the de nition of transconductance that ∆ I C = g m ∆V BE ∆V BE Q1 V CE ∆I B VBE I S exp ∆I C V BE + ∆V BE VT V CE ∆V BE ∆I E B C B vπ g vπ m C B rπ vπ g vπ m £ £ £ £ £ . 4.21 Excitation of ipolar transistor with small changes in (a) ase-emit ter and ( ) collectoremitter voltage.22).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 142 (1) 142 Chap.

49) concluding that a voltage-controlled current source must e connected etween th e collector and the emitter with a value equal to gm V . The change in VBE crea tes another change as well: IB = IC (4.22 evelopment of small-signal model. if the ase-emitter voltage changes y VBE ..C ∆V BE g ∆V BE m E E E Figure 4. (4. IC = gm VBE . y a resistor pla ced etween the ase and emitter having a value: r = VIBE B (4. i.50) (4. For simplicity.e. the current owing etween th ese two terminals changes y gm = VBE . we denot e VBE y v and the change in the collector current y gm v . Since the voltage and current correspond to the same two terminals. they can e related y Ohm’s Law.51) = gm VBE : That is.52) £ £ £ £ £ £ £ £ £ £ £ ¢ £ £ .

exhi its a small-sig nal resistance of VT =IC = = VT =IC = =gm .4 Bipolar Transistor Models and Characteristics 143 =g : m (4. the model developed in Fig. the collector voltage has no effect o n IC or IB ecause IC = IS expVBE =VT and IB = IC = . 4. this trade-off pro ves undesira le in some cases. 4. 4. gm and r .58). from Eq. ∆I C ∆V CE Q1 V BE V BE VBE I S exp V BE VT ∆V CE Figure 4. ut the impedance etween the ase and emitter falls to lower values.23 Response of ipolar transistor to small change in VCE . (a) If v1 = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. versatile tool in t he analysis and design of ipolar circuits. The simple sma ll-signal model developed in Fig. 4. where v1 represents the signal generated y a microphone. for a constant VBE .24(a). the forward. Consider the circuit shown in Fig. a greater gm is o tained. IC Q1 v1 800 mV £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ . such a change also results in a zero change in the terminal currents.16 A. As illu strated in Fig. We now turn our attention to the colle ctor and apply a voltage change with respect to the emitter (Fig. 4. We should remark that oth parameter s of the model.22 serves as a powerful.53) Thus. depend on the ias current of the device. Studied in Chapter 5. With a high collector ias current. 2006] June 30.22 need not e a ltered.cls v. IS = 3 10. Since VCE leads to no change in any of the terminal currents.iased diode etween the ase and the emitter is modeled y a small-signal resistance equal to =gm .11. and Q1 operates in the active mode. This result is expected ecause the diode carries a ias current equal to IC = and.ase voltage? As studied in Pro lem 18. = 100. How a out a change in the collector.23). 2007 at 13:42 143 (1) Sec. 4. (3.

24 (a) Transistor with bias and small signal excitation. we obtain a collector bias current of 6. (b) sm all signal equivalent circuit. Thus.92 mA for VBE = I gm = VC T (4.Example 4. Solution = IS ex VBE =VT .8 V v1 rπ vπ iC g vπ m (a) (b) Figure 4.10 iB V CC = 1.54) ¡ ¡ ¡ ¡ . determine the small signal arameters of Q1 . how much change is observed in the collector and base currents? (a) Writing IC 800 mV. (b) If the micro hone generates a 1 mV signal.

and (4. equal to IC = . leading to a otential dro of IC RC = 692 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if the collector current ows through a resistor. On the other hand. is thus given by: ¡ ¡ ¡ . The micro hone signal roduces a change in IC . where resistor RC converts the collector current to a voltage.63) which is.60) v IB = r 1 1 mV = 375 = 2:67 A. 4. 4. The circuit of Fig.cls v.56) (4. 4 Physics of Bi olar Transistors 1 = 3:75 .24(a) is modi ed as shown in Fig. of course. (a) Verify that the transistor o e rates in the active mode. a useful out ut is rovide d.57) (b) Drawing the small signal equivalent of the circuit as shown in Fig.8 V battery. 4.62) (4.61) (4. the circuit generates no out ut. we obtain the change in the collector current as: IC = gm v1 1 mV = 3:75 = 0:267 mA: The equivalent circuit also redicts the change in the base current as (4. The above exam le is not a useful circ uit. In other words.92 mA ows through R C .55) r = g = 375 : m (4. (b) Determine the out ut signal level if the micro hon e roduces a 1 mV signal.25. The collector voltage. (a) The collector bias current of 6. Exercise Re eat the above exam le if IS is halved.59) (4. but the result ows through t he 1.24(b) and recognizing that v = v1 . (4. 2007 at 13:42 144 (1) 144 Cha . 2006] June 30. which is equal to Vout .58) (4.

11 Solution Vout = VCC . RC IC = 1:108 V: (4.64) (4. . the device o erates in the active mode.Exam le 4.65) Since the collector voltage (with res ect to ground) is more ositive than the b ase voltage.

We will study and quantify the behavior of this and other am li er to ologies in t he next cha ter. The key rinci le here is that the su ly voltage (ideally) remains constant even though various voltages and currents within the circuit m ay change with time. The circuit therefore am li es the in ut by a factor of 26 .4. Thus. other com onents in the circuit must also be re resented by a small signal model. (b) As seen in the revious exam le. The voltage dro ac ross RC now increases to 6:92 mA 200 = 1:384 V. Note ¡ ¡ ¡ ¡ ¡ ¡ ¡ What value of RC laces results in a zero collector base voltage? ¡ ¡ ¡ ¡ . Similarly. so me circuits require attention to such effects if meaningful results are to be ob tained.11. Exercise The foregoing exam le demonstrates the am li cation ca ability of the transistor. In such an analysis. Verify that the devi ce o erates in the active mode and com ute the voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this change yields a change of 0:267 mA 100 = 26:7 mV in Vout . Since the su ly does not change and since the small signal model of the circuit entails only changes in the quantities.7. a 1 mV micro hone signal leads to a 0.8 V Q 1 Vout v1 800 mV Figure 4.5 Early Effect Our treatment of the bi olar transistor has thus far concentr ated on the fundamental rinci les. ignoring second order effects in the device and their re resentation in the large signal and smallsignal models. any other consta nt voltage in the circuit is re laced with a ground connection. U on owing through RC . However. we sim ly “ground” the su ly voltage in small signal analysis.cls v. su ose we raise RC to 200 and VCC to 3. Considering the circuit of Exam le 4.6 V. behaves with res ect to small changes in the currents and volt ages of the circuit. The following exam le illustrates this oint. 4. 1:384 V = 2:216 V and guaranteeing o eration in the active mode. 2007 at 13:42 145 (1) Sec.4 Bi olar Transistor Models and Characteristics 145 RC 100 Ω V CC = 1. we observe that VC C must be re laced with a zero voltage to signify the zero change. we must determine how the su ly voltage. we sometimes say a node is an “ac ground.267 m A change in IC . leading to a collector voltage o f 3:6 V .25 Sim le stage with bias and small signal excitation. Small Signal Model of Su ly Voltage We have seen that the use of the small signal model of diodes and transistors can sim lify the analysis co nsiderably. 2006] June 30.” 4. VCC . In articular. To em hasize tha t such grounding holds for only signals.

that Exam le 4.12 Solution .

This result is also obtained with the aid of the small signal model. 2006] June 30. WB .1 and RC = 200 . limit the maximum gain that can be achieved? Indeed. Illustrated in Fig.27(b)]. then Vout = 1:8 V . we return to the internal o eration of the transistor and reexamine the claim shown in Fig. 200 Ω RC rπ vπ v1 g vπ m v out Figure 4.gm v1 RC and hence vout =v1 = . Does this mean that. 4. erha s in the transistor. Now su ose VCE is raised to VCE 2 [Fig. 4. Recall from art (b) of the above exam le t hat the change in the out ut voltage is equal to the change in the collector cur rent multi lied by RC . 2 the effective base width. the equivalent circuit yields vout = . x0 . the “Early effect” translates to a n onideality in the device that can limit the gain of am li ers. (4.” Consider the device shown in Fig. Since RC is doubled.53:4.26. 4 Physics of Bi olar Transistors if VCC is not doubled.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.25. 2007 at 13:42 146 (1) 146 Cha . reaching a value of 53.27(a). Discovered by Early. 4. 1:384 V = 0:416 V and the transistor is not in the forward active region.4. Equivalently.26 Small signal equivalent circuit of the stage shown in Fig. 4. in Eq. thus increasing the reverse bias and widening the de letion re gion in the collector and base areas. thereby i ncreasing the collector current. then the gain also grows in de nitely? Does another mechanism in the circuit.gm RC . the voltage gain must also double. so does the voltage gain of the circuit.cls v. How is the Early effect re resent ¡ ¡ . Exercise What ha ens if RC = 250 ? This exam le oints to an im ortant trend: if RC increases.g m v RC = . With gm = 3:75 . w e have vout =v1 = . To understand this effect. Since the base charge ro le must still fall to zero at the edge of de letion region. 4. this henomenon oses inte resting roblems in am li er design (Cha ter 5). the slo e of the ro le increases.8) decreases. where the collector volta ge is somewhat higher than the base voltage and the reverse bias across the junc tion creates a certain de letion region width. if RC ! 1.11 that “the collector current does not de end on the collec tor voltage.

1 1 + VV . It can be roved that the rise in the collector current with VCE can be a roxim ately ex ressed by a multi licative factor: 2 E BE CE IC = ANqDn ni ex VV . (4.9) to include this effect. E WB T A .ed in the transistor model? We must rst modify Eq.

.

BE V CE IS ex VV 1+ V : T A .

.

The quantity VA is called the “Early voltage.67) where WB is assumed constant and the second factor.” .(4. models the Earl y effect. 1+ VCE =VA .66) (4.

4 Bi olar Transistor Models and Characteristics V CE1 n x x2 x1 n + 147 V CE2 n x ’ x2 e V BE e V BE n + x1 (a) (b) Figure 4. It is instructive to examine the I/V characteristics of Fig. (b ) effect of higher collector voltage. 4 .15 in the resenc e of Early effect.27 (a) Bi olar device with base and collector bias voltages. In fact.cls v. IC With Early Effect IC VBE 1 (4.28(b)].69) A VA and hence IC This is a reasonable a roxIC V BE1 VT Without Early Effect With Early Effect IS ex VBE =VT . 4. f or a constant VBE . ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. the IC VCE characteristic dis lays a nonzero slo e [Fig.68) VCE = IS ex VT VA I VC . 2007 at 13:42 147 (1) Sec. For a constant VCE . (4. On the other hand. 4. 4.28(a)]. the de endence of IC u on VBE remains ex onential but with a somewhat greater slo e [Fig. differentiation of (4.67) with res ect to VCE yields where it is assumed VCE imation in most cases.

.

With VA Exam le 4. 4. Assume IS = 2 10. (4. requiring modi cation of the ers ec tive shown in Fig. 4.28 Collector current as a function of (a) VBE and (b) VCE with and without Early effect. The transistor can still be viewed as a two terminal device but with a current that varies to some extent with VCE (Fig.67) VBE = VT ln IC I S (4.28(b) reveals that the transistor in fact does not o erate as an ideal current source. 4. Determine t he required base emitter voltage if VA = 1 or VA = 20 V.11(a).13 Solution = 1.Without Early Effect V BE (a) (b) V CE Figure 4. A bi olar transistor carries a collector current of 1 mA with VCE = 2 V. The variation of IC with VCE in Fig. we have from Eq.70) ¡ ¡ I S ex .16 A.29).

29 Realistic model of bi olar transistor as a current source. we have 1 + VCE =VA .72) = 757:8 mV: In fact. we rewrite Eq. 2006] June 30. VCE =VA ( I S ex .71) = 20 V. = 760:3 mV If VA (4. 2007 at 13:42 148 (1) 148 X Cha . 4 X Physics of Bi olar Transistors Q1 V1 V1 VT ) ( 1+ VX VA ) Figure 4.1 1 . (4.73) where it is assumed ln1 .67) as 0 B VBE = VT ln B IC @ 1 1 C C IS 1 + VCE A VA (4. VA . for VCE (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

The large signal model of Fig.1 and 4. VCE VBE VT ln I T VA S CE . ¡ ¡ .4.IC + V ln 1 .13 must now be modi ed to that in Fig.74) (4.75) 1.4. IS A Large Signal and Small Signal Models The resence of Early effect alters the tra nsistor models develo ed in Sections 4. 4.30. VT VV .4. for (4. VT ln IC . 4. where BE CE IC = IS ex VV 1 + VV T ¡ Exercise Re eat the above exam le if two such transistors are laced in arallel.

A BE IB = 1 IS ex VV T IE = IC + IB : .

.

For the small signal model.(4. we note that the controlled current source remains u nchanged and gm is ex ressed as dI gm = dV C BE (4.77) (4.76) (4.79) ¡ ¡ .78) Note that IB is inde endent of VCE and still given by the base emitter voltage.

2007 at 13:42 149 (1) Sec. 2006] June 30.4 Bi olar Transistor Models and Characteristics 149 B IB VBE IE E C V1 VT ) ( 1+ V CE VA ) Figure 4.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4.30 Large signal model of bi olar transistor including Early effect. BE = V1 IS ex VV T T ¡ IC ( I S ex .

.

83) Considering that the collector current does vary with VCE . 4.81) r = g = VT : I C m (4.I = VC : T Similarly.80) (4.82) (4. CE 1 + VV A (4. let us now a ly a v oltage change at the collector and measure the resulting current change [Fig. 31(a)]: BE IC + IC = IS ex VV T It follows that .

.

IC = IS ex VV VA T .1 + VCE + VCE : V A (4.84) BE VCE .

= 100 ¡ rO = VICE C VA = BE IS ex VV T VA : I C ¡ ¡ . Determine the small signa l model if and VA = 15 V. Note that both r and rO are inversel y ro ortionally to the bias current. (4. yielding an equivalent res istor: De icted in Fig. IC .88) Exam le 4.86) (4.14 A transistor is biased at a collector current of 1 mA. (4.(4.” rO lays a cri tical role in high gain am li ers (Cha ter 5). they satisfy Ohm’s Law. 4.69). to re resent the Early effect.87) (4. Called the “out ut resistance. Since the voltage and current change corres ond to the same two terminals. the small signal model contains only one extra element . rO .31(b).85) which is consistent with Eq.

93) (4. 4 Physics of Bi olar Transistors C ∆I C Q1 V BE ∆V B rπ vπ g vπ m rO E (a) (b) Figure 4. r = g Also.90) 1 = 26 . = 2600 : m (4. 2007 at 13:42 150 (1) 150 Cha .cls v. Solution We have I gm = VC T and (4.31 (a) Small change in VCE and (b) small signal model including Early effect.92) rO = VA I C (4.94) = 15 k : Exercise What early voltage is required if the out ut resistance must reach 25 k ? ¡ .89) (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.91) (4. 2006] June 30.

VCE 0).. An im ortant notion that has emerged from o ur study of the transistor is the conce t of biasing. We must create ro er dc v oltages and currents at the device terminals to accom lish two goals: (1) guaran tee o eration in the active mode (VBE 0. Finally. rO . the load resistance tied to the collector faces an u er limit for a given su ly voltage (Exam le 4. rO .31(b) does not re ect the highfrequency limitations of the tran sistor.In the next cha ter. e.7). The analysis of am li ers in the next cha ter exercises these ideas extensively. For exam le.12 and determine the gain of the am li er in the resence of the Early effect. and r .32 summarizes t he conce ts studied in this section. ¡ ¡ ¡ ¡ ¡ . 4. we return to Exam le 4. the base emitter and base collector junctions exhibit a de letion region ca acitance that im acts the s eed.g. These ro erties are studied i n Cha ter 11. We will conclude that the gain is event ually limited by the transistor out ut resistance. (2) establish a collector current that yields the required values for the small signal arameters gm . Figure 4. we should remark that the small sign al model of Fig.

5 O eration of Bi olar Transistor in Saturation Mode V BE VT n V CE e 151 O eration in Active Mode V CE V BE n n + Large−Signal Model B C I/V Characteristrics IC B Small−Signal Model C VBE IS V BE VT I S ex IC V BE1 VT V CE V BE rπ vπ g vπ m β exp V BE VT E Early Effect I S ex n − e + V BE + h I C = I S ex .cls v. 2007 at 13:42 151 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 4.

For VCE = VBE . But what ha ens if VCE VBE .” Su ose VCE = 550 mV and hence VBC = +200 mV. it is desirable to o erate bi olar devices in the forward active region. car6 About nine orders of magnitude less than one sustaining 750 mV: 750 mV .. even in this case the transistor continues to o e rate as in the active mode. 200 mV=60 mV=dec 9:2. 750 mV.33(a)]. and VBC goes from a negative value toward zero. VBC 0 and the B C junction is forward biased? We say the transistor ente rs the “saturation region. we study the behavior of the device outside this region an d the resulting dif culties. 4. and we say the device is in “soft saturation. the junction sust ains a zero voltage difference. Let us set VBE to a ty ical value. 4.5 O eration of Bi olar Transistor in Saturation Mode As mentioned in the revious section.32 Summary of conce ts studied thus far. ¡ ¡ ¡ ¡ . e.6 Thus. where they act as voltage controlled current sour ces.E n V CE B Modified Small−Signal Model C rπ vπ g vπ m rO V BE n + E Figure 4. i. the base col lector junction ex eriences less reverse bias. In this section. the B C junction ex eriences greater forward bias . As V CE a roaches VBE .” If the co llector voltage dro s further. We know fr om Cha ter 2 that a ty ical diode sustaining 200 mV of forward bias carries an e xtremely small current. but its de letion region still absorbs most of t he electrons injected by the emitter into the base.e.. and vary the collector voltage from a high level to a low level [Fig.g.

(b) ow of holes to collector. 2006] June 30.33(b)].95) (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.15 Solution If the base collector junction is forward biased so much that it carries a curre nt equal to onetenth of the nominal base current. VBC (4. S ince IB = IC =100. 2007 at 13:42 152 (1) 152 Cha . rying a signi cant current [Fig. A bi olar transistor is biased with VBE = 750 mV and has a nominal of 100. a large number of holes m ust be su lied to the base terminal—as if is reduced. Exercise Re eat the above exam le if VBE 180 mV: ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ n − e + ¡ . we have VBE . heavy satur ation leads to a shar rise in the base current and hence a ra id fall in .cls v. 4 Physics of Bi olar Transistors ∆I C V CE Q1 V BE V BE + h V CE n (a) (b) Figure 4. Consequently. How much B C forward bias can the device tolerate if must not degrade by more than 10? For sim licity. assume base collector and base emitter junctions have identical str uctures and do ing levels. We therefo re ask.33 (a) Bi olar transistor with forward biased base collector junction. In other words. 4. what B C voltage results in a current of IC =1000 if VBE = 750 mV gives a collector current of IC ? Assuming identical B E and B C junctions.96) (4. Exam le 4.97) = 570 mV: = 800 mV. IB . VT ln IC =1000 IS IS = VT ln 1000 That is. the B C junction must carry no more than IC =1000. then the degrades by 10. VBC = VT ln IC .

as illustrated in Fig. We construct the model as shown in Fig. then DB C is forward biased so much that its current becomes equal to the controlled cur rent. 4.It is instructive to study the transistor large signal model and I V characteris tics in the saturation region. In fact.34(a).35. 4. where IC begins to fall for VCE less than V1 . The above observations lead to the IC VCE characteristics de icted in Fig . including the base collector diode. if the collector is left o en.34(b). about a few hundred milli volts. 4. Note that the net collector current decrease s as the device enters saturation because art of the controlled current IS 1 ex VBE =VT is rovided by the B C diode and need not ow from the collector terminal. The term “saturation” is ¡ ¡ ¡ ¡ ¡ ¡ .

Thus. As a rule of thumb. rovided that vario us tolerances in the com onent values do not drive the device into dee saturati on. between o eration in so ¡ . electronic circuits rarely allow o eration of bi ola r devices in this mode. 2007 at 13:42 153 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Saturation Forward Active Region IC V1 V CE Figure 4. it is the external com onent that de nes the collector voltage and hence the region of o eration. 4. the s eed of bi olar transistors also degrades in sat uration (Cha ter 11). a resistor.g. we ermit soft saturation with VBC 4 00 mV because the current in the B C junction is negligible.cls v. 2006] June 30.35 Transistor I/V characteristics in different regions of o era tion.5 O eration of Bi olar Transistor in Saturation Mode I S2 ex D BC B C 153 V BE VT D BC I S1 ex V BE VT V BE VBE D BE I S1 ex V BE VT VBE D BE E (a) (b) Figure 4. (b) ca se of o en collector terminal.36. the collector current is still equal to IS ex VBE =VT . 4. Thus. e. It is im ortant to recognize that the transistor sim ly draws a current from any com onent tied to its collector.16 For the circuit of Fig. used because increasing the base current in this region of o eration leads to li ttle change in the collector current..34 (a) Model of bi olar transistor including saturation effects. RC and VCC that guarantees In soft saturation. determine the relationshi ft saturation or active region. In addition to a dro in . The co llector voltage must not fall below the base voltage by more than 400 mV: Solution Exam le 4.

400 mV: (4.VCC .99) . RC IC VBE . (4. 400 mV.98) VCC IC RC + VBE . Thus.

we may wonder wh y such a device would be useful.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e . Under this condition.37 Transistor model in dee saturation.. ¡ ¡ Figure 4. We may naturally wonder if the do ant olarities can be inver ted in the three regions.sat (about 200 mV). (The battery tied betwe en C and E indicates that VCE is relatively constant in dee saturation. More im ortantly. VCE.6.) B 800 mV 200 mV C In the dee saturation region.1 Structure and O eration Figure 4. with the emitter and collector made of n ty e materials and the base made of a ty e material. ¡ ¡ ¡ ¡ . i. VCC must be suf ciently large so that VCC reasonable col lector voltage. (b) acce table range of VCC and RC . em hasizing that the emitter is heavily d o ed. For a given value of RC . 2006] June 30. 4.36 (a) Sim le stage.cls v. 4. the collector emitter voltage a roaches a consta nt value called E 4. forming a “ n ” device.37. As with the n n counter art. o eration in the active region requires forwa rd biasing the base emitter junction and reverse biasing the collector junction.38(a) sh ows the structure of a n transistor. IC RC still maintains a Exercise Determine the maximum tolerable value of RC . the transistor bears no resemblanc e to a controlled current source and can be modeled as shown in Fig. .6 The PNP Transistor We have thus far studied the structure and ro erties of the n n transistor. 4 Physics of Bi olar Transistors Acce table Region RC IC Q1 V BE (a) V CC V CC V BE − 400 mV RC (b) Figure 4. 2007 at 13:42 154 (1) 154 Cha .

Under this condition. . majority carriers in the emitter ( holes) are injected into the base and swe t away into the collector. Also. thus creating the base current.Thus. All of the o eration rinci les and equ ations described for n n transistors a ly to n devices as well. a lin ear ro le of holes is formed in the base region to allow diffusion. A small numbe r of base majority carriers (electrons) are injected into the emitter or recombi ned with the holes in the base region. 38(b) illustrates the ow of the carriers. Figure 4. VBE 0 and VBC 0.

4..6. illustrating Figure 4.38(c) de icts the symbol of the n transistor along with constant volt age sources that bias the device in the active region.2 Large Signal Model The current and voltage olarities in n n a nd n transistors can be confusing. Following our convention of lacing more ositive nodes on the to of the age. (c .cls v. we redraw the circuit as in Fig. bottom of the age).6. 4. 2006] June 30. (1) The (conventional) current always ows from a ositive su ly (i.38(d) to em has ize VEB 0 and VBC 0 and to illustrate the actual direction of current ow into eac h terminal. In contrast to the biasin g of the n n transistor in Fig.. (d) more intuitive view of (c).6 The PNP Transistor 155 + V CE h V BE n + Hole Density (a) (b) V BE Q1 V BE (c) IE IB Q1 IC (d) V CE V CE Figure 4.e. We address this issue by making the followi ng observations. Fi gure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ¡ x x2 x1 V CE V BE − e − e n + h ow in n transistor. 4. 2007 at 13:42 155 (1) Sec.39(a) shows two branches em loying n n and n transistors.e. here the base and collector voltages are lo wer than the emitter voltage.38 (a) Structure of n transistor. 4. to of the age) toward a lower otential (i. (b) current ) ro er biasing.

101) (4. For t he n device.23) (4.25) must be modi ed as follows for the n device (4. Since the base current must be in cluded in the emitter current.that the (conventional) current ows from collector to emitter in n n devices and from emitter to collector in n counter arts. (2) The distinction between active and satu ration regions is based on the B C junction bias. (3) The n n current equations (4. we note that IB1 and IC 1 add u to IE1 whereas I E2 “loses” IB2 before emerging as IC 2 . We note that an n n transistor is in the ac tive mode if the collector (voltage) is not lower than the base (voltage). T ¡ ¡ . where the relative osition of the base and collector node s signi es their otential difference. the collector must not be higher than the base . on the other hand.39(b). 4. The different cases are summar ized in Fig.102) EB IC = IS ex VV T IS ex VEB IB = VT EB IE = + 1 IS ex VV .100) (4.

cls v.40. ¡ transist . the Early effect can be includ ed as EB IC = IS ex E VV T I E2 I C1 I B1 Q1 I E1 0 (a) (b) Figure 4. 2006] June 30. (b) illustration of active and saturation regions. 4 Active Mode Physics of Bi olar Transistors Edge of Saturation 0 Saturation Mode I B2 Q2 I C2 V CC Active Mode Edge of Saturation Saturation Mode where the current directions are de ned in Fig. 4. Also.39 (a) Voltage and current olarities in n n and n ors. 2007 at 13:42 156 (1) 156 Cha . The only difference between the n n and n equations relates to the base emitter voltage that a ears in th e ex onent. an ex ected result because VBE 0 for n devices and must be changed to VEB to create a large ex onential term.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

.

40 Large-signal model of pnp transistor.16 A and = 50.2 V X RC V CC 2V 200 Ω Figure 4.41. Assume IS = 2 10.41 Sim le stage using a n transistor. ut VA = 1. Example 4. £ . 4. determine the terminal currents of Q1 and ver ify operation in the forward active region.103) IS β exp V EB VT VEB IE I S exp IC V EB VT C B IB Figure 4. In the circuit shown in Fig.EC 1 + VV : A (4.17 Q1 1.

Q1 V in 1.18 IC RC 300 Ω Vout ¡ ¡ ¡ .107) We must now com ute the collector voltage and hence the bias across the B C junc tion.105) It follows that IB = 92:2 A IE = 4:70 mA: RC carries IC . we conclude that We should mention that some books assume all of the transistor terminal currents ow into the device. In the circuit of F ig. 4.42. 2006] June 30.109) which is lower than the base voltage. Exercise What is the maximum value of RC is the transistor must remain in soft saturation ? (4.100) (4.102) is justi ed. Since VX = RC IC = 0:922 V. (4.108) (4.16 A. Vin re resents a signal generated by a micro hone.39(b). We nonetheless continue with our notat ion as it re ects the actual direction of currents and roves more ef cient in the a nalysis of circuits containing many n n and n transistors. (4.104) (4.cls v. 4.6 The PNP Transistor 157 We have VEB Solution = 2 V .101) be multi lied by a negative sign. 4.7 V Exam le 4. 1:2 V = 0:8 V and hence EB IC = IS ex VV T = 4:61 mA: (4. Determine Vout for Vin = 0 and Vin = +5 mV if IS = 1:5 10.100) and (4.106) (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thus requiring that the right hand side of Eqs. Q1 o erates in the active mode and the use of equations (4 . Invoking the illustration in Fig. 2007 at 13:42 157 (1) Sec.

VEB = +800 mV and we have EB IC jVin =0 = IS ex VV T (4. For Vin Solution = 0.42 PNP stage with bias and small signal voltages.110) ¡ .V CC 2.5 V Figure 4.

2007 at 13:42 158 (1) 158 Cha .43(a).38(d). we ex ect n n and n transistors to have similar models.6.43(b).cls v. 4. Since a 5 mV change in V1 gi ves a 182 mV change in Vout . De icted in Fig. 4 Physics of Bi olar Transistors = 3:46 mA. 4.114) Note that as the base voltage rises.5 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. yielding (4.112) = +795 mV and IC jVin =+5 mV = 2:85 mA.113) Vout = 0:856 V: (4. the small signal model of the n transistor is indee d identical to that of the n n device. 4.25.4. 2006] June 30. VBE 1 (4. the voltage gain is equal to 36. the collector voltage falls. 4.3 Small Signal Model Since the small signal model re resents changes in the voltages and currents. Following the convention in Fig. Exercise Determine Vout is Vin = .111) Vout = 1:038 V: If Vin increases to +5 mV. These results a re more readily obtained through the use of the small signal model. and hence (4. 4. E B ib rπ vπ ie E (a) ic g vπ m rO ¡ ¡ ¡ ¡ ¡ ¡ . we sometimes draw the model as shown in Fig. a behavior sim ilar to that of the n n counter arts in Figs.

one may automatically assume that the “to ” t erminal is the collector and hence the model in Fig. 4. ¡ ¡ ¡ ¡ .43(b) is not identical to that in Fig.31(b). 4. (b) more intuitive view of (a).4 3(b). The small signal model of n transistors may cause confusion. es ecially if drawn as in Fig. 4. 40. A few exam le s rove hel ful here. This is not an inconsistency and is studied in Problem 49. We caution the reader about this confusion. In analogy with n n transistors.43 (a) Small signal model of n transistor. The reader may notice that the terminal currents in the small signal model bear an o osite direction with res ect to those in the large signal model of Fig.C ie rπ B vπ g vπ m rO C ib (b) ic Figure 4. 4.

6 The PNP Transistor 159 Exam le 4. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. Determine the small signal im edance of the devices shown in Fig.44(a).118) g1 m VT : =I C Interestingly.116) (4. we have vX = 1 . Exercise What is the im edance of a diode connected device o erating at a current of 1 mA ? ¡ ¡ ¡ ¡ ¡ ¡ .44(a). Assume VA = 1. iX Q2 Q1 vX rπ vπ g vπ m (a) (b) Figure 4. 4.” The same results a ly to the n con guration in Fig. 4. 4 .117) (4. the device exhibits an im edance simi lar to that of a diode carrying the same bias current. iX gm + r 1 (4.19 If the collector and base of a bi olar transistor are tied together. with a bias current of IC . a two termi nal device results. we write a KCL at the in ut node: Solution vX + g v = i : r m X Since gm r (4. We call this structure a “d iode connected transistor. Noting that r i carries a cu rrent equal to vX =r . 4.44(b)].44 We re lace the bi olar transistor Q1 with its small signal model and a ly a sma ll signal voltage across the device [Fig.115) = 1. 2007 at 13:42 159 (1) Sec.

Solution As illustrated in Figs.45 (a) (c) and com are the results. It is seen that all three to ologies re duce to the same equivalent circuit because VCC is grounded in the small signal re resentation.Exam le 4.20 Draw the small signal equivalent circuits for the to ologies shown in Figs. 4.45(d) f. ¡ ¡ ¡ ¡ ¡ . 4. we re lace each transistor with its small sig nal model and ground the su ly voltage.

cls v. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 160 (1) 160 VCC RC v in Q 1 v out v in RC Cha . 4 VCC Q1 Physics of Bi olar Transistors VCC v in Q1 v out RC v out (a) (b) (c) RC rπ vπ g vπ m rπ vπ g vπ m v in rO v out v in r O RC v out (d) rπ v in vπ g vπ m rO RC v out v in rπ vπ .

(d) small signal equivalent of (a). ¡ ¡ ¡ ¡ .45 (a) Sim le stage using an n n transistor. Figure 4. (f) small signal equivalent of (f). 4. (b) sim le stage using a n transistor. (c) another n stage. (e) sm all signal equivalent of (b). Exam le 4.21 Draw the small signal equivalent circuit for the am li er shown in Fig.46(a).g vπ m r O RC v out (e) v in rπ vπ g vπ m rO RC v out v in rπ vπ g vπ m r O RC v out (f) Exercise Re eat the above exam le if a resistor is laced between the collector and base of each transistor.

7 Cha ter Summary A voltage de endent current source can form an am li er along with a load resistor . Bi olar transistors are electronic devices that can o erate as voltage de ende nt current sources. For ro er o eration. Solution RC 1 .46 (a) Stage using n n and n devices.47 Stage using two n n devices. 4. (b) small signal equiva lent of (a). VCC RD R C1 Q2 v out Q1 v in Figure 4. The carriers ow from the emitter to th e collector and are controlled by the base. and collector. and r2 a ear in arallel. the base emitt er junction is forward biased and the base collector junction reverse biased (fo rward active region). Such observations sim lify the analysis (Cha ter 5). emitter. Figure 4.7 Cha ter Summary 161 VCC R C1 RC Q1 v in R C2 v out Q2 v in rπ1 vπ 1 g m1 rπ2 vπ 1 r O1 vπ 2 g m2 v π2 r O2 v out R C2 (a) (b) Figure 4. Note that rO1 .46(b) de icts the equivalent circuit. The bi olar transistor consists of two n junctions and thre e terminals: base. 4. 2007 at 13:42 161 (1) Sec.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Show that the circuit de icted in Fig. Carriers injected by the emitter into the base a roach th ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ .47 has the same small signal model as t he above am li er. 4. 2006] June 30.

e edge of collector de letion region and ae swe t away by the high electric eld. .

Plot the voltage gain as a function of x.2. 7. determine VB such that IX = 1:2 mA.1(b) is necessary to achieve a voltage gain of 15? 2.49.16 A. 4 Physics of Bi olar Transistors The base terminal must rovide a small ow of carriers. The large signal model of the bi olar transisto r consists of an ex onential voltage de endent current source tied between the c ollector and emitter.1(a) is constructed with K = 20 mA/V. The small signal models of n n and n tra nsistors are identical. If the base collector junction is forward biased. (b) With the value of VB found in (a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4.cls v. and an out ut resistance. 4. The ratio of collector curre nt and the base current is denoted by . ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ . Due to a manufacturing erro r. In the forward active region. 4. unless otherwise stated. A resistance of RS is laced in series with the in ut voltage source in Fig.48 if VBE 1 . 6. VBE 2 = 20 mV. Determine Vout =V in . In the forward active region. In the circuit of Fig. a resistance tied between the base and emitter. What value of load resistance in Fig. and a diode (accounting for the base current) tied between the base and emitter. 3. In the circuit of Fig. it is observe d that the collector currents of Q1 and Q2 are equal I C1 Q1 V BE1 V BE2 I C2 Q2 Figure 4.16 A. the base width of a bi olar transistor has increased by a factor of two. (a) If IS 1 = 2IS 2 = 5 10.50. Su ose the voltage de endent current source o f Fig. 2006] June 30. 4. 4. Determine the ratio of transistor cross section areas if the other device arameters are identical. Problems In the following roblems. IS 1 = IS 2 = 3 10. the bi ola r transistor exhibits an ex onential relationshi between its collector current and base emitter voltage. 1. 2007 at 13:42 162 (1) 162 Cha . Re eat Problem 2 but assuming that rin and K are related: rin = a=x and K = bx. 4. Consider the circuit s hown in Fig. some of which go to the em itter and some others recombine in the base region. The transconductance of a bi olar transistor is given by gm = IC =VT and remains inde endent of the device dimensions. (a) Calculate VB such that IX = 1 mA. The small signal m odel of bi olar transistors consists of a linear voltage de endent current sourc e. a bi olar transistor beh aves as constant current source. How does the collector current change? 5. choose IS 3 such that IY = 2:5 mA. 4.48. the bi olar transistor enters sat uration and its erformance degrades. assume the bi olar transisto rs o erate in the active mode.

In the circuit of Fig.52.51. 4.53 if IS = 6 10. and only a single voltage source.52 11. 2007 at 13:42 163 (1) Sec. Assuming that only integer m ulti les of a unit bi olar transistor having IS = 3 10. 4.cls v. 10.51 of the active region.49 RC IX Q1 VB Q2 V CC = 2. Calculate VX in Fig.16 A. R e eat Problem 7 if VCC is lowered to 1. RC R1 10 k Ω 1 kΩ V CC = 2 V Q1 Figure 4. is available (Fig. 12.50 (b) What value of RC laces the transistors at the edge of the active mode? 8. Assume IS = 5 10. VB . An integrated circuit requi res two current sources: I1 = 1 mA and I2 = 1:5 mA.5 V Figure 4. 4.16 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9. Consider the circuit shown in Fig .16 A can be laced in ar allel.5 V. Assum e IS = 3 10.54). 4. de termine the maximum value of VCC that laces Q1 at the edge of saturation. construc t .7 Cha ter Summary 163 IX Q1 VB Q2 Q3 IY Figure 4. 4. Calculate the value of VB that laces Q1 at the edge RC 500 Ω V CC = 2 V Q1 VB Figure 4. 2006] June 30.16 A.

VB = 800 mV and RB 16. The base emitter junction of a transistor is driven by a constant volt age. 2007 at 13:42 164 (1) 164 Cha . I2 = 0:3 mA. 4. Co nsider the circuit shown in Fig. If 1 = 2 = 100 and IY Q1 Q2 VB Figure 4. IC R1 Q1 VB Figure 4.56. = 4 10. R1 = 5 k . 4 Physics of Bi olar Transistors Q1 1.5 V X 1 kΩ V CC = 2 V Figure 4. 4. IS 1 = 2IS 2 IX R1 = 10 k . 4.16 A.54 the required circuit with minimum number of unit transistors. Calculate the collector current.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.55.16 A. In the circuit of Fig. determine VB such that IC = 1 mA.55 15.56 . IS 2 = 5 10.55. 4. IS 1 = 3 10. and VB = 800 mV. and I3 = 0:45 mA. Re eat Problem 12 for three current sources I1 = 0:2 mA. Su ose a voltage source is a lied between the base and collector.56. com ute VB such that IX = 1 mA. In the circuit of Fig. assuming = 100 and IS = 7 10. 18. 14. Calculate IX and IY . 2006] June 30. 17. If R1 = 10 k . 13.16 A.53 I1 I2 VB Unit Transistor Figure 4. If the device o erates in the forward active ¡ . 1 = 2 = 100. In the circuit de icted in Fig.1 6 A.

R1 = 5 k .

e.) 19.cls v. = 100.5 V 1 kΩ V CC = 2. Nonetheless.16 A must rovide a transconductance of 1=13 . 10 A Q1 1 kΩ (a) V CC = 2 V Q1 ¡ ¡ ¡ ¡ . (Neglect the Early effect. A transistor with IS = 6 10.5 V 10 A 1 kΩ RC V CC = 2. If a bi olar device is biased a t IC = 1 mA. Determine the o erating oint and the small signal model of Q1 for each of t he circuits shown in Fig.16 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Most a lications require that the transconductance of a tran sistor remain relatively constant as the signal level varies.g. Determine the o erating oint and the small signal model of Q1 for ea ch of the circuits shown in Fig.58.. ro er design ensures negligible variation. and VA = 1.5 V Q1 Q1 0. and VA = 1. Assume IS = 8 10. 4. gm = IC =VT does vary. What base emitter voltag e is required? 20. what is the largest change in VBE that guarantees only 10 variation i n gm ? 21. 4. 2006] June 30.7 Cha ter Summary 165 region. RC 50 Ω RC V CC = 2. Assume IS = 8 10.57 22.57.16 A. rove that a change in base collector voltage results in no change in th e collector and base currents.8 V (a) Q1 (b) (c) Figure 4. since t he signal changes the collector current. 4. Of course. 2007 at 13:42 165 (1) Sec. = 100. 10.

58 IC = IS ex VBE .1 kΩ (b) V CC = 2 V V CC = 2 V Q1 1 mA 1 mA V CC = 2 V Q1 (d) (c) Figure 4. Construct the small signal model of the device i f IC is still equal to IB . A ctitious bi olar transistor exhibits an IC VBE characteristic given by . ¡ ¡ 23.119) where n is a constant coef cient. nV T (4.

Assuming IS RC 2 kΩ = 1 10.8 V V CC = 2.cls v. The collector voltage of a bi olar tran sistor varies from 1 V to 3 V while the base emitter voltage remains constant. (4. In the circuit of Fig. In Problem 27. w e wish to decrease VB to com ensate for the change in IC . 4.59 VA = 5 V.5 to 3 V. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Construct the small signal model of the device i f IC is still equal to IS ex VBE =VT . 4. 29. IS = 5 10.5 V Figure 4. 4 Physics of Bi olar Transistors 24. In the circuit of Fig. determine the change in the collector current of Q1 .17 A.17 A. VCC changes from 2. Determine the new val ue of VB .120) where a is a constant coef cient. 27.59. Consider the circuit shown in Fig. Determine VX for (a) VA = 1.17 A and V CC Q1 0.8 V Figure 4. where I1 is a 1 mA ideal cur rent source and IS = 3 10. 2006] June 30.60.61. VA = 5 V. W hat Early voltage is necessary to ensure that the collector current changes by l ess than 5? 26. 2007 at 13:42 166 (1) 166 Cha .60 28.61 ¡ ¡ ¡ . I1 Q1 VB V CC = 2 V Figure 4. and (b) RC 1 kΩ X Q1 V B = 0. A ctitious bi olar transistor exhibits the following relationshi between its base and collector currents: 2 IC = aIB . 25.

5 V. (b) If VA = 5 V. determine VB such that IC = 1 mA.(a) Assuming VA = 1. determin e VB such that IC = 1 mA for a collector emitter voltage of 1. ¡ .

4. 32.65.5 V Q1 Figure 4. 34.16 A and VA = 1. If IS = 5 10.63.g. In the circu it of Fig. by how much can VB increase? 33. What val ue of VA guarantees an out ut resistance of greater than 10 k . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. e. Ass ume IS = 2 10. 2007 at 13:42 167 (1) Sec. 4.cls v. 4.65 ¡ ¡ ¡ ¡ .16 A a nd VA = 1.64 collector base forward bias of 200 mV. where IS = 6 10. VA = 1.. calculate the m aximum value of VCC that roduces a RC 1 kΩ V CC Q1 Figure 4. (b) If we allow soft saturation.62 and VA = 8 V for each device. 4. A bi olar current source is designed for an out ut current of 2 mA. construct the small signal model of the equivalent transistor. and = 100 in Fig. What is the maximum value of RC if the collector base must ex erience a forward bias of less than 200 mV? 100 k Ω RB RC V CC = 2.7 Cha ter Summary 167 30.8 V Figure 4. 31. Assume IS = 7 10. 2 kΩ RC V CC = 2. 4. n identical transistors are laced in arallel.17 A. a collector base forward bias of 200 mV.5 V Q1 VB Figure 4.64.63 (a) Determine VB such that Q1 o erates at the edge of the active region.16 A V B = 0. Consider the circuit shown in Fig. For the circuit de icted in Fig.62.

68 38.68.69 if IS 50 k Ω = 2 10.66 36. 2007 at 13:42 168 (1) 168 Cha .7 V ¡ ¡ ¡ ¡ .16 A and VA = 1. 4 Physics of Bi olar Transistors 35. what is the collector current? Q1 VB 1 kΩ V CC = 2.16 A. Consider the circuit shown in Fig. = 100 and VA = 1. calculate IX in Fig.7 V Q2 V CC IX 2V Figure 4. RB 1.17 A and = 100.5 V Figure 4.67. If IS 1 = 3IS2 = 6 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. where IS = 5 10. 2006] June 30.66. 4. 4.67 37. 4. Determine the collector current of Q1 in Fig. Calculate the value of IS suc h that the base collector junction is forward biased by 200 mV. RC R 9 kΩ V CC = 2.82 V Q1 1. In the circuit of Fig. 0. 4.5 V 1 kΩ Q1 Figure 4. If VB is chosen to forward bias the base collector junction by 200 mV.

4. 4. If = 100.72? Assume IS = 8 10. What is the value of that laces Q1 at the edge of the active mode in Fig. 40. it is observed that IC = 3 mA. 42.Q1 V CC IC 2V Figure 4. .69 39. In the circuit of Fig.71 such that Q1 o erates at the edge of the active mode. 41. 4.70. calcul ate IS . Determine the value of IS in Fig.17 A.73 if IS = 3 10. 4. Calculate the collecto r current of Q1 in Fig.16 A.

Q1 1.cls v. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V 20 ¡ . 2007 at 13:42 169 (1) Sec.74.17 A. 4.72 1 kΩ V CC Q1 2.71 100 k Ω RB Q1 V CC 1 kΩ 1.7 Cha ter Summary 169 23 k Ω RB Q1 V CC IC 1.7 V Q1 V CC 2. Assume IS = 3 10. 4.5 V Figure 4. and VA = 1.2 V RC V CC 2V 2 kΩ Figure 4. Determine the o erating oint and the small signal model of Q1 for each of t he circuits shown in Fig. = 100.5 V 1V Figure 4.5 V Figure 4.73 43.70 Q1 V B = 1.

17 A. Assume IS = 3 10.17 A.Q1 V CC 2. Calculate VX for (a) VA = 1. In the circuit of Fig. 45. ¡ .74 44. and VA = 1. = 100. IS = 5 10.76.5 V 1 kΩ (a) A V CC 2 kΩ (c) 2. 4. and (b) VA = 6 V. 4. Determine the o erating oint and the small signal model of Q1 for each of t he circuits shown in Fig.75.5 V 500 (b) Ω Figure 4.

5 V 0.5 V V CC Q1 2. 4. What is the required Early voltage? 47.7 V X V CC 500 2. A n current source must rovide an out ut current of 2 mA with an out ut r esistance of 60 k . 48. 2006] June 30. Re eat Problem 46 fo r a current of 1 mA and com are the results.cls v. 4 Physics of Bi olar Transistors V CC Q1 2. 2007 at 13:42 170 (1) 170 2 kΩ 5 kΩ Cha .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 V .75 Q1 1.77. Q1 1.5 V 2 A (a) (b) (c) Figure 4.5 mA V CC Q1 2.5 V Ω Figure 4. Su ose VA = 5 V in the circuit of Fig.76 46.

1 mV. = 100 and VA = 1. what is the change in VX ? (c) Construct the small signal model o f the transistor. 4. and I1 = 2 mA.X V CC 3 kΩ 2. Q1 VB X I1 V CC 2. where IS = 6 10.77 (a) What value of IS laces Q1 at the edge of the active mode? (b) How does the result in (a) change if VA = 1? 49. In the circuit of Fig. The terminal currents in the small signal mo del of Fig.16 A.79. Consider the circuit de i cted in Fig.5 V Figure 4.40.78. 4. ¡ ¡ ¡ .43 do not seem to agree with those in the large signal model of Fi g. 51. 4. VA = 5 V. 50.5 V Figure 4. Ex lain why this is not an inconsistency. 4.78 (a) What value of VB yields VX = 1 V? (b) If VB changes from the value found in (a) by 0.

52.5 V RB Q1 RE Q1 V CC RC 2.5 V Q1 V CC RC 2. (b) Calculate the transconductance of the transistor.5 V 300 Ω V CC 1 kΩ (c) 2. VA = 1. = 100.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. Assume IS = 5 1 0. Determine the regio n of o eration of Q1 in each of the circuits shown in Fig.80. 2006] June 30.cls v. 2007 at 13:42 171 (1) Sec.16 A.5 mA V CC Q1 500 Ω 2.5 V Figure 4. 4. RE Q1 V CC RC 2.5 V (a) (b) RE 0.7 Cha ter Summary 360 k Ω 171 RB Q1 V CC 4 kΩ 2.5 V (d) (e) ¡ .79 (a) Determine IS such that Q1 ex eriences a collector base forward bias of 200 m V.

16 A.81 (a) We wish to forward bias the collector base junction of What is the maximum a llowable value of Vin ? Q2 by no more than 200 mV. ¡ ¡ . where. Consider the circuit shown in Fig. and RC = 500 . IS 1 2 = 50.5 V Figure 4.Figure 4.80 53. Q1 V in Q2 Vout RC V CC = 2.81. = 3IS2 = 5 10. 4. 1 = 100. VA = 1.

82 but for art (a). 85 for 0 Vin 2:5 V.83. ¡ ¡ . Re eat Problem 57 for the stage de icted in Fig. In the circuit of Fig. n = 3:5 V.17 A. determine the minimum allowable value of Vin .86. 54. n = 50.16 A. 4. 57. VA.5 V Figure 4.84. calculate the small signal arameters of Q1 and Q2 and constr uct the equivalent circuit. VA.16 A. IS. n n = 100. calculate the small signal arameters of Q1 and Q2 and construct the equivalent circuit.5 V V in Figure 4. Q1 V in Q2 Vout RC V CC = 2. n n = 5 10. IS 1 = 2IS2 = 6 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. assume IS. 2007 at 13:42 172 (1) 172 Cha .5 V Figure 4. RC Q1 Vout Q2 1 = 80 and 2 = 100. 2006] June 30. What value of Vin laces the transistor at the edge of satur ation? 58. n = 8 10. RC Q1 V in Q2 Vout V CC = 2. Verify that Q1 o erates in the active mode. SPICE Problems In the following roblems.87 for 0 Vin 1:8 V. Ex lain the d ramatic difference between the two. 4.cls v. 4. 4.n n = 5 V. 4 Physics of Bi olar Transistors (b) With the value found in (a). V CC = 2.82 55. Plot the in ut/out ut characteristic of the circuit shown in Fig. 4. At what value of Vin does Q1 carry a collector current of 1 mA? 59. Plot IC 1 and IC 2 as a fu nction of Vin for the circuits shown in Fig. Re eat Problem 53 for the circuit illustrated in Fig. Re eat Problem 53 for the circuit de icted in Fig.84 (a) What value of Vin yields a collector current of 2 mA for Q2 ? (b) With the v alue found in (a).83 56.

.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. 4.89 for 0 V in 2:5 V.5 V Figure 4.1 for Q1 ? RC 1 kΩ Vin 2 V. 2006] June 30.85 V CC = 2.87 60.88 61.5 V V in Q2 V CC = 2.9 V V in V CC = 2. Plot the in ut/out ut characteristic of the stage shown in Fig.7 Cha ter Summary 173 RC 1 kΩ Vout Q1 V B = 0. 2007 at 13:42 173 (1) Sec. Plot the in ut/out ut characteristic of the circuit illustrated in Fig.86 I C2 I C1 V in Q1 Q3 V CC = 2.88 for 0 What value of Vin yields a transconductance of 50 .5 V Vout Q1 V in Q2 Figure 4. 4.cls v.5 V (a) (b) Figure 4. At what value of Vin do Q1 and Q2 carry equal collector currents? Can . V CC = 2.5 V V in 1 kΩ Q1 Vout Figure 4.

you ex lain this result intuitively? .

2007 at 13:42 174 (1) 174 Cha .cls v.89 .5 V 1 kΩ Figure 4. 2006] June 30. 4 Physics of Bi olar Transistors 1 kΩ V CC = 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V V in Q1 Q2 Vout 1.

What other as ects of an am li er’s erformance are im ortant? Three arameters that readily come to mind are (1) ower dissi ation (e.cls v. General Conce ts In ut and Out ut Im edances Biasing DC and Small−Signal Analysis O erating Point Analysis Sim le Biasing Emitter Degeneration Self−Biasing Biasing of PNP Devices Am lifier To ologies Common−Emitter Stage Common−Base Stage Emtter Follower Building the foundation for the remainder of this book.1 General Considerations Recall from Cha ter 4 that a voltage controlled current source along with a load resistor can form an am li er. Most of the conce ts introduced here are invoked again in Cha ter 7 (MOS am li ers).. The reader is therefore encouraged to take frequent breaks and absorb the material in small doses. 175 ¡ ¡ ¡ ¡ . because it determines the battery lifetime in a cell hone or a digital camera). we now deal with am li er circuits em loying such devices. 1 Exce tions are described in Cha ter 12.” vout =vi n .g.. some am li ers in a cell hone or analog to digital converters in a digital camera must o erate at high frequencies). (2) s eed (e.. Since mo st electronic circuits both sense and roduce voltage quantities. the front end am li er in a cell h one or a digital camera rocesses small signals and must introduce negligible no ise of its own).g. an am li er roduces an out ut (voltage or current) that is a magni ed version of the in ut (voltage or current).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. this cha ter is quite lo ng. our study of cell hones and digital cam eras in Cha ter 1 indicates the extremely wide usage of am li cation. 2006] June 30. This cha ter rocee ds as follows. motivating u s to master the analysis and design of such building blocks. 5. While the eld of microelec tronics involves much more than am li ers. In general. 2007 at 13:42 175 (1) 5 Bi olar Am li ers With the hysics and o eration of bi olar transistors described in Cha ter 4.1 our discussio n rimarily centers around “voltage am li ers” and the conce t of “voltage gain. (3) noise (e.

. The ideal in ut im edance is therefore in nite. the circuit must behave as a voltage source. A t the out ut. At the in ut.1 An am li er with a voltage gain of d a lies the am li ed out ut to a n be modeled with a voltage source es resistance of 200 .cls v. the in ut and out ut (I/O) im edances of an am li er lay a critical role in its ca ability to interface with receding and following stages.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In reality. the ideal out ut im edance is equa l to zero. the I/O im edances of a voltage am li er may considerably d e art from the ideal values. sense a voltage without disturbin g (loading) the receding stage.1(a)]. Assume the micro hone ca having a 10 mV eak to eak signal and a seri the s eaker can be re resented by an 8 resis .1 In ut and Out ut Im edances In addition to the above arameters. A v = 10 200 Ω 10 mV vm Rm 8Ω (a) 200 Ω vm Rm R am v1 R in v am RL 8 Ω v out (b) (c) ¡ ¡ ¡ ¡ Exam le 5. 2006] June 30.1. requiring attention to the interface with other sta ges. i. The following exam le illustrates the issue.e. deliver a const ant signal level to any load im edance. 2007 at 13:42 176 (1) 176 Cha . To understand this conce t. i. l et us rst determine the I/O im edances of an ideal voltage am li er. Micro hone Am lifier S eaker 10 senses a signal generated by a micro hone an s eaker [Fig. 5.e. 5 Bi olar Am li ers 5. Also assume tor. the circuit must o erate as a voltmeter.. Thus.

1(b) shows the interface between the micro hone and the am li er.1 (a) Sim le audio system. Solution (a) Figure 5.Figure 5. The voltage . (c) signal loss due to am li er out ut im edance. (b) signal loss due to am li er in ut im edanc e. (b) Determine the signal level delivered to the s eake r if the circuit has an out ut im edance of 10 or 2 . (a) Determine the signal level sensed by the am li er if the circuit has an in ut im edance of 2 k or 500 .

For Ram R vout = R + L vam : L Ram For Ram . (b) Drawing the interface between the am li er and the s eaker as in Fig. nearly 30 loss. 2006] June 30.2) = 500 . a substantial attenuation. we have (5.6) vout = 0:44vam .4) = 10 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. i. (5.1) =2k .e.1(c).5) =2 . only 9 less than the micro hone signal level. (5. 5.3) v1 = 0:71vm. 2007 at 13:42 177 (1) Sec. It is therefore desirable to maximize the in ut im edance i n this case. 5.. v1 = 0:91vm.1 General Considerations 177 sensed by the am li er is therefore given by v1 = R RinR vm : in + m For Rin (5. On the other hand.cls v. (5. for Rin (5.

5. and de ning vX =iX as the im edance. and since all inde endent sources must be set to zero.2 Illustrated in Fig.vout = 0:8vam : Thus. 5. o n the other hand. 5.2. As with the im edance of two terminal devices such as resist ors and ca acitors. nd the ratio of Rm and The im ortance of I/O im edances encourages us to carefully rescribe the method of measuring them. Exercise If the signal delivered to the s eaker is equal to 0:2vm .2(a) is left o en whereas the in ut ort in Fig.2(a). 5. 5. In Fig.2(b) must be shorted to re resent a zero voltage source. Also shown are arrows to denote “looking int o” the in ut or out ut ort and the corres onding im edance. the in u t ort in Fig. RL . 2 Recall that a zero voltage source is re laced by a short and a zero current so urce by an o en. the out ut im edance of the am li er must be minimized. That i s. Since a voltage am li er is driven by a voltage source during n ormal o eration. the method involves a lying a voltage sour ce to the two nodes (also called “ ort”) of interest. ¡ . the out ut remains o en because it is not connected to any ext ernal sources.2(b) is shorted. the rocedure for calculating the out ut im edance is identical to that used for obtaining the Thevenin im edance of a circuit (Cha ter 1). measuring the resulting curren t. The reader may wonder why the out ut ort in Fig. the in ut (out ut) im edance is measured between the in ut ( out ut) nodes of the circuit while all inde endent sources in the circuit are se t to zero.

2 Measurement of (a) in ut and (b) out ut im edances.2 Assuming that the transistor o erates in the forward active region. Exam le 5. we not e that the in ut im edance is sim ly given by vx = r : ix Since r = im edance. VCC RC vX iX rπ vπ RC g vπ m v in Q1 rO (a) (b) Figure 5. 5. Determining the transfer of signals from one stage to the next.3 (a) Sim le am li er stage. 2007 at 13:42 178 (1) 178 In ut Port Cha . For exam le.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the in ut im edance is obtained by a lying a small change in the in ut voltage and measuring the resulting cha nge in the in ut current. (b) small signal model. determine th e in ut im edance of the circuit shown in Fig. 5 Bi olar Am li ers Out ut Port iX iX vx Short vX R out R in (a) (b) Figure 5. the I/O im edanc es are usually regarded as small signal quantities—with the tacit assum tion that the signal levels are indeed small. Solution Constructing the small signal equivalent circuit de icted in Fig. 5. 2006] June 30. The small signal models of semiconductor devices there fore rove crucial here.3(a).3(b). ¡ ¡ ¡ ¡ .cls v.

we often refer to the im edance seen at a node rather than between two nodes (i.. 5 . we conclude that a higher Exercise What ha ens if RC is doubled? To sim lify the notations and diagrams.e. As illustrated in Fig.4. th e test voltage source is a lied between the node of interest and ground. i. at a ort). such a convention sim ly assumes that the other node is the ground.e.7) or lower IC yield a higher in ut =gm = VT =IC . .(5..

5(a).5(b ). Calculate the im edance seen looking into the collector of Q1 in Fig.cls v. gm v = 0. 2006] June 30. rπ vπ g vπ m rO Exam le 5. 5.4 Calculate the im edance seen at the emitter of sim licity.3 v in Q 1 R out R out (a) (b) Figure 5. we note that v = 0. 5. 2007 at 13:42 179 (1) Sec. Exercise What ha ens if a resistance of value R1 is laced in series with the base? Exam le 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Neglect the Early effect for rπ vπ rπ vπ iX vX g vπ m ¡ ¡ . 5.6(a). Solution Setting the in ut voltage to zero and using the small signal model in Fig.1 General Considerations 179 Short R in R out (a) (b) Figure 5.5 (a) Im edance seen at collector.4 Conce t of im edance seen at a node. and hence Rout = rO . 5. VCC v in Q1 Q1 in Fig. (b) small signal model.

(b) small signal model.R out (a) (b) Figure 5.6 (a) Im edance seen at emitter. Setting the in ut voltage to zero and re lacing VCC with ac ground. we arrive at the small signal Solution ¡ ¡ .

3 rO VA = rπ ac ac ac ac 1 gm Figure 5.7): Looking into the base. that is.cls v.6(b). we see 1=gm if the base is (ac) grounded and the Earl y effect is neglected.8) That is.iX : r = . as ex lained in Section 4.7 Summary of im edances seen at terminals of a transistor. Exercise What ha ens if a resistance of value R1 is laced in series with the collector? The above three exam les rovide three im ortant rules that will be used through out this book (Fig. 5. am li cation ro erties of the transistor such as gm . we see r if the emitter is (ac) grounded. the su ¡ ¡ ¡ ¡ .1. and rO de end on the quiescent (bias) collector current. res ectively. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. More over. r . v gmv + v = . the environment surrounding the device must ensure that the base emitter and base collector junctions are forward and reverse biased.9) = =gm 1=gm. Looking into the emitter. 5. 2006] June 30. Interestingly. Looking into the collector. It is im erative that the reader master these rules and b e able to a ly them in more com lex circuits.vX and (5. 5 Bi olar Am li ers circuit shown in Fig. we have Rout 1=gm. in the absence of si gnals. vX = 1 : iX gm + 1 r Since r (5. 2007 at 13:42 180 (1) 180 Cha .4. Thus.2 Biasing Recall from Cha ter 4 that a bi olar transistor o erates as an am lifying device if it is biased in the active mode. we see rO if the emitter is (ac) grounded.

3 DC and Small Signal Analysis The foregoing observations lead to a rocedure for the analysis of am li ers (and many other circuits). 5.1. Called the “dc analysis” or “bias analysis. ¡ ¡ .” this ste determi nes both the region of o eration (active or saturation) and the small signal ar ameters of 3 While beyond the sco e of this book. First. we com ute the o erat ing (quiescent) conditions (terminal voltages and currents) of each transistor i n the absence of signals.rrounding circuitry must also set (de ne) the device bias currents ro erly. it can be shown that the im edance seen a t the emitter is a roximately equal to 1=gm only if the collector is tied to a relatively low im edance.

must be set to zero for small signal an alysis. we analyze the res onse to signal sources while constant sources ar e set to zero. we determine th e effect of constant voltages and currents while signal sources are set to zero. voltage and cur rent sources that do not vary with time. From another oint of view. 2006] June 30. Some iter ation between the two ste s may often be necessary so as to converge toward the desired behavior.” i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. while establishing ro er bias oints.9 summarizes these conce ts. under what conditions can we re resent the devices w ¡ ¡ ¡ ¡ ¡ ¡ ¡ . study the res onse of the circuit to small signals and com ute quantities such as the voltage gain an d I/O im edances. DC Analysis Small−Signal Analysis VCC R C1 V CB V BE I C1 I C2 Short O en v in v out Figure 5. we erform “small signal analysis..4. For exam le.8 Bias and signal levels for a bi olar transistor. How do we differentiate between small signal and large signal o erations? In other words. as mentioned in Section 4. Second.9 Ste s in a general circuit analysis. 5. the small signal behavior of the circuit is studied to verify the required erformance. Fig. all constant sources. We should remark that the design of am li ers follows a similar rocedure .e. We therefore gro und all constant voltage sources4 and o en all constant current sources while co nstructing the smallsignal equivalent circuit..4. and second. 2007 at 13:42 181 (1) Sec.cls v. the su ly voltage is constant and. the t wo ste s described above follow the su er osition rinci le: rst. V BE Bias (dc) Value t IC Bias (dc) Value t Figure 5. lays no role in the res onse to small signals. It is im ortant to bear in mind that small signal analysis deals with only (smal l) changes in voltages and currents in a circuit around their quiescent values. 5. the circuitry around the transistor is designed to establish ro er bias condit ions and hence the necessary small signal arameters.8 illustrates the bias and signal com on ents of a voltage and a current. First. i.1 General Considerations 181 each device. Second. As an exam le.e. Thus. Figure 5.

This criterion is justi ed because the am lifying ro erties of the transistor such as gm and r are 4 We say all constant voltage sources are re laced by an “ac ground. In Fi g. for exam le. 5.” ¡ . we say the circuit o erates in the smallsignal regime.ith their small signal models? If the signal erturbs the bias oint of the devi ce only negligibly. the change in IC due to the signal must remain small.8.

then (5. with t he understanding that the other node is ground. 5 Bi olar Am li ers considered constant in small signal analysis even though they in fact vary as th e signal erturbs IC . we will em loy some sim li ed notations and symbols. we introduce various am li er to ologies and examine their small signal behavior. 5.10 is an exam le where the battery serving as the su ly voltage is re laced with a horizontal bar labeled VCC .5 A student familiar with bi olar devices constructs the circuit shown in Fig.2 O erating Point Analysis and Design It is instructive to begin our treatment of o erating oints with an exam le. we consider 10 variation in the collector current as the u er bound for sma ll signal o eration. This hase of our study r equires no knowledge of signals and hence the in ut and out ut orts of the circ uit. the student has forgotten to bias the transistor. That is.5 Also.10 Notation for su ly voltage.16 A and the eak value of the micro hone signal is 20 mV. VCC RC 1 kΩ Vout Q1 Vin Figure 5. 5. we begin with the DC analysis and design of bi olar stages.11 Am li er driven directly by a micro hone.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2007 at 13:42 182 (1) 182 Cha . the in ut voltage source is sim li ed to one node called Vin . but as a rule of th umb.1 1 and attem ts to am lify the signal roduced by a micro hone. Exam le 5. 5. (The micro hone does not roduce a dc out ut). 2006] June 30. Illustrated in Fig. If IS = 6 10. Solution Unfortunately. Next. If Vin (= VBE ) reaches 20 mV. In drawing circuit diagrams hereafter. a linear re resentation of the transistor holds only if the small signal arameters themselves vary negligibly. In this cha ter. The de nition of “ne gligibly” somewhat de ends on the circuit and the a lication. VCC RC Q1 Vout V in V in Q1 VCC RC Vout Figure 5. dev elo ing skills to determine or create bias conditions.10) V IC = IS ex T V BE ¡ ¡ ¡ ¡ . determine the eak value of the out ut signal.

.5 The subscri t CC indicates su ly voltage feeding the collector.

1.65 V is laced in series wit h the micro hone.12.5 V RC 1 kΩ Vout Q1 Figure 5.12) The circuit generates virtually no out ut because the bias current (in the absen ce of the micro hone signal) is zero and so is the transconductance.5 modi es the circuit a s shown in Fig. As mentioned in Section 5. so does Vout . Exercise Re eat the above exam le if a constant voltage of 0. Ex lain why the student needs to learn more about biasing. the student in Exam le 5. connecting the base to VCC to allow dc biasing for the bas e emitter junction. Another im ortant issue relates to the value of VBE : with VBE = VCC = 2:5 V.15 A: This change in the collector current yields a change in the out ut voltage equal to (5. The fundamental issue here is that the signal generated by the micro hone is sho rted to VCC . VCC maintains the base voltage at a constant value.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and set the collector current to the value r equired in the a lication. Let us return to the above exam le for a moment. enormous currents ow into the transistor. 5.12 V: ¡ . biasing seeks to ful ll two objectives: ensure o er ation in the forward active region.2. Since VBE remains constant.2 O erating Point Analysis and Design 183 = 1:29 10.6 Having realized the bias roblem. rohibiting any change introduced by the micro hone. 2006] June 30. leading to no am li cation. 5. Solution Exercise 10. 2007 at 13:42 183 (1) Sec.cls v. Acting as an ideal voltage source. Exam le 5.12 Am li er with base tied to VCC .11) RC IC = 1:29 (5. VCC = 2.

Does the circuit o erate better if a resistor is laced in series with the emitt er of Q1 ? .

5. Instead. Our objective is to determine the terminal voltages and currents of Q1 and obtain the conditions that ensure biasing in the active m ode.13 Use of base resistance for base current ath. we require the collector voltage to remain above the base voltage: . ¡ ¡ ¡ ¡ . 5 Bi olar Am li ers 5.17) Calculation of VCE is necessary as it reveals whether the device o erates in the active mode or not.1 Sim le Biasing Now consider the to ology shown in Fig. 2007 at 13:42 184 (1) 184 Cha . Since t he voltage dro across RB is equal to RB IB .16) (5. In summary. using the sequence IB ! IC ! VCE .2. How do we analyze this circuit? One can re lace Q1 with its large signal mo del and a ly KVL and KCL. For exam le. VCC . . we recall that the base emitter voltage in most cases falls in the range of 700 to 800 mV and can be considered relatively constant. VCCR VBE RC VBE : B (5.cls v.15) (5. and Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. RB . but the resulting nonlinear equation(s) yield little intuition. we have com uted the im ortant terminal currents and voltages of Q1 . IC = VCCR VBE . to avoid saturation com letely. we write (5. 2006] June 30. IB = VCCR VBE : B With the base current known.18) The circuit arameters can therefore be chosen so as to guarantee this condition .13) . While not articularly interesting here.13. RC IC . B note that the voltage dro hence obtain VCE as VCE = VCC . = VCC . so as to forward bias the base emitter junction.14) (5. where the bas e is tied to VCC through a relatively large resistor. we have VCC RB Y IC X IB Q1 RC RB IB + VBE = VCC and hence (5. VCCR VBE RC : B across RC is equal to RC IC .

The reader may wonder about the error in the above calculations due to the assum tion of a constant VBE in the range of 700 to 800 mV. .the emitter current is sim ly equal to IC + IB . An exam le clari es this issue.

IB = VCCR VBE B 17 A: It follows that (5.23) . That is. 2007 at 13:42 185 (1) Sec. 5.26) are quite close.14. determine the collector bias current. Thus. (5.5 V 100 k Ω 1 kΩ = 100 and RB RC Y IC X IB Q1 Figure 5.21) VBE = VT ln IC IS = 852 mV. Since IS is relatively small. we calculate a new value for VBE : (5. and iterate to obtain more accurate results. Assume IS = 10.22) (5.19) (5. Verify that Q1 o erates in the forward active region. we use VBE = 800 mV as an initial guess and write Eq.7 For the circuit shown in Fig. we consider IC enou ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.25) IC = 1:65 mA: Since the values given by (5. 2006] June 30.2 O erating Point Analysis and Design 185 Exam le 5. (5. we surmise that the base emitter voltage required to carry ty ical current level is relatively large.21) and (5.20) IC = 1:7 mA: With this result for IC . VCC = 2. IB = VCCR VBE B = 16:5 A and hence (5.cls v. 5.14 Sim le biased stage.14) as Solution .17 A.24) (5.

gh and iterate no more. RC IC = 0:85 V.16).27) (5. (5. we have (5.26) = 1:65 mA accurate VCE = VCC .28) . Writing (5.

(5. Second. Figure 5.13 merits a few remarks. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. driving the transistor toward heavy saturation. In the above e xam le. we recognize from Eq.2.52. 1+ 2 if the base current is negligible. (5.cls v.13 is rarely used in ractice. 5. we return to the fundamental rel ationshi IC = IS ex VBE =VT and ostulate that IC must be set by a lying a well de ned VBE . roviding a baseemitter voltage equal to VX = R R2 R VCC . Exercise What value of RB rovides a reverse bias of 200 mV across the base collector jun ction? The biasing scheme of Fig. 2007 at 13:42 186 (1) 186 Cha . then IC rises to 1.15) that IC heavily de ends on . 2006] June 30. a arameter that may change considerably. First. in low voltage design—an increasingly common ara digm in modern electronic systems— the bias is more sensitive to VBE variations am ong transistors or with tem erature .2 Resistive Divider Biasing I n order to su ress the de endence of IC u on . the effect o f VBE “uncertainty” becomes more ronounced at low values of VCC because VCC . where R1 and R2 act as a voltage div ider. Thus. 5.29) ¡ ¡ ¡ .VBE de termines the base current. 5 Bi olar Am li ers a value nearly equal to VBE . if increases from 100 to 120. the to ology of Fig. For these reasons. Thus. The transistor therefore o erates near the edge of active and saturation modes.15 de icts an exam le.98 mA and VCE falls to 0.

Nonetheless. = 100.16 if IS = 10.17 A and base curr ent is negligible and the transistor o erates in the active mode. Verify that the Determine the collector current of Q1 in Fig. Figure 5. Exam le 5. 5.8 .15 Use of resistive divider to de ne VBE . the design must ensure that the base cu rrent remains negligible. 1 2 T VCC R1 Y X R2 RC IC Q1 (5.IC = R VCCIS ex R +2 R V .30) a quantity inde endent of .

IB ? We also note that BE IC = IS ex and VV T = 231 A . IB must be negligible with res ect to the current owing through R1 and R2 : VCC (5.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5.31) (5.35) Is the base current negligible? With which quantity should this value be com are d? Provided by the resistive divider.33) (5. Neglecting the base current of Q1 .34) IB = 2:31 A: (5.16 Exam le of biased stage.36) R1 + R2 : This condition indeed holds in this exam le because VCC =R1 + R2 = 100 A 43IB . 2007 at 13:42 187 (1) Sec. we have Solution VX = R R2 R VCC 1+ 2 = 800 mV: It follows that (5.32) (5. 2006] June 30.2 O erating Point Analysis and Design VCC = 2.5 V 17 k Ω 187 R1 RC Y 5 kΩ IC X 8 kΩ Q1 R2 Figure 5.

VCE = 1:345 V. Let us r e lace the voltage divider with a Thevenin . and hence Q1 o erates in the active region. requiring veri cation at the end. (5. But what if the end result indicates that IB is not negligible? We now analyze the circuit without this assum tion.37) Exercise What is the maximum value of RC if Q1 must remain in soft saturation? The analysis a roach taken in the above exam le assumes a negligible base curre nt.

we rewrite (5. noting that VThev is equal to the o en circuit out ut vo ltage (VX when the am li er is disconnected): VCC R1 VCC RC IC X R2 R1 VCC R2 VThev Q1 V Thev R1 R2 R Thev X IB VCC RC IC Q1 Figure 5. VT ln IC R 1 .17).40) IC = IS ex VThev . VThev = R R2 R VCC : 1+ 2 Moreover.42) IS Thev and begin with a guess for VBE = VT l nIC =IS .39) VX = VThev . but the ex onential de endence in IB = VThev . iterations rove useful here. Calculate the collector current of Q1 in Fig.cls v.17 Use of Thevenin equivalent to calculate bias. 5 Bi olar Am li ers equivalent (Fig. 2007 at 13:42 188 (1) 188 Cha . (5.18(a).38) RThev = R1 jjR2 : The sim li ed circuit yields: (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (5. 5. IB RThev and (5. 2006] June 30. The iteration then follows the sequence VBE ! IB ! IC ! VBE ! . RThev is given by the out ut resistance of the network if VCC is set t o zero: (5.41) gives rise to wide uctuations in the intermediate solutions. For this reason.41) Eq. IB RThev : V T (5. As in the revious exam les. 5.41) as This result along with IC = IB forms the system of equations leading to the valu es of IC and IB . Assume ¡ .

17 A.18(b).43) .9 Solution = 100 and IS = 10. Constructing the equivalent circuit shown in Fig. 5.Exam le 5. we note that VThev = R R2 R VCC 1+ 2 (5.

44) RThev = R1 jjR2 = 54:4 k : (5.2 O erating Point Analysis and Design VCC = 2. VBE RThev = 0:919 A: Thus. thereby arriving at t he base current: IB = VThev .cls v.49) (5.5 V 170 k Ω 189 VCC RC R Thev X V Thev IB IC Q1 R1 RC Y 5 kΩ X 80 k Ω IC IB Q1 R2 Figure 5.46) We begin the iteration with an initial guess VBE = 750 mV (because we know that the voltage dro across RThev makes VBE less than VThev ).48) = IB = 91:9 A and VBE = VT ln IC IS = 776 mV: (5.50) . 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 (a) Stage with resistive divider bias.47) (5. 2006] June 30.45) (5. V = 800 mV and (5. IC (5. 2007 at 13:42 189 (1) Sec. (b) stage with Thevenin equiv alent for the resistive divider and CC .

Continuing the iteration. IB = 0:79 A and IC = 79:0 A. still a large uctuation with re s ect to the rst value from above. the ex onential de endence of IC u on the voltage generated by the r esistive divider still leads to substantial bias variations. VBE 766 mV and IC = 63 A. After many iterations.15 makes the bias relatively insen sitive to . so is VX . In other words. 5. thus multi lying the collector cur rent by ex 0:01VBE =VT 1:36 (for VBE = 800 mV). if R2 is 1 higher than its nominal value. The circuit is ther efore still of little ractical value.It follows that IB = 0:441 A and hence IC = 44:1 A. Exercise How much can R2 be increased if Q1 must remain in soft saturation? While ro er choice of R1 and R2 in the to ology of Fig. we obtain VBE = 757 mV. . a 1 error in one r esistor value introduces a 36 error in the collector current. For exam le.

resistor RE a e ars in series with the emitter. an error in VX due to inaccuracies in R1 . 2007 at 13:42 190 (1) 190 Cha . Neglecting the base current. 5 Bi olar Am li ers 5. Here.cls v. To understand the above ro erty. introducing a smaller error in VBE and hence IC .2.” the VCC R1 Y X R2 P RC IC Q1 IE RE Figure 5. R2 . VBE E 1+ 2 E IC . this occurs because RE exhibits a linear (rather than ex onential) IV relationshi . Thus. Also. or VCC is artly “absorbed” by RE . addition of RE in series with the emitter alters many attributes of the circuit. 2006] June 30.3 Biasing with Emitter Degeneration A biasing con guration that alleviates the roblem of sensitivity to and VBE is shown in Fig. yielding V IE = RP 1 =R VCC R R2 R . From a n intuitive view oint.19 Addition of degeneration resistor to stabilize bias oint. we hav e VX = VCC R2 =R1 + R2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . as described later in this cha ter. thereby lowering the sensitivity to VBE . VBE . VP = VX . 5. let us de termine the bias currents of the transistor.19. Called “emitter degeneration.

(5. Calculate the bias currents in the circuit of Fig.54) (5. the difference between VCC R2 =R1 + R2 and VBE is large enough to absorb and swam such variations.52) (5. i.57) . VBE = 100 mV. How can this result be made less sensitive to VX or VBE variations? If the voltage dro across RE . (5.e. then IE and IC remain relativ ely constant.56) (5.17 A.51) (5.20 and verify that Q1 o erates in the forward active regio n.53) if 1.10 Solution We neglect the base current and write VX = VCC R R2 R 1+ 2 = 900 mV: Using VBE (5. Assume = 100 and IS = 5 10.. 5. An exam le illustrates this oint. we have VP = VX . How much does the collector current change i f R2 is 1 higher than its nominal value? Exam le 5.55) = 800 mV as an initial guess.

Eq.60) VBE = VT ln IC IS = 796 mV. 2007 at 13:42 191 (1) Sec. IB 10 A whereas the current owing through R1 and R2 is equal to 100 A.cls v. The collector voltage is given by VY = VCC .5 V 16 k Ω 191 R1 RC Y X 1 kΩ Q1 P RE 100 9 kΩ R2 Ω Figure 5. we conclude that the initial guess is reasonable.62) With the base voltage at 0. 5. Furthermore. an iterative rocedure similar to that in Exam le ¡ . For greater accuracy. Let us now determine if Q1 o erates in the active mode. IC RC = 1 :5 V : (5.20 Exam le of biased stage. 2006] June 30. indicating a good a roximation. the device is indeed in the active region. Is th e assum tion of negligible base current valid? With IC 1 mA.61) (5.57) sugges ts that a 4 mV error in VBE leads to a 4 error in VP and hence IE .58) = 800 mV. The assum tion is therefore rea sonable.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.59) (5. we must reexamine the assum tion of VBE (5. (5. and hence IE IC 1 mA: With this result. Since (5.9 V.2 O erating Point Analysis and Design VCC = 2.

5. 5. and (2) VRE must be large enoug h (100 mV to several hundred millivolts) to su ress the effect of uncertainties in VX and VBE . raising the emitter current by 9 mV=100 = 90 A.21.56). Illustrated in Fig. two rules are ty ical ly followed: (1) I1 IB to lower sensitivity to . which is reasonable because the emitter and collector currents have changed by only 9. 5. we note that this assum tion is equivalent to considering VBE consta nt. ¡ . From Eq. then (5. If R2 is 1 higher than its nominal value. Exercise What value of R2 laces Q1 at the edge of saturation? The bias to ology of Fig.19 is used extensively in discrete circuits and occa sionally in integrated circuits. (5. We may assume that the 9 mV change d irectly a ears across RE .9 can be followed.54) indic ates that VX rises to a roximately 909 mV.

(3) calculate VX = VBE + IC RE with VBE = VT lnIC =IS . VCC R1 + R2 IB .21 so as to rovide a transconductance of 1=52 for Q1 .64) (5.cls v. which in conjunction with (5. we obtain RE = 400 . = 100. The following exam le illustrates the se conce ts. ¡ ¡ . e.5 mA and a VBE of 778 mV. RC IC . For the base current IB = 5 A to be negligible. we A gm of 52 Solution R2 R1 + R2 VCC = VBE + RE IC . we ose the (5. 200 mV.67) VCC . R2 . Assuming RE I C = 200 mV. e. and IS = 5 10. RC IC VX . Assume VCC = 2:5 V. To establish VX = VBE + RE IC = 978 mV. (4) choose R1 and R2 so as to rovide the necessary value of VX and establish I1 IB . 5 Bi olar Am li ers R C Small Enough to Avoid Saturation IC Q1 VRE >> Variations in VX and VBE Figure 5. by a factor of 10. where the base current is neglected.1 translates to a collector current of 0..66) .g. What is the maxi mum tolerable value of RC ? Exam le 5.21 Summary of robust bias conditions. the value of RC is bounded by a maximum that laces Q1 at the edge of saturation. 2007 at 13:42 192 (1) 192 VCC R1 I1 I 1 >> I B R2 RE X IB Y Cha . Design the circuit of Fig.17 A. R1 + R2 = 50 k .. 5. choose a value for VRE IC RE . and VBE . Design Procedure It is ossible to rescribe a design rocedure for the bias to ology of Fig. Thu s.g. 2006] June 30.21 that serves most a lications: (1) decide on a collector bias current that yields ro er small signal arameters such as gm and r . Deter mined by small signal gain requirements.65) (5.11 must have .63) yields R1 = 30:45 k R2 = 19 :55 k : How large can RC be? Since the collector voltage is equal to VCC following const raint to ensure active mode o eration: (5. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (2) based on the ex ected variations of R1 .63) (5.

that is.68) . RC IC 1:522 V: (5.

21 to lower sensitivities do im ose some trade offs.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11 but assuming VRE Exam le 5. It follows that R1 = 1:45 k R2 = 3:55 k : (5. obtaining R1 + R2 (5. i.12 Solution = 500 mV and I1 100IB . Re eat the above exam le if the ower budget is only 1 mW and the transconductan ce of Q1 is not given. As mentioned in Cha ter 4. leading to a low in ut im edance. in low voltage a lications . 2006] June 30. Re eat Exam le 5.cls v. RC 3:044 k : (5. the transistor can tolerate soft saturation. We rewrite (5.64) as VCC R1 + R2 100IB .72) ¡ ¡ ¡ ¡ . Thus. 5. (2) if we choose a very la rge VRE . Let us return to the above exam le and study these issues.e. Exercise The two rules de icted in Fig. thereby limiting the minimum valu e of the collector voltage to avoid saturation. 2007 at 13:42 193 (1) Sec. the collector voltage falls below the base voltage. 400 mV and hence a greater value for RC . then R1 + R2 and hence R1 and R2 are quite small. an overly conservative design faces the following issues: (1 ) if we wish I1 to be much much greater than IB .70) =5k . 5. S ecifically.71) (5. The collector current and base emitter voltage remain unchanged.2 O erating Point Analysis and Design 193 Consequently.. we may allow VY VX .6 3) still holds. then VX (= VBE + VRE ) must be high. u t o about 400 mV of base collector forward bias.69) If RC exceeds this value. VX = VBE + RE IC = 1:278 V and (5. The value of RE is now given by 500 mV=0:5 mA = 1 k . Also.

. VX IC 1:044 k : (5. We com ute the exact in ut im edance of this circuit in Section 5.1.74) As seen in Section 5. leading to RC VCC .11 introduce a low in ut im edance. loading the receding stage. the collector voltage must exceed t his value to avoid saturation.3. the reduction in RC translates to a lower voltage gain .3.1.Since the base voltage has risen to 1.278 V. Also.73) (5. the much smaller values of R1 and R2 here than in Exam le 5.

IC . (5. a critical advantage over the circuit o f Fig. thereby yielding VY = VCC .13 ¡ ¡ ¡ ¡ . if RC increases ind e nitely.22 Self biased stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Called “self biased” because the base curren t and voltage are rovided from the collector. Q1 remains in the active region. IB RB . this stage exhibits many interest ing and useful attributes.. VBE : RC + RB As usual. Exam le 5. Re eat the calculations for RC = 2 k .77) gives (5. VCC RB IB X RC Y IC Q1 Figure 5. 5 Bi olar Am li ers Exercise Re eat the above exam le if VRE is limited to 100 mV. Let us begin the analysis of the circuit with the observation that the base volt age is always lower than the collector voltage: VX = VY .cls v. 5. and = 100.22. 5.e.78) = VT lnIC =IS k Determine the collector current and voltage of Q1 in Fig.17 A. com ute IC . 2007 at 13:42 194 (1) 194 Cha . i. A result of se lf biasing. IS = 5 10.4 Self Biased Stage Another biasing scheme commonly used in discrete and int egrated circuits is shown in Fig. we begin with an initial guess for VBE .22 if RC = 1 k . 5. RC carries a current We now determine the collector bias current by assuming IB equal to IC . RC IC : Also.2. and utilize VBE to im rove the accuracy of our calculations.77) IC = VCC . RB = 10 VCC = 2:5 V. (5. this im ortant ro erty guarantees that Q1 o erates in the active mo de regardless of device and circuit arameters.75) and (5.21. For exam le.76) (5.75) VY = RB IB + VBE = RB IC + VBE : Equating the right hand sides of (5. 5. 2006] June 30.

. .

5. concluding that the initial guess for VBE and the value of IC given by it are reasonably accurate. IC RC VBE . Since RB IB = 81 mV. We also note that RB I B = 154:5 mV and VY = RB IB + VBE 0:955 V. 2007 at 13:42 195 (1) Sec. VBE must be much greater than the unce rtainties in the value of VBE . if RC RB = . (2) RC must be much greater than RB = to lower s ensitivity to .80) is acce table.78) and the above exam le suggest two im ortant guidelines for the d esign of the self biased stage: (1) VCC . we choose RC = 10RB = and rewrite (5. In fact. Exercise What ha ens if the base resistance is doubled? Equation (5.78): IC = 1:545 mA. the 9 mV error is negligible and the value of IC in (5. IC VCCR VBE . then with VBE = 0:8 V. If RC = 2 k . we have from (5. we write VBE = VT lnIC =IS = 791 mV. VBE in the numerator of (5.cls v.2 O erating Point Analysis and Design 195 Assuming VBE Solution = 0:8 V. C (5.80) To check the validity of the initial guess.78) together with the condition RC RB = rovides th e basic ex ressions for the design of the circuit. 2006] June 30. With the required value of IC known from smallsignal considerations. (5. VY 0:881 V.78). Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Com ared with VCC .78) gives IC = 0:810 mA: (5. This result serves as a quick estimate of the transistor bias . then and VY = VCC conditions. (5. .78) as ¡ ¡ .79) and hence VBE = VT lnIC =IS = 807:6 mV.81) Design Procedure Equation (5.

84) The choice of RB also de ends on small signal requirements and may deviate from this value. Design the self bia sed stage of Fig. . but it must remain substantially lower than RC .16 A and = 100. 10 Exam le 5. IC = VCC:1RVBE . That is. 5. 1 C where VBE (5.14 = 1=13 and VCC = 1:8 V.22 for gm IS = 5 10. RC = VCC:1I VBE 1 C R = RC : B (5. Assume ¡ ¡ ..83) (5.82) = VT lnIC =IS .

and . we have IC = 2 mA.2. Circuits using pnp devices follow the same analysis and de sign procedures while requiring attention to voltage and current polarities.86) Also. RC VCC:1I VBE 1 C 475 : R RB = 10C = 4:75 k : (5. VBE = 754 mV.cls v.5 V. 5 Bi olar Am li ers Since gm Solution = IC =VT = 1=13 . (5.87) (5. yielding a collector voltage of 754 mV + 95 mV = 849 mV.85) (5. . 2007 at 13:42 196 (1) 196 Cha .23 Summary of iasing techniques. 5. We illustrate these points with the aid of some examples.88) Note that RB IB = 95 mV. 2006] June 30.5 Biasing of PNP Transistors The dc ias topologies studied thus far incorpo rate npn transistors. R1 I1 RB RC R1 RC Q1 Q1 R2 Sensitive to Resistor Errors RC Q1 RE VRE R2 RB RC Q1 Always in Active Mode Sensitive to β 5. £ £ £ Figure 5. Figure 5.23 summarizes the biasing rinci les studied in this section. Calculate the collector a nd voltage of Q1 in the circuit of Fig.24 and determine the maximum allowa le value of RC for operation in the active mode. Exercise Re eat the above design with a su ly voltage of 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Example 5. IB RB + VEB = VCC : (5.89) .15 Solution The topology is the same as that in Fig. 5.13 and we have.

The transistor enters saturation at VY = VX .92) RC.2 197 IB RB VEB X Figure 5. .24 Simple iasing of pnp stage.max = VCC I.25( ): £ £ £ ¢ Operating Point Analysis and VCC Q1 Y IC RC esign £ ¢ . 2007 at 13:42 197 (1) Sec. we have IB RB as the condition for edge of saturation.93) (5. thus app roaching VX (= VCC . (5. what value of RB places the device at the edge of saturation? etermine the collector current and voltage of Q1 in the circuit of Fig. VY rises.91) The circuit suffers from sensitivity to .. 5.cls v. we assume IB is signi cant and construct the Thevenin equival ent of the voltage divider as depicted in Fig. 5.25(a) . o taining RB = RC.max .94) = IC RC. 5.max Exercise For a given RC . VEB and hence (5. That is.90) . i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IC = VCCR VEB : B (5. since VX = IB RB and VY = IC RC . IC RC. VEB C = RB : From another perspective.max = VCC . VEB ) and ringing Q1 closer to saturation.e. IB = VCCR VEB B and (5. 2006] June 30. If RC is increased. As a general case.

16 Solution VThev = R R1 R VCC 1+ 2 RThev = R1 jjR2 : (5.Example 5.95) (5.96) .

100) RThev As in Example 5. ( ) Thevenin equivalen £ . we equate the voltage drop across R2 to VEB . that is. 5 Bipolar Ampli ers VCC R2 I1 R1 I B VEB X Y IC RC (a) ( ) VCC R Thev IB VEB X V Thev Y IC RC Q1 Q1 VCC .cls v. (5. V CC EB 2 = R1 + RR : Thev It follows that (5.97) V IB = VCC . there y R2 V = V R1 + R2 CC EB £ £ £ £ Figure 5.100) indicates that if IB is signi ca nt. VEB Thev R2 V . some iteration etw een IC and VEB may e necessary.98) (5. 2007 at 13:42 198 (1) 198 Chap.25 (a) PNP stage with resistive divider t of divider and £ £ £ iasing. Equation (5.99) o taining the collector current: R2 R1 + R2 VCC . Adding the voltage drop across RThev and VEB to VThev yields VThev + IB RThev + VEB = VCC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then the transistor ias heavily depends on . if IB I1 . On the other hand. 2006] June 30. RThev .9. VEB : IC = (5.

calculate the collector current and voltage £ . Exercise What is the maximum value of RC is Q1 must remain in soft saturation? Q1 in the £ Example 5.IC = IS R2 VCC exp R + R V : 1 2 (5. (5.101) (5.102) T Note that this result is identical to Eq.17 Assuming a negligi le of ase current.30).

With IB I1 . 5.ase voltage and the drop across RE .cls v. 5. What is the maximum allowa le value of forward active regi on? VCC R2 I1 RE I B VEB X R1 Y IC RC Q1 VRE RC for Q1 to operate in the Figure 5.26 PNP stage with degeneration resistor. Adding to VX the emitter.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. we o tain Solution VX + VEB + RE IE = VCC and hence (5.103) IE = R1 £ £ ¢ £ Operating Point Analysis and esign . 2007 at 13:42 199 (1) Sec.26.2 199 circuit of Fig. we have VX = VCC R1 =R1 + R2 .

maxIC 1+ 2 . we can verify the assumption IB I1 . we can compute a new value for VEB and iterate if necessary. VEB : E R1 + R2 (5.e. 1+ 2 VCC R R1 R = RC. i. VCC R R2 R = VEB + IE RE .VCC R2 . Also. But a more straightforward approach is to recognize that the voltage drop across R2 is equal to VEB + IE R E . with IB = IC = .. (5. Eq.103). In arriving at (5.104) Using IC IE . w e have written a KVL from VCC to ground.104).

The maximum allowa le value of RC is o tained y equating the ase and collector voltages: (5.RC. V : R1 + R2 CC EB 1 (5.105) which yields the same result as in (5.106) (5.104).V R R1 + R2 CC EB : E R It follows that (5.max 2 V .107) RC.108) 1+ 2 £ £ £ £ .max = RE VCC R R1 R R2 V .

etermine the collector current and voltage of Q1 in the self. VCC Q1 IB RB Y IC RC Example 5. RC carries a current approximately equal to IC . 5. Since 1 and hence IC IB .18 X VEB Figure 5. 2006] June 30. and RC to ground. creating VY = RC IC . yield ing Solution VCC = VEB + VX = VEB + RB IB + IC RC £ £ £ £ ¢ . Moreover.iased circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5 Bipolar Ampli ers Exercise Repeat the a ove example if R2 = 1. 2007 at 13:42 200 (1) 200 Chap.27 Self.cls v.ase junction of Q1 . RB . VX = RB IB + VY = RB IB + RC IC .27.iased pnp stage. We must write a KVL from VCC through the emitter.

+ RC (5. and determine a new value for VEB . comput e IC .109) (5.= VEB + RB + RC IC : Thus. VEB .110) (5. Exercise How far is Q1 from saturation? £ £ . (5. As usual.111) CC IC = VRB . since the ase is hig her than the collector voltage. Q1 always remains in the active mode. we egin with a guess for VEB . etc. (5.112) a result similar to Eq. Note that.78).

the circuit is called a “common-emitter” (CE) stage (Fig. the ipolar transistors operate in the active mode. In all cases. seeking to compute its gain and input and output impedances. ipolar transistors operating in the active mode respond to ase-emitter voltage variations y varying their collector current.1( ) and hence the to pology of Fig. The term “common-emitter” is used ecause the emitter terminal is grounded and hence appears in common to the input and output ports.3 Bipolar Ampli er Topologies Following our detailed study of iasing.7 efore proceeding further. 5. the large-signal ehavior of ampli ers also ecomes important in many applications. 5.29). (f) However.cls v. 5. 5. 5. 5.2)-(5. the output signal can e sensed from any of the terminals ( with respect to ground) [Figs. Also. 5. 4. But we note that the input and o utput connections in Figs.3 Bipolar Ampli er Topologies 201 5.4) and the three resulting rules illustrated in Fig. v in v in v in (a) ( ) (c) v out v out v out (d) (e) Figure 5. The n um er of possi ilities therefore falls to four. 2006] June 30. Nevertheless.28 (f) proves of no value as Vout is not a function of the collector current. 6 While eyond the scope of this ook.6 Since the ipolar transis tor contains three terminals. 28(a)(c). We study each carefully.1 pointed to the circuit of Fig. If the input signal is applied to the ase [Fi g. res pectively) so as to avoid confusion in more complex topologies.25 as an ampli er. The a ove o servations reveal three possi le ampli er topologies. The reader is enc ouraged to review Examples (5.28( ) and (e) remain incompati le ecause Vout woul d e sensed at the input node (the emitter) and the circuit would provide no fun ction. 5. 4. 5.28 Possi le input and output connections to a ipolar transisto r.1 Common-Emitter Topology Our initia l thoughts in Section 4. £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ . we may surmise that three possi ilities exist for applying the input signal to the device.28(d)-(f)]. 5. leading to nine possi le com inatio ns of input and output networks and hence nine ampli er topologies. the topology in Fig. as conceptually illustrated in Figs. Similarly. We have encountered an d analyzed this circuit in different contexts without giving it a name.3. we can now delve into different ampli er topologies and examine their small-signal properties. 5. T his property rules out the input connection shown in Fig. we identify the stage a sed on the input and output connections (to the ase and from the collector. 2007 at 13:42 201 (1) Sec.28(a)] and the output signal is sensed at the collector [Fig.28(c) ecause here V in does not affect the ase or emitter voltages.28(d)]. as seen in Chapter 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

RC . It follows that Av = . In order to examine the amplifying properties of the CE stage.4.29 Common-emitter stage.e. We neglect the Early effect for now. the supply voltage node. v in rπ vπ g vπ m v out − RC RC v out Figure 5.114) embodies two interesting and im ortant ro erties of the CE sta ge. Analysis of CE Core Recall from the de nit ion of transconductance in Section 4. Av is ro ortio nal to gm (i.cls v. we have ort and writing a KCL at the £ £ £ ¡ £ ¡ ¡ £ £ .. We deal with the CE ampli er in two phases: (a) analysis of the CE core to underst and its fundamental properties. As explained in Chapter 4. 2007 at 13:42 202 (1) 202 VCC RC Vout Chap.30. VCC . In terestingly. the collector bias current) and the collector resistor.113) . and ( ) analysis of the CE stage including the ias circuitry as a more realistic case.3 that a small increment of V applied to t he ase of Q1 in Fig. the voltage gain of the stage is limited by the su ly voltage. 5.114) Equation (5.29 lowers Vout . A h Let us rst com ute the small signal voltage gain Av collector node. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. shown in Fig. 2006] June 30.30 Small signal model of CE stage. R C and v = vin . acts as an ac ground ecause its value remains constant with time. 5. vout = gm v . 5 Bipolar Ampli ers V in Q 1 Output Sensed at Collector Input Applied to Base Figure 5.gmRC : (5. = vout =vin . Beginning from the out ut (5.29 increases the collector current y gm V and hence the voltage drop across RC y gm V RC . First. we construct the small-signal equivalent of the circuit. the small signal gain is negative because raising the base voltage an d hence the collector current in Fig. Second.

we ex ress (5.115) . denoting the dc dro across RC with VRC and writing gm = IC =VT . In fact. but this dro cannot exceed VCC .114) as jAv j = IC RC V T (5.igher collector bias current or a larger RC demands a greater voltage dro acros s RC .

the transistor itself requires a minimum collector emitter voltage of about VBE to remain in the active region. jAv j VCC V VBE : T Design a CE core with VCC voltage gain. an in ut signal drives the transistor into saturation.38:5: (5. 2006] June 30.118) Exam le 5. Nevertheless. the circuit am li es ro erly. 2007 at 13:42 203 (1) Sec. RC IC = VBE . A ¡ ¡ ¡ ¡ ¡ .119) Since P = IC Solution VCC . which.121) 1:8 k : VCC = 1 mW. P . a 2 mV in ut results in a 77 mV out ut.116) VCC .120) (5. so lo ng as Q1 remains in soft saturation (VBC 400 mV). 5.gmRC = .31(a).3 Bi olar Am li er To ologies 203 RC = VV : T Since VRC (5. along with VBE 800 mV.122) (5. forward biasing the base collector junction for half of each cycle. As illustrated in Fig.117) Furthermore.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. CC jAv j VV : T (5. we have IC edge of saturation is given by The voltage gain is therefore equal to Av = .cls v. of 1 mW while achieving maximum = 0:556 mA. yields RC VCC I. 5. (5. lowering the limit to . The value of RC that laces Q1 at the (5.123) Under this condition.19 = 1:8 V and a ower budget. VBE C (5.

53:9: (5.126) 40 Of course. a 2 mV in ut signal gives rise to a 107. For exam le. driv ing Q1 into heavy saturation [Fig. ¡ ¡ . VCE 0 mV and hence RC VCC .125) Av = . e.I400 mV C 2:52 k : In this case. the circuit can now tolerate only very small voltage swings at the ou t ut.more aggressive design may allow Q1 to o erate in soft saturation.124) (5.. the maximum voltage gain is given by (5.8 mV out ut.g.

5. we write Rin = vX iX = r : Thus. iX vX rπ vπ g vπ m RC rπ vπ g vπ m RC (5. Using the equivalent ci rcuit de icted in Fig. (b) in saturation.127) (5.cls v. Let us now calculate the I/O im edances of the CE stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.32(a). 5 Bi olar Am li ers 77 mV 800 mV Q1 t t (a) VCC RC 2 mV 800 mV 400 mV Q1 t t (b) Figure 5. 2006] June 30.” Exercise Re eat the above exam le if VCC = 2:5 V and com are the results.31 CE stage (a) with some signal levels. We say the circuit suffers from a trade off between voltage gain and v oltage “headroom. the in ut im edance is sim ly equal to bias increases.128) =gm = VT =IC and decreases as the collector iX vX (a) (b) ¡ 107.31(b)]. 2007 at 13:42 204 (1) 204 VCC RC 2 mV 800 mV Cha .8 mV . 5.

where the in ut voltage sour ce is set to zero (re laced with a short).32(b). 5. leaving . The out ut im edance is obtained from Fig.Figure 5.32 (a) In ut and (b) out ut im edance calculation of CE stage. Since v = 0. the de endent current sou rce also vanishes.

Voltage Headroom (Swings) g m Voltage Gain RC Out ut Im edance RC In ut Im edance β gm Figure 5.3 Bi olar Am li er To ologies 205 RC as the only com onent seen by vX . Rout : Rin (5. t hereby lowering both the voltage headroom and the in ut im edance.gmRC = .130) The out ut im edance therefore trades with the voltage gain.cls v. A CE stage must achieve an input impedance of Rin and an output impedance of Rou t . 2007 at 13:42 205 (1) Sec.131) (5. for a given value of out u t im edance. We will develop other circuits in this ook that avoid this “coupling” of design speci cations.3 3 summarizes the trade offs in the erformance of the CE to ology along with the arameters that create such trade offs. we have Av = . In other words.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. £ ¡ ¡ .33 CE stage trade-offs. Rout = vX iX = RC : (5.20 Solution = r = =gm and Rout = RC .132) Interestingly. For exam le.gm RC . 5. What is the voltage gain of the circuit? Since Rin Example 5.129) (5. 2006] June 30. Figure 5. then the voltage gain is automa tically set. RC is xed and the voltage gain can be increased by increasing IC . . if the I/O impedances are speci ed.

4. From an intuitive point of view. this trend appears valid if VCC is also raised to ensure t he transistor remains in the active mode. a giv en change in the input voltage and hence the collector current gives rise to an increasingly larger output swing as RC increases.114) suggests that the voltage gain of the CE stage can e increased inde nitely if RC ! 1 while gm remains constant.Exercise What happens to this result if the supply voltage is halved? Inclusion of Early Effect Equation (5. Mentio ned in Section 4.5. £ .

we must reexamine the a ove derivations in the presence of the E arly effect. Since achieving a high gain proves critical in circuits such as opera tional ampli ers. allowing us to rewrite (5.29 is biased with a collector current of 1 mA and RC = 1 k . £ ¡ . Figure 5. If and VA = 10 V. Exam le 5. The circuit of Fig.135) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Note that rO appears in paralle l with RC .gm RC jjrO : (5.114) as Av = .34 CE stage including Early effect.1 rO = VA I C Thus. 2007 at 13:42 206 (1) 206 Chap.34 depicts the small-signal equivalent circuit of the CE s tage including the transistor output resistance.133) We also recognize that the input impedance remains equal to r whereas the output impedance falls to Rout = RC jjrO : v in rπ vπ g vπ m rO RC v out (5. the Early effect limits the voltage gain even if RC approac hes in nity. 5.136) = 26 .134) Figure 5. 5 Bipolar Ampli ers In reality.cls v. determine the small signal voltage gain and the I/O im edan ces. 2006] June 30.21 = 100 Solution We have I gm = VC T and (5. however.

142) (5.(5.137) (5.140) Rin = r =g m = 2:6 k (5.143) = 1. we write . if VA (5.139) (5. then Av 38.gmRC jjrO 35: (As a com arison.138) = 10 k : Av = .) For the I/O im edances.141) (5.

2006] June 30. In modern integrated bi olar transistors. (5. the intrinsic gain of a bi olar transistor is inde endent of the bias current. in (5.cls v. Equation (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. jAv j = VA : V Interestingly. We rarely deal with this arameter for voltage am li ers.3 Bi olar Am li er To ologies 207 and Rout = RC jjrO = 0:91 k : (5. Let us determine the gain of a CE stage as RC ! 1.” de ned as AI = iiout . VA falls in the vicinity of 5 V.gmrO : role in high gain am li ers. but note tha ¡ .146) Av = . thereby arriving at T (5.133) gives (5. we assume gm rO 1 (and he nce rO 1=gm) for all transistors.145) Exercise Calculate the gain if VA = 5 V. layi ng a fundamental = VA =IC in Eq. 2007 at 13:42 207 (1) Sec. 5.147) Called the “intrinsic gain” of the transistor to em hasize that no external device l oads the circuit.144) (5. yielding a gain of nearly 200. We now substitute gm = IC =VT and rO gm rO re resents the maximum voltage gain rovided by a single transistor.133).148) where iout denotes the current delivered to the load and iin the current owing to the in ut.7 In this book. Another arameter of the CE stage that may ro ve relevant in some a lications is the “current gain.

¡ ¡ . roducing a collector current change of gm V . thus leaving a voltage change across the BE junctio n that is less than V .t AI = for the stage shown in Fig. the collector current change is also less t han gm V .29 is modi ed as shown in Fig. we intend to determi ne the voltage gain and I/O im edances of the circuit. it is instructive to make some q ualitative observations. Before delving into a detailed analysis.35(a). 5. 5.” this technique im rove s the “linearity” of the circuit and rovides many other interesting ro erties that are studied in more advanced courses. But with RE 6= 0. As with the CE core.35(b)]. 5. Consequently. Called “emitter degeneration. We therefore ex ect that the voltage gain of 7 But other second order effects limit the actual gain to about 50. If RE were zero.29 because the entire collector current is delivered to RC . where a resistor RE a ea rs in series with the emitter. some frac tion of V a ears across RE . CE Stage With Emitter Degeneration In many a lications. assuming Q1 is biased ro erly. then the base emitter voltage would also increase by V . Su ose the in ut signal raises the base voltage by V [F ig. the C E core of Fig. 5.

A common mistake is to conclude that Rin = r + RE .149) v = . vout .36 is the small-signal equivalent circuit.35 (a) CE stage with degeneration. ut as explained elow. the voltage dro across RE is given by vRE = r + gm v RE : Since the voltage dro across r and RE must add u to vin .36 Small signal model of CE stage with emitter degeneration. epicted in Fig. a desira le property. where VCC is replaced with an ac ground and the Early effect is neglected. We now quant ify the foregoing o servations y analyzing the small-signal ehavior of the cir cuit. Wh ile undesira le. Thus. we £ £ £ £ £ £ £ £ £ £ £ ¡ £ ¢ £ . To determine vout =vin . the degenerated stage is lower than that of the CE core with no degeneration.cls v. we rst write a KCL at the output node. Note that v appear s across r and not from the ase to ground. ( ) effect of input voltage change. Thus. gm v = . R C obtaining (5. yielding an input impedance greater than =gm = r . How a out the input impedance? Since the collector current chang e is less than gm V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the ase current also changes y less than gm V= . emitter degeneration increases th e input impedance of the CE stage. 2006] June 30. gvout : R m C (5. 5 VCC RC Vout Bi olar Am li ers ∆V RE Q1 (a) ( ) Figure 5. the reduction in gain is incurred to improve other aspects of t he performance. v out v in rπ vπ RE g vπ m RC Figure 5.150) We also recognize that two currents ow through RE : one originating from r equal t o v =r and another equal to gm v . 2007 at 13:42 208 (1) 208 VCC RC Vout V in RE Q1 Cha . Rin = r + + 1RE . 5.

have vin = v + vRE .

= v + v + gm v RE r .

152) (5.v (5.153) .151) (5.

cls v.3 Bi olar Am li er To ologies 209 = v 1 + r1 + gm RE : Substituting for v from (5. 2006] June 30.150) and rearranging the terms. 2007 at 13:42 209 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. we arrive at .

.154) vout = .(5.

To arrive at an interesting inte r retation of Eq. We identify the circuit as a CE stage because the in ut is a lied to the base f Q1 and the out ut is sensed at its collector. Av = . VCC RC v out v in RE rπ2 (a) (b) VCC RC VCC v in Q2 RE rπ2 Q1 v out Q1 Figure 5. we can assume gm 1=r and hence (5.” (In verbal desc ri tions.37(b).37(a). (5.157) It is hel ful to memorize this result as “the gain of the degenerated CE stage is equal to the total load resistance seen at the collector (to ground) divided by 1=gm lus the total resistance laced in series with the emitter. with the understanding that it must be included. 5. we divide the numerator and denominator by gm . we often ignore the negative sign in the gain. the magnitude of the voltage gain is lower than gm RC for RE 1.156) g Av = .37 (a) CE stage exam le. 5. 1 +m RC : g R m E Thus.22 Determine the voltage gain of the stage shown in Fig. With (5. leading to the sim li ed model de d in Fig. This transistor is degenerated y two devices: RE and the base emitter junction of Q2 .156).7). (b) sim li ed circuit. 5. Exam le 5. the gain falls by a factor of 1 + gm RE .155) 6= 0. The total resistance laced in series with the emitter is Solution ¡ o b i icte . The latter exhibits an m edance of r2 (as illustrated in Fig. 1 RC : gm + RE (5.) This and similar inter retations throughout this book greatly sim lify the analysis of am li ers—often obviating the need for drawing sma llsignal circuits.: RC gmvin 1 + r1 + gm RE As redicted earlier.

but the load resistance between t he collector of Q1 and ac ground consists of RC and the base emitter junction of Q2 . To com ute the in ut im edance of the degenerated CE stage.159) Exercise Re eat the above exam le if a resistor is laced in series with the emitter of Q 2 . where the total load resistance seen at the collector of Q1 is equal to RC jjr2 . we reduce the circuit to that shown in Fig. 5. (b) The to ology is a CE stage degenerated by RE . we would need to draw the small signal model of both Q1 and Q2 and solve a system of several equations. (b) sim li ed circuit. the curren t owing through RE is equal to iX + gm r iX = 1 + iX . yielding Av = .3 8(b). 1 RC : + RE jjr2 gm1 (5. Since v = r iX . we redraw the small signal model as in Fig.38 (a) CE stage exam le.cls v. 5 Bi olar Am li ers therefore equal to RE jjr2 . 2007 at 13:42 210 (1) 210 Cha .23 Calculate the voltage gain of the circuit in Fig. RC jjr2 : 1 gm1 + RE (5. we have ¡ ¡ ¡ . 2006] June 30.158) Without the above observations. 5. Summing v and vRE and equating the result to vX . creating a voltage dro of RE 1 + iX . 5. Exercise Re eat the above exam le if a resistor is laced in series with the emitter of Q 2 .39(a) and calculate vX =iX .38(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VCC RC v out v in RE Q1 Q2 RE VCC v in Q1 rπ2 VCC RC v out (a) Figure 5. Modeling the latter by r2 . The voltage gain is thus given by Solution Av = . Exam le 5.

.

The above observation is articulated as follows: any im edance tied between the emitter and ground is multi lied by + 1 when “seen from the base. 5. if the two carried equal curr ents. but in the circuit of Fig. 2006] June 30. + 1RE : . and hence (5..3 Bi olar Am li er To ologies iX vX rπ vπ v RE P RE g vπ m RC iX vX R in ( β +1) R E 211 v out rπ (a) (b) Figure 5. vin = 0 = v + r + gmv RE .39(b)].39(a). Thus. gm v . even though the current drawn from vX is merely iX . emitter degeneration increases the in ut im edance [Fig.” The ex ression “see n from the base” means the im edance measured between the base and ground. 5. + 1iX RE . also ows i nto node P .cls v. where the in ut voltage is set to zero. 2007 at 13:42 211 (1) Sec. yielding v = 0 and hence gm v = 0. the test voltage source. Why is Rin not sim ly equal to r + RE ? This would hold only if r and RE were exactly in series. We also calculate the out ut im edance of the stage with the aid of the equivalent show n in Fig. Does the factor + 1 bear any intuitive meaning? We observe that the ow of both base and collector currents through RE results in a large voltage dro .161) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. 5. In other words . the collector current.162) As redicted by our qualitative reasoning.40.40 Out ut im edance of degenerated stage. all of iX ows thr ough RC .160) Rin = vX iX = r + (5.39 (a) In ut im edance of degenerated CE stage. i. su lies a current of only iX while roducing a voltage dro of + 1iX RE across RE —as if iX ows through a resistor equal to + 1RE . vX . (b) equivalent circuit.e. Equation (5. vX = r iX + RE 1 + iX .153) a lies to this circuit as well: iX rπ vπ v RE P RE g vπ m RC vX (a) Figure 5. and Rout = vX iX = RC .

164) (5.v (5.165) .163) (5.

we require gm RC = 20. RE . 5 Bi olar Am li ers revealing that emitter degeneration does not alter the out ut im edance if the E arly effect is neglected. together with gm (5.171) (5. For Av Solution = 20 in the absence of degeneration.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.175) . which. yields RC = 520 : Since degeneration lowers the gain by a factor of two.172) (5.170) Rin = r + + 1RE = g + + 1RE m 2r because (5. (5.174) (5.e. (5.24 A CE stage is biased at a collector current of 1 mA.166) = IC =VT = 26 ..1 . 2007 at 13:42 212 (1) 212 Cha . and the I/O im edances.167) 1 + gm RE = 2. (5. i.173) . If the circuit rovides a v oltage gain of 20 with no emitter degeneration and 10 with degeneration.cls v. 2006] June 30.169) (5. Assume = 100. determi ne RC .168) RE = g1 The in ut im edance is given by = 26 : m (5. Exam le 5. Finally.

Rin = 5200 Rout = RC = 520 : Exercise What bias current would result in a gain of 5 with such emitter and collector re sistor values? Exam le 5. 5. Thus.1 and RE = 1=gm in this exam le. .41 . Assume a very large value for C1 .25 Com ute the voltage gain and I/O im edances of the circuit de icted in Fig.

5. (b ) small signal equivalent. If C1 is very large. Solution Exercise Re eat the above exam le if we tie another ca acitor from the base to ground.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.162). 5.165) a ly. The degenerated CE stage can be analyzed from a different ers ective to rovide more insight. the equivalent transconductance is obtained from Fig. (5. 1 + r 1 + gm RE vin (5. Denoted by Gm to avoid confusion w ith gm of Q1 . (5.41 CE stage exam le. For small signal o eration.35( a) and Eqs. the stage reduces to that in Fig.157).154) still holds. 2007 at 13:42 213 (1) Sec.3 Bi olar Am li er To ologies 213 VCC RC Vout V in RE Constant Q1 C1 Figure 5. Let us lace the transistor and the emitter resistor in a black b ox having still three terminals [Fig. iout = gmv = gm and hence .176) ¡ ¡ ¡ .42(b). Also. we have i out rπ vπ RE g vπ m i out v in Q1 RE v in (a) (b) Figure 5.42 (a) Degenerated bi olar transistor viewed as a black box.cls v. Thus. Si nce Eq. we c an view the box as a new transistor (or “active” device) and model its behavior by n ew values of transconductance and im edances. 5. the constant current source is re laced with an o en circuit in th e small signal equivalent circuit. it acts as a short circuit for the signal frequencies of in terest. (5. (5. 5. 2006] June 30.42(a)].

177) Gm = ivout in (5.. (5.178) .

this trend in fact re resents the “line arizing” effect of emitter degeneration. but often roves inevitable. and vout =vA represents the voltage gain from the as e of Q1 to the output.39 ( ).RC =RE under this condition.43( ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we note that Av ! .155) and (5. VCC RC v in RB A RE v out Q1 v in RB rπ ( β +1) R E A (a) ( ) Figure 5. the voltage gain of the stage with a load resistance of RD is given by .180) Here. We leave the former approach for Pro lem 44 and continue with the latter here. 2007 at 13:42 214 (1) 214 Cha . An interesting ro erty of the degenerated CE stage is that its vol tage gain becomes relatively inde endent of the transistor transconductance and hence bias current if gm RE 1.cls v. From Eq. The resulting voltage divider yields r + + 1RE vA vin = r + + 1RE + RB : Com ining (5. RB may re resent the out ut resistance of a micr o hone connected to the in ut of the am li er.155) and (5. as illustrated in Fig.157). as already o tained in Eqs. 5.162) and the model depicted in Fig. As a more general case. Let us rst compute vA =vin with the aid of Eq. To analyze the small-signal ehavior of this stage. 5. we now consider a degenerated CE stage containing a resistance in series with the base [Fig. we arrive at the overall gain as (5. 2006] June 30. vA =vin denotes the effect of voltage division etween RB and the impedanc e seen at the ase of Q1 .157). (5. ( ) equivalent circuit. we can adopt one of two appr oaches: (a) draw the small-signal model of the entire circuit and solve the resu lting equations. 5 Bi olar Am li ers 1 + gm R : g m E (5.181) vout = r + + 1RE £ £ £ £ £ £ £ £ £ £ £ £ £ .157).Gm RD . For exam le. RB only degrades the erformance of the circuit. As seen below. or ( ) recognize that the signal at node A is simply an attenua ted version of vin and write vout = vA vout : vin vin vA (5. As studied in Problem 40.179) For exam le. 5.43 (a) CE stage with ase resistance. (5. (5.43 (a)].

183) (5.gmRC + + 1RE + RB 1 + 1 + g R r m E r r + .184) + 1 m = r ++ + 1R RER r .182) (5.g1 r RCR E+ B + + E RC . 1R + R : + E B (5.vin r .

Solution £ £ £ £ £ £ £ £ £ £ £ £ ¢ £ £ . For the stage of Fig. 2007 at 13:42 215 (1) Sec. Assume RE = 4=gm and = 100. we divide the numerator and the denominat or y : Av 1 . The following quantities are o tained: RB 104 . (5.43(a). 5. 2006] June 30.44 Input impedances seen at different nodes. Example 5. The former is equal to VCC RC RB Q1 R in2 R in1 RE v out Figure 5.157). 5.26 A microphone having an output resistance of 1 k generates a peak signal level of 2 mV. (5.187) In practice. we can de ne two different inpu t impedances.RC RB : gm + RE + + 1 (5. ut RB is scaled down y + 1.185) Compared to (5. esign a CE stage with a ias current of 1 mA that ampli es this signal to 40 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We also note that the output impedance of the circuit remains equal to Rout = RC even with RB (5.3 Bipolar Ampli er Topologies 215 To o tain a more intuitive expression. This is studied in Pro lem 45. The signi cance of this o servation ecomes clear later.185). 5. From Eq.188) 6= 0.cls v. Rin1 proves more relevant and useful. The a ove results reveal that resistances in series with the emitter and the ase have similar effects on the voltage gain. Rin1 = r + + 1RE and the latter.186) Rin2 = RB + r + + 1RE : (5. one seen at the ase of Q1 and another at the left terminal of RB (Fig.44). this result contains only one additional term in the denomi nator equal to the ase resistance divided y + 1.

1 . jAv j = 20. and RE = RC = jAv j g1 + RE + RB1 + m 2:8 k : . gm = 26 .= 1 k .

190) .(5.189) (5.

27 etermine the voltage gain and I/O impedances of the circuit shown in Fig. Assume a very large value for C1 and neglect the Early effect. 5.188 ) are therefore written respectively as Solution Av = 1 . 2007 at 13:42 216 (1) 216 Chap.193) Exercise What happens if a very large capacitor is tied from the emitter of Q1 to ground? Effect of Transistor Output Resistance The analysis of the degenerated CE stage has thus far neglected the Early effect.185)-(5. as it provides the foundation for many other topologies studied later. Equations (5. we arrive at the simpli ed model in Fig.45( a). and VCC with ac grou nd.192) (5.RC jjR1RB gm + R2 + + 1 Rin = RB + r + + 1R2 Rout = RC jjR1 : (5.45 (a) CE stage example. Example 5. 5. ( ) simpli ed circuit. 5 Bipolar Ampli ers Exercise Repeat the a ove example if the microphone output resistance is dou led. £ £ £ £ £ £ £ £ ¢ . Replacing C1 with a short circuit. 2006] June 30. I1 with an open circuit. the derivation of the circuit properties in the presence of this effect is outl ined in Pro lem 48 for the interested reader. Somewhat eyond the scope of this ook.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.191) (5. namely. where R1 and RC appear in pa rallel and R2 acts as an emitter degeneration resistor.cls v. We nonetheless explore one aspect of the circuit. the output resistance.45( ). VCC RC v in RB Q1 v out R1 R2 I1 (a) ( ) RC v in RB Q1 R2 v out R1 C1 Figure 5.

200) Rout rO + gm rO RE jjr rO 1 + gm RE jjr : rO + iX RE jjr : Interestingly. £ £ . We readily note t hat RE and r appear in parallel. We al so recognize that rO carries a current of iX . v = iX + gm iX RE jjr It follows that (5.3 Bipolar Ampli er Topologies 217 Our o jective is to determine the output impedance seen looking into the collect or of a degenerated transistor [Fig.v ) and equating the res ult to vX . v = . we obtain vX = iX .46 (a) Out ut im edance of degenerated stage. Since gm v ows from t he output node into P . gm v rO . i. emitter degeneration raises the out ut im edance from rO to the a bove value. 2006] June 30. gm v rO . 5. 5.194) where the negative sign arises because the ositive side of v is at ground. we d raw the small-signal equivalent circuit as in Fig. R out V in RE Q1 rπ vπ P RE iX g vπ m iX rO vX (a) (b) Figure 5.iX RE jjr . To include the Early effect. and hence (5. The “boosting” of out ut r esistance as a result of degeneration roves extremely useful in circuit design. Thus. Adding this voltage to that across RE (= . (5. 2007 at 13:42 217 (1) Sec.46(a)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 that Rout = rO if RE = 0.197) (5.198) 1. gm rO (5. gm v and hence sustains a voltage of iX .46( ). grounding the input terminal. 5. resistors rO and RE are not in series.e.195) (5.199) (5. by a factor of 1 + gm RE jjr . A common mistake here is to write Rout = rO + RE ..146) that the intrinsic gain of the transistor. and the current owing through RE jjr is equal to i X . Rout = 1 if VA = 1 (why?). The reader may wonder if the incre ase in the out ut resistance is desirable or undesirable. (b) equivalent circuit. 5.196) Rout = 1 + gm RE jjr rO + RE jjr = rO + gm rO + 1RE jjr : Recall from (5. Also.cls v. Recall from Fig.

200) for two s ecial cases RE r and RE r . . we have RE jjr ! r and Rout rO 1 + gm r (5.202) rO .201) (5. It is instructive to examine (5. These conce ts are studied in Cha ter 9.conferring am li ers with a higher gain as well as creating more ideal current so urces. For RE r .

Exam le 5.47 Stage with ex licit de iction of rO . Thus. degeneration must raise the out ut resistance by a factor of two .47). R out Q1 V in RE rO Figure 5. 5 Bi olar Am li ers because 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the maximum resistance seen at the collector of a bi olar trans istor is equal to rO —if the degeneration im edance becomes much larger than r . . 2006] June 30. We ostulate that the condition RE r holds and write Solution 1 + gm RE = 2: That is.28 We wish to design a current source having a value of 1 mA and an out ut resistan ce of 20 k . the out ut resistance is boosted by a factor of 1 + gm RE . The available bi olar transistor exhibits = 100 and VA = 10 V. Since rO = VA =IC = 10 k . 2007 at 13:42 218 (1) 218 Cha . Fo r RE r .203) Thus. we sometimes draw the transistor out ut resistance ex licitly to em hasize its signi cance (Fig. we have RE jjr ! RE and Rout 1 + gmRE rO : (5. In the analysi s of circuits.204) RE = g1 Note that indeed r = 26 : m (5. (5. of course.206) = =gm RE . This re resentation. assumes Q1 itself does not contain another rO . 5.205) (5. Dete rmine the minimum required value of emitter degeneration resistance.cls v.

29 Solution . 5.48(a) if C1 is ve ry large.Exercise What is the out ut im edance if RE is doubled? Calculate the out ut resistance of the circuit shown in Fig. we arrive at the sim li ed Exam le 5. Re lacing Vb and C1 with an ac ground and I1 with an o en circuit.

2007 at 13:42 219 (1) Sec. reducing the circui t to that in Fig.200) as Rout1 = 1 + gm R2 jjr rO : Returning to Fig.48(c). Exam le 5. we rewrite Eq.3 Bi olar Am li er To ologies R out R out R out1 219 Q1 Vb R1 R2 C1 Q1 R2 R1 Q1 R2 I1 (a) (b) (c) Figure 5. 5. 5. we ignore R1 for the moment. we have (5.207) Rout = Rout1 jjR1 = f 1 + gm R2 jjr rO g jjR1 : (5. 2006] June 30. 5. 5. (5.209) Exercise What is the out ut resistance if a very large ca acitor is tied between the emit ter of ground? Q1 and The rocedure of rogressively sim lifying a circuit until it resembles a known to ology roves extremely critical in our work. The reader is encouraged to attem t the above exam le using the small signa l model of the overall circuit to a reciate the ef ciency and insight rovided by our intuitive a roach. (b) sim li ed circuit.40.48(b).” thi s method obviates the need for com lex small signal models and lengthy calculati ons.cls v.48 (a) CE stage exam le. model in Fig.48(b). Since R1 a ears in arallel with the resistance seen loo king into the collector of Q1 . Called “analysis by ins ection.30 ¡ ¡ . 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In analogy with Fig. (c) resistance seen at th e collector.208) (5.

Thus. Q2 is reduced to rO2 because its base emitter voltage is xed by Vb1 . 5. we rewrite Eq. 5. Recall from Fig. 5.40(a).Determine the out ut resistance of the stage shown in Fig.49(a). rO2 lays the role of emitter degenera tion resistance for Q1 . In analogy with Fig. Fr om another ers ective. (5. Now. 5.49(b)].7 that the im edance seen at the collector is equal to rO if the base and emitter are (ac) grounded. yielding a zero gm2 v2 .200) as Solution Rout = 1 + gm1rO2 jjr1 rO1 : (5.210) ¡ . Q2 can be re laced with rO2 [Fig.

2007 at 13:42 220 (1) 220 R out Cha . failing to am lify. 5.49 (a) CE stage exam le. Ex lain the cause of this roblem. For exam le. 2006] June 30. such a micro hone creates a low resistance from the base of Q1 to ground. VCC = 2. If used in this circuit.. Let us begin with an exam le.2 and rogressively add com lexity (and more robust erformanc e) to the circuit. Called a “cascode” circuit. we now study a more general case wherein the cir cuit contains a bias network as well. (b) sim li ed circuit. We begin with sim le biasing schemes descr ibed in Section 5.50 to am lify the signal roduced by a micro hone. Many micro hones exhibit a small low frequency resistance (e.31 A student familiar with the CE stage and basic biasing constructs the circuit sh own in Fig. 5 Bi olar Am li ers R out Q1 V b2 Q1 r O2 Q2 V b1 (a) (b) Figure 5. this to ology is studied and utilized extensively in Cha ter 9. Exam le 5. forming a voltage divider with RB and roviding a very low base volta ge. CE Stage with Biasing Having learned the small signal ro erties of the common e mitter am li er and its variants. Q1 carries no current. Unfortunately. 100 ). Exercise Re eat the above exam le for a “stack” of three transistors.cls v.g.5 V 100 k Ω RB X RC 1 kΩ Vout Q1 Figure 5. a micro hone resistance of 100 yields ¡ ¡ ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.50 Micro hone am li er.

Solution VX = 100 k100 100 2:5 V + 2:5 mV: Thus. the micro hone low frequency resistance disru ts the bias of the am li er.211) (5. (5.212) ¡ .

52(b). 5.51 Ca acitive cou ling at the in ut of micro hone am li er.3 Bi olar Am li er To ologies 221 Exercise Does the circuit o erate better if RB is halved? How should the circuit of Fig. 5. Let us begin with th e stage de icted in Fig. That is. The foregoing observation suggests that the methodology illustrated in Fig.9 must include an additional rule: re lace all ca acitors with an o en circuit for dc analysis and a short circuit for small signal analysis. We say C1 is a “cou ling” ca acitor and the in ut of this stage is “ac cou le d” or “ca acitively cou led.” Many circuits em loy ca acitors to isolate the bias cond itions from “undesirable” effects.50 be xed? Since only the signal generated by th e micro hone is of interest.1.cls v. For bias calculations.51 so as to isolate the dc biasing of the am li er from the micro hone.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VCC = 2. 5. From Section 5. 5. leading to Fig. a series ca acitor can be inserted as de icted in F ig.52(a). the bias oint of Q1 remains inde endent of the resistance of the micro hon e because C1 carries no bias current. 5. 5. the signal source is se t to zero and C1 is o ened. More exam les clarify this oint later.2. The value of C1 is chosen so that it rovi des a relatively low im edance (almost a short circuit) for the frequencies of i nterest. 2007 at 13:42 221 (1) Sec. 2006] June 30. we have VCC RB X C1 (a) VCC RB RC X Y Q1 v in X Q1 RB RC v out RC Y Q1 Vout (b) ¡ ¡ ¡ .5 V 100 k Ω RB X RC 1 kΩ Vout Q1 C1 Figure 5.

213) ¡ . (e) sim li ed circuit for out ut im e dance calculation. (d) sim li ed circuit for in ut im edance calculation. B (5. IC = VCCR VBE . (b) sim li ed stag e for bias calculation. . (c) sim li ed stage for small signal calculation.(c) Q1 RB R in2 R in1 (d) RC RB Q1 RC R out (e) Figure 5.52 (a) Ca acitive cou ling at the in ut of a CE stage.

To determine the out ut im edance. RC VCCR VBE : B (5. 2006] June 30. 5. Here. vX = vin regardless of the value of RB .29.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We now turn our attention to small sig nal analysis. the ci ¡ ¡ ¡ . Interestin gly. 5. 5. Nevertheless. Unfortunately.216) m C O vin However.52(a). the bias resisto r. RB . 5. VY = VCC . we will resort to usi ng a small signal model for Q1 and writing KVLs and KCLs. i.215) vout = . then Thus. Com aring this circuit with that in Fig. Recall from Fig. exce t for RB . we have vout = . With the bias current known. 5 Bi olar Am li ers . and rO can be calculated. as shown in Pr oblem 51. this effect is usually negligible. Here. 5. the small signal ar ameters gm . RB has no effect on the voltage at node X so long as vin remains an ideal v oltage source.217) 1.gm RC . 52(c) resembles the CE core illustrated in Fig. but Q1 is maintained as a symbol. Since the voltage gain from the base to the collector is given by vout =vX = . VY VBE .7 that the im edance seen looking into the b ase.52(c). the bias resistor lowers the in ut im edance. 5.53 and attem ts to drive a s eaker.31 modi es the design t o that shown in Fig.cls v. 5. Rin1 . the student in Exam le 5. 5. We at tem t to solve the circuit by ins ection: if unsuccessful. considering the sim li ed circuit of Fig.52(d)].g R : m C vin If VA (5. the in ut im edance is affected by RB [Fig.g R jjr : (5. The circuit of Fig. RB sim ly a ears in arallel with Rin1 . we set the in ut source to zero [Fig.32(b). yielding Rin2 = r jjRB : (5. r .214) To avoid saturation. 2007 at 13:42 222 (1) 222 Cha . we recognize that Rout remains unchanged: Rout = RC jjrO : (5.e. Exam le 5. C1 is re la ced with a short and VCC with ac ground.32 Having learned about ac cou ling.218) because both terminals of RB are shorted to ground.. In summary. is equal to r if the emitter is grounded.52(e)]. 5. negligibly im acts the erformance of the stage shown in Fig.

Ex lain why. VCC = 2. .5 V 100 k Ω RB X RC 1 kΩ C1 Q1 Figure 5.53 Am li er with direct connection of s eaker.rcuit still fails.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 223 (1) Sec. 5.3 Bi olar Am li er To ologies 223 Solution Ty ical s eakers incor orate a solenoid (inductor) to actuate a membrane. The so lenoid exhibits a very low dc resistance, e.g., less than 1 . Thus, the s eaker in Fig. 5.53 shorts the collector to ground, driving Q1 into dee saturation. Exercise Does the circuit o erate better if the s eaker is tied between the out ut node a nd VCC ? Exam le 5.33 The student a lies ac cou ling to the out ut as well [Fig. 5.54(a)] and measure s the quiescent oints to ensure ro er biasing. The collector bias voltage is 1 .5 V, indicating that Q1 o erates in the active region. However, the student sti ll observes no gain in the circuit. (a) If IS = 5 10,17 VCC = 2.5 V 100 k Ω 1 kΩ RB X RC v out 100 k Ω C1 (a) Q1 C2 Q1 RB RC

8Ω v in (b)

1 k Ω R s

Figure 5.54 (a) Am li er with ca acitive cou ling at the in ut and out ut, (b) sim li ed small signal model. A and VA = 1, com ute the of the transistor. (b) Ex lain why the circuit rovides no gain. Solution (a) A collector voltage of 1.5 V translates to a voltage dro of 1 V across coll ector current of 1 mA. Thus, RC and hence a VBE = VT ln IC IS = 796 mV: It follows that (5.219) (5.220) , IB = VCCR VBE B = 17 A; (5.221) (5.222) and = IC =IB = 58:8. (b) S eakers ty ically exhibit a low im edance in the audio frequency range, e.g., 8 . Drawing the ac equivalent as in Fig. 5.54(b), we not e that the total resistance seen at the collector node is equal to 1 k jj8 , yie lding a gain of jAv j = gmRC jjRS (5.223) = 0:31

¡

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 224 (1) 224 Cha . 5 Bi olar Am li ers Exercise Re eat the above exam le for RC = 500 . The design in Fig. 5.54(a) exem li es an im ro er interface between an am li er and a load: the out ut im edance is so much higher than the load im edance that the connection of the load to the am li er dro s the gain drastically. How can we reme dy the roblem of loading here? Since the voltage gain is ro ortional to gm , w e can bias Q1 at a much higher current to raise the gain. This is studied in Pro blem 53. Alternatively, we can inter ose a “buffer” stage between the CE am li er and the s eaker (Section 5.3.3). Let us now consider the biasing scheme shown in Fig . 5.15 and re eated in Fig. 5.55(a). To determine the bias conditions, we set th e signal source to zero and o en the ca acitor(s). Equations (5.38) (5.41) can t hen be used. For small signal analysis, the sim li ed circuit in Fig. 5.55(b) reve als a resemblance to that in Fig. 5.52(b), exce t that both R1 and R2 a ear in arallel with the in ut. Thus, the voltage gain is still equal to ,gm RC jjrO and the in ut im edance is given by VCC R1 RC Q1 R2 v in Q1 R1 R2 RC v out v in C1 (a) (b) Figure 5.55 (a) Biased stage with ca acitive cou ling, (b) sim li ed circu it. Rin = r jjR1 jjR2 : (5.224) The out ut resistance is equal to RC jjrO . We next study the more robust biasin g scheme of Fig. 5.19, re eated in Fig. 5.56(a) along with an in ut cou ling ca acitor. The bias oint is determined by o ening C1 and following Eqs. (5.52) and (5.53). With the collector current known, the small signal arameters of Q1 can be com uted. We also construct the sim li ed ac circuit shown in Fig. 5.56(b), no ting that the voltage gain is not affected by R1 and R2 and remains equal to Av = 1,RC ; gm + RE (5.225)

¡

¡

¡

where Early effect is neglected. On the other hand, the in ut im edance is lower ed to:

(5.226) As ex lained in Section 5.2.3, the use of emitter degeneration can effectively s tabilize the bias oint des ite variations in and IS . However, as evident from (5.225), degeneration also lowers

Rin = r + = 1.

+ 1RE jjR1 jjR2 ; whereas the out ut im edance remains equal to RC if VA

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 225 (1) Sec. 5.3 Bi olar Am li er To ologies VCC R1 RC Q1 R2 (a) 225 v out Q1 v in R1 R2 RE RC v in C1 RE (b) Figure 5.56 (a) Degenerated stage with ca acitive cou ling, (b) sim li ed circuit. the gain. Is it ossible to a ly degeneration to biasing but not to the signal? Illustrated in Fig. 5.57 is such a to ology, where C2 is large enough to act as a short circuit for signal frequencies of interest. We can therefore write VCC R1 RC Q1 R2 RE C2 v in C1 Figure 5.57 Use of ca acitor to eliminate degeneration. Av = ,gm RC and (5.227) Rin = r jjR1 jjR2 Rout = RC : Exam le 5.34 (5.228) (5.229) Design the stage of Fig. 5.57 to satisfy the following conditions: IC = 1 mA, vo ltage dro across RE = 400 mV, voltage gain = 20 in the audio frequency range (2 0 Hz to 20 kHz), in ut im edance 2 k . Assume = 100, IS = 5 10,16, and VCC = 2:5 V. With IC = 1 mA IE , the value of RE is equal to 400 . For the voltage gain t o remain unaffected by degeneration, the maximum im edance of C1 must be much sm aller than 1=gm = 26 .8 Occurring at 20 Hz, the maximum im edance must remain be low roughly 0:1 1=gm = 2:6 : Solution

1 1 1 C2 ! 10 gm for ! = 2 20 Hz: 8 A common mistake here is to make the im edance of (5.230) C1 much less than RE .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 226 (1) 226 Cha . 5 Bi olar Am li ers Thus, C2 6120 F: (This value is unrealistically large, requiring modi cation of the design.) We als o have (5.231) jAv j = gm RC = 20; obtaining (5.232) RC = 512 : (5.233) Since the voltage across RE is equal to 400 mV and VBE = VT lnIC =IS = 736 mV, we have VX = 1:14 V. Also, with a base current of 10 A, the current owing through R1 and R2 must exceed 100 A to lower sensitivity to : VCC R1 + R2 and hence 10IB (5.234) R1 + R2 25 k : Under this condition, (5.235) VX R R2 R VCC = 1:14 V; 1+ 2 yielding (5.236) R2 = 11:4 k R1 = 13:6 k : We must now check to verify that this choice of R1 and R2 satis es the condition R in That is, (5.237) (5.238)

2k . Rin = r jjR1 jjR2 = 1:85 k : (5.239) (5.240) Unfortunately, R1 and R2 lower the in ut im edance excessively. To remedy the r oblem, we can allow a smaller current through R1 and R2 than 10IB , at the cost of creating more sensitivity to . For exam le, if this current is set to 5IB = 5 0 A and we still neglect IB in the calculation of VX , VCC R1 + R2 and 5IB (5.241) R1 + R2 50 k : (5.242)

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 227 (1) Sec. 5.3 Bi olar Am li er To ologies 227 Consequently, R2 = 22:4 k R1 = 27:2 k ; giving (5.243) (5.244) Rin = 2:14 k : (5.245) Exercise Redesign the above stage for a gain of 10 and com are the results. We conclude our study of the CE stage with a brief look at the more general case de icted in Fig. 5.58(a), where the in ut signal source exhibits a nite resistan ce and the out ut is tied to a load RL . The biasing remains identical to that o f Fig. 5.56(a), but RS and RL lower the voltage gain vout =vin . The sim li ed ac circuit of Fig. 5.58(b) reveals Vin is attenuated by the voltage division betwee n RS and the im edance seen at node X , R1 jjR2 jj r + + 1RE , i.e., VCC R1 RS v in C1 Q1 R2 (a) RC C2 RL v out v in RS R1 R2 v out X Q1 RE RC RL RE (b) RS v in R1 R2 v out X Q1 RE RC RL (b) Figure 5.58 (a) General CE stage, (b) sim li ed circuit, (c) Thevenin model of in ut network. vX = R1 jjR2 jj r + + 1RE : vin R1 jjR2 jj r + + 1RE + RS

The voltage gain from vin to the out ut is given by (5.246) vout = vX vout vin vin vX R1 R r 2 r E S 1 + RE gm (5.247) (5.248) + 1 E = , R jjRjjjj 2 jj + + + 1R R+ R RC jjRL : 1

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 228 (1) 228 Cha . 5 Bi olar Am li ers As ex ected, lower values of R1 and R2 reduce the gain. The above com utation vi ews the in ut network as a voltage divider. Alternatively, we can utilize a Thev enin equivalent to include the effect of RS , R1 , and R2 on the voltage gain. I llustrated in Fig. 5.58(c), the idea is to re lace vin , RS and R1 jjR2 with vTh ev and RThev : R1 vThev = R jjRjjR2R vin 1 2+ S RThev = RS jjR1 jjR2 : The resulting circuit resembles that in Fig. 5.43(a) and follows Eq. (5.185): (5.249) (5.250) R1 Av = , 1 RC jjRLRThev (5.251) where the second fraction on the right accounts for the voltage attenuation give n by Eq. (5.249). The reader is encouraged to rove that (5.248) and (5.251) are identical. The two a roaches described above exem lify analysis techniques use d to solve circuits and gain insight. Neither requires drawing the small signal model of the transistor because the reduced circuits can be “ma ed” into known to o logies. Figure 5.59 summarizes the conce ts studied in this section. Headroom RC Gain RC rO R out A v = − g m (RC r O ) A v , R in A v = − g mR C R out R in R1 C1 R2 RC Q1 R1 R2 RC RE RE C2 Figure 5.59 Summary of conce ts studied thus far. R jjRjjR2R ; 1 2+ S gm + RE + + 1

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5.3.2 Common Base To ology Following our extensive study of the CE stage, we now turn our attention to the “common base“ (CB) to ology. Nearly all of the conce ts d escribed for the CE con guration a ly here as well. We therefore follow the same train of thought, but at a slightly faster ace. Given the am li cation ca abiliti es of the CE stage, the reader may wonder why we study other am li er to ologies. As we will see, other con gurations rovide different circuit ro erties that are referable to those of the CE stage in some a lications. The reader is encourag ed to review Exam les 5.2 5.4, their resulting rules illustrated in Fig. 5.7, an d the ossible to ologies in Fig. 5.28 before roceeding further.

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 229 (1) Sec. 5.3 Bi olar Am li er To ologies 229 Figure 5.60 shows the CB stage. The in ut is a lied to the emitter and the out ut is sensed at the collector. Biased at a ro er voltage, the base acts as ac g round and hence as a node “common” to the in ut and out ut orts. As with the CE sta ge, we rst study the core and subsequently add the biasing elements. VCC RC Vout Q1 Vb v in In ut A lied to Emitter Out ut Sensed at Collector Figure 5.60 Common base stage.

g ∆V R C m v out rπ vπ g vπ m RC ∆V ( ) Figure 5.61 (a) Response of CB stage to small input change, ( ) small-signal mod el. Av = gm RC : (5.252) Interestingly, this expression is identical to the gain of the CE topology. Unli ke the CE stage, however, this circuit exhi its a positive gain ecause an incre ase in Vin leads to an increase in Vout . Let us con rm the a ove results with the aid of the small-signal equivalent depicted in Fig. 5.61( ), where the Early ef fect is neglected. Beginning with the output node, we equate the current owing th rough RC to gm v : , vout = gm v ; R C (5.253) 9 Note that the topologies of Figs. 5.60-5.61(a) are identical even though

Analysis of CB Core How does the CB stage of Fig. 5.61(a) res ond to an in gnal?9 If Vin goes u by a small amount V , the base emitter voltage of Q1 ses by the same amount because the base voltage is xed. Consequently, the or current falls by gm V , allowing Vout to rise by gm V RC . We therefore that the small signal voltage gain is equal to VCC RC Vout Q1 Vb v in V in (a)

ut si decrea collect surmise

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Q1 is drawn differently.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 230 (1) 230 Chap. 5 Bipolar Ampli ers o taining v = ,vout =gm RC . Considering the input node next, we recognize that v It follows that = ,vin . (5.254) vout = g R : vin m C As with the CE stage, the CB topology suffers from trade-offs etween the gain, the voltage headroom, and the I/O impedances. We rst examine the circuit’s headroom limitations. How should the ase voltage, V , in Fig. 5.61(a) e chosen? Recal l that the operation in the active region requires VBE 0 and VBC 0 (for npn devi ces). Thus, V must remain higher than the input y a out 800 mV, and the output must remain higher than or equal to V . For example, if the dc level of the in put is zero (Fig. 5.62), then the output must not fall elow approximately 800 m V, i.e., the voltage drop across RC cannot exceed VCC , VBE . Similar to the CE stage limitation, this condition translates to VCC RC VCC − V BE ~0V ~800 mV 800 mV 0 Vb t V in Figure 5.62 Voltage headroom in CB stage. I Av = VC RC T VCC , VBE : = VT Exam le 5.35 (5.255) (5.256) The voltage roduced by an electronic thermometer is equal to 600 mV at room tem erature. Design a CB stage to sense the thermometer voltage and am lify the cha nge with maximum gain. Assume VCC = 1:8 V, IC = 0:2 mA, IS = 5 10,17 A, and = 10 0.

Solution Illustrated in Fig. 5.63(a), the circuit must o el of 600 mV. Thus, Vb = VBE + 600 mV = VT lnIC saturation, the collector voltage must not fall allowing a maximum voltage dro across RC equal can then write

erate ro erly with an in ut lev =IS + 600 mV = 1:354 V. To avoid below the base voltage, thereby to 1:8 V , 1:354 V = 0:446 V. We

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Av = gmRC = IC RC VT = 17:2: (5.257) (5.258) (5.259)

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 231 (1) Sec. 5.3 Bi olar Am li er To ologies VCC RC Vout Q1 Vb Q1 RC Vout IB VCC R1 I1 R2 231 V in 600 mV V in 600 mV Thermometer (a) (b) Figure 5.63 (a) CB stage sensing an in ut, (b) bias network for base.

Vb R R2 R VCC 1+ 2 and hence (5.260) R2 = 67:7 k R1 = 22:3 k : (5.261) (5.262) Exercise Re eat the above exam le if the thermometer voltage is 300 mV. Let us now com ute the I/O im edances of the CB to ology so as to understand its ca abilities in interfacing with receding and following stages. The rules illu strated in Fig. 5.7 rove extremely useful here, obviating the need for small si gnal equivalent circuits. Shown in Fig. 5.64(a), the sim li ed ac circuit reveals that Rin is sim ly the im edance seen looking into the emitter with the base at ac ground. From the rules in Fig. 5.7, we have Rin = g1 m (5.263) for

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The reader is encouraged to re eat the he maximum gain remains relatively inde w generate Vb . A sim le a roach is to n Fig. 5.63(b). To lower sensitivity to s, R1 + R2 = 90 k . Also,

roblem with IC = 0:4 mA to verify that t endent of the bias current.10 We must no em loy a resistive divider as de icted i , we choose I1 10IB 20 A VCC =R1 + R2 . Thu

if VA = 1. The in ut im edance of the CB stage is therefore relatively low, e.g. , 26 IC = 1 mA (in shar contrast to the corres onding value for a CE stage, =gm ).

10 This exam le serves only as an illustration of the CB stage. A CE stage may rove more suited to sensing a thermometer voltage.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 232 (1) 232 VCC RC Cha . 5 VCC RC Bi olar Am li ers Q1 ac IX VX Q1 Vb R in (a) ∆V ( ) Figure 5.64 (a) Input impedance of CB stage, ( ) response to a small change in i nput. The input impedance of the CB stage can also e determined intuitively [Fig. 5.6 4( )]. Suppose a voltage source VX tied to the emitter of Q1 changes y a small amount V . The aseemitter voltage therefore changes y the same amount, leading to a change in the collector current equal to gm V . Since the collector current o ws through the input source, the current supplied y VX also changes y gm V . Co nsequently, Rin = VX =IX = 1=gm. oes an ampli er with a low input impedance nd any p ractical use? Yes, indeed. For example, many stand-alone high-frequency ampli ers are designed with an input resistance of 50 to provide “impedance matching” etween modules in a cascade and the transmission lines (traces on a printed-circuit oa rd) connecting the modules (Fig. 5.65).11 50− Ω Transmission Line 50− Ω Transmission Line 50 Ω 50 Ω Figure 5.65 System using transmission lines. The out ut im edance of the CB stage is com uted with the aid of Fig. 5.66, wher e the in ut voltage source is set to zero. We note that Rout = Rout1 jjRC , wher e Rout1 is the im edance seen at the collector with the emitter grounded. From t he rules of Fig. 5.7, we have Rout1 = rO and hence Q1 rO

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ac RC R out1 R out Figure 5.66 Out ut im edance of CB stage. Rout = rO jjRC (5.264) 11 If the in ut im edance of each stage is not matched to the characteristic im edance of the receding transmission line, then “re ections” occur, corru ting the sig nal or at least creating de endence on the length of the lines.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 233 (1) Sec. 5.3 Bi olar Am li er To ologies 233 or Rout = RC if VA = 1: Exam le 5.36 (5.265)

Solution = 1=gm and Rout = RC , we have Av = Rout : R in (5.266) Exercise Com are this value with that obtained for the CE stage. From Eqs. (5.256) and (5.266), we conclude that the CB stage exhibits a set of t rade offs similar to those de icted in Fig. 5.33 for the CE am li er. It is instru ctive to study the behavior of the CB to ology in the resence of a nite source r esistance. Shown in Fig. 5.67, such a circuit suffers from signal attenuation fr om the in ut to node X , thereby roviding a smaller voltage gain. More s eci call y, since the im edance seen looking into the emitter of Q1 (with the base ground ed) is equal to 1=gm (for VA = 1), we have VCC RC v out RS v in Q1 X v in RS X 1 gm 1 gm Figure 5.67 CB stage with source resistance. vX = 1 = 1 + g R vin : m S We also recall from Eq. (5.254) that the gain from the emitter to the out ut is given by RS + g1

A common base am li er is designed for an in ut im edance of Rin and an out ut im edance of Rout . Neglecting the Early effect, determine the voltage gain of the circuit. Since Rin

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gm 1 vin (5.267) m (5.268) vout = g R : m C vX (5.269)

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 234 (1) 234 Cha . 5 Bi olar Am li ers It follows that vout = gm RC vin 1 + gm RS = 1 RC ; gm + RS (5.270) (5.271) a result identical to that of the CE stage (exce t for a negative sign) if RS is viewed as an emitter degeneration resistor. Exam le 5.37 A common base stage is designed to am lify an RF signal received by a 50 antenn a. Determine the required bias current if the in ut im edance of the am li er must “match” the im edance of the antenna. What is the voltage gain if the CB stage also drives a 50 load? Assume VA = 1. Figure 5.68 de icts the am li er12 and the equi valent circuit with the antenna modeled by a VCC RC v out Antenna Antenna Solution VCC RC v out RS v in Q1 VB Q1 VB Figure 5.68 (a) CB stage sensing a signal received by an antenna, (b) equivalent circuit. voltage source, vin , and a resistance, RS = 50 . For im edance matching, it is necessary that the in ut im edance of the CB core, 1=gm , be equal to RS , and h ence

(5.272) (5.273) Av = 1 RC gm + RS = 1: 2 The circuit is therefore not suited to driving a 50 load directly. (5.274) (5.275)

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IC = gm VT = 0:52 mA: If RC itself is re laced by a 50

load, then Eq. (5.271) reveals that

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12 The dots denote the need for biasing circuitry, as described later in this se ction.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 235 (1) Sec. 5.3 Bi olar Am li er To ologies 235 Exercise What is the voltage gain if a 50 resistor is also tied from the emitter of Q1 t o ground? Another interesting oint of contrast between the CE and CB stages relates to th eir current gains. The CB stage dis lays a current gain of unity because the cur rent owing into the emitter sim ly emerges from the collector (if the base curren t is neglected). On the other hand, as mentioned in Section 5.3.1, AI = for the CE stage. In fact, in the above exam le, iin = vin =RS + 1=gm, which u on owing thr ough RC , yields vout = RC vin =RS + 1=gm. It is thus not sur rising that the volt age gain does not exceed 0.5 if RC RS . As with the CE stage, we may desire to a nalyze the CB to ology in the general case: with emitter degeneration, VA 1, and a resistance in series with the base [Fig. 5.69(a)]. Outlined in Problem 64, th is analysis is somewhat beyond the sco e of this book. Nevertheless, it is inVCC RC v out RE v in (a) (b) rO Q1 RB VB RE rO Q1 R out1 RC R out2 Figure 5.69 (a) General CB stage, (b) out ut im edance seen at different nodes. structive to consider a s ecial case where RB = 0 but VA 1, and we wish to com u te the out ut im edance. As illustrated in Fig. 5.69(b), Rout is equal to RC in arallel with the im edance seen looking into the collector, Rout1 . But Rout1 i s identical to the out ut resistance of an emitter degenerated common emitter st age, i.e., Fig. 5.46, and hence given by Eq. (5.197): Rout1 = 1 + gmRE jjr It follows that (5.276) Rout = RC jj f 1 + gmRE jjr rO + RE jjr g : (5.277) rO + RE jjr :

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The reader may have recognized that the out ut im edance of the CB stage is equa l to that of the CE stage. Is this true in general? Recall that the out ut im ed ance is determined by setting the in ut source to zero. In other words, when cal culating Rout , we have no knowledge of the in ut terminal of the circuit, as il lustrated in Fig. 5.70 for CE and CB stages. It is therefore no coincidence that the out ut im edances are identical if the same assum tions are made for both c ircuits (e.g., identical values of VA and emitter degeneration). Exam le 5.38 Old wisdom says “the out ut im edance of the CB stage is substantially higher than that of the CE stage.” This claim is justi ed by the tests illustrated in Fig. 5.71 . If a constant current is , injected into the base while the collector voltage is varied, IC exhibits a slo e equal to rO 1 [Fig. 5.71(a)]. On the other hand, if a constant current is drawn from the emitter, IC dis lays much less de endenc e on the collector voltage. Ex lain why these tests do not re resent ractical s ituations.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 236 (1) 236 VCC RC Q1 v in RE v out VCC RC Q1 RE R out v in (a) Cha . 5 VCC RC Vb Q1 RE v out Bi olar Am li ers VCC RC Q1 R out RE (b) Figure 5.70 (a) CE stage and (b) CB stage sim li ed for out ut im edance calculati on. IC VCC IB Q1 V1 V1 (a) O en (b) IC IC VB Q1 IE V1 IC V1 rπ vπ g vπ m rO R out rπ vπ g vπ m rO R out O en (c) (d) Figure 5.71 (a) Resistance seens at collector with emitter grounded , (b) resistance seen at collector with an ideal current source in emitter, (c) small signal model of (a), (d) small signal model of (b).

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Solution The rinci al issue in these tests relates to the use of current sources to driv e each stage. From a small signal oint of view, the two circuits reduce to thos e de icted in Figs. 5.71(c) and (d), with current sources IB and IE re laced wit h o en circuits because they are constant. In Fig. 5.71(c), the current through r is zero, yielding gm v = 0 and hence Rout = rO . On the other hand, Fig. 5.71(d) resembles an emitter degenerated stage (Fig. 5.46) with an in nite emitter resist ance, exhibiting an out ut resistance of Rout = 1 + gmRE jjr rO + RE jjr (5.278) (5.279) (5.280) which is, of course, much greater than rO . In ractice, however, each stage may be driven by a voltage source having a nite im edance, making the above com aris on irrelevant. Exercise Re eat the above exam le if a resistor of value R1 is inserted in series with th e emitter. = 1 + gmr rO + r rO + r ;

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 237 (1) Sec. 5.3 Bi olar Am li er To ologies 237 Another s ecial case of the to ology shown in Fig. 5.69(a) occurs if VA = 1 but RB 0. Since this case does not reduce to any of the con gurations studied earlier, we em loy the smallsignal model shown in Fig. 5.72 to study its behavior. As us ual, we write gm v = ,vout =RC and hence v = ,vout =gm RC . The current owing through r (and RB ) is then equal to v =r = ,vout =gmr RC = ,vout = RC . Multi lying this curr ent by RB + r , we obtain the voltage at node P : RB rπ vπ P v in RE g vπ m RC v out Figure 5.72 CB stage with base resistance. vP = , ,vout RB + r RC vout R + r : = R B We also write a KCL at P : (5.281) (5.282) v + g v = vP , vin ; r m (5.283) that is, RE C

1 It follows that out r + gm gm RC = ,v vout R + r , v RC B (5.284) RC vout = vin + 1RE + RB + r : Dividing the numerator and denominator by (5.285) + 1, we have (5.286) vout RC RB + 1 : vin RE + + 1 gm As ex ected, the gain is ositive. Furthermore, this ex ression is identical to that in (5.185) for the CE stage. Figure 5.73 illustrates the results, revealing that, exce t for a negative sign, the two stages exhibit equal gains. Note that RB degrades the gain and is not added to the circuit deliberately. As ex lained later in this section, RB may arise from the biasing network. Let us now determ ine the in ut im edance of the CB stage in the resence of a resistance in serie s with the base, still assuming VA = 1. From the small signal equivalent circuit shown in in : RE

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 238 (1) 238 Cha . 5 Bi olar Am li ers VCC RC RB Q1 v in RE v in v out RB VCC RC v out Q1 RE Figure 5.73 Com arison of CE and CB stages with base resistance. Fig. 5.74, we recognize that r and RB form a voltage divider, thereby roducing13 RB rπ vπ g vπ m RC v out vX iX Figure 5.74 In ut im edance of CB stage with base resistance. r v = , r +R vX : B Moreover, KCL at the in ut node gives (5.287) v + g v = ,i : X r m Thus, (5.288)

1 ,r r + gm r + RB vX = ,iX vX = r + RB iX +1 g1 + RB1 : + m (5.289) and (5.290) (5.291) Note that Rin = 1=gm if RB = 0, an ex ected result from the rules illustrated in Fig. 5.7. Interestingly, the base resistance is divided by + 1 when “seen” from the emitter. This is in contrast to the case of emitter degeneration, where the emi tter resistance is multi lied by + 1 13 Alternatively, the current through r + R is equal to v =r + R , yielding a volt age of B X B across r . ,r vX =r + RB

75 Impedance seen at the emitter or £ £ ase of a transistor. VCC RB Q1 Q2 R eq RX RC Q2 in Fig. RB VA = Q1 RB 1 + g m β +1 r π + (β +1) R E VA = Q1 RE Example 5.291) is simply equal to Solution Req = g 1 + RB1 : + m1 Reducing the circuit to that shown in Fig. 5.39 etermine the impedance seen at the emitter of identical and VA = 1. we have (5. Thus. (5. 5.76( ). which from Eq.3 Bi olar Am li er To ologies 239 when seen from the base. 2007 at 13:42 239 (1) Sec.cls v.ase device. ut with its ase tied to a nite series resistance equal to that seen at the emitter of Q1 . £ ¢ . 5. The circuit employs Q2 as a common. th ese results remain inde endent of RC if VA = 1. 2006] June 30.292) RX = g 1 + Req1 + m2 1 = g1 + + 1 g1 + m2 m1 £ £ £ £ £ Figure 5.76(a) if the two transistors are VCC RB 1 + g m1 β +1 RC v out Q2 RX ( ) v out (a) Figure 5. Figure 5. ( ) simpli ed circuit.76 (a) Example of CB stage. Interestingly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we must rst o t ain the equivalent resistance Req .75 summarizes the two cases.

RB : +1 (5. £ .294) Exercise What happens if a resistor of value R1 is placed in series with the collector of Q1 ? CB Stage with Biasing Having learned the small-signal properties of the CB core. An example proves instructive at this point.293) (5. we now extend our analysis to the circuit including iasing.

That is. the student quickly connects the emitter to ground so that and a reasona le collector current can e esta lished (Fig.77. Explain why this circuit does not work. £ £ £ £ .41 Figure 5.40 The student in Example 5. 2007 at 13:42 240 (1) 240 Chap.6.78). where no ase current can e support ed. the design provides no dc path for the emitter current of Q1 . 5 Bipolar Ampli ers Example 5. fo rcing a zero ias current and hence a zero transconductance.” out Q1 V v in C1 £ In what region does Q1 operate if V £ £ £ Figure 5. Solution Exercise = VCC ? Example 5. yielding vo ut = 0. 2006] June 30. Exp “haste makes waste. t he emitter voltage is equal to zero regardless of the value of vin . VCC RC Vout Q1 V V in C1 Unfortunately.5. drawing the d esign as shown in Fig.cls v.77 CB stage lacking ias current. Solution As with Example 5. The situation is si milar to the CE counterpart in Example 5. 5. £ £ £ £ £ £ Somewhat VBE = V lain why VCC RC v em arrassed.78 CB stage with emitter shorted to ground.31 decides to incorporate ac coupling at the input of a CB stage to ensure the ias is not affected y the signal source. the student has shorted the signal to ac ground. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

2006] June 30.58).79( ). 5. ( ) inclusion of source resistanc e. VCC RC v out 1 gm Q1 v in C1 RE RE (a) ( ) Figure 5.79 (a) CB stage with iasing.cls v. Shown in Fig. seen looking “down. seen looking “up” into the emitter (with the ase at ac ground) and (2) RE .295) As with the input iasing network in the CE stage (Fig.” Thus.296) = 1 m g jjRE + RS ¢ £ £ £ £ £ £ £ VCC RC v out Q1 V X v in R S C1 R in RE V £ £ £ £ £ £ £ £ ¢ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.67. ep icted in Fig. the reduction in Rin manifests itself if the source voltage exhi its a nite output resistance. such a circuit attenuates the signal. Following the analysis illustrated in Fig. 5. Rin = g1 jjRE : m (5.79(a) is an exampl e.3 Bipolar Ampli er Topologies 241 Exercise oes the circuit operate etter if V is raised? The a ove examples imply that the emitter can remain neither open nor shorted to ground. lowering the overal l voltage gain. We recognize that Rin now consists of two parallel components: (1) 1=gm. 5. 5. where RE provides a path for the ias current at the cost of lowering the inp ut impedance. we can write vX Rin vin = Rin + RS 1 g jjRE m (5. 2007 at 13:42 241 (1) Sec. 5. there y requiring some ias element.

297) 1 = 1 + 1 + g R R : m E S Since vout =vX (5.299) As usual. we have preferred solution y inspection over drawing the small-signal equivalent.(5. The reader may see a contradiction in our thoughts: on the one hand .298) = gm RC . we consider the reduction of the input impedance due to RE undesira le. we must distinguish etween the two comp onents 1=gm and RE . on the othe r hand. noting that the latter shunts the input gmRC : £ £ £ . To resolve this apparent contradiction. vout = 1 vin 1 + 1 + gm RE RS (5. we view the low input impedance of the CB stage a useful property.

source current to ground.80.300) IC RE (5. generated? We can employ a resistive divider similar to that used in the CE stage.301) That is. V . with only i2 reaching RC and contri uting to the output signal. then i2 rises. we mu st have RE and hence gm VT : 1 (5. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. yielding VCC RC Q1 C1 R E (a) VCC RC R Thev Q1 V Thev RE ( ) VCC RC Q1 R2 RE (c) R1 IB R2 R1 £ I1 V £ £ £ £ VCC RC v out i in R S C1 Q1 i2 i1 RE V £ £ £ £ . 5.80 Small-signal input current components in a CB stage. iin spli ts two ways.81(a). If RE decreases while 1=gm remains constant. reduction of Rin due to RE is undesira le. By contrast. 2007 at 13:42 242 (1) 242 Chap. the dc voltage drop across RE muts e much greater than VT . How is the ase voltage. For RE to affect the input impedance negligi ly. such a topology must ensure I1 IB to minimize sensitivity to .14 Thus. 5 Bipolar Ampli ers v in Figure 5.cls v. As shown in Fig. then i2 also falls. if 1=gm decreases while RE remains constant. 5. Shown in Fig. thus “wasting” the signal.

recall from Eq. RE = 0 (Example 5.81 (a) CB stage with ase ias network.286) that a resistance in series with the ase reduc es the voltage gain of the CB stage. (5. 5. 14 In the extreme case. £ £ £ £ V R R2 R VCC : 1+ 2 £ £ £ £ . Su stituting a Thevenin equivalent for R1 a nd R2 as depicted in Fig. ( ) use of Thevenin equivalent.302) However.41) and i2 = 0. (5.81( ). (c) effect of ypass capacitor.CB Figure 5.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. e. Example 5.303) IC = 0:52 mA: If the ase is ypassed to ground (5.82) for a voltage gain of 10 and an input impedance of 50 .81(c)]. Thus. VCC RC V out V in C1 Q1 R2 RE I C RE R1 V CB Figure 5. acting as a short circuit at frequencies of interest [Fig.305) RC = 500 : (5. 5. a “ ypass capacitor” is often tied from the ase to ground.cls v. 2006] June 30.304) Av = gm RC .82 Example of CB stage with iasing. For this reason.306) We now determine the ase ias resistors. Assume IS = 5 10. yielding (5. VA = 1.g. and VCC = 2:5 V. 5.3 Bipolar Ampli er Topologies 243 we recognize that a resistance of RThev = R1 jjR2 now appears in series with the ase. 2007 at 13:42 243 (1) Sec. Solution We egin y selecting RE . = 100. RE 1=gm. RE = 500 . we have £ £ £ £ £ £ £ £ £ £ £ £ ¢ .16 A.. Since the voltage drop across RE is eq ual to 500 0:52 mA = 260 mV and VBE = VT lnIC =IS = 899 mV. 5.42 esign a CB stage (Fig. to minimize the undesira le effect of Rin g1 = 50 m and hence (5.

(5.308) = 52 A.310) V R R2 R VCC : 1+ 2 VCC R + R = 52 A: 1 2 £ V = IE RE + VBE = 1:16 V: Selecting the current through R1 and R2 to £ £ e 10IB . we write (5.309) (5.307) (5.

1 = 1=gm =20 to ensure negligi le gain degra dation. jC1 ! j.271). 2006] June 30. rules illustrated in Fig. we may also use the £ £ £ £ £ £ £ £ ¢ .313) (5. 5.5.315) CB = 0:7 pF: (A common mistake is to make the impedance of CB negligi le with respect to than with respect to 1=gm . 5. For example. (5.3. 5.7. its impedance. must remain much less than 1=gm = 50 .3 Emitter Follower Another important circuit topology is the emitter followe r (also called the “common-collector” stage). The reader is encouraged to review Exa mples 5.314) = 71 pF: Since the impedance of CB appears in series with the ase and plays a role simil ar to the term RB = + 1 in Eq.2 . Consequently.67 and Eq. For the sake of revity. Appearing in series with the emitter of Q1 . 1 . 2007 at 13:42 244 (1) 244 Chap. the impedances of C1 and CB must e suf ciently small at this frequency.3.28 efore proceeding further. if the ampli er is used at the receiver front end of a 900-MHz cellphone. C1 plays a role similar to RS in Fig. and the possi le topologies in F ig.cls v. for ! = 2 900 MHz: g C1 = 20! m (5.286). we require that 1 1 1 1 + 1 CB ! = 20 gm and hence (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (5.316) R1 jjR2 rather Exercise esign the a ove circuit for an input impedance of 100 . 5 Bipolar Ampli ers It follows that R1 = 25:8 k R2 = 22:3 k : (5.) (5. we may choose jC1 ! j. 5.312) The last step in the design is to compute the required values of C1 and CB accor ding to the signal frequency. Thus. In high-performance applications such as cellphones.311) (5.

Emitter Follower C ore How does the follower in Fig. then VBE must rise and so must IE . From another perspective. Since Vout changes in the same £ £ £ £ £ . We rst study the core and su sequently add the iasing elements.84(a) respond to a change in Vin ? If Vin ri ses y a small amount Vin . 5. 5. Shown in Fig. the emitter follower senses the input at the ase of the transistor and produces the output at the emitter. Vout is constant. rai sing the collector and emitter currents.term “follower” to refer to emitter followers in this chapter. The higher emitter current translates t o a greater drop across RE and hence a higher Vout . requiring that Vout go up. the ase-emitter voltage of Q1 tends to increase.83. i f we assume. The collector is tied to VCC and hence ac ground. for example.

If the output changes y a greater amount than the input. 5. 2007 at 13:42 245 (1) Sec. Vout Vin .” VCC V in Q1 Vout RE V in1 V BE1 V out1 ( ) V in1 + ∆V in V BE2 V out1 + ∆V out (a) Figure 5. the in put and output impedances of the emitter follower make it a particularly useful circuit for some applications.84( )]. Another interesting and important o servation here is that the change in Vout ca nnot e larger than the change in Vin . rst assuming VA = 1. contra dicting the assumption that Vout has increased. Suppose Vin increases from Vin1 to Vin1 + Vin and Vout from Vout1 to Vout1 +Vout [Fig. As explained later. Let us now derive the small-signal properties of the follower.85.83 Emitter follower.84 (a) Emitter follower sensing an input change. Thus. and the circuit is said to pro vide “level shift. then VBE2 must e less than VBE1 . we expect the voltage gain to e positive. 2006] June 30.cls v. ( ) response of the ci rcuit. But this means the emitter current also decreases and so does IE RE = Vout . Shown in Fig. 5.15 The reader may wonder if an ampli er with a su unity gain has any practical value. Note that Vout is always lower than Vin y an amount equal to VBE . 5. implying that the follower exhi its a voltage gain less than unity.3 Bipolar Ampli er Topologies VCC V in Input Applied to Base 245 Q1 RE Output Sensed at Emitter Vout Figure 5. Vout Vin . the equivalent circuit yie lds v in rπ vπ £ £ £ £ £ £ £ £ £ £ £ . direction as Vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

85 Small signal model of emitter follower. (5. the gain becomes equal to unity .43.318) ¡ .317) v = r+ 1 vout : RE 15 In an extreme case described in Exam le 5.g vπ m v out RE Figure 5. v + g v = vout r m RE and hence (5.

Su ose.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 246 (1) 246 Cha . 5.321) Exam le 5. Determine the voltage gain if the current source is ideal and VA = 1.322) This result can also be derived intuitively. (5. we recognize that Vout exactly follows Vin if VBE is constant. 5 ¡ . 2006] June 30. 5 Bi olar Am li ers We also have vin = v + vout : Substituting for v from (5.321) suggests that the emitter follower acts as a voltage divider. VBE .320) (5.cls v.319) vout = 1 vin 1 + r 1 + 1 RE RE 1 : RE + g m The voltage gain is therefore ositive and less than unity. Exercise Re eat the above exam le if a resistor of value R1 is laced in series with the collector. we wish to model vin and Q1 by a Thevenin equivalent.86 . as show n in Fig. the value o f RE in Eq. 5. Since the emitter resistor is re laced with an ideal current source. VCC V in Q1 Vout I1 Figure 5. (5. Equation (5.43 In integrated circuits. a ers ective that can be reinforced by an alternative analysis.321) must tend to in nity. A constant current source owing thro ugh Q1 requires that VBE = VT lnIC =IS remain constant.87(a). yielding Solution Av = 1: (5. Writing Vout = Vin . The The venin voltage is given by the o en circuit out ut voltage roduced by Q1 [Fig.86 Follower with current source.318). we obtain (5. the follower is ty ically realized as shown in Fig.

87(c)] and i s equal to 1=gm . vThev = vin . 5. 5. The T hevenin resistance is obtained by setting the in ut to zero [Fig.87(b)]. 5. as if Q1 o erates with RE = 1 (Exam le 5. .43)..87(d). Thus. con rming o eration as a voltage divider.87(a) therefore reduces to that shown in Fig. The circuit of Fig.

(c) simpli ed circuit. (d) sim li ed circuit. RS v in RE R Thev (a) (b) £ nite source im edance of RS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 247 (1) Sec.88 (a) Follower with source impedance.44 VCC RS v out VCC Q1 Q1 RS 1 + gm β+ 1 v Thev = v in RE v out (c) Figure 5. (c) Thevenin resi stance.3 Bi olar Am li er To ologies VCC Q1 v in RE (a) (b) 247 VCC Q1 v out v in v out = v in VCC Q1 v Thev = v in R Thev (c) R Thev = 1 gm v out RE (d) Figure 5. RS .cls v. 5. (b) Thevenin voltage . and Q1 y a Thevenin equivalent. Exam le 5. 5. £ We model vin . 2006] June 30.87 (a) Emitter follower stage.88(a)] if VA = 1. The reader can show that th Determine the voltage gain of a follower driven by a [Fig. ( ) Thevenin resistance seen at emitter.

£ £ e o tained y solving the small-signal equivalent circuit . 5.88(c) depicts the e quivalent circuit. Furthermore. the Thevenin resistance [F ig. revealing that Solution vout = RE vin RE + RS + 1 : + 1 gm (5.323) £ £ £ This result can also of the follower.88( )] is given y (5. Figure 5.e open-circuit voltage is equal to vin .291) as RS = + 1 + 1=gm .

we have iX r = v .162) derived for a degenerated CE stage. we have iX vX rπ vπ RE g vπ m R in VCC RC Q1 RE R in 0 VCC Q1 RE (a) (b) Figure 5. vX = v + iX + gm v RE = iX r + iX + gm iX r RE . This is.89 (a) In ut im edance of emitter follower. 2006] June 30. which is the case for an emitter follower [Fig. In the equivalent circuit of Fig. of course. 2007 at 13:42 248 (1) 248 Chap.324) (5. 5 Bipolar Ampli ers Exercise What happens if RE = 1? In order to appreciate the usefulness of emitter followers. 5. RE . and hence (5.cls v.325) vX = r + 1 + R : E iX (5. Since the in ut im edance of the CE to ology is inde endent of the collector resistor (for VA = 1). to a much larger value.” This conce t can be i llustrated by an exam le. let us compute their input and output impedances.89(b)]. no coincidence. the current iX and gm v ow through RE . The key observation here is that the follower “transforms” the load resistor. (b) equivalence of CE and f ollower stages. producing a voltage drop e qual to iX + gm v RE . thereby serving as an ef cient “buffer. its value remain s unchanged if RC = 0. Also. Exam le 5.45 A CE stage exhibits a voltage gain of 20 and an out ut resistance of 1 k . Deter . Adding the voltages across r and RE and equating the result t o vX .89(a). 5. (5.326) This ex ression is identical to that in Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Assume = 100. 5.90(a). and the follower is biased source. . (b) An emitter the CE stage and the with an ideal current of the CE am li er if (a) The stage drives an 8 s eaker dir follower biased at a current of 5 mA is inter osed between s eaker. The voltage gain therefore de grades drastically. the equivalent resistance seen at the collector is now given by the arallel combination of RC and the s eaker im edance. VA = 1. Rs . reducing the gain from 20 to 20 RC jj8 =RC = 0:159.Solution (a) As de icted in Fig. ¡ mine the voltage gain ectly.

5.327) (5. we need not resort to a small signal model here as Rout can be obtained by ins ection. 5.cls v. the out ut resistance can be viewed as the arallel combina tion of two com onents: one seen looking “u ” into the emitter and another looking “do wn” into RE .91 (a) Output impedance of a follower. (5. 5. £ ¡ VCC RC Q2 Q1 R in1 I1 C1 R s ¡ £ .91(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. assuming the circuit is d riven by a source im edance RS [Fig. the former is equal to RS = + 1 + 1=gm. From Fig. the voltage gain of the CE stage dro s from 20 to substantial im rovement over case (a). We now calculate the out ut im edance of the follower.91(a)].3 Bi olar Am li er To ologies 249 1 kΩ VCC RC R s Q1 C1 v in 1 kΩ v in (a) (b) Figure 5.328) 20 RC jjRin1 =RC = 10:28. a Exercise Re eat the above exam le if the emitter follower is biased at a current of 10 mA . 5. we note that Rin1 = r2 + + 1Rs = 1058 : Thus. 2006] June 30. ( ) components of output resistance. 2007 at 13:42 249 (1) Sec. and hence RS VCC Q1 RE R out RE RS VCC Q1 RS 1 + gm β+ 1 RE (a) ( ) Figure 5.90(b). 5.90 (a) CE stage and (b) two stage circuit driving a s eaker. (b) From the arrangement in Fig.88. Interestingly. As illustra ted in Fig.

£ £ .R S Rout = + g1 jjRE : +1 m (5.88( c) y setting vin to zero. 5.329) This result can also e derived from the Thevenin equivalent shown in Fig.

92 Follower including transistor output resistance. the re sults o tained a ove can e readily modi ed to re ect this nonideality. RE jjrO RE jjrO + RS 1 + g1 + m Rin = r + + 1RE jjrO £ £ £ £ £ £ £ £ . 2007 at 13:42 250 (1) 250 Chap. rO appears in parallel with RE . Figure 5. We say the follower operates as a good “voltage uffer” e cause it displays a high input impedance (like a voltmeter) and a low output imp edance (like a voltage source). there y providing higher “driving” capa ility.92 illustrates a key point that facilitates the analysis: in small-signal operation . We can therefore rewrite Eqs.cls v. Effect of Transistor Output Resistance Our analy sis of the follower has thus far neglected the Early effect. RS . to a much lower value.323). 2006] June 30. (5.326 ) and (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5 Bipolar Ampli ers Equation (5.329) reveals another important attri ute of the follower: the circui t transforms the source impedance. (5. Fortunately.329) as VCC RS v in Q1 RE rO v in RS Q1 RE rO Figure 5.

Since RE Solution = 1.43) ut with a nite source impedance RS .332) etermine the small-signal properties of an emitter follower using an ideal curr ent source (as in Example 5. we have rO RS + 1 rO + + 1 g m Rin = r + + 1rO £ ¢ .330) (5.331) (5.46 (5.Rout = RS 1 + g1 jjRE jjrO : + m Av = Example 5.

334) (5. and hence (5.337) + 1rO : Av rO .336) (5. gm rO 1.335) Also.Rout = RS 1 + g1 jjrO : + m Av = rO + RS 1 + Rin (5.333) (5.

a condition typically valid. iL β+ 1 vX VCC Q1 iL Load Figure 5.19 for the CE stage. the follower draws only iL = + 1 from t he source voltage (Fig.94 Biasing a follower e resistor. the current owing through R1 and R2 is chosen to e much greater than the a se current. 5.93 Current ampli cation in a follower. Exercise How are the results modi ed if RE 1? The uffering capa ility of followers is sometimes attri uted to their “current ga in. 2007 at 13:42 251 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Emitter Follower with Biasing The iasing of emitter followers entails de ning ot h the ase voltage and the collector (emitter) current. ( ) single as £ £ £ £ £ £ £ £ £ £ £ £ . Thus. unlike the CE topology. we can say th at for a current iL delivered to the load.” Since a ase current iB results in an emitter current of + 1iB . y means of (a) resistive divider.94(a) depicts a n example similar to the scheme illustrated in Fig. VCC R1 C1 X R2 RE Q1 Vout v in RB C1 IB X Y RE Q1 Vout VCC v in (a) ( ) It is interesting to note that. Figure 5. 5.3 Bipolar Ampli er Topologies 251 We note that Av approaches unity if RS + 1rO . the emitter follower can operate with a ase voltage near VCC . allowing the same voltage for the ase without driving Q1 into saturation £ £ £ £ £ Figure 5. 5. As us ual.cls v.93). 2006] June 30. This is ecause the collector is tied to VCC . vX sees the load impedance multiplied y + 1.

= 100.94( ) employs RB = 10 k and RE = 1 k .16 A. 5. followers are often iased as shown in Fig.94( ).. For this reason.3. we follow the iterative procedure descri ed in Se ction 5. where RB IB is chosen much less than the voltage drop across RE . and VCC = 2:5 V. The following example illustrates this point. What happens if drops to 50? Example 5. thus lowering the sens itivity to . The follower of Fig.2. Calculate the ias current and voltages if IS = 5 10. 5. Writ- £ £ £ £ £ £ .47 Solution To determine the ias current.

5 Bipolar Ampli ers RB IC + V + R I = V . with VBE (5. In integrated circuits.4 Summary and Additional Examples This chapter has created a foundation for ampli er design. this issue is resolved y replacing the emitter resistor with a constant current source (Fig. Under this condi tion.cls v. and RE gives £ £ £ £ . if VCC rises. BE E C CC which. The reader is encouraged to repeat the a ove iterations with = 50 and determine the exact current. That is. 5. we have £ £ £ £ £ £ £ ing a KVL through RB . for = 50. Now.94 suffer from supply-dep endent iasing. so do VX and VY . IE = 1:593 V . 2007 at 13:42 252 (1) 252 Chap. leads to IC = 1:545 mA: (5.95 Capacitive coupling at input and output of a follower. 5. IB RB = 159 mV whereas RE IC = 1:593 V. 2006] June 30. Thus.340) a value close to that in (5. reducing the drop across RE y 159 mV. the topologies of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IB RB i s dou led ( 318 mV). the ase-emitter junction. ut the i as current remains constant.338) 800 mV. emphasizing that a prop = 748 mV. since IEE is c onstant. is the circuit more or less sensitive to the variatio n in ? As manifested y Eq. (5. 5. Using this value in Eq.339) and hence relatively accurate. (5.338). VCC RB C1 Q1 C2 RL v in Figure 5.339) It follows that VBE = VT lnIC =IS IC = 1:593 mA. Exercise If RB is dou led. we expect that variation of and hence IB RB negligi ly affects the voltage drop across RE and hence the emitter and collector currents. (5. 0:159 V=1 k = 1:434 mA.338).95). Since IB RB RE IC . As a rough estimate. implying that a twofold change in leads to a 10 change i n the collector current. so are VBE and RB IB .

96.er ias point must e esta lished to de ne the small-signal properties of each cir cuit. 5. each serving a speci c application. the three ampli er topologies studied here exhi it di fferent gains and I/O impedances. epicted in Fig. CE and CB st ages can provide a voltage gain greater than unity and their input and output im pedances are independent of the load and source impedances. respectively (if £ £ £ ¢ £ .

341) (5. 5.96 Summary of £ ipolar ampli er topologies. 5. 2007 at 13:42 253 (1) Sec.43(a) and satis es Eq.97(c)].48 = 1. RS . our emphasis is on solution y inspection and hence intuitive understanding of the circuits. On the other hand. VCC V in Vout V £ £ . 5. revealing that R1 appears etw een ase and ground. followers display a voltage gain of at most unity u t their terminal impedances depend on the load and source impedances. 2006] June 30. determine the voltage gain of the circuit shown in Fig. we consider a num er of challenging examples. (5. 5. Assuming VA Example 5. As usual. a nd R1 with a Thevenin equivalent [Fig.97 (a) Example of CE stage. In this se ction. Replacing vin . we have Solution vThev = R R1R vin 1+ S RThev = R1 jjRS : The resulting circuit resem les that in Fig.97(a).342) vout R2 jjRC vThev = . ( ) equivalent circuit with C1 shorted. and R2 etween collector and ground. 5. VCC RC v out Q1 RE v in R1 RS Q1 RE R2 RC v out v Thev R Thev Q1 RE RC v out R2 R1 RS C1 R2 v in (a) ( ) (c) Figure 5. We assume various capacitors use d in each circuit have a negligi le impedance at the signal frequencies of inter est. RThev + 1 + RE : + 1 gm £ £ £ £ £ £ £ £ £ £ Figure 5.cls v. (c) simpli ed circuit . The simpli ed ac model is depicted in Fig.185): (5.97( ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4 Summary and Additional Examples CE Stage CB Stage Follower 253 VCC RC Vout V in Q1 V in Q1 RC VCC Q1 Vout RE VA = 1). seeking to improve our circ uit analysis techniques.

343) .(5.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. 2007 at 13:42 254 (1) 254 Chap.cls v. RS . R2 appears as an emitter degene ration resistor.345) £ £ £ £ R1 + RS : vin E + 1 gm £ .98( ).98 (a) Example of CE stage. (5. 5.344) Exercise What happens if a very large capacitor is added from the emitter of Q1 to ground ? Assuming VA Example 5. compute the voltage gain of the circuit shown in Fig. As shown in the simpli ed diagram of Fig. RC RThev + 1 + R vin 2 + 1 gm and hence (5. and R1 with a Th evenin equivalent and utilize Eq.185): Solution vout = . ( ) simpli ed circuit. we replace vin . As in the a ove example. 5 Bipolar Ampli ers Su stituting for vThev and RThev gives R2 jjRC R1 vout = . VCC RC C1 v out Q1 R1 C2 (a) v out RS Q1 R1 R2 RC v in RS R2 v in I1 ( ) Figure 5.49 = 1.98(a). R1 jjRS + 1 + R (5. 2006] June 30.

vout = . RC R1 RS jjR1 + 1 + R R1 + RS : vin 2 + 1 gm (5.346) Exercise What happens if C2 is tied from the emitter of Q1 to ground? .

347) Av = 1 .348) (5. 5.4 Summary and Additional Examples 255 5. £ £ £ £ £ £ £ . Calculate the voltage gain of the circuit in Fig.100(a) if VA Example 5.75 that Req = R1 1 + g 1 : + m2 The simpli ed model in Fig.RC = 1 : + R1 1 + g 1 gm1 + m2 The input impedance is also o tained from Fig.99 (a) Example of CE stage. ( ) simpli ed circuit. 5.349) Rin = r1 + + 1Req = r1 + R1 + r2 : (5. Recall from Fig. 5. compute the voltage gain and input impedance of th e circuit shown in Fig.75: (5. Example 5. Solution The circuit resem les a CE stage (why?) degenerated y the impedance seen at the emitter of Q2 . VCC RC v out Q1 v in I1 R eq (a) ( ) RC VCC Q2 VB R1 v in v out Q1 R eq Figure 5.cls v.350) (5. Req . 5.RC gm1 + Req .50 Assuming VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51 = 1.99(a).99( ) thus yields (5. 2006] June 30.351) Exercise Repeat the a ove example if R1 is placed in series with the emitter of Q2 . 2007 at 13:42 255 (1) Sec. 5.

101(a) if VA VCC RC v out Q1 R eq R in (a) Example 5. as given y E q. we recognize that Q2 resem les an emitter follower.100 (a) Example of CB stage. 5 Bipolar Ampli ers v out Q1 RS RC R1 (a) ( ) Figure 5. 5. Since the ase is at ac ground.g. concludin g that Req can e viewed as the output resistance of such a stage.. RC Q2 RB RE R in ( ) Q1 R eq Figure 5. ut with RC replaced y RC jjR1 : 1 Av = RC jjR1 : RS + g m Solution (5.cls v. To o tain Req .329): £ £ £ £ £ £ £ What happens if RC is replaced y an ideal currents source? £ £ £ £ £ £ £ £ £ £ £ £ ¢ .271). R1 appears in parallel with RC and R2 is shorted to ground on oth ends [Fig.101( )]. 5. 2007 at 13:42 256 (1) 256 VCC RC v out C1 v in RS Q1 R2 CB v in R1 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.91(a). ( ) simpli ed circuit. 5. e.101 (a) Example of CB stage.52 = 1.ase device (why?) ut with a resistanc e Req in series with its ase [Fig. (5. In this circuit. the topology in Fig. 2006] June 30.100( )].352) Exercise etermine the input impedance of the circuit shown in Fig. The voltage gain is given y (5. Q1 operates as a common. 5. ( ) simpli ed circuit.

Solution Req = .

RB 1 +1 + g m2 jjRE : (5.353) .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30. from Fig. we o serve that Rin contains two components: one equal to the resistance in series with the ase.4 Summary and Additional Examples 257 Now. 2007 at 13:42 257 (1) Sec. 5. Req . 5. and another equ al to 1=gm1 : eq Rin = R+ 1 + g 1 £ £ £ £ . divided y + 1.101( ).

Exercise What happens if the current gain of Q2 goes to in nity? Example 5. Noting that X is at ac ground. we construct the simpli ed circuit shown in Fig. R2 .102(a) with VA 1. R S . VCC RS Q1 v in R1 X C2 R2 RE v out v in RS R1 Q1 RE ( ) rO v out R2 (a) R Thev Q1 v Thev RE (c) v out R2 r O Figure 5.354) (5. ( ) circuit with C1 shorted. 5. (5. and rO appear in parallel [Fig. 5. where the output resistance of Q1 is explicitly drawn. (c) s impli ed circuit.355) The reader is encouraged to o tain Rin through a complete small-signal analysis and compare the required “manual la or” to the a ove alge ra.m1B11R + = +1 + 1 gm2 jjRE + gm1 : 1 (5. Replacing vin . 102( ). 5.356) £ £ £ £ £ £ £ .102 (a) Example of emitter follower. and R1 with their Thevenin equivalent and recognizing that RE . we employ Eq.102(c)].330) and write Solution vout RE jjR2 jjrO vThev = RE jjR2 jjrO + 1 + RThev g +1 m (5.53 Compute the voltage gain and the output impedance of the circuit depicted in Fig .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 258 (1) 258 Chap.cls v.357) Rout = RThev + g1 jjRE jjR2 jjrO +1 . 2006] June 30. (5. 5 Bipolar Ampli ers and hence vout = RE jjR2 jjrO R R1R : vin R jjR jjr + 1 + RS jjR1 1 + S E 2 O g +1 m For the output resistance.332): (5. we refer to Eq.

= g1 m RS+jjR1jjRE jjR2 jjrO : +1 m .

54 etermine the voltage gain and I/O impedances of the topology shown in Fig. 5 .(5.359) Exercise What happens if RS = 0? Example 5. Solution We identify the stage as a CE ampli er with emitter degeneration and a composite c ollector load. VCC R B2 R eq2 v in R eq1 R B1 Q2 Q1 RC v out Q3 RE v in Q3 RE R eq1 R eq2 RC v out (a) ( ) Figure 5.75 B Req1 = R+11 + g 1 : m2 (5.10 3(a).103 (a) Example of CE stage. ( ) simpli ed circuit.358) (5.360) £ £ £ £ ¢ . we have from Fig. 5. we represent the role of Q2 and Q3 y the impedan ces that they create at their emitter. Assume VA = 1 and equal ’s for npn and pnp transistors. As the rst step. Since Req1 denotes the impedance seen loo king into the emitter of Q2 with a ase resistance of RB 1 .

B Req2 = R+21 + g 1 .103( ). 2006] June 30. It follows that (5.362) (5.361) Av = . Rin = r3 + + 1RE + Req1 £ . 2007 at 13:42 259 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. m1 leading to the simpli ed circuit shown in Fig.cls v. 5. 5. R B1 + 1 + 1 + R E + 1 gm2 gm3 RC + Req2 (5. Req1 + g 1 + RE m3 B RC + R+21 + g 1 m1 : =.363) Also.5 Chapter Summary 259 Similarly.

In order to o tain the required small-signal ipolar device parameters such as gm . carry a certain collector current and operate in the active region.365) + 1 RE + + 1 g m2 Rout = RC + Req2 B = RC + R+21 + g 1 : m1 (5.. Voltage ampli ers must ideally provi de a high input impedance (so that they can sense a voltage without distur ing t he node) and a low output impedance (so that they can drive a load without reduc tion in gain). respectively. the tra nsistor must e “ iased.367) Exercise What happens if RB 2 ! 1? 5. r .366) (5. = r3 + and (5. Signals simply pertur these conditions.” i.5 Chapter Summary In addition to gain. and 1=gm (with ase grounded).364) (5. and emitter of a ipolar transistor are equal to r (with emitter grounded). Biasing techniques esta lish the required ase-emitter and ase-collector voltages while providing the ase current. rO (with emitter grounded).e. the input and output impedances of ampli ers determine the ea se with which various stages can e cascaded. The impedances seen looking into the ase. £ £ £ £ £ £ £ £ £ £ £ £ £ £ .RB1 + 1 . collector. and rO .

a moderate input impedance. 2006] June 30. E mitter degeneration raises the output impedance of CE stages considera ly. The CE stage provides a moderate voltage gain. Pro lems 1. The C B stage provides a moderate voltage gain. a high input impedance. 5. a low input impedance.ase stages and emitter followers. Emitter degeneration improves the linearity ut lowers the voltage gain.cls v.iased. (Recall from Chapter 3 that each diode eha ves as a linear 1 R1 1 R1 2 R1 1 (a) ( ) (c) R in R in R in 2 Figure 5. 5. etermine the average power d elivered to a load resistance RL and plot the result as a function of RL . only three ampli er topologies are possi le: com mon-emitter and common.104 resistance if the voltage and current changes are small. and a moderate output impedance. serving as a good voltage uff er. A ssume all diodes are forward. and a low output impedance. 2007 at 13:42 260 (1) 260 Chap. Assume VA VCC R1 Q1 R2 R in R in (a) ( ) (c) = 1.104.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and a moderate output imped ance. 5 Bipolar Ampli ers With a single ipolar transistor. e termine the small-signal input resistance of the circuits shown in Fig.) 3. 2. An antenna can e modeled as a Thevenin equivalent having a sinusoidal voltag e source V0 cos !t and an output resistance Rout .105. VCC Q1 VCC Q1 R1 R in VCC Q1 R in Q2 (d) ¢ £ £ £ £ ¢ £ £ £ ¢ £ £ ¢ ¢ £ £ £ ¢ ¢ £ . Compute the input r esistance of the circuits depicted in Fig. The voltage gain expressions for CE and CB stages are similar ut for a sign. The emitter follower provides a voltage gain less than unity.

108. IS = £ ¢ . 6. 5. 5. Compu te the output impedance of the circuits shown in Fig.105 4. 5.106. Assume VA = 1.107. 5. 5. Compute the output resistance of the circuits depicted in Fig.109. Compute the ias po int of the circuits depicted in Fig. etermine the input impedance of the circuits depicted in Fig. 7.Q2 Figure 5. Assume = 100.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 A.106 VCC VCC Q1 R in R1 Q1 R in R1 (a) ( ) Ideal VCC Q1 R in Q2 VB R1 (c) VB VCC Q2 Q1 R in (d) (e) VCC Q2 R in Q1 Figure 5.5 Chapter Summary R out RB Q1 R1 R out VB Q1 Q2 ( ) (c) (d) 261 R out Q1 Q1 Q2 R out VCC VB (a) Figure 5.16 A. and VA = 1. 5. Construct the small-signal equivalent of each of the circuits in Pro lem 7. and VA = 1.108 6 10. 11. £ £ £ £ £ £ . 2006] June 30. 10. Calculate the ias point of the circuits shown in Fig. IS = 510. Assume = 100. 2007 at 13:42 261 (1) Sec. Consider the circuit shown in Fig. IS = 6 10.16 A. Construct the small-signal equivalent of each of the circuits in Pro lem 9. and VA = 1.111.107 VCC Q1 RC R out Q1 Q2 VB ( ) R out (a) Figure 5. 9 . 5. where = 10 0. 5.cls v.110. 8.

2006] June 30. 5 V CC = 2.cls v.5 V 100 k Ω 500 Ω 100 k Ω Cha .5 V 1 kΩ Q1 Q1 Q2 0.110 .5 V Q1 (a) (b) (c) Figure 5.5 V 12 k Ω 1 kΩ Ω 16 k Ω Q1 16 k Ω Q1 Q2 13 k Ω 0.5 V 34 k Ω 3 kΩ 9 kΩ V CC = 2.109 V CC = 2. 2007 at 13:42 262 (1) 262 V CC = 2.5 V Q1 (a) Figure 5.5 V 500 V CC = 2.5 V 1 kΩ 100 k Ω Bi olar Am li ers V CC = 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

= 100 and VA = 1.5 V 50 k Ω 3 kΩ rises 30 k Ω Q1 Figure 5. calculate the value of IS .(b) (c) V CC = 2.111 (a) What is the minimum value of RB that guarantees o eration in the active mode ? (b) With the value found in RB . ¡ .5 mA. how much base collector forward bias is susta ined if to 200? 12. In the circuit of Fig. 5. V CC = 2.5 V RB 2 kΩ 3 kΩ Q1 Figure 5.112.112 (a) If the collector current of Q1 is equal to 0.

2007 at 13:42 263 (1) Sec. and VA = 1. IS = 10. 16.115 (a) Determine the required value of R1 . (a) Determine the collect or currents of Q1 and Q2 . 5. We wish to design the CE stage de icted i n Fig. 5.16 A. IS = 2 10.114 for a gain (= gm RC ) of A0 with an V CC R1 RC Q1 R2 Figure 5. 13.25 mA. wh ere IS 1 = 2IS 2 = 5 10. Ex lain why no solution exists. determine the minim um allowable values of R1 and R2 . 5.5 Cha ter Summary 263 (b) If Q1 is biased at the edge of saturation. The circuit of Fig. Assume = 100. In the circuit of Fig.16 A. What is the maximum achievable in ut im edance here? As sume VA = 1. determine the maximum value of R2 that guarantees o eration of Q1 in the active mode.114 out ut im edance of R0 . 15.5 V R1 5 kΩ Q1 R2 Figure 5. calculate the value of IS .117.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. and VA = 1. (b) What is the error in IC if RE devia tes from its nominal value by 5? 17. 5. = 100. 5.5 V R1 RC 3 kΩ 10 k Ω Q1 R2 R E = 200 Ω Figure 5.115 is designed for a collector current o f 0.116.17 A. 14. ¡ . and VA = 1. 6 10. Re eat Problem 13 for a gm of at least 1=2 6 . 2006] June 30.17 A. 1 = 2 = 100. 18. and VA = 1. (b) Construct the small signal equivalent circuit. T he circuit of Fig. 5. Assume IS = V CC = 2. If = 100.113 must be designed for an in ut im edance of greater than 10 k and V CC = 2. Consider the circuit shown in Fig.113 a gm of at least 1=260 .

cls v. and .16 A.5 V 13 k Ω R1 RC Q1 1 kΩ Q2 12 k Ω R2 RE 400 Ω Figure 5. IS 1 VA = 1. 2006] June 30. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. V CC = 2.116 VCC = 2. 2007 at 13:42 264 (1) 264 V CC = 2.5 V 30 k Ω Cha .117 19. 5 Bi olar Am li ers RC 2 kΩ Q1 R2 R E = 100 Ω Figure 5. In the circuit de icted in Fig.118. 9 kΩ = IS2 = 4 10.5 V 100 Ω 1 = 2 = 100.

(b) Draw the small signal e quivalent circuit.16 k Ω Q1 Q2 Figure 5.5 V RB R 1 kΩ 100 Ω Q1 Figure 5. The circuit of Fig. Com ute the VCC = 2. 20.119 ¡ .119 must be biased with a collector current of 1 mA.118 (a) Determine the o erating oint of the transistor. 5.

2007 at 13:42 265 (1) Sec.16 A. where IS Calculate the o erating oint of Q1 . VX = 1 :1 V.5 V 10 k Ω 1 kΩ = 1. = 100. IS = 8 10.121 23.120 = 6 10.122 forward bias must not exceed 200 mV? Assume IS = 3 10. V CC = 2. a arasitic resistor.5 Cha ter Summary 265 required value of RB if IS = 3 10.122. Due to a manufacturing error.16 A. and VA = 1. 5. 20 k Ω 500 Ω ¡ . = 100 and VA = 1.cls v. = 100. has a eared in ser ies with the collector of Q1 in Fig. = 100. If = 100. and VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. 2006] June 30. 5. In the circuit of Fig. Consider the circuit shown in Fig.121. What is the minimum allowable value of RB if the base collector VCC = 2. what is the value of IS ? V CC = 2. 40 k Ω 22. 5.123. RP .5 V Q1 400 Ω Figure 5. 21.5 V 300 Ω X 10 k Ω Q1 Figure 5. V CC = 2.5 V RB R 1 kΩ 500 Ω Q1 Figure 5. and VA = 1. In the circuit of Fig.120. 5.16 A.16 A. and VA 24.

123 (a) Determine the o erating oint of Q1 .Q1 Figure 5. .

125. 28. 5. and VA = 1. IS 1 = IS 2 = 3 10. and VA = 1. Calculat e the bias oint of the circuits shown in Fig. 5 Bi olar Am li ers (b) Draw the small signal equivalent circuit.5 V Q1 60 k Ω 200 Ω VCC = 2. 27. Assume n n VCC = 2.125 IS = 9 10.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 26. 2006] June 30. V CC = 2. 200 Ω = 100.5 V Q1 Q1 Q2 1 kΩ (a) (b) VCC = 2.5 V Q1 Q2 300 Ω 80 k Ω (b) (a) Figure 5. 25. Assume n n 32 k Ω = 2 n = 100.16 A.124. 5. ¡ ¡ .5 V Q1 VB 500 Ω Q2 Figure 5. Construct the small signal model of the circuits in Problem 26. Determine the bias oint of each circu it shown in Fig. In the circuit of Fig. (b) Construct the small signal equivalent circuit.126. 2007 at 13:42 266 (1) 266 Cha .5 V 32 k Ω 18 k Ω ¡ = 2 n = 100.16 A. 5. VCC = 2.124 (a) Calculate VB such that Q1 carries a collector current of 1 mA.

16 A.127 to lace Q1 at the edge of saturation. We have chose n RB in Fig. 5. 30. Calculate the value of RE in Fig. Draw the small signal model of the circuits in Problem 28. 5. 29. and VA = 1. and VA = 1. IS = 8 10.128 such that Q1 sustains a revers e bias of 300 mV ¡ ¡ ¡ . Determine the forward or reverse bias across the b asecollector junction at these two extremes.100 Ω 18 k Ω Figure 5. Assume = 50.16 A.126 IS = 9 10. 31. But the actual value o f this resistor can vary by 5.

5 V 10 k Ω RE Q1 10 k Ω 5 kΩ Figure 5. The to ology de icted in Fig.5 Cha ter Summary VCC = 2. and VA = 1. Wha t ha ens if the value of RE is halved? 32. 5.128 across its base collector junction. what value of IS yields a collector current of 1 mA in Fig.5 V Q1 20 k Ω 1. Assume = 50.127 VCC = 2. 5. determine the collectorVCC R1 Q1 R2 R1 Q1 R2 R3 (a) (b) Figure 5. 5. If = 80 and VA = 1.) Constructing the circuit shown in Fig.”(The n n cou nter art has a similar to ology.129 33.5 V Q1 RB 1 kΩ 267 5 kΩ Figure 5.130(b ). IS = 8 10. 2007 at 13:42 267 (1) Sec.130(a) is called a “VBE multi lier.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.129? VCC = 2.cls v.6 k Ω Figure 5. 5.16 A. 2006] June 30.130 ¡ .

cls v.) 34. We wish to design the CE stage of Fig. determine the bias curre nt of the transistor. Su ose the bi olar transistor in Fig. 36. 5. The circuit of Fig.5 V Vout V in Q1 Figure 5.133 em loys an ideal current source as the loa d. 37. (The n n counter art ca n also be used.131 allowable su ly voltage if Q1 must remain in the active mode? Assume VA = 1 and VBE = 0:8 V. 2007 at 13:42 268 (1) 268 Cha . 5. If VA = 10 V and VBE = 0:8 V.132 must be designed for maximum voltage gain while maintaining Q1 RC V in 1 kΩ VCC Vout Q1 Figure 5.133 is equal to 50 and the out ut im edance equal to 10 k . The CE stage of Fig. 2006] June 30. 5. 5 Bi olar Am li ers emitter voltage of Q1 if the base current is negligible.131 for a voltage gain of 20. What is the minimum 50 k Ω VCC = 2. If the voltage gain VCC Ideal Vout V in Q1 Figure 5. calculate the required bias cu rrent. 5.132 in the active mode. 35.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.134 exhibits the following hy othetical characterisRC V in 1 kΩ VCC Vout Q1 .

Figure 5. (5.134 tic: IC = IS ex VBE . 2V T and no Early effect.368) . Com ute the voltage gain for a bias current of 1 mA.

For the following two cases. 40.135 39.157) for the gain of a dege nerated CE stage.136 current.135(d) and (e) o erates in soft s aturation. (5. I S = 5 10. 5. Writing gm = IC =VT . 5. Assume VA = 1.5 Cha ter Summary 269 38.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Consider Eq. Re e at Problem 42 for a voltage gain of 100. Calculate the in ut im edance of the circuit. res ectively? 42.137 for a voltage gain of 10 with Q1 o erating at th e edge of saturation.135. determ ine the relative change in the gain if IC varies by 10%: (a) gm RE is nominally equal to 3. we note that gm and hence the voltage ga in vary if IC changes with the signal level. What is the maximum gain that can be achieved in this stage? . Re eat Problem 38 with VA 1.16A. Ex lain why no solution exists. 2007 at 13:42 269 (1) Sec. 43. IC . 5. Determine the voltage gain and I/O im edances of the circuits shown in Fig. (b) gm RE is nominally equal to 7.136 in terms of the collector bias VCC RC Vout V in Q1 RE Figure 5. Ex ress the voltage gain o f the stage de icted in Fig. The more constant gain in the sec ond case translates to greater circuit linearity. If VA = 1. We wish to design the degenerated stage of Fig. and VA = 1. 2006] June 30. Transistor Q2 in Figs. VCC VCC Q2 Vout V in Q1 V in Q1 Q2 R1 Vout V in Q1 VCC Q2 RC Vout (a) (b) (c) VCC Q2 RC Vout V in Q1 V in VCC Q2 Vout RC Q1 (d) (e) Figure 5. 5. and VT . 5. 41. what is the gain if the dc voltage dro s acros s RC and RE are equal to 20VT and 5VT . Calculate the bias current and the value of RC if = 100.cls v.

5. 49. Com ute the voltage gain the I/O im edances of the circuits de icted in Fig.138 47. 2006] June 30.cls v. Assume 1. 5.137 44. Construct the small signal model of the CE stage shown in Fig.5 V RC Vout V in Q1 200 Ω Figure 5. 46.140. Assume VA = 1. 5.43(a) and c alculate the voltage gain. Assume VA = 1. 5. 5.43(a) and rove that the out ut im edance is equa l to RC if the Early effect is neglected. Construct the small signal model o f the CE stage shown in Fig. 5 Bi olar Am li ers VCC = 2. Assume 1. 2007 at 13:42 270 (1) 270 Cha . 45.141. VCC Q2 R1 Vout V in Q1 RE (a) (b) (c) VCC RC Vout V in Q1 Q2 V in Q2 VCC RC Vout Q1 VCC RC V in RB Q1 Q2 Vout V in RB Q1 RC Vout Q2 VCC VB (d) (e) Figure 5.139. 48. Calculate th e out ut im edance of the circuits shown in Fig. Assume 1. Determine the voltage gain and I/O im edances of the circuits shown in Fig. 50. 5. Com are th e out ut im edances of the circuits illustrated in Fig. Using a small signal equivalent circuit. com ute the out ut im edance of a degenerated CE stage with VA 1.138. ¡ ¡ ¡ . Assume VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

¡ .cls v.) 52. 53. assume the ca acitor s are very large.5 VCC RE V in Q1 Cha ter Summary VCC RE V in Vout Q1 RC Vout Q2 V in VCC Q3 VCC RE Q1 Vout RC Q2 Q2 V in VCC Q1 Vout RC 271 RC Q2 (a) (b) (c) (d) Figure 5. and VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. The common base stage of Fig. 5. (5. Is the ga in greater than unity? 54.142. Assume VA = 1.143 is biased with a collector current of 2 mA. 2006] June 30. (a) Calculate the voltage gain and I/O im edances of the circuit. 5.217) and rove that the result remains clo se to r if IB RB VT (which is valid because VCC and VBE ty ically differ by about 0. Calculate vout =vin for each of the circuits de icted in Fig.140 VCC Q1 Q2 R out (a) VCC Q1 Q2 R out (b) Figure 5. 2007 at 13:42 271 (1) Sec.16 A.5 V or higher. Re eat Exam le 5. Also. Writing r = VT =IC .33 with RB = 25k and RC = 250 .141 51. ex and Eq. Assume IS = 8 10. = 100.139 R out R out Q1 Q2 Q1 R out Q2 VCC Q1 RB R1 Q2 VCC I1 (a) (b) (c) Figure 5.

.

142 VCC RC 500 Ω Vout Q1 V in Vb Figure 5. 2007 at 13:42 272 (1) 272 V CC = 2. 2006] June 30.144 (b) (c) (d) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V RC 10 k Ω Vout V in C1 Q1 100 Ω Vout V in 1 kΩ C1 V in 1 kΩ Vout Q1 500 Ω C1 C2 Q1 2 kΩ 11 k Ω C2 (a) (b) (c) 2 kΩ Figure 5. VCC Q3 VCC Q2 RC Vout Q1 V in (a) Figure 5.143 (b) How should VB and RC be chosen to maximize the voltage gain with a bias curr ent of 2 mA? 55. 5 V CC = 2.5 V 1 kΩ 14 k Ω Bi olar Am li ers V CC = 2.5 V 100 k Ω 1 kΩ 50 k Ω Cha .144.cls v. Assume VA = 1. Determine the voltage gain of the circuits shown in Fig. 5.

VCC Q3 RC Vout Vout Q1 V in RS RE Vb V in Vb VCC Q2 Q1 Vout V in RC Q1 RE Vb Vb .

Assume VA 1. Com ute the in ut im edance of the stages de icted in Fig.145.16 A.146. VCC ideal Vout Q1 V in Vb Figure 5. . 2007 at 13:42 273 (1) Sec.147. IS = 8 VCC = 2. 5. VCC R2 R2 R1 Q1 Vb R in Q2 R2 R1 Q1 Q2 R in (b) R in (c) (d) Figure 5.cls v.5 Cha ter Summary 273 56. Consider the CB stage de icted in Fig. where and CB is very large. 5. 1 kΩ = 100. VA = 1. 2006] June 30. Assume VA VCC VCC VCC R1 Q1 Q2 R1 Q1 Q2 R in (a) = 1. 5.145 57.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5.5 V 13 k Ω V out Q1 V in 400 Ω 10.146 58. Calculate the voltage gain and I/O im edances of the CB stage shown in Fig.

Calculate the voltage gain and the I/O im edances of the stage de icted i n Fig.CB 12 k Ω Figure 5.148 if VA = 1 and CB is very large.150 if VA 1.147 59. 62. 61. 5. Re eat Problem 58 for CB = 0. Calculate the voltage gain of the c ircuit shown in Fig. 5. Assume VA = 1. (a) Determine the o erating oint of Q1 . 63.151 rovides two out u ts. If IS 1 = 2IS 2 . 5. (b) Calculate the voltage gain and I/O im edances of the circuit. The circuit of Fig. Com ute the voltage ga in and I/O im edances of the stage shown in Fig. 5.149 if VA = 1 and CB is very large. determine the relationshi between vout1 =vin and vout2 =v in . 60. .

149 VCC ideal V out Q1 V in RS Vb Figure 5. 2007 at 13:42 274 (1) 274 Cha .9.8. Assume VA = 1.152. Calculate the required bias curren t and RE .148 VCC ideal V out Q1 V in R1 CB R2 Figure 5. Assume = 100 and VA = 1. determine the voltage gain of a CB stage with em itter degeneration. 65. A micro hone having an out ut im edance RS = 200 drives an emitter follower as shown ¡ . determine the bias current of Q1 such that the gain is equal to 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and VA 1. Using a small signal model.151 64. 67. 5.cls v. For RE = 100 in F ig.152 must rovide an in ut im edance of greater than 10 k with a minimum gain of 0.150 VCC RC R C V out1 Q1 V in Vb Q2 Vout2 Figure 5. The circuit of Fig. 2006] June 30. 5 Bi olar Am li ers VCC Q2 V out Q1 V in R2 R1 CB Figure 5. 66. Assume 1. 5. a base resistance.

Note that IE1 IC 1 = IB2 = IC 2 = . . Assume = 100 and VA = 1. Figure 5. (c) Com ut e the current gain of the air.5 V V in Q1 Vout RE 275 Figure 5.5 V V in RS Q1 I1 R out Figure 5. Assume VA = 1. 2006] June 30. 5. Determine the bias current such that the out ut im edance does no t exceed 5 VCC = 2. (b) If the base o f Q1 is grounded. 5. 2007 at 13:42 275 (1) Sec.cls v.155 de icts a “Darlington air.” where Q1 lays a role somewhat similar to an emitter follower driving Q2 .154 69. Com ute the voltage gain and I/O im edances of th e circuits shown in Fig. calculate the im edance seen at the emitter of Q2 . (a) If the emitter of Q2 is grounded. Assume VA = 1 and the collectors of Q1 and Q2 are tied to VCC . de ned as IC 1 + IC 2 =IB 1 . 68.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.154.5 Cha ter Summary VCC = 2.153 .153. 5. VCC V in Q1 Vout Vb Q2 (a) VCC V in Q1 Vout Q2 (b) (c) VCC V in RS Q2 Q1 Vout VCC V in RE Q2 Q1 Vout RE V in VCC Q1 Vout Q2 (d) (e) Figure 5.152 in Fig. determine the im edance seen at the base of Q1 .

158 illustrates a cascade of an emi tter follower and a common emitter stage.155 70.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.) Also. (But for bias calculations.156 Q1 . 5. RCS . 5 Bi olar Am li ers Q1 Q2 Figure 5.16 VCC = 2. assume VA = 1.5 V 10 k Ω V in C1 Q1 C2 100 Ω 1 kΩ Vout Figure 5.157. 71. (a) Calculate the out ut im edance of the current source. = 100. In the emitter follower shown in Fig. and VA = 5 V.cls v.157 A. ¡ .156. 2007 at 13:42 276 (1) 276 Cha .158 sume VA 1. assume the ca acitors are very large. Assume IS = 7 10. Q2 serves as a current source f or the in ut device VCC V in Q1 R CS Vb Q2 RE Figure 5. (b) Re lace Q2 and RE with the im edance obtained in (a) and com ute the voltage gain and I /O im edances of the circuit. 2006] June 30. 72. Figure 5. Determine the voltage gain of the follower de icted in Fig. 5. AsVCC V in RC Q1 X RE Q2 Vout Figure 5.

cls v. estimate the minimum allowable value of CB . (b) Calculate the voltage gain. design the stage and calculate the required su ly voltage.159 VA = 1. ¡ ¡ . vout =vin = vX =vin vout =vX .161 must be designed for minimum su ly voltage but with a voltage gain of 15 and an out ut im edance of 2 k . 2006] June 30.161 must achieve maximum in ut im edance but with a voltage gain of at l east 20 and an out ut im edance of 1 k . (b) Determine the voltage gain. 74. 5.161 for maximum voltage gain but with an out ut VCC = 2. 5. 76. Assume VCC V in RC Q1 X RE Q2 Vout Vb Figure 5. Design the stage.5 Cha ter Summary 277 (a) Calculate the in ut and out ut im edances of the circuit. 5. and in ut im edance of VCC = 2. 5. Figure 5. vout =vin = vX =vin vout =vX . 77. The stage de icted in Fig. Allowing the transistor to ex erience at most 40 0 mV of base collector forward bias. 2007 at 13:42 277 (1) Sec.161 im edance no greater than 500 . and an out ut im edance of 1 k .160 greater than 5 k . If the lowest signal frequen cy of interest is 200 Hz. If the transistor is allowed to sustain a b asecollector forward bias of 400 mV.159 shows a cascade of an emitter follower and a common base stage.16 A. The CE stage of F ig. 5. We wi sh to design the CE stage of Fig. assume = 100. and VA = 1. 75.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. unless ot herwise stated.160 for a voltage gain of 10.5 V RB V in RC Vout Q1 Figure 5. Design Problems In the following roblems. design the stage. (a) Calculate the I/O im edances of the circuit. 73.5 V RB V in CB RC Vout Q1 Figure 5. Design the CE stag e shown in Fig. IS = 6 10.

a voltage gain of 5. Also. What is the mini mum required ower dissi ation? Make the the same assum tions as those in Proble m 83. 85. Assume RE sustains a voltage dro of 300 mV and the current ow ing through R1 is a roximately 10 times the base current. The stage of Fig. Design the CE stage of Fig. 5. 2006] June 30. Design the stage of Fig. and Q1 ex er iences a maximum base collector forward bias of 400 mV. determine the trade off between the o wer dissi ation and the out ut im edance of the circuit. 5.163 for an out ut im edance of 200 and a voltage gain of 20. 81. and a voltage dro o f 200 mV across RE . 5. 82. 5. Design the common base stage shown in Fig. 5. 84.5 V R1 V in R2 RE RC Vout Q1 Figure 5. 5 Bi olar Am li ers 78. 83. 2007 at 13:42 278 (1) 278 Cha . Make the same assum tions as those in Problem 83.162 for a ower budget of 5 mW.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. assume the curren t owing through R1 is a roximately 10 times the base current.162 for a voltage gain of 5 and an out ut V CC = 2. If the voltage gain must be equal to A0 . 5.163 for a v oltage gain of 20 and an in ut V CC = 2. Design t he degenerated CE stage of Fig. We wish to design the CB stage of Fig.163 must achieve a vol tage gain of 8 with an out ut im edance of 500 . and the current owing through R1 is a roximately 10 times the base current. 80. Design the CB am li er of Fig. ¡ ¡ ¡ . Assume a voltage dro of 10VT = 260 mV across RE so that this resistor does not affect the in ut im edance signi cantly. 5.162 im edance of 500 . assuming that RE sustains 200 mV. The CB am li er of Fig.161 for minimum ower dissi ation. We wish to design the CE stage of Fig.163 im edance of 50 .5 V R1 CB Q1 R2 RE Vin RC Vout Figure 5. 79.161 for a ower budget of 1 mW and a voltage gain of 20.162 must be designed for maximum voltage gain but an out ut im edance of no g reater than 1 k . 5. Design the circuit with the sam e assum tions as those in Problem 83. Assume the current owing through R1 is a roximately 10 time s the base current.163 for a ower budget of 5 mW and a vo ltage gain of 10. 5. Design the circuit. 86. and the lowest fre quency of interest is 200 Hz.

VA. that it can drive? 90. The follower shown in Fig.n n = 5 V. Assume RL = 200 .8. The follower of Fig.cls v.n n = 5 10. n = 3:5 V. 5.164 im edance of greater than 10 k .16 A. Design the circuit assuming that the lowest frequency of interest i s 100 MHz.5 V R1 V in Q1 Vout RL Figure 5.166 ¡ . 5.85 and an in ut VCC = 2. What is the minimum load resistance. 89. VA.16 A.165 must drive a load resistance. RL = 50 .164 fo r a voltage gain of 0. Make the same assum tion s as those in Problem 83. with a voltage VCC = 2.) SPICE Problem s In the following roblems. Design the CB stage of Fig. 5.16 4 must consume 5 mW of ower while achieving a voltage gain of 0. 88. IS. n = 50. 5. Design the emitter follower shown in Fig. assume IS.5 V R1 V in C1 Q1 RE C2 Vout RL Figure 5. 5. (Hint: select the voltage dro across RE to be much greater than VT s o that this resistor does not affect the voltage gain signi cantly. V CC = 2. n n = 100. 2007 at 13:42 279 (1) Sec. 5.5 V 100 k Ω 1 kΩ V in C1 C2 P Vout Q1 500 Ω Figure 5. The common emitter shown in F ig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.165 gain of 0.166 must am lify signals in the range of 1 MHz to 100 MHz. RL . 91.5 Cha ter Summary 279 87. 2006] June 30.9. n = 8 10.163 for the minimum su ly voltage if an in ut im edance of 50 and a voltage gain of 20 are required.

e. Unfortunately. 1 F.. (One a roach is to insert a resistor in series with Vin and adjust its value until VP =Vin or Vout =Vin dro s by a facto r of two.cls v.168.) 92. V CC = 2. 2007 at 13:42 280 (1) 280 Cha . How much can VCC fall while the gain of the circuit degrades by only 5? 94. 5. determine the bias conditions of Q1 and verify that i t o erates in the active region. Which one of th e two circuits is less sensitive to su ly variations? .5 V 100 k Ω 1 kΩ N C1 C2 IX VX Q 1 1 kΩ 500 Ω Figure 5. jVP =Vin j 0:99) at 10 MHz.167. 5. (c) Plot jVout =Vin j as a function of freq uency for several values of C2 . Determine the value o f C2 such that the gain of the circuit at 10 MHz is only 2 below its maximum (i.166. 5 Bi olar Am li ers (a) Using the . V CC = 2. Predicting an out ut im edance of about 1 k for the stage shown i n Fig. Ex lain why. 2006] June 30. (b) Select the value of C1 such that i t o erates as nearly a short circuit (e.5 V 10 k Ω 1 kΩ Vout Q1 V in C1 P Figure 5.g. Re eat Problem 93 for the stage illustrated in Fig.g. a student constructs the circuit de icted in Fig. (d) Determine the in ut im edance of the circuit at 10 MHz. 5.167 93.e . Consider the self biased stage shown in Fig. 1 nF. where VX re resents an ac source with zero dc value..168 (a) Determine the bias conditions of Q1 . for C2 = 1 F). and 1 F.169. VN =VX is far from 0. This ensures that C1 acts as a short cir cuit at all frequencies of interest.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (d) With the ro er value of C2 found in (c). determine the in ut im edance of the circuit at 10 MHz.. 5. 5. choose the value of C1 such that jVP =Vin j 0:99 at 1 MHz. (b) Running an ac analysis. (c) Com ute the voltage gain of the circuit at 10 MHz.o command. (e) Su ose the su ly voltage is rovided by an agin g battery.

.

2006] June 30. V CC = 2.170 (a) Determine the value of RE 1 such that Q2 carries a bias current of 2 mA. 5.169 95. The am li er shown in Fig.5 V 10 k Ω 1 kΩ 281 V in C1 1 kΩ Vout Q1 Figure 5. and C3 if each one is to de grade the gain by less than 1.170 em loys an emitter follower to drive a 50freq uency of 100 MHz. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 Cha ter Summary V CC = 2.cls v. (c) What is the signal attenuation of the emitter follower? Does the overall gain increase if RG2 is reduced to 100 ? Why? .5 V 2 kΩ 600 Ω load at a V in C1 2 kΩ X Q1 R E1 C2 Q2 200 Ω C3 50Ω Vout Figure 5. (b) Determine the minimum acce table value of C1 . C2 . 2007 at 13:42 281 (1) Sec.

g. The key oint here is that the densi ty of electrons in the channel varies with V1 . Illustrated in Fig. memory chi s co ntaining billions of transistors. O eration of MOSFETs MOS Structure O eration in Triode Region O eration in Satur ation I/V Characteristics MOS Device Models Large−Signal Model Small−Signal Model PM OS Devices Structure Models 6. In this cha ter. 1(b)? As ositive charge is laced on the to late.1 Structure of MOSFET Recall from Cha ter 5 that any voltage controlled current source can rovide sig nal am li cation.. where C denotes the ca acitance between the two lates. Conceived in the 1930s but rst r ealized in the 1960s.. we analyze the structure and o eration of MOSFETs. e. such a structure o erates as a ca acitor because the ty e silicon is somewhat conductive. Our treatment of MOS devices and c ircuits follows the same rocedure as that taken in Cha ters 2 and 3 for n junc tions.1(a).cls v. (Even though do ed with acce tors. and so histicated communication circuits rovi ding tremendous signal rocessing ca ability. metal) late. we begin with a sim le geometry consisting of a con ductive (e. 6.g. seeki ng models that rove useful in circuit design. This revolution h as culminated in micro rocessors having 100 million transistors. What ha ens if a otential difference is a lied as shown in Fig. Figure 6 illustrates the sequence of conce ts covered in this cha ter. 2006] June 30. electrons.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 282 ¡ ¡ ¡ ¡ ¡ . an insulator (“dielectric”). from the iece of silicon. it attracts negative charge . “mirroring” any charge de osited on the to late. and a do ed iece of silic on. as evident from Q = CV . 2007 at 13:42 282 (1) 6 Physics of MOS Transistors Today’s eld of microelectronics is dominated by a ty e of device called the metal o xidesemiconductor eld effect transistor (MOSFET). otentially serving as a good conductive ath if the electron density is suf ciently high. In Cha ter 7.) We therefore obse rve that a “channel” of free electrons may be created at the interface between the i nsulator and the iece of silicon. In order to arrive at the structure of the MOSFET. we utilize the mode ls to study MOS am li er to ologies. MOSFETs (also called MOS devices) offer unique ro erties that have led to the revolution of the semiconductor industry. the ty e silicon does contain a small number of electrons. MOSFETs also behave as such controlled sources but their charact eristics are different from those of bi olar transistors. 6.

1(c). wherein the arrow signi es the source terminal. The gate late must serve as a good conductor and was i n fact realized by metal (aluminum) in the early generations of MOS technology. Called the “gate” (G). to achieve a strong control of Q b y V . the to conductive late resides on a thin dielectric (insulator) layer.” To allow current ow thro ugh the silicon material..2(a) as a candidate for an am lifying device. V1 can control the current by adjusting the resistivit y of the channel.1 Conductive Plate Structure of MOSFET 283 Insulator V1 −Ty e Silicon Channel of Electrons V1 V2 (a) (b) (c) Figure 6. i. 2007 at 13:42 283 (1) Sec. The foregoing thoughts lead to the MOSFET structure shown in Fig. by reducing the thickness o f the dielectric layer se arating the two lates. either o f these two terminals can drain the charge carriers from the other.2(c) de icts the circuit symbol for an NMOS transistor. with n ty e source/drain and ty e substrate.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6. this transistor o erates with electrons rather than holes and is therefore called an n ty e MOS (NMOS) device. let us consider the ty es of mater ials used in the device. 6.1 The ability of silicon fabric ation technology to roduce extremely thin but uniform dielectric layers (with t hicknesses below 20 A today) has roven essential to the ra id advancement of mi croelectronic devices. de ending on the voltages a lied to the device. for exam le.4.e. Figure 6. it was discovered that noncrystaline silicon (“ olysilicon” or sim ly “ oly”) w ith heavy do ing (for low resistivity) exhibits better fabrication and hysical ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ . Equation Q = CV suggests that.2(a) reveals that the device is symmetric with res ect to S and D.2.1 (a) Hy othetical semiconductor device. Bef ore delving into the o eration of the MOSFET. (Note that the current refers to take the ath of least resis tance.2(b) for sim licity. thus owing rimarily through the channel rather than through the entire bo dy of silicon. (The ty e counter art is studied in Section 6.) We draw the d evice as shown in Fig. the value of C must be maximized. two contacts are attached to the substrate through two heavily do ed n ty e regions because direct connection of metal to the substrat e would not roduce a good “ohmic” contact. However. we allow a current to ow from left to right thro ugh the silicon material.cls v. 6. which itsel f is de osited on the underlying ty e silicon “substrate. As ex lained in Section 6. 2006] June 30. 6. Figure 6.2 These two terminals are called “source” (S) and “drain” (D) to indicate that the former can rovide charge carriers and the lat ter can absorb them.) This will serve our objective of building a voltage controlled c urrent source. The de endence of the electron density u on V1 leads to an interesting ro erty: if. as de icted in Fig. (b) o eration as a ca acitor. (c) current ow as a result of otential difference.

ro erties. . the term “ohmic” contact em hasizes bidirectional current ow—as in a resistor. where is the “dielectric con stant” (also called the “ ermitivity”). and t is the diel ectric thickness. today’s MOSFETs em loy olysilicon gates. Thus. The dielectric layer s andwiched between the gate and the substrate lays a critical role in the erfor mance of transistors and is created by growing silicon dioxide (or sim ly “oxide”) o n to 1 The ca acitance between two lates is given by A=t. 2 Used to distinguish it from other ty es of contacts such as diodes. A is the area of each late.

cls v.” r eferring to a fabrication method used in early days of microelectronics. Figure 6.2 (a) Structure of MOSFET. of the silicon area. only the de letion region ca acita nce associated with the two diodes must be taken into account. (c) circuit symbol. The n+ regions are sometimes called source/drain “diffusion. 2006] June 30. 6. 6 Physics of MOS Transistors Source Gate Conductive Plate Drain n+ −substrate Insulator (a) G S D n+ G n + n + S D (c) −substrate (b) Figure 6. (b) side view. The ox ide thickness is denoted by tox . As ex lained later.3). Polysilicon S/D Diffusion Oxide n+ t ox = 18 A Length 90 nm ¡ ¡ ¡ ¡ ¡ . 2007 at 13:42 284 (1) 284 Cha .3 shows some of the device dimensions in today’s state of the art MOS technologies. Thus. We shou ld also remark that these regions in fact form diodes with the ty e substrate (Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ro er o eration of the transistor requires that these junctions remain reverse biased.

6.4.n+ −substrate Oxide−Silicon Interface Figure 6. 6.2 O eration of MOSFET This section deals with a multitude of conce ts related to MOSFETs. . The outline is shown in Fig.3 Ty ical dimensions of today’s MOSFETs.

Note that the gate terminal draws no (lo w frequency) current as it is insulated from the channel by the oxide. the substrate itself is also tied to zero. Moreover. the ositive c harge on the gate must be mirrored by negative charge in the substrate. ensuring that these diodes are not forwardbiased. Recall from Fig. Our analysis will indeed con rm these conjectures while reveal ing other subtle effects in the device. the only current of interest is that owing between the source and the drain. Fortunately. We say the MOSFET is on.4 Outline of conce ts to be studied. with the (low frequency) gate current being zer o. we do not show this connect ion in the diagrams.1 Qualitative Analysis Our study of the sim le structures shown in Figs. 6. Since the MOSFET contains three terminals.2 suggests that the MOSFET may conduct current between the source and dra in if a channel of electrons is created by making the gate voltage suf ciently os itive. W e must study the de endence of this current u on the gate voltage (e.g.. 6. Let us rst consider the arrangement s hown in Fig. thereb y ex osing negative ions and creating a de letion region [Fig. no current can ow from the source to the drain.5(a).1 and 6. 6.2. 6. if VG b ecomes suf ciently ositive.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the ositive charge on the gate re els the holes in the substrate. 6. another henomenon recedes the formation of the channel. 6.1(b) that. where the source and drain are grounded and the gate voltag e is varied. as VG rises. This circuit does not a ear articularly useful but it gives us a great deal of insight. in reality . While we stated in Section 6. Thus. 2007 at 13:42 285 (1) Sec. forming a conductive channel [Fig. For sim licity. We say the MOSFET is off. C an the source substrate and drain substrate junctions carry current in this mode ? To avoid this effect. more negative ions are ex osed and the de letion region under the oxide bec omes dee er. These conce ts become clearer below. What ha ens as VG increases? To mirror the charge on the g ate.cls v.1 that electrons are attracted to the interface.2 O eration of MOSFET 285 Qualitative Analysis Formation of Channel MOSFET as Resistor Channel Pinch−off I/V Characteristics I/V Characteristics Channel Charge Density Dain Current Triode and Saturation Re gions Analog Pro erties Transconductance Channel−Length Modulation Other Pro erties Body Effect Subthreshold Conduction Velocity Saturation Figure 6. for a constant gate vol tage). 2006] June 30.5(c)]. we ex ect that the magnitude of the current can be controlled b y the gate voltage.4 Note th at the device still acts as a ca acitor— ositive charge on the gate is mirrored by negative charge in the substrate—but no channel of mobile charge is created yet. The ¡ ¡ ¡ ¡ ¡ . for a c onstant drain voltage) and u on the drain voltage (e. Does this mean the transistor never turns on?! Fortunately.. As VG increases from zero.3 we may face many combinations of terminal vol tages and currents.5(b)].g. 6. free electrons are attracted to the oxide silicon int erface.

¡ . Furthermore. the gate r emains insulated from other terminals and sim ly o erates as a late of a ca aci tor. but we ignore that for now. and need not be su lied by the substrate.” VTH . whereas the de letion region in a n junction consists of two areas of negative and ositive ions on the two sides of the junction. MOSFET as a Variable Resistor The conductive channel between S and D can be viewed as a resistor. 4 Note th at this de letion region contains only one immobile charge olarity. It is interesting to recognize that the gate terminal of the MOSFET draws no (low frequency) current.gate otential at which the channel begins to a ear is called the “threshold vol tage. since the density of electrons in the channe l must increase as VG 3 The substrate acts as a fourth terminal. and falls in the range of 300 mV to 500 mV. Note that the electrons a re readily rovided by the n+ source and drain regions. Resting on to of the oxide.

Devise a variable gain circuit that lowers the signal level as the cell hone a roaches the base station.1 In the vicinity of a wireless base station. the signal received by a cell hone m ay become very strong. (c) formation of channel. Solution A MOSFET can form a voltage controlled attenuator along with a resistor as shown in Fig.5 (a) MOSFET with gate voltage. ¡ ¡ ¡ ¡ VG n+ (a) −substrate . becomes more ositive (why?). 6. 6. Exam le 6.cls v. Conce tually illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 Use of MOSFET to adjust signal levels.6 MOSFET viewed as a voltage de endent resistor. 2006] June 30. G S D Figure 6. Since V cont v in RM R1 v out Figure 6. the value of this resistor changes with the gate v oltage. 6 Physics of MOS Transistors VG n+ VG n+ −substrate De letion Region (b) VG n+ n+ −substrate n+ Free Electrons Negative Ions (c) Figure 6. 2007 at 13:42 286 (1) 286 Cha . such a voltage de endent resistor roves extremely useful in analog and digital circuits. ossibly “saturating” the circuits and rohibiting ro er o e ration.7. (b) formation of de letion region.6.

In fact. no ch annel exists. The slo e of the characteristic is equal to 1=Ron . and ID = 0 regardless of the value of VD . 6. where Ron denotes the “on resistance” of the transistor.8(b)]. 2007 at 13:42 287 (1) Sec. On t he other hand. vin RM + R1 (6. If VG VTH . 2006] June 30. 6. the source drain a th may act as a sim le resistor. yielding the ID VD characteristic shown in Fig .1) the out ut signal becomes smaller as Vcont falls because the density of electron s in the channel decreases and RM rises.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. MOSFETs are commonly utilized as voltag e de endent resistors in “variable gain am li ers. if VG VTH . 6. 6. We now raise the drain voltage as shown in Fig.5 ID VG VD VD VTH (a) (b) ID ID VD VG ID VG ID ID VD VG R on −1 ID VG3 VG2 VG1 VG n+ −substrate n+ ¡ ¡ ¡ ¡ ¡ . the device is off.8(a) and examine the drain current (= source current).5(c).2 O eration of MOSFET 287 vout = R1 .cls v.8(c). 6. then ID 0 [Fig. no current ows between S and D because the two terminals are at the same otential.” Exercise What ha ens to RM if the channel length is doubled? In the arrangement of Fig.

6. Each view ro vides valuable insight into the o eration of the transistor. ¡ ¡ ¡ ¡ .8(b). (d) ID VD characteristics for various g ate voltages . 5 The term “on resistance” always refers to that between the source and drain as no resistance exists between the gate and other terminals. VD is varied while VG remains constant. Our brief treatment of the MOS I/V characteristics thus far oints to two differ ent views of the o eration: in Fig. (c) ID VD characteristic. 6.8 (a) MOSFET with gate and drain voltages. (b) ID VG cha racteristic.VD VD (c) (d) Figure 6. VG is varied while VD remains consta nt whereas in Fig.8(c).

6.8(d). The following exam le reinforces the conce ts studied thus far. 6. 6. As the channel length increases. How about the trans ort mechanism in a M OSFET? Since the voltage source tied to the drain creates an electric eld along t he channel. res ectively. It is therefore desirable to minimize the channel length so as to achieve large drain currents—an im ortant trend in the MOS technology de velo ment.8(b) and (c). Recall from Cha ter 2 that charge ow in semic onductors occurs by diffusion or drift. 6. the current results from the drift of charge. Exam le 6. De icted in Fig.8(b) change if VG increases? The higher de nsity of electrons in the channel lowers the on resistance.cls v. The ID VG and ID VD characteristics shown in Figs. 6. lay a central role in our understanding of MOS devices.9 (a) ID VG characteristics for different channel lengths.6 Thus. the drain current begins with lesser values as the channel le ngth increases [Fig. yielding a greater s lo e.9(a)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) ID ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ VD . the resulting characteristics strengthen the noti on of voltage de endent resistance. 2006] June 30.2 Sketch the ID VG and ID VD characteristics for (a) different chann el lengths. Similarly. 2007 at 13:42 288 (1) 288 Cha .9(b)]. ID ID Solution VTH (a) VG (b) VD ID ID VTH (c) VG (d) VD ¡ Figure 6. 6 Physics of MOS Transistors How does the characteristic of Fig. for VG VTH . ID exhibits a smaller slo e as a functi on of VD [Fig. so does the on resistance. and (b) different oxide thicknesses.

tox .characteristics for different channel lengths.9(d)]. 6. the ca acitance between the gate and the silicon substrate decreases. For this reason. roducing less drain current for a given gate v oltage [Fig. the device suff ers from a higher on resistance. (d) ID VD characteristics for different oxide thickn esses. Consequently. from Q = CV . Thus .9(c)] or drain voltage [Fig. affect the I V characteristics? As tox incre ases. How does the oxide thickness. If the mobility f alls at high 6 Recall that the resistance of a conductor is ro ortional to the length. Exercise The current conduction in the channel is in the form of drift. ¡ ¡ ¡ ¡ . 6. (c) ID VG characteristics for di fferent oxide thicknesses. we note that a given voltage results in less charge on the gate and hence a lower electron density in the channel. the semico nductor industry has continued to reduce the gate oxide thickness.

cls v.. We may then surmise that W must be max imized. (b) ID characteristics for different values of W . We the refore observe that “lateral” dimensions such as L and W can be chosen by circuit de signers whereas “vertical” dimensions such as tox cannot. but we must also note that the total gate ca acitance increases with W . 6.10 (a) Dimensions of a MOSFET (W and L are under circuit design er’s control. 2006] June 30. 6. 2007 at 13:42 289 (1) Sec.e. rodu cing a high drain current [Fig.2 O eration of MOSFET 289 While both the length and the oxide thickness affect the erformance of MOSFETs.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6. on the other hand. it can be s eci ed i n the “layout” of the transistor. a wider device can be viewed as two narrower transistors in arallel.10(b). (c) equivalence to devices in arallel.). t ox W n+ L (a) n+ ID W ID W S G D VTH VG VD (b) (c) Figure 6. so does the width of the channel. i. thus lowering the resistance between the source and th e drain7 and yielding the trends de icted in Fig. 6. From another ers ect ive. How does the gate width im act the I V characteristics? As W increases. Thus. the width of each device in t tem eratures.10(a)]. The latter. the dimension er endicular to the length [Fig. Another MOS arameter controlled by circuit designers is the width of the transistor. is de ned during fabr ication and remains constant for all transistors in a given generation of the te chnology. only the former is under the circuit designer’s control.10(c)]. ossibly limiting the s eed of the circuit. what can we say about the on resistance as the tem erature goes u ? ¡ ¡ .

the otential difference between 7 Recall that the resistance of a conductor is inversely ro ortional to the cro ss section area. and since the otential at the oxide silicon interface rises from the source to the drain. Illustrated in Fig. the transistor o erates as a current source if the drain voltage is suf ciently ositive.11(a). this effect arises from the gradual voltage dro along the channel resistance. In reality. 6. To understand th is effect. Channel Pinch Off Our qualitative study of the MOSFET thus far im lies that the device acts as a voltage de endent resistor if the gate voltage exceeds VTH . (2) if t he drain voltage remains higher than the source voltage.he circuit must be chosen carefully. the otential differ ence between the gate and the oxide silicon interface must exceed VTH . Since the gate voltage is con stant (because the gate is conductive but carries no current in any direction). then the voltage at eac h oint along the channel with res ect to ground increases as we go from the sou rce towards the drain. however. which itself is equal to the roduct of the width and thickness of the conductor. ¡ ¡ ¡ ¡ . we make two observations: (1) to form a channel.

the voltage difference between th e gate and the substrate falls to VTH at some oint L1 L [Fig. then the channel ceases to exist near the drain. 6. and the MOSFET acts as a constant current source—similar to a bi olar transistor in the forward active r egion. VG VD n+ ID Potential = V G Difference < VG n+ x = VG − VD Gate−Substrate Potential Difference V (x ) VG VD − VG L L x x (a) (b) Figure 6. if the drain voltage is high enough t o roduce [Fig. VTH at x = L.12(c). The dev ice therefore contains no channel between L1 and L. we conclude that. What ha ens if VD rises even higher than VG .2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Nonetheless. The density of electrons in the channel follows the same trend. 6.12(b)]. Note that the source substrate and drain substrate junctions carry no cur rent. we can now formulate the behavior of MOSFETs in terms of their terminal volt ¡ ¡ ¡ ¡ ¡ ¡ . they ex erience the hi gh electric eld in the de letion region surrounding the drain junction and are ra idly swe t to the drain terminal.cls v. the device still conducts: as illustrated in Fig. 2006] June 30.12(a)]. once the electrons reach the end of the channel. 6.11(b )]. as shown in the next section. VTH ? Since V x now goes from 0 at x = 0 to VD VG . VG . 6. 2007 at 13:42 290 (1) 290 Cha . 6 Physics of MOS Transistors the gate and the oxide silicon interface decreases along the x axis [Fig. Does this mean the transisto r cannot conduct current? No. (b) gate substrate voltage difference along the channel. th e drain voltage no longer affects the current signi cantly.11 (a) Channel otential variation. We say the gate s ubstrate otential difference is not suf cient at x = L to attract electrons and t he channel is “ inched off” From these observations.2 Derivation of I/V Characteristics With the foregoing qualitative stu dy. VD VTH . 6. falling to a minimum at x = L.

we have V = VGS . free electrons) er unit length.e. (Hereafter. Moreover. we note that if C is the gate ca acitance er unit length and V th e voltage difference between the gate and the channel. VTH because no mobile charge exists for V GS VTH . we denote both the gate and drain voltages with res ect to the source. VTH : (6.” From Q = CV . 6. Denoting the gate ca acitance er unit area by Cox (ex ressed in F/ m2 or fF/m2 ).13(a)].2) .ages..) It follows that Q = WCox VGS . we write C = WCox to account for the width of the transistor [Fig. also called the “charge density. Channel Charge Density Our derivations require an ex ression for the chann el charge (i. then Q is the desired cha rge density.

where the channel otential remains close to zero. and the charge densi ty falls as we go from the source to the drain. As sh Figure 6. Eq. .2 O eration of MOSFET VG n+ Electrons 291 ID > V TH n+ VD VG VD VG n+ n+ ID VD V TH VG VD (a) VG n+ n+ ID VD E n+ 0 (b) L1 L x (c) Figure 6.cls v. Thus. (c) detail ed o eration near the drain. 2006] June 30.12 (a) Pinchoff. Now recall from Fig.2) is valid only ne ar the source terminal. 2007 at 13:42 291 (1) Sec. 6.11(a) that the channel voltage varies along the length of the transistor.13 Illustration of ca acitance er unit length. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. W n+ n+ Note that Q is ex ressed in coulomb/meter. (b) variation of length with drain voltage. (6.

6. VTH .3) Drain Current What is the relationshi between the mobile charge density and the current? Consider a bar of semiconductor having a uniform charge density ( er u nit length) equal to Q and carrying a current I (Fig. . 6.own in Fig. Note from Cha ter 2 that (1) I is given by the total charge that asses through the cross section o f the bar in one second.15). V x .14. noting that V x goes from zero to VD if the channel is not inched off. then the charge enclosed in v meters along the bar asses through the cross Qx = WCox VGS . we denote the channel otential at x by V x and write (6. and (2) if the carriers move with a velocity of v m/s.

dx (6.5) (6.4) v = . (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Combining (6 . w e have v meters W t = t1 t = t1 + 1 s L h x1 V1 x x1 V1 x I = Q v. we obtain Figure 6. 2007 at 13:42 292 (1) 292 Cha . VTH and dV=dx is inde endent of x. = +n dV . V x .14 Device illustration for calculation of drain current.cls v. (6.15 Relationshi between charge velocity and current.6). 2006] June 30. VTH n dV x : dx where dV=dx denotes the derivative of the voltage at a given . and (6. our immediate need is to n d an ex ression for ID in terms of the terminal voltages. V x and dV= dx must vary such that the roduct of VGS . To this end. oint. 0 x section in one second.6) Interestingly. we write ID = WCox VGS . 6 Physics of MOS Transistors VG n+ n+ ID VD V (x ) L dx Figure 6. V x .3). Since the charge enclosed in v meters is equal to Q v . since ID must remain constant along the channel (why?).4).n E. As ex lained in Cha ter 2. While it is ossible to solve the above differential equation to obtain V x in terms of ID (and the reader is encouraged to do that).

V x . 2 ID = 1 n Cox W 2VGS .(6.8) That is. VTH dV: (6. VTH VDS .7) Z x=L x=0 ID dx = Z V x=VDS V x=0 n Cox W VGS . VDS : 2 L (6.9) .

reaching a maximum of ID 1 2 n C ox W (VGS − V TH ( L 2 VGS − V TH VDS at VDS = VGS . VTH 2 .17 MOS characteristics for different gate source voltages. As VGS increases. Cox . 6. the characteristics exhibit maxima that follow a ara bolic sha e themselves because ID.. for a constant VGS .3 Solution VGS3 I D.cls v.max and VGS . Illustrated in Fig. VTH 2 2 L (6. ID varies arabolically with VDS (Fig. For exam le. VTH . if both W and L are doubled.17.max4 Parabola ID. Secon d.max VGS .g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8) to em hasize the choice of W and L.max = 1 n Cox W VGS .10(c)].max3 VGS2 I D. First. 6. ID I D. and a larger W=L (called the device “as ect r atio”) is equivalent to lacing more transistors in arallel [Fig.2 O eration of MOSFET 293 We now examine this im ortant equation from different ers ectives to gain more insight. 2007 at 13:42 293 (1) Sec. VTH . 6.max2 VGS1 − V TH VGS1 VGS2 − V TH VGS3 − V TH VDS Figure 6.10) Exam le 6.16). Plot the ID VDS characterist ics for different values of VGS . the individual values of W and L also become critical in most cases. While only the r atio a ears in many MOS equations. 5 m=0:18 m (rather than 27. 6. a higher gate oxide ca acitance leads to a larger electron density in the chan nel for a given gate source voltage. the ratio rem ains unchanged but the gate ca acitance increases. ¡ ¡ . the linear de endence of ID u on n . so do ID. 2006] June 30. It is common to write W=L as the ratio of two values e. and W=L is to be ex ec ted: a higher mobility yields a greater current for a given drain source voltage .16 Parabolic ID VDS characteristic. ¡ ¡ ¡ Figure 6.

Exercise What ha ens to the above lots if tox is halved? .

19 Role of antenna switch in a cordless hone. V (6. the arabolas in Fig. In fact. VTH VDS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . Thus.19). Exam le 6. 2007 at 13:42 294 (1) 294 Cha . e. 6.g.12) Figure 6. (6. if VDS 2VGS .1.17 can be a roximated by straight lines having different slo es (Fig. 6.e. the antenna is alternately connected to the rec eiver and the transmitter in regular intervals.cls v. the device can o erate as an electronic switch.. (6. Eq . 6 Physics of MOS Transistors The nonlinear relationshi between ID and VDS reveals that the transistor cannot generally be modeled as a sim le linear resistor. the equivalent o n resistance is given by VDS =ID : ID n Cox W VGS . 6.4 A cordless tele hone incor orates a single antenna for rece tion and transmissio n. at small VDS (near the origin). every 20 ms (Fig.9) reduces to: exhibiting a linear ID VDS behavior for a given VGS . In articular.18).8 Receiver Receiver Transmitter Transmitter : n Cox L GS TH Figure 6. A n electronic antenna switch is therefore necessary here.11) Ron = From another ers ective. ID VGS2 VGS1 VDS VDS VGS3 ID VGS3 VGS2 VGS1 W V . for VGS = VTH . Ex lain how the system must be con gured. ¡ ¡ ¡ ¡ . VTH .2.12) suggests that the on resistance can be con trolled by the gate source voltage. As redicted in Section 6. Solution The system is designed such that the hone receives for half of the time and tra nsmits for the other half. L 1 (6. Ron = 1. However.18 Detailed characteristics for small VDS . 2006] June 30. i.

8 Some cell hones o erate in the same manner. .

12). 6. Solution As de icted in Fig.4.13) Ron 5:6 : Setting VGS to the maximum value. If VDD = 1:8 V. The circuit designer must therefore maximize W=L and VGS . (6. we obtain from Eq.g. 2007 at 13:42 295 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.15) ¡ ¡ ¡ .5 In the cordless hone of Exam le 6. 2006] June 30. Assume the antenna can be modeled as a 50 resistor. by no more than 10.cls v. Vout 0:9 Vin and hence (6. (6.20.. each of which receives and transmits signals.20 Signal degradation due to on resistance of antenna switch. The following exam le illustrates this oint. e. n Cox = 100 A=V2 . the switch connecting the transmitter to t he antenna must negligibly attenuate the signal. determine the minimum required as ec t ratio of the switch. and VTH = 0:4 V.14) W 1276: L (6. Exam le 6. 6. it is desirable to achieve a low on resistance for MOS swi tches. VDD . How many switches are needed? In most a lications.2 O eration of MOSFET 295 Exercise Some systems em loy two antennas. we wish to ensure R on V out 50 Ω R on R ant Transmitter V in Figure 6.

th ¡ . (Since wide transistors introduce substantial ca acitance in the signal is choice of W=L may still attenuate high frequency signals.) ath.

6.7) and (6. from x = 0 to x = L1 in Fig.2 V? Triode and Saturation Regions Equation (6. Thus. VTH . We also use the term “d ee triode region” for VDS transistor o erates as a resistor. an d be modi ed to ID 1 2 n C ox W (VGS − V TH ( L 2 Triode Region Saturation Region VGS − V TH VDS Figure 6. becomes constant for VDS VGS . (6. im lying that the current begins to fall for VDS VGS . recall that Eqs.8) must encom ass only the channel. the drai n current reaches “saturation.12 that the channel ex eriences inch off if VDS = VGS .12(b).VTH V x=0 ¡ ¡ .cls v. 2006] June 30.. where the arabola).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. It follows that the integration in (6. 6.21 Overall MOS characteristic.9) ex resses the drain current in term s of the device terminal voltages. VTH . VTH (the rising section of the 2VGS . i. 2007 at 13:42 296 (1) 296 Cha . 6 Physics of MOS Transistors Exercise What W=L is necessary if VDD dro s to 1. VTH . 6. 21). further increase in VDS sim ly shifts the inch off oint slightly toward the drain. We say the device o erates in the “triode region”9 if VDS VGS . Z x=L x=0 1 ID dx = Z V x=VGS . In reality.” that is.8) are valid only where channel charge exists. VTH (Fig. To understand why. recall from Fig. Also.e.

the integral on the right hand side is evaluated u to VGS . For the sake of brevity. w ith the triode and saturation regions in MOSFETs a earing similar to saturation and forward active regions in bi olar transistors. VTH 2 .10) if we assume L1 L. V x . 6. Consequently.16) Note that the u er limits corres ond to the channel inch off oint.21 resembles that of bi olar devices. It is unfortun ate that the term “saturation” refers to com letely different regions in MOS and bi olar I V characteristics. we hereafter denote L1 with L.” the quantity VGS .max in (6. Called the “overdrive voltage. W ID = 1 n Cox L VGS . 9 Also called the “linear region. VTH rather tha n VDS . The I V characteristic of Fig.n Cox W VGS . VTH lays a key role in MOS circ uits. res ectively. In articu lar. VTH dV: (6.17) a result inde endent of VDS and identical to ID. 2 1 (6. MOSFETs are sometimes called “square law” devices to em hasize the relationshi between ID and the overdrive.” ¡ ¡ ¡ ¡ .

6. Furthermore. Calculate the bias current of M1 in Fig. a MOSFET can o erate as a current source having a value given by (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VTH ¡ ¡ ¡ ¡ .2 O eration of MOSFET 297 > VTH ID 1 2 n C ox W (VGS − V TH ( L 2 Saturated Triode Region Saturation Region M1 VGS − V TH VDS (a) (b) Figure 6.17). VTH suggests that the device can act as a voltage controlled cur rent source. 6. 2006] June 30.22 to determine the region of o eration. 1V Figure 6.18 5 kΩ Exam le 6.6 = 0:4 V. Assume n Cox = 100 A=V 2 and VTH If the gate voltage increases by 10 mV. It is unclear a riori in which region M1 o erates. 6.23 Sim le MOS circuit. Let us assume M1 is saturate We em loy the conce tual illustration in Fig. Note that the gate drain otential difference suits this ur ose and we need not com ute the gatesource and gate drain voltages se arately. the square law de endence o f ID u on VGS .23.8 V RD ID X M1 W = 2 L 0.cls v. what is the change in the drai n voltage? VDD = 1. Exhibiting a “ at” current in the saturation region.22 Illustration of triode and saturation regions based on the g ate and drain voltages. 2007 at 13:42 297 (1) Sec.

VTH 2 L = 200 A: We must check our assum tion by calculating the drain otential: (6.19) VX = VDD .21) . RD ID = 0:8 V: (6. Solution 1 ID = 2 n Cox W VGS .20) (6.18) (6. Since VGS = 1 V.d and roceed.

23 that lac es M1 at the edge of saturation and calculate the drain voltage change for a 1 m V change at the gate. ¡ ¡ ¡ . (4) The gate of MO SFETs draws no bias current. 6. ID = VDDR VDS D = 240 A: Since ID scales linearly with W=L. most transistors have the same dimensions a nd hence the same IS . That is . but by less than VTH . (2) Bi olar devices exhibit an ex onent ial IC VBE characteristic while MOSFETs dis lay a squarelaw de endence. the as ect ratio of each device may be chosen differently to satisfy the design requirements. With VGS = +1 V.7 Solution = 0:6 V for M1 to enter the triode (6.22 therefore indicates that M1 indeed o erates in saturation .23) Fortunately.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6 Physics of MOS Transistors The drain voltage is lower than the gate voltage. (3) In bi olar circuits. the former rovide a greater transconductance than the latter (for a given bia s current). 2007 at 13:42 298 (1) 298 Cha . VTH region. That is. The 34 mV change in VX reveals that the circ uit can am lify the in ut. (1) A bi olar transistor with VBE = VCE resides at the edge of the act ive region whereas a MOSFET a roaches the edge of saturation if its drain volta ge falls below its gate voltage by VTH . whereas in MOS circuits. The ill ustration in Fig. 2006] June 30.25) . 6. Assume VTH = 0:4 V. M1 is still saturated. If the gate voltage increases to 1.22) VX = 0:766 V: (6.cls v. then ID = 206:7 A. the drain voltage mus t fall to VGS .24) (6. Exercise What choice of RD laces the transistor at the edge of the triode region? It is instructive to identify several oints of contrast between bi olar and MOS devices. Exam le 6.10 Determine the value of W=L in Fig.01 V. lowering VX to (6.

28) 10 New generations of MOSFETs suffer from gate “leakage” current. (6. .26) (6. but we neglect thi s effect here.27) (6. W j = 240 A 2 L max 200 A 0:18 4 = 02::18 : ID = 248:04 A.If VGS increases by 1 mV.

. VTH 2 .31) VGS . RD ID : Substituting for ID from (6. 6.17) (6. L and hence VGS . VGS .1 + 1 + 2RD VDD n Cox W L RD n Cox W L q : (6.02 in this case. VTH gives Solution = VDS = VDD . VDD = 1. 6. VTH = Thus.8 Figure 6. At the edge of saturation.24 if M1 must remain satu rated.8 V RD ID V GS X M1 W = 2 L 0. Calculate the maximum allowable gate voltage in Fig. R2D n Cox W VGS . 2006] June 30.24 Sim le MOS circuit. 2007 at 13:42 299 (1) Sec. (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VTH = VDD .2 O eration of MOSFET 299 changing VX by VX = ID RD = 4:02 mV: The voltage gain is thus equal to 4.cls v.32) VGS = .30) Exercise Re eat the above exam le if RD is doubled.18 5 kΩ Exam le 6.29) (6.

1 + 1 + 2RD VDD n Cox W L RD n Cox W L q + VTH : (6..33) Exercise Calculate the value of VGS if mun Cox = 100 A=V2 and VTH = 0:4 .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Unlike the E arly effect in bi olar devices (Cha ter 4). channe l length modulation results in a nite out ut im edance given by the inverse of th e ID VDS slo e in Fig. 6 Physics of MOS Transistors 6. L where is called the “channel length modulation coef cient. the base width o f bi olar devices cannot be adjusted by the circuit designer. (6. we observe d that the oint at which the channel vanishes in fact moves toward the source a s the drain voltage increases. 2007 at 13:42 300 (1) 300 Cha .25. 6. the amount of channel length modulat ion is under the circuit designer’s control.12(b) v aries with VDS to some extent. 2006] June 30.2.17). the value of L1 in Fig. In other words. yielding a constan t Early voltage for all transistors in a given technology. Called “channel length modulation” and illustrated in Fig. 6. this henomenon yields a larger drain current as VDS increases becau se ID 1=L1 in Eq.11 (By contrast. 6.” While only an a roximati on.25. VTH 2 1 + VDS . we assume hand side of (6. Similar to the Early effect in bi olar devices. VDS To account for channel length modulation.25 Variation of ID in saturation region. but multi ly the right (6. the relative change in L (and hence in ID ) fo r a given change in VDS is smaller (Fig.17) by a cor rective term: L is constant.26). ID 1 2 n C ox W (VGS − V TH ( L 2 VGS − V TH Figure 6.3 Channel Length Modulation In our study of the inch off effect.cls v. 6.) L1 ID ID L2 ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ .34) 1 ID = 2 n Cox W VGS . This is because is inversely ro ort ional to L: for a longer channel. this linear de endence of ID u on VDS still rovides a great deal of insight into the circuit design im lications of channel length modulation.

9 11 Since different MOSFETs in a circuit may be sized for different ’s.26 Channel length modulation. Exam le 6. A MOSFET carries a drain current of 1 mA with VDS = 0:5 V in saturation. Determi ne the change in ID if VDS rises to 1 V and = 0:1 V.VDS VDS Figure 6.1 . we do not d e ne a quantity similar to the Early voltage here. What is the device out ut im edance? ¡ .

10 Solution 1=L.41) (6. (6.40) Exercise Does W affect the above results? The above exam le reveals that channel length modulation limits the out ut im ed ance of MOS current sources. ID (6.cls v. V 2 1 + V ID2 = 2 n ox L GS TH DS 2 ¡ . yielding an out ut im edance of (6. VDS1 = 0:5 V. In Eqs.9 if both W and L are doubled. The same effect was observed for bi olar current so urces in Cha ters 4 and 5.2 O eration of MOSFET 301 Solution We write ID1 = 1 n Cox W VGS .42) 2 L 1 C W V . 2007 at 13:42 301 (1) Sec.1 .35) and (6. Thus. VTH 2 1 + VDS1 and hence (6.39) (6.05 V. and = 0:1 V.35) (6. VDS2 = 1 V.36) ID2 = ID1 1 + VDS2 : 1 + V DS 1 With ID1 (6. W=L remains unchanged but dro s to 0. Assuming Exam le 6. 6.1 . 1 + V ID2 = ID1 1 + VDS2 DS 1 = 1:024 mA: That is.36).37) = 1 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. calculate ID and rO in Exam le 6. ID2 = 1:048 mA: The change in ID is therefore equal to 48 A. 2006] June 30.38) rO = VIDS D = 10:42 k : (6.

= 24 A and rO = 20:84 k : (6.43) .

substitut ing for VGS . (6.46) is ¡ . (6.DV . and (2) gm is ro ortion al to a given W=L.cls v. VTH . 2007 at 13:42 302 (1) 302 Cha . VTH from (6.45) by (6. (1) gm is ro ortional to W=L for a given ID .44) This quantity serves as a measure of the “strength” of the device: a higher value co rres onds to a greater change in the drain current for a given change in VGS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2.47) GS TH revealing that (1) gm is linearly ro ortional to I D for a given VGS . we have concluding that (1) gm is linearly ro ortional to W=L for a given VGS .17) gives gm = 2n Cox W ID : L r (6. Among these three ex ressions for gm .45) That is. L (6. 2006] June 30. (6. 6 Physics of MOS Transistors Exercise What out ut im edance is achieved if W and L are quadru led and ID is halved. we obtain gm = n Cox W VGS . Also. VTH for a given ID .1. a nd (2) gm is linearly ro ortional to VGS . a MOS transis tor can be characterized by its transconductance: @I gm = @V D : GS (6. Summarized in Table 6.17) for the saturation region.12 . VTH . VTH . dividing (6. and (2) gm is inversely ro ortional to VGS . VTH for a given W=L. U sing Eq.46) I D for I gm = V 2.4 MOS Transconductance As a voltage controlled current source. these de endencies rove critical in understanding erformance trends of MOS devices and have no counter art in bi olar transistors.17). Moreover. 6.

it is as if two transisto rs carrying equal currents are laced in arallel. . if VGS re mains constant and the width of the device is doubled.17) suggests that the overdrive remains constant. (6.more frequently used because ID may be redetermined by ower dissi ation requi rements. Indeed.11 . VTH change if both W=L and Equation (6.46) indicates that gm is also doubled. thereby doubling the transcon ductance. The reader can show that this trend a lies to any ty e of transistor. These results can be understood intuitivel y if we view the doubling of W=L and ID as shown in Fig. Moreover. then both IC and gm increase linearly. Solution 12 There is some resemblance between the second column and the behavior of gm = IC =VT . If the bi olar transistor width is increased while VBE remains constant . For a MOSFET o erating in saturation.27. 6. Eq. how do gm and VGS ID are doubled? Exam le 6.

VTH and no de endence on L. 6. VTH change if only W and ID are doubled? 6.1 Various de endencies of gm . Denoting the saturate d velocity by vsat .48) (6. Figure 6. V GS V GS V DS V DS Exercise How do gm and VGS .. As a result. modern MOS devices ex erience velocity satu ration even with drain source voltages as low as 1 V.2.g. VTH : Interestingly. ca rrier mobility degrades.27 Equivalence of a wide MOSFET to two in ¡ ¡ arallel.49) is not accurate.2 under velocity saturation conditions. eventually leading to a constant velocity.2 O eration of MOSFET 303 W Constant L VGS − V TH Variable g g m m W Variable L VGS − V TH Constant g g m m W Variable L VGS − V TH Constant g g m m ID VGS − V TH ID W L W L 1 VGS − V TH Table 6. the I/V chara cteristics no longer follow the square law behavior.3 that at high electric elds.13 saturation and (6. Let us examine the derivati ons in Section 6. we have ID = vsat Q = vsat WCox VGS . (6. . ID now exhibits a linear de endence on VGS This section can be ski ed in a rst reading.49) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 m). Owing to the ir very short channels (e.1. 2007 at 13:42 303 (1) Sec.5 Velocity Saturation Recall from Section 2. 0.cls v. 2006] June 30.2.

13 Of course. then the device ex eriences less velocity . while VDS remains constant. if L is increased substantially.

6.28 illustrates this case. An interesting henomenon occurs as the source substrate otential difference de arts from zero: the threshold voltage of the device changes. In articular.50) (6. 6 Physics of MOS Transistors We also recognize that @I gm = @V D GS = vsat WCox. assume VS = 0:5 V. as the source becomes more ositive with res ect to the substrate.4 V. Figure 6 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a quantity inde endent of L and ID .” this henomenon is formulated as VTH = VTH 0 + j2 F + VSB j .14 The dash ed line added to the transistor symbol indicates the substrate terminal. and and F are technology de endent arameters having ty ical values of 0. this con dition need not hold in all circuits.28. C alled “body effect.51) Body Effect In our study of MOSFETs. 2007 at 13:42 304 (1) 304 Cha .6 Other Second Order Effects (6.cls v. Substrate Contact VG VD n+ VG VS VD Figure 6. VG = VD = 1 ¡ ¡ VS + −substrate n+ ¡ ¡ ¡ .4 V and 0. VTH increases. if the source terminal rises to a ositive voltage while the substrate is at zero. The source terminal is tied to a otential VS with re s ect to ground while the substrate is grounded through a + contact. then the source substrate junction remains reverse biased and the device still o erates ro erly. We deno te the voltage difference between the source and the substrate (the bulk) by VSB . 2006] June 30. (6. we have assumed that both the source and th e substrate (also called the “bulk” or the “body”) are tied to ground. 6. For exam le.28 Body effect. res ectively. However.2.52) where VTH 0 denotes the threshold voltage with VSB = 0 (as studied earlier). In the circuit of Fig. j2 F j.

Sin ce the source body voltage. Determine the drain current if = 0. n Cox W=L = 50. ¡ . (6.53) Solution = 0:5 V. and VTH 0 = 0:6 V.52) and the ty ical values for VTH = 0:698 V: 14 The + island is necessary to achieve an “ohmic” contact with low resistance. and F yield (6. VSB Exam le 6.12 = 100 A=V2 . Eq.:4 V.

29(b).30(a) versus V1 as V1 varies from zer o to VDD . VTH 2 1 + VDS Saturation Region 2 L (6. if VDS 2VGS . VTH . but it can still incor orate a voltage control led current source as de icted in Fig.55) Exercise Sktech the drain current as a function of VS as VS goes from zero to 1 V. formation of the channel is a gradual effect. Ca lled “subthreshold conduction. the t ransistor can be viewed as a voltage controlled resistor [Fig. we write ¡ ¡ ¡ ¡ . with VG = VD .3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.57) In the saturation region.cls v. lending itself to the model shown in Fig. Note that ID does de en d on VDS and is therefore not an ideal current source. 6. We neglect body effect in this book. VTH VDS . the transistor acts as a voltage controlled current so urce. 2006] June 30.56) (6. 6. 6.29(a).29(c)]. Subthreshold Conduc tion The derivation of the MOS I/V characteristic has assumed that the transisto r abru tly turns on as VGS reaches VTH . Body effect manifests itself in some analog and digital circuits and is studied in more advanced texts.1 Large Signal Mod el For arbitrary voltage and current levels. VS . Exam le 6. 6. VDS Triode Region 2 L ID = 1 n Cox W VGS . and the device conducts a small current even for VGS VTH .” this effect has become a critical issue in modern MO S devices and is studied in more advanced texts. In all three cases. we must resort to Eqs.3 MOS Device Models With our study of MOS I/V characteristics in the revious section. the gate remains an o en circuit to re resent the zero gate current . Finally. (6. the m odel must re ect the triode region.13 Solution Noting that the device o erates in saturation (why?). the device o erates in saturation (why?) and hence ID = 1 n Cox W VG . VTH . 2007 at 13:42 305 (1) Sec. Sketch the drain current of M1 in Fig.3 MOS Device Models 305 Also. 6. we now develo models that can be used in circuit analysis and design. Assume = 0.9) and (6 . For VDS VGS . 6. VTH 2 2 L = 102 A: (6.54) (6. In reality.34) to ex ress the device behavior: 2 ID = 1 n Cox W 2VGS .

58) . VTH 2 L (6.1 ID = 2 n Cox W VGS .

= 1 n Cox W VDD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2007 at 13:42 306 (1) 306 VGS < V TH VDS < VGS − V TH G D 1 2 Cha . VDD M1 V1 VDD − V TH V1 (a) (b) ID Figure 6. V1 . (b) variation of ID with V1 . As V1 rises. turning the tr ¤ ¤ ¤¤ . VTH 2 : 2 L (6. VTH . (c) deep tr iode region.29 MOS mode s for (a) saturation region. (b) triode region. VGS drops to VTH . 2006] June 30.59) At V1 = 0.30 (a) Simp e MOS circuit. 6 Physics of MOS Transistors ID S n C ox W (VGS − V TH ( (1+ λVDS ) L 2 (a) VGS < V TH VDS > VGS − V TH G D G 1 2 2 n C ox W [ 2 (VGS − V TH ( VDS + VDS ] L VGS < V TH VDS >> 2 (VGS − V TH ( D 1 W (V n C ox GS − V TH ( L ID S R on = S (b) (c) Figure 6. If V1 reaches VDD . VGS = VDD and the device carries maximum current. VGS fa s and so does ID .

6. the non inear.3.2 Sma Signa Mode If the bias currents and vo tages of a MOSFET are on y s ight y disturbed by signa s. Exercise Repeat the above examp e if the gate of V. Note that.30(b). The deve opment ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ M1 is tied to a vo tage equa to 1. 6. VTH varies with V1 if the substrate is tied to grou nd. arge signa mode s can be reduced to inear.5 V and VDD = 2 ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¡¤¤ ¤ ¤ ¤ . sma signa representations.ansistor off. owing to body effect. The drain current thus varies as i ustrated in Fig.

31(a). where iD = gm vGS and the gate rem ains open. Of particu ar interest to us in this book is the sma signa mode for the saturation region. 6. 6. Viewing the transistor as a vo tage contro ed current source . To represent channe ength modu ation. 2006] June 30.c s v. variation of iD with vD S . we add a resistor as in Fig. 2007 at 13:42 307 (1) Sec. we draw the basic mode as in Fig.31(b): G D G D v GS g v GS m v GS g v GS m rO S (a) S (b) ¤¡¤ ¤ ¤ ¤ ¡¤¤ Figure 6. signa mode of MOSFET.e. (b) inc usion of channe ¤ ¤ ¤ ¤¤ ¡¤¤ ¡ ¤ ¤ ¤ ¤ ¤¡¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ength mo .31 (a) Sma du ation.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. i.3 MOS Device Mode s 307 of the mode proceeds in a manner simi ar to that in Chapter 4 for bipo ar devic es.. 6.

5 mA.63) (6.1 rO = @V D DS @I (6. If n Cox = 0:1 V.64) 1 rO = I = 20 k : D (6. V 2 D : 2 n Cox L GS TH 1 rO I : Since channe ength modu ation is re ative y sma . ¤ This means that the intrinsic gain. (Chapter 4) is equa choice of device dimensions and bias current. Examp e 6..65) (6.14 = 100 A=V2 . to 20 for this ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡¤ ¡¤¤ ¤ ¤ ¤ . W=L = 10. yie ding (6.1 .66) Exercise Repeat the above examp e if W=L is doub ed.60) (6. gm rO . r (6. and So ution We have gm = 2nCox W ID L = 11 : k A so. the denominator of (6.61) c an be approximated as ID . ca cu ate its sma signa parameters.61) 1 =1 W V .62) A MOSFET is biased at a drain current of 0.

(c) i ustrat ion of triode and saturation regions based on gate and drain vo tages.4 PMOS Transistor Having seen both npn and pnp bipo ar transistors. Fo owing the conventions used for bip o ar devices. The channe now consists of ho es and is formed if the gate vo tage is be ow the source potentia by one thresho d vo tage. As V1 fa s and approaches VDD . Indeed.c s v.32(a).jVTH j. VDD M1 V1 1V Examp e 6. determine the region of operation of M1 as V1 goes from VDD to zero. 6 Physics of MOS Transistors 6. we draw the PMOS device as in Fig. as i ustrated in Fig. 6. approaching saturation as VD fa s to VG . VGS VTH .33 Simp e PMOS circuit. with the source termin a identi ed by the arrow and p aced on top to emphasize its higher potentia . That is. the gate source ¤ ¡ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤¤ ¤¤ ¤ ¡ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ .32(b).BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. VGS = 0 and M1 is off. chan ging the doping po arities of the substrate and the S/D areas resu ts in a “PMOS” de vice. (b) PMOS circuit symbo . Assume VDD = 2:5 V and jVTH j = 0:5 V. The transistor operates in the triode region if the drain vo tage is near the sourc e potentia . 2006] June 30. the reader may wonder if a p t ype counterpart exists for MOSFETs.15 Figure 6. 6. where VTH itse f is negative. Figur e 6. S D S G D (a) Triode Region Edge of Saturation (b) Saturation Region p+ n −substrate p+ ID > VTHP VTHP < VTHP (c) Figure 6.32(c) conceptua y i ustrates the gate drain vo tages G required for each r egion of operation. For V1 So ution = VDD . 2007 at 13:42 308 (1) 308 Chap. VTH = VG + jVTH j. to turn the device on .32 (a) Structure of PMOS device.33. In the circuit of Fig. 6.

BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 6. VTH 2 1 . VTH VDS . VDS : L A ternative y.69) (6. turning the device on. VDS : 2 L The sma signa mode of PMOS transistor is identica to that of NMOS devices ( Fig.4 PMOS Transistor 309 potentia is negative enough to form a channe of ho es. jVTH j2 1 + jVDS j 2 L (6. 2006] June 30. At this point. (6. As V1 goes be ow 0. 2 p Cox W VGS . 6. M1 is saturated [F ig. The fo owing examp e i ustrates this point. The vo tage and current po arities in PMOS devices can prove confusing.32(c)].c s v. jVTH jjVDS j . M1 is at the edge of the triode r egion. VG = VDD . we express ID in the saturation regio n as 1 ID.sat = . 6. both equations can be expressed in terms of abso ute va ues: (6..jVTH j = +2 V whi e VD = +1 V.tri = . jVTH j = 0:5 V. (b) sma ¤ ¡¤¤ Examp e 6. 2 p Cox W 2VGS . As V1 fa s further.15 In the triode region. For V1 = +1 V . 6.16 For the con gurations shown in Fig. VGS becomes more negative and the transistor current rises.67) 1 2 ID. Assume 6= 0.5 V.34(a).e. L where is mu tip ied by a negative sign.70) 2 jID.68) jID. VDS . i. RX and M2 gm2v 1 r O2 ¡¤¤ (a) (b) (c) Figure 6. 6. the transistor enters the triode region further.34 (a) Diode connected NMOS and PMOS devices.32(b). Using th e current direction shown in Fig. 2007 at 13:42 309 (1) Sec.sat j = 1 p Cox W jVGS j . RX VDD M2 M1 RY vx iX v1 gm1v 1 r O1 vY iY v1 signa ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ resistance sig .tri j = 1 p Cox W 2jVGS j . determine the sma s RY .31).

RX = vX i X (6. . But. (6. we can de ne itse f to be negative and express ID as 1=2p Cox W=LVGS VTH 2 1 + VDS . ¤ ¤ na mode of (a). i1 ¤ ¤ ¤ ¡¤¤ So ution For the NMOS version. the sma 34(b).34)]. yie ding signa equiva ent appears as depicted in Fig.71) vX = gm1 vX + rO1 X (6.72) 15 To make this equation more consistent with that of NMOS devices [Eq. (c) sma signa mode of (b). 6. a negative carries itt e physica meaning. ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .

76) In both cases. 2006] June 30. 2(a) and 6. PMOS devices exhibit a poorer performance than NMOS transistors. In ana ogy with their bipo ar counterparts [Fig. Fortu nate y. 6. 6.34(c) and write (6.74) (6. thereby a ccommodating PMOS transistors. For examp e.46) indicates that the tr ansconductance of a PMOS device is ower for a given drain current.3 4(a) are ca ed “diode connected” devices and act as two termina components: we wi encounter many app ications of diode connected devices in Chapters 9 and 10. the sma signa resistance is equa to 1=gm if ! 0.44(a)].5 CMOS Techno ogy Is it possib e to bui d both NMOS and PMOS devices on the same wafer? Figures 6.75) (6. 4. an “n we ” enc oses a P MOS device whi e the NMOS transistor resides in the p substrate. 6 Physics of MOS Transistors = g 1 jjrO1 : m1 For the PMOS version.35.c s v. 2007 at 13:42 310 (1) 310 Chap. As i ustrated in Fig. We therefore prefer to use NMOS transistors wherever possib e. we draw the equiva ent as shown in Fig. (6. Eq.73) RY = vY iY vY = gm2 vY + rO1 m2 (6. the structures shown in Fig. 6.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. a oca n type substrate can be created in a p type substrate. NMOS Device B S PMOS Device D S G G D B p+ n+ n+ p+ n+ ¤¤ p+ n −we ¤ ¤ ¤ ¤¤ ¡ ¤ ¡ ¡ ¡ ¤ ¤ ¤ ¤ ¡ ¤¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¡ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ . i1 Y 1 jjr : =g O2 Owing to the ower mobi ity of ho es (Chapter 2). 6.32(a) revea that the two require different types of substrate.

¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤¤ ¤ . the 4004. In fact. many signi cant advantages of comp ementa ry devices eventua y made CMOS techno ogy dominant and NMOS techno ogy obso ete . 16 The rst Inte microprocessor. Ca ed “comp ementary MOS” (CMOS) techno ogy. the above structure requires more comp ex processing than simp e NMOS or PMOS devices.35 CMOS techno ogy. However.16 and the higher cost of CMO S processes seemed prohibitive. the rst few generations of MOS techno ogy contained on y NMOS transistors. was rea ized in NMOS techno ogy.p −substrate Figure 6.

2 Comparison of bipo ar and MOS transistors. In this region..e. As the drain vo tage rises.6 Comparison of Bipo ar and MOS Devices Having studied the physics and operation of bipo ar and MOS transistors. A MOSFET consists of a conductive p ate (the “gate”) atop a semiconductor su bstrate and two junctions (“source” and “drain”) in the substrate. If the drain source vo tage is sma . tem MOSFETs enter the “saturation region” if channe pinch of f occurs. the drain end of the channe begins to move toward the source. 2006] June 30. the device operates a vo tage dependent resistor. Tab e 6. In this region. we can now compare their properties.” de ned as the change i n the output current divided by the change in ¤ ¤ ¤ ¡ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¡¤¤ ¤ ¤ ¤ ¤¡¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¡ ¡ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . i.” this eff ect eads to variation of drain current in the saturation region. Note that the exponentia IC VBE dependence of bipo ar devices acco rds them a higher transconductance for a given bias current. As the gate vo tage ris es.2 shows some of the important aspects of e ach device. Beyond a certain gate source vo tage (the “thresho d vo tage”). As the drain vo tage exceeds VGS . the charge density near the drain fa s. The gate contro s the current ow from the source to the drain. VTH 2 . A measure of the sma signa performance of vo tage dependent current sources is the “transconductance. Ca ed “channe ength modu ation. 2007 at 13:42 311 (1) Sec. the drain current is proportiona to VGS . The current is a so proportiona to the dev ice aspect ratio. If the drain vo tage reach es one thresho d be ow the gate vo tage. reduc ing the effective ength of the device. MOSFETs are e ectronic devices that can operate as vo tage dependent current s ources. MOSFETs op erating in the saturation region behave as current sources and nd wide app icatio n in microe ectronic circuits. mobi e carriers are attracted to the oxide si icon interface and a channe is formed. Bipo ar Transistor Exponentia Characteristic Active: VCB > 0 Saturation: VCB < 0 Finite Base Current Ear y Effect Diffusion Current − MOSFET Quadratic Characteri stic Saturation: VDS < VGS − V TH Triode: VDS > VGS − V TH Zero Gate Current Channe −L ength Modu ation Drift Current Vo tage−Dependent Resistor Tab e 6.” MOSFETs operate in the “triode” region if the drain vo tage is more than one thresho d be ow the gate vo tage.6 Comparison of Bipo ar and MOS Devices 311 6. the drain vo tage is ess than one thresho d be ow the gate vo a tge. a dep etion region is formed in the substrate under the gate area.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. The gate draws near y zero current beca use an insu ating ayer separates it from the substrate. the channe ceases to exist near the dr ain. W=L. 6. 6.7 Chapter Summary A vo tage dependent current source can form an amp i er a ong with a oad resistor .c s v. eading to “pinch off. That is. the d evice is not an idea current source. the drain cu rrent is a function of VGS and VDS . VTH and pinch off occurs.

wh ere the charge density approaches zero? Ca cu ate the tota charge stored in the channe of an NMOS device if Cox = 10 fF=m2 . 6. What are the width and ength of Meq ? Consider a MOSFET expe riencing pinch off near the drain. Referring to Fig. 2007 at 13:42 312 (1) 312 Chap. 6. 3. un ess otherwise stated.4) indicates that the charge dens ity and carrier ve ocity must change in opposite directions if the current remai ns constant. (a) Sketch t he e ectron density in the channe as a function of x. Meq . The transconductance of MOSFETs can be expressed by one of th ree equations in terms of the bias vo tages and currents. Prob ems = 200 A=V2 . Equation (6. How can this re ationship be interpreted at the pinch off point. L = 0:1 m. T he sma signa mode s of NMOS and PMOS devices are identica . Operation across diffe rent regions and/or with arge swings exemp i es “ arge signa behavior. .36 2. The sma signa mode is derived by making a sma change in the vo tage difference between two termina s whi e the the other vo tages remain constant.c s v. Assume VDS = 0. (b) Sketch the oca resi stance of the channe (per unit ength) as a function of x.” If the signa swings are suf cient y sma . If both dev ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¡ ¤ ¤¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ . NMOS and PMOS tra nsistors are fabricated on the same substrate to create CMOS techno ogy. the MOSFET can be represented by a sma signa mo de consisting of a inear vo tage dependent current source and an output resist ance.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Two identica ices operate MOSFETs are p aced in series as shown in Fig. and VTH = 0:4 V for NMOS devices and devices.11 and assuming that VD 0. 4. 2006] June 30.0:4 V for PMOS M1 W L W L M2 M eq Figure 6. 5. VTH = 1 V. as resistors.36. assume n Cox p Cox = 100 A=V2 . 6. Assuming ID is const ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 1. 6 Physics of MOS Transistors the input vo tage. and VGS . W = 5 m. In the fo owing prob ems. exp ain intuitive y why this combination is equiva ent to a sing e transistor.

¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .VTH = 0:6 V and 1. An NMOS device carries 1 mA with VGS . VTH and VDS and measuring ID ? 7. ca cu ate VDS and W=L. VTH VDS . so ve Eq. If the device operates in the triode region.7) to obtain an expression for V x. Is it possib e to determine thes e quantities by app ying different va ues of VGS .VTH = 0:8 V. 1 VDS : L 2 (6.77) Suppose the va ues of n Cox and W=L are unknown.6 mA with VGS . (6.ant. P ot both V x and dV=dx as a f unction of x for different va ues of W or VTH . The drain current of a MOSFET in the triode region is expressed as 2 ID = n Cox W VGS .

Compute the transconductance of a MOSFET operating in the triode region. If the s upp y vo tage is 1.8 V. 2006] June 30. Exp ain why this is not pos sib e.c s v.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. we can de ne an incre menta drain source resistance as rDS.tri = @V DS ¤ ¤ ¡ ¤ ¤ ¤ ¡ ¤¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ . De ne gm = @ID =@VGS for a constant VDS . 2007 at 13:42 313 (1) Sec. For a MOS transistor biased in the triode region. An NMOS d evice operating with a sma drain source vo tage serves as a resistor. 11. We wish to use an NMOS transistor as a variab e resistor with Ron = 500 at VGS = 1 V and Ron = 400 at VGS = 1:5 V. Exp ain why gm = 0 for VDS = 0.7 Chapter Summary 313 8. 6. 9. what is the minimum on resistance that can be achieved w ith W=L = 20? 10.

Compare the resu ts. A some what better approximation is: ID = 1 n Cox W VGS . It is possib e to de ne an “intrinsic ti me constant” for a MOSFET operating as a resistor: = Ron CGS . (a) For V1 = 0. Advanced M OS devices do not fo ow the square aw behavior expressed by Eq. 18.. In Fig. VTH (6. In the circuit of Fig. where V0 is on the order of a few mi ivo t s. . 6. M1 se rves as an e ectronic switch. the square aw behavior is not va id .78) Derive an expression for this quantity. exp ain why the peaks of the parabo as ie on a parabo a themse ves. (b) Repeat part (a) for V1 = 0:5 V. such that the circuit attenuates the signa by on y 5. For an NMOS device. 15.37. p ot ID as a function of VGS for different va ues of VDS . 2 L ¤ ¤ ¤¤ ¤ ¤ ¤ ¤¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . (6. 12. If Vin 0. the input is a sma sinusoid superimposed o n a dc eve : Vin = V0 cos !t + V1 . and we may instead write: ID = WCox VGS . Assume VG = 1:8 V and RL = 100 .81) where vsat is a re ative y constant ve ocity. determine W=L VG M1 RL V in Vout Figure 6. 13. In the circuit of Fig. VTH vsat .1 @ID : (6. Determine the transconductance of such a device.17. Obtain an expression for and exp ain what the circuit design er must do to minimize the time constant. Determine the transconductance of such a device.17).80) where is ess than 2. 6. obtain W=L in terms of RL and other parameters so that Vout = 0:95Vin .37.37 14.79) where CGS = WLCox . For M OS devices with very short channe engths. 16. (6. (6. 17. 6.

5 V M1 0.5 V 0.5 V M1 0.5 V 2V 1.5 V M1 1V ¤ ¤ ¤ ¤ .5 V 0.5 V 2V 1.5 V 1. 2007 at 13:42 314 (1) 314 Chap. 6 Physics of MOS Transistors M1 0.c s v.5 V 0.5 V 0.5 V M1 0.5 V (a) (b) (c) M1 1. 2006] June 30.5 V M1 0.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.5 V (d) (e) (f) M1 0.

7 V (c) (d) Figure 6.5 V (g) (h) (i) Figure 6.2 V 1V 0.M1 0.38. i. If VDS1 = 0:5 V and VDS2 = 1 V. 6. 20.5 V 0.40) match to withi n 1. compute W=L of M1 in Fig.39 21.39. In the Fig.42.2 V (b) M1 M1 0. M1 1V 1V M1 (a) 1V 0. 6.e. what is the maxim um to erab e va ue of ? 22. 23. Assume = 0. what is the minimum a owab e v a ue of VDD if M1 must not enter the ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .38 19.. 6. Using the va ue of W=L foun d in Prob em 22. exp ain what happens if the gate oxide thickness is doub ed due to a manufacturing error. Two current sources rea ized by identica MOSFETs (Fig. 6.2 V 0. Determine the region of operation of M1 in each of the circuits shown in Fig .41 such tha t the device operates at the edge of saturation. 24. Determine the region of operation of M1 in each of the circuits show n in Fig. 0:99ID2 ID1 1:01ID2. 6.

27.40 VDD = 1. 6. In Fig. Assume = 0. 6. 6.c s v. Assume VX goes from 0 to VDD = 1:8 V.46.7 Chapter Summary 315 I D1 M1 VB I D2 M2 Figure 6. derive a relationshi among the ci rcuit arameters that guarantees M1 o erates VDD RD M1 W L Figure 6. 29. 2007 at 13:42 315 (1) Sec. and VDD = 1:8 V. = 0. Assume = 0. calculate the drain current of M1 in Fig.47.8 V RD 1 kΩ 1V M1 Figure 6. Sketch IX as a function of VX for the circuits shown in Fig. Calculate the bias current of M1 in Fig. Assuming W=L = 10=0:18 = 0:1 V.1 . 6. Com ute the value of W=L for M1 in Fig. Determine at what value of VX the device changes its region of o eration. 28.18 Figure 6.43 26.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 2006] June 30. Also. 25.43.8 V RD 500 Ω 1V M 1 W = 10 L 0.45 if = 0. 6.44 for a bias current of I1 .42 triode region? Assume = 0. at the edge of saturation. 6. ¤ ¤ ¤ ¤ .41 VDD = 1.

8 V M1 RS Figure 6. In the circuit of Fig.46 1 kΩ VDD RD M1 Figure 6.45 VDD = 1.1 .8 V M1 VB Figure 6.cls v.48 0:1 V.8 V M1 M1 VX (a) 1V 1V IX IX M1 VX IX M1 VX IX VX (b) (c) (d) Figure 6.47 30.44 VDD RD M1 W L Figure 6. 6 Physics of MOS Transistors VDD = 1. 6. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. W=L = 20=0:18 and = transistor at the edge of saturation? RD 5 kΩ VDD = 1. 2007 at 13:42 316 (1) 316 Cha .48. What value of VB laces the .

VTH = 0 :5 V. (a) Determine W=L if ID = 0 :5 mA.31. (c) Determine ID if VGS . = 0 must rovide a transconductance of . (b) Determine W=L if VGS . An NMOS device o erating in saturation with 1=50 . VTH = 0:5 V.

Deri ve an ex ression for gm rO and lot the result as a function of ID . 6.49.8 V 1 mA Ω M1 1V M1 M1 (a) (b) (c) VDD = 1. VTH remains constant.1 and W=L = 20=0:18.8 V RD 5 kΩ VDD = 1. lot the intrinsic gain. (c) ID is doubled but W=L remains constant. Assume VDS is constant. VDD = 1. 35. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If = 0:1 V.5 mA (d) (e) Figure 6. Determine how the transconductance of a MOSFET (o erating in saturation) cha nges if (a) W=L is doubled but ID remains constant.7 Cha ter Summary 317 32. 33.8 V M1 0. The “intrinsic gain” of a MOSFET o erating in saturation is de ned as gm rO . constru ct the small signal model of each of the circuits shown in Fig. 6. (d) ID is doub led but VGS .8 V RD 100 VDD = 1. (b) VGS .49 34. VTH is doubled but ID remains constant.8 V M1 2 kΩ VDD = 1. Assuming a constant VDS . 2007 at 13:42 317 (1) Sec. of a ¡ .cls v. gm rO .

39. Assume all transistors o erate in saturation and 6= 0. Determine at what value of VX the device changes its region of o eration.56 if all of the transistors o erate in saturation and 6= 0. 38. 40. Determine the region of o eration of M1 in each circuit shown in Fig. With the value of W=L obtained in Problem 41. VTH if ID is constant. If W=L = 10=0:18 and = 0. Re eat Problem 36 for = 0:2 V.55. If = 0. Sketch IX as a function of VX for the circuits shown in Fig. 6. 6. 44. Determine the region of o eration of M1 in each circuit shown in Fig. 6. Assume VX goes from 0 to VDD = 1:8 V. 45. 6.52. Determine the required value of W=L if ID = 0:5 mA. 41.MOSFET (a) as a function of VGS . 6.1 must rovide a gm rO of 20 with VDS = 1:5 V. 37. VTH is constant. An NMOS device with = 0:1 V. (b) as a function of I D if VGS . 6. what value of W=L laces M1 at the edge of saturation in Fig. determine the o erating oint of M1 in each circuit de icted in Fig.1 .50.51. Construct the small signal model of t he circuits de icted in Fig. = 0. ¡ ¡ . 6. what ha ens if VB changes to +0:8 V? 43. Also. 36. Construct the small signal model of each circuit shown in Fig.54.53? 42.

2007 at 13:42 318 (1) 318 VDD RD Vout M2 VB V in M1 (a) Cha .3 V M1 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Consider the circuit de icted in Fig.3 V 0. 2006] June 30. where M1 and M2 o erate in satur ation and exhibit channel length modulation coef cients n and . (a ¡ .51 (b) (c) (d) 46.3 V 1V 0.6 V M1 (a) Figure 6.57. res ectively. 6. 6 VDD RD Vout V in M2 (b) Physics of MOS Transistors VDD RD Vout V in M1 M2 (c) M1 VDD VDD V in M1 Vout M2 VB V in M2 (e) RD Vout M1 (d) Figure 6.cls v.50 M1 2V 2V M1 0.

6. res ectively. lot VX as a function of IX for 0 IX 3 mA. At what value of Vin does the slo e (gain) re ach a maximum? 49.) Construct the small signal equivalent circuit and ex lain why M1 and M2 a ear in “ arallel.58. lot ID as a functio n of VX as VX varies from 0 to 1. 48. Can we say these two arrangements are equi valent? ¡ ¡ . use the MOS models and source/drain di mensions given in A endix A. Plot the in ut/out ut characteristic of the stage s hown in Fig.59 for 0 Vin 1:8 V. For the arrangements shown in Fig. SPICE Problems In the following roblems. 6. 47. Ex lain the shar change in VX as IX exceeds a certain value. 6.” (b) Determine the small signal voltage gain of the circuit. For the circuit shown in Fig.60.8 V. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD .

8 V 1 kΩ M1 (a) (b) (c) Figure 6.5 V 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.54 VDD = 1.9 V 0. 2007 at 13:42 319 (1) Sec.8 V M1 1 kΩ VDD = 1.9 (a) (b) M1 0.8 V M1 VX IX 1V .8 V M1 500 Ω VDD = 1.9 V 319 M1 0.9 V 0. 2006] June 30.cls v.8 V M1 1V 2 kΩ Figure 6.53 VDD = 1.4 V Figure 6.5 V 0.4 V 1V M1 0.52 (c) (d) VDD = 1.7 Cha ter Summary M1 1.

8 V M1 IX M1 VX IX VX (c) (d) Figure 6.VDD = 1.8 V M1 IX VX (a) (b) VDD = 1.55 .

18 .56 VDD M2 V in M1 Vout Figure 6.9 V 2 0. 6 Physics of MOS Transistors V in VDD RS V in M1 Vout RD V in VDD M1 Vout RD M2 Vb M1 Vout R1 M2 RD (c) (a) (b) VDD V in M1 Vout R1 RD M2 V in VDD R2 Vout M1 M2 R1 (d) (e) Figure 6.57 M1 0. 2006] June 30.58 VDD = 1.8 V 500 Ω M1 V in 10 0.18 VX IX Figure 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2007 at 13:42 320 (1) 320 Cha .

59 .Vout Figure 6.

36 5 0.cls v. 2007 at 13:42 321 (1) Sec.36 VX M2 (a) (b) Figure 6. 2006] June 30.9 V 5 0.9 V 5 0. 6.60 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.36 321 IX M1 VX 0.7 Cha ter Summary IX M1 0.

18 IX M1 5 0.8 V M1 5 0.9 V 5 0. Re eat Problem 50 for the circuit illustrated in Fig.62.62 . 6 Physics of MOS Transistors 50. 6.61 51. 2007 at 13:42 322 (1) 322 Cha . 2006] June 30. Plot IX as a function of VX for the arrangement de icted in Fig.61 as VX varies from 0 to 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 VX Figure 6.cls v. 6.8 V. Can you ex lain the behavior of the circuit? IX M1 0.18 M1 5 0.18 VX Figure 6. VDD = 1.

General Conce ts Biasing of MOS Stages Realization of Current Sources MOS Am lif iers Common−Source Stage Common−Gate Stage Source Follower 7. The outline of the cha ter is shown below.1 General Considerations 7. Section 5. we ex ect three basic CMOS am li ers: the “common source” (CS) stage. In othe r words. The similarity of bi olar and MOS small signal models (i. in most bias calculations.1.1. we have VX = R R2 R VDD : 1+ 2 (7. 2007 at 13:42 323 (1) 7 CMOS Am li ers Most CMOS am li ers have identical bi olar counter arts and can therefore be analy zed in the same fashion. 7. 2006] June 30. Nonet heless. and the “source follower. s eci c ally.. it is still instructive to a ly some of the biasing conce ts of Cha ter 5 to MOS stages. and dc and small signal analysis. It is recommended that the reader review Cha ter 5.1. Consider the circuit shown in Fig. Noting that the gate cur rent is zero.e. the “comm on gate” (CG) stage.” 7.1) 323 ¡ ¡ ¡ ¡ ¡ ¡ . biasing.1 MOS Am li er To ologies Recall from Section 5. Our study in this cha ter arallels the develo ments in Cha ter 5.3 that the nine ossible circu it to ologies using a bi olar transistor in fact reduce to three useful con gurati ons.1.2 Biasing De ending on the a lica tion. where the gate voltage is de ned by R1 and R2 . We assume M1 o erates in saturation. identifying both similarities and differences between CMOS and bi ol ar circuit to ologies.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We assume the reader is familiar with conce ts such as I/O im edances. we can neglect channel length modulation. Also. MOS circuits may incor orate biasing techniques that are quite different f rom those described in Cha ter 5 for bi olar stages. Most of these techniques ar e beyond the sco e of this book and some methods are studied in Cha ter 5. a voltage cont rolled current source) suggests that the same must hold for MOS am li ers.cls v.

3): . either by iterati on or by nding ID from (7.8 V 4 kΩ CMOS Am li ers R1 Y RD ID X 10 k Ω M1 R2 RS 1 kΩ Figure 7. (7.2) and re lacing for it in (7.2) and (7. VTH 2 : 2 L (7.2) Also.3) Equations (7.3) can be solved to obtain ID and VGS . 7 VDD = 1. 2006] June 30. Since VX = VGS + ID RS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. R2 V = V + I R : R1 + R2 DD GS D S ID = 1 n Cox W VGS . 2007 at 13:42 324 (1) 324 Cha .cls v.1 MOS stage with biasing.

1 R 1 W 2 2 R1 + R2 VDD . VTH : r s . VGS RS = 2 n Cox L VGS .

7.6) V1 = This value of VGS can then be substituted in (7.2) to obtain ID . and = 0. 1 2 RV = . VTH . VTH to ensure o eration in the saturation region.4) That is R 2 VGS = . Determine bias current of M1 in Fig. W=L :18. n Cox = 100 A=V2 .7) Exam le 7. VTH 2V1 R 2 +DD .1 assuming VTH = 0:5 V. 1 R2 where (7. must exceed VX . VTH 2 .1 Solution We have VX = R R2 R VDD 1+ 2 = 1:286 V: (7.(7.9) VY the = 5=0 sat + V12 + .8) (7. Of course. What is the maximum allowable value of RD for M1 to remain in uration? : n Cox W RS L 1 (7.5) (7.V1 .V1 . VTH + V1 . VTH + R 2+2R V1 VDD .

16) (7. Since V1 = 0:36 V. VTH = 0:786 V.3) gives the new value of VGS as v u VGS = VTH + u t = 0:954 V: n Cox W L 2ID (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11) Consequently. VY D = 3:25 k : = VX .cls v. .14) This gives ID = 297 A. ID = VX R VGS S = 332 A. That is. We may therefore util ize the exact result in (7.19) ¡ .6) to avoid lengthy calculations. 7. ID = VX R VGS S = 312 A: The maximum allowable value of RD is obtained if VY (7. (7. VGS = 0:974 V and (7. the voltage dro across RS can be ex ressed as VX .10) (7. yielding a drain current of 286 A.1 General Considerations 325 With an initial guess VGS = 1 V.13) VGS = 0:989 V: (7. the solutions converge more s lowly than those encountered in Cha ter 5 for bi olar circuits. VGS = 286 mV.18) (7.15) . Substituting for ID in Eq.12) (7. 2007 at 13:42 325 (1) Sec. As seen from the iterations.17) RD = VDDI . (7. 2006] June 30. and hence (7. This is due to t he quadratic (rather than ex onential) ID VGS de endence.

Exercise In the circuit of Exam le 7. Assume = 0.1.2 What is the value of R2 that laces M1 at the edge of saturation? . Exam le 7. assume M1 is in saturation and RD = 2:5 k and com ute (a) the maximum allowable value of W=L and (b) the minimum allowable value of RS (with W=L = 5=0:18).

25) (7.26) . With RD and VX = 1:286 V. M1 must carry a current of 406 A with VGS = 0:88 V : 1 ID = 2 n Cox W VGS . It follows that RS = VX . the minimum allowable value of RS gives a drain current of 406 W = 56:2: L (7. M1 can carry a larger current for a given VGS . VGS = 245 mV. 7 CMOS Am li ers (a) As W=L becomes larger. the maximum allowable value of ID is given by Solution = 2:5 k (7.20) (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (7. 0:4 06 V = 0:88 V. In other words. VTH 2 L 406 A = 50 A=V2 W 0:38 V2 .22) (7.cls v.23) A. Since (b) With W=L = 5=0:18.21) ID = VDD . 2006] June 30. yielding VGS = 1:286 V . 2007 at 13:42 326 (1) 326 Cha . n Cox W L 2ID (7. L thus. VGS I = 604 : D the voltage dro across RS is equal to VX .24) v u VGS = VTH + u t = 1:041 V. VY RD = 406 A: The voltage dro across RS is then equal to 406 mV.

the circuit can be analyzed by noting that M1 is in saturation (why?) and the voltage dro across RG is zero. De i cted in Fig.29) 1 ID = 2 n Cox W VDD . 7. RS + RD ID .2.28) Exercise Re eat the above exam le if VTH = 0:35 V.(7. The self biasing technique of Fig. we have (7. 5. VTH 2 .3). L (7.22 can also be a lied to MOS am li ers.27) (7.30) ¡ . Thus. ID RD + VGS + RS ID = VDD : Finding VGS from this equation and substituting it in (7.

Solution Equation (7. W 5 M 1 L = 0.1 General Considerations VDD RD RG ID M1 RS 327 Figure 7. 2007 at 13:42 327 (1) Sec. and = 0. we solve (7.3 = 0:5 V.31) for RD : (7.2 V.8 V RD 20 k Ω 1 kΩ Exam le 7. VTH What value of RD is necessary to reduce ID by a factor of two? VDD = 1.3 Exam le of self biased MOS stage. VTH RS + RD 1 n Cox L 3 7 2 W 5 ID + VDD . 2006] June 30.33) Exercise Re eat the above exam le if VDD dro s to 1. 7. 2 6VDD .31) = 0: Calculate the drain current of M1 in Fig. ¡ ¡ ¡ + 4 .32) RD = 2:867 k : (7.2 Self biased MOS stage. VTH (7.31) gives ID = 556 A: To reduce ID to 278 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. It follows that 2 2 RS + RD 2 ID . where channel length modulation is neglected.cls v.3 if n Cox = 100 A=V2 .18 200 Ω Figure 7. 7.

.

7.2. NMOS or PMOS devices con gured as shown in Figs. M1 converts the in ut voltage variations to ro orti onal drain current changes. From another ers ective. It is im ortant to understand that only the drain terminal of a MOSFET can draw a dc current and still resent a high im edance. these currents remain inde endent of VX or VY ( so long as the transistors are in saturation).1 CS Core Shown in Fig. (d) NMOS to ology not o erating as a current source.4(b)] draws curre nt from VDD to node Y . and RD transforms the drain currents to the out ut v oltage. the small signal model in Fig .5(a). 7. (b) PM OS device o erating as a current source.gm v1 RD . with the in ut a lied to the gate and the out ut sensed at th e drain.e.cls v.4(a). 7. 7. it draws current from node X to ground. t he small signal model of these two structures is identical to that of the diode connected devices in Fig. the basic CS stage is similar to the common emitter to ology.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34.3 Realization of Current Sources MOS transistors o erating in saturation can act as current sources. thus changing the drain current considerably. 7. On the other hand. (c) PMOS to ology not o erating as a cu rrent source.g R . i. 7. 2006] June 30. revealing a small signal im edance of only 1=gm (if = 0) rather than in nity. VDD X Vb M1 Y Y X Vb M2 VDD Vb Y Vb M1 X VDD M1 (a) (b) (c) (d) Figure 7. 6. (b) small signal mode. That is. As illustrated in Fig. If channel length modulation is neglected..5(b) yields vin = v1 and vout = . vout = .2 Common Source Stage 7.1.5 (a) Common source stage. ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ . m D vin a result similar to that obtained for the common emitter stage in Cha ter 5. If = 0. a PMOS transistor [Fig. 2007 at 13:42 328 (1) 328 Cha . S eci cally. For small signals.4 (a) NMOS device o erating as a current source. VDD RD ID V in In ut A lied to Gate (a) (b) v in Vout M1 Out ut Sensed at Drain v out v1 g v1 m RD Figure 7. 7 CMOS Am li ers 7. an NMOS device serves as a current source with one terminal tied to ground.4(c) and (d) do not o erate as current sources beca use variation of VX or VY directly changes the gate source voltage of each trans istor.

(7.34) .

cls v. 2007 at 13:42 329 (1) Sec. (7. Solution We have gm = 2nCox W ID L 1 = 300 : Thus.35) VDD .18 Figure 7.8 V RD 1 kΩ = v out v in 10 M1 W = L 0. ¡ ¡ across RD (= ID .2 Common Source Stage 329 of 2TheCvoltage gain. so is the voltage dro RD ). VDD = 1. 7. L (7. that is. VTH .36) RD ID VDD . VTH = 0:5 V. 2n Cox W ID RD . 2006] June 30. Verify that M1 o erates in saturat ion. and = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VTH : Exam le 7. r concluding that if ID or RD is increased. Si nce gm n ox W=LID have r = Av = . 7. n Cox 100 A=V2 .6 Exam le of CS stage.4 (7. VGS .37) Calculate the small signal voltage gain of the CS stage shown in Fig. RD ID VGS .1 For M1 to remain in saturation. we the CS stage is also limited by the su ly voltage.6 if ID = 1 mA.

we rst determine the gate source voltage: .39) (7. but “subthresh old conduction” eventually limits the transconductance.(7.38) (7.41) v u VGS = VTH + u t = 1:1 V: n Cox W L 2ID (7. ¡ Av = .43) 1 It is ossible to raise the gain to some extent by increasing W . This conce t is beyond the sco e of this book.40) (7.42) (7.gmRD = 3:33: To check the o eration region.

2 V with res ect to t he triode region. Since VGS . v1 g v1 m (7. 7. 2007 at 13:42 330 (1) 330 Cha .7. In ractice. 7 CMOS Am li ers The drain voltage is equal to VDD . Since the gate current is zero (at low frequencies). The si milarity between the small signal equivalents of CE and CS stages indicates that the out ut im edance of the CS am li er is sim ly equal to . channel length modulation may not be negligible. VTH = 0:6 V. es ecially if RD i s large. The small signal model of CS to ology is therefore modi ed as shown in Fi g. revealing that iX v1 g v1 m rO RD vX ¡ ¡ ¡ a oint of contrast to the CE stage (whose Rin is equal to r ).45) iX RD vX Figure 7.cls v. Let us now com ute the I/O im eda nces of the CS am li er.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The high in ut im edance of the CS to ology lays a critical role in many analog circuits. 7. the curre nt gain of a commonemitter stage is equal to . the device indeed o erates in saturation and has a margin of 0. 2006] June 30. then M1 enters the triode region and its transconductance dro s. we say the CS am li er rovides a current gain of in nity.8. For exam le. By contrast. Rin = 1. (7. if RD is doubled with the intention of doubling A v . RD ID = 0:8 V. Exercise What value of VTH laces M1 at the edge of saturation? Since the gate terminal of MOSFETs draws a zero current (at very low frequencies ).7 Out ut im edance of CS stage.44) Rout = RD : This is also seen from Fig.

48) In other words. channel length modulation and the Early effect im act the CS and CE stages.gmRD jjrO Rin = 1 Rout = RD jjrO : (7.46) (7.Figure 7.8 Effect of channel length modulation on CS stage. res ectively. in a similar manner. Av = .47) (7. ¡ ¡ .

2 Common Source Stage 331 Assuming M1 o erates in saturation. 7. Exercise Re eat the above exam le if a resistor of value M1 .5 v out v in M1 L (a) (b) Figure 7. ¡ ¡ .1 : (7. 7. allowing the use of (7. (b) gain as a funct ion of device channel length. 2006] June 30.9(b)].1 r 2n Cox W can rovide.cls v. determine the voltage gain of the circuit de icted in Fig.46) with RD = 1: Av = .gmrO : This highest voltage a 2 is theW=LI and r = gain that.9 (a) CS stage with ideal current source as a load. jAv j increases with L [Fig.49) gm = jAv j = I L : D (7. VDD Av Exam le 7. but recall from Cha ter 6 that r 2 C WL n ox jAv j ID : L.9(a) and lot the result as a function of the transistor channe l length while other arameters remain constant.51) Consequently.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7.50) This result may im ly that jAv j falls as L increases. Solution The ideal current source resents an in nite small signal resistance. we single transistor have n Cox D O ID . Writing (7. 2007 at 13:42 331 (1) Sec.

2 CS stage With Current Source Load As seen in the above exam le.2. 7. 7. The observations made in relation to Fig. M2 sim ly behaves as a resistor equal to its out ut im edance [Fig.4(b) therefore suggest the use of a PMOS device as the load of an NMOS CS am li er [Fig.R1 is tied between the gate and drain of 7. Let us determine the small signal gain and out ut im eda nce of the circuit.10(b)] ¡ ¡ ¡ ¡ . 7. Having a constant gate source voltage. the trade off between the voltage gain and the voltage headroom can be relaxed by re lacin g the load resistor with a current source.10(a)].

Thus.gm2 vin rO1 jjrO2 . ows ¡ ¡ .52) (7.gm2 rO1 jjrO2 : (7.gm1rO1 jjrO2 Rout = rO1 jjrO2 : Exam le 7. 2006] June 30.6 (7. Com ute the voltage gain of the circuit. (b) small sign al model.53) Figure 7. 7 CMOS Am li ers v1 gm2v 1 r O2 v out v in M1 (b) r O1 (a) Figure 7. VDD v in M2 v out Vb M1 Figure 7. which then through rO1 jjrO2 .46) and (7.11 shows a PMOS CS stage using an NMOS current source load.cls v.54) Exercise Calculate the gain if the circuit drives a loads resistance equal to RL .48) give Av = . Equations (7.10 (a) CS stage using a PMOS device as a current source. because v1 = 0 and hence gm2 v1 = 0. Thus. 2007 at 13:42 332 (1) 332 VDD Vb M2 v out v in M1 VDD Cha . roducing vout = .11 CS stage using an NMOS device as current source. the drain node of M1 sees both rO1 an d rO2 to ac ground. Transistor M2 generates a small signal current equal to gm2 vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution Av = .

M2 acts as a small signal resista nce equal to 1=gm2 .3). and (7.3 CS stage With Diode Connected Load In some a lications.1. we may use a diod e connected MOSFET as the drain load. Illustrated in Fig.12(a).34) yields ¡ ¡ ¡ ¡ .2. With = 0.7. such a to olo gy exhibits only a moderate gain due to the relatively low im edance of the diod e connected device (Section 7. 7.

such a circuit is not used because it r ovides a voltage gain of only unity: Av = . 2006] June 30. n ox 2n Cox W=L2 ID ¡ ¡ .57) and (7. W=L1 : W=L2 s (7. 7.58) (7.56) = . V I =V T C2 T (7. A more accurate ex ression for the gain of the stage in Fig. The reader ma y wonder why we did not consider a common emitter stage with a diodeconnected lo ad in Cha ter 5. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.57) Interestingly. Shown in Fig.59) (7. the gain is given by the dimensions of M1 and M2 and remains inde endent of rocess arameters n and Cox and the drain current.12(b).55) (7. 7.gm1 g 1 (7.gm1 .1: ¡ ¡ m 2 C 2 W=L I 1 D = . As de icted in Fig. ID . (c) sim li ed circuit of (a). 7. and hence Av = .2 Common Source Stage VDD M2 Vout V in M1 V in Q1 (b) 333 VCC Q2 Vout v in M1 (c) 1 g m2 r O2 v out r O1 (a) Figure 7.12(c). (b) bi olar counter art.60) arises from a fundamental difference betw een MOS and bi olar devices: transconductance of the former de ends on device di mensions whereas that of the latter does not. the resistance seen at the drain is now equal to 1=gm2 jjrO2 jjrO1 .12(a) must take channel length modulation into acco unt. Av = .cls v.gm1 g 1 m2 IC 1 1 = .12 (a) MOS stage using a diode connected load. 2007 at 13:42 333 (1) Sec.60) The contrast between (7.

61) Similarly.62) Exam le 7. the out ut resistance of the stage is given by Rout = g 1 jjrO2 jjrO1 : m2 Determine the voltage gain of the circuit shown in Fig. 7.7 .13(a) if 6= 0. (7.1 g jjrO2 jjrO1 : m2 (7.

Solution This stage is similar to that in Fig.12(a).gm2 ¡ ¡ ¡ .cls v.13 CS stage with diode connected PMOS device. 7. 2007 at 13:42 334 (1) 334 VDD V in M2 Vout M1 Cha . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Av = . Thus. 7 CMOS Am li ers Figure 7. but with NMOS devices changed to PMOS transistors: M1 serves as a common source device and M2 as a diode connecte d load.

vin = v1 + gmv1 RS and hence (7. Figure 7.1 jjr jjr : O1 O2 g m1 (7. 7. (b) small signal model.5 V.64) v1 = 1 +vgin R : m S (7. From Fig.65) ¡ ¡ . I/O im edances. As with the bi olar counter art. we have VDD RD Vout V in M1 RS RS v in v1 g v1 m v out RD (a) (b) Figure 7. We ex ect similar results for a degenerated CS am li er. the degeneration resistor sustains a fraction of the in ut voltage change.14 de icts the stage along with its small signal equivalent (if = 0).4 CS Stage With Degeneration Recall from Cha ter 5 that a resistor laced in series with the emitter of a bi olar transistor alters characteristics such as gain.2. 7.14(b). and linearity.63) Exercise Re eat the above exam le if the gate of M1 is tied to a constant voltage equal t o 0.14 (a) CS stage with degeneration.

7. 2007 at 13:42 335 (1) Sec. (b) sim li ed circuit.1 5(b)]. we may study the effect of a res istor a earing in series with the gate (Fig. Effect of Transistor Out ut Im edance As with the bi olar counter arts.gmv1 RD and vout = .68) Exercise What ha ens if 6= 0 for M2 ? In arallel with the develo ments in Cha ter 5. However. Av = . gm + RS a result identical to that ex ressed by (5.157) for the bi olar counter art.67) Exam le 7. the inclusion of the transistor out ut im eda nce com licates the analysis and is studied in Problem 31.cls v.15(a) if = 0.67) if RS is re laced with 1=gm2 : Solution 1=gm2 [Fig. the out ut im edance of the degenerated CS stage lays a critical role in analog design ¡ ¡ .2 Common Source Stage 335 Since gm v1 ows through RD . Nonetheless. 1 RD 1 : gm1 + gm2 (7.8 RD v out M1 (a) Figure 7. vout = . 1 RD . since the gate cur rent is zero (at low frequencies).66) (7. 7. gmRD vin 1 + gm RS = . RG sustains no voltage dro and does not affe ct the voltage gain or the I/O im edances.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The gain is therefore given by (7. VDD RD Vout V in M1 M2 v in 1 g m2 (b) (7.16). Com ute the voltage gain of the circuit shown in Fig. 7. Transistor M2 serves as a diode connected device.15 (a) Exam le of CS stage with degeneration. 2006] June 30. resenting an im edance of 7.

Adding the voltage dro s across rO and RS and equating the result to e have of the RS . we have v1 = . Since RS carries a current equal to iX (why?).iX RS = iX RS . A + gm iX vX .17 shows the small signal equivalent circuit. Figure 7.and is worth studying here.iX lso. the current through rO is equal to iX . gm v1 = iX . w ¡ . gm .

2007 at 13:42 336 (1) 336 Cha .46(a) but with r = 1.18(a) if M1 and M2 are identic al. Com u te the out ut resistance of the circuit in Fig.cls v. iX v1 RS g v1 m rO vX Figure 7. (5.72) Alternatively.69) vX = r 1 + g R + R m S S iX O = 1 + gm rO RS + rO gm rO RS + rO : + iX RS = vX . (b) sim li ed circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 (a) Exam le of CS stage with degeneration.1 97) yields the same results as above. 7 CMOS Am li ers VDD RD RG M1 RS Vout V in Figure 7.196) and (5.70) (7. 7. Letting r ! 1 in Eqs. As ex ected from our study of the bi olar degenerated stage. 5. 7. R out R out Exam le 7. 2006] June 30.17 Out ut im edance of CS stage with degeneration.16 CS stage with gate resistance. . rO iX + gm iX RS and hence (7.9 Vb M1 M2 (a) M1 r O1 1 r g m2 O2 (b) Figure 7.17 is similar to its bi olar counter art in Fig.71) (7. we observe that the model in Fig. the MOS version also exhibits a “boosted” out ut im edance. (7.

Solution The diode connected device M2 can be re resented by a small signal resistance of ¡ ¡ .

and from (7. 2007 at 13:42 337 (1) Sec.70) : Rout = rO1 1 + gm1 g which.2 Common Source Stage 337 1=gm2jjrO2 1=gm2. Transistor M1 is degenerated by this resistance. 2006] June 30. since gm1 ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 7.

19 (a) Exam le of CS stage with degeneration. Equ ation (7. 7.71) can therefore be written as Solution Rout = 1 + gm1 rO1 rO2 + rO1 Assuming gm1 rO2 (7. we have Rout gm1 rO1 rO2 : We observe that this value is quite higher than that in (7. 7.76) (7.77) 1 (which is valid in ractice). (b) sim li ed circuit.19(a) and com are the r esult with that in the above exam le.75) Exercise Do the results remain unchanged if vice? M2 Exam le 7. With its gate source voltage xed. R out R out V b2 V b1 M1 M2 (a) M1 r O1 r O2 (b) Figure 7.75). transistor M2 o erates as a current source. gm1rO1 rO2 + rO1 : ¡ is re laced with a diode connected PMOS de ¡ ¡ . int roducing a resistance of rO2 from the source of M1 to ground [Fig.74) (7.19(b)].m2 1 + g1 m2 (7.10 Determine the out ut resistance of the circuit in Fig.73) = gm2 = gm. reduces to Rout = 2rO1 + g1 m 2rO1 : (7. Assume M1 and M2 are in saturation.

(7.78) .

82) Design the CS stage of Fig. such a circuit no longer exhibits an in nite in ut im edance: VDD R1 C1 V in R2 M1 RS RD Vout V in R1 RG C1 M1 R2 RS VDD RD Vout V in R1 RG C1 M1 R in R2 RS C2 VDD RD Vout (a) (b) (c) Figure 7.20 (a) CS stage with in ut cou ling ca acitor.20(b)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. = 0. (b) inclusion of gate re sistance. and a ower budget of 5 mW.81) Av = . but raises the voltage gain: (7. the vol . G + R1 jj 2 gm + RS where is assumed to be zero.1 is similar to that analyzed for the bi olar stage in Cha ter 5. 7. 7.cls v. it is ossible to utili ze degeneration for bias oint stability but eliminate its effect on the small s ignal erformance by means of a by ass ca acitor [Fig.20(a) along with an in ut cou ling ca acitor (assumed a short circuit). (c) use of by ass ca acitor. Assume n Cox = 100 A=V2 .11 (7. 2007 at 13:42 338 (1) 338 Cha .5 CS Core With Biasing The effect of the sim le biasing network shown in Fig . if the circuit is driven by a tage gain falls to (7. 7.RD . R R1 jjR2 R gmRD : G + R1 jj 2 Exam le 7. 7. 2006] June 30.80) nite source im edance [Fig. De icted i n Fig. VTH = 0:5 V. an in ut im edance of 50 k . ¡ Thus. this does not alter the in ut im edance of the CS stage : Rin = R1 jjR2 . 7 CMOS Am li ers Exercise Re eat the above exam le for the PMOS counter art of the circuit. 7.79) 1.20(c)].2. As mentioned in Cha ter 5.20(c) for a voltage gain of 5. 7. Rin = R1 jjR2 : Av = R R1 jjR2 R (7. Unlike the case of bi olar realization.

. Also. assume a voltage dro of 400 mV across RS .and VDD = 1:8 V.

we have chosen an excessively large RD . 6 and hence (7.. Since the gate voltage i s equal to 1. the gate drain voltage difference exceeds VTH . This choice yields (7. along with R in = R1 jjR2 = 50 k .89) R1 + R2 VDD = 1:4 V. 2007 at 13:42 339 (1) Sec.4 V.85) RD = 463 : Writing (7. driving M1 int o the triode region! How did our design rocedure lead to this result? For the g iven ID .88) L With VGS = 1 V and a 400 mV dro across RS . an excessively small gm (because gm RD = 5). even though VGS is reasonable. As an initial guess. e.86) ID = 1 n Cox W VGS .cls v. we allocate 2.83) As with ty ical design roblems. It follows that Solution RS = 148 : V. However.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.84) (7. R1 = 64:3 k R2 = 225 k : (7.e. 1:25 V = 0:55 V. The drain vol tage is given by VDD . 2006] June 30.DV GS TH = 92:1 . with ID known.4 V. VGS = 1 I gm = V 2. yields. su ose we halve RD and do uble gm by increasing W=L by a factor of four: ¡ ¡ ¡ . which.2 Common Source Stage 339 The ower budget along with VDD = 1:8 V im lies a maximum su ly current of 2. the gate voltage reaches 1. the choice of gm and RD is somewhat exible so lo ng as gm RD = 5.90) (7.91) We must now check to verify that M1 indeed o erates in saturation. We must therefore increase gm so as to allow a lower value for RD . For exam le.. requiring that R2 (7. ID RD = 1:8 V . we must ensure a reasonable value for V GS .7 mA to M1 and the remaining 80 A to R1 a nd R2 . VTH 2 2 L gives (7.g.78 mA.87) W = 216: (7. 7. i.

W = 864 L gm = 46:1 : 3 (7.92) (7.93) .

2006] June 30. In articular.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VTH to ensure M 1 is saturated.95) The CG stage suffers from voltage headroom gain trade offs similar to those of t he CB to ology. a value higher Exercise = 1:2 V. to achieve a high gain. That is.3 Common Gate Stage Shown in Fig. a high ID or RD is necess ary. n Cox = 100 A=V2 . thereby lowering the drain current by g m V and raising Vout by gm V RD . RD ID than the gate voltage minus VTH . then the gate source vol tage of M1 decreases by the same amount. V .21 Common gate stage. 2007 at 13:42 340 (1) 340 Cha .cls v. the voltage gain is ositive and equal to VDD RD Vout V in In ut A lied to Source M1 Vb Out ut Sensed at Drain Figure 7. Negl ¡ ¡ ¡ ¡ Re eat the above exam le for a ower budget of 3 mW and VDD ¡ ¡ ¡ .84): VGS = 250 mV. Thus. 7 CMOS Am li ers The corres onding gate source voltage is obtained from (7. if the in ut rises by a small value. must remain above Vb . Here. Is M1 in saturation? The drain voltage is equ al to VDD . A micro hone having a dc level of zero drives a CG stage biased at ID = 0:5 mA. (7. dete rmine the maximum allowable value of RD and hence the maximum voltage gain. the CG to ology resembles the common base stage studied in C ha ter 5. VTH = 0:5 V. 7. yielding a gate voltage of 650 mV. and VDD = 1:8 V. Av = gmRD : (7.21. M1 o erates in saturat ion. 7. VDD . If W=L = 50. ID RD . but the drain voltage.94) = 1:17 V.

VTH 2 L (7. the gate source voltage can be de termined from Exam le 7. With W=L known.96) ¡ ¡ .ect channel length modulation.12 Solution 1 ID = 2 n Cox W VGS .

VTH and hence (7.22 summarizes the allowable signal levels in this design. Exercise If a gain of 10 is required.100) Av 6:06: Figure 7. The gate volt age can be generated using a resistive divider similar to that in Fig. ID RD Vb .447 V M1 0 Vout Vb = 0. 7.97) VDD .cls v.947 V V in Figure 7.20(a). 7.1 and (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. what value should be chosen for W=L? We now com ute the I/O im edances of the CG stage. 2007 at 13:42 341 (1) Sec. we have from Fig.98) RD 2:71 k : Also. 2006] June 30.99) = 447 . ex ecting to obtain results s imilar to those of the CB to ology. 7.22 Signal levels in CG stage.vX and iX v1 iX g v1 m ¡ ¡ . VDD RD Vb − V TH = 0.23(a) v1 = . the above value of W=L and ID yield gm (7. Neglecting channel length modulation for now .3 Common Gate Stage 341 as VGS = 0:947 V: For M1 to remain in saturation. (7.

23 (a) In ut and (b) out ut im edances of CG stage.gmv1 = gmvX : (7.101) (7.102) . iX = .RD v1 g v1 m RD vX vX (a) (b) Figure 7.

105) (7.24) but still with = 0.109) The gain is therefore equal to that of the degenerated CS stage exce t for a neg . 2007 at 13:42 342 (1) 342 Cha . 7.104) Rout = RD . from Fig. an ex ected result because the circuits of Figs.23(b) and 7.23(b).7 are identical. Also.cls v. we write VDD RD Vout RS v in M1 X 1 gm Vb v in RS vX 1 gm Figure 7. v1 (7.108) (7. 7. 7. 7 CMOS Am li ers That is. vX = 1 gm vin gm + RS 1 = 1 + g R vin : m S Thus.24 Sim li cation of CG stage with signal source resistance.107) (7. Rin = g1 .103) = 0 and hence (7. Let us study the behavior of the CG stage in the resence of a nite source im eda nce (Fig. In a manner similar to that de icted in Cha ter 5 for the CB to ology. 1 (7.106) vout = vout vX vin vX vin g = 1 +mgRD m RS = 1 RD : gm + RS (7. m a relatively low value. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

we can make two observations. 7. However.ative sign. the CG am li er exhibits a cur rent gain of unity: the current rovided by the in ut voltage source sim ly ows t hrough the channel and emerges from the drain node.e. a resistance a earing in series with the gate terminal [Fig.25(a)] does not alter the gain or I/O im edances (at low f requencies) because it sustains ¡ ¡ ¡ . The analysis of the common g ate stage in the general case. i. First.. including both channel length modulation an d a nite source im edance is beyond the sco e of this book (Problem 41). In contrast to the common source stage.

25(b)] is identical to that of the dege nerated CS to ology: Rout = 1 + gm rO RS + rO : Exam le 7. VDD RD Vout RS M 1 V in X M2 Vb v in RS 1 g m1 R out1 RS r O1 M1 1 r g m2 O2 (c) vX 1 g m2 (b) (a) Figure 7.25 (a) CG stage with gate resistance. calculate the voltage gain if = 0 and th e out ut im edance if 0. We rst com ute vX =vin with the aid of the equivalent circuit de icted in Fig. (b) out ut resistance of CG stage .26(a).13 (7. 26(b): Solution vX = gm2 jj gm1 1 1 vin gm2 jj gm1 + RS Noting that vout =vX ¡ . (b) equivalent in ut network. 7. 7.110) For the circuit shown in Fig. 7. Second. 2006] June 30. 7. (c) calculati on of out ut resistance.cls v. 2007 at 13:42 343 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the out ut resistance of the CG stage in the general case [Fig. a zero otential dro —as if its value were zero.26 (a) Exam le of CG stage.3 Common Gate Stage VDD RD Vout M1 v in RG Vb RS rO M1 R out 343 (a) (b) Figure 7.

we have vout = gm1 RD vin 1 + gm1 + gm2 RS : (7.111) = 1 + g 1 g R : m1 + m2 S (7.1 1 (7.113) .112) = gm1 RD .

Design the common gate stage of Fig. 2006] June 30. we have vout = vX vout vin vin vX R3 = R jj1jj1=gm R (7.119) where channel length modulation is neglected. 7.27 CG stage with biasing.110) is equal to Rout1 = 1 + gm1rO1 g 1 jjrO2 jjRS gm1 rO1 m2 m2 (7. 7.1 CG Stage With Biasing Following our study of the CB biasing in Cha ter 5. resistor R3 lowers the in ut im edance—and hence th e voltage gain—if the signal source exhibits a nite out ut im edance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.27 for the gm1 rO1 g 1 jjRS g 1 jjRS + rO1 : gm RD . we surmise the CG am li er can be biased as shown in Fig. we .cls v.27. Providing a ath f or the bias current to ground. VDD RD Vout RS C1 M1 X R3 R1 V in R2 Figure 7. RS .117) Exercise Calculate the out ut im edance if the gate of M2 is tied to a constant voltage.116) (7. 7.118) (7. 7 CMOS Am li ers To com ute the out ut im edance.115) The overall out ut im edance is then given by Rout = Rout1 jjRD m2 (7. =gm + S 3 ¡ ¡ ¡ rst consider Rout1 . as shown in Fig. As mentioned earlier. Since the im edance seen to the right of node X is equal to R3 jj1=gm .3. which from (7. 7. the voltage divider consisting of R1 and R2 does not affect the small signal behavior of the circuit (at low frequencies). 2007 at 13:42 344 (1) 344 Cha .26(c) + rO1 + rO1 jjRD : .114) (7.

Exam le 7.14 = 5. following arameters: vout =vin .

we wish to minimize W=L (and hence transistor ca acitan ces). Exercise If W=L cannot exceed 100.cls v.15 Solution VDD . we choose an initial valu e for VGS to arrive at a reasonable guess for W=L.11. ¡ . Thus. and = 0. ID RD VGS + VR3 . if VGS = 0:8 V. we obtain a total su ly current of 1. The gate voltage is equal to VGS lus the dro across R3 . Let us determine whether M1 o erates in saturation. For exam le.1 . ower budget = 2 mW. Thus. Assume n Cox = 1 00 A=V2 .120) (7. What is the minimum acce table value of W=L? For a given ID .121) = 45 k and R2 = 135 k . we must rst com ute the maximum allowable VGS . VTH = 136:4 . M1 is indeed in saturation. 7. We im ose the condition for saturation as Exam le 7.1 mA for the drain current of M1 . VTH . then W=L = 244. dictating RD = 682 for vout =v in = 5. VGS . t he drain voltage is given by VDD . On the other hand. VTH . From the ower budget. we leave 1.3 Common Gate Stage 345 RS = 0. R1 and R2 . 2007 at 13:42 345 (1) Sec. Since the drain voltage excee ds VG . VDD = 1:8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The resistive divider consisting of R1 and R2 must establish a gate voltage equal to 1. VTH = 0:5 V. 2006] June 30.35 V. the voltage dro across R3 is equal to 550 mV. VTH increases. Allocating 1 0 A to the voltage divider. ID RD = 1:05 V. A larger value of W=L yields a greater g m . allowing a lower value of RD . As in Exam le 7.11 mA. amounting to 1. what voltage gain can be achieved? Su ose in Exam le 7. We must now com ute tw o interrelated arameters: W=L and RD . as W=L decre ases. and gm = 2ID =VGS . R3 = 500 . 1=gm = 50 .35 V while drawing 10 A: Solution VDD = 10 A R1 + R2 R2 V = 1:35 V: R1 + R2 DD It follows that R1 (7.14.

124) where VR3 denotes the voltage dro n: across R3 .122) and (7. VTH VGS .123) VDD . VTH + VR3 2 (7.122) VGS . and set gm RD to the required gai . VTH RD = Av : Eliminating RD from (7.(7.123) gives: 2ID (7. Av VGS .

2007 at 13:42 346 (1) 346 Cha . VDD .cls v. 2006] June 30. VR3 : Av + 1 2 (7. 7 CMOS Am li ers and hence VGS . VTH In other words.125) W=L It follows that 2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

including channellength modu lation. 7. we have gmv1 rO jjRL (7.128) = vout : ¡ ¡ .4. we say the follower can ser ve as a “level shift” circuit. too. The circuit’s behavior is similar to that of the bi olar counter art. VDD V in In ut A lied to Gate M1 Vout RL Out ut Sensed at Source Figure 7.126) Av + 2 W=L 172:5: (7.2VIDn. Vout “follows” Vin . the gate source voltage tends to increase. Thus.28 Source follower. 7. Recognizing that rO a ears in arallel with RL .29(a) de icts the small signal equivalent of the source follower.1 Source Follower Core If the gate voltage of M1 in Fig.28. we ex ect this to ology to exhibit a subunity gain. The am li er senses the in ut at the gate and roduces the out ut at the source. 7. Vin . 7. Figure 7. Since the dc level of Vout is lower than that of Vin by VGS . From our analysis of emitter followers in Cha ter 5.127) Exercise Re eat the above exam le for Av = 10.4 Source Follower The MOS counter art of the emitter follower is called the “source follower” (or the “c ommondrain” stage) and shown in Fig.28 is raised by a small amount.Cox 2 DD R3 : V (7. thereby raising t he source current and hence the out ut voltage. with the drain tied to VDD .

130) (7. The voltage gain is therefore ositive and less than unity. however.16 vin 1 + gmrO jjRL = 1 rO jjRL : g + rO jjRL ¡ . 7. Also. (b) sim li ed circuit.1 31) (at low frequencies) because it sustains a zero dro . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.29 (a) Small signal equivalent of source follower.cls v.131) As with emitter followers. we can view the above result as voltage division betw een a resistance equal to 1=gm and another equal to rO jjRL [Fig. vin = v1 + vout : It follows that (7. rO ).129) vout = gm rO jjRL m (7.4 Source Follower 1 gm 347 v in v1 g v1 m rO v in v out RL r O v out RL (a) (b) Figure 7. It is desirable to m aximize RL (and Exam le 7.29(b)]. Note . that a resistance laced in series with the gate does not affect (7. 2007 at 13:42 347 (1) Sec. 7.

30(a). Since M2 sim ly resents an im edance of rO2 from the out ut node to ac ground [ Fig. we substitute RL = rO2 in Eq.A source follower is realized as shown in Fig. VDD V in M1 Vout Vb M2 (a) (b) M2 serves as a current source. 7.131): Solution Av = 1 rO1 jjrO2 : gm1 + rO1 jjrO2 (7.30 (a) Follower with ideal current source. V in M1 r O1 Vout r O2 Figure 7.30(b)].132) . (b) sim li ed circuit. 7. (7. where Calculate the volt age gain of the circuit.

VTH = 0:5 V. U sing this value for ID in gm = 2n Cox W=LID gives W=L = 360: (7.5 and a o wer budget of 10 mW. Assume n Cox = 100 A=V2 . RS is laced in series with the source of Exam le 7.56 mA.28. and VDD = 1:8 V.17 Design a source follower to drive a 50 load with a voltage gain of 0.135) Exercise What voltage gain can be achieved if the ower budget is raised to 15 mW? ¡ .134) The ower budget and su ly voltage yield a maximum su ly current of 5. we have Av = 1 RL gm + RL and hence (7.cls v. With RL Solution = 50 and rO = 1 in Fig. 2007 at 13:42 348 (1) 348 Cha .133) gm = 501 : (7. Exercise Re eat the above exam le if a resistance of value M2 . 7 CMOS Am li ers If rO1 jjrO2 1=gm1. 2006] June 30. then Av 1. = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7.

It is instructive to com ute the out ut im edance of the source follower.2 As il lustrated in Fig. 7.31, Rout consists of the resistance seen looking u into the source in arallel with that seen looking down into RL . With 6= 0, the former is equal to 1=gm jjrO , yielding Rout = g1 jjrO jjRL g1 jjRL : m m (7.136) (7.137) In summary, the source follower exhibits a very high in ut im edance and a relat ively low out ut im edance, thereby roviding buffering ca ability. 2 The in ut im edance is in nite at low frequencies.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 349 (1) Sec. 7.4 Source Follower 349 M1 RL rO M1 rO 1 gm rO R out RL Figure 7.31 Out ut resistance of source follower. 7.4.2 Source Follower With Biasing The biasing of source followers is similar to that of emitter followers (Cha ter 5). Figure 7.32 de icts an exam le where RG establishes a dc voltage equal to VDD at the gate of M1 (why?) and RS sets the d rain bias current. Note that M1 o erates in saturation because the gate and drai n voltages are equal. Also, the in ut im edance of the circuit has dro ed from in nity to RG . VDD C1 V in RG M1 RS C2 Vout Figure 7.32 Source follower with in ut and out ut cou ling ca acitors. Let us com ute the bias current of the circuit. With a zero voltage dro across RG , we have VGS + ID RS = VDD : Neglecting channel length modulation, we write (7.138) 1 ID = 2 n Cox W VGS , VTH 2 L 1 C W V , I R , V 2 : = 2 n ox L DD D S TH The resulti ng quadratic equation can be solved to obtain ID . Exam le 7.18 (7.139) (7.140) Design the source follower of Fig. 7.32 for a drain current of 1 mA and a voltag e gain of 0.8. Assume n Cox = 100 A=V2 , VTH = 0:5 V, = 0, VDD = 1:8 V, and RG = 50 k . The unknowns in this roblem are VGS , formed:

¡

Solution W=L, and RS . The following three equations can be (7.141) (7.142) ID = 1 n Cox W VGS , VTH 2 2 L ID RS + VGS = VDD

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 350 (1) 350 Cha . 7 CMOS Am li ers Av = 1 RS : gm + RS RS Av = VGS , VTH 2ID + RS 2 = V , VID RS 2I R GS TH + D S 2 ID RS = V ,V +I R : DD TH D S Thus, (7.143) If gm is written as 2ID =VGS , VTH , then (7.142) and (7.143) do not contain W=L a nd can be solved to determine VGS and RS . With the aid of (7.142), we write (7. 143) as (7.144) (7.145) (7.146) A RS = VDD I, VTH 2 , vA D v = 867 : and (7.147) (7.148) VGS = VDD , ID RS A = VDD , VDD , VTH It follows from (7.141) that (7.149) (7.150) (7.151) W = 107: L (7.152) Exercise What voltage gain can be achieved if W=L cannot exceed 50? Equation (7.140) reveals that the bias current of the source follower varies wit h the su ly voltage. To avoid this effect, integrated circuits bias the followe r by means of a current source (Fig. 7.33). 7.5 Summary and Additional Exam les In this cha ter, we have studied three basic CMOS building blocks, namely, the c ommon source stage, the common gate stage, and the source follower. As observed throughout the cha ter, the small signal behavior of these circuits is quite sim ilar to that of their bi olar counter arts, with the exce tion of the high im ed ance seen at the gate terminal. We have noted that the biasing 2 , v Av = 0:933 V:

¡

¡

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 351 (1) Sec. 7.5 Summary and Additional Exam les VDD C1 RG M1 C2 Vout Vb M2 V in C1 RG M1 C2 Vout VDD 351 V in Figure 7.33 Source follower with biasing. schemes are also similar, with the quadratic ID VGS relationshi su lanting th e ex onential IC VBE characteristic. In this section, we consider a number of a dditional exam les to solidify the conce ts introduced in this cha ter, em hasiz ing analysis by ins ection. Exam le 7.19 Calculate the voltage gain and out ut im edance of the circuit shown in Fig. 7.3 4(a). VDD V in M1 Vout Vb M2 M3 v in M1 r O2 r O1 v out 1 r g m3 O3 (b) (a) Figure 7.34 (a) Exam le of CS stage, (b) sim li ed circuit. We identify M1 as a common source device because it senses the in ut at its gate and generates the out ut at its drain. Transistors M2 and M3 therefore act as t he load, with the former serving as a current source and the latter as a diode c onnected device. Thus, M2 can be re laced with a small signal resistance equal t o rO2 , and M3 with another equal to 1=gm3 jjrO3 . The circuit now reduces to that de icted in Fig. 7.34(b), yielding Solution Av = ,gm1 g 1 jjrO1 jjrO2 jjrO3 m3 and (7.153) Rout = g 1 jjrO1 jjrO2 jjrO3 : m3 Note that 1=gm3 is dominant in both ex ressions. (7.154) Exercise Re eat the above exam le if M2 is converted to a diode connected device.

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 352 (1) 352 Cha . 7 CMOS Am li ers Exam le 7.20 Com ute the voltage gain of the circuit shown in Fig. 7.35(a). Neglect channel l ength modulation in M1 . V DD M3 V in Vb M1 Vout M2 (a) (b) 1 r g m3 O3 V in M1 Vout r O2 Figure 7.35 (a) Exam le of CS stage, (b) sim li ed circuit. O erating as a CS stage and degenerated by the diode connected device M3 , trans istor M1 drives the current source load, M2 . Sim lifying the am li er to that in Fig. 7.35(b), we have 2 Av = , 1 rO1 : + g jjrO3 gm1 m3 Solution (7.155) Exercise Re eat the above exam le if the gate of M3 is tied to a constant voltage. Exam le 7.21 Determine the voltage gain of the am li ers illustrated in Fig. 7.36. For sim lici ty, assume rO1 = 1 in Fig. 7.36(b). VDD V in M2 Vout Vb M1 RS V b1 M1 RS (b) VDD V b2 M2 Vout V in (a) Figure 7.36 Exam les of (a) CS and (b) CG stages . Degenerated by RS , transistor M1 in Fig. 7.36(a) resents an im edance of 1 + gm 1 rO1 RS + rO1 to the drain of M2 . Thus the total im edance seen at the drain is equal to 1+ gm1 rO1 RS +

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 353 (1) Sec. 7.5 Summary and Additional Exam les 353 rO1 jjrO2 , giving a voltage gain of Av = ,gm2 f 1 + gm1 rO1 RS + rO1 jjrO1 g : Av 2 = 1 rO2 : gm1 + RS (7.156) In Fig. 7.36(b), M1 o erates as a common gate stage and M2 as the load, obtaining (7.109): (7.157) Exercise Re lace RS wit a diode connected device and re eat the analysis. Calculate the voltage gain of the circuit shown in Fig. 7.37(a) if = 0. VDD RD Vout V in M1 M2 I1 Vb v in 1 g m1 M 2 Exam le 7.22 RD v out (a) Figure 7.37 (a) Exam le of a com osite stage, (b) sim li ed circuit. (b) In this circuit, M1 o erates as a source follower and M2 as a CG stage (why?). A sim le method of analyzing the circuit is to re lace vin and M1 with a Thevenin equivalent. From Fig. 7.29(b), we derive the model de icted in Fig. 7.37(b). Th us, Solution Av = 1 RD 1 : gm1 + gm2 (7.158) Exercise What ha ens if a resistance of value R1 is laced in series with the drain of M 1 ?

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 354 (1) 354 Cha . 7 CMOS Am li ers Exam le 7.23 The circuit of Fig. 7.38 roduces two out uts. Calculate the voltage gain from t he in ut to and to X . Assume = 0 for M1 . VDD Vb M4 V in X M2 M3 Y M1 Vout1 Vout2 Y Figure 7.38 Exam le of com osite stage. For Vout1 , the circuit serves as a source follower. The reader can show that if rO1 = 1, then M3 and M4 do not affect the source follower o eration. Exhibiting a small signal im edance of 1=gm2jjrO2 , transistor M2 acts as a load for the fol lower, yielding from (7.131) Solution 1 vout1 = gm2 jjrO2 : 1 1 vin gm2 jjrO2 + gm1 (7.159) For Vout2 , M1 o erates as a degenerated CS stage with a drain load consisting o f the diode connected device M3 and the current source M4 . This load im edance is equal to 1=gm3jjrO3 jjrO4 , resulting in 1 vout2 = , gm3 jjrO3 jjrO4 : 1 + 1 jjr vin gm1 gm2 O2 (7.160) Exercise Which one of the two gains is higher? Ex lain intuitively why. 7.6 Cha ter Summary The im edances seen looking into the gate, drain, and source of a MOSFET are equ al to in nity, rO (with source grounded), and 1=gm (with gate grounded), res ectiv ely . In order to obtain the required small signal MOS arameters such as gm and rO , the transistor must be “biased,” i.e., carry a certain drain current and susta in certain gate source and drain source voltages. Signals sim ly erturb these c onditions.

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 355 (1) Sec. 7.6 Cha ter Summary 355 Biasing techniques establish the required gate voltage by means of a resistive ath to the su ly rails or the out ut node (self biasing). With a single transis tor, only three am li er to ologies are ossible: common source and common gate st ages and source followers. The CS stage rovides a moderate voltage gain, a high in ut im edance, and a moderate out ut im edance. Source degeneration im roves the linearity but lowers the voltage gain. Source degeneration raises the out ut im edance of CS stages considerably. The CG stage rovides a moderate voltage g ain, a low in ut im edance, and a moderate out ut im edance. The voltage gain ex ressions for CS and CG stages are similar but for a sign. The source follower rovides a voltage gain less than unity, a high in ut im edance, and a low out ut im edance, serving as a good voltage buffer. Problems In the following roblems, unless otherwise stated, assume n Cox = 200 A=V2 , Cox = 100 A=V2 , = 0, and VTH = 0:4 V for NMOS devices and ,0:4 V for PMOS devices. 1. In the circuit of Fig. 7.39, determine the maximum allowable value of VDD = 1.8 V 50 k Ω 1 kΩ W=L if M1 must M1 Figure 7.39 remain in saturation. Assume = 0. 2. We wish to design the circuit of Fig. 7.40 for a drain current of 1 mA. If W=L com ute R1 and R2 such that the in ut im ed ance is at least 20 k . VDD = 1.8 V R1 500 Ω = 20=0:18, M1 R2 Figure 7.40 3. Consider the circuit shown in Fig. 7.41. Calculate the maximum transconductan ce that M1 can rovide (without going into the triode region.) 4. The circuit of Fig. 7.42 must be designed for a voltage dro of 200 mV across RS . (a) Calcula te the minimum allowable value of W=L if M1 must remain in saturation. (b) What are the required values of R1 and R2 if the in ut im edance must be at least 30 k .

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 356 (1) 356 Cha . 7 CMOS Am li ers VDD = 1.8 V 10 k Ω 1 kΩ M1 100 Ω Figure 7.41 VDD = 1.8 V R1 500 Ω M1 R2 RS 100 Ω Figure 7.42 5. Consider the circuit de icted in Fig. 7.43, where W=L = 20=0:18. Assuming the current owing through R2 is one tenth of ID1 , calculate the values of R1 and R2 so that ID1 = 0:5 VDD = 1.8 V R1 500 Ω M1 R2 RS 200 Ω Figure 7.43 mA. 6. The self biased stage of Fig. 7.44 must be designed for a drain current o f 1 mA. If M1 is to VDD = 1.8 V RG RD M1 Figure 7.44 rovide a transconductance of 1=100 , calculate the required value of RD . 7. We w ish to design the stage in Fig. 7.45 for a drain current of 0.5 mA. If W=L = 50= 0:18, calculate the values of R1 and R2 such that these resistors carry a curren t equal to one tenth of ID1 . 8. Due to a manufacturing error, a arasitic resis tor, RP has a eared in the circuit of Fig. 7.46. We know that circuit sam les f ree from this error exhibit VGS = VDS whereas defective

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 357 (1) Sec. 7.6 Cha ter Summary VDD = 1.8 V R1 2 kΩ 357 M1 R2 Figure 7.45 VDD = 1.8 V 10 k Ω 20 k Ω 1 kΩ M1 RS RP 200 Ω Figure 7.46 sam les exhibit VGS = VDS + VTH . Determine the values of W=L and RP . 9. Due to a manufacturing error, a arasitic resistor, RP has a eared in the circuit of Fig. 7.47. We know that circuit sam les free from this error exhibit VGS = VDS + 100 mV whereas VDD = 1.8 V 30 k Ω RP 2 kΩ M1 Figure 7.47 defective sam les exhibit VGS = VDS + 50 mV. Determine the values of W=L and RP . 10. In the circuit of Fig. 7.48, M1 and M2 have lengths equal to 0.25 m and = 0:1 V,1 . IX M1 VB IY M2 Figure 7.48 Determine W1 and W2 such that IX = 2IY = 1 mA. Assume VDS 1 = VDS 2 = VB = 0:8 V . What is the out ut resistance of each current source? 11. An NMOS current sour ce must be designed for an out ut resistance of 20 k and an out ut current of 0. 5 mA. What is the maximum tolerable value of ? 12. The two current sources in Fi g. 7.49 must be designed for IX = IY = 0:5 mA. If VB 1 = 1 V, VB 2 = 1:2 V, = 0

:1 V,1 , and L1 = L2 = 0:25 m, calculate W1 and W2 . Com are the out ut resistanc es of the two current sources.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 358 (1) 358 Cha . 7 CMOS Am li ers IX M1 V B1 V B2 IY M2 Figure 7.49 13. A student mistakenly uses the circuit of Fig. 7.50 as a current source. If W =L = 10=0:25, = 0:1 V,1 , VB1 = 0:2 V, and VX has a dc level of 1.2 V, calculat e the im edance seen at the source of M1 . VX M1 V B1 Figure 7.50 14. In the circuit of Fig. 7.51, M1 and M2 serve as current sources. Calculate IX VDD W L IX M1 VB M2 2W L and IY if IY Figure 7.51 15. VB = 1 V and W=L = 20=0:25. How are the out ut resistances of M1 and M2 related? Consider the circuit shown in Fig. 7.52, where W=L1 = 10=0:18 and W=L2 = 30=0:18. i f = 0:1 V,1 , calculate VB such that VX = 0:9 V. VDD = 1.8 V M2 VB X M1 Figure 7.52 16. In the circuit of Fig. 7.53, W=L1 = 5=0:18, W=L2 = 10=0:18, 1 = 0:1 V,1 , and 2 = 0:15 V,1 . (a) Determine VB such that ID1 = jID2 j = 0:5 mA for VX = 0:9 V. (b ) Now sketch IX as a function of VX as VX goes from 0 to VDD . 17. In the common source stage of Fig. 7.54, W=L = 30=0:18 and = 0. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M1 o erates in saturation.)

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 359 (1) Sec. 7.6 Cha ter Summary VDD = 1.8 V M2 VB IX VX 359 M1 Figure 7.53 VDD = 1.8 V RD 2 kΩ Vout V in M1 Figure 7.54 (b) With such a drain bias current, calculate the voltage gain of the stage. 18. The circuit of Fig. 7.54 is designed with W=L = 20=0:18, = 0, and ID = 0:25 mA . (a) Com ute the required gate bias voltage. (b) With such a gate voltage, how much can W=L be increased while M1 remains in saturation? What is the maximum vo ltage gain that can be achieved as W=L increases? 19. We wish to design the stag e of Fig. 7.55 for a voltage gain of 5 with W=L 20=0:18. VDD = 1.8 V RD Vout V in M1 Figure 7.55 Determine the required value of RD if the ower dissi ation must not exceed 1 mW . 20. The CS stage of Fig. 7.56 must rovide a voltage gain of 10 with a bias cu rrent of 0.5 mA. Assume 1 = 0:1 V,1 , and 2 = 0:15 V,1 . VDD = 1.8 V Vb M2 Vout V in M1 Figure 7.56 (a) Com ute the required value of W=L1 . (b) if W=L2 = 20=0:18, calculate the requir ed value of VB .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 360 (1) 360 Cha . 7 CMOS Am li ers 21. In the stage of Fig. 7.56, M2 has a long length so that 2 1 . Calculate the voltage gain if 1 = 0:1 V,1 , W=L1 = 20=0:18, and ID = 1 mA. 22. The circuit of Fi g. 7.56 is designed for a bias current of I1 with certain dimensions for M1 and M2 . If the width and the length of both transistors are doubled, how does the v oltage gain change? Consider two cases: (a) the bias current remains constant, o r (b) the bias current is doubled. 23. Ex lain which one of the to ologies shown in Fig. 7.57 is referred. VDD Vb M2 Vout V in M1 (a) VDD V in M2 Vout Vb M1 (b) Figure 7.57 24. The CS stage de icted in Fig. 7.58 must achieve a voltage gain of 15 at a bi as current of 0.5 VDD = 1.8 V V in M2 Vout Vb M1 Figure 7.58 mA. If 1 = 0:15 V,1 and 2 = 0:05 V,1 , determine the required value of W=L2 . 25. We wish to design the circuit shown in Fig. 7.59 for a voltage gain of 3. If W=L1 VDD = 1.8 V M2 Vout V in M1 = Figure 7.59 26. (b) Now calculate the voltage gain. (c) Ex lain why this choice of W=L2 yields the maximum gain. 27. The CS stage of Fig. 7.59 must achieve a voltage gain of 5. ( a) If W=L2 = 2=0:18, com ute the required value of W=L1 . (b) What is the maximum al lowable bias current if M1 must o erate in saturation? 20=0:18, determine W=L2 . Assume = 0. In the circuit of Fig. 7.59, W=L1 = 10=0:18 a nd ID1 = 0:5 mA. (a) If = 0, determine W=L2 such that M1 o erates at the edge of saturation.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 361 (1) Sec. 7.6 Cha ter Summary VDD M2 Vout Vb M2 VDD M3 Vout V in M1 V in M1 M3 Vb VDD M2 Vout 361 V in M1 (a) (b) (c) VDD V in M2 Vout Vb M1 M3 Vb V in VDD M2 Vout M1 M3 V in (e) (f) VDD M2 RD Vout M1 (d) Figure 7.60 28. If 6= 0, determine the voltage gain of the stages shown in Fig. 7.60. 29. I n the circuit of Fig. 7.61, determine the gate voltage such that M1 o erates at the edge of saturation. Assume = 0. VDD = 1.8 V RD Vout V in M1 RS Figure 7.61 30. The degenerated CS stage of Fig. 7.61 must rovide a voltage gain of 4 with a bias current of 1 mA. Assume a dro of 200 mV across RS and = 0. (a) If RD = 1 k , determine the required value of W=L. Does the transistor o erate in satura tion for this choice of W=L? (b) If W=L = 50=0:18, determine the required value of RD . Does the transistor o erate in saturation for this choice of RD ? 31. Co nsider a degenerated CS stage with 0. Assuming gm rO 1, calculate the voltage g ain of the circuit. 32. Calculate the voltage gain of the circuits de icted in F ig. 7.62. Assume = 0. 33. Determine the out ut im edance of each circuit shown in Fig. 7.63. Assume 6= 0. 34. The CS stage of Fig. 7.64 carries a bias current of 1 mA. If RD = 1 k and = 0:1 V,1 , com ute the required value of W=L for a g ate voltage of 1 V. What is the voltage gain of the circuit?

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 362 (1) 362 VDD M2 Vout V in M1 M3 V in M1 M3 (a) (b) Cha . 7 VDD M2 RD Vout V in M1 CMOS Am li ers VDD RD Vout M2 I1 Vb (c) VDD RD Vout V in M2 M1 Vb Vb V in VDD M2 M1 Vout M3 (d) (e) Figure 7.62 35. Re eat Problem 34 with = 0 and com are the results. 36. An adventurous stud ent decides to try a new circuit to ology wherein the in ut is a lied to the dr ain and the out ut is sensed at the source (Fig. 7.65). Assume 6= 0, determine the voltage gain of the circuit and discuss the result. 37. In the common source stage de icted in Fig. 7.66, the drain current of M1 is de ned by the ideal curre nt source I1 and remains inde endent of R1 and R2 (why?). Su ose I1 = 1 mA, RD = 500 , = 0, and C1 is very large. (a) Com ute the value of W=L to obtain a vol tage gain of 5. (b) Choose the values of R1 and R2 to lace the transistor 200 m V away from the triode region while R1 + R2 draws no more than 0.1 mA from the s u ly. (c) With the values found in (b), what ha ens if W=L is twice that found in (a)? Consider both the bias conditions (e.g., whether M1 comes closer to the triode region) and the voltage gain. 38. Consider the CS stage shown in Fig. 7. 67, where I1 de nes the bias current of M1 and C1 is very large. (a) If = 0 and I 1 = 1 mA, what is the maximum allowable value of RD ? (b) With the value found i n (a), determine W=L to obtain a voltage gain of 5. 39. The common gate stage sh own in Fig. 7.68 must rovide a voltage gain of 4 and an in ut im edance of 50 . If ID = 0:5 mA, and = 0, determine the values of RD and W=L. 40. Su ose in Fi g. 7.68, ID = 0:5 mA, = 0, and Vb = 1 V. Determine the values of W=L and RD for an in ut im edance of 50 and maximum voltage gain (while M1 remains in saturati on). 41. A CG stage with a source resistance of RS em loys a MOSFET with 0. Ass uming gm rO , calculate the voltage gain of the circuit.

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 363 (1) Sec. 7.6 Cha ter Summary VDD R out V in M2 M1 Vb V in R out M1 M2 I1 (b) 363 Vb (a) R out Vb M2 VDD V in M2 Vb V in M1 (c) M1 M3 M3 R out (d) Figure 7.63 VDD = 1.8 V RD Vout V in M1 Figure 7.64 V in VB M1 Vout RS Figure 7.65 42. The CG stage de icted in Fig. 7.69 must rovide an in ut im edance of 50 and an out ut im edance of 500 . Assume = 0. (a) What is the maximum allowable val ue of ID ? (b) With the value obtained in (a), calculate the required value of W =L. (c) Com ute the voltage gain. 43. The CG am li er shown in Fig. 7.70 is biased by means of I1 = 1 mA. Assume = 0 and C1 is very large. (a) What value of RD laces the transistor M1 100 mV away from the triode region? (b) What is the requ ired W=L if the circuit must rovide a voltage gain of 5 with the value of RD ob tained in (a)?

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 364 (1) 364 Cha . 7 VDD = 1.8 V R1 C1 M1 V in R2 I1 C1 RD Vout CMOS Am li ers Figure 7.66 VDD = 1.8 V R1 C1 M1 V in I1 C1 RD Vout Figure 7.67 VDD = 1.8 V RD Vout V in M1 Vb Figure 7.68 VDD = 1.8 V RD Vout V in M1 Figure 7.69 44. Determine the voltage gain of each stage de icted in Fig. 7.71. Assume = 0. 45. Consider the circuit of Fig. 7.72, where a common source stage (M1 and RD1 ) is followed by a common gate stage (M2 and RD2 ). (a) Writing vout =vin = vX =v in vout =vX and assuming = 0, com ute the overall voltage gain. (b) Sim lify the result obtained in (a) if RD1 ! 1. Ex lain why this result is to be ex ected. 46 . Re eat Problem 45 for the circuit shown in Fig. 7.73. 47. Assuming = 0, calcu late the voltage gain of the circuit shown in Fig. 7.74. Ex lain why this stage is not a common gate am li er.

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 365 (1) Sec. 7.6 Cha ter Summary 365 VDD = 1.8 V RD Vout C1 V in M1 I1 Figure 7.70 VDD M2 Vout V in M1 RS Vb V in (a) VDD M2 RD Vout M1 Vb V in M1 RS VDD M2 Vout Vb R1 (c) (b) VDD Vb M3 M2 RD Vout V in M1 (d) V in Vb RD I1 (e) VDD M1 M2 Vout Vb Figure 7.71 48. Calculate the voltage gain of the stage de icted in Fig. 7.75. Assume = 0 a nd the ca acitors are very large. 49. The source follower shown in Fig. 7.76 is biased through RG . Calculate the voltage gain if W=L = 20=0:18 and = 0:1 V,1 . 50. We wish to design the source follower shown in Fig. 7.77 for a voltage gain of 0.8. If W=L = 30=0:18 and = 0, determine the required gate bias voltage. 51 . The source follower of Fig. 7.77 is to be designed with a maximum bias gate vo ltage of 1.8 V. Com ute the required value of W=L for a voltage gain of 0.8 if = 0. 52. The source follower de icted in Fig. 7.78 em loys a current source. Det ermine the values of I1 and W=L if the circuit must rovide an out ut im edance less than 100 with VGS = 0:9 V. Assume = 0. 53. The circuit of Fig. 7.78 must e xhibit an out ut im edance of less than 50 with a ower budget of 2 mW. Determin e the required value of W=L. Assume = 0.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 366 (1) 366 VDD R D1 M2 M1 R D2 Vout Vb X V in Cha . 7 CMOS Am li ers Figure 7.72 VDD R D2 V in M1 M2 R D1 X Vout Vb Figure 7.73 VDD I1 Vout RG V in M1 Figure 7.74 54. We wish to design the source follower of Fig. 7.79 for a voltage gain of 0.8 with a ower budget of 3 mW. Com ute the required value of W=L. Assume C1 is ve ry large and = 0. 55. Determine the voltage gain of the stages shown in Fig. 7. 80. Assume 6= 0. 56. Consider the circuit shown in Fig. 7.81, where a source fo llower (M1 and I1 ) recedes a common gate stage (M2 and RD ). (a) Writing vout =vin = vX =vin vout =vX , com ute the overall voltage gain. (b) Sim lify the result obtained in (a) if gm1 = gm2 . Design Problems In the following roblems, unless otherwise stated, assume = 0. 57. Design the CS stage shown in Fig. 7.82 for a voltage gain of 5 and an out ut im edance of 1 k . Bias the transistor so that it o erates 100 mV away from the triode region. Assume the ca acitors are very l arge and RD = 10 k . 58. The CS am li er of Fig. 7.82 must be designed for a volta ge gain of 5 with a ower budget of 2 mW. If RD ID = 1 V, determine the required value of W=L. Make the same assum tions

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BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 367 (1) Sec. 7.6 Cha ter Summary VDD RD Vout C1 R3 R4 M1 R1 CB R2 367 V in Figure 7.75 RG V in 50 k Ω VDD = 1.8 V M1 Vout 1 kΩ RS Figure 7.76 VDD = 1.8 V V in 500 Ω M1 Vout RS Figure 7.77 VDD = 1.8 V V in M1 Vout I1 Figure 7.78 as those in Problem 57. 59. We wish to design the CS stage of Fig. 7.82 for maxi mum voltage gain but with W=L 50=0:18 and a maximum out ut im edance of 500 . De termine the required current. Make the same assum tions as those in Problem 57. 60. The degenerated stage de icted in Fig. 7.83 must rovide a voltage gain of 4 with a ower budget of 2 mW while the voltage dro across RS is equal to 200 mV . If the overdrive voltage of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5 of the allocated ower, design the circuit. Make th e same assum tions as those in Problem 57. 61. Design the circuit of Fig. 7.83 f or a voltage gain of 5 and a ower budget of 6 mW. Assume

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 368 (1) 368 VDD = 1.8 V V in M1 C1 Vout I1 50 Ω Cha . 7 CMOS Am li ers RL Figure 7.79 VDD V in M1 Vout RS Vb M2 (a) (b) VDD V in M1 Vout Vb M2 RS (c) VDD V in M1 Vout M2 VDD V in R1 M2 R2 (d) (e) VDD VDD V b2 V b1 Vb M3 M2 Vout V in M1 (f) M1 Vout M3 M1 Vout V in M2 Figure 7.80 VDD RD Vout V in M1 X M2 I1 Vb Figure 7.81 the voltage dro across RS is equal to the overdrive voltage of the transistor a nd RD = . 62. The circuit shown in Fig. 7.84 must rovide a voltage gain of 6, w ith CS serving as a low im edance at the frequencies of interest. Assuming a ow er budget of 2 mW and an in ut im edance of 20 k , design the circuit such that M1 o erates 200 mV away from the triode region. Select the values of C1 and CS s o that their im edance is negligible at 1 MHz. 63. In the circuit of Fig. 7.85, M2 serves as a current source. Design the stage for a voltage 200

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 369 (1) Sec. 7.6 Cha ter Summary VDD = 1.8 V RG C1 V in M1 RD C2 Vout 369 Figure 7.82 VDD = 1.8 V R1 C1 M1 V in R2 RS RD Vout Figure 7.83 VDD = 1.8 V R1 C1 M1 V in RS CS RD Vout Figure 7.84 VDD = 1.8 V Vb M2 Vout V in M1 Figure 7.85 gain of 20 and a ower budget of 2 mW. Assume = 0:1 V,1 for both transistors an d the maximum allowable level at the out ut is 1.5 V (i.e., M2 must remain in sa turation if Vout 1:5 V). 64. Consider the circuit shown in Fig. 7.86, where CB i s very large and n = 0:5 = 0:1 V,1 . (a) Calculate the voltage gain. (b) Design the circuit for a voltage gain of 15 and a ower budget of 3 mW. Assume RG 10rO1 jjrO2 and the dc level of the out ut must be equal to VDD =2. 65. The CS stage of Fig. 7.87 incor orates a degenerated PMOS current source. The degeneration mu st raise the out ut im edance of the current source to about 10rO1 such that the voltage gain remains nearly equal to the intrinsic gain of M1 . Assume = 0:1 V ,1 for both

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 370 (1) 370 Cha . 7 VDD = 1.8 V M2 RG Vout V in M1 CMOS Am li ers CB Figure 7.86 VDD = 1.8 V RS Vb M2 Vout V in M1 Figure 7.87 transistors and a ower budget of 2 mW. (a) If VB = 1 V, determine the values of W=L2 and RS so that the im edance seen looking into the drain of M2 is equal to 1 0rO1 . (b) Determine W=L1 to achieve a voltage gain of 30. 66. Assuming a ower bu dget of 1 mW and an overdrive of 200 mV for M1 , design the circuit shown in Fig . 7.88 for a voltage gain of 4. VDD = 1.8 V M2 Vout V in M1 Figure 7.88 67. Design the common gate stage de icted in Fig. 7.89 for an in ut im edance of 50 voltage gain of 5. Assume a ower budget of 3 mW. VDD = 1.8 V RD Vout V in M1 I1 and a Figure 7.89

¡

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 371 (1) Sec. 7.6 Cha ter Summary 371 68. Design the circuit of Fig. 7.90 such that M1 o erates 100 mV away from the t riode region while roviding a voltage gain of 4. Assume a ower budget of 2 mW. VDD = 1.8 V RD Vout V in M1 RS Figure 7.90 69. Figure 7.91 shows a self biased common gate stage, where RG VDD = 1.8 V RD V out V in M1 RS RG CG 10RD and CG serves as a Figure 7.91 low im edance so that the voltage gain is still given by gm RD . Design the circ uit for a ower budget of 5 mW and a voltage gain of 5. Assume RS 10=gm so that the in ut im edance remains a roximately equal to 1=gm . 70. Design the CG stag e shown in Fig. 7.92 such that it can accommodate an out ut swing of 500 VDD = 1.8 V RD V out V in M1 R1 RS R2 Figure 7.92 mV , i.e., Vout can fall below its bias value by 250 mV without driving M1 int o the triode region. Assume a voltage gain of 4 and an in ut im edance of 50 . S elect RS 10=gm and R1 + R2 = 20 k . (Hint: since M1 is biased 250 mV away from t he triode region, we have RS ID + VGS , VTH + 250 mV = VDD , ID RD .) 71. Design the source follower de icted in Fig. 7.93 for a voltage gain of 0.8 and a ower budget of 2 mW. Assume the out ut dc level is equal to VDD =2 and the in ut im edance exceeds 10 k . 72. Consider the source follower shown in Fig. 7.94. The c ircuit must rovide a voltage gain of

¡

¡

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 372 (1) 372 Cha . 7 CMOS Am li ers VDD = 1.8 V RG V in M1 Vout RS Figure 7.93 VDD = 1.8 V RG V in X RS M1 C1 Vout 50 Ω RL Figure 7.94

Figure 7.95

I1 Vout W ( (1 L V in C1 1 kΩ M1 Figure 7.96 (a) Using hand calculations, determine W=L1 such that gm1 = 100 ,1 .

with a ower budget of 3 mW, a voltage gain of 0.9, and a minimum allowable out ut of 0.3 V (i.e., M2 must remain in saturation if VDS 2 0:3 V). Assuming = 0: 1 V,1 for both transistors, design the circuit. SPICE Problems In the following roblems, use the MOS models and source/drain dimensions given in A endix A. As sume the substrates of NMOS and PMOS devices are tied to ground and VDD , res ec tively. 74. In the circuit of Fig. 7.96, I1 is an ideal current source equal to 1 mA. VDD = 1.8 V 10 k Ω

0.8 at the t o VDD

at 100 MHz while consuming 3 mW. Design the circuit such that the dc voltage node X is equal to VDD =2. Assume the in ut im edance exceeds 20 k . 73. In source follower of Fig. 7.95, M2 serves as a current source. The circuit mus erate = 1.8 V V in M1 Vout Vb M2

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 373 (1) Sec. 7.6 Cha ter Summary 373 (b) Select C1 for an im edance of 100 ( 1 k ) at 50 MHz. (c) Simulate the circui t and obtain the voltage gain and out ut im edance at 50 MHz.. (d) What is the c hange in the gain if I1 varies by 20? 75. The source follower of Fig. 7.97 em loys a bias current source, M2 . M1 V in VDD = 1.8 V 20 0.18 Vout M2 0.8 V 10 0.18 Figure 7.97 (a) What value of Vin laces M2 at the edge of saturation? (b) What value of Vin laces M1 at the edge of saturation? (c) Determine the voltage gain if Vin has a dc value of 1.5 V. (d) What is the change in the gain if Vb changes by 50 mV? 7 6. Figure 7.98 de icts a cascade of a source follower and a common gate stage. A ssume Vb 1:2 V and W=L1 = W=L2 = 10 m=0:18 m. VDD 1 kΩ = Vout V in M1 M2 1 mA Vb Figure 7.98 (a) Determine the voltage gain if Vin has a dc value of 1.2 V. (b) Verify that t he gain dro s if the dc value of Vin is higher or lower than 1.2 V. (c) What dc value at the in ut reduces the gain by 10 with res ect to that obtained in (a)? 7 7. Consider the CS stage shown in Fig. 7.99, where M2 o erates as a resistor. M2 VDD = 1.8 V W2 0.18 Vout V in M1 10 0.18 Figure 7.99 (a) Determine W2 such that an in ut dc level of 0.8 V yields an out ut dc level of 1 V. What is the voltage gain under these conditions? (b) What is the change in the gain if the mobility of the NMOS device varies by 10? Can you ex lain this

¡

result using the ex ressions derived in Cha ter 6 for the transconductance? .

100 and com are the sensitivities to the mobility. Re eat Problem 77 for the circuit illustrated in Fig. VDD = 1.8 V W2 0.cls v. 2006] June 30. 7.18 Vout 10 0. 2007 at 13:42 374 (1) 374 Cha .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.100 . 7 CMOS Am li ers 78.18 M2 V in M1 Figure 7.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Called “analog com uters. 2006] June 30. integration). develo ing o am based circuits that erform inte resting and useful functions. 375 O Am Nonidealities DC Offsets In ut Bias Currents S eed Limitations Finite In ut and Out ut Im edances Nonlinear O Circuit Am Circuits Precision Rectifier Logarithmic Am lifier Square Root ¡ ¡ ¡ ¡ . and another that controlled the ow—somewhat simi lar to MOSFETs.g. The outline is shown below.. well before the inve ntion of the transistor and the integrated circuit. 2007 at 13:42 375 (1) 8 O erational Am li er As A Black Box The term “o erational am li er” (o am ) was coined in the 1940s. arriving at the equivalent circuit de icted in Fig.. 8.” “differentiators. thus form ing systems whose behavior followed a given differential equation. the analo to digital converter(s) u sed in digital cameras often em loy o am s. Since each o am im leme nted a mathematical o eration (e. a late that collected them. In the cell hone studied in Cha ter 1. integrated o am s serve as building blocks in (active) lters.2 Shown in Fig. o am s ty ically have two out uts that vary by equal and o osite amounts. Vin1 and Vin2 are called the “noninverting” and “i nverting” in uts.1) 1 Vacuum tubes were am lifying devices consisting of a lament that released elect rons.cls v.” etc.1 General Considerations The o erational am li er can be abstracted as a black box having two in uts and on e out ut. Vin2 : (8.1(b). the o am symbol distinguishes between the two in uts by the lus and minus sign.” such circuits were used to study the stability of differential equatio ns that arose in elds such as control or ower systems. 2 In modern integrated circuits. General Conce ts O Am Pro erties Linear O Am Circuits Noninverting Am lfier Inverting Am lifier Integrator and Differentiator Voltage Adder 8. In this cha ter. O am s realized by vacuum t ubes1 served as the core of electronic “integrators. The voltage gain is denoted by A0 : Vout = A0 Vin1 . O am s nd wide a lication in today’s discrete and integrated electronics. Similarly. for exam le.1(a). res ectively. the term “o erational am li er” was born. we study the o era tional am li er as a black box. We view the o am as a circuit that am li es the di fference between the two in uts. 8.

1 (a) O am symbol. Vin2 = VA : 0 ¡ ¡ ¡ Figure 8. 8.2(b)]. The ositive slo e (gain) is consistent with the label “noninverti ng” given to Vin1 .A0 Vin2 [Fig. How does the “ideal” o am behave? Such an o am would rovide an in nite voltage gain. 2 V. and in nite s eed. the rst orde r analysis of an o am based circuit ty ically begins with this idealization. e. revealing a negative slo e and hence an “inverting” behavior. Vout = .. 2006] June 30. 2007 at 13:42 376 (1) 376 V in1 V in2 Vout Cha . On the other hand. the rinci al ro erty of the o am .e. we have Vout = A0 Vin1 . 8 O erational Am li er As A Black Box Vout V in1 V in2 (a) (b) A 0 (V in1 − V in2 ) It is instructive to lot Vout as a function of one in ut while the other remain s at zero. In fact.. Vout V in1 Vout A0 V in1 V in2 Vout −A 0 Vout V in2 (a) (b) The reader may wonder why the o am has two in uts. 8. characteristics from (a) noninverting and (b) inverting in uts Figure 8. if Vin1 = 0.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Am li er circuits having two in uts are studied in Cha ter 10. they sense the in ut voltage with res ect to ground).g. a zero out ut im edance. 8. obtaining the behavior shown in Fig. With Vin2 = 0. As seen throughout this cha ter. forms the foundation for many c ircuit to ologies that would be dif cult to realize using an am li er having Vout = AVin .2 O am to out ut. . Vin2 . Vout = A0 Vin1 . After all. q uickly revealing the basic function of the circuit. an in nite in ut im edance. (b) equivalent circuit.2(a). the difference between Vin1 and Vin2 in Fig. Since realistic circuits roduce nite out u t swings. We can then consider the eff ect of the o am “nonidealities” on the erformance. The very high gain of the o a m leads to an im ortant observation.1(a) is alwa ys small: out Vin1 . the am li er stage s studied in Cha ters 5 and 7 have only one in ut node (i.

(8. A common mistake is to inter ret Vin1 = Vin2 as if the two termina ls Vin1 and Vin2 are shorted together. It must be borne in mind that Vin1 . Determine the out ut voltage if Vin1 = +1 V and A0 = 1000. along with the circuitry around it. Exam le 8.3 is called a “unity gain” buffer. the o am .1 The circuit shown in Fig. brings Vin1 and Vin2 close to each other. we may say Vin1 = Vi n2 if A0 = 1. Vin2 becomes only in nitesimally small as A0 ! 1 but cannot be assumed exactly equal t o zero. ¡ . 8. Note that the out ut is tied to the inverting in ut.2) In other words. Following the above idealization.

2 O Am Based Circuits In this section. In each case.cls v. we study a number of circuits that utilize o am s to rocess a nalog signals. VCC V in1 V in2 VEE Vout = A0 Vin . 2007 at 13:42 377 (1) Sec. the gain a roaches unity as A0 becomes large. we rst assume an ideal o am to understand the unde rlying rinci les and subsequently examine the effect of the nite gain on the er formance. VEE and VCC .4 to ex licitly indicate th e su ly voltages.5) 1000. 8. in which case VEE = 0.4) Vout = A0 : Vin 1 + A0 As ex ected. we write Vout = A0 Vin1 . Figure 8. Vin2 That is. (8.9999? O am s are sometimes re resented as shown in Fig. Solution If the voltage gain of the o am were in nite. ¡ ¡ ¡ ¡ ¡ ¡ . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A0 = Vin = 1 V. Vin2 is small com ared to Vin an d Vout . For exam le. hence the term “unity gain buffer.3 Unity gain buffer.2 O Am Based Circuits A 0 = 1000 +1V 377 V in Vout Figure 8. and Vout = 0:999 V.3) (8. (8. Vout : 8. Exercise What value of A0 is necessary so that the out ut voltage is equal to 0.4 O am with su ly rails. an o am may o erate between grou nd and a ositive su ly.” For a nite gai n. In this exam le. the difference between the two in uts would be zero and Vout = Vin . Vin1 . Indeed. 8.

.

with no effect on the gain if the o am is ideal. e.. a much more recise gain (e.000) is required. If R1 =R2 ! 0.cls v. if R2 a roaches zero.5. Vin2 = R R2 R Vout : 1+ 2 Since a high o am gain translates to a small difference between Vin1 and Vin2 . O am based c ircuits can rovide such recision. this case in fact reduces to the unity gain buffer of Fig. 1+ 2 and hence (8. 8. If R1 =R2 ! 1. we have Vout =Vin ! 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g.5 Noninverting am li er. Study the noninverting am li er for two extreme cases: R1 =R2 Exam le 8. A/ D converters).3 because the ideal o am draws no current at its in uts.2 Solution = 1 and R1 =R2 = 0. if R1 and R2 in crease by 20. 2007 at 13:42 378 (1) 378 Cha . Shown in Fig . The idea of creating de endence on only th e ratio of quantities that have the same dimension lays a central role in circu it design.6) Vin1 Vin2 R R2 R Vout . 8. the voltage gain de ends on only the ratio of the resistors. 8. However. 20. R1 =R2 remains constant. as de icted in Fig..1 Noninverting Am li er Recall from Cha ters 5 and 7 that the voltage gain of am li ers ty ically de ends on the load resistor and other arameters that may var y considerably with tem erature or rocess. if R2 a roaches in nity. 8 O erational Am li er As A Black Box 8. the circuit is called a “noninverting am li er. 8.2. the voltage gain itsel f may suffer from a variation of.9) Due to the ositive gain.” Interesting ly. Illustrated in Fig.8) Vout (8. say. yielding a zero dro across R1 1 + R1 : Vin R2 ¡ ¡ . the noninverting am li er consists of an o am and a voltage divider that returns a fraction of the out ut voltage to the inverting in ut: V in1 A0 V in V in2 R1 R2 Vout Figure 8.g. this occurs because the circuit reduces to the o am itself...3 As a result. Of cours e.g. e.6(b).g.7) (8. Resistor R1 s im ly loads the out ut node.6(a). with no fraction of the out ut fed back to the in ut. we have (8. 2006] June 30. we note that Vout =Vin ! 1. in some a lications (e. 2.

3 Variation with rocess means the circuits fabricated in different “batches” exhibi t somewhat different characteristics. .and hence Vin2 = Vout .

2 O Am Based Circuits 379 Vout V in R1 R2 = 0 (a) (b) Vout V in R1 R2 = Figure 8. R2 =R1 + R2 can be factored from the deno ..11) indicates th a small error in the value of Vout =Vin .00 but the R1 and mismat ch of 5% (i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10) Vout = A0 (8. 2007 at 13:42 379 (1) Sec. 9) if A0 R2 =R1 + R2 1. ¡ the “o en loo ” gain and the latter the at the nite gain of the o am creates If much greater than unity. the term A0 minator to ermit the a roximation 1 + “closed loo ” gain.6): (8.cls v.6 Noninverting am li er with (a) zero and (b) in nite value for R2 . 2006] June 30. 8.e.” the term 1 + R1 =R2 =A0 must be minimized according to each a lication’s requirements. R1 = 1 0:05R2 ).12) Vin R2 R2 A0 Called the “gain error.1 1 . Vin2 A0 = Vout . 8. Exercise Su ose the circuit is designed for a nominal gain of 2. this result reduces to (8. What is the actual voltage gain? R2 suffer from a Vin1 . we write ¡ ¡ ¡ nite gain of the o am . and substitute for Vin2 from (8. we call the former Vout 1 + R1 1 . To avoid confusion between the gain of the o am . for 1: Let us now take into account the n in Fig.1(b). a nd the gain of the overall am li er.11) Vin 1 + R2 A0 : R1 + R2 As ex ected. Vout =Vin . A0 . Equation (8. 1 + R1 1 : (8. Based on the model show .

.

Fo r a nominal gain of 5. we have 1 + R1 =R2 Solution . or (b) 50.Exam le 8.3 A noninverting am li er incor orates an o am having a gain of 1000. Determine th e gain error if the circuit is to rovide a nominal gain of (a) 5.

obtaining a gain error of: (8.13) .1 1 + R1 A = 0:5: R2 0 = 5.

then . 2007 at 13:42 380 (1) 380 Cha . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if 1 + R1 =R2 = 50. 8 O erational Am li er As A Black Box On the other hand.cls v.

8.2.15) Vout = . the I/O im edances are deriv ed in Problem 7. Vin2 ! 0. (c) analogy wit Exercise Re eat the above exam le if the o ¡ am has a gain of 500. 8. node X bears a zero otential even though it is not shorted to ground.R1 : Vin R2 (8. R1 R2 X Vout V in V in Virtual Ground (a) (b) V in R2 R2 X R1 Vout A R2 R1 (c) B Figure 8.16) owing in resistors. th en a nite out ut swing translates to Vin1 . With an ideal o am . the “inverting am li er” incor orates an o am along with resistors R1 and R2 while the noninverting in ut is grounded. (b) currents h a seesaw. the noninverting am li er exhibits an in nite in ut im edance and a zero out ut im edance. Recall from Section 8.7(a). a higher closed loo gain inevitably suffers from less accuracy. For this reason.7(b)]..” Under this condition. which must then ow through R1 if the o a m in ut draws no current [Fig. . the entire in ut voltage a ears acros s R2 . node X is cal led a “virtual ground.e. 8. i.1 that if the o am gain is in nite. 0 . For a nonideal o am . Since the left terminal of R1 remains a t zero and the right terminal at Vout . Vout = Vin R1 R2 yielding (8.14) In other words.7 (a) Inverting am li er.2 Inverting Am li er De icted in Fig. roducing a current of Vin =R2 .R 1 1 + R1 A = 5: 2 0 (8.

8 Inverting am li er.g. 8. This behavior is similar to a seesaw [Fig. Moreover . in F ig. then ne ither Vin =R2 nor Vout =R1 would accurately re resent the currents owing through R2 and R1 . That is. 1 1 + R2 (8.7(c)]. Vout R2 V in R1 Figure 8.. 8. 8. thereby ex eriencing only small variations with tem erature and rocess. 8. If the inverting in ut of the o am were not near zero otential. 8.7(b) would force to ground all of the current owing through R2 . It is im ortant to understand the role of the virtual ground in this cir cuit. 2007 at 13:42 381 (1) Sec.2 O Am Based Circuits 381 Due to the negative gain. Let us now com ute the closed loo gain of the inverting am li er with a nite o am gain. we o btain (8.7(b).A0 VX : Equating the currents through R2 and R1 and substituting .7(a) that the currents owing t hrough R2 and R1 are given by Vin . the circuit is called the “inverting am li er.R Vout = .VX =R2 and VX .” As with its noninverting counter art. In contrast to the noninverting am li er.18) 1 1 1 + R2 : 2 R1 + A0 R1 Factoring R2 =R1 from the denominator and assuming 1 + R 1 =R2 =A0 =. the to ology of Fig.19) 1 + 1 Vin A0 R1 A0 ¡ ¡ ¡ ¡ . 2006] June 30. res ectively.8. Vout = A0 Vin1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. allowing dis l acement of oint A to be “am li ed” (and “inverted”) at oint B . The above develo ment al so reveals why the virtual ground cannot be shorted to the actual ground.17) (8.Vout =A0 for VX . Vin2 = . This trade off sometimes makes this am li er less attractive than its non inverting counter art. yielding Vout = 0. Such a short in Fig. It is interesting to note that the inverting am li er can also be drawn as shown in Fig. res ectively. wh ere the oint between the two arms is “ inned” (e. Vout =R1 .7(a) exhibits an in ut im edance equal to R2 —as can be seen from the in ut current. the gain of this circuit is given by the ratio of the two resistors. We note from Fig. dis laying a similarity with the noninverting ci rcuit but with the in ut a lied at a different oint. Vin =R2 . does not move).cls v. 8. a lower R2 results in a greater gain but a smaller in ut im edance. 8.

20) .(8.

Vout . 1 1 + R1 : Vin R2 A0 R2 1. ¡ . Note that the gain error ex ression is the same for noninverting and inverting am li ers. a higher closed loo gain ( .R1 =R2 ) is accom anied with a greater gain error. we have (8.21) As ex ected. R1 1 .

We have R1 = 4 2 . and an in ut im edance of at least 10 k . Exam le 8. 8 O erational Am li er As A Black Box Design the inverting am li er of Fig.7(a) for a nominal gain of 4. 2006] June 30.cls v.4 Solution Since both the nominal gain and the gain error are given. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 382 (1) 382 Cha . we must rst determine t he minimum o am gain. a gain error of 0:1.

26) Exercise Re eat the above exam le for a gain error of 1% and com are the results. we choose: (8.22) (8.27) . 8. (8. Vin Z2 (8. How accurate is this assum tion? With A0 = 5000.9 Circuit with general im edances around the o am .2. 8 .3 Integrator and Differentiator Our study of the in verting to ology in revious sections has assumed a resistive network around the o am . In general. Vout . our assum tion leads to an error of about 0:08—an acce table val ue in most a lications. it is ossible to em loy com lex im edances instead (Fig.9).Vout =5000 . That is.16). In analogy with (8.25) (8.4Vin =5000. In the above exam le. the virtual ground ex erien ces a voltage of . we can write Z1 Z2 Vout V in Figure 8.23) A0 = 5000: Since the in ut im edance is a roximately equal to R2 .24) R2 = 10 k R1 = 40 k : (8. we assumed the in ut im edance is a roximately equal to R 2 .1 RR1 + 1 = 0:1: A0 R2 Thus. yielding an in ut current of Vin + 4Vin =5000=R1. Z1 .

This can also be seen in the time domain.10). Integrator Su ose in Fig.2 O Am Based Circuits 383 where the gain of the o am is assumed large. 8.1 and Z2 = R1 . 2007 at 13:42 383 (1) Sec. Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.28) (8.C dVout 1 R1 dt and hence (8. R 1C Z 1 1 Vin dt: (8. two i nteresting functions result. Z1 is a ca acitor a nd Z2 a resistor (Fig. Equating the currents owing throu gh R1 and C1 gives Vout Vin f Figure 8.31) ¡ ¡ ¡ .9. With an ideal o am . Vin = .30) Vout = . we have C1 R1 X Vout V in = Figure 8. Z1 C1 s.R 1 s: C 1 1 Providing a ole at the origin.cls v. 8. If Z1 or Z2 is a ca acitor. Vout = . C1 s Vin R1 1 (8.29) = .10 Integrator. 8.11 Frequency res onse of integrator.4 the circuit o erates as an integrator (and a lo w ass lter). That is. 2006] June 30.11 lots the magnitude of Vout =Vin as a function of frequ ency.

¡ . This is to be ex ected: the ca acitor im edance becomes very larg e at low frequencies. a roaching an o en circuit and reducing the circuit to th e o en loo o am . Today. electronic integrators nd usage in analog lters. control systems. 8. Exam le 8. Assume a zero ini tial condition across C1 and an ideal o am .5 Plot the out ut waveform of the circuit shown in Fig. integrators or iginally a eared in analog com uters to simulate differential equations. 4 Pole frequencies are obtained by setting the denominator of the transfer funct ion to zero. and many other a lications.12(a). As mentioned at the beginning of the cha ter.Equation (8.29) indicates that Vout =Vin a roaches in nity as the in ut frequency goes to zero.

33) (Note that the out ut waveform becomes “shar er” as R1 C1 decreases. Thus. 2007 at 13:42 384 (1) 384 Cha . the voltage across the .) When Vin retur ns to zero. When the in ut jum s from 0 to V1 . R 1C Vin dt 1 1 1 = . a constant current equal to V1 =R1 begins to ow through the resistor and hence the ca acitor. 8 O erational Am li er As A Black Box V1 0 V in Tb C1 V1 0 I C1 V1 R1 0 0 V in Tb R1 X Vout V1 R1 Vout − 0 V1 R 1C1 (b) − V1 T b R 1C1 t (a) Figure 8.12(b)]: Solution Vout = . 2006] June 30.12 (a) Integrator with ulse in ut. RVC t 0 t Tb : 1 1 Z (8.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. so do the currents through R1 and C1 . 8 . (b) in ut and out ut waveforms.32) (8. forcing the right late voltage of C1 to fall linearly with time while its left late is inned at zero [Fig.

8.32) occurs because the left late of C1 i s inned at zero. 8. The above exam le demonstrates the role of the virtual ground in the integrator. Vout =R1 . let us com are the integrator with a rst order RC lter in terms of their ste res onse. we have Vin . 8.34) ¡ ca acitor and hence Vout remain equal to . On the other hand. the i ntegrator forces a constant current (equal to V1 =R1 ) through the ca acitor. Denoting the otential of the virtual ground nod e in Fig. leading to an increasingly slower voltage variation across C1 . As illustrated in Fig.V1 Tb =R1 C1 under the in ut ulse) thereafter. We now examine the erforma nce of the integrator for A0 1. Vout 1 R1 C1 s (8. ( ro ortional to the area . We may therefore consider the RC lter as a “ assive” a roximation of the integr ator. VX = VX .Exercise Re eat the above exam le if V1 is negative. To gain more insight.13( b) becomes slow enough to be a roximated as a ram .10 with VX .13. the ex onential res onse of Fig. In fact. The ideal integration ex ressed by (8. for a large R1 C1 roduct. which decr eases as Vout rises. the RC lter creates a current equal to Vin .

14 Sim le low ass lter.14 contains a ole at . RX Vout CX V in Figure 8.37) Such a circuit is sometimes called a “lossy” integrator to em hasize the nonideal ga in and ole osition.cls v.36) 1 + 1 + 1 R C s . Vin 1 1 A0 A0 revealing that the gain at s = 0 is limited to A0 (rather than in nity) and the ole frequency has moved from zero to s = A +. Determine RX and CX such that this circuit exhibits the same ol e as that of the above integrator. and V VX = .1R C : 0 1 1 1 (8. Exam le 8. 2007 at 13:42 385 (1) Sec.1 (8.6 Recall from basic circuit theory that the RC lter shown in Fig.2 O Am Based Circuits C1 385 V1 0 V in R1 X Vout V1 R1 0 V1 V in R1 Vout V 1 − V out R1 C1 Figure 8. ¡ ¡ ¡ .35) Thus. 8.1=RX CX . Vout = . 8.out : A 0 (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13 Com arison of integrator with and RC circuit. 2006] June 30.

38).38) RX and CX is arbitrary so long as their roduct satis es (8.37).Solution From (8. . An interesting RX = R1 CX = A0 + 1C1 : (8.39) (8.40) It is as if the o am “boosts” the value of C1 by a factor of A0 + 1. RX CX = A0 + 1R1 C1 : The choice of choice is (8.

the circuit acts as a differentiator (and a hig h ass lter).42) Exhibiting a zero at the origin. Vout = .R1 C1 dVin : dt Exam le 8. Z1 is a resistor and Z2 a ca acitor (Fig. R1 1 Vin C1 s = .9.7 Plot the out ut waveform of the circuit shown in Fig. .cls v.41) (8. we have R1 C1 V in X Vout Figure 8. Vin = 0 and Vout = 0 (why?).43) Vout = . 2006] June 30. 2007 at 13:42 386 (1) 386 Cha . dt 1 arriving at (8. 8 O erational Am li er As A Black Box Exercise What value of RX is necessary if CX = C1 ? Differentiator If in the general to ology of Fig.16 Frequency res onse of differentiator.17(a) assuming an ideal o am . 8.16 lots the magnitude of Vout =Vin as a function of frequ ency. 8.R1 C1 s: (8.15 Differentiator. we can equate the currents owing through C1 and R1 : Vout Vin R 1 C1 f Figure 8.15). Figure 8. VR .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an im ulse of cu rrent ows through C1 because the o am maintains VX constant: Solution Iin = C1 dVin dt (8.45) ¡ ¡ . From a time domain ers ective.44) At t = 0. When Vin jum s to V1 . 8. out C1 dVin = . (8.

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cls v. At current in C1 : (8.46) Vout = . (b) in ut and out ut waveforms.52) We can therefore say that the circuit generates an im ulse of current C1 V1 t and “am li es” it by R1 to roduce Vout . Exercise = C1 V1 t: The current ows through R1 .17 (a) Differentiator with ulse in ut.47) (8. of course.2 O Am Based Circuits V1 0 387 V in I C1 R1 V1 0 0 Tb C1 V in Tb I in X Vout Vout 0 0 (a) (b) t Figure 8.51) (8. again creating an im ulse of Iin = C1 dVin dt = C1 V1 t: (8.17(b) de icts the result.Iin R1 = .Iin R1 = R1 C1 V1 t: (8. (8.48) t = Tb.50) It follows that Vout = . 8. the out ut exhibits neithe r an in nite height (limited by the su ly voltage) nor a zero width (limited by t he o am nonidealities).R1 C1 V1 t: Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49) (8. generating an out ut given by ¡ ¡ . 2007 at 13:42 387 (1) Sec. In reality. Vin returns to zero. 2006] June 30.

In the ideal differentiator. In the RC lter. It is instructive to com are the o eration of the differentiator with that of it s “ assive” counter art (Fig. on the other hand.Plot the out ut if V1 is negative. 8. node X is not “ inned.” thereby following the in ut chang e at t = 0 and limiting the initial current in the circuit to V1 =R1 . .18). the virtual ground node ermits the in ut to change the voltage across C1 instantaneously.

A0 + 1 : RC 1 1 (8.15 gives gain.Vout =A0 for VX .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the be viewed as an a roximation of the ideal differentiator.18 Com arison of differentiator and RC circuit.R1C1 s Vin 1 + 1 + R1 C1 s : A0 A0 In contrast to the ideal differentiator. the circuit contains a ole at (8.19 and choo Let us now study the differentiator with a nite o am or and resistor currents in Fig.54) s = . Vin . VX = VX .8 Determine the transfer function of the high ass lter shown in Fig. 8 O erational Am li er As A Black Box C1 V in I in X Vout 0 V1 V in C1 X R1 V1 Vout (a) (b) Figure 8. R1 V1 0 ¡ assive circuit can . 8. Equating the ca acit If the decay time constant. Vout : 1 R1 C1 s Substituting . we have (8. 8. 2007 at 13:42 388 (1) 388 Cha .cls v. 2006] June 30. is suf ciently small.53) Vout = . R1 C1 .55) Exam le 8.

Solution The ca acitor and resistor o erate as a voltage divider: Vout = RX Vin RX + 1 CX s X Xs = R RC Cs + 1 : X X (8.19 Sim le high ass lter.55).56) (8.57) ¡ .se CX such that the ole of this circuit coincides with (8. CX V in RX Vout RX and Figure 8.

The gener al to ology of Fig. a number of micro hon es may convert the sounds of various musical instruments to voltages. This o eration is called “mixing” in the audio industry. in“noise cancelling” head hones. ¡ Figure 8.55 . for exam le. we require ¡ ¡ ole to be equal to (8. ¡ The circuit therefore exhibits a zero at the origin (s ). The reader may wonder if it is ossible to em loy a con g uration similar to the noninverting am li er of Fig. Shown in Fig. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 O Am Based Circuits 389 = 0) and a ole at .2. As suggested by (8. the increasingly larger gain o f the circuit at high frequencies tends to boost noise in the circuit. 8.20 O am with general network. For exam le.1=RX CX . Vin Z2 (8. and these voltages must then be added to create the overall musical iece.61) if the o am is ideal. 2007 at 13:42 389 (1) Sec. 8.9 and its integrator and differentiator descendants o erat e as inverting circuits.4 Voltage Adder The need for adding voltages ari ses in many a lications.60) Exercise What is the necessary value of CX if RX = R1 ? An im ortant drawback of differentiators stems from the am li cation of high frequ ency noise. this function does not translate to ideal integration or differentiation. 2006] June 30.42) and Fig.5 to avoid the sign reversa l. Z1 = R1 and Z2 = 1=C2 s yield a noni deal differentiator (why?). such a circuit rovides the following transfer function Vout V in Z2 Z1 Vout = 1 + Z1 . 8. 8.58) A0 + 1 1 RX CX = R1 C1 : One choice of RX and CX is 1 RX = A R+ 1 0 CX = C1 . For this (8. (8.cls v. In audio recording. 8.20. Unfortunately. the environmen 5 The term “mixing” bears a com letely different meaning in the RF and wireless indu stry.5 For exam le.59) (8.16.

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21 de icts a voltage adder (“summer”) incor oratin g an o am . res ectively. (8. The two currents add at the virtual ground nod e and ow through RF : RF V1 V2 R1 X R2 Vout Figure 8. if R1 . and R1 and R2 carry currents ro orti onal to V1 and V2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.62) V V Vout = .cls v. With an ideal o am .Vout : R1 R2 RF That is. 8 O erational Am li er As A Black Box tal noise is a lied to an inverting am li er and subsequently added to the signal so as to cancel itself.21 Voltage adder. V1 + V2 = . Figure 8.RF R1 + R2 : 1 2 For exam le. 2007 at 13:42 390 (1) 390 Cha . 2006] June 30. VX = 0.

a circuit that recti es even very small signals. I t is ossible to lace a diode around an o am to form a “ recision recti er. then R Vout = . This can be ¡ ¡ . Let us begin with a unity gain bu ffer tied to a resistive load [Fig.3. i.g.(8.e.1 Precision Recti er The recti er circuits descri bed in Cha ter 3 suffer from a “dead zone” due to the nite voltage required to turn o n the diodes.22(a)].R F V1 + V2 : (8. We note that the high gain of the o am ensures that node X tracks Vin (for both ositive and negative cycles). The behavior of the circuit in the resence of a nite o am gain is studied in Problem 31.” i. res ectively. if the in ut signal am litude is less than a roximately 0.63) indicates that V1 and V2 can be add ed with different weightings: RF =R1 and RF =R2 . That is.. N ow su ose we wish to hold X at zero during negative cycles.. a task ossible by varying R1 and R2 . This drawba ck rohibits the use of the circuit in high recision a lications.3 Nonlinear Functions It is ossible to im lement useful nonlinear functions through the use of o am s and nonlinear devices such as transistors.63) = R2 = R.7 V. “break” the conne ction between the out ut of the o am and its inverting in ut. in audio recording it may be necessary to lower the “volume” of one musical instrument for art of the iece.e. 8. 8. Equation (8. 8. the diodes remain off and the out ut voltage remains at zero.. The virtual ground ro erty lays a n essential role here as well. e. For exam le. Extension to more than two voltages is straightforward.64) This circuit can therefore add and am lify voltages. This ro erty al so roves useful in many a lications. if a s mall signal received by a cell hone must be recti ed to determine its am litude.

VD. Figure 8. thus raising t he current through R1 . D1 must c arry a current from X to Y . 2007 at 13:42 391 (1) Sec. VY rises further so that the current owing through D1 and R1 yields Vout Vin .on (a) Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. D1 turns off and the o am roduces a very large negative out ut (near the negative su ly rail) beca use its noninverting in ut falls below its inverting in ut. which is not ossible. Note that Vout is sensed at X rather than at the out ut of the o am .VD.on t V out t (a) (b) (c) Figure 8. Exam le 8. V in V in X Vout V in X V out R1 R1 D1 t Y VY V D.23 (a) Inverting recision recti er. 8. D1 turns off (why?). For Vin 0.22 (a) Sim le o am circuit. (b) t VX t t For Vin = 0.on for ositive in ut cycles. turning D1 barely o n but with little current so that VX 0. In its attem t to minimize the voltage difference between the noninverting and the inve rting in uts. the o am raises VY to a roximately VD1. VX 0 and VY . and X is a virtual ground. where D1 is inserted in the feedback l oo . VY only slightly decreases to allow D1 to carry the high er current.cls v. Figure 8. 8. let us rst assume that Vin = 0. the o am creates VY . leading to VX = Vin and driving VY to a very ositive value. As Vin becomes ositive. (b) circuit waveforms.on .23(a) in res onse to an in ut sinuso id.22(b).23(b) shows the resulting waveforms.3 Nonlinear Functions 391 accom lished as de icted in Fig.9 Plot the waveforms in the circuit of Fig.on so that D1 is barely on. What ha ens if Vin becomes slightly negative? For Vout to assume a negative value. V in D1 R1 X Y V in VY −V D. That is. Solution . R1 carries li ttle current. 2006] June 30. Now if Vin becomes slightly ositive. That is. Thus.22(c) lots the circuit’s waveforms in res onse to an in ut sinusoid. To analyze the o eration of this circuit. (c) circuit wavefor ms. even small ositive levels at the in ut a ear at the out ut. (b) recision recti er.

Logarithmic am li ers (“logam s”) rove useful in a lications where the in ut sig nal level may vary by a large factor. Vout = .65) The out ut is therefore ro ortional to the natural logarithm of Vin . we surmise that re lacing the bi olar transistor with a MOSFET V Vout = . The large swings at the out ut of the o am in Figs.24. Q1 cannot carry a “negativ e” current. and Vout a roaches the negative su ly rail. 8.2 Logarithmic Am li er Consider the circuit of Fig. where a bi olar transistor is laced around the o am . The reader may wonder what ha ens if Vin becomes negative. 8. 8.22(b) and 8. Since the base is at zero. Note that Q1 o erates in the active region because both the base and t he collector remain at zero.23(a) lower the s eed of the circuit as the o am must “recover” from a saturated value before it can turn D1 on again. 8. the emitter voltage must fall below zero to rovide a greater collector current. The negative sign in (8. the loo around the o am is broken. It is therefore necessary to ensure Vin remains ositive.66) is to be ex ected: if Vin rises. As with revious linear and nonlinear circuits. hence a logarithmic de en dence. V in R1 R1 X V in Q1 Vout Figure 8. so do the cu rrents owing through R1 and Q1.3.2 V to +2 V. With an ideal o am . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Sq uare Root Am li er Recognizing that the logarithmic am li er of Fig. the virtual ground lays an essential rol e here as it guarantees the current owing through Q1 is xactly ro ortional to Vi n .VBE and hence VBE = VT ln Vin =R1 : I S (8. requiring an increase in VBE . Thus. 8 O erational Am li er As A Black Box Exercise Re eat the above exam le for a triangular in ut that goes from .VT ln R in : I 1 ¡ .66) redicts that Vout is not de ned. It may be desirable in such cases to am li fy weak signals and attenuate (“com ress”) strong signals. The effect of nite o am gain is studied in Problem 41.24 in fact im lements the inverse function of the ex onential characteristic.24 Logarithmic am li er.3.cls v. R1 carries a curre nt equal to Vin =R1 and so does Q1 . In the actual circuit. 2007 at 13:42 392 (1) 392 Cha . Equation (8. Also. Additional techniques can resolve this issue (Problem 3 9). 8.

66) .S (8.

In reality. .e. 2006] June 30.Vout .4 O Am Nonidealities 393 leads to a “square root” am li er.26 (a) Offset in an o am . M1 o erates in saturation.26(a). called the in ut “offset voltage.cls v. (8.. Vout falls to allow M1 to carry a greater c urrent. a z ero in ut difference may not give a zero out ut difference! Illustrated in Fig. however. 8.1 DC Offsets The o am charac teristics shown in Fig.u t If Vin is near zero.25.) Since VGS = . such a circuit requires t hat M1 carry a current equal to Vin =R1 : M1 Vout V in R1 X Figure 8. V 2 : R1 2 n ox L GS TH (Channel length modulation is neglected he re. the in ut difference must be raised to a certain value.” Vout Vos V in1 − V in1 Vos (a) (b) (c) Vout Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.VTH . 8.25 Square root circuit. Vin = 1 C W V .2 im ly that Vout = 0 if Vin1 = Vin2 . then Vout remains at . lacing M1 at the edge of condu ction. As Vin becomes more ositive. In ractice. 8. 8. for Vout = 0. Vos .68) 8. (c) re resentation of offset. In t his section.4. 2007 at 13:42 393 (1) Sec. i. VTH : n Cox W R1 L 2Vin (8. ¡ ¡ ¡ . o am s suffer from other im erfections that may affect the erformance signi cantly. the characteristic is “offset” to the right or to the left. we deal with such nonidealities. 8.67) v u Vout = . Illustrated in Fig. With its gate and drain at zero.4 O Am Nonidealities Our study in revious sections has dealt with a relatively idealized o am mode l—exce t for the nite gain—so as to establish insight. (b) mismatch between in ut devices.

For exam le. . as conce tually shown in Fig.What causes offset? The internal circuit of the o am ex eriences random asymme tries (“mismatches”) during fabrication and ackaging.

The same effect occurs for MOSFETs. thereby generating Vos V in R1 R2 Vout Figure 8. Since offsets are random and hence can be ositive or negative. De icted in Fig. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26(c)]. Vout = 1 + R1 Vin + Vos : R2 ¡ .26(b). 8 . 8. We model the o ffset by a single voltage source laced in series with one of the in uts [Fig.27 Offset in noninverting am li er.2 in the re sence of o am offsets. Vos can a ear at either in ut with arbitrary olarity. 2007 at 13:42 394 (1) 394 Cha . Why are DC offsets im ortant? L et us reexamine some of the circuit to ologies studied in Section 8.27. the noninverting am li er now sees a total in ut of Vin + Vos . the bi olar transistors sensing the two in uts may dis lay slightly dif ferent base emitter voltages.cls v. 8 O erational Am li er As A Black Box 8.

thus incurr ing accuracy limitations.11 An electrical engineering student constructs the circuit shown in Fig.e. . what is the accuracy of the w eighing station? Solution An offset of 2 mV corres onds to a load of 10 kg. Exam le 8. Solution From Fig. We therefore say the station h as an error of 10 kg in its measurements. the circuit am li es the offset as well as the signal.. microvolt signals) can be detected.28 to a m lify the signal roduced by a micro hone.27. 8. The targeted gain is 104 so that ver y low level sounds (i. 8. The second stage 6 The reader can show that lacing Vos in series with the inverting in ut of the o am yields the same result. 8. Ex lain what ha e ns if o am A1 exhibits an offset of 2 mV.69) In other words. Exercise What offset voltage is required for an accuracy of 1 kg? DC offsets may also cause “saturation” in am li ers. If the ressure meter generates 20 mV for ever y 100 kg of load and if the o am offset is 2 mV.6 Exam le 8.(8.27. generating a dc level of 200 mV at node X (if the micro hone roduces a zer o dc out ut). The following exam le illustrates this oint.10 A truck weighing station em loys an electronic ressure meter whose out ut is am li ed by the circuit of Fig. we recognize that the rst stage am li es the offset by a factor of 100.

70) (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This is studied in Problem 49. thereby attem ting to generate Vout = 20 V. the out ut cannot exceed this value. What ha ens at the out ut? Recall from Fig. the second o am drives its transistors into saturation (for bi ola r devices) or triode region (for MOSFETs). 2006] June 30.. as Vout a roaches the ositive or negati ve su ly voltages. 3 V. if Vos = 2 mV and R2 =R1 least remains away from saturation. say. and its gain falls to a small value.29(c) are sim ilar at low frequencies: Vout = Vos 1 + R2 : R1 For exam le.9) because the circuits of Figs. 8.) Exercise Re eat the above exam le if the second stage has a voltage gain of 10. Figure 8. DC offsets im act the inverting am li er of Fig. Even in the resence of an in ut signal.10.61)] and the integral of the in ut [the second term in (8. 2007 at 13:42 395 (1) Sec. where resistor R2 is laced in arallel with C1 . now am li es VX by another factor of 100. 8.29(a) integrates the offset and reaches saturation. 1 C1 Zt (8. We say the second stage is saturated. (8. the circuit of Fig.61)].29(c) de icts a modi catio n. 8.7(a) in a similar manner.28 Two stage am li er. the circu it integrates the o am offset.1 de ending on the sign of Vos . 8. Su ose the in ut is set to zero and Vos is referred to the noninv erting in ut [Fig. 8. If A2 o erates with a su ly voltage of. The roblem of offsets roves quite serious in i ntegrators. (The roblem of offset am li cation in casca ded stages can be resolved through ac cou ling. 8. 8.4 O Am Nonidealities A1 X 10 k Ω 100 Ω 10 k Ω 100 Ω 395 A2 Vout Figure 8. We now examine the effect of offset on the integrator of Fig. In other words.5 and 8. W e can therefore ex ress Vout in the time domain as Vos dt Vout = Vos + R 1C 1 1 0 V = Vos + R os t. 8. ¡ . Of course.29(a)]. the transistors in the o am fail to rovide gain and the o ut ut saturates [Fig.20 a nd Eq.29(b)]. Now the effect of Vos at th e out ut is given by (8. generating an out ut that tends to +1 or .cls v.71) where the initial condition across C1 is assumed zero.61) that the res onse to this “in ut” consists of the in ut itself [the un ity term in (8.

but at . then Vout contains a dc error of 202 mV.72) = 100.(8.

8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1=R2 C1 rather than at the origin. 8 O erational Am li er As A Black Box Vout R1 VCC Vout VCC V os VEE t (a) (b) R2 C1 R1 Vout V in V os R1 R2 C1 Vout (c) (d) Figure 8. Thus.74) Vin R1 C1 s That is.73) Vin R1 R2 C1 s + 1 : Thus. 8.30. each bias curr ¡ . R2 (8. (b) out ut waveform. R2 =R1 must be suf ciently small so as to minimize the am li ed offset given by (8.cls v.27). the in ut bias currents may create inaccuracies in some circuits.4. 2007 at 13:42 396 (1) 396 C1 Cha .72) whereas R2 C1 must be suf ciently large so as to negligibly im act the signal frequencies of interest. the circuit now contains a ole at . While relatively small ( 0:1 1 A). As shown in Fig.2 In ut Bias Current O am s im lemented in bi olar technology draw a base c urrent from each in ut. How does R2 affect the integration function? Disregarding Vos . we have 1 Vout = .29 (a) Offset in integrator. viewing the circ uit as shown in Fig. (c) addition of R2 to reduce effect of offset. 2006] June 30. and using (8. then R2 C1 s 1 and Vout = . 8. the integration function holds for in ut frequencies much higher than 1 =R2 C1 . (d) determination of transfer function. If the in ut signal frequencies of interes t lie well above this value.29(d). 1 : (8.

Let us study the effect of the in ut currents on th e noninverting am li er.31(b). Using su er osition and setting Vin to zero. introducing an error. we arrive at the circuit in Fig.ent is modeled by a current source tied between the corres onding in ut and grou nd. which can be transformed to that in Fig. IB 1 = IB 2 .7(a) . The current IB2 . Nominally. 8. ows through R1 and R2 . 8. IB 1 has no effect on the ci rcuit because it ows through a voltage source. 8.31(a). thereby yielding . the circuit now resembles the inverting am li er of Fig. on the other han d. 8. Interestingly.31(c) if IB 2 and R2 are re laced with their Thevenin equivale nt. As de icted in Fig.

cls v. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (c) Thevenin equivalent. Vout V in I B1 I B2 (a) Vout I B1 X I B2 (b) R1 R2 R1 R2 Vout R2 − I B2 R 2 (c) Figure 8.31 (a) Effect of in ut bias currents on noninverting am li e r.4 O Am Nonidealities 397 V in1 V in2 Vout I B1 I B2 Figure 8.30 In ut bias currents. 2006] June 30. R1 . 2007 at 13:42 397 (1) Sec. (b) sim li ed circuit.

R Vout = . We may therefore seek a method of canceling this error. the base currents drawn from the inverting and noninverting in uts remain a r oximately equal. Since Vcorr “sees” a noninverting am li er. 8. corru ting the out ut. we have R Vout = Vcorr 1 + R1 + IB2 R1 : 2 For Vout . an ex ected result because the virtual ground at X in Fig. this henomenon is no t random.75) (8. for a given bias current in the bi olar transistors used in the o am . However.31(b) forces a zero voltage across R2 and hence a zero current through it.27. The error due to th e in ut bias current a ears similar to the DC offset effects illustrated in Fig . This ex ression suggests that IB 2 ows only through R1 .76) if the o am gain is in nite.32). For exa m le. we can insert a corrective voltage in series with the noninverting in ut s o as to drive Vout to zero (Fig. 1 = R1 IB2 R2 (8. unlike DC offsets.R2 IB2 . 8. 8.

77) = 0.IB2 R1 jjR2 : (8.78) .(8. Vcorr = .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.33 a lies to this circuit as well.33 Correction for variation of beta.78) im lies that Vcorr de ends on IB 2 and hence the current gain of transistors. we observe that the in ut bias currents have a n identical effect on the inverting am li er. A bi olar o am em loys a collector current of 1 mA in each of the in ut device s. 8. Thus.cls v. 8. We have IB Exam le 8.31(b). 8. If = 100 and the circuit of Fig.33. det ermine the out ut error and the required value of Vcorr . R1 = 10 k . 8.80) Exercise Determine the correction voltage if = 200. Vcorr is chosen as (8. . R1 V in R2 I B1 Vout I B2 R1 R2 Figure 8. 2006] June 30. if IB 1 = IB2 .32 Addition of voltage source to correct for in ut bias currents. Vcorr cannot remain at a xed value and must “track” .32 incor orates R2 = 1 k . leading to the to ology shown in Fig. Here.12 Solution = 10 A and hence Vout = 0:1 mV: Thus. 8 O erational Am li er As A Black Box Vout = 0 X I B2 R1 R2 Figure 8.9:1 V: (8. From the drawing in Fig.79) Vcorr = . Fortunately. Equation (8. Since varies with rocess and tem erature. 2007 at 13:42 398 (1) 398 Vcorr Cha . The reader is encouraged to take the nite gain of the o am into account and rove that Vout is still near zero. the correction technique shown in Fig. then Vout = 0 for Vin = 0.78) also reveals that Vcorr can be obt ained by assing a base current through a resistor equal to R1 jjR2 . (8.

.

Can we a ly the correcti on technique of Fig.81) (8. 8.35 Correction for in ut currents in an integrator.) In other words. 8.34(b)] yields C1 C1 R1 Vout − I B2 R 1 R1 Vout I B2 (a) (b) Figure 8. the circuit forces IB 2 to ow through C1 because R1 s ustains a zero voltage dro .cls v. We now consider the effect of the in ut bias cu rrents on the erformance of integrators.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.82) (8.35 in the labo . the Thevenin equivalent of R1 and IB2 [Fig . Vout = . the ow of IB 2 through C1 leads to the same result. R 1C Z = + R 1C IB2 R1 dt B = IC 2 dt: 1 1 1 1 1 Vin dt (8. 8.34(a) with Vin = 0 and IB 1 omitted (why?). 8. Exam le 8. 8.33. 8. 8. the circuit integrates the in ut bias current.34(b) suggests that a resistor equal to R1 laced in series with the noninverting in ut can can cel the effect. 2007 at 13:42 399 (1) Sec. The result is de icted in Fig.83) (Of course.4 O Am Nonidealities 399 In reality. 8.35. Illustrated in Fig. thereby forcing Vout to eventuall y saturate near the ositive or negative su ly rails.33 to the integrator? The model in Fig.13 An electrical engineering student attem ts the to ology of Fig. Problem 53 studies the effect of this mism atch on the out ut in Fig. (b) Thevenin equiva lent. asymmetries in the o am ’s internal circuitry introduce a slight (ran dom) mismatch between IB 1 and IB 2 .34 (a) Effect of in ut bias currents on integrator. In fact. C1 V in R1 Vout R1 Figure 8. 2006] June 30.

Third.1). creating an additional error. 8. ossible reasons .35 als o exhibit mismatches. the two resistors in Fig. Give three for this effect. Second. thus causing incom lete cancellation. ratory but observes that the out ut still saturates. the two in ut bias currents always suffer from a slight mismatch.4. the DC offset voltage of the o am itself is still integrated (Section 8 .Solution First.

29(c). 8 O erational Am li er As A Black Box Exercise The roblem of in ut bias current mismatch requires a modi cation similar to that in Fig. the gain begins to fall as the frequency of o eration exceeds f1 . Vin2 s = 1 + s . At very high frequencies. as illustrated in Fig. Consider the noninverting am li er of Fig. We utilize Eq. s=!1 1. 8. To re resent the gain roll off shown in Fig. 2006] June 30. we must modify the o am mod el offered in Fig.4. As a sim le a roximation. deferring a more d etailed study to Cha ter 11. the internal circuitry of the o am can be modeled by a rst order (one ole) system having the following tran sfer function: Vout A0 Vin1 .36 Frequency res onse of an o am . we rovide a sim le analysis of such effects. This frequency is called the “unity gain bandwidth” of the o am . Using this model. 8. Av A0 1 f1 fu f Figure 8.36. the internal ca acitances of the o am degrade the erformance at high frequencies.36. For exam le. In reality. 8.3 S eed Limitations Finite Bandwidth Our study of o am s has thus f ar assumed no s eed limitations. (8. The mismatch current then ows through R2 rather than through C1 (why?). !1 (8.84) where !1 = 2f1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11) but re l ace A0 with the above transfer function: Vout s = Vin 1+ Is resistor R1 necessary if the internal circuitry of the o s? ¡ ¡ ¡ ¡ am uses MOS device . s=!1 1 and the gain is equal to A0 . Note that at frequencies well below !1 . 2007 at 13:42 400 (1) 400 Cha . I n this cha ter. and the gain of the o am falls to unity at !u = A0 !1 . we can reexamine the erformance of the circuits studied in the revious sectio ns.cls v.1. 8. 8. 8.5.

86) gives .85) Multi lying the numerator and the denominator by 1 + s=!1 Vout s = A0 s + R2 A + 1 : Vin !1 R1 + R2 0 (8.A0 : R1 + R2 + 1 + s !1 R2 1 s 1+ ! A0 (8.

8. 2007 at 13:42 401 (1) Sec.closed j = 1 + R R2 R A0 !1 : 1+ 2 ¡ The system is still of n is given by rst order and the ole of the closed loo transfer functio .4 O Am Nonidealities 401 j! .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.cls v.

37 Frequency res onse of (a) o en loo it. of course. accrues at the cost of a ro ortional reduction in gain—from A0 to 1 + R2 A0 =R1 + R2 .(8. If the circuit is designed for a closed loo gain of 16. Av A0 A0 (1+ O Am Frequency Res onse Noninverting Am lifier Frequency Res onse R2 A ) R 1+ R 2 0 1 f1 (1+ fu R2 A )f R 1+ R 2 0 1 f Exam le 8.87) As de icted in Fig. o am and (b) closed loo ¡ ¡ circu .37.closed j = 1 + R R2 R A0 !1 1+ 2 ¡ ¡ ¡ ¡ Figure 8. we require that 1 + R1 =R2 Solution j! . For a closed loo gain of 16. de termine the resulting bandwidth and time constant. This im rovement.14 A noninverting am li er incor orates an o am having an o en loo gain of 100 and bandwidth of 1 MHz. the bandwidth of the closed loo circuit is substantia lly higher than that of the o am itself. 8.

89) R2 (8.88) (8.90) Given by j! . above analysis can be re eated for the inverting am li er as well. The analysis is beyond sco e of this book. but it is outlined in Problem 57 for the interested read Exercise Re eat the above exam le if the o am gain is 500.= 16 and hence 1 0 C B = B1 + R 1 A0 C !1 A @ 1 +1 = 2 635 MHz: (8. The nite bandwidth of the o am considerably degrade the erformance of integrators. the time constant of the circuit is equal to 2. . The reader rove that the result is similar to (8. The can may the er.closed j.87).51 ns.1 .

38( ).38(b)]. If the in ut ste is raised to 2V . 8. In reality. as a ramp) and eventually settles as in the linear case of Fig. The nonlinearity can also e o served y applying a large-s ignal sine wave to the circuit of Fig. V in t V in Vout V in R2 R1 V out ∆V 2 ∆V t V out Ramp Linear Settling t t (a) ( ) (c) Figure 8.7 In other words. 2007 at 13:42 402 (1) 402 Cha . large-signal steps must face slewing prior to linear settling. also called “frequency com ensation. 8 O erational Am li er As A Black Box Another critical issue in the use of o am s is stability. doubling the in ut am litude doubles both the out ut am litude and the out ut slo e. 8. some o am s may oscillate. if laced in the to o logies seen above.. (c) input and output waveforms in slewing regime. Figure 8.closed j. the points on the ramp section do not follow linear scaling (if x ! y .1 [F ig.86). A small ste of V at the in ut thus result s in an am li ed out ut waveform having a time constant equal to j! . each oint on the out ut wavefo rm also rises by a factor of two. Arising from the internal circuit ry of the o am . with a large input step. this henomenon often requires internal or external stabilizat ion. While for s mall-signal steps. where the closed loo transfer function is given by (8. It is important to unders tand that slewing is a nonlinear phenomenon. As illustrated in Fig. th e internal circuitry of the op amp reduces to a constant current source charging a capacitor. As suggested y the waveforms in Fi g. C onsider the noninverting con guration shown in Fig.” These conce ts are studied in Cha ter 12.38(a).38(c). revealing the longer settling time in the latter case.cls v. 8.38(c). the output rst rises with a constant sl ope (i. op amps do not exhi it the a ove ehavior if the signal amplitudes a re large. The slope of the ramp is c alled the “slew rate” (SR). 2006] June 30. Slewing further limits the speed of op amps.e. another interesting effect is observed in o am s that relates to their res onse to large signals. We say the op amp “slews” during this time.3 9 compares the response of a non-slewing circuit with that of a slewing op amp.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.38 (a) Noninverting ampli er. 8. Slew Rate In addition to bandwidth and stability roblems. 8.38(a) and gradually increasing the freq ¡ £ £ £ £ £ £ £ £ £ £ £ £ . ( ) input and output wavefo rms in linear regime. then 2x 6! 2y ). The ramp section of the waveform arises ecause. 8. the output response is determined y the closed-loop time con stant.

Writing Vin t = V0 sin !t and Vout t = V0 1 + R1 =R2 sin !t.uency (Fig. 8. £ £ .40(a)]. if xt ! yt. we o serve that 7 Recall that in a linear system. then 2xt ! 2yt. 8. At low frequencies. the op amp output “tracks” the sine wave eca use the maximum slope of the sine wave remains less than the op amp slew rate [F ig.40).

2006] June 30.40 (a) Simple noninverting ampli er.39 Output settling speed with and without slewing. 8. (c) input and output waveforms with slewing.4 Op Amp Nonidealities 403 V in t Without Slewing V out With Slewing t Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2007 at 13:42 403 (1) Sec. dVout = V 1 + R1 ! cos !t: 0 dt R2 £ £ . ( ) input and output waveforms witho ut slewing. Vout V in R2 R1 V in Vout t (a) ( ) V in t1 Vout t2 (c) t Figure 8.

determine the maximum fr equency of operation that avoids slewing.15 The internal circuitry of an op amp can e simpli ed to a 1-mA current source char ging a 5-pF capacitor during large-signal operation.40( ). and the op amp slew rate must exceed this value to avoid slewing. If an ampli er using this op amp produces a sinusoid with a peak amplitude of 0. Example 8..91) The output therefore exhi its a maximum slope of V0 ! 1 + R1 =R2 (at its zero cro ssing points). What happens if the op amp slew rate is insuf cient? The output then fails to fol low the sinusoidal shape while passing through zero. 8. £ £ £ £ £ £ .(8. e. exhi iting the distorted e havior shown in Fig.5 V.g. etween t1 and t2 . Note that the output tracks the input so long as t he slope of the waveform does not exceed the op amp slew rate.

8 Operational Ampli er As A Black Box The slew rate is given y I=C = 0:2 V/ns. To de ne the maximum sinusoidal frequency that remains free from slewing.7 MHz. for frequencies a ove 63. 1+ Figure 8.92) dVout j = V !: dt max p Equating this to the slew rate.41 Maximum op amp output swings.91) indicates that the onset of slewing depends on the closed-loop g ain. Exercise Plot the output waveform if the input frequency is 200 MHz. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. the maximum slope is equal to Solution = Vp sin !t.93) That is. If the op amp provides a slew rate of SR. namely. we have ! = 263:7 MHz: (8.94) where Vmax and Vmin denote the ounds on the output level without saturation. R1 =R2 . As exempli ed y Fig. For an output given y Vout Vp = 0:5 V . the zero crossings of the output experi ence slewing. 2007 at 13:42 404 (1) 404 Chap. it is common to assume the worst case.cls v. where (8.41. Vout = Vmax . 2 2 (8. Vmin sin !t + Vmax + Vmin . when the op amp produces its max imum allowa le voltage swing without saturation. then the maximum frequency of the a ove sinusoid can e o tained y writing £ £ £ £ £ ¢¢ V V max £ £ £ £ £ £ ¢¢ . the l argest sinusoid permitted at the output is given y V V in1 V in2 Vout V min 0 Equation (8.

2 (8.” !FP serves as a measure of the useful large-signa l speed of the op amp.95) !FP = VmaxSRVmin : .dVout j = SR dt max and hence (8.96) Called the “full-power andwidth. £ .

we view R1 and R2 as a vo tage divider: (8.42( )].4. (b) effect of nite output resistance of op amp. 8. vin + R1 + R2 .4 Op Amp Nonidealities 405 8.42 (a) Inverting amp i er. R1 R1 vin R2 1 + Rout + A0 + R1 : R R 2 2 (8.cls v. For an output swing of.42(a) using R1 = 50 and R2 = 10 . We must solve the circuit in the presence of Rout . Rout .99). we write a KV L from vin to vout through R2 and R1 : R1 R2 X Vout V in v in − A 0v X R1 R2 X R out v out (a) (b) Figure 8. vout =Rout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exp ain why.97) thus yie ds (8.1 and place Rout in series with the output voltage source [Fig. vin + vin : 1+ 2 Substituting for vX in (8. 8. 8. Unfortunate y. Recognizing that the current owing through Rout is equal to . 2007 at 13:42 405 (1) Sec. assuming the op amp suffers f rom an output resistance. vout = vout : R out To construct another equation for vX . the circuit fai s to provide arge vo tage swings at the output even though Rout =R1 and Rout =R2 remain much ess than A0 in (8. How should the circuit e analyzed? We return t o the model in Fig.Rout =R1 in the numerator and Rout =R2 in the denominator increase the gain error of the circuit.42(a).A0 vX .98) A0 . Rout vout = . 8.4 Finite Input and Output Impedances Actual op amps do not provide an in nite input impedance8 or a zero output impedance—the latter often creating limitations in the design. Co nsider the inverting ampli er shown in Fig. 8 .97) vX = R R2 R vout . Many op amps can provide on y a sma output current even though their sma signa output impeda ¤ ¤ ¤ ¤ ¤ ¡¤¤ £ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ £ ¤ ¤ ¤ . 2006] June 30. the op am p may need to de iver a current as high as 40 mA to R1 (why?). An e ectrica engineering student purcha ses an op amp with A0 = 10. say.A0 vX . We analyze the effect of this nonideality on one circuit here.99) The additiona terms . 000 and Rout = 1 and constructs the amp i er of Fig. 2 V.

nce is very ow. Examp e 8.16 So ution 8 Op amps emp oying MOS transistors at their input exhibit a very high input imp edance at ow frequencies. ¤ ¤ ¤ ¤ ¤ .

7(a). what va ue of R1 is acceptab e for output vo tages as high as 1 V? 8. For an input impedance of 10 k .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. We begin with simp e examp es and gradua y proceed to more cha enging prob ems.5 Design Examp es Fo owing our study of op amp app ications in the previous sections. Determine the minimum op amp gain required here. we choose the same va ue of R2 in Fig. 2007 at 13:42 406 (1) 406 Chap. a gain error of 0:1.17 So ution 1 R1 A0 1 + R2 and hence ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ . 8 Operationa Amp i er As A B ack Box Exercise If the op amp can de iver a current of 5 mA. 8. 2006] June 30. Eq.21) deman ds that Examp e 8. Design an i nverting amp i er with a nomina gain of 4.c s v. (8. Under these conditions. and an input imped ance of at east 10 k . we now cons ider severa examp es of the design procedure for op amp circuits. arrivin g at R1 = 40 k for a nomina gain of 4.

Determine the required open oo and bandwidth of the op amp.102) 1 R1 A0 1 + R2 ¤¡ ¤¡ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¡ ¤ ¤ Design . R1 = 4: R2 (8.100) A0 5000: (8. we have The choice of R1 and R2 themse ves depends on the “driving capabi ity” (output resis tance) of the op amp. For examp e. For a gain error of 1%.99) at the end. (8.5 and Eq. we may se ect R1 = 4 k and R2 = 1 k and check the gain error from (8. Assume the op amp has an input bias current A. 8. Examp e 8.0:1 (8.18 So ution From Fig.9).101) Exercise Repeat the above examp e for a nomina gain of 8 and compare the resu ts. ¤ ¤ ¤ ¤ ¤ . gain p gain of 0.2 a noninverting amp i er for the fo owing speci cations: c osed oop gain = 5 error = 1. c osed oop bandwidth = 50 MHz.

103) .1 (8.

5 Design Examp es 407 and hence A0 500: A so.105) (8.c osed 1 + R R2 R A0 1+ 2 !p. Examp e 8.106) (8. the open oop bandwidth is given by (8. If the op amp provides a s ew rate of 0.87). from (8. ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¡ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¡ ¤ ¤ ¤ ¤ ¤ .107) Thus.19 Design an integrator for a unity gain frequency of 10 MHz and an input impedance of 20 k . Exercise Repeat the above examp e for a gain error of 2 and compare the resu ts. the op amp must provide an open oop bandwidth of at east 500 kHz.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 2007 at 13:42 407 (1) Sec.104) !1 !1 !p.c s v.1 V/ns.1 A0 2 250 MHz : 100 (8.108) = 20 k . we have R1 C1 2 10 MHz = 1 and. what is the argest p eak to peak sinusoida swing at the input at 1 MHz that produces an output free from s ewing? So ution From (8.29). with R1 1 (8. 8. 2006] June 30.c osed R 1 + 1 + R1 .

C1 = 0:796 pF: (In discrete design.C Vp sin !t.110) dVout j = 1 V : dt max R1 C1 p Equating this resu t to 0.109) 1 Vout = R.1 V/ns gives (8.111) Vp = 1:59 V: (8. (8. such a sma capacitor va ue may prove impractica .112) ¤ ¤ ¤¤ ¤ ¤ .) For an input given by Vin = Vp cos !t. 1 1 ! with a maximum s ope of (8.

An inverting con guration using mu tip e input r esistors tied to the virtua ground node can serve as a vo tage adder.e. These effects impact the performance of vario us circuits. a circuit that can re ctify very sma input swings. The speed of op amp circuits is imited by the bandwidth of the op amps.c s v. Exercise How do the above resu ts change if the op amp provides a s ew rate of 0. and c ose to zero for jVout j 2 V. 2006] June 30. For examp e. Actua op amps exhibit “non inear” characteristics. the input peak to peak swing at 1 MHz must remain be ow 3. most notab y. 500 for 1 V jVout j 2 V. non inearity)? ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .1 V Vout +1 V.5 V/ns? 8. i.6 Chapter Summary An op amp is a circuit that provides a high vo tage gain and an output proportio na to the difference between two inputs. t he circuit acts as a differentiator. If the input resistor in an inverting con guration is rep aced with a capacitor.. Op amps suffer from various imperfections. (a) P ot the input/output characteristic of this op amp. With the noninverting input of the op amp tied to ground. The inverting amp i er con guration pro vides a nomina gain equa to the ratio of two resistors. Its gain error is the same as that of the noninverting con guration.. for arge signa s. 8 Operationa Amp i er As A B ack Box In other words. the op amp suffers fro m a nite s ew rate.18 V f or the output to be free from s ewing. Integrator nd wide app ication in ana og ters and ana og todigita converters. 2007 at 13:42 408 (1) 408 Chap. differentiators are ess common than integrators. integrators.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. P acing a bipo ar device around an op amp provide s a ogarithmic function.” If the feedback resistor in an invertin g con guration is rep aced with a capacitor. an op am p producing a moderate output swing requires on y a very sma input difference. ( b) What is the argest input swing that the op amp can sense without producing “di stortion” (i. Prob ems 1. Due to their higher noise. Due to its high vo tage gain. The circuit a so suffers from a gain error that is inver se y proportiona to the gain of the op amp. inc uding d c offsets and input bias currents. the inverting input a so remains c ose to the ground pote ntia ans is thus ca ed a “virtua ground. the vo tage gain may be equa to 1000 for . The noninverting amp i er topo ogy exhibits a nomina gain equa to one p us the ratio of two resistors. P acing a diode around an op amp eads to a precision recti er. A so.e. the circuit operates as an integrator . distorting the output waveform.

43 What happens if A0 ! 1? 7. resistor R2 deviates from its nomina va ue V in1 A0 V in V in2 R1 R2 Vout Figure 8. What happens if A0 ! 1? 8.44 impedance. 5. Vin2 0. Vin2 (8. 8. (a) Su ppose a nomina c osed oop gain of 1 is required. Rout .113) 3. 8. Compute the minimum required op amp gain. compute the c osed oop gain and output R out Vout V in1 V in2 A 0 (V in1 − V in2 ) Figure 8. A noninverting amp i er emp oys an op amp having a nomina gain of 2000 to achieve a nomina c osed oop gain of 8. Sketch this characteristic and determine the sma signa gain of the op amp in the vicinity of Vin1 . Vout V in1 V in2 R in A 0 (V in1 − V in2 ) Figure 8. an adventurous student decides that it is possib e to achieve a zero gain error with a nite A0 if R2 =R1 + R2 is s ight y adjusted from its nomina va ue.11).6 Chapter Summary 409 2.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.44. 2006] June 30. A noninverting amp i er emp oys an op amp with a nite ou tput impedance. 2007 at 13:42 409 (1) Sec. In the noninverting amp i er shown in Fig. 8. determine the gain error if A0 drops to 0:6A0 . A noninverting amp i er must provide a nomina gain of 4 with a gain er ror of 0:1. Looking at Equation (8. determine the c osed oop gai n and input impedance. 8 . Determine the g ain error. 6.c s v. 4. An op amp exhibits the fo owing non inear characteristic: Vout = tanh Vin1 . A noninverting amp i er incorporates an op amp having an input impedance o f Rin .45 : ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ . Mode ing the op amp as shown in Fig.45. How shou d R2 =R1 + R2 be chos en? (b) With the va ue obtained in (a).43. Representing the op amp as depicted in Fig.

13. Ca cu ate cteristic of an strated in Fig. 8 Operationa Amp i er As A B ack Box mV A0 +2 mV +4 mV V in1 − V in2 Figure 8. 9. determine the c osed oop gain and input impedance. 8.) 10. The op amp used in an invertin g amp i er exhibits a nite input impedance. A so. Determine the gain of the system.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.47 divided by the change in W . the c osed oop circuit is much more inear. A0 V in R1 R2 R3 R4 Vout = 1. i.. The input/output chara op amp can be approximated by the piecewise inear behavior i u 8. A truck weighing stat ion incorporates a sensor whose resistance varies inear y with the weight: RS = R0 + W . Figure 8. 2006] June 30. An inverting amp i er must provide a nomina gain of 8 with a gain error of 0: 2.48 12. 11. Ca cu ate the c osed oop gain of the noninvert ing amp i er shown in Fig.43.46. 8. Here R0 is a constant va ue. Rin . 2007 at 13:42 410 (1) 410 Chap.8A 0 −4 mV −2 the gain error of the circuit if R=R2 1. Suppose RS p ays the ro e of R2 in the noninverting amp i er (Fig . (Note that the c osed oop gain experiences much ess variatio n.e. 8. Vout 0. Mode ing the op amp as shown in F ig.c s v. and W the weigh t of each truck.47). Suppose this op amp is used in a noninverting amp i er with a nomina gain of 5. Vin2 j increases. de ned as the change i n Vout Vin =1 V A0 R1 Vout RS Figure 8. Vin = 1 V.48 if A0 Verify that the resu t reduces to expected v a ues if R1 ! 0 or R3 ! 0. a proportiona ity factor. Determine the minimum required op amp gain. P ot the c osed oop input/output characteristi c of the circuit.46 zero as jVin1 . ¤¤ ¤¤ ¤ ¤ ¤¡ by R. where the gain drops from A0 to 0:8A0 and eventua y to ¤ ¤ ¤ ¤¡ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .

BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 2007 at 13:42 411 (1) Sec. determine the gain error. 8. 8. ¤ ¤ 19.c s v. Determine the Figure 8. If the op amp exhibits an open oop gain of 1000 and an output impedance of 1 k .50 = V0 sin !t.50 if A0 R1 R2 X A0 V in Vout R4 R3 = 1. 8. 17. 21.51 output signa amp itude if A0 = 1.49 18. ca cu ate the required open oop gai n of the op amp. 20. An inverting amp i er emp oys an op amp having an output impedance of Rout . The integrator of Fig. 8. 2006] June 30.51 must provide a p o e at no higher than 1 Hz. If A0 = 1 and R1 C1 = 10 ns.51 senses an input signa C1 R1 V in A0 Vout given by Vin ¤ ¤¡ ¤¡ ¤¡ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . compute the c osed oop gain and ou tput impedance. If the va ues of R1 and C1 are imited to 10 k and 1 nF. 15. M ode ing the op amp as depicted in Fig. 8.6 Chapter Summary 411 14. compute the frequency of the sinusoid. An inverting amp i er must provide an input impedance of appro ximate y 10 k and a nomina gain of 4. respective y. Figure 8.51 is used to am p ify a sinusoida input by a factor of 10. If the input impedance of the c ircuit must be equa to approximate y 1 k . 16. The integrator of Fig. Verify that the resu t reduces to expected va ues if R1 ! 0 or R3 ! 0. 8. The integrator of Fig. compute the c osed oop gain of the invert ing amp i er shown in Fig. 8. Assuming A0 = 1. determine the required gain of the op amp. Determine the c osed oop gain of the circuit depicted in Fig. R3 R1 R4 R2 Vout V in Figure 8.49.44. An invert ing amp i er is designed for a nomina gain of 8 and a gain error of 0:1 using an o p amp that exhibits an output impedance of 2 k .

24.42). respective y. Compute the transfer function and compare the resu t with Eq. We wish to design th e differentiator of Fig. (8. determine the va ue of R1 C1 . (8. (8. Determine the transfer function Vout =Vin and compare th e ocation of the po e with that given by Eq.52 exhibits a nite input impedan ce and is mode ed as shown in Fig.37). P ot Vout as a function of time if V1 = RF V1 V2 R2 X R1 A0 Vout ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .53 29.5 2 is used to amp ify a sinusoida input at a frequency of 1 MHz R1 C1 V in A0 Vout Figure 8. 8. Can the resistors and capacitors be chosen so as to reduce jVout =Vin j to approximate y unity? 30. 27. 26. by a factor of 5. If A0 = 1.51 exhibits a nite output impedance and is mode ed as depic ted in Fig. The op amp used in the differentiator of Fig.43. If the va ues of R1 and C1 cannot be ower than 1 k and 1 nF. Consider the integrator shown in Fig.42).53 if A0 = 1. 8. 8. compute the required gain of the op amp.52 for a po e frequency of 100 MHz. Suppose the op amp in Fig.51 and suppose the op amp is mode ed as shown in Fig.44. 8.c s v. 2007 at 13:42 412 (1) 412 Chap. Consider the vo tage adder sh own in Fig.57). 8. 8. 8 Operationa Amp i er As A B ack Box 22. Determine the transfer function Vout =V in and compare the resu t with Eq. 8.54. Ca cu ate the transfer function of the circuit shown in Fig. 23. (8. 8. 8. The op amp used in the integrator of Fig. 8. The differentiator of Fig.52 25. 8. 8.43. 2006] June 30. Compute the transfer function Vout =Vin and compare the ocati on of the po e with that given by Eq. Repeat Prob em 28 if A0 1.52 suffers from a nite output impedance and is mode ed as depicted in Fig. 28.44.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Wh at choice of component va ues reduces jVout =Vin j to unity at a frequencies? R2 C1 C2 V in R1 A0 Vout Figure 8.

54 V0 sin !t and V2 = V0 sin3!t. Assume R1 = R2 and A0 = 1.Figure 8. .

where a parasitic resistor RP has appeared in para e with D1 .1 V to +1 V.57 current owing through D1 as a function of time for a sinusoida input.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Using the op amp m ode depicted in Fig. 8. Figure 8.56 op amp exhibits a nite input impedance.24 varies from . Exp ain how this can be accomp ished. 2006] June 30. With the aid of the op amp mode shown in Fig.58. 8. 8.22(b) as a function of time for a sinu soida input. We wish to improve the speed of the recti er shown in Fig. and the V in X V out R1 D1 Y Figure 8. 8.6 Chapter Summary 413 31. 8.55 a so represent the input impedance of the op amp.44. 40. 8. 2007 at 13:42 413 (1) Sec. where RP is a parasitic resistance and the R F V1 V2 R2 X R1 A0 RP Vout Figure 8. 32. Use a constant vo tage mode for the diode. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 8. Suppose Vin in F ig. 38.54 emp oys an op amp having a nite output impedance. The vo tage adder of Fig. (Note that RP can RF V1 V2 R2 X R1 A0 RP Vout Figure 8. Ca cu ate Vout in terms of V1 and V2 .22(b) by connecting a diode f rom node Y to ground.55. Consider th e vo tage adder i ustrated in Fig. compute Vout in terms of V1 and V2 . Ca cu ate Vout in terms of V1 and V2 for A0 = 1 and A0 1.57 shows a precision recti er producing negative cyc es. 8. 35. P ot the current owing thr ough D1 in the precision recti er of Fig. 37. 36.56.54 suffers from a nite gain. 8.) 33. 8. 39. determine Vout in terms of V1 and V2 . 8. 34. Consid er the precision recti er depicted in Fig. 8. Vout .23(a) as a function of time for a sinusoida input.43. Rout . P ot VY . a parasitic resistance RP has appe ared in the adder of Fig. Due to a manufacturing error. P ot the current owing through D1 in the precision recti er of Fi g. The op amp in Fig.c s v. P ot VX and VY as a function of time in response to a sinusoida input. Sketch Vout and VX as a function of Vin if th e op amp is idea .

48. 8. Ca cu ate Vout . 8.66) with respect to Vin . Suppose each op amp in Fig.1 V to . Ca cu ate Vout in terms of Vin for the circu it shown in Fig. 45. Determine the sma signa vo tage gain of the ogarithmic amp i er depicted i n Fig. In the noninverting amp i er of Fig.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 2007 at 13:42 414 (1) 414 V in X V out Chap. Determine the maximum offset error in Vout if each amp i er is designed f or a gain of 10. the op amp o ffset is represented by a vo tage source in series with the inverting input.59.58 41.62. 44. 8.24 is nite. (a) Determine the required va ues of IS and R1 .24 by differentiating both sides of (8. 2006] June 30. The ogarithmic amp i er of Fig.1:5 V. 42. Deter R1 X V in V TH M1 Vout Figure 8. 8.24 must “map” an input range of 1 V to 10 V to an output range of . 8. P ot t he magnitude of the gain as a function of Vin and exp ain why the circuit is sai d to provide a “compressive” characteristic. Determine the input/outp ut characteristic of the circuit. 8. 46. The circuit i ustrated in Fig. Describe the operation of t his circuit.61.60 can be considered a “true” square root amp i er. 8 Operationa Amp i er As A B ack Box Y D1 R1 RP Figure 8.60 mine Vout in terms of Vin and compute the sma signa gain by differentiating t he resu t with respect to Vin .59 43. A student attempts to construct a noninver ting ogarithmic amp i er as i ustrated in Fig.c s v. (b) Ca cu ate the sma signa vo t age gain at the two ends of the range. 47. Q1 Vout V in R1 X Figure 8. Suppose the gain of the op amp in Fig.28 suffers from an input offset of 3 mV. 8. ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 8.

Exp ain why dc offsets are not considered a serious issue in diffe rentiators. 2007 at 13:42 415 (1) Sec. 54.c s v. 56. f1 = 1 MHz. Determine the transfer function of the c osed oop circuit and compute the bandwidth. Assume A0 = 1. 8.62 49. Figure 8.61 A0 V in R1 V OS R2 Vout Figure 8..114) ¤¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ . 51.29(c) must operate with frequencies as ow as 1 kHz whi e providing an output offset of ess than 20 mV with an op amp offset of 3 mV. Exp ain the effect of op amp offset on the output of a ogarithmic a mp i er. The integrator of Fig. f1 = 50 Hz.33.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 8. What is the maximum a owab e va ue of R1 jjR2 if the output error due t o this mismatch must remain be ow a certain va ue.6 Chapter Summary 415 R1 X V in M1 Vout Figure 8. 57. 2006] June 30. (a) A 0 = 500.e. ca cu ate Vout if the op amp exhibits an R1 R2 A0 V in Vout Figure 8. Suppose the input bias currents in Fig. V ? A noninverting amp i er must provide a bandwidth of 100 MHz with a nomina gain of 4.63. For the inverting amp i er i ustrated in Fig. i. 8. input offset of Vos . 55. IB 1 = IB 2 + I . 8. Ca cu ate Vout . (8.64 shows an integrator emp oying an op amp whose frequency response is given by As = A0 s : 1+ ! 0 (8.84). Determine which one of the fo owing op amp speci cations are adequate: (a) A0 = 1000. Determine the required va ues of R1 and R2 if C1 100 pF. Repeat Prob em 53 for the circuit shown in Fig . 52.31 incur a sma offset. An inverting amp i er incorporates an op amp whose frequency response is given by Eq.63 50. 8. 53.

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7(a) for a nomin a gain of 8 and a gain error of 0:1. Assume = 10 V=s. 1 V . Assume Rout = 100 . 8. 64. 2006] June 30.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. A voltage adder must realize t he following function: Vout = 1 V1 + 2 V2 . 8 Operationa Amp i er As A B ack Box !0 Figure 8. V0 = 1 V0 R am p ∆V ∆V = 0.1:5. Des ign Prob ems 60. Design an integrator whose step response approximates V t = t with an error ess than 0:1 for the range 0 V t V0 (Fig. Assume the argest avai ab e capacitor is 50 pF. what is the highest input frequency for which no s ewing occurs? 59. 63. The unity gain buffer of Fig. Design an integrato r that attenuates input frequencies above 100 kHz and exhibits a po e at 100 Hz. and a tota resistance of 20 k . 65. C1 R1 Vout V in A (s ( ¤ ¤ ¤ ¤ ¤ ¤ £ £ ¤ ¤ ¤ ¤ ¤ ¤ £ ¤ £ ¤ ¤ ¤ ¤ ¤ ¤ ¤ integrator.0:5 V .64 58. 8.1% V0 Id ea Vout t Figure 8.3 must be designed to drive a 100 oad with a gain error of 0:5.c s v. and the capacitor must remain elow 20 pF. 8.65 V. A noninverting amp i er with a nomina gain of 4 senses a sinusoid having a pe ak amp itude of 0. Design the inverting amp i er of Fig. a gain e rror of 0:2. th e step response of an integrator is a s ow exponentia rather than an idea ramp . esign a logarithmic ampli er t hat “compresses” an input range of 0:1 V 2 V to an output range of . 62. Determ ine the required op amp gain if the op amp has an output resistance of 1 k . 61. Simp ify the resu t i ¤ ¤ . SPICE Pro lems ¤ ¤ ¤ ¢ ¡ ¤ ¤ ¤ £ ¤ ¢ ¤ ¤ ¤¤ Determine the transfer function of the overa f 1=R1 C1 .5 V. Can a logarithmic ampli er e designed to have a small-signal gain (dVout =dVin ) of 2 at Vin = 1 V and 0.0:5 and 2 = . where 1 = . 2007 at 13:42 416 (1) 416 Chap. With a nite op amp gain. 66 .2 at Vin = 2 V? Assume the gain of the op amp is suf cie ntly high. Design a noninverting amp i er with a nomina gain of 4. If the op amp provides a s ew rate of 1 V/ns. Assume the op amp has a nite gain bu t is otherwise idea . esign the circuit if the worst-case error in 1 or 2 must remain elow 0:5 and the input impedance seen y V1 or V2 must exceed 10 k .65).

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17 A for 1 . 69.69 71. Assume IS. V CC = 2.5 V 500 Ω am to “linearize” a commo ¢ ¡ ¡ . The arrangement shown in Fig.cls v.66 68.6 Chapter Summary 417 67. Using ac analysis in SPICE. 8. plot the input/out put characteristic of the precision recti er shown in Fig.66.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assuming an op amp gain of 1000 and IS = 10. A ly a 10 MHz sinusoid at the in ut and lot the out ut as a function of tim e. lot the frequency res onse of the circuit de ic ted in Fig.Q1 = 5 10. each o am rovides a gain of 50 0. 8. 8. 8.69 incor orates an o n emitter stage. Re eat Problem 67 but assuming that the o am suffers from an out ut resist ance of 1 k . 10 k Ω 10 F 1 kΩ 1 kΩ 10 F V in Vout Figure 8. 2007 at 13:42 417 (1) Sec. What is the error in the out ut am litude with res ect to the in ut am litude ? 10 F 1 kΩ 1 kΩ 10 F V in Vout Figure 8.68.67. 8.68 Vout Q1 V in X 100 Ω Figure 8. and = 100. 2006] June 30.16 A.67 70. In the circuit of Fig. V in V out 1 kΩ Y D1 Figure 8.

) ¡ . (Hint: VX Vin .(a) Ex lain why the small signal gain of the circuit a roaches RC =RE if the ga in of the o am is very high.

¡ . 2007 at 13:42 418 (1) 418 Cha . 8 O erational Am li er As A Black Box (b) Plot the in ut/out ut characteristic of the circuit for 0:1 V Vin 0:2 V and an o am gain of 100. (c) Subtract Vout = 5Vin (e. 2006] June 30.cls v.. using a voltage de endent voltage source) from the above characteristic and determine the maximum error.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

The “cascode”1 stage is a modi ed version of common emitter or common source to ologies and roves useful in high erformance circuit design. we de al with two other im ortant building blocks in this cha ter.” 419 ¡ ¡ ¡ ¡ ¡ ¡ . 9. We also k now that a single transistor can o erate as a current source but its out ut im e dance is limited due to the Early effect (in bi olar devices) or channel length modulation (in MOSFETs).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.1.1. Cascode Stages Cacode as Current Source Cacode as Am lifier Current Mirrors Bi o lar Mirrors MOS Mirrors 9. and the “current mirror” is an interesting and versatile technique em loyed extensively in integrated circuits. 1 Coined in the vacuum tube era. For the ci rcuits shown in Fig. 2006] June 30. 2007 at 13:42 419 (1) 9 Cascode Stages and Current Mirrors Following our study of basic bi olar and MOS am li ers in revious cha ters. the term “cascode” is believed to be an abbreviatio n of “cascaded triodes.1 Out ut im edance of degenerated bi olar and MOS devices. Shown below is the outline of the cha ter.1 Cascode as a Current Source Recall from Cha ters 5 and 7 that the use of c urrent source loads can markedly increase the voltage gain of am li ers. Our study inclu des both bi olar and MOS im lementations of each building block. we have R out1 Vb Q1 RE Vb R out2 M1 RS Figure 9. res ectively.1 Cascode Stage 9. How can we increase the out ut im edance of a transisto r that acts as a current source? An im ortant observation made in Cha ters 5 and 7 forms the foundation for our study here: emitter or source degeneration “boosts” the im edance seen looking into the collector or drain.

5) rO + RE jjr = 1 + gmrO RE jjr + rO Rout2 = 1 + gmRS rO + RS = 1 + gm ¡ ¡ ¡ ¡ .2(a) for the bi olar version. 9. 2007 at 13:42 420 (1) 420 Cha .3) (9.4 V to remain soft saturation. we call Q1 the cascode transistor and Q2 the degenerat ion transistor. For exam le. Note thatIC 1 IC 2 if 1 1. 2006] June 30. Bi olar Cascode In order to relax the trade off between the out ut im edance and the voltage headr oom.1. Let us com ute the out ut im edance o f the bi olar cascode of Fig. (9.2(b)]. we have Rout = 1 + gm1 rO2 jjr1 rO1 + rO2 jjr1 : Since ty ically gm1 rO2 jjr1 (9. the idea is to introduce a high small signal r esistance (= rO2 ) in the R out R out V b1 V b2 Q1 Q2 (a) Vb Q1 r O2 (b) Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. however. In this cas e. De icted in Fig . th en the degenerated current source “‘consumes” a headroom of 800 mV. This con guration is called the “cascode” stage.2) (9.2(a).2 To em hasize that Q1 and Q2 lay distinc tly different roles here. consuming voltage headroom and ultimately limiting the voltage swings rovided by the circuit using such a current source. Since the baseemitter voltage of Q2 is con stant.cls v. the voltage dro across the degeneration resistor also increase s ro ortionally. In analogy with the resistively degenerated counter art in Fig.4) observing that RE or RS can be increased to raise the out ut resistance. 9 Cascode Stages and Current Mirrors Rout1 = 1 + gm RE jjr rO RS + rO . 9. 9. this transistor sim ly o erates as a small signal resistance equal to rO2 [Fig. emitter of Q1 while consuming a headroom inde endent of the current. if RE sustains 300 mV and Q1 requires a minimum collectoremitter voltage of 500 mV. Unfortu nately.2 (a) Cascode bi olar current source. 9. (b) equivalent circuit. Q2 requires a headroom of a roximately 0. we can re lace the degeneration resistor with a transistor.1) (9.

7) If Q1 and Q2 in Fig. that rO cannot generally be assumed much greater than r . (9. 9. Exam le 9.1 2 Or sim ly the “cascode. Assume = 100 and VA = 5 V for both transistors.6) (9. determine the out ut resistance.2(a) are biased at a collector current of 1 mA.” .1. however. Rout 1 + gm1 rO1 rO2 jjr1 gm1rO1 rO2 jjr1 : Note.

“cascoding” has boosted Rout by a factor of 66 here.3 Cascode to ology using an ideal current source. the out ut resistance of Q1 with no degeneration would be equal t o rO1 = 5 k . After all.3) [or RE = 1 in (9. (9. 9. e .. thereby limiting Rout to 1 rO1 . 2006] June 30.12) rO2 = 1 (Fig. rO = VA =IC .11) (9. Exercise What Early voltage is required for an out ut resistance of 500 k ? It is interesting to note that if rO2 becomes much greater than r1 .8) (9. V + (9. then Rout1 a roaches gm1 rO1 r1 1 rO1 : Rout.9) = IC 1 = IC 2 and VA = VA1 = VA2 .10) By com arison. R out Q1 r π1 Ideal Figure 9. At room tem erature.cls v. This is the maximum out ut im edance ven with rovided by a bi olar cascode. r1 still a ears from the emitter of Q1 to ac ground. Note that r O2 and r1 are com arable in this exam le. 2007 at 13:42 421 (1) Sec. Eq.7) ca n be sim li ed by noting that gm = IC =VT . VT Rout 328:9 k : 26 mV and hence VA1 IC 2 IC 1 Rout V I T C 1 VA2 + VT IC 2 IC 1 I 1 VA V VA VT .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.max (9.1)]. 9. i.e.1 Cascode Stage 421 Since Q1 and Q2 are identical and biased at the same current level. and r = VT =IC : Solution VA2 VT IC 1 V C1 T A T where IC (9.

1. . This exam le a lies to discrete im lementations. all bi olar transistors fabricated on the same wafer e xhibit the same Early voltage.12 ). the Early voltage of Q2 is equal to 50 V.3 Com are the r esulting out ut im edance of the cascode with the u er bound given by Eq. Exam le 9.Su ose in Exam le 9.2 3 In integrated circuits. (9.

13) (9. 9.3 We wish to increase the out ut resistance of the bi olar cascode of Fig. RoutA = 1 + gm2 RE jjr2 rO2 + RE jjr2 : It follows from (9.1): R out R out V b1 Q1 R outA Vb Q1 R outA Solution V b2 Q2 RE Figure 9. Determine the required value of the degeneration resistor if Q1 and Q2 are i dentical. rO1 = 5 k . 2006] June 30.15) Rout gm1 rO1 RoutA jjr1 : We wish this value to be twice that given by (9. about 5 higher.16) .2(a) by a factor of two through the use of resistive degeneration in the emitter of Q 2 .cls v. As illustrated in Fig.1 .7): (9. Exam le 9. and rO2 = 50 k .14) Rout gm1 rO1 rO1 jjr1 475 k : The u er bound is equal to 500 k .4 . we have (9. 2007 at 13:42 422 (1) 422 Cha . 9 Cascode Stages and Current Mirrors Since gm1 Solution = 26 . we re lace Q2 and RE with their equivalent resistance from (9. Exercise Re eat the above exam le if the Early voltage of Q1 is 10 V. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4.7) that (9. r1 = 2:6 k .

RoutA jjr1 = 2rO2 jjr1 : That is. .18) In ractice. 1 O2 (9. it is im ossible to double the out ut im edance of the cascod e by emitter degeneration. and no ositive value of RoutA exist s! In other words.17) RoutA = r2rO2 rr1 : . (9. r1 is ty ically less than rO2 .

Exam le 9.1 and 9.5 if rO2 r1 .5 shows a n cascode. For com leteness.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where Q1 serves as the c ascode device and Q2 as the degeneration device.1 Cascode Stage 423 Exercise Is there a solution if the out ut im edance must increase by a factor of 1.5? What does the above result mean? Com aring the out ut resistances obtained in Ex am les 9.7 are not cascodes. Fig. a value greater than 0. R out V b1 X V b2 Q2 (a) R out V b1 V b1 Q1 1 r g m2 O2 VCC Q2 X V b2 Q1 R out (b) VCC 1 r g m2 O2 Q1 V b2 Q1 R out Figure 9. VCC V b2 V b1 Q2 Q1 R out Figure 9. The out ut im edance is given b y (9. 9. 2007 at 13:42 423 (1) Sec. the ratio of (9. That is.5 PNP cascode current source. we recognize that even identical transistors yield an Rout ( = 328:9 k ) that is not far from the u er bound (= 500 k ).4 Ex lain why the to ologies de icted in Fig. While we have arrived at the cascode as an it is also ossible to view the evolution since Q2 rovides only an out ut im edance ise Rout . More s eci cally.7 Figure 9. of rO2 . 2006] June 30. as illustrated in Fig.2.7) and (9.6 Evolution of cascode to ology viewed as stacking Q1 ato .12) is equal to rO2 =rO2 + r1 . 9. 9. we “stack” Q1 on to of it to ra g m1 r O1 ( r O2 r π 1 ) Q2 .cls v. 9. R out R out = r O2 V b2 Q2 V b1 V b2 Q1 Q2 extreme case of emitter degeneration.6.5).

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1).2(a).cls v. the out ut im edance. 9. Rout . the circuits of Fig. ¡ . 9 Cascode Stages and Current Mirrors Unlike the cascode of Fig. 2006] June 30.7 connect the emitter of Q1 to the emitter of Q2 . is therefore considerably lower: Solution Rout = 1 + gm1 g 1 jjrO2 jjr1 rO1 + g 1 jjrO2 jjr1 : m2 m2 In fact. r1 and since gm1 gm2 (why?). since 1=gm2 rO 2 . 2007 at 13:42 424 (1) 424 Cha . Transistor Q2 now o erates as a diode connected dev ice (rather than a current source).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thereby resenting an im edance of 1=gm2 jjrO2 (rather than rO2 ) at node X . Given by (9. 9.

7(b).Rout 1 + gm1 rO1 + g 1 m2 m2 2rO1 : g The same observations a ly to the to ology of Fig. . 9.

9. Assume n Cox = 100 A=V2 and = 0:1 V. Illustrated in Fig.21) Exercise Estimate the out ut im edance for a collector bias current of 1 mA and VA = 8 V. im lying that the out ut im edance is ro ortional to the intrinsi c gain of the cascode device. rO2 . Exam le 9. (9. 9.8.8 MOS cascode current source and its equivalent.23) where it is assumed gm1 rO1 rO2 rO1 .5 mA.3) for degenerated stages sugge sts that cascoding can also be realized with MOSFETs so as to increase the out u t im edance of a current source. ¡ . source. For sim licity.19) (9.(9. the idea is to re lace the degeneration resistor with a MOS current R out V b1 X V b2 M2 M1 Vb R out M1 r O2 Figure 9.3) can now be written as Rout = 1 + gm1 rO2 rO1 + rO2 (9. gm1rO1 rO2 .22) (9.20) (9. thus resenting a small signal resistance of rO2 from X to ground. assume M1 and M2 in Fig.23) is an extremely im o rtant result.5 Design an NMOS cascode for an out ut im edance of 500 k and a current of 0. MOS Cascodes The similarity of Eqs. Equation (9.1) and (9.1 .8 are identical (they need not be). Equat ion (9.

24) = rO2 = ID . we require that gm1 = 800 . 9.6 for the MOS counter art (Fig.1 Cascode Stage 425 We must determine W=L for both transistors such that Solution gm1 rO1 rO2 = 500 k : Since rO1 (9.1 and hence (9.9 MOS cascode viewed as stack of M1 ato of M2 .9).25) 1 2nCox W ID = 800 : L It follows that We should also note that gm1 rO1 W = 15:6: L = 25 1. Rout.cls v.26) Exercise What is the out ut resistance if W=L = 32? Invoking the alternative view de icted in Fig. 9. (9. 2007 at 13:42 425 (1) Sec. This obser vation reveals an interesting oint of contrast between bi olar and MOS cascodes : in the former. recognize that stacking a MOSFET on to of a current source “boosts” the im edance b y a factor of gm2 rO2 (the intrinsic gain of the cascode transistor).4 This is because in MOS .bi = rO1 . whereas in the latter. raising rO2 eventually leads to Rout.1 = 20 k r . we R out R out = r O2 V b2 M2 V b1 X V b2 M2 M1 g m1 r O1 r O2 Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.MOS = gm1 rO1 rO2 increases with no bound. 2006] June 30.

It is the refore ossible to rewrite (9. 9. (9. Determi ne the out ut resistance.22).27) ¡ . has a eared in a cascode as shown in Fig. Figure 9.23) as Exam le 9. We observe that R is in arallel with rO1 .10 illustrates a PMOS ca scode.11. other second order effects limit the out ut im edance of MOS casco des. a large arasitic resistor.devices. and r are in nite (at low frequencies). During manufacturing. R . The out ut resistance is given by (9.6 Solution Rout = gm1 rO1 jjR rO2 : 4 In reality.

9. 2006] June 30.12. 2007 at 13:42 426 (1) 426 Cha . and the “short circuit transconductance” of t he circuit is ¡ ¡ ¡ Rout = 1 + gm1 rO2 rO1 jjR + rO2 : ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In f act. 9 VDD V b2 X V b1 M1 R out M2 Cascode Stages and Current Mirrors Figure 9.12 Com utation of transconductance for a circuit. we de ned the transconductance of a transistor as the cha nge in the collector or drain current divided by the change in the base emitter or gate source voltage. we need to understand the conce t of the transconductance for circui ts.22). As illustrated in Fig. For our s tudy below. the out ut voltage is set to zero Circuit i out ac GND v in Figure 9. be shorting the out ut node to ground. we return to the original equatio n.cls v.10 PMOS cascode current source. (9.11 If gm1 rO1 jjR is not much greater than unity. substituting rO1 jjR for rO1 : (9. R out M1 V b1 V b2 M2 RP Figure 9. In Cha ters 4 and 6.1.28) Exercise What value of R degrades the out ut im edance by a factor of two? 9. This conce t can be generalized to circuits as well. the out ut im edance and the gain of am li ers are closely related.2 Cascode as an Am li er In addition to roviding a high out ut im edance as a current source. the cascode to ology can also serve as a high gain am li er.

9. 2007 at 13:42 427 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13 As de icted in Fig. (9.7 Calculate the transconductance of the CS stage shown in Fig. Exam le 9.33) where Rout denotes the out ut resistance of the circuit (with the in ut voltage . write Solution Gm = ivout in iD1 =v GS 1 = gm1 : Thus. in this case. noting t hat RD carries no current (why?). 9. 9. we short the out ut node to ac ground and.32) Exercise How does Gm change if the width and bias current of the transistor are doubles? Lemma The voltage gain of a linear circuit can be ex ressed as Av = .31) (9.cls v.5 Note the direction of iout in Fig.12.30) (9.13(b).1 Cascode Stage 427 de ned as Gm = ivout jvout=0 : in (9. (9.13(a). 2006] June 30. the transconductance of the circuit is equal to that of the transistor.29) The transconductance signi es the “strength” of a circuit in converting the in ut volt age to a current. 9.Gm Rout . VDD RD v out v in M1 (a) VDD RD i out M1 (b) ac GND v in Figure 9.

Norton’s theorem states that iout is obtained by shor ting the out ut to ground vout = 0 and 5 While omitted for sim licity in Cha ters 4 and 6. = 0 is also required for the transconductance .set to zero). That is. 9. the collector or drain must by shorted to ac ground. Proof We know that a linear circuit can be re laced with its Norto n equivalent [Fig. the condition vout of transi stors.14(a)].

15 Solution ¡ ¡ ¡ . 2006] June 30. (b) com utation of short circuit out ut current .14 (a) Norton equivalent of a circuit. com uting the short circuit current [Fig.ioutRout = .14(b)]. 9. Thus. in Fig. 9 Cascode Stages and Current Mirrors Vout v in i out R out Vout (a) i out v in (b) Figure 9.cls v. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34) (9.36) iX Q1 vX (a) (b) (c) Figure 9.35) vout = .8 Determine the voltage gain of the common emitter stage shown in Fig. Gm = iout =vin . 9.Gm vin Rout and hence (9.G R : m out vin Exam le 9. We also relate iout to vin b y the transconductance of the circuit. vout = . VCC I1 v out v in Q1 v in Q1 i out ac GND (9. 2007 at 13:42 428 (1) 428 Cha .14(a).15(a).

. Gm = ivout in = gm1 : (9.37) (9. 9. we lace an ac s hort from the out ut to ground and nd the current through it [Fig.To calculate the short circuit transconductance of the circuit. gm1 vin .e. i. iout is sim ly equal to the collector current of Q1 . In t his case.15(b)].38) ¡ .

1. the small signal current. thus generating an out ut voltage equal to . 2007 at 13:42 429 (1) Sec. 9. (b) use of cascode to increase the out ut im edance. The t ransconductance falls but the ou ut resistance rises. Av = .16(b). 9.42) Exercise Su ose the transistor is degenerated by an emitter resistor equal to RE . we obtain the o ut ut resistance as de icted in Fig. the collector load im edan ce must be maximized. roduced by Q1 ows through rO1 . VA : V T (9.41) (9. 9. as in cascodes. Next. 9.gm1rO1 = . gm1 vin .gm1 vin rO1 . an ideal current source serving as the load [Fig.44) In this case.40) Av = .15(c): Rout = vX iX = rO1 : It follows that (9.39) (9. In the limit. from the above lemma.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.43) (9. su ose we stac k a transistor on to of Q1 as shown in Fig. Now. a voltage gain higher than that of a CE stage.cls v. It also ind icates that the voltage gain of a circuit can be increased by raising the out ut im edance. We know from Section 9.gm1rO1 : (9.1 Cascode Stage 429 Note that rO does not carry a current in this test (why?).1 that the circuit achieves a high out ut im edance and.Gm Rout = . 2006] June 30. ¡ ¡ .16 (a) Flow of out ut current generated by a CE stage through rO1 .16(a)] yields a voltage gain of VCC I1 VCC I1 v in Q1 g v m1 in r O1 V b1 v out v in Q1 Q2 v out (a) (b) Figure 9. Does the voltage gain incr ease or decrease? The above lemma serves as an alternative method of gain calculation. Bi olar Cascode Am li er Recall from Cha ter 4 that to maximize the voltage gain of a common emitter stage.

.

9. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. which subseque ntly ows through Q2 and hence through the out ut short: iout = gm1vin : That is. As a commoni out Q2 ac GND i out Q2 r O2 X Q1 v in ac GND Q1 v in (a) g v m1 in g v m1 in r O1 (b) Figure 9. We must therefore verify that only a negligible fraction o f gm1 vin is “lost” in rO1 . this transistor can be viewed as a diode connected device having an im edance of 1=gm2 jjrO2 .46) The reader may view (9. 9 Cascode Stages and Current Mirrors Let us determine the voltage gain of the bi olar cascode with the aid of the abo ve lemma. as shown in Fig. 2007 at 13:42 430 (1) 430 Cha . After all. 2006] June 30. (b) detailed view of (a). As shown in Fig. we have iout = gm1 vin ¡ ¡ ¡ . Dividing gm1 vin between this im edance and rO1 . (9. emitter stage. the short circuit transconductance is equal to iout =vin . the c ollector current of Q1 must s lit between rO1 and the im edance seen looking int o the emitter of Q2 . Q1 still roduces a collector current of gm1 vin .cls v.17 (a) Short circuit out ut current of a cascode.46) dubiously.17(a).17(b).45) Gm = gm1 : (9. Since the base and collector voltages of Q2 are equal.

gm1 rO1 gm1 rO1 jjr2 + 1 .gm1 f 1 + gm2rO1 jjr2 rO2 + rO1 jjr2 g . and hence iout (9.gm1 rO1 gm1rO1 jjr2 : .53) Av = .Gm Rout = . 1=gm2 rO1 jjr2 + g 1 jjrO2 m2 rO1 jjr2 : (9.5).49) (9.47) rO2 . the a roximation Gm = gm1 is reasonable. since Q1 and Q2 carry a roximately equal bias currents. gm1 (9. rO1 .51) gm2 and rO1 rO2 : (9.For ty ical transistors.33) and (9.52) (9.gm1 gm2 rO1 jjr2 rO2 + rO1 jj r2 : Also. Av = . To obtain the overall voltage gain.48) gm1vin : That is. we write from (9.50) (9.

2006] June 30. 9.8.54) gm1 rO1 jjr2 = 65:8 and from (9. Thus. 9. Q2 . V CC I1 v out Q2 CB Vb Stage v in Q1 CE Stage r2 2600 ¡ ¡ .1 . The bi olar cascode of Fig.000? It is ossible to view the cascode am li er as a common emitter stage followed by a commonbase stage. If VA = 5 V and = 100 for both transistors. the idea is to consider the cascod e device.55) Exercise What Early voltage gives a gain of 5. jAv j = 12. 654: Cascoding thus raises the voltage gain by a factor of 65. rO 1 rO2 = 5 k .cls v.18. 9.16(a). (9. (9.9 Solution = 26 .53). We have gm1 Exam le 9. determine th e voltage gain.16(b) is biase d at a current of 1 mA. Assume the load is an ideal current source.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. as a commonbase transistor that senses the small signal current roduced by Q1 . 9. Illustrated in Fig. 2007 at 13:42 431 (1) Sec. This ers ective may rove useful in some cases.1 Cascode Stage 431 Com ared to the sim le CE stage of Fig. r1 . the cascode am li er exhibits a g ain that is higher by a factor of gm1 rO1 jjr2 —a relatively large value because rO1 and r2 are much greater than 1=gm1 .

The high voltage gain of the cascode to ology makes it attractive for many a li cations. An actual current source lowers the im edance seen at the out u t node and hence the voltage gain. the load is assumed to be an ideal current source. the circuit illustrated in Fig. 9.57) rO2 + rO1 jjr2 g rO3 jj gm2 rO2 rO1 jjr2 + rO1 jjr2 : .18 Cascode am li er as a cascade of a CE stage and a CB stage.16(b).56) (9. dro ing the out ut im eda nce to Rout = rO3 jj f 1 + gm2 rO1 jjr2 (9. in the circuit of Fig. For exam le. But.19(a) suffers from a low gain because the n current source introduces an im edance of only rO3 from the out ut node to ac ground. 9.Figure 9.

gm1 f gm2rO2 rO1 jjr2 jj gm3 rO3 rO4 jjr3 g : ¡ Ron gm2 rO2 rO1 jjr2 Ro gm3 rO3 rO4 jjr3 : ¡ . Exam le 9. since n n and n devices may dis lay different Early voltages.7). 9. 9 Cascode Stages and Current Mirrors VCC V b3 VCC V b2 Q3 v out V b1 v in Q2 Q1 V b1 v in Q2 Q1 R out VCC r O3 V b2 v out V b1 v in Q2 Q1 Q4 Q3 R o R on (a) (b) Figure 9. How should we realize the load current source to maintain a high gain? We know f rom Section 9. (b) use of ca scode in the load to raise the voltage gain.cls v.1 that cascoding also raises the out ut im edance of current sou rces.60) (9. What is the voltage gain? n transistors with Solution The load transistors carry a collector current of a roximately 1 mA. res ect ively.19 (a) Cascode with a sim le current source load.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this gain is about half of that ex ressed by (9. we ex ress the voltage gain as (9. Recognizing that the short circuit tr ansconductance.63) Av = . Ron and Ro .5 is a good candidate and arriving at the stage de icted in Fig.1.19(b). Ro = gm3 rO3 rO4 jjr3 = 151 k and (9.59) Note that.61) This result re resents the highest voltage gain that can be obtained in a cascod e stage. we have (9. ostulating that the circuit of Fig.gm1Ron jjRo . Thus. of the stage is still a roximately equal to gm1 (why?). 9.53).10 Su ose the circuit of Exam le 9.62) (9. The out ut im edance is now given by the arallel combination of those of the n n and n cascodes. rO1 ( = rO2 ) may not be equal to rO3 (= rO4 ) .58) (9. 2006] June 30. 2007 at 13:42 432 (1) 432 Cha . Using (9.9 incor orates a cascode load using VA = 4 V an d = 50. Gm . For com arable values of Ron and Ro .

64) .Ron = 329 k : (9.

gm1rO1 gm2 rO2 : ¡ ¡ ¡ jAv j = gm1 Ron jjRo = 3. 9. load.68) (9. the gain has fallen by a roximately a factor of 3 because the n devices suffer from a lower Early voltage and . the lemma illustr ated in Fig. (b) realization of load by a PMOS cascode. allowing straightforward calculation of the out ut im edance. CMOS Cascode Am li er The foregoing analysis of the bi olar cascode am li er can readily be extended to the CMOS counter art.cls v. 981: . 9.5 mA. 2006] June 30.66) Com ared to the ideal current source case. Moreover.1 Cascode Stage 433 It follows that (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The cascode of Fig.14 utilizes our knowledge of the out ut im edance to quickly rov ide the voltage gain of the stage.20 (a) MOS cascode am li er.22). this stage also rovides a short circuit transconductance Gm out ut resist ance is given by (9. 9. Exercise Re eat the above exam le for a collector bias current of 0. yielding a voltage gain of gm1 if 1=gm2 rO1 .Gm Rout .67) (9.20(a) with an ideal current source VDD V b2 V b2 VDD I1 v out V b1 X v in M1 (a) M4 M3 v out M2 X M1 (b) R o R on V b1 v in M2 Figure 9. It is im ortant to take a ste back and a reciate our analysis techniques. 2007 at 13:42 433 (1) Sec.19(b) roves quite formidable if we attem t to re lace each tr ansistor with its small signal model and solve the resulting circuit. 9. De icted in Fig. The (9.gm1 1 + gm2 rO2 rO1 + rO2 .65) (9. Our gradua l a roach to constructing this stage reveals the role of each device.69) Av = .

Note. Since an d r are in nite for MOS devices (at low frequencies). that M1 and ¡ . com ared to a sim le common source stage.69). however. the voltage gain has r isen by a factor of gm2 rO2 (the intrinsic gain of the cascode device). we can also utilize (9.In other words.53) to arrive at (9.

As with the bi ol ar counter art. If n Cox = 100 A=V2 . 9 Cascode Stages and Current Mirrors M2 need not exhibit equal transconductances or out ut resistances (their widths and lengths need not be the same) even though they carry equal currents (why?).4 = 40.20(b).74) ID1.2 = 577 . 2007 at 13:42 434 (1) 434 Cha . Illustrated in Fig.73) (9. determine the voltage gain.1 and s : .2 gm1. 9. gm1 rO3 = rO4 .1 and = 0:15 V. 9.cls v. gm3 = gm4 . the ci rcuit exhibits the following out ut im edance com onents: Ron gm2 rO2 rO1 Ro gm3 rO3 rO4 : The voltage gain is therefore equal to (9. W=L3.1 . and (9.2 = 2nCox L 1. 2006] June 30. the MOS cascode am li er must incor orate a cascode PMOS current s ource so as to maintain a high voltage gain.11 (9. With the articular choice of device arameters here.71) Av . We have Solution = gm2 .2 = 30. ID1 = = ID4 = 0:5 mA.gm1 gm2 rO2 rO1 jjgm3 rO3 rO4 Exam le 9.20(b) incor orates the following device arameters: W=L1. n = 0:1 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Cox = 50 A=V2 .70) (9.72) The cascode am li er of Fig. rO1 = rO2 .

79) (9.4 = 13:3 k : Equations (9.2 = 20 k and (9.70) and (9.76) (9.W gm3.1 : Also.77) rO3.78) (9.82) Av = .75) rO1.318: .80) (9.71) thus res ectively give (9.gm1Ron jjRo Ron and 693 k Ro 250 k . (9.4 = 707 .2 = I1 n D1.81) (9.

for a desired current I 1 . Another critical issue in biasing relates to ambient tem erature variations. this voltage ex eriences some var iation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. contai ns two tem erature de endent arameters: VT = kT=q and IS .2 Current Mirrors 9. for exam le. 9. The rechargeable battery in a cell hone or la to com uter. Thus. For exam le.2. however.25 mA. 9. To understand how te m erature affects the biasing. a MOS current sourc e biased by means of a resistive divider suffers from de endence on VDD and tem erature.cls v. consider the bi olar current source shown in Fig. the bias current of CE and CS stages is a function of the su ly voltage—a serious issue because in ractice.21(b). Here.1 Initial Thoughts The biasing techniques studied for bi olar and MOS am li er s in Cha ters 4 and 6 rove inadequate for high erformance microelectronic circ uits. I1 does not. R1 and R2 divide VCC down to the required VBE . 9.2 Current Mirrors 435 Exercise Ex lain why a lower bias current results in a higher out ut im edance in the abo ve exam le. Illustrated in Fig. what ha ens if the tem erature varies ? The left hand side remains constant if the resistors are made of the same mate rial and hence vary by the same ercentage. where VCC R1 I1 Q1 R2 VBE (a) VDD R1 I1 M1 R2 VGS (b) Figure 9. VTH 2 L 1+ 2 ¡ ¡ ¡ ¡ ¡ . gradually loses voltage as it is discharged. Calculate the out ut im edance for a drain current of 0. we have R2 I1 (9. thereby mandating that the circuit s o erate ro erly across a range of su ly voltages.21 Im ractical biasing of (a) bi olar and (b) MOS current sources.83) R1 + R2 VCC = VT ln IS . A similar sit uation arises in CMOS circuits. even if the ba se emitter voltage remains constant with tem erature.21(a). 2006] June 30. VTH 2 2 L = 1 n Cox W R R2 R VDD . where the base current is neglected. 9.20 C in Finland and +50 C in Saudi Arabia. 2007 at 13:42 435 (1) Sec. The right hand side. we can write I1 = 1 n Cox W VGS . A cell hone must maintain its erformance at . That is. But.

84) : (9.2 (9.85) .

The golden current generated by a bandga reference is “read” by the curre nt mirror and a co y having the same characteristics as those of IREF is roduce d. Unfor tunately. In orde r to avoid su ly and tem erature de endence. VCC I REF I co y Current Mirror Figure 9.22 Conce t of current mirror. For exam le. In summary. e. an elegant method of creating su ly and tem erature inde endent voltages and c urrents exists and a ears in almost all microelectronic systems. this scheme is studi ed in more advanced books [1].22 conce tually illustrates our g oal here. Figure 9. Fortunately.23(a). Ico y = IREF or 2IREF . The bandga circuit by itself does not solve all of our roblems! An integrated circuit may incor orate hundreds of current sourc es.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. I1 is n ot constant even if VGS is. (The MOS counter art is similar. a bandga reference can rovide a “g olden current” while requiring a few tens of devices. 9 . the ty ical biasing schemes introduced i n Cha ters 4 and 6 fail to establish a constant collector or drain current if th e su ly voltage or the ambient tem erature are subject to change.. 9 Cascode Stages and Current Mirrors Since both the mobility and the threshold voltage vary with tem erature. 2007 at 13:42 436 (1) 436 Cha . Current mirrors serve this ur ose. as the load im edance of CE or CS stages to achieve a high gain.2. where Q1 o erates in th e forward active region and the black box guarantees Ico y = IREF regardless of tem erature or transistor characteristics. 2006] June 30. the com lexity of the bandga rohibits its use for each current sourc e in a large integrated circuit.g. Let us summarize our thoughts thus far. 9. We must therefore seek a met hod of “co ying” the golden current without du licating the entire bandga circuitry . Called the “band ga reference circuit” and em loying several tens of devices.2 Bi olar Current Mirror Since the current source generating Ico y in Fig. we surmise that the curr ent mirror resembles the to ology shown in Fig.22 must be im lemented as a bi olar or MOS transistor. 9.cls v.) VCC I REF X VBE (a) (b) (c) VCC I co y I REF Q REF V1 I REF Q REF VCC I co y ? Q1 X Q 1 Current Mirror ¡ ¡ .

(b) voltage ro orti onal to natural logarithm of current.86) . V T (9. How should the black box of Fig. (c) bi olar current mirror.23(a) be realized? The black box generates an out ut voltage.23 (a) Conce tual illustration of current co ying. such that Q1 carries a current equal to IREF : IS1 ex VX = IREF .Figure 9. VX = VBE . 9.

thereby yielding Ico y = IREF . 9. F rom one ers ective. Ex lain what ha ens. For now.cls v. S.24). V1 = VX if IS. This holds even thou gh VT and IS vary with tem erature.87). we can write IREF = IS. 2007 at 13:42 437 (1) Sec. Fortunately. Negle cting the base current in Fig. VCC I REF Q REF I co y ? ¡ ¡ ¡ . we have V1 = VT ln IIREF . 2006] June 30. Thus. 9.e.REF denotes the reverse saturation current of QREF .. 9. i.88) where IS.. Note that VX does vary with tem erature but such that Ico y does not. We say Q1 “mirrors” or co ies the current owing through QREF . Exam le 9. i. a single diode connected device satis es (9. QREF takes the natural logarithm of IREF and Q1 takes the e x onential of VX . From another ers ective.90) Ico y = I IS1 IREF .91) which reduces to Ico y = IREF if QREF and Q1 are identical.12 An electrical engineering student who is excited by the conce t of the current m irror constructs the circuit but forgets to tie the base of QREF to its collecto r (Fig. if QREF is identical to Q1 . dis laying the current mirror circuitry.REF (9. the black box satis es the following relati onshi : VX = VT ln IREF : I S1 (9.89) (9. the inverse function of bi olar transistor ch aracteristics.2 Current Mirrors 437 where Early effect is neglected.23(c) consol idates our thoughts. we neglect the base currents. sin ce QREF and Q1 have equal base emitter voltages.e.87) We must therefore seek a circuit whose out ut voltage is ro ortional to the nat ural logarithm of its in ut.23(b). Figure 9.REF ex VX VT Ico y = IS1 ex VX VT and hence (9. In other words.REF = IS1 .REF (9. S.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Q1 Figure 9.24 Solution The circuit rovides no ath for the base currents of the transistors. More fund amentally. ¡ . the base emitter voltage of the devices is not de ned. The lack of the base currents translates to Ico y = 0.

j = IS. thus arriving at the circuit shown in Fig.13 Realizing the mistake in the above circuit. Exercise Su ose VX is slightly greater than the necessary value. Here.87).25. VT lnIREF =IS.26(b) for sim licity. Ex lain what ha ens.21.22(c).e. how do we obtain different values for these co ies. The circuit is often drawn as in Fig.cls v. 5IREF .? Consideri ng the to ology in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. 2IREF .. how do we make additional co ies of IREF to feed different arts of an integrated circuit? Second. 9 Cascode Stages and Current Mirrors Exercise What is the region of o eration of QREF ? Exam le 9. Q1 now carries a nite current. the student makes the modi cation show n in Fig. ho ing that the battery VX rovides the base currents and de nes t he base emitter voltage of QREF and Q1 .93) ¡ ¡ . yields (9. along with (9. 2007 at 13:42 438 (1) 438 Cha . The student has forgotten that a diodeconnected device is necessary here to ensure that VX remains ro ort ional to lnIREF =IS. 9. the biasing of Q1 is no different from that in Fig . etc. In what region does QREF o erate? We must now address two im ortant questions. 9.j ex VX . 9. Ico y = IS1 ex VX . First. VCC I REF Q REF VX I co y ? I REF Q REF VX VX VCC I co y ? Q1 Q1 Figure 9. V T (9.26(a). given by Ico y..92) which is a function of tem erature if VX is constant. V T which. 2006] June 30.REF . 9. we recognize that VX can serve as the base emit ter voltage of multi le transistors.R EF . 9. tra nsistor Qj carries a current Ico y.j .25 Solution While i. e.

REF (9.94) .j = I IS.j IREF : S.Ico y.

the n Ico y. VCC I REF Q REF 0.14 A multistage am li er incor orates two current sources of values 0.94) readily answers the second question as well: If IS.j ( the emitt er area of Qj ) is chosen to be n times IS.cls v. all transistors are identical to ensu re ro er scaling of IREF . (b) sim li ed drawing of ( a).75 mA and 0. Here.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Using a bandga reference current of 0. The key oint here is that multi le co ies of IREF can be generated with minimal additional com lexity because IREF and QREF themselves need not be du licated.27 illustrates the circuit.25 mA. Solution Figure 9.REF ( the emitter area of QREF ). roviding Ico y = 3IREF .2 Current Mirrors VCC I REF Q REF I co y1 I co y2 I co y3 439 Q1 Q2 Q3 (a) VCC I REF Q1 Q REF (b) VCC I co y1 Q2 I co y2 Q3 Q REF (c) I co y3 I REF Q1 Q2 I co y = 3 I REF Q3 Figure 9.5 m A. Equation (9. Neglect the effect of the base current for now. design the required current sou rces. We say the co ies are “scaled” with res ect to IREF . F igure 9. 9.26 (a) Multi le co ies of a reference current.75 mA ¡ . Recall fro m Cha ter 4 that this is equivalent to lacing n unit transistors in arallel. (c) combining out ut currents to generate larger co ies. Exam le 9.26(c) de icts an exam le where Q1 Q3 are identical to QREF .25 mA 0.j = nIREF . 2007 at 13:42 439 (1) Sec. 2006] June 30.

Q1 Q2 Q3 0.5 mA Q4 Q5 Figure 9.27 .

Design the current mirror circuit. 9.96) Ico y = 1 IREF : 3 Exam le 9. we ha ve (9. denoted by 10AE for sim licity.95) (9. how do we create fractions of IREF ? Th is is accom lished by realizing QREF itself as multi le arallel transistors.89) and (9.29). 2006] June 30.28 Co ying a fraction of a reference current . to begin with a larger IS. VCC I REF 0. But.REF (= 3IS here) so that a unit transistor. The current of 500 A requires 10 unit trans istors. 9. Re eating the ex ressions in (9. 2007 at 13:42 440 (1) 440 Cha .cls v.90).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we mus t em loy four unit transistors for QREF such that each carries 50 A. A unit trans istor thus generates 50 A (Fig. To roduce the smaller current. can g enerate a smaller current. Ex em li ed by the circuit in Fig.28.2 mA Solution I co y1 X Q1 AE 4A E IREF = 3IS ex and hence VX VT VX Ico y = IS ex V T .15 (9.25 mA I co y Q1 X Q REF1 Q REF2 Q REF3 Figure 9. The use of multi le transistors in arallel rovides an accurate means of scalin g the reference in current mirrors. 9 Cascode Stages and Current Mirrors Exercise Re eat the above exam le if the bandga reference current is 0. the idea is VCC I REF 0. Q1 .97) It is desired to generate two currents equal to 50 A and 500 A from a reference of 200 A.1 mA.

29 .I co y2 Q2 10 A E Figure 9.

so does the error in Icopy . Our o jective is to calculate Icopy .. emitter follower QF is interposed etween the collector £ £ £ £ £ Figure 9. The error ari ses because a fraction of IREF ows through the bases rather than through the coll ector of QREF . Thus.e. Here. However.REF (9.2 Current Mirrors 441 Exercise Re eat the above exam le for a reference current of 150 A. an effect leading to a signi cant error a s the number of co ies (i. Effect of Base Current We have thus far neglected the base current drawn from no de X in Fig.30 Error due to ase currents. where AE and nAE denote one unit transistor and n unit transistors. 2006] June 30. 9. the second term in the denominator is much less than unity and Icopy nIREF . since IC.26(a) by all transistors. the ipolar current mirror can e modi ed as illustra ted in Fig. To suppress the a ove error.30. VCC I REF Q REF AE I co y nβ I copy Q1 I copy nA E β respectively. the ase currents of Q1 and QREF can e expressed as IB1 = Icopy 1 IB.98) (9.REF = Icopy n : Writing a KCL at X therefore yields (9. the total co ied current) increases.REF + Icopy n + Icopy . 2007 at 13:42 441 (1) Sec.99) 1 IREF = IC. 9 . recognizing that QREF and Q1 still have equal ase-emitter voltages and hence carry currents with a ratio of n. as the copied current ( n) increases. £ £ £ £ .100) = Icopy =n. leads to Icopy = nIREF : 1 + 1 n + 1 (9.101) For a large and moderate n.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9. 9. We analyze the error with the aid of the diagram shown in Fig.31. which.

of QREF and node X . we can repeat the a ove analysis y writing a KCL at X : 1 IC.102) £ £ £ £ £ . More speci cally.F IE.F . there y reducing the effect of the ase currents y a facto r of . (9. assuming IC.F = Icopy + Icopy n .

2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.F I C. 2007 at 13:42 442 (1) 442 Chap.F = Icopy 1 + n : 2 Another KCL at node P gives £ £ £ . o taining the ase current of QF as 1 IB.cls v.F QF X I copy Q1 Cascode Stages and Current Mirrors I copy nA E β Figure 9.31 Addition of emitter follower to reduce error due to ase currents. 9 VCC I REF P Q REF AE I copy nβ I B.

103) IREF = IB.(9.REF .F + IC.

105) Icopy = nIREF : 1 + 12 n + 1 (9.Icopy 1 + 1 + Icopy = 2 n n and hence (9. we write a KCL at X : Example 9. (9.16 Solution IREF = IC. 9. 9.108) Icopy1 = IREF 4 + 15 Icopy2 = 10IREF : 15 4+ With the addition of emitter follower (Fig.106) That is. Compute the error in Icopy1 and I copy2 in Fig. Icop y2 .REF : copy1 Thus.REF = 4I + Icopy1 + 10Icopy1 + IC. the error is lowered y a factor of .107) (9. we have at X : (9.104) (9.110) £ £ .109) (9.REF (the total current owing through four unit transistors) still ret ain their nominal ratios (why?).REF + Icopy1 + Icopy2 + IC.32). Noting that Icopy1 .29 efore and after adding a follower. and IC.

116) Icopy2 = 10IREF : 15 4+ 2 (9.e. where a cur rent source serves as a load to achieve a high voltage gain. 2006] June 30. The current source .F = IC.117) Exercise Calculate Icopy1 if one of the four unit transistors is omitted.113) IREF = 15Icopy1 + IC. i.. 2007 at 13:42 443 (1) Sec. 2 (9.33(a).114) (9.2 Current Mirrors VCC I REF P 0. 9. the reference transistor has an area of 3AE . PNP Mirrors Consider the common-emitter stage shown in Fig.REF + Icopy1 + Icopy2 = 4Icopy1 + Icopy1 + 10Icopy1 = 15Icopy1 : A KCL at P therefore yields (9.32 IC.2 mA 443 QF Q 1 X 4A E I copy1 AE I copy2 Q2 10 A E Figure 9.115) copy1 and hence Icopy1 = IREF 15 4+ 2 (9.REF 2 = 15Icopy1 + 4I . 9.112) (9.111) (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

9. We must therefore de ne the ias current of Q2 properly.23(c). In analogy with the np n counterpart of Fig. £ £ £ £ £ .33( ) ]. 9. 9 .can e realized as a pnp transistor operating in the active region [Fig.33(c). For example. if QREF and Q2 are identical and the ase currents negligi le. we form the pnp current mirror depicted in Fig. then Q2 Q1 carries a current equal to IREF .

Q1 and Q2 are iased at a current of 700 A.npn VA. ( ) realization of current so urce y a pnp device.33(c) for a voltage gain of 100 and a power udget of 2 mW. From t he power udget and VCC = 2:5 V. 9. a fundamental constant of the technology and independent of the ias current.85:5: £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ ¢ . In the mirror of Fig. 9. 9. of wh ich 100 A is dedicated to IREF and QREF .34. Assume VA.npn + VA. 2006] June 30. QREF incorporates one unit device and Q1 seven unit devices.cls v. (c) proper iasing of Q2 .33 (a) CE stage with current-source load. 9 VCC V v out v in Q1 v in Q1 Q2 v out Cascode Stages and Current Mirrors VCC Q REF X v in Q2 v out I REF Q1 VCC I1 (a) ( ) (c) Figure 9. there y forcing the same current through Q2 and Q1 .gm1rO1 jjrO2 = . QREF 2 .pnp = 4 V. requiring that the (emitter) area of Q2 e 7 times that of QREF . V1 (9.23(c). and VCC = 2:5 V.33(c) it ows from X to ground. we o tain a total supply current of 800 A. QM .5! This is ecause the gain of the stage is simply given y the Early voltage s and VT . 9. the circuit’s gain cannot reach 100. Assuming for simplicity that QREF 1 .npn = 5 V.119) (9. How do we generate the latter from the former? It is po ssi le to com ine the npn and pnp mirrors for this purpose. with the a ove choice of Early voltages. we o serve that QM draws a current of IREF f rom QREF 2 .120) What happened here?! We sought a gain of 100 ut inevita ly o tained a value of 85. Exercise What Early voltage is necessary for a voltage gain of 100? We must now address an interesting pro lem. (For example.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and Q2 are identica l and neglecting the ase currents. VA. 2007 at 13:42 444 (1) 444 Chap. Thus.) The volt age gain can e written as Solution Av = . IREF = 100 A. as illustrated in Fi g.pnp T A. whereas in Fig. Thus. Example 9. We can also cr VVA.17 esign the circuit of Fig.pnp = .118) (9. it is assumed that the golden current ows from VCC to node X .

34 at a collect or current of 1 mA while IREF Example 9. We wish to ias Q1 and Q2 in Fig. 9.18 = 25 A.M onto IC 2 . Note that the ase currents introduce a cumulative error as IREF is copied onto IC. £ £ £ £ .M . and IC.eate various scaling scenarios etween QREF 1 and QM and etween QREF 2 and Q2 .

Icopy is 30 higher than IREF .2 Current Mirrors VCC I REF I C. £ £ £ . 16 units. the four transistors in the current mirror n the latter case. Random variations during manufac turing may lead to changes in the device parameters and even the emitter area. the npn and pnp scaling factors se. A s a result. Unfort unately. This is why cu rrent mirrors are rarely used in discrete design. Solution It is possi le that the two transistors were fa ricated in different atches and hence underwent slightly different processing. Note that we have M = 40IC. Explain why. 9.121) (9.M = 8IREF jIC 2 j = 5IC. For an overall scaling factor of 1 mA=25 A = 40. and i implicitly dismissed the case IC.M = 10IREF jIC 2 j = 4IC.REF 1 and IC 2 = IC. 2007 at 13:42 445 (1) Sec.23(c).cls v. necessitate 43 units. the two transistors suffer from signi cant IS mismatch.M Q REF1 X1 QM Q REF2 X2 v in Q2 v out Q1 445 Figure 9.REF 2 as it would can e swapped. Exercise How much IS mismatch results in a 30% collector current mismatch? £ £ £ (In each case.122) IC. Choose the scaling factors in the circuit so as to minimize the num er of unit t ransistors.19 An electrical engineering student purchases two nominally identical discrete ip olar transistors and constructs the current mirror shown in Fig. 9.M : (9.M or (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.) In the former ca circuitry require 15 units. Example 9.124) Exercise Calculate the exact value of IC 2 if = 50 for all transistors.34 Generation of current for pnp devices. 2006] June 30.123) (9. we can choose either Solution IC.

.

drawing the MOS counterpart of Fig.3 MOS Current Mirror The developments in Section 9.2. we recognize that the lack ox must generate VX such t hat V I REF X M1 VGS (a) ( ) (c) ? X M 1 Current Mirror Figure 9.35(a). 2007 at 13:42 446 (1) 446 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 C W 2 n ox L £ ¢¢ V ¢¢ V I copy1 I REF M REF VX I REF M REF I copy £ £ £ £ ¢¢ £ . (c) MOS curr ent mirror.35 (a) Conceptual illustration of copying a current y an NMOS device. 9. In particular.2 can e applied to MOS current mirrors as well.cls v. 2006] June 30.2.2 3(a) as in Fig. ( ) generation of a voltage proportional to square root of current. 9 Cascode Stages and Current Mirrors 9. 9.

the lack ox must satisfy t he following input (current)/output (voltage) characteristic: vuutVX Cox 2IREF n = u £ £ .125) where channel-length modulation is neglected. (9. Thus.1 VX . VTH 1 2 = IREF .

35(c).35( )]. As with the ipolar ve rsion. it must operate as a “square-root” circuit. thus arri ving at the NMOS current mirror depicted in Fig.126) That is. we can view the circuit’s operation from two perspectives: (1) MREF takes t he square root of IREF and M1 squares the result. VTH £ £ £ ¢ . 9. 9. From Chapter 6. or (2) the drain currents of t he two transistors can e expressed as 2 I . we recall that a diodeconnected MOSFET provides such a characteristic [Fig.W L + VTH 1 : 1 (9.REF = 1 n Cox W 2 L REF VX .

VTH 2 .1 Icopy = 2 n Cox W VX . L 1 .

(9.128) where the threshold voltages are assumed equal. It follows that which reduces to Icopy = IREF Icopy = .127) (9.

L REF if the two transistors are identical. .WL 1 IREF .

20 The student working on the circuits in Examples 9.129) Example 9.36).12 and 9.W (9. Explain what happens.13 decides to try the MOS counterpart. . 9. thinking that the gate current is zero and hence leaving the g ates oating (Fig.

26. an initial condition created at node X when the power supply is turned on.cls v. they can assume any voltag e. e.36 Solution This circuit is not a current mirror ecause only a diode-connected device can e sta lish (9.3 mA I REF W 3( ( L £ ¢ £ ¢¢ ¢¢ ¢¢ ¢¢ ¢¢ .37(a).2 mA V V in2 M2 Vout2 0.129) and hence a copy current independent of device parameters and t emperature. 2006] June 30. The following example illustrates these c oncepts. In other words. Example 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. esign a current mirror that produces I1 and I2 from a 0. 9.g.21 An integrated circuit employs the source follower and the common-source stage sh own in Fig. 2007 at 13:42 447 (1) Sec.5 mA I1 (a) I2 V V in2 M2 Vout2 I2 M I2 5( M1 Vout1 I1 M I1 M REF 2( ¢¢ V V in1 V 0.3mA reference. V V in1 M1 Vout1 0. 9.2 Current Mirrors V I REF X M REF Floating Node 447 I copy ? M1 Figure 9. Icopy is very poorly de ned.. Exercise Is MREF always off in this circuit? Generation of additional copies of IREF with different scaling factors also foll ows the principles shown in Fig. 9. Since the gates of MREF and M1 are oating.

37 £ .W ( L ( ) W ( L Figure 9.

34.29.38 exempl i es these ideas. this effect mandates circuit modi cations that are descri ed in mor e advanced texts [1]. The circuit of Fig. The idea of com ining NMOS and PMOS current mirrors follow s the ipolar counterpart depicted in Fig.cls v. 37( ) shows the overall circuit. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 MOS mirrors need not resort t o the technique shown in Fig. 9. Investigated in Pro lem 53. we select an aspect ratio of 3W=L for the diode-connected device. and 5W=L for MI 2 . 2W=L for MI 1 . resulting in a hig h output impedance. On the other hand. The cascode topology can also e considered an extreme case of source or emitter degeneration. 9.31.38 NMOS and PMOS current mirrors in a typical circuit. £ ¢¢ CS Stage V ¢¢ Vout1 V ¢¢ V I REF V in1 V in2 £ £ £ £ £ £ £ . Solution Exercise Repeat the a ove example if IREF = 0:8 mA. CS Stage Follower Vout2 M REF V in3 Follower V in4 Vout3 Vout4 Figure 9. 9 Cascode Stages and Current Mirrors Following the methods depicted in Figs. 9. 2007 at 13:42 448 (1) 448 Chap. Figure 9.3 Chapter Summary Stacking a transistor atop another forms a cascode structure. 2006] June 30. 9. channel-length modulation in the current-source transistors does lead to additional errors. Since MOS devices draw a negligi le gate current.28 and 9.

6 In deep-su micron CMOS technologies. This effect is eyond the scope of this ook. leading to “tunneling” and hence noticea le gate current. £ £ £ £ . the gate oxide thickness is reduced to le ss than 30 A.

Suppose t he circuit of Fig.42.40.17 A and = 100 for ot V 2 for a ias current of 1 the value of V 1 such that 300 mV. assuming a ias current of 0.5 mA.3 Chapter Summary 449 The voltage gain of an ampli er can e expressed as . ue to a manufacturing error. (a) Repeat Pro lem 1 for this circuit. where Gm denotes th e short-circuit transconductance of the ampli er. Estimate the maximum allowa le ias current if each transistor sustains a ase-collector forward ias of 200 mV. 9. In the ipolar cascode stage of Fig.2(a). 9.cls v. we have chosen RC = 1 k and VCC = 2:5 V. Setting the ias currents of analog circuits to well-d e ned values is dif cult. 2006] June 30. IC 1 = 0:5 mA while IC 2 = 1 mA. Figure 9. 2.5 mA. 2007 at 13:42 449 (1) Sec. The load of a cascode stage is also realized as a cascode circuit so as to approach an ideal current source. Repeat Example 9. 4. Neglect the Early effect. 9. 5. Current mirr ors are rarely used in disrcete design as their accuracy depends on matching et ween transistors. assuming I 1 is ideal and equal to 0.39. ( ) Wi th the minimum allowa le value of V 1 . 9. 9. (a) Compute mA. VBE 1 . Current mirrors can “copy” a well-de ned refere nce current numerous times for various locks in an analog system. With i ts high output impedance. resistive dividers tied to the ase or gate o f transistors result in supply. then IC or I are not.39. a cascode stage can operate as a high-gain ampli er. where Q3 plays the ro le of £ £ £ £ £ £ £ Pro lems 1.. This relationship indicates that the gain of ampli ers can e maximized y maximing their output impedance. ( ) Noting that VCE 2 = V 1 . Consider the cas £ £ £ £ ¢ £ £ £ £ £ £ £ ¢ £ £ £ ¢ £ £ £ £ £ £ £ £ £ £ £ . VCC RC V1 V 1 V 2 Q1 Q2 6 10. Current mirro rs can scale a reference current y integer or non-integer factors.Gm Rout . 9. i.1 for the circuit shown in Fig. 9. determine Q2 experiences a ase-collector forward ias of only code stage depicted in Fig.41 is realized as shown in Fig. etermine the output resistance in each case.41. compute the maximum allowa le value of R C such that Q1 experiences a ase-collector forward ias of no more than 300 mV. IS = h transistors. If VBE or VGS are well-de ned. a parasitic resistor RP ha s appeared in the cascode circuits of Fig.39 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.e.and temperaturedependent currents. where VCC = 2:5 V. 6. In the circuit of Fig. For example.

Assuming VA1 = VA2 = VA.44. £ £ £ £ R out VCC V 1 V 2 Q1 Q2 Q3 V 3 £ £ £ £ £ £ £ 450 R out V 1 RP V 2 Q2 V 2 Q2 Q1 V 1 Q1 RP R out £ £ £ £ £ £ £ £ £ £ .n and VA3 = VA. 9.40 R out VCC V 1 V 2 Q1 Q2 I1 Figure 9. Excited y the output impedance “ oosting” capa ility of cascodes.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. arriving at the circuit shown in Fig.43 student can achieve? Assume the transistors are identical.p .42 circuit.41 Figure 9. While constructing a cascode stage. 7. 9 Cascode Stages and Current Mirrors R out R out V 1 RP RP V 2 Q2 Q1 V 1 Q2 V 2 Q1 (a) ( ) (c) (d) Figure 9. 9. determine the output impedance o f the V n Qn Figure 9. 2006] June 30. 2007 at 13:42 450 (1) Chap. 8. a student adventurously swaps the collector and ase terminals of the degeneration transistor.cls v. a stu dent decides to extend the idea as illustrated in Fig. What is the maximum output impedance that the R out V 1 V 2 Q1 Q2 I1 .43.

9.5 mA to a circuit. 9. What is the minimum tolera le value of V 1 if M2 must remai n in saturation? ( ) Assuming = 0:1 V.45 11.1 .5 V V 2 V 1 Q2 X Q1 Circuit 0. Assume 1. Assume n Cox = 100 A/V2 and VTH = 0:4 V. 9. compute the maximum tolera le value of .45 must provide a ias current of 0. 9. Assume n Cox = 10 0 A/V2 and VTH = 0:4 V. W=L1 = 20=0: 18. 12. Consider the circuit shown in Fig. Explain which ones are considered cascode stages .23) in terms of I and plot the result as a function of I . For discrete ipolar transistors. 9. compute the req uired value of V 2 .5 mA Figure 9. calculate the output impedance of the circuit. If VCC = 2. 14. (a) Calculate the required value of V 2 .44 (a) Assuming oth transistors operate in the active region. The pnp casc ode depicted in Fig. The MOS cascode of Fig. 2006] June 30. 13. (a) Writing gm = 2n Cox W=LI .cls v.3 Chapter Summary R out V 1 V 2 Q2 Q1 451 Figure 9.9) and explain why the result resem les that in Eq. etermine the output impedance of each circui t shown in Fig. d etermine the maximum allowa le value of V 1 such that Q2 experiences a ase-coll ector forward ias of only 200 mV. 9. ( ) Noting that VX = V 1 + jVBE 1 j. IS = 10.5 mA. If n Cox = 100 A/V2 and W=L = 20=0:18 for oth tr ansistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9) for the ipolar counterpart. 2007 at 13:42 451 (1) Sec. 10. (9. determine the output impedance of the circuit. 15. allowing the approximation VA VT if 100. the Early voltage reaches tens of volts. Using this approximation.47 must provide a ias current of 0. simplify Eq. (9. p ¢ £ £ ¢ £ £ £ ¢¢ £ £ £ £ £ £ £ £ £ £ £ ¢ ¢ £ £ £ £ £ £ £ £ £ £ £ £ £ . (9. where V = 1:8 V.5 mA with an out put impedance of at least 50 k .48 must e designed for a ias current of 0.16 and = 100. express Eq. ( ) Compare the result with that of a cascode stage f or a given ias current (IC 1 ) and explain why this is generally not a good ide a. ( ) Compare this expression with that in Eq. and W=L2 = 40=0:18.12).49.46. (a) Neglecting channel-length modulation. (9. Whi ch one is a stronger function of the ias current? The cascode current source sh own in Fig. 9.

.

Compute the output resistance of the circuits depicted in Fig. 2006] June 30. what is the highest allo wa le value of V 1 ? ( ) With such a value chosen for V 1 . 9. The PMOS cas code of Fig. 2007 at 13:42 452 (1) 452 Chap.50. what is the value of VX ? 16.51 must provide a ias current of 0.18 M 2 W = 20 L 0.18 Figure 9.47 V 1 V 2 M 1 W = 30 L 0.cls v.46 Figure 9. 9 Cascode Stages and Current Mirrors R out Q1 V 1 RP R out R out V 1 V 2 RB Q1 Q2 (a) R out V 1 V 1 V 2 RB ( ) Q1 RB Q2 (c) Q1 Q2 Q2 (d) VCC RE V 2 V 1 Q2 Q1 V 2 VCC Q2 Q1 VCC I1 Q2 R out (g) R out (e) (f) Figure 9. 9.48 (a) If we require a ias current of 1 mA and R = 500 . 17.5 mA with an output impedance £ ¢ £ £ £ £ £ £ R out V 1 V 2 M1 M2 £ £ £ R out V V 2 I1 Q1 V 2 £ £ £ £ £ £ £ £ £ £ £ £ £ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A ssume all of the transistors operate in saturation and gm rO 1.

If p Cox = 50 A/V2 and = 0:2 V. . determine the required value of W=L1 = W=L2 .1 .of 40 k .

explain what happens if the widths of oth transistors are increased y a factor of N while the transistor lengths and ias currents remain unchanged. Assume 0 and VA 1. The cascode stage of Fig. Using Eq. 23. 9. 2007 at 13:42 453 (1) Sec. 21. determine the mini mum required value of VA1 = VA2 .23). Compute the short-circuit transconductance and the voltage gain of each of t he stages in Fig.49 R out R out V 1 RG M2 (a) R out V 1 V 2 V 3 R out M1 M1 M2 ( ) M1 M3 M2 (c) V 1 M2 M1 (d) Figure 9.50 V V 2 V 1 M2 M1 R out Figure 9.16( ) must e designed for a voltage gain of 500. T A+ T (9. Having learned a out the £ £ £ £ ¢ £ £ £ £ £ ¢¢ £ V 1 £ £ £ £ £ £ ¢ ¢¢ £ £ . etermine the output impedance of the stages shown in Fig.3 Chapter Summary V R V1 V 1 X V 2 M2 M1 453 Figure 9. Assume L. 9. 2006] June 30. Assume all of the transistors operate in saturation and gm rO 1.cls v. 22. 9. (9.51 18. 9. 20. The PMOS cascode of Fig. (9.53. Prove that Eq.1 . Rout .130) a quantity independent of the ias current. Assume I1 = 1 mA.53) reduces to 2 Av V V VA V .52. If 1 = 2 = 100.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51 is designed for a given output impedance. 19. 9.

high voltage gain of the cascode stage. a student adventurously constructs the circuit depicted in Fig. 9.54. where the input is applied to the ase of Q2 £ .

52 VCC V V M2 Vout V in M1 V M1 V in V (c) (d) £ £ £ ¢¢ £ V 3 £ £ £ £ £ £ ¢¢ £ £ £ ¢¢ £ £ M2 Vout V in Q1 RE . 9 Cascode Stages and Current Mirrors R out V V 1 V 2 M1 M2 M3 V 3 RG (a) ( ) V V 2 V 1 M2 M1 R out (c) R out V 1 V 2 V 3 (d) M1 M2 M3 M3 VCC V in Q2 Vout V Q1 RE Q2 Vout (a) ( ) V RE V 2 M2 Vout M1 V in RS (e) V RE V in M2 Vout M1 RS (f) (g) VCC RE V in V 1 Q2 Vout RC Figure 9.53 £ V 1 £ £ ¢¢ ¢¢ £ V ¢¢ Figure 9. 2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 454 (1) 454 R out V 1 M1 M2 Chap.

Calculate the voltage gain of each stage illust rated in Fig. 24. 9. compute the short-circuit transconductance and the voltage ga in.55. 25. £ £ £ ¢ .rather than to the ase of Q1 . (a) Replacing Q1 with rO1 . 9. ( ) Assuming gm rO 1.56. explain intuitively why the voltage gain of this stage cannot e as high as that of the cascode. etermine the short-circuit transconductance and the voltage gain of the circuit shown in Fig.

19 and assume 1 = 2 = N . VA1 = VA2 = VA. 29. (9. 9. (9.54 VCC I1 Vout V 2 V 1 V in Q2 Q1 Figure 9. Av . The MOS cascode of Fig.1 for oth transistors.20(a) must provide a voltage gain of 200. Writing gm = 2n Cox W=LI and rO = 1=I . Using Eq. 9. explain what happens if the widths of the transistors are increased y a factor of N wh ile the transistor lengths and ias currents remain p ¢ ¢ £ ¢ £ £ ¢ £ £ £ £ £ £ £ £ £ £ Chapter Summary VCC I1 Vout V in V 1 Q2 Q1 £ £ £ ¢ ¢ £ . 9. 9. 3 = 4 = P . V31 = VA4 = VA.P . 28.57.3 455 Figure 9. a ipolar cascode ampli er has een con gured as shown in Fig. 9. (9.cls v. oes the result depend on the ias current? 27. 2006] June 30.72) in terms of the device parameters and plot the result as a function of I . ue to a manufacturing er ror.20(a) is designed for a given vo ltage gain. determine the required v alue of W=L1 = W=L2 . 2007 at 13:42 455 (1) Sec.55 VCC I1 Vout V 1 RP V in Q2 V in Q2 Q1 V 1 Q1 RP I1 Vout V 1 V in Q1 Q2 RE V i n Q2 VCC I1 Vout V 1 Q1 VCC I1 Vout Q3 VCC V 3 VCC (a) ( ) (c) (d) Figure 9. etermine the voltage gain of the circuit. The MOS cascode of Fig. Consider the cascode ampli er of Fig. If n Cox = 100 A=V2 and = 0:1 V. 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Express Eq.79) and the result o tained in Pro lem 28.61) in terms of these quant ities.56 26.N . expres s Eq.

9. n = 0:1 V. 2006] June 30. 32. 9 VCC Q4 V 2 Q3 £ £ ¢ £ £ £ ¢¢ ¢¢ £ £ £ .cls v. Repeat Pro lem 30 if the lengths of oth transistors are increase d y a factor of N while the transistor widths and ias currents remain unchange d. a CMOS cascode ampli er has een con gured as s hown in Fig.58. etermine the volta ge gain of each circuit in Fig. V V 4 V 3 M2 V 2 V in M1 RP M4 M3 Vout V 2 V in M2 M1 RP V 4 V 3 V M4 M3 Vout V 2 V 1 M2 M1 V in M5 V in M5 V 4 V 3 V M4 M3 Vout V 2 V 1 M2 M1 V 4 V 3 V M4 M3 Vout (a) ( ) (c) (d) Figure 9.59.59 ¢¢ £ £ £ £ £ £ ¢ ¢¢ £ £ £ £ £ £ £ £ £ £ ¢¢ £ £ £ £ Chap. ue to a manufacturing error. 9. 31. W=L1 = = W=L4 = 20=0:18.1 .20( ). V V 4 V 3 V 2 V in M4 M3 Vout M2 M1 V 1 Figure 9.58 33.1 . 2007 at 13:42 456 (1) 456 Cascode Stages and Current Mirrors v out V 1 v in Q2 Q1 Figure 9. In the cascode stage of Fig. and p = 0:15 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If n Cox = 100 A=V2 . Calculate the voltage gain of the circuit. calculate the ias curre nt such that the circuit achieves a voltage gain of 500.57 unchanged. 34. and p Cox = 50 A=V2 . Assume gm rO 1. 9.

Assume QREF and Q1 are identical. The para meters n Cox and VTH in Eq. If I1 i s 10% greater than its nominal value.85) (in terms of V ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.62. 43. 42. ¢ £ ¢¢ £ £ £ £ £ ¢ £ £ £ £ £ £ £ £ ¢ ¢ . Explain intuitively why this sensitivity is proportional to the transconductan ce of Q1 . Neglect the ase curents. 9.85) also vary with the fa rication process.61 40. If I1 is half of its nominal value. Explai n what happens. Assume QREF and Q1 are identical and 1. 9. 2006] June 30.60. (9. 44.62 41. determine the sensitivity of I1 to VCC . 2007 at 13:42 457 (1) Sec. esi gn an npn current mirror for this purpose.3 Chapter Summary 457 35.cls v. de ned as @I1 =@VCC . 9.15 if the reference current is equal to 180 A. ut assuming that I1 is twice its nominal value. From Eq. (9.83).61.) etermine the sensitivity of I1 to VTH and explain why this issue ecomes more serious at low supply voltages. 9. (Integ rated circuits fa ricated in different atches exhi it slightly different parame ters.64.63. IX R1 Q1 V1 Q2 V REF Figure 9. Repeat Pro lem 40 for the ci rcuit shown in Fig. We wi sh to generate two currents equal to 50 A and 230 A from a reference of 130 A.23( ). a student remem ers the logarithmic ampl i er studied in Chapter 8 and constructs the circuit depicted in Fig. (9. 37. 9. 36. 38. resistor RP has appeared in series with the em itter of Q1 in Fig. Repeat Pro lem 35 for Eq. 9. Repeat Pro lem 38 for the topology shown in Fig. Having learned a out the logarithmic f unction of the circuit in Fig. 9. Repeat Exam ple 9. Q1 V1 V REF R1 IX Q2 Figure 9. ue to a manufacturing error .60 39. express the value of RP in terms of other circuit parameters. parameters. ue to a manufacturing error. resistor RP has appeared in series with the ase of QREF in Fig. express the value of RP in terms of other circuit VCC I REF Q REF I1 Q1 RP Figure 9.

.

67. VCC I REF Q1 AE Q REF (a) VCC I copy 5A E VCC I copy AE I REF Q1 2A E I REF Q1 5A E I copy 3A E Q2 I2 5A E Q REF ( ) Q REF (c) Figure 9.63 VCC I REF Q REF I1 RP Q1 Figure 9. Repeat Pro lem 44 for the circuit shown in Fig.65. determine t he value of Icopy in each circuit depicted in Fig. 9 VCC I REF Q REF RP Cascode Stages and Current Mirrors I1 Q1 Figure 9. 48. Taking ase currents into account. 46.66. 2007 at 13:42 458 (1) 458 Chap. 9.64 VCC I REF Q REF I1 RP Q1 Figure 9.65 45. 2006] June 30.66 47. ut assuming I1 is 10% less than its nominal value.cls v. Normalize the error to the nominal value of Icopy . 9. Taking £ £ £ £ . 9. Calculate the error in Icopy for the circuits shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

9. does I1 change if the threshold voltage of oth transistors increases y V ? £ ¢ £ £ ¢ £ £ .69 such that I1 = IREF =2. With this choice of RP . compute the error in Icopy for each of the circuits illustrated in Fig. does I1 change if the thre shold voltage of oth transistors increases y V ? 50. With this choice of RP . etermine the value of RP in the circuit of Fig. 49. 9. 9.68. etermine the value of RP in the circuit of Fig.ase currents into account.70 such that I1 = 2IREF .

68 V I REF M1 W L M REF I1 W L RP Figure 9. Consider the MOS current mirror shown in Fig.35(c) and assume M1 and M2 are identical ut 6= 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Repeat Example 9. 9.21 if the reference current is 0.70 51. (a) How should V S 1 e chosen so that Icopy1 is exactly equal to IREF ? £ ¢ £ ¢¢ ¢¢ £ . 9. 2007 at 13:42 459 (1) Sec. 52.71. 9.cls v.67 VCC I REF AE AE AE I copy AE 3A E 2A E VCC I REF 5A E 9A E I copy (a) ( ) Figure 9. 53. Assume all of the transistors opera te in saturation. Calculate Icopy in each of the circuits shown in Fig.35 mA.69 V I REF M1 W L RP M REF I1 W L Figure 9.3 Chapter Summary VCC I REF Q1 nA E Q REF Q2 I2 kAE I copy1 mA E 459 Figure 9.

assume IS.p = 5 V. 2007 at 13:42 460 (1) 460 V I REF 3 (W( L n 5 (W( L p 2 (W( L n Chap.p = .72( ) for an output im pedance of 50 k .72 voltage of Q2 in Fig. Assume a ias current of 1 mA.cls v. VTH. 55. VA. p = 50.73 for an output impedance of 200 k and a R out V 1 V 2 M1 M2 £ £ £ ¢ £ £ ¢ £ £ £ £ £ £ ¢ £ £ £ £ ¢ ¢¢ ¢¢ £ £ £ . esign Pro lems In the fol lowing pro lems.n = 0:4 V.16 A. and VTH. unless otherwise stated. nCox = 100 A/V2 . Assuming a ias current of 1 mA.72( ) ( 0:5 V). 9 V W 3( ( L p I copy I REF Cascode Stages and Current Mirrors ( W (p L 5 (W( L n 2 (W( L p ( W (n L M REF I copy W 3( ( L n M REF (a) ( ) Figure 9. 2006] June 30. p Cox = 50 A/V2 . esign the cascode current source of Fig. design the degenerated current source of Fig. 9.0:5 V. 9.p = 6 10. where the su scripts n and p refer to n-type (npn or NMOS) and p-type (pnp or PMOS) devices. 54. We wish to design the MOS cascode of Fig. respectively. VTH (so that M1 resides at the edge of saturation). 9.n = IS.71 ( ) etermine the error in Icopy1 with respect to IREF if V S 1 is equal to VGS . n = 100. 9.72(a) such that RE sustains a v oltage approximately equal to the minimum required collector-emitter R out V Q1 RE V 1 V 2 Q1 Q2 ( ) R out (a) Figure 9.n = VA. Compare the output impedances of the two circuits. 56. Select V 1 such that Q2 experiences a ase-collector forward ias of only 100 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

( ) Calculate the required value of V 2 . (a) etermine W=L1 = W=L2 if = 0:1 V.1 .5 mA. £ ¢ £ £ .Figure 9.73 ias current of 0.

9. Assuming VA = 1 and 1.75 is achieved? 59. 9. 2006] June 30. etermine the required dc levels of Vin and V 3 . Select V 1 and VCC = 2.74 Figure 9. For simplicity. The current mirror shown in Fig. (c) V 1 such that Q1 sustains a collector-emitter voltage of 5 cascode ampli er shown in Fig. 9. 9. Use VCC I1 Vout V 1 V in Q2 Q1 Figure 9.76 udget of 2 mW with V = 1:8 V. The ipolar cascode ampli er of Fig.5 mA. £ £ £ £ Q4 Q3 Vout V 1 V in Q2 Q1 £ £ £ £ £ £ Eq. 60.53) and assume For a ias current of Compute the value of 00 mV. Assume W=L1 = = W=L4 = 20=0:18 and p = 2n = 0:2 V.76 for a voltage gain of 200 and a power V V 3 V 2 V 1 V in M4 M3 Vout M2 M1 V 2 such that Q1 and Q4 sustain a ase-collector forward ias of 200 mV. (a) What is the minimum required value of VA ? ( ) 0.74 must e designed for a voltage gain of 500. calculate the required ias component in Vin . esign the CMOS cascode ampli er of Fig.cls v. assume V 1 = V 2 = 0:9 V.77 must deliver I1 = 0:5 m A to a circuit with a total power udget of 2 mW. 2007 at 13:42 461 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75 for a power udget of 2 £ ¢¢ £ ¢ £ £ £ £ ¢ £ £ £ £ £ ¢ ¢¢ £ £ . 58. 9. esign the mW. What vo ltage gain Figure 9.3 Chapter Summary 461 57. (9. determi ne the required value of IREF and the relative sizes of QREF and Q1 .1 .5 V V 3 V 2 = 100.

and a power udget of 3 mW. 9.5 V V in I REF Q REF Q1 Q2 Vout esign the £ ¢ £ £ £ £ £ ¢ ¢ £ . esign the circuit of Fig. The common-source sta ge depicted in Fig.34 such that the ias current of Q2 is 1 mA and the error in IC 1 with respect to its nominal value is less than 2. 9. output impedance of 500 . 9. Explain the trade-off etween accuracy and power dissipation in this circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 64.1 .cls v. 65. 9 Cascode Stages and Current Mirrors VCC = 2.81 must e designed for a voltage gain of 20 and a power udget of 2 mW. Q2 operates as a common.79. 2006] June 30. and p = 0:2 V. £ £ ¢ ¢ 61.1 . Assuming W=L1 = 20=0:18. In the c ircuit of Fig. Assume VA = 1 and 1. circuit for a power VCC = 2.80 shows an arrangement where M1 and M2 serve as current sources for circui ts 1 and 2. 67. Q2 operates as an emitter follower.78 udget of 3 mW and an output impedance of 50 . In the circuit of Fig.ase stage.78.30 for Icopy = 0:5 mA and an error of less than 1 with respect to the nominal value. Is the solution unique? Figu re 9. esign the circuit for a power udget of 3 mW. Assu me VA = 1 and 1. esign the circuit for an VCC = 2. 9. n = 0:1 V.5 V Circuit I REF I1 Q REF Q1 Figure 9. 9. The source follower of Fig.5 V RC Vout I REF V in Q REF Q1 Q2 V Figure 9. design the circuit.1 . 62. esign the c ircuit of Fig. 66.1 .85 a nd an output impedance of 100 . design the circuit. 2007 at 13:42 462 (1) 462 Chap.77 Figure 9. n = 0:1 V. Assuming W=L2 = 10=0:18. and p = 0:2 V. a voltage gain of 20. 9.82 must achieve a voltage gain of 0.79 63. Assume VCC = 2:5 V.

9. (You may not need all of the power udget.5 mA M REF M1 M2 Figure 9.) SPICE Pro lems £ £ £ £ ¢¢ V ¢¢ V ¢¢ ¢¢ = 1. 9. 2007 at 13:42 463 (1) Sec. 2006] June 30.83 a high voltage gain. design the circuit for a v oltage gain of 20. n = 0:1 V.82 68.1 .83 employs the current source M3 as the load to achieve V = 1. neglect channel-length modulation in M1 . an input impedance of 50 .1 . A ssuming W=L3 = 40=0:18.8 V I REF M REF V in M1 Vout M2 .3 Chapter Summary 463 V = 1.cls v. For simplicity.8 V M4 M3 Vout M1 I REF M REF M5 V in M2 V Figure 9.8 V Circuit 1 Circuit 2 1 mA I REF 0.80 I REF V in M1 Figure 9. The common-gate stage of Fig.8 V M REF M2 = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.81 Figure 9. and p = 0:2 V. and a power udget of 13 mW.

pnp = 50. select the value of RP so as to minimize the error etween I1 and IREF .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. npn = 100. Repeat Pro lem 69 for the circuit shown in Fig. ( ) eterm ine the change in Iout if V varies y 100 mV.5 V I REF Q REF 1 mA I1 Q1 RP Figure 9.16 A. 2006] June 30.5 V I REF Q REF RP 1 mA I1 Q1 Figure 9. 2007 at 13:42 464 (1) 464 Chap. Figure 9. Assume W=L = 5 m=0:18 m for M1 -M3 .8 V I out 0.5 mA y the mirr £ £ £ £ £ £ £ £ £ £ £ ¢¢ . VA.85. 72. Explain the cause of this change.5 mA. (c) Using oth hand analysis and SPICE simulations. VCC = 2.87. 69.pnp = 3:5 V. determine the output impedan ce of the cascode and compare the results. IS.84.npn = 5 V.pnp = 8 10. M1 -M2 .npn = 5 10. 9. 9. we wish to suppress the error due to the ase currents y means of resistor RP . use the MOS device models given in Appendix A. (a) Plot the input/output char £ £ ¢ £ £ £ £ £ £ £ V £ 71.cls v. assume IS. and I1 = 1 mA is an ideal current source.85 M3 M2 M1 Figure 9. V = 1.84 (a) Tying the collector of Q2 to VCC .2 = 10 m=0:18 mum.16 A. ( ) What is the change in the error if the of o th transistors varies y 3? (c) What is the change in the error if RP changes y 10? 70. We wish to study the pro lem of iasing in a high-gain cascode stage. V = 0:9 V.86 (a) Select the value of V so that Iout is precisely equal to 0. VA. Which circuit exhi it s less sensitivity to variations in and RP ? VCC = 2. 9. For i polar transistors. In the circuit of Fig. 9 Cascode Stages and Current Mirrors In the following pro lems. Assume W=L1.86 depicts a cascode current source whose value is de ned or arrangement. Fig.

acteristic and determine the value of Vin at which the slope (small-signal gain) reaches a maximum. .

2001. 2006] June 30. B.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.88 References 1. Razavi.87 ( ) Now. esign of Analog CMOS Integrated Circuits McGraw-Hill. Repeat Pro lem 72 for the cascode shown in Fig. suppose the iasing circuitry that must produce the a ove dc value for Vin incurs an error of 20 mV. 73. explain what happens to the small-signal gain.8 V M5 1 mA V in M1 Figure 9.8 V I1 Vout V V in M2 M1 465 Figure 9. 2007 at 13:42 465 (1) References V = 1. From (a). assuming W=L = 1 0 m=0:18 m for all of the transistors.cls v. ¢ £ M4 M3 V M2 Vout £ £ £ £ ¢¢ ¢¢ £ . 9.88. V = 1.

cls v.1 Genera Considerations 10. this phenomenon is summarized as the “supp y 466 £ ¤ £ ¤ ¤¤ ¢ ¤ ¤ £ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¢ ¤ ¤ ¤ £ ¤ ¤ ¤ ¤ ¤ ¤ ¤ £ ¤ ¤ ¤ ¢ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¢ .1(b)]. So ution Reca from Chapter 3 that the current drawn from the recti ed output creates a ri pp e waveform at twice the ac ine frequency (50 or 60 Hz) [Fig. Exp ain what happens. an e ectrica engi neering student constructs the circuit shown in Fig. General Considerations ifferential Signals ifferential Pair Bipolar ifferenti al pair Qualitative Analysis Large−Signa Ana ysis Sma −Signa Ana ysis MOS Differe ntia pair Qua itative Ana ysis Large−Signa Ana ysis Sma −Signa Ana ysis Other Co ncepts Cascode Pair Common−Mode Rejection Pair with Active Load 10.1(a) to amp ify the sign a produced by a microphone. high-p erformance design paradigm in many of today’s systems. 2007 at 13:42 466 (1) 10 ifferential Ampli ers The elegant concept of “differential” signals and ampli ers was invented in the 1940s and rst utilized in vacuum-tu e circuits. Unfortunate y. 2006] June 30. et us rst consider an examp e.. This chapter descri es ipo lar and MOS differential ampli ers and formulates their large-signal and small-sig nal properties.1 Initia Thoughts In order to understand the need for differentia circuit s.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exami ning the output of the commonemitter stage. upon app ying the resu t to a speake r. we can write Vout = VCC . I ustrated in Fig. the student observes that the amp i er output contains a strong “humming” noise. Since then. (10.1) noting that Vout simp y “tracks” VCC and hence contains the ripp e in its entirety.1 Having earned the design of recti ers and basic amp i er stages. 10. differential circuits have found increasingly wider usage in microelectronics and serve as a ro ust.1(c) depicts the overa output in t he presence of both the signa and the ripp e. we can identify two components: (1) the amp i ed version of the microphone signa and (2) the ripp e waveform present on VCC . 10. The “hum” originates from the ripp e. a steady ow frequency component.1.1(d). RC IC . Figure 10. 10. i. Examp e 10. e. For the atter. The concepts are outlined elow.

BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. noise goes to the output with a gain of unity. 10. the above conjecture can be r eadi y imp emented. we c an modify the amp i er topo ogy such that the output is insensitive to VCC .) How shou d we suppress the hum in the above examp e? We can increase C1 . How i s that possib e? Equation (10. (c) effect at output.” (A MOS imp ementation wou d suffer from the same prob em. But what if Vout is not “referenced” to ground?! More spe ci ca y. fundamenta y because both Vout and VCC are measured with respect to gr ound and differ by RC IC . and the output is now measured between nodes X and Y r ather than from X to ground. A ternative y. What happens if VCC contains ripp e? Both VX and VY ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¡¤¤ Exercise What is the hum frequency for a fu wave recti er or a ha f wave recti er? ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ Vout Signa ¤ ¤ VCC Voice Signa Ripp e ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 2006] June 30. The CE stage is dup icated on the right. Whi e rather abstract.2(a) i ustrates the core concept. (b) ripp e on supp y vo tage. 2007 at 13:42 467 (1) Sec.1 (a) CE stage powered by a recti er. but the required capacitor va ue may become prohib itive y arge if many circuits draw current from the recti er. thus owering the ripp e amp itude.1 Genera Considerations VCC 110 V 60 Hz To Bias 467 RC Vout Q1 C1 (a) VCC t (b) (c) t (d) Figure 10.1) imp ies that a change in VCC direct y appears i n Vout .c s v. (d) ripp e and signa paths to output. what if Vout is measured with respect to another point that itse f exper iences the supp y ripp e to the same extent? It is thus possib e to e iminate th e ripp e from the “net” output. Figure 10.

4) ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¡¤¤ . In fact. vY = Av vin : Note that Q2 carries no signa . we express the s ma signa vo tages at these nodes as vX = Av vin + vr vY = vr : That is.2) (10. simp y serving as a constant current source. (10.3) vX . denoting the ripp e by vr .rise and fa by the same amount and hence the difference between VX and VY rem ains free from the ripp e. (10.

2 Differentia Signa s Let us return to the circuit of Fig. we direct y app y the input signa to the base of Q2 [Fig.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.2(a) and reca that the dup icate stage consisting of Q2 and RC 2 r emains “id e.7) VCC R C1 X Y Q2 − v in R C2 To Bias R C2 X Q1 V in (a) vX .1. 10. the signa components at X and Y are in phase. 10 Differentia Amp i ers VCC Ripp e Ripp e VCC R C1 X Q1 Y Q2 R C2 A1 R C1 To Bias R C2 X Q1 Vout To Bias Y Q2 v in (a) (b) Figure 10.” thereby “wasting” current. I n our rst attempt.2 Use of two CE stages to remove effect of ripp e. 10. cance ing e ach other as they appear in vX .5) (10. 3(a)]. 2006] June 30. The above deve opment serves as the foundation for differentia amp i ers: the sym metric CE stages provide two output nodes whose vo tage difference remains free from the supp y ripp e. Unfortunate y. vY : vX = Av vin + vr vY = Av vin + vr Vr VCC R C1 To Bias (10.c s v. We may therefore wonder if this stage can prov ide signa amp i cation in addition to estab ishing a reference point for Vout . 2007 at 13:42 468 (1) 468 Chap. 10.6) (10. vY = 0: ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .

we can invert one of the input ¤ ¤ ¤ ¤ ¤ ¤ ¤ .Y Q2 + v in Q1 (b) (c) Figure 10. (c) generation of differentia phases from one signa . For the signa components to enhance each other at the output.3 (a) App ication of one input signa to two CE stages. (b) use of dif ferentia input signa s.

3(c).BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.1 Genera Considerations 469 phases as shown in Fig. this topo ogy provides twice the output swing by exp oiting the amp i cation capabi ity of the dup icate stage.10) Compared to the circuit of Fig. 10. Our thought process has ed us to the speci c waveforms in Fig.Av vin + vr and hence (10. 2007 at 13:42 469 (1) Sec. 10. 10.c s v. The reade r may wonder how . 10.8) (10.” wherea s a differentia signa is measured between two nodes that have equa and opposi te swings [Fig. a sing e ended signa is one measure d with respect to the common ground [Fig.4(a)] and “carried by one ine.9) vX .2(a). I ustrated in Fig. a simp e ap proach is to uti ize a transformer to convert the microphone signa to two compo nents bearing a phase difference of 180 . 10. These waveforms are examp es of “differentia ” signa s and stand in contrast to “si ng e ended” signa s—the type to which we are accustomed from basic circuits and prev ious chapters of this book.4(b)] and is thus “carried by two ines. More speci ca y.3(b).3(b): the circuit senses two inputs that vary by equa and opposite amounts and generates two outputs that behave in a simi ar fashio n. 10. 10. obtaining vX = Av vin + vr vY = .” VCC Vin Vout Q1 (a) VCC Q1 V1 VCM V2 t (c) 2V0 ¤ Q2 Output Differentia Signa ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ . vY = 2Av vin : (10. 2006] June 30.vin can be generated.

(b) differentia signa s.(b) Figure 10.4 (a) Sing e ended signa s. Here. with respect to ground: V1 = V0 sin !t + VCM V2 = . Figure 10. (c) i ustra tion of common mode eve . V1 and V2 vary by equ a and opposite amounts and have the same average (dc) eve .12) ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ Input Differentia Signa ¡ ¤ .11) (10.4(c) summarizes the foregoing deve opment.V0 sin !t + VCM (10. VCM .

w here RC = RC 1 = RC 2 and IC denotes the bias current of Q1 and Q2 . 10. VCM = VCC . we say the “differentia swing” is 4V0 . 2007 at 13:42 470 (1) 470 Chap.3(c) produce an output CM eve equa to +2 V. 10.2 So ution v in2 v in2 t Figure 10. RC IC in the above examp e? W hy is it interesting that the ripp e appears in VCM but not in the differentia output? We wi answer these important questions in the fo owing sections. The dc vo t age that is common to both V1 and V2 [VCM in Fig.c s v. 10.vin disp ay a CM eve of zero bec ause the center tap of the transformer is grounded. But. In the absence of signa s.5 Examp e 10.3( b).3 Determine the common mode eve at the output of the circuit shown in Fig.” That is. For examp e. Interesting y.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. We may a so say V1 and V2 are differentia signa s to emphasize t hat they vary by equa and opposite amounts around a xed eve . in the absence of differentia signa s. how about the commo n mode eve ? What is the signi cance of VCM = VCC . 10. RC IC (with respect to ground). the two nodes rem ain at a potentia equa to VCM with respect to the g oba ground. in the transformer of Fig. Thus. The center tap can simp y be tied to a vo tage equa to +2 V (Fig. 2006] June 30. 10.4(c)] is ca ed the “commonmo de (CM) eve . what is the output CM eve ? Our observations regarding supp y ripp e and the use of the “dup icate stage” provid e suf cient justi cation for studying differentia signa s. VX = VY = VCC . v in1 v in1 2V +2 V Examp e 10. How can the transformer of F ig. RC IC . VCM . So ution Exercise If a resistor of va ue R1 is inserted between VCC and the top termina s of RC 1 and RC 2 . 10 Differentia Amp i ers Since each of V1 and V2 has a peak to peak swing of 2V0 .5). ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ Exercise Does the CM eve change if the inputs of the amp i er draw a bias current? ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ . the ripp e affects VCM but not the differentia ou tput. +vin and .3(c).

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13) (10. In both cases.2 that in the absence of signa s.15) ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¤ ¡¤¤ ¤ ¡ ¡ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . We therefore draw the pair as sho wn in Fig. 10. 10.” The MOS counterpart is shown in Fig. 2 VX = VY = VCC . 10. This observation eads to the differentia pair. the sum of the transistor currents is equa to the tai current.2 Bipo ar Differentia Pair 10.6 (a) Bipo ar and (b) MOS differentia pairs. 10.4(b) senses two inputs and can therefo re serve as A1 in Fig. RC IEE : 2 1 A so ca ed the “emitter coup ed pair” or the “ ong tai ed pair.1 Qua itative Ana ysis It is instructive to rst examine the bias conditions of the circuit. We ca IEE the “tai current source.6(b).1. 10. Fortunate y.1. 2007 at 13:42 471 (1) Sec. diffe rentia nodes reside at the common mode eve . For each differentia pair.6(a). We a so assum e each circuit is perfect y symmetric. we begin with a qua itative.2 Bipo ar Differentia Pair 471 10. VCC RC X V in1 Q1 Q2 RC Y Vin2 V in1 RD X M1 M2 I SS VDD RD Y Vin2 I EE (a) (b) Figure 10. i.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. By virtue of symmetry. v ersati e topo ogy. with the two inputs tied to VCM to indicate no signa exists at the input. Reca from Section 10.7. a simp e modi cation yie ds an e egant. 10. VBE1 = VBE2 IC 1 = IC 2 = IEE . the circuit of Fig. 10.3 Differentia Pair Before forma y introducing the differentia pair. 2006] June 30. Our objective is t o ana yze the arge signa and sma signa behavior of these circuits and demon strate their advantages over the “sing e ended” stages studied in previous chapters.c s v..e. we m ust recognize that the circuit of Fig. intuitive ana ysis and subsequent y formu ate the arge signa and sma signa behavior.4(b) s uffers from some drawbacks. 10.” (10.” Thus. 10.2. the vo tage drop across each oad resistor is equa to RC IEE =2 and hence (10. the transistors are identica and s o are the resistors. the (bipo ar) “differentia pair”1 i s simi ar to the circuit of Fig.4(b). Whi e sensing and producing differentia signa s.2(b). I ustrated in Fig. We say the circuit i s in “equi ibrium. except that the emitters of Q1 and Q2 are tied to a constant current source rather than to ground.14) where the co ector and emitter currents are assumed equa .

7 by a sma amount and determine the circuit’s re sponse. Are Q1 and Q2 in the active region? To avoid sa turation. In the atter. so do their co ector currents and vo tage s (why?). Interesting y. 2006] June 30. In other words. VCM must remain be ow VCC by at east 0. thereby suggesting that neither the co ector current nor the co ector vo tage of the transistors is affected. RC IEE VCM . or the circuit “rejects” input CM variations. Eqs.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.7 Response of differentia pair to input CM change.5 V. 10.4(b).16) Examp e 10.16 gives VCC .8 summarizes th ese resu ts. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤¤ ¡ ¤¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ . the differen tia output. if t he base vo tage of Q1 and Q2 changes. the co ector vo tages must not fa be ow the base vo tages: revea ing that VCM cannot be arbitrari y high.4 A bipo ar differentia pair emp oys a oad resistance of 1 k c ose to VCC can VC M be chosen? and a tai current of 1 mA. The “common mode rejection” capabi ity of the differentia pair distinc t y sets it apart from our origina circuit in Fig.15) remain unchanged. so are the two outputs. 10 VCC R C1 X Q1 V CM I EE R C1 = R C2 = R C Q2 R C2 Y Differentia Amp i ers Figure 10. The circuit a so “rejects” the effect of supp y ripp e: if VCC experiences a change. We say the circuit does not respond to changes in the input common mode eve . VCC . does not.17) (10. (10. 10.c s v. 2 (10. if the two input vo tages are equa . How So ution Equation 10. We say a zero differentia input produces a zero differentia output. (10. Figure 10. et us vary VCM in Fig.18) What va ue of RC a ows the input CM eve to approach VCC is the transistors ca n to erate a base co ector forward bias of 400 mV? Exercise Now. VX . The reader may recognize that it is the tai current source in the dif ferentia pair that guarantees constant co ector currents and hence rejection o f the input CM eve . VCM RC IEE 2 0:5 V: That is.13) (10. 2007 at 13:42 472 (1) 472 Chap. VY .

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IC 1 IEE and IC 2 6= 0.e. thereby turning Q 2 off.. where the two tr ansistors are drawn with a vertica offset to emphasize that Q1 senses a more po sitive base vo tage. We ho d one input constant. RC IEE VY = VCC : (10. 0:2 V = 1:8 V!! Since with VBE = 1:8 V. t hen its base emitter vo tage must reach a typica va ue of. If Q2 carries an appreciab e current. 10. VCC = 2.20) VX = VCC . 0. Since the difference between the base vo tages of Q1 and Q2 is so arge.5 V RC Vout RC Y Q2 Q1 P I EE Vin2 = +2 V RC Vout Y Vin2 = +1 V V in1 = +1 V X IC 1 = IEE IC 2 = 0. With our treatment of the common mode response. vary the other. say. the device therefore requires an emitter vo tage of VP 0:2 V . this means that Q1 sustains a base emitter vo tage of Vin1 . we now turn to the more interest ing case of differentia response. Reca that IC 1 + IC 2 = IEE .19) (10. such input signa s provide a simp e. arge positive input di ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¡ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ . However. 2007 at 13:42 473 (1) Sec.8 Effect of VCM 1 and VCM 2 at output. and hence (10. VP = +2 V . how can we prove that Q1 indeed absorbs a of IEE ? Let us assume that it is not so. 10.9(a).c s v. we postu ate that Q1 “hogs” a of the tai current. VY VCM1 VCM2 Figure 10.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.21) (10. With its base he d at +1 V.2 Bipo ar Differentia Pair VCC R C I EE Upper Limit of VCM to Avoid Saturation 2 473 VX . i. Whi e not exact y different ia .8 V. intuitive starting point. That is.22) But.5 V RC X V in1 = +2 V Q1 Q2 P I EE (a) (b) VCC = 2. a nd examine the currents owing in the two transistors.9 Response of bipo ar differentia pair to (a) fference and (b) arge negative input difference. a typica transistor carries an enor ¤ ¤ ¤ Figure 10. Consider the circuit shown in Fig. 2006] June 30.

Q1 ho ds node P at approximate y +1:2 V. we conc ude that the conditions VBE1 = 1:8 V and VP 0:2 V cannot occur. In fact.8 V. ensuring that Q2 remain s off. with a typica base emitter vo tage of 0.mous current. ¡ ¤ ¤ ¤ ¤ ¤ . and since IC 1 cannot exceed IEE .

(10.24) IC 2 = IEE IC 1 = 0.10 Variation of (a) co ector currents and (b) output vo tages as a fu nction of input.19). 2007 at 13:42 474 (1) 474 Chap. RC IEE VX = VCC : (10. based on Eqs. and hence VY = VCC . and (10. Vin2 j becomes suf cient y arge. 2006] June 30.14).c s v. (10. giving Q1 and Q2 reverses the (10.9(b)]. we can sketch the co ector currents of Q1 and Q2 as a function of the input difference [Fig. We have not yet formu ated these characteristics but we do observe t hat the co ector current of each transistor goes from 0 to IEE if jVin1 . Q2 Q1 Q1 Q2 Q1 Q2 I EE VCC I EE VCC − R C 2 VCC − R C I EE 0 (b) I C2 I C1 0 (a) I EE 2 VX VY V in1 − V in2 V in1 − V in2 Figure 10. In fact. 10.23). as the difference between the two inputs depa rts from zero.25) (10. It is a so important to note that VX and VY vary differentia y in response to V ¤ ¤¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤ ¤ . 10.23) (10. 10 Differentia Amp i ers Symmetry of the circuit imp ies that swapping the base vo tages of situation [Fi g. the differentia pair “steers” the tai current from one transistor t o the other.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.26) The above experiments revea that.10(a)].

If IEE is comp ete y steered. RC IEE = 2 V. this quantity is ca ed the “output CM eve . That is. Thus.5 mA and a co ector res istance of 1 k . Since VX and VY are differentia . the transistor carrying the current owers its co ector vo tage to VCC .21).5 A bipo ar differentia pair emp oys a tai current of 0.25). From Eqs. Given by VCC . we can sketch the input/ou tput characteristics of the circuit as shown in Fig. So ution ¡ ¤ ¤ ¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .15). What is the maximum a owab e base vo tage if the differentia input is arge enough to comp ete y steer the tai current? Assume VCC = 2:5 V.in1 . (10. Vin2 .” Examp e 10.10(b). RC IEE =2. and (10. 10. we can de ne a common mode eve for them. (10. a nonzer o differentia input yie ds a nonzero differentia output— a behavior in sharp con trast to the CM response. the base vo tage must remain be ow t his va ue so as to avoid saturation.

( ) hypothetical change at P . I: I = C2 (10. then I would simply e equal to gm V .11(a). In the ast step of our qua itative ana ysis. 2006] June 30. Suppose. 2007 at 13:42 475 (1) Sec. node P is free to rise or fall. since IC 1 + IC 2 = IEE . IC 2 decreases by the same amount: VCC RC + ∆V RC Y Q1 P I EE (a) ( ) + ∆V X Q2 X Q1 P Q2 Y VCM − ∆V VCM VCM − ∆V VCM ∆VP I EE IC 1 = IEE + I 2 IEE .2 Bipo ar Differentia Pair 475 Exercise Repeat the above examp e if the tai current is raised to 1 mA. We surmise that I C 1 increases s ight y and. ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ £ ¤ ¤ ¢ ¤ ¤ ¤¤ ¤ ¤ ¤ £ ¤ ¤ .28) How is I related to V ? If the emitters of Q1 and Q2 were directly tied to ground. Vin2 = 0 (t he equi ibrium condition) and study the circuit’s behavior for a sma input diffe rence. 10. In the differential pair. As i ustrated in Fig. the base vo tage of Q1 is raised from VC M by V whi e that of Q2 is owered from VCM by the same amount.11 (a) ifferential pair sensing small.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. We must therefore compute the change in VP . a £ Figure 10.c s v. 10. we “zoom in” around Vin1 . however.27) (10. differential input changes.

IC 2 . yielding (10. the tail voltage remains constant if the two inputs vary differen tially and y a small amount—an o servation critical to the small-signal analysis of the circuit. VP rises y VP . the net increase in VBE 1 is equal to V . 10.27) and (10.31) VP = 0: (10.s shown in Fig. dictating t hat gm V . VP : Similarly.30) IC 2 = . = gm V + VP £ £ £ £ £ . As a result. VP and hence (10. VP and hence 2 IC 1 = gm V .29) + VP .28) that IC 1 must e equal to .32) Interestingly. the net decrease in VBE 2 is equal to V (10.gmV + VP : But recall from (10.11( ).

It follows that Solution RC = jAV j g m (10.1 . we can rewrite (10.gmV RC VY = gmV RC : The differential output therefore goes from 0 to (10.32) does not hold if V is large.34) VX = . thus exhi iting unequal transconductances and prohi i ting the omission of gm ’s from the two sides of (10.29) and (10.40) (Note that the change in the differential input is equal to 2V .25 mA near equ ili rium.31).41) (10. Which one of the a ove equations is violated? For a large differential input.30) respectively as IC 1 = gm V IC 2 = .11 (a). providing a transconductance of 0:25 mA=26 mV = 104 .cls v.2gmV RC = 2V = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.) This expression is similar to that of the common-emitter stage. 10.6 esign a ipolar differential pair for a gain of 10 and a power udget of 1 mW w ith a supply voltage of 2 V. VY = . the power udget translates to a ta il current of 0. Example 10.gmR £ £ £ £ ¢ ¢ £ . With VP = 0 in Fig. 10 ifferential Ampli ers The reader may wonder why (10. Q1 and Q2 carry sign i cantly different currents.2gmV RC : We de ne the small-signal differential gain of the circuit as (10.35) (10. Each transistor thus carries a current of 0. 2007 at 13:42 476 (1) 476 Chap. With VCC = 2 V.36) VX .5 mA.gmV and (10.42) = 1040 : £ £ ¢ ¢ Av = Change in C : i erential Output Change in i erential Input .33) (10.38) (10.39) (10.37) (10.

£ Exercise Redesign the circuit for a power udget of 0. .5 mW and compare the results.

43) jAV.di j = gm1. For a C E stage (10. where gm1.2 RC . we now quantify its large-signal ehavior. Exercise If oth circuits are designed for the same power udget. 2VT VT (10.2 Large-Signal Analysis Having o tained insight into the operation of the ipolar differential pair. and equal supply voltages.7 Compare the power dissipation of a ipolar differential pair with that of a CE s tage if oth circuits are designed for equal voltage gains. In other words. collector resistance s. Solution The gain of the differential pair is written from (10.2 RC = gm RC and hence (10. (10. equal collector resista nces. This is one of the draw acks of differential circuits. 2006] June 30. 2007 at 13:42 477 (1) Sec. compare their voltage gains. 10.2 Bipolar ifferential Pair 477 Example 10. aiming to f £ £ £ £ £ £ £ £ ¢ £ £ .45) IEE = IC .47) indicating that the differential pair consumes twice as much power.cls v.CE j = gmRC : Thus.2. an d IC represents the ias current of the CE stage.44) gm1. and supply voltages.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.2 denotes the transconductance of each of the two transistors. IEE = 2IC . (10.46) where IEE =2 is the ias current of each transistor in the differential pair.40) as jAV.

48) (10. RC IC 2 (10. In order to derive the relationship etween the differential input and output of the circuit.10).ormulate the input/output characteristic of the circuit (the sketches in Fig. RC IC 1 Vout2 = VCC . Our interest arises from (a) the need to understand the circui t’s limitations in serving as a linear ampli er. and ( ) the application of the diff erential pair as a (nonlinear) current-steering circuit.12 that Vout1 = VCC . the re ader may naturally wonder why we are suddenly interested in this aspect of the d ifferential pair.49) £ £ . Not having seen any large-signal analysis in the previous chapters. 10. 10 . we rst not e from Fig.

Vin2 = VBE1 .55) in (10.58) ut with the roles of Vin1 and Vin2 IC 2 = £ £ £ £ £ ¢ .50) (10. a KCL at node P gives (10. : 1 + exp Vin1 V Vin2 T The symmetry of the circuit with respect t o Vin1 and Vin2 and with respect to IC 1 and IC 2 suggests that IC 1 exhi its th e same ehavior as (10. Vin1 .56) yields .57) IEE (10.56) Equations (10. and hence Vout = Vout1 .58) .cls v. and recalling from Chapter 4 that VBE = VT lnIC =IS . (10. o taining (10. IC 2 exp Vin1 V Vin2 + IC 2 = IEE T and.51) We must therefore compute IC 1 and IC 2 in terms of the input difference.56) contain two unknowns. Su stituting for IC 1 from ( 10. 10 ifferential Ampli ers VCC RC V out1 V in1 Q1 P I EE Vout Q2 RC Vout2 Vin2 Figure 10.12 Bipolar differential pair for large-signal analysis.52) Vin1 .55) and (10. we write a KVL around the input network.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. VBE2 . therefore. Vout2 = .55) IC 1 + IC 2 = IEE : (10.53) (10. VT ln IC 2 IS1 IS2 IC 1 : = VT ln I C2 Also.RC IC 1 . VBE1 = VP = Vin2 .54) (10. IC 2 : (10. VBE2 = VT ln IC 1 . Assumi ng = 1 and VA = 1. 2007 at 13:42 478 (1) 478 Chap.

10VT ? Since exp.60) IC 1 ! 0 IC 2 ! IEE . IC 1 IE E :4:54 105 1 + 4 54 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Similarly. IC 1 = (10.67) (10. Q1 carries only 0:0045 of the tail current. Vin2 =VT ! 1 and as predicted y our qualitative analysis [Fig. 10. if Vin1 (10.56) to o ta in IC 1 . £ £ £ ¢ £ £ £ ¢ .2 Bipolar ifferential Pair 479 exchanged: Equations (10.9( )]. 1 + exp Vin2 V Vin1 T Vin1 . . 4:54 10. if Vin1 . Vin2 : 1 + exp VT A lternatively.64) IC 1 ! IEE IC 2 ! 0: IEE if Vin1 . 2006] June 30. Vin2 = .cls v.59) (10. 2007 at 13:42 479 (1) Sec.10 4:54 10.58) in (10.5: In other words. the reader can su stitute for IC 2 from (10.60) play a crucial role in our quantitative understand ing of the differential pair’s operation. then expVin1 .68) IEE 1 . 10. In particular.5 10. etermine the differential input voltage that st eers 98 of the tail current to one transistor.63) (10. Vin2 is very positive. Vin2 IEE exp V T = Vin1 .65) (10. can we say IC 1 0 and IC 2 (10.5 .5IEE (10. Vin2 =VT ! 0 and IEE .61) (10.58) and (10. Vin2 is very ne gative.62) . (10. expVin1 . and IEE can e consid ered steered completely to Q2 .5 What is meant y “very” negative or positive? For example.66) 4:54 and IEE IC 2 1 + 4:54 10.

70) IEE exp Vin1 V Vin2 .69) (10. T (10.Example 10.8 Solution We require that IC 1 = 0:02IEE .

8. Exercise What differential input is necessary to steer 90% of the tail current? For the output voltages in Fig. indicating that the differential output vol tage egins from a “saturated” value of +RC IEE for a very negative differential inp ut.RC IEE as Vin1 . Vout2 = .78) Figure 10. Note that this value remains independent of IEE and IS . 2007 at 13:42 480 (1) 480 Chap.73) Vout2 = VCC .3:91VT : £ £ £ £ £ £ ¢ .76) (10. IC 2 . From Example 10. : 1 + exp Vin1 V Vin2 T (10. 10.13 summarizes the results. Vin2 1 + exp VT Vin1 .71) We often say a differential input of 4VT is suf cient to turn one side of the ipo lar pair nearly off. we have Vout1 = VCC . IEE exp Vin1 V Vin2 T = VCC . 1 . gradually ecomes a linear function of Vin1 . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vin2 1 + exp VT and (10. there y concluding that jVin1 . and reaches a saturated level of . Vin2 for relatively small valu es of jVin1 . .cls v.12. 10 ifferential Ampli ers and hence Vin1 . RC IC 1 .RC IC 1 .75) Of particular importance is the output differential voltage: Vout1 .74) (10.77) (10. RC IC 2 = VCC . RC IEE . we recognize that even a differential in put of 4VT 104 mV “switches” the differential pair. Vin2 (10. Vin2 e comes very positive.RC IEE tanh 2V T (10. RC Vin1 .72) (10. Vin2 j. Vin2 j must remain well elow this value for linear operation. Vin2 : = . exp Vin1 V Vin2 T = RC IEE Vin1 .

14(a) in response to the sinusoidal inputs shown in Figs. the circuit operates linearly ecau se the maximum £ £ £ £ . Assume Q1 an d Q2 remain in the forward active region.Example 10.9 Sketch the output waveforms of the ipolar differential pair in Fig. 10. 10.14( ) and (c). 10. Solution For the sinusoids depicted in Fig.14( ).

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 2007 at 13:42 481 (1) Sec.cls v. Vin1 VCC RC V out1 V in1 Q1 P I EE Vout2 (a) Vin1 VCM Vin2 Vin2 t (b) 1 mV 100 mV RC Vout2 Q2 Vin2 VCM t1 (c) t Vout2 1 mV x g m R C VCC VCC − R C I EE 2 VCM Vout1 ¤ ¢ . 10.2 Bipolar ifferential Pair 481 I EE I C2 I C1 0 I EE 2 V in1 − V in2 VCC I EE VCC − R C 2 VCC − R C I EE V out1 V out2 0 V in1 − V in2 + R C I EE V out1 − V out2 0 V in1 − V in2 − R C I EE Figure 10.13 Variation of currents and vo tages as a function of input.

as Vin1 approaches 50 mV above VCM and Vin2 reaches 50 mV be ow V CM (at t = t1 ). 10.14(d)].14(c) force a maximum input difference of 200 mV.79) (10. the sinusoids in Fig. The outputs are therefore sinusoids having a peak amp itude of 1 mV gm RC [Fig. For examp e. turning Q1 or Q2 off . On the other hand.80) VCC : ¤ ¤ ¤ ¤ ¤ ¤ . thus producing Vout1 VCC .14 differentia input is equa to 2 mV.Vout1 t (d) VCC − R C I EE t t1 (e) Figure 10. Q1 absorbs most of the tai current. RC IEE Vout2 (10. 10.

2007 at 13:42 482 (1) 482 Chap. Assuming perfect symmetry. vP = vin1 . (10.vin2 for differentia operation. The ¤¤ ¤ ¤ ¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ Exercise What happens to the above resu ts if the tai current is ha ved? ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¡¤¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . The resu t is sketched in Fig. We say the circuit operates as a “ imiter” in this case. We now study the sma signa behavior of the circui t in greater detai . In Prob em 28 . we prove that this property ho ds in the presence of Ear y effect as we . the de nition of “sma sign a s” is somewhat arbitrary. p aying a ro e simi ar to the diode imiters studied in C hapter 3.82) (10.82) yie ds v1 = . Vin2 j fa s to ess than 100 mV. et us write a KVL around the input network and a K CL at node P : vin1 . In other words. Here. Note that the tai current source is rep aced with an open circuit. but the requirement is that the input signa s not in uen ce the bias currents of Q1 and Q2 appreciab y.15(a). v1 = vP = vin2 . the sma signa mode con rms the prediction made by (10. the two transisto rs must exhibit approximate y equa transconductances—the same condition required for node P to appear as virtua ground.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. an input difference of ess than 10 mV is considered “sma ” for most app ications. for sma differentia inputs. 10 Differentia Amp i ers Thereafter.14(e). In practice. 2006] June 30.86) Thus. the outputs remain saturated unti jVin1 . 10. vin1 and vin2 represent sma chan ges in each input and must satisfy vin1 = .83) = . v2 v1 + g v + v2 + g v = 0: r1 m1 1 r2 m2 2 With r1 = r2 and gm1 = gm2 . and VA = 1.81) (10.81) trans ates to 2vin1 = 2v1 : (10. We a so obtained a vo tage gain equa to gm RC . (10. As with the fore going arge signa ana ysis.84) That is. 10. 10.2. v1 = 0: (10.3 Sma Signa Ana ysis Our brief investigation of the differentia pair in Fig. the tai node maintain s a constant vo tage (and hence is ca ed a “virtua ground”).vin2 .85) (10.11 revea ed that. an idea tai current source.32). As exp ained in previous chapters.v2 and since vin1 (10. 10.c s v. we construct the sma signa mode of the circuit as shown in Fig.

10. With each ha f resemb ing a commonemitter stage.gmRC vin1 (10. this node can be shorted to ac ground. re ducing the differentia pair of Fig.15(a) to two “ha f circuits” [Fig. Since vP = 0.87) ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¡¤ ¤ .15(b)] . we can write vout1 = .virtua ground nature of node P for differentia sma signa inputs simp i es th e ana ysis considerab y. 10.

(c) sim lied diagram. (b) sim li ed small signal mo .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.15 (a) Small signal model of bi olar del. ¤ ¤ ¡ ¤ ¤ ¤ ¤ air.2 Bipo ar Differentia Pair 483 RC v in1 r π1 vπ 1 g m1 RC vπ 1 P (a) g m2 vπ 2 vπ 2 r π2 v in2 RC v in1 r π1 vπ 1 g m1 RC vπ 1 g m2 vπ 2 vπ 2 r π2 v in2 (b) VCC RC RC V in1 Q1 (c) Q2 Vin2 ¡ Figure 10. 2007 at 13:42 483 (1) Sec. 10. 2006] June 30.c s v.

Thus. we may dr aw only one half.16(a). 10.40). vin2 (10. with the understanding that the incremental in uts are small and differential.88) vout1 .10 Com ute the differential gain of the circuit shown in Fig. 10.gmrO vin1 vout2 = . m C vin1 . With ideal current sour ces.91) . the Early effect in Q1 and Q2 cannot be neglected. and the half circuits mu st be visualized as de icted in Fig.16(b).g R .90) (10. For sim licity. Also.gmRC vin2 : It follows that the differential voltage gain of the differential air is equal to (10. where ideal current sources are used as loads to maximize the gain.gmrO vin2 (10.15(c). 10. Exam le 10. vout2 = .vout2 = . Solution vout1 = . since the two halves are identical.89) the same as that ex ressed by (10. we may draw the two half circuits as in Fig.

Exam le 10.17(a) illustrates an im lementation of the to ology shown in Fig.1 6(a). vin2 (10.16 and hence vout1 .g r : m O vin1 . 2006] June 30.cls v. Calculate the differential voltage gain. 10 Differential Am li ers v out Vout V in1 Q1 P I EE (a) (b) Q2 Vin2 v in1 Q1 r O1 r O2 Q2 v in2 Figure 10. 10. vout2 = . 2007 at 13:42 484 (1) 484 VCC Cha .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11 Figure 10.17 .92) Exercise Calculate the gain for VA = 5 V. VCC Vb Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 v in1 Q1 (b) Q3 v out Figure 10.

10. m ON OP vin1 .93) . we have Solution vout1 . vin2 where rON denotes the out ut im eda nce of the n n transistors.Noting that each n device introduces a resistance of rOP at the out ut nodes a nd drawing the half circuit as in Fig. vout2 = .g r jjr .17(b). (10.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Additional exam le s make this conce t clearer. 2006] June 30. R2 Q2 Vin2 V in1 Q3 Vout R1 Q1 ¡ £ ¢ .18 R1 X R2 B ∆V etermine the differential gain of the circuit in Fig. As noted abov e.2 Bi olar Differential Pair 485 Exercise Calculate the gain if Q3 and Q4 are con gured as diode connected devices. this g ain is equal to the singleended gain of each half circuit.12 VCC 1. We now make an observ ation that roves useful in the analysis of differential circuits.18 create a virtual ground at X if (1) R1 = R2 and (2) nodes A and B vary by equal and o osite amounts.12 if the incremental in uts are small and differential. As such. 10. 10.19(a) if VA V Q3 Q4 Vout R1 V in1 Q1 P I EE (a) Example 10. ∆V A Figure 10. This ro erty holds for any other node that a ears on the axis of symmetry. For exam le. 2007 at 13:42 485 (1) Sec. 10. We assume erfect symmetry in each case. the symmetry of the circuit (gm1 = gm2 ) establishes a virtual ground at node P in Fig. the two resistors shown in Fig. 10. We must em hasize that the differential voltage gain is de ned as the difference b etween the out uts divided by the difference between the in uts.cls v.

19 Solution rawing one of the half circuits as shown in Fig.( ) Figure 10. the voltage gain is equal to (10. 10. we express the total resistance seen at the collector of Q1 as Rout = rO1 jjrO3 jjR1 : Thus. the signals need not £ £ ¢ e small in this case.19( ).gm1rO1 jjrO3 jjR1 : 2 Since the resistors are linear.94) (10.95) £ Av = . .

2007 at 13:42 486 (1) 486 Chap. there y serving as current sources and exhi iting only an output ce. leading onceptual half circuit shown in Fig. This is ecause Q3 and Q4 experience a constant ase-emitter voltage cases. X Q4 R2 Q2 Vin2 v in1 Q3 R1 v out1 Q1 Figure 10. and IEE = 1 mA. VX remains constant. 2006] June 30. Calculate the differential gain of the circuit illustrated in Fig. 10. R1 = R2 = 10 k .cls v.20 Solution Av = .20(a) if V A VCC X Q3 R1 Vout V in1 Q1 P I EE (a) ( ) Example 10. 10. £ £ For small differential inputs and outputs. It follows that £ £ £ £ £ £ £ ¢ to the c ove exampl in oth resistan .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13 1. 10 ifferential Ampli ers Exercise Repeat the a ove example if R1 6= R2 .20( )—the same as that in the a e.gm1rO1 jjrO3 jjR1 : (10.96) Exercise Calculate the gain if VA = 4 V for all transistors.

node P is a virtual g round.14 etermine the gain of the degenerated differential pairs shown in Figs. 10.Example 10. 10.21(a).21(a) and ( ). Assume VA = 1. yielding the half circuit depicted in Solution £ ¢ . In the topology of Fig.

RERC 1 : 2 + gm (10.21( ). 10.21(d)]. the line of symmetry passes through the “midpoint” of RE . if RE is regarded as two RE =2 units in series.98) £ ¢ £ £ .21 Fig. 2006] June 30.21(c). 10. 10. In other words. we have Av = . then the node etween the units acts as a virtual ground [Fig. 10.97) m In the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. It follows tha t Av = . From Chapter 5. RE + g1 RC : (10.2 Bipolar ifferential Pair VCC RC X Vout Q1 RE P Q2 RE I EE (a) 487 VCC RC X Vin2 V in1 Q1 RE Vout Q2 RC Y Vin2 RC Y V in1 I EE I EE ( ) RC v out v in1 Q1 RE (c) RC v out v in1 Q1 RE 2 (d) Figure 10. 2007 at 13:42 487 (1) Sec.cls v.

10. and RE = 2=gm. From the equivalent circuit in Fig. r2 : (10.21( ) incorporates a total degeneration resistance of 2RE . Assume VCC VA = 1.22( ). 10.99) £ £ ¢ .The two circuits provide equal gains if the pair in Fig. 10.22(a). I/O Impedances For a differential pair. Exercise esign each circuit for a gain of 5 and power consumption of 2 mW. we can de ne the input impedance as illust rated in Fig. we have v 1 v 2 rpi1 = iX = . = 2:5 V.

obtainin g VCC RC iX Q1 vX Figure 10. 2006] June 30. It is also ossible to de ne a “s ingle ended in ut im edance” with the aid of a half circuit (Fig. v2 = 2r1 iX : It follows that (10. i1 iX (10. Also.103) This result rovides no new information with res ect to that in (10. vX = v1 .23).23 Calculation of single ended in ut im edance. 2007 at 13:42 488 (1) 488 Chap.102) as if the two base emitter junctions a ear in series. 10 ifferential Ampli ers VCC RC iX Q1 Q2 r π1 vπ 1 g m1 RC iX RC vπ 1 P g m2 RC vπ 2 vπ 2 iX r π2 vX I EE vX (a) (b) Figure 10.cls v. vX = r : iX (10. (b) equivalent circuit of (a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the reader can show that the differential and single ended out ut im edances are equal to 2RC and RC . In a manner similar to the foregoing develo men t.102) but ro ves useful in some calculations.101) vX = 2r .22 (a) Method for calculation of differential in ut im edance. The above quantity is cal led the “differential in ut im edance” of the circuit. 1 ¡ ¡ ¡ ¡ ¢ . res ectively. 10.100) (10.

10.3 MOS Differential Pair Most of the rinci les studied in the revious section for the bi olar different ial air a ly directly to the MOS counter art as well. For this reason. . We continue to assume erfect symmetry. our tre atment of the MOS circuit in this section is more concise.

105) That is.6 V.3 MOS Differential Pair 489 ID1 = ID2 = ISS 2 and (10. VTH = 0:5 A MOS differential air is driven with an in ut CM level of 1. VTH : (10.107) It can also be observed that a change in VCM cannot alter ID1 VY undisturbed. what is the maximum allowable load resistance? Figure 10. VTH 2 . Note that t he out ut CM level is equal to VDD . VTH : VDD . We assume = 0 and hence ID = 1=2nCox W=LVGS . we require that their drain voltages not fall below VCM . RD ISS 2 VCM . a greater tail current or a smaller W=L translates to a larger equi librium overdrive. RD ISS =2. leaving VX and = 0:5 mA. each device exhibits an overdrive of v u VGS . RD ISS : 2 (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.106) As ex ected. VGS .24 Res onse of MOS differential air to in ut CM variation. 2007 at 13:42 489 (1) Sec. VTH e quil: .3. and VDD = 1:8 V. Carrying a current of IS S =2. yielding VDD RD X M1 V CM I SS M2 RD Y air with the two in . 2006] June 30. a zero differential in ut gives a zero differential out ut. For our subsequent derivations.1 Qualitative Analysis Figure 10. 10. it is useful to com ute the “equilibrium overdrive voltage” of M1 and M2 . = ID2 = ISS =2.24(a) de icts the MOS uts tied to VCM . To guarantee that M1 and M2 o erate in saturation. If ISS V.104) VX = VY = VDD . VTH equil: = u ISS W : t n Cox L (10. Th e circuit thus rejects in ut CM variations. 10.cls v.

109) . VCM + VTH ISS 2:8 k : (10.108) (10.15 Solution From (10.Exam le 10. we have RD 2 VDD .107).

cls v.25 (a) Res onse of MOS differential air to very ositive in ut. 2006] June 30. (b) r es onse of MOS differential air to very negative in ut. 2007 at 13:42 490 (1) 490 Cha . (c) qualitative lots o . generating VDD RD Vout X V in1 M1 M2 I SS (a) (b) VDD RD Vout Y RD RD Y Vin2 V in1 X M1 M2 Vin2 I SS I SS I D2 I D1 0 I SS 2 VX VY VDD I SS VDD − R D 2 VDD − R D I SS 0 V in1 − V in2 (c) V in1 − V in2 Figure 10. Exercise What is the maximum tail current if the load resistance is 5 k .25(a)]. as ex lained later.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Figure 10. If Vin1 is well above Vin2 [Fig. then M1 carries the entire tail current.25 illustrates the res onse of the MOS air to large differential in u ts. 10. 10 Differential Am li ers We may sus ect that this limitation in turn constrains the voltage gain of the c ircuit.

It follows that ¡ . if Vin2 is well above Vin1 [Fig. RD ISS : (10. VX = VDD . roduc ing a differential out ut in res onse to a differential in ut. then (10. 10.112) (10. (10.110) (10. RD ISS VY = VDD : Similarly. 10. such a scenario mai ntains VP constant because Eqs.25(b)].111) VX = VDD VY = VDD .f currents and voltages. De icted in Fig. Let us now examine the circuit’s behav ior for a small in ut difference.113) The circuit therefore steers the tail current from one side to the other. Figure 10.27) (10.32) a ly to this case equally well.25(c) s ketches the characteristics of the circuit.26(a).

Assume n Cox = 100 A=V2 .116) Av = .out = V .3 MOS Differential Pair VDD RD + ∆V 491 R Y M1 P I SS M2 VCM − ∆V X VCM Figure 10.6 V. we have ISS = 1:11 mA: The output CM level (in the a sence of signals) is equal to (10.gmV and (10. (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 491 (1) Sec. and V = 1:8 V. the differential voltage gain is given £ ¢ £ ¢ £ ¢ £ ¢ ¢ y ¢ .cls v.gmR . each resistor must sustain a voltage drop of no more than 2 00 mV.118) For VCM.out = 1:6 V. R ISS : 2 R = 360 : ¢¢ £ £ VX . = 0.2gmR V: As expected. I 1 = gm V I 2 = . there y assuming a maximum value of ¢ ¢ ¢¢ VCM.16 esign an NMOS differential pair for a voltage gain of 5 and a power udget of 2 mW su ject to the condition that the stage following the differential pair requ ires an input CM level of at least 1. 2006] June 30. 10. similar to that of a common-source stage.115) (10. VY = .117) Example 10. Solution From the power udget and the supply voltage.114) (10.26 Response of MOS pair to small differential inputs.

Since (10. L 2 and hence r W = 1738: L (10.122) ¢ .121) gm = 2n Cox W ISS .120) Setting gm R = 5.(10.119) (10. = 5=360 . we must choose the transistor dimensions such that gm each tr ansistor carries a drain current of ISS =2.

10. discuss the choice of (a) transistor dimensions for a given power udget. Example 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.in V TH (10. If the two circuits are designed for the same voltage ga in and the same supply voltage.out Figure 10. Thus.17 Solution = 0:4 V? We rewrite (10. 2006] June 30. ( ) power dissipation for given transistor dimensions.125) Interestingly.in V . the constraint on the load resistor in this case arises from the output CM level requirement.27 VCM.124) V CM.in I SS M2 V R Y V CM. 10. the input CM level can comforta ly remain at V .107) as VCM.123) (10. 10 ifferential Ampli ers The large aspect ratio arises from the small drop allowed across the load resist ors. 2007 at 13:42 492 (1) 492 Chap.in 2 V: (10. (a) For the two circuits to consume the same amount of power I 1 £ ¢ ¢¢ £ £ £ Exercise If the aspect ratio must remain ¢ ¢¢ £ £ £ ¢ £ ¢¢ ¢ ¢ ¢ elow 200.18 The common-source stage and the differential pair shown in Fig. In contrast to Example 10. R ISS + VTH 2 VCM. Exercise oes the a ove result hold if VTH = 0:2 V. What is the maximum allowa le input CM level in the a ove example if VTH Example 10.27.out + VTH : This is conceptually illustrated in Fig. what voltage gain can e achieved? .28 incorporat e equal load resistors.5. R X M1 V CM.

Solution = ISS = 2I 2 = 2I 3 .e.. i. ¢ ¢ .

Vout2 = . From Fig. our o jective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values . Vout = Vout1 .29 MOS differential pair for large-signal analysis.29.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. I 2 . 2006] June 30.3. 10. 2007 at 13:42 493 (1) Sec.129) £ £ £ £ £ £ ¢ ¢ ¢ £ ¢ ¢ ¢ £ ¢ £ ¢ £ ¢ ¢¢ £ ¢¢ V R ¢ ¢¢ ¢ . I 2 : (10. 10.127) To o tain I 1 .121) therefore requires that th e differential pair transistors e twice as wide as the CS device to o tain the same voltage gain.126) (10. 10. dou ling the po wer consumption. ( ) If the transistors in oth circuits have the same dimensi ons. Exercise iscuss the a ove results if the CS stage and the differential pair incorporate equal source degeneration resistors.28 each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor.3 MOS ifferential Pair V R V in1 v in M1 M1 M2 I SS R Vin2 493 Figure 10.128) (10. Equation (10. VGS1 = Vin2 .cls v. V R V out1 V in1 M1 Vout M2 I SS R Vout2 Vin2 Figure 10. VGS2 I 1 + I 2 = ISS : (10. then the tail current of the differential pair must e twice the ias curre nt of the CS stage for M1 -M3 to have the same transconductance.R I 1 .2 Large-Signal Analysis As with the large-signal analysis of the ipolar pa ir. we neglect channel-length modulation and write a KVL aroun d the input network and a KCL at the tail node: Vin1 .

2 16I 1 I 2 = 2ISS . n Cox W Vin1 . Vin2 2 = We now nd pI I . VGS2 n Cox L 2 W I 1 . we have Vin1 . ¢ ¢ ¢ £ ¢ I 1 + I 2 .128). u VGS = VTH + u 2I W : t n Cox L v u =u t 2 v (10. n Cox W Vin1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 494 (1) 494 Chap. 2 I 1 I 2 ¢ ¢ ¢ ¢ ¢ ¢ ¢ £ ¢ n Cox W L 2 I . L and su stitute ISS . Vin2 2 .131) (10. I 1 for I 2 . Vin2 = VGS1 .130) Su stituting for VGS 1 and VGS 2 in (10. L square the result again. VTH 2 . Vin2 2 .133) (10.cls v. 2006] June 30.134) 4 I 1 I 2 = 2ISS . 1 2 p (10. 10 ifferential Ampli ers = 1=2nCox W=LVGS .132) Squaring oth sides yields Vin1 . 2pI I : = SS 1 2 n Cox W L Since I ¢ ¢ ¢ ¢ ¢ £ ¢ ¢ . I 2 : p p (10.

we show that only the solution with the sum of the two terms is a ccepta le: s (10.139) In Pro lem 44. Vin2 n Cox W 4ISS . Vin2 2 : L (10. I 1 = 2ISS . 16ISS I 1 + 2ISS . Vin2 2 : 2 4 L L s (10. 2ISS : 2 4 L I 1 = ISS + Vin1 . n Cox W Vin1 . n Cox W Vin1 .138) and hence 2 2 I 1 = ISS 1 4ISS . n Cox W Vin1 .p (10. n Cox W Vin1 .140) ¢ ¢ ¢ ¢ £ £ ¢ ¢ .137) It follows that 16I 2 2 .136) 2 16I 1 ISS .135) (10. Vin2 2 = 0 1 L (10. Vin2 2 .

Vin2 j rises. 10. We must therefor e determine the input difference that places one of the transistors at the edge of conduction. Vin2 2 : t 2 L C n ox v (10. But. n Cox W Vin2 . M1 Edge of Conduction + ~0 I SS M2 − I SS + VGS2 M1 VTH − £ ¢ ¢ £ £ £ £ £ £ £ £ ¢ ¢ ¢ ¢ .cls v.141) u I 1 .3 MOS ifferential Pair 495 The symmetry of the circuit also implies that I 2 = ISS + Vin2 . Vin1 . an effect not predicted y our qualitative sketches in Fig.141). Vin2 2 reaches 4ISS =n Cox W=L .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.142) form the foundation of our understanding of the MOS differential pair. dropping to zero for a zero input difference.142) closely. ut leading to lengthy alge ra. Vin1 n Cox W 4ISS . or (10. Vin2 . Vin2 u 4ISSW .142) L Equations (10.25(c). Vin1 2 : 2 4 L L That is. violating the a ove equations. the right-hand side is an odd (symmetric) functio n of Vin1 . we recognize from Fig. I 2 = 1 n Cox W Vin1 . for example. 10. As expected from the cha racteristics in Fig. However. 30 that if.25(c). I 2 fa lls to zero as Vin1 . Furthermore.1 42) to ISS . 2006] June 30.140). 10. (10. 2007 at 13:42 495 (1) Sec. as jVin1 . s (10. it appears that the argumen t of the square root ecomes negative as Vin1 . This can e accomplished y equating (10. 10. Instead. Vin2 2 exceeds this value! How sho uld these results e interpreted? Implicit in our foregoing derivations is the a ssumption that oth transistors are on.140)-(10. Let us now examine (10. at som e point that M1 or M2 turns off. too? That would suggest that I 1 . can the di fference under the square root vanish.

Equation (10. Vin2 jmax = u 2ISSW . then its gate source vo tage fa s to a va ue equa to VTH . A so. the gate source vo tage of M2 must be suf cient y arge to a ccommodate a drain current of ISS : VGS1 = VTH v u VGS2 = VTH + u 2ISSW : t n Cox L It fo ows from (10.145) is inva id for input differences gr eater than this va ue.143) (10.128) that (10.144) v u jVin1 . t n Cox L (10. Indeed.30 MOS differentia pair with one device off. Vin2 jmax denotes the input difference that p aces one transistor at the edge of conduction. approaches the edge of conduction. ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¡ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ .Figure 10.145) where jVin1 .

Vin2 . Vin2 jmax = 2VGS . and (c) differentia output vo tage as a function of input. ID2 j = ISS .max V in1 − V in2 V out1 − V out2 + R D I SS − ∆V in.max .78): the MOS pair steers a of the tai c urrent3 for jVin1 . Speci ca y.145) in (10.31(a).max − R D I SS V in1 − V in2 Figure 10.c s v.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. (10 . we p ot ID1 and ID2 as in Fig. 10.31 Variation of (a) drain currents.142) a so yie ds jID1 . Equation (10. Vin. I SS I D2 I D1 − ∆V in. We a so note that jVin1 . 2007 at 13:42 496 (1) 496 Chap. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤¤ . 2006] June 30.106)] as fo ows: p jVin1 .max 0 (c) + ∆V in. (10. In other words.146) provides a great dea of intuition into the operation of the MOS pair.146) The above ndings are very important and stand in contrast to the behavior of the bipo ar differentia pair and Eq. 10.31(b) and (c).max 0 − I SS (b) − ∆V in.max 0 (a) I SS 2 + ∆V in.max + I SS V in1 − V in2 I D1 − I D2 + ∆V in. Vin2 jmax whereas the bipo ar counterpart on y approaches th is condition for a nite input difference. where Vin = Vin1 .max serves as an abso ute bound on the input signa eve s that have any eff ect on the output. VTH equi : : (10. (b) the difference between drain c urrents. 10 Differentia Amp i ers substituting from (10. arriving at the differentia char acteristics in Figs. Vin2 jmax can be re ated to the equi ibrium overdrive [Eq. The circuit thus behaves inear y for sma va ues of Vin and becomes comp ete y non inear for Vin Vin.

31(c) expands horizonta y. (a) Equati on (10. since ISS RD doub es.32(a) i u strates the resu t. making these observations on y an approximate ¤¤ ¤ ¤¤ 3 In rea ity.max by a factor of 2. 10. or (b) the transistor aspect ratio is doub ed. Thus.Examp e 10. Furthermore. ¤¤ ¤ ¤ ¤¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .19 Examine the input/output characteristic of a MOS differentia pair if (a) the ta i current is doub ed. the characteristic expands vertica y as we .145) suggests that doub ing ISS increases Vin. Figure 10. So ution p VGS = VTH . disp aying a greater s ope. MOS devices carry a sma current for i ustration. the characteristic of Fig.

max y a factor of 2 while maintaining ISS R constan t. (10.148) £ ¢ £ £ £ £ ¤ £ ¤ ¤ ¢¢ £ ¤ £ ¢ ¤ £ ¢ .max 497 V in1 − V in2 V out1 − V out2 + R D I SS − ∆V in.20 esign an NMOS differential pair for a power udget of 3 mW and Assume n Cox = 10 0 A=V2 and V = 1:8 V.max − 2 ∆V in.max = 500 mV.max 2 − R D I SS (b) + ∆V in. p Exercise Repeat the a ove example if (a) the tail current is halved. 2006] June 30. we wri te Solution 2ISS W= 2 L n Cox Vin.c s v. The characteristic therefore contracts horizontally [Fig.145).max − ∆V in.147) (10. 2007 at 13:42 497 (1) Sec. exhi iti ng a larger slope in the vicinity of Vin = 0.max Figure 10.32( )].max 2 V in1 − V in2 + ∆V in. 10.max = 133:6: The value of the load resistors is determined y the required voltage gain. Example 10. Vin.3 MOS Differentia Pair V out1 − V out2 +2R D I SS + R D I SS + ∆V in.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 10. From Eq. The tail current must not exceed 3 mW=1:8 V = 1:67 mA. or ( ) the transisto r aspect ratio is halved.max − ∆V in.max − R D I SS −2 R D I SS (a) + 2 ∆V . (10.32 ( ) ou ling W=L lowers Vin.

v2 2 n Cox W Vin1 . Vin2 u 4ISSW t L n Cox L r = n Cox W ISS Vin1 . 2007 at 13:42 498 (1) 498 Chap. W (10.149) u 1 I 1 . The de nition of “small” signals in this case can e seen from Eq. v1 = vin2 .150) (10.3.153) v1 = .33 (a) Small-signal model of MOS differential pair. Vin2 j then n Cox L 4ISS .cls v.153) (10. we have from (10. I 2 v (10. yielding R v in1 v1 g v m1 1 P (a) RC v in1 v1 g v m1 1 g v m2 2 RC v2 v in2 g v m2 2 R v2 v in2 ( ) Figure 10. (10.142).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the circuit reduces to that shown in Fig. i f jVin1 . and the circ uit operates linearly. ( ) simpli ed circui t.33(a). If = 0.3 Small-Signal Analysis The small-signal analysis of the MOS differential p air proceeds in a manner similar to that in Section 10.152) (10.151) Now. the differential inputs and outputs are linearly proportional. vin1 .3 for the ipolar count erpart. We now use the small-signal model to prove that the tail node remains constant in the presence of small differential inputs. v2 gm1 v1 + gm2 v2 = 0: Assuming perfect symmetry. 10.2. Vin2 : L ¢ £ £ £ £ Exercise How does the a ove design change if the power £ ¢ ¢ ¢ £ ¢ . 10 ifferential Ampli ers udget is raised to 5 mW? 10. 2006] June 30.

(10.154) .

vout1 = . Vout2 from (10.cls v.R I 1 . I 2 p and since gm = n Cox W=LISS (why?). therefore.gm R Vin1 . (10.81)-(10.162) £ This is. Since Vout1 . vin2 Example 10.159) vout1 . leading to the simpli ed topolo gy in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.86) with the o servation t hat v =r = 0 for a MOSFET. 10.21 Prove that (10. Thus.152) translates to vin1 = v1 and hence (10. Vin2 : £ ¢ ¢ £ ¢ ¢ ¢ ¢ ¢ .160) Solution = . Vin2 L = .155) vP = vin1 . and. 10. (10.33( ). vout2 = .156) (10. After all. arriving at the same result. we require vin1 = . With node P acting as a vi rtual ground. small-signal operation simply mea ¢ ¢ Vout1 . 2006] June 30. we have r (10.157) Alternatively. Vout2 = . we can simply utilize Eqs. to e expected.gmR vin1 vout2 = .151) (10. of course.R n Cox W ISS Vin1 . v1 =0 (10. the concept of half circuit applies.3 MOS ifferential Pair 499 and for differential inputs.g R : m vin1 .gmR vin2 . Here.vin2 .161) (10. 2007 at 13:42 499 (1) Sec.158) (10.151) can also yield the differential voltage gain. (10.

34(a).ns approximating the input/output characteristic [Eq. (10. VTH . the analysis o f MOS differential topologies is greatly simpli ed if virtual grounds can e ident i ed. Assume 6= 0. Exercise = 2I =VGS .14. The following examples reinforce this concept.151)] around an operating point (equili rium).22 £ £ ¢ £ £ £ ¢ . (10. express the a ove result in terms of the equili rium As with the ipolar circuits studied in Examples 10.10 and 10. Example 10. etermine the voltage gain of the circuit shown in Fig.142)] with a straight line [Eq. 10. Using the equation gm overdive voltage.

10.gm1 g 1 jjrO3 jjrO1 : m3 £ ¢¢ £ ¢ ¢ .cls v. 2007 at 13:42 500 (1) 500 V M3 Vout V in1 M1 M2 I SS (a) Chap.34 Solution rawing the half circuit as in Fig. 10 ifferential Ampli ers M4 M3 Vin2 v in1 v out1 M1 ( ) Figure 10. The voltage gain is therefo re equal to Av = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34( ). we note that the total resistance seen at the drain of M1 is equal to 1=gm3jjrO3 jjrO1 . 2006] June 30.

we construct the half circuit shown in Fig. 10.35 (a).(10. Solution £ £ ¢¢ £ . Assuming = 0.23 Vout V in1 P I SS1 (a) M3 Q M4 Vin2 v out1 I SS2 v in1 M1 M3 ( ) Figure 10.35 Identifying oth nodes P and Q as virtual grounds. compute the voltage gain of the circuit illustrated in Fig. V Example 10.163) Exercise Repeat the a ove example if a resistance of value R1 is inserted in series with the sources of M3 and M4 .

36 . 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. we o tain the half circuit in Fig.164) Exercise Repeat the a ove example if 6= 0. Assuming = 0.24 v out1 M2 Vin2 v in1 M1 R SS 2 V in1 M1 (a) ( ) Figure 10. gm1 : m3 (10.36 . 10. 2007 at 13:42 501 (1) Sec.cls v.36(a) .4 Cascode ifferential Ampli ers 501 10. 10. V Example 10. where ¢¢ R 2 ¢¢ Vout R R SS £ ¢ £ ¢¢ £ £ . calculate the voltage gain of the topology shown in Fig. Solution Av = . RSS 2 1 : 2 + gm Exercise ¢¢ R £ ¢¢ Grounding the midpoint of RSS and R ( ).35( ). and write g Av = .

165) Repeat the a ove example if the load current sources are replaced with diode-con nected PMOS devices.4 Cascode ifferential Ampli ers Recall from Chapter 9 that cascode stages provide a su stantially higher voltage gain than simple CE and CS stages do.(10. 10. Noting that the differential gain of diff erential pairs is equal to the single- £ ¢ £ .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we express the voltage gain as V CC V 3 Q7 V 2 Q5 Q3 V 1 V in1 Q1 Q2 Vin2 v in1 I EE (a) ( ) Q8 Q6 Vout Q4 Q7 Q5 Q3 v out1 Q1 Figure 10. 10.gm1 gm3 rO3 rO1 jjr3 jj gm5 rO5 rO7 jjr5 : (10. Equation (9. 2007 at 13:42 502 (1) 502 Chap.38( ). We egin our study with the structure depicted in Fig. Av = . Illustrated in Fig. (9. we surmise that cascoding oost s the gain of differential pairs as well. (10.38 (a) Bipolar cascode differential pair with cascode loads. The development s in Chapter 9 also suggest the use of pnp cascodes for current sources I1 and I 2 in Fig.37(a). Utilizing Eq.37 (a) Bipolar cascode differential pair.61) . ( ) half circuit of (a).167) £ £ £ £ £ £ £ £ £ £ £ £ £ £ ¢ .166) con rming that a differential cascode achieves a much higher gain.37(a).38(a). ( ) half circuit of (a). where Q3 and Q4 serve as cascode devices and I1 and I 2 are ideal. 10. 2006] June 30. 10. we constr uct the half circuit shown in Fig. 10. the resulting con guration can e analyzed with the aid of its half circuit.51) readily gives the g ain as VCC I1 Vout Q3 V V in1 Q1 Q2 Vin2 v in1 I EE (a) ( ) I2 Q4 Q3 v out1 Q1 Figure 10.gm1 gm3 rO1 jjr3 rO3 + rO1 jjr3 . 10 ifferential Ampli ers ended gain of their corresponding half circuits. Av .37( ). Fig.cls v. 10. Recognizing that the ases of Q3 and Q4 are at ac ground.

.

ue to a esistance has appeared etween nodes A and the ne the voltage gain of the circuit.39(a).4 Cascode ifferential Ampli ers 503 v in1 I EE Example 10. R1 =2 appears in para llel with rO7 .cls v. Since the valu e of R1 is not given.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a parasitic r circuit of Fig.39( ). (9.39 The symmetry of the circuit implies that the midpoint of R1 is a virtual ground. VCC V 3 Q7 A V 2 Q5 Q3 V 1 V in1 Q1 Q2 Vin2 (a) ( ) £ ¢ £ £ £ ¢ Fig. Thus. lowering the output impedance of the pnp cascode. 10. 10.1): Solution R1 + r jjr jj R1 : Rop = 1 + gm5 rO7 jjr5 jj 2 O5 O7 5 2 Av = . we cannot make approximations and must return to the origi nal expression for the cascode output impedance. etermi £ £ . 2006] June 30.25 B in Q8 B R1 Q6 Vout Q4 Q7 Q5 Q3 R1 2 v out1 Q1 Figure 10.” the topology of ircuit of some operational ampli ers.gm1 gm3 rO3 rO1 jjr2 r jjRop : ¢ £ Called a “telescopic cascode. 10. leading to the half circuit shown in Fig. Eq.38( ) exempli es the internal c manufacturing defect. 10. 2007 at 13:42 503 (1) Sec.

168) The resistance seen looking down into the npn cascode remains unchanged and appr oximately equal to gm3 rO3 rO1 jjr2 . Following the a ove deve lopments for ipolar counterparts.(10.16 9) If = 50 and VA = 4 V for all transistors and IEE gain y a factor of two? Exercise = 1 mA. what value of R1 degrades the We now turn our attention to differential MOS cascodes.4 0(a) and draw the half £ £ £ . 10. The voltage gain is therefore equal to (10. we consider the simpli ed topology of Fig.

V M3 V 1 V in1 Vout M4 M1 M2 I SS (a) M3 Vin2 v in1 v out1 M1 ( ) Figure 10. 2007 at 13:42 504 (1) 504 Chap. (9. Av .72) that the voltage gain is given y V 3 V 2 M5 M3 V 1 V in1 M1 M2 I SS (a) ( ) M7 M8 M6 Vout M4 Vin2 v in1 M5 M3 v out1 M1 Figure 10.69). 10 ifferential Ampli ers circuit as depicted in Fig.40 (a) MOS cascode differential pair.41 (a) MOS telescopic cascode ampli er. ( ) half circuit of (a). yielding the half circuit shown in Fig. 10.41( ).40( ). (9. the complete CMOS telescopic cascode ampli er incorp orates PMOS cascades as load current sources.170) Illustrated in Fig. 10. From Eq.gm3rO3 gm1 rO1 : (10. It follows from Eq. 2006] June 30.41(a). 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Av .gm1 gm3 rO3 rO1 jjgm5 rO5 rO7 Example 10. ( ) half circuit of (a).cls v.26 : £ ¢¢ V M7 £ £ £ £ £ £ £ £ ¢¢ £ £ ¢ .

(10. respectively.171) R1 and R2 . Eq. we must resort to the original expression for the output impedance. Without the value of R1 given.172) £ ¢ . two equal parasitic resistances. 10 . Compute the voltage gain of the circuit. 10. have appeared as Noting that R1 and R2 appear in parallel with rO5 and rO6 .3): Solution Rp = 1 + gm5 rO5 jjR1 rO7 + rO5 jjR1 : (10.ue to a manufacturing defect.42( ). shown in Fig.42(a). we dra w the half circuit as depicted in Fig. (9.

a resistor of value R3 appears etween £ The resistance seen looking into the drain of the NMOS cascode can still oximated as £ £ £ ¢¢ £ £ £ £ e appr .5 Common-Mode Rejection In our study of ipolar and MOS differential pairs.174) Exercise Repeat the a ove example if in addition to the sources of M3 and M4 . 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.173) Av = . The rst nonideality relates to the output impedance of th £ £ R1 and R2 .cls v. 2006] June 30. we have o served that these circuits produce no change in the output if the input CM level changes. in practice the CM reject ion is not in nitely high. we examine the CM rejection in the pre sence of nonidealities.5 Common-Mode Rejection M7 M8 V M7 V 2 M6 M5 M4 M1 M2 I SS (a) ( ) 505 V 3 V 2 M5 M3 V 1 V in1 R1 R2 R1 v out1 Vout M3 Vin2 v in1 M1 Figure 10. 10. 2007 at 13:42 505 (1) Sec. In this section.gm1 Rp jjRn : (10.42 Rn gm3 rO3 rO1 : The voltage gain is then simply equal to (10. As the reader may have guessed. The comm on-mode rejection property of differential circuits plays a critical role in tod ay’s electronic systems.

we can place a short circuit etwe en the output nodes. 10. so d oes VP . so does the current through REE and hence the collector currents o f Q1 and Q2. the output common-mode level falls. 10.e tail current source.43( ). where REE d enotes the output impedance of IEE . from Chapter 5. 10. The change in the output CM level can e computed y noting that the stage in Fig. Q1 and Q2 operate as an emitter follower. What happens if the input CM level changes y a small amount? The symmetry requires that Q1 and Q2 still carry equal curren ts and Vout1 = Vout2 . Consequently. That is. But. noting that Vout1 = Vout2 . That is. As VP increases. Consider the topology shown in Fig. as far as node P is concerned.43(a). £ £ £ £ £ £ £ £ £ . In fact.43( ) resem les a degenerated CE stage. since the ase voltages of oth Q1 and Q2 rise. reducing the topology to that shown in Fig.

cls v.176) where the term 2gm represents the transconductance of the parallel com ination o f Q1 and Q2 . the differential pair produces an output CM change in respon se to an input CM change. with REE 1.CM .43 (a) CM response of differential pair in the presence of pedance. the input CM variation would have no effect at the o utput. 10 ifferential Ampli ers VCC Vout Q2 Q1 P I EE R EE RC 2 V CM R EE (a) ( ) Figure 10. if the circuit suffers from asymmetries and a nit e tail current source impedance. 2 1 Vin. ut not the differential o utput [Fig. Figur e 10. a nite CM gain does not corrupt the differential output and hence proves enign. leading to the output waveforms shown in Fig. ( ) simpli ed circuit of (a).44( ).” These o servations app ly to the MOS counterpart equally well.175) is outlined in Pro lem 65.44(a) illustrates such a situation. experience some common-mode noise. if the tail current exhi its a nit e output impedance. On the other hand .44(c)]. After all. In summary.CM = . two differential inputs. In summary. the single-ended outputs are corrupted. Vin1 and Vin2 . 10. a change in the output CM level introduces no corruption.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.44( ).CM REE + 2g m =. The reader may naturally wonder whether this is a seri ous issue. With an ideal tail current source. (10. 2006] June 30. 10. the a ove study indicates that. then the differential output is corrupted. in the presen ce of input CM noise. the ase voltag es of Q1 and Q2 with respect to ground appear as shown in Fig.175) RC . . Vin. 2007 at 13:42 506 (1) 506 VCC RC V out1 Q1 V CM I EE P Q2 RC Vout2 Chap. uri ¢ £ £ £ £ £ £ £ £ £ £ £ £ £ ¢ nite tail im . Here. 2REE + gm1 RC (10.4 However. This quantity is called the “common-mode gain. so long as the quantity of interest is the difference etw een the outputs. As a result. An alternative approach to arriving at ( 10. Vout. 10.

random “mismatches” appear etween the two sides of the differenti al pair.5 this imperfection leads to a difference etwe en Vout1 and Vout2 . 4 Interestingly. As an example of the effect of asymmetries. we consider the simple case of load resistor mismatch. 5 We h ave chosen a MOS pair here to show that the treatment is the same for oth techn ologies. We must compute the change in I 1 and I 2 and multiply the result y R and R + R . older literature has considered this effect trou lesome.45(a) for a MOS pair. 10. £ ¢ £ £ ¢ ¢ £ ¢ ¢ ¢ £ . Consequently. the transistors or the load resistors may display slightly different dimensions. for example. epicted in Fig. the change in the tail current due to an in put CM variation may affect the differential output.ng manufacturing.

(b) effect of CM nois e at output with REE = ∆V V CM I SS R SS ¢ VDD R D + ∆R Vout2 M1 P M2 ¤ . 10.5 Common-Mode Rejection 507 VCC RC Vout1 A V in1 Q1 P Q2 RC Vout2 B V in2 VA VB VA VB Vout1 Vout1 V CM I EE R EE Vout2 Vout2 Vout1 −Vout2 Vout1 −Vout2 t (a) (b) (c) t 1. 2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 507 (1) Sec. RD V out1 Figure 10.44 (a) Differentia pair sensing input CM noise. (c) effect of CM noise at the output with REE 6= 1.

the load resistor mismatch does not impact the urrents carried y M1 and M2 . ¢ ¢ ¢ ¢ ¢ ¢ £ ¢ ¢ ¢ £ ¢ ¢ £ £ VTH 2 . (10. we re change of 2I RSS £ ¢ . creating a voltage 6 But with 6= 0.6 Writing I 1 = I 2 = I and VGS 1 = cognize that oth I 1 and I 2 ow through RSS . it would. concluding that I 1 must e equal to I 2 ecause VGS 1 = VGS 2 and 2 .177) L 1 I 2 = 2 n Cox W VGS2 .45 MOS pair with asymmetric loads. How do we determine the change in I 1 and I 2 ? Neglecting channel-length modula tion.Figure 10. we rst o serve that 1 I 1 = 2 n Cox W VGS1 . VTH 2 (10.178) L hence VGS 1 = VGS symmetry of c VGS 2 = VGS . In other words.

10 ifferential Ampli ers across it. VCM = VGS + 2I RSS and.179) = I =gm. Thus. 2006] June 30. VCM = I g1 + 2RSS : m That is.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 508 (1) 508 Chap. since VGS (10. ¢ ¢ ¢ ¢ .

Assume VA Example 10.27 Solution = 1 for Q1 and Q2 . M = 1 : + 2f 1 + gm3 R1 jjr3 (10. 1 VCM R : g + 2RSS ¢ Produced y each transistor. In practice.183) (10. M .184) (10.) We say the cir cuit exhi its “common mode to differential mode ( M) conversion” and denote the a ov e gain y ACM .182) (10. this current change ows through oth R and R +R there y generating a differential output change of . Recall from Chapter 5 that emitter degeneration raises the output impedance to Rout3 = 1 + gm3 R1 jjr3 rO3 + R1 jjr3 : Replacing this value for RSS in (10. a ipolar cur rent source may employ emitter degeneration and a MOS current source may incorpo rate a relatively long transistor. M 2R SS : £ £ £ ¢ £ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ Vout = Vout1 .(10.186) (This result can also e o tained through small-signal analysis.46. ¢ ¢ £ £ £ ¢ £ £ ¢ ¢ £ £ ¢ ¢ ¢ .181) (10.189) rO3 + R1 jjr3 g gm1 ¢ ¢ R ACM .185) R Vout VCM = 1 + 2RSS : g m (10. It is therefore reasona le to assume RSS 1=gm and (10.I R = . 10. For example.186) yields (10. Vout2 = I m It follows that R . M for the circuit shown in Fig.188) RC ACM .180) I = 1 VCM : g + 2RSS m (10.187) etermine ACM . we strive to minimize this corruption y maximi zing the output impedance of the tail current source. I R + R = .

This effect is eyond the scope of this ook [1].46 Exercise Calculate the a ove result if R1 ! 1.28 Calculate the CMRR of the circuit in Fig.. If the circuit provides a large differential gain.191) m CMRR = g1 RC g 1 + 2 1 + gm3 R1 jjr3 rO3 + 2R1 jjr3 : RC m1 Exercise etermine the CMRR if R1 ! 1. ¢ £ ¢ £ £ £ £ ¢ £ £ £ £ ¢ ¢ ¢ ¢ . 10.g.46. A M . While undesira le . (10. and the differential gain is equal to gm1 RC . Thus. 1).” CMRR serves as a measure of how much wanted s ignal and how much unwanted corruption appear at the output if the input consist s of a differential component and common-mode noise. Example 10.5 Common-Mode Rejection VCC RC V out1 Q1 V CM P R out3 V Q3 R1 Q2 R C + ∆R C Vout2 509 Figure 10. 10. RC RC . We therefore de ne the “common-mode rejection ratio” (CMRR) as CMRR = A A M : CM . 2007 at 13:42 509 (1) Sec. M . Solution For small mismatches (e.190) Representing the ratio of “good” to “ ad.M conversion cannot e simply quanti ed y ACM . CM. then the relative corruption at the output is small. M (10. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. The mismatches etween the transistors in a differential pair also lead to CM.M conversion.

48. 47(a)]. the circuit emp loys a symmetric differential pair.6 ifferential Pair with Active Load In this section. we study an interesting com ination of differential pairs and c urrent mirrors that proves useful in many applications. £ £ £ £ £ £ ¢ £ ¢ £ £ ¢ . 10. We may naturally conside r the topology shown in Fig.7 Unfortunately. the voltage gain is now halved ecause the signal swing at node X is not used. Q1 -Q2 . Shown in Fig. 10. Recall that the op amps used in Chapter 8 have a differential input ut a single-ended output [Fig. let us rst address a pro lem encountered in some cases. 2007 at 13:42 510 (1) 510 Chap.47 (a) Circuit with differential input and single-ended output . Here. the internal circuits of such op amps must incorporate a stage tha t “converts” a differential input to a single-ended output. along with a current-mirror load. VCC RC V in1 V in2 Vout X V in1 V in2 RC Y Vout (a) ( ) Figure 10. VCC Q3 N V in1 Q1 Q2 Vin2 Vout Q4 I EE Figure 10.48 ifferential pair with active load. 7 In practice. ( ) possi le implementation of (a).) The output is sensed with re spect to ground. Thus. We now introduce a topology that serves the task of “differential to single-ended” c onversion while resolving the a ove issues. the ou tput is sensed at node Y with respect to ground rather than with respect to node X .47( ) as a candidate for this task. additional stages precede this stage so as to provide a high gain . (Transistors Q3 and Q4 are also identical. Q 3 -Q4 . To arrive at the circuit . 10 ifferential Ampli ers 10.cls v. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.

2007 at 13:42 511 (1) Sec.1 Qualitative Analysis It is instructive to rst decompose the circuit of Fig .6 ifferential Pair with Active Load 511 10. ( ) response of active load to current change. Q1 and Q2 prod uce equal and opposite changes in their collector currents in response to a diff erential ∆I R L V I EE 2 + ∆V + ∆I I EE 2 CC − ∆I Q3 N − ∆V Q4 VCM Q1 P Q2 VCM I EE 2 + ∆I ∆I R L RL I EE (a) ( ) Figure 10. As depicted in Fig. 2006] June 30. 10.6.cls v. 10. 10.48 into two sections: the input differential pair and the current-mirror lo ad. £ £ £ ¢ RL V .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49 (a) Response of input pair to input change.49(a) (along with a ctitious load RL ).

RL . What happens? First.50 etailed operation of pair with active load. Now consider th e circuit in Fig. £ £ ¢ Figure 10. is added to augment our intuition ut it is not necessary for the actu al operation. In other words. 10. the collector current of Q4 also incr eases y I . Vout rises. since the small-signal impedance seen at node N is approximately equal to 1=gm3 . £ £ £ £ £ £ £ £ £ £ £ £ .change at the input. IC 1 . jIC 3 j. The output change can therefore e an ampli ed version of V . The load resis tor. Ignoring the role of Q3 and Q4 for the moment. in response to the differential input shown in F ig. 10. differential change s at the input and follow the signals to the output (Fig.50). we note that IC 1 incre ases y some amount I and IC 2 decreases y the same amount. creating a voltage change of IRL across RL . VCC Q3 N I EE 2 + ∆V + ∆I Q4 I C4 I EE 2 − ∆I RL Vout VCM Q1 P Q2 VCM − ∆V I EE Let us now determine how the change in IC 1 travels through Q3 and Q4 . As a result.49( ) and suppose the current drawn from Q3 increases from IEE =2 to IEE =2 + I . we apply small. With the input voltage changes shown here. Since Q4 “injects” a greater c urrent into the output node. S econd. Neglecti ng the ase currents of these two transistors. In order to under stand the detailed operation of the circuit. y virtue of current mirror action. This change is copied into IC 4 y virtue of the current mirror action. we o serve that the fall in IC 2 translates to a rise in Vout ecause Q2 draws less current from RL . VN changes y I=gm3 (for small I ). 10. we recognize that the change in I C 3 is also equal to I . and jIC 4 j increase y I . the voltage across RL changes y IRL .50.

(In this circuit.) 10.54) to demonstrate that oth CMOS and ipolar versions are tr £ ¢ ¢ £ £ ¢ £ ¢ £ £ £ ¢ £ ¢ ¢ ¢ £ £ ¢ . This also stands in contrast to the curr ent-source loads in Fig. vin1 . To con rm this conjectur e. We deal with a CMOS implementa tion here (Fig. the current mirror transistors are identical. the com ination of Q3 and Q4 p lays a critical role in the operation of the circuit. 10. Q3 and Q4 [Fig.47( )].6 . 10. 10. VCC Q3 N V in1 Q1 Path 1 Path 2 Q4 Q2 Vin2 Vout I EE Figure 10. 2006] June 30. 10. each path forces Vout to increase. we wish to determine the small-signal single-ended output. 10 ifferential Ampli ers In summary.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.51(a)].52 ifferential pair with current-source loads.. Called an “active load” to distin guish it from the load transistors in Fig.52.50 indicates an interesting diff erence with respect to current mirrors studied in Chapter 9: here Q3 and Q4 carr y signals in addition to ias currents. 10. VCC V Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 Figure 10. Specifically.51 Signal paths in pair with active load.2 Quantitative Analysis The existence of the signal paths in the differential t o single-ended converter circuit suggests that the voltage gain of the circuit m ust e greater than that of a differential topology in which only one output nod e is sensed with respect to ground [e. increasing jI 4 j and raising V out . the change in I 1 and I 3 is copied into I 4 . 2007 at 13:42 512 (1) 512 Chap.52. The foregoing analysis directly applies to the CMOS counterpart. the circuit of Fig. differential input.50 contains two signal paths. in response to a small. The key point here is that the two paths enhance ea ch other at the output. divided y the smallsignal differential input. in the a ove example. too.53. 10. where the aseemitter voltage of the load transi stors remains constant and independent of signals. shown in Fig. 1 0. The change in I 2 tends to raise Vout . vin2 . Fig. For a differential in put change.g. 10. I 1 rises to ISS =2 + I and I 2 falls to ISS =2 . Also . I . vout . Our initial examination of Q3 and Q4 in Fig. one through Q1 and Q2 and another through Q1 . each path experiences a current change. which translates to a voltag e change at the output node.

eated identically. .

Approach I Without a half circui t availa le.53 MOS differential pair with active load. M3 . we expect a relatively small voltage swing—on the order of the input swing—at th is node. We present two approaches to solving this circuit. With the diodeconnected device.6 ifferential Pair with Active Load V M3 + ∆V 513 M4 RL M1 M2 I SS − ∆V Vout Figure 10. 55.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the analysis can e performed through the use of a complete small-s ignal model of the ampli er. M3 A V in1 M1 P I SS M2 Figure 10. In M3 1 g mP M4 g v mP A iY r ON r ON P g v mN 2 v2 M2 v in2 r OP vA iX g v mN 1 r OP v out £ £ £ ¢¢ V ¢¢ ¢ M4 Vout Vin2 . 2006] June 30. we perform the analysis in two steps.cls v. 2007 at 13:42 513 (1) Sec.) The asymmetry resulting from the very different voltage swings at t he drains of M1 and M2 disallows grounding node P for small-signal analysis. Referring to the equivalent circuit shown in Fig. On the other hand.54 presents a quandary. 10. While the transistors themselves are symmetric and the input signals are small and differential. 10. the circuit serves as an ampli er. The circuit of Fig. the circuit is a symmetric.54 MOS pair for small-signal analysis. 10. creating a low impedance at node A. where the dashed oxes indicate each transistor. transistors M2 and M4 provide a high impedance and h ence a large voltage swing at the output node. (After all.

A v in1 v1 M1 Figure 10. the rst step. we note that iX and iY must add up to zero at node P and hence iX = .iY . Also.55 (a) Small-signal equivalent circuit of differential pair with activ e load. .

192) (10. gmN v1 rON . then vout (10.cls v. iY .195) In the second step. It follows that .198) Solving for vout yields vout rOP 1 + gmP g 1 jjrOP vout mP : (10. vin2 = gmN rON 2rON + 2rOP This is the exact expression for the gain. The current through rON of M1 is equal to iX . gmN rON vin1 .vA + iX .200) vin1 . 2007 at 13:42 514 (1) 514 Chap. gmN v1 and that through rO N of M2 equal to iY .iY = r out + gmP vA OP vout .193) (10. we have (10.199) vin1 . 10 ifferential Ampli ers and 1 jjr =r mP X g OP . g i OP = iX : mP (10.197) 1 vout 1 jjr gmP jjrOP + 2rON r 1 + g vout = gmN rON vin1 . gmN v2 rON + vout = 0: Since v1 . v2 (10.196) = vin1 . vin2 and iX = .iY . 2006] June 30. vin2 : (10. . we write a KVL around the loop consisting of all four transi stors. vin2 + vout = 0: Su stituting for vA and iX from a ove. iX = rOP 1 + gmP g 1 jjrOP mP .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 vA = . gmN v2 .194) Thus.vA + 2iX rON . If gmP rOP 1.iX gmP jjrOP vout : (10. vi n2 = gmN rON jjrOP : The gain is indepedent of gmP and equal to that of the fully1 jjr rOP 1 + gmP g OP mP g OP OP mP mP + £ £ ¢ v .

M1 and M2 . Recall that vThev is the voltage etween A and B in the “open -circuit condition” This section can e skipped in a rst reading. £ £ £ . assuming vin1 and vi n2 are differential. w e decompose the circuit into sections that more easily lend themselves to analys is y inspection.differential circuit. In other words.56(a). Approach II In this approach. the use of the active load has restored the gain. 10. we rst seek a Thevenin equival ent for the section consisting of vin1 . As illustrated in Fig. vin2 .

2007 at 13:42 515 (1) Sec. Havi ng reduced the input sources and transistors to a Thevenin equivalent. To determine the Thevenin resistance.92) thus yields vThev = . gm1 v1 rO1 + iX + gm2 v2 rO2 = vX and hence (10. we set the inputs to zero and apply a volt age etween the output terminals [Fig.gmN rON vin1 . where the su script N refers to NMOS devices. and (c) Thev enin resistance of input pair.56(c)]. M3 A v in1 M1 P I SS M2 V M4 B v out v in2 (10. vin2 . 10.6 ifferential Pair with Active Load 515 [Fig. the circuit is symmetric. we ha ve iX .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. Since the voltage at node E with respect to ground is equal to vout + vThev . 10. The o jective is to calculate vout in term s of vThev .202) RThev = 2rON : (10.56( )].16(a). Figure 10. Equation (10. we now co mpute the gain of the overall ampli er.201) v Thev R Thev (a) vX iX iX M2 r O1 r O2 P I SS v2 v Thev A v in1 M1 P I SS M2 B v in2 M1 v1 ( ) (c) Figure 10.57 depicts the simpli ed circuit. Noting that M1 and M2 have equ al gate-source voltages (v1 = v2 ) and writing a KVL around the “output” loop. Under this condition.203) The reader is encouraged to o tain this result using half circuits as well. we can view vA as a divided version of vE : £ £ £ £ ¢¢ £ £ £ £ ¢ .cls v. where the diodeconnected transistor M3 is replaced with 1=gm3 jjrO3 and the output impedance of M4 is drawn explicitly.56 (a) Thevenin equivalent. 2006] June 30. ( ) Thevenin voltage. 10. resem ling the topology of Fig.

1 gm3 jjrO3 vout + vThev : vA = 1 gm3 jjrO3 + RThev (10.204) .

and 1=gm3 rO3 = rO4 = rOP . rO4 gm3 jjrO3 + RThev (10. vin2 ON OP ON and hence + vout = 0: C out Thev A owing through RT £ ¢¢ ifferential Ampli ers ¢ .207) 2 v + v + vout = 0: out Thev R r Thev Equations (10.206) Recognizing that 1=gm3 rO3 . 2007 at 13:42 516 (1) 516 r O3 1 g m3 Chap. we reduce (10. 2006] June 30.57 Simpli ed circuit for calculation of voltage gain.205) where the last term on the left hand side represents the current hev .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.204) and (10. 10 V M4 R Thev v Thev E B v out r O4 A Figure 10. the small-signal drain current of M4 must satisfy KCL at the o utput node: gm4vA + vout + 1 vout + vThev = 0. It follows from (10.205) that 0 Bg B m4 @ 1 + 1 1 jjr + R gm3 O3 Thev gm3 jjrO3 + RThev 1 gm3 jjrO3 1 C v + v rO4 (10.201) and (10.206) to RThev and assuming gm3 = gm4 = gmp and OP (10.cls v. Given y gm4 vA .207) therefore give vout r 1 + r 1 = gmN rONr vin1 .

vin2 = gmN rON jjrOP : (10.29 Solution vA = .(10. Interestingly. Prove this point.vout rO4 + gm4 vA g 1 jjrO3 : m3 £ £ £ £ .vout =rO4 . As de picted in Fig.51( ).56 is much less than that at the output.209) The gain is independent of gmp . 10. 10. This current ows through M1 and hence through M3 . generating Example 10. we surmised that the voltage swing at no de A in Fig. KCL at the output node indicates that the total current dr awn y M2 must e equal to .58. In other words. the path through the active load restores the gain even though the output is sin gle-ended. gm4 vA . In our earlier o servations.208) vout vin1 . 10. the gain of this circuit is the same as the differential gain of the topology in Fig.

210) .(10.

The pair can then be decomposed into two ha f circuits. The tai current can be most y steered to one side with a differ entia input of about 4VT .. For sma signa operation.58 Exercise Ca cu ate the vo tage gain from the differentia input to node A. A differentia signa consists of two sing e ended signa s carried over two wires. MOS differentia pairs can steer the tai current with a differentia input equa to p 2ISS =n Cox W=L.211) V M4 r O4 v out M1 P I SS M2 +v in r O3 A −v in Figure 10. and two identica oads. the circuit “rejects” input CM changes. 2g vout . which is 2 arger than the equi ibrium overdrive of each transistor. 2006] June 30. The transistor currents change in opposite d irections if a differentia input is app ied. vA . i. ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¢¢ ¤ ¤ . a tai current. 1 g m3 (10. 2007 at 13:42 517 (1) Sec. r mP OP revealing that vA is indeed much less that vout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. with the t wo components beginning from the same dc (common mode) eve and changing by equ a and opposite amounts.e. the circuit responds to diff erentia inputs. differentia signa s are more immune to common mode noise. Compared with sing e ended signa s.. differentia changes at the input. i.cls v.7 Chapter Summary Sing e ended signa s are vo tages measured with respect to ground.e. Bipo ar differentia pairs exhibit a hyperbo ic tangent input/output characteristic. the input differentia s wing of a bipo ar differentia pair must remain be ow rough y VT . each of which is simp y a common emit ter stage. A differentia pair consists of two iden tica transistors. For sma . 10.7 Chapter Summary 517 That is. The transistor curre nts in a differentia pair remain constant as the input CM eve changes. the tai node vo tage of a differentia pair remains constant and is thus considered a virtua gr ound node.

p .

¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¡ ¡ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . The input transistors of a differentia pair can be cascoded so as to achieve a high er vo tage gain. 2. 3. 2006] June 30. 10 Differentia Amp i ers Un ike their bipo ar counterparts. 10. MOS differentia pairs can provide more or e ss inear characteristics depending on the choice of the device dimensions. Repeat Prob em 1 for the stage s shown in Fig. A so. To ca cu ate the effect of ripp e at the output of the circuit in Fig. 10. assuming VA 1.60 at X and Y and determine their peak to peak swings and common mode eve . 10. corrupting the desired signa .I0 cos !t + I0 . The circuit is ca ed a differentia pair with active oad. Assume VA 1 and 0. Repeat Prob em 1 for the c ircuit of Fig. Simi ar y.61. 5. we can assume VCC is a sma signa “input” and determine the (sma signa ) gain fr om VCC to Vout .c s v. In the presence of asymmetries and a nite tai current source impedance. 10. The differentia output of a perfect y symmetric differentia pair remains f ree from input CM changes.59. Compute this gain. the oads can be cascoded to maximize the vo tage ga in. P ot the waveforms VCC I1 X RC Y RC I2 Figure 10. assuming RC 1 = RC 2 . Prob ems 1. In the circuit of Fig.2(a). It is possib e to rep ace the oads of a differentia pair w ith a current mirror so as to provide a sing e ended output whi e maintaining th e origina gain. The gain seen by the CM c hange norma ized to the gain seen by the desired signa is ca ed the common mod e rejection ration.1.60. I1 = I0 cos !t + I0 and I2 = . 10.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. p ot the vo tage at node P as a function of time. 2007 at 13:42 518 (1) 518 Chap. VCC RC Vout Q1 V in I EE Vb V in M1 RS RD Vout VDD V in VCC Q1 Vout I EE RS V in VDD M1 Vout (a) (b) (c) (d) Figure 10. a fraction of the input CM change appears as a differentia c omponent at the output. Rep eat Prob em 4 for the circuit depicted in Fig.59 4.

VCC RC X I1 Y I2 IT RC RC X I1 IT VCC RC Y I2 RC RP X I1 Y I2 VCC RC RC X I1 Y I 2 RP VCC RC (a) (b) (c) (d) Figure 10. p ot VP as a functio n of time for the circuits shown in Fig. VCC I1 X RC Vb Y RC I2 Figure 10. p ot VX and VY as a function of time for the circuits i ustrated in F ig.61 VCC RC X I1 RC Y I2 Figure 10. 7.63 8. Assuming V1 = V0 cos !t + V0 and V2 = .7 Chapter Summary VCC R1 RC X I1 P RC Y I2 519 Figure 10. Assume I1 is constant. Repeat Prob em 4 for the topo ogy shown in Fig. Assume IT is constant. Repeat Prob em 4.c s v. 10. 10.64 10. Assuming I1 = I0 cos !t + I0 and I2 = . 10.64.I0 cos !t + I0 .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.62.62 6. Can X and Y be conside red true differentia signa s? 9. 2006] June 30. Repeat Prob em 4 fo r the topo ogy shown in Fig. 10.V0 cos !t + V0 . but assume I2 = .I0 cos !t + 0:8I0 . 10. ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .63. 2007 at 13:42 519 (1) Sec.65.

(10. VCC rises by V . In the circuit of Fig. 10.65 11. 10. Consider the circuit of Fig.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. How do VX .7. VY . Using Eq.58). 17. how does IC 1 =IC 2 change if the temperature rises from 27 C t o 100 C? 19. What is the maximum a owab e va ue of IEE if Q2 must remain in the active region? 16. 10. In the circuit of Fig. What is the corresponding input differentia vo tage? With this vo tage app ied. 10. 10.10 if (a) IEE is ha ved. 14. (b) V CC rises by V . IEE experiences a change of I . VY . VC 2 in1 in2 : V ¤ ¤ ¤ ¤ ¤¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ . In the differentia pair of Fig. Repeat Prob em 12. determine the change in VX . VY . Exp ain why we say the circuit “rejects” supp y noise. determine the maximum a owab e input. determin e the input difference at which the transconductance of Q2 drops by a factor of 2.c s v. and VX .9(a) and assume IEE = 1 m A. 10 RC RC P V1 V2 (b) Differentia Amp i ers RC RC P V1 V2 (c) RC P I1 R1 Figure 10.12.9(b).9(a). 2007 at 13:42 520 (1) 520 RC V1 V2 (a) Chap. IC 1 =IC 2 = 5. 2006] June 30.58). RC = 500 .I Gm = @@IC 1 . Suppose the input differentia signa app ied to a bipo ar differen tia pair must not change the transconductance (and hence the bias current) of e ach transistor by more than 10. What is the maximum a owab e va ue of RC if Q1 must remain in the active reg ion? 15.12: . Determine the region of operation of Q1 . It is possib e to de ne a differentia transconductance for the bipo ar dif ferentia pair of Fig. What h appens to the characteristics depicted in Fig. and VX . 10. 21.7. 12. 20. In Fig. VY change? 13. the sma signa transconductance of Q 2 fa s as Vin1 . Suppose in Fig. From Eq. or (c) RC is ha ved? 18. 10. Neg ect the Ear y effect. Suppose IEE = 1 mA an d RC = 800 in Fig.12. (10. but assuming that RC 1 = RC 2 + R. 10. 10. Vin2 rises because IC 2 decreases. Neg ecting the Ear y effect.

Vout2 in1 in2 (10. compute Gm and p ot the resu t as a function in1 .60). (10. (10. we can compute the sma signa vo tage gain of the bipo ar erentia pair: out .58) and (10. Vin2 contains a dc component of 30 mV. Vin2 Gm drop by a factor of two with respect to its maximum va ue? 22. : of V does aid diff ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤ ¤ ¤ . 23. With the of Eq.(10.13 if the ambient temperature goes from 27 C to 100 C. Exp ain what happens to the characteristics shown in Fig. 10. What is the maximum va ue of Gm ? At what va ue of Vin1 .78). Vin2 .212) From Eqs. V Av = @@ VV 1 .213) Determine the gain and compute its va ue if Vin1 .

and VCC = 2:5 V.215) Vin1 = V0 sin !t + VCM Vin2 = .7 Chapter Summary 521 24. In Examp e 10. Assume (10. The study in Examp e 10. ca cu ate the required tai current.9 suggests that a differentia pair can convert a sinusoid to a square wave.9. In Prob em 25.66. prove that Eq.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. p ot the output waveforms if V0 = 80 mV or 160 mV.p = 4 V.67 30. 29. 10. Using the circuit parameters given in Prob em 24. (10. 2006] June 30. Consider the circuit shown in Fig. 2 7. (a) If V0 = 2 mV.68. Ca cu ate the vo tage gain of the circuit. Repeat the sma signa ana ysis of Fig. 10.p = 4 V.68 must provide a gain of 50 with R1 = R2 = 5 k . VA.67. 10. 10. VCC Vout V in1 Q1 P I EE Q2 Vin2 Figure 10. where VCM = 1 V denotes the input common mode eve . (First. 25. In F ig. Exp ain why the output square wave becomes “sharper” as the input amp itude increases. 2007 at 13:42 521 (1) Sec. Using a sma signa mode and inc uding the output resistance of the transi stors. prove that P is sti a virtua ground. IEE = 1 mA and VA = 5 V.214) (10.V0 sin !t + VCM . determine the time t1 at which one transistor carries 95 of the tai current.c s v.) VCC RC Vout V in1 Q1 P I EE Q2 Vin2 RC R EE Figure 10. (b) If V0 = 50 mV. What va ue of R1 = R2 a ows a vo tage gain of 50? 31. p ot the output waveforms (as a function of time). 26.86 ho ds in the presence of the Ear y effect. RC = 500 . If VA. The circuit of Fig . IEE = 1 mA.n = 5 V VA.n = 5 V and VA. where IEE = 2 mA. 10. 10. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . P ot the output wavefo rms.66 28. N ote that the gain is independent of the tai current. estimat e the s ope of the output square waves for V0 = 80 mV or 160 mV if ! = 2 100 MHz.15 for the circuit shown in Fig.

Consider the differentia pair i ustrated in Fig.69. 10.Gm Rout in some cases. 10. 34.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. 2006] June 30.7 ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .69 33. 10 VCC Q4 Differentia Amp i ers Vin2 Figure 10. 10. compute the differentia vo tage gain of each VCC RC Vout RC R2 Q4 V in1 Q2 Vin2 R1 Q1 P I EE R2 Q2 Vin2 (b) VCC R1 Q3 V in1 Q1 P I EE (c) VCC R1 R2 Q4 Vout V in1 Q1 P I EE (d) R2 Vout Q2 Q4 Vin2 Q3 Q2 Vin2 Figure 10.68 32. 2007 at 13:42 522 (1) 522 X Q3 R1 Vout V in1 Q1 P I EE Q2 R2 Chap. VCC R1 Q3 Vout V in1 Q1 P I EE (a) 1. Assuming perfect symmetry and VA 1. compute the differentia vo tage gain of each stage depicted in Fig.70. You may need to compute the gain as Av = .c s v. Assuming perfect symmetry and VA stage depicted in Fig.

(a) Determine the vo tage gain. (b) Und er what condition does the gain become independent of the tai currents? This is an examp e of a very inear circuit because the gain does not vary with the inp ut or output signa eve s. Assuming perfect symmetry and VA = 1.1. ¤ ¤ ¤ ¤ ¤ ¤ ¤ .

36. If n Cox = 100 A=V and W=L = 20=0:18. 10.c s v.70 VCC Q3 RC Vout V in1 Q1 RE Q2 Vin2 Q4 RC I EE I EE Figure 10. VCM = 1 V.24. (c) th e gate oxide thickness is doub ed. 10. Consider the MOS differentia pair of Fig. differentia inputs. 40.71 35. In Fig. what is the required va ue of ISS ? 38. What is the minimum a owab e supp y vo tage if the transistors must remain in saturation? Assume VTH. 2007 at 13:42 523 (1) Sec.n = 0:5 V.72). Formu ate the trade of ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¡¤¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Without using the sma signa mode . A MOS differentia pair contains a parasitic resistance tied bet ween its tai node and ground (Fig. 39. 10.24 must be designed for an equi ibrium overdr ive of 2 200 mV. For a MOSFET. What happens to the tai n ode vo tage if (a) the width of M1 and M2 is doub ed. Vin1 = 1:5 V and Vin2 = 0:3 V. Repeat Examp e 10.25(a). determine a co ndition among the circuit parameters that guarantees operation of M1 in saturati on.2 4. In the MOS differentia pair of Fig. Exp ain how the equi ibriu m overdrive vo tage of a MOS differentia pair varies as a function of the curre nt density. 10. and RD = 1 k .16 for a supp y vo tage of 2 V. (b) ISS is doub ed. the “current density” can be de ned as the drain current di vided by the device width for a given channe ength. 10. 41. Th e MOS differentia pair of Fig. prove that P is sti a virtua ground for sma . 10. 37. ISS = 1 mA. 2006] June 30.7 Chapter Summary VCC RC Vout RC RC Vout Q2 RE P RE R SS (a) 523 VCC RC V in1 Q1 Vin2 V in1 Q1 R1 RE P R2 Q2 RE R SS Vin2 (b) Figure 10. Assuming M2 is off.

f between VDD and W=L for a given output common mode eve . ¤ ¤ ¤ ¤¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ . Exp ain which aspects of our differentia signa s and amp i ers this circuit vio ates. An adventurous s tudent constructs the circuit shown in Fig. 42. Vin2 . 10.73 and ca s it a “differentia amp i er” because ID Vin1 .

(b) the thresho d vo tage is ha v ed.c s v. (c) At what va ue of Vin1 . 50. determine the va ue of Vin1 . (10. (a) What simi arities exist between this circuit and the s tandard MOS differentia pair? (b) Ca cu ate the equi ibrium overdrive vo tage o f T1 and T2 . From Eq. 46.I Gm = @@V D1 . 45. VTH 3 . (10. 10. Vin2 at 2. 10 VDD RD X V in1 I SS M1 M2 P R SS RD Y Vin2 Differentia Amp i ers Figure 10. 2007 at 13:42 524 (1) 524 Chap. (10. and (c) ID1 = ISS . ID2 = ISS . Verify p that is resu t is equa to 2 times the equ i ibrium overdrive vo tage. de ned as I .74 shows a differentia pair emp oy ing such transistors. Figure 10. 47 ate the va ue of Vin1 .142). (b) ID1 = ISS =2.72 VDD RD Vout V in1 M1 Vin2 Figure 10.134) for the fo owing cases: (a) ID1 = 0. (c) ISS and W=L are ha ved. Assuming that the mobi ity of carriers fa s at high temperatures. compute the sma signa tran sconductance of a MOS differentia pair. Using the resu t obtained in Prob em 46.31 as the temperature rises. Vin2 such that ID1 .139) is a ways negative if the so ution with the negati ve sign is considered. exp ain what happens to the characteristics of Fig. Prove that the ri ght hand side of Eq. 10. Suppose a new type of MO fo owing I V characteristic: ¤ ¡¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Vin2 does one transistor turn off? 49. VD2 : in1 in2 (10. From Eq. (10. 44. Vin2 and .142).31 if (a) the gate oxide thickness of the transistor is doub ed. Examine Eq. Exp ain what happens to the characteristics shown in Fig.217) where is a proportiona ity factor. 2006] June 30. Exp ain the signi cance of these cases. 48. (10.216) ID = VGS . ca cu which the transconductance drops by a factor of S transistor has been invented that exhibits the determine its maximum va ue.73 43. ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¤ P ot the resu t as a function of Vin1 .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.

(b) Viewing M1 as a source fo ow er and M2 as a common gate stage.76. 77. ¤¤ ¡ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¡ ¡ ¤ ¤ ¤ 51.75 (a) Viewing M1 as a common source stage degenerated by the impedance seen at the source of M2 . Ca cu ate the differentia vo tage gain of the circuits depicted in Fig. 2006] June 30.c s v. how does it compare with the gain of differentia y driven pair s? 52. You may need to compute the gain as Av = . hoping to obtain differentia outputs. Assume perfect symmetry and 0. in ut VDD A student who has a sing e ended vo tage source constructs the circuit shown Fig.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.7 Chapter Summary VDD RD Vout V in1 T1 T2 I SS Vin2 RD 525 Figure 10. 10. 2007 at 13:42 525 (1) Sec. vY =vin . Assume perfect symmetry b = 0 for simp icity.Gm Rout in some cases. 10. If the vo tage gain is de ned as vX . ca cu ate vY in terms of vin . VDD M3 Vout V in1 M1 M2 I SS Vin2 M4 Vb M5 V in1 M3 Vout M1 M2 I SS I SS (a) (b) (c) VDD M4 M6 Vin2 V in1 Vb M3 R1 Vout M1 M2 R2 VDD M4 Vin2 Figure 10. RD X Vout M1 V in P I SS M2 Vb RD Y ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . ca cu ate vX in terms of vin .76 53. Ca cu ate the differentia vo tage gain of the circuits depicted in Fig. Assume perfect symmetry and 0. (c) Add the res u ts obtained in (a) and (b) with proper po arities.74 Figure 10. 10.75. 10.

78. Ca cu ate the vo tage gain. If Q1 Q4 are identica and = 100. Due to a manufacturing error. VCC Vout Q3 Vb V in1 Q1 RP Q2 Vin2 Q4 I EE Figure 10. what is the minimum required Ear y vo tage? 55. 2006] June 30.78 56.37(a) must achieve a vo tage gain o f 4000.79 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ . RP .77 54. a parasitic resistance. VCC Vout Q3 Vb V in1 RP Q1 RP Q2 Q4 Vb Vin2 I EE Figure 10.c s v. 2007 at 13:42 526 (1) 526 Chap. 10.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Repeat Prob em 55 for the circuit shown in Fig. 10 Differentia Amp i ers VDD M3 Vout V in1 M1 R1 R2 R SS M2 Vin2 V in1 M4 Vb M3 M4 Vout M1 R SS M2 VDD RS M3 M4 Vout V in1 M1 R SS M2 VDD RS Vb Vin2 Vin2 (a) (b) (c) Figure 10.79. has appear ed in the circuit of Fig. 10. 10. The cascode differentia pair of Fig.

40(a) mus t provide a vo tage gain of 300. 10. Assume n = 2 p = 100 and VA.Gm Rout .) VCC Vout Q3 Vb V in1 Q1 Q2 Vin2 Q4 I EE Figure 10. Assuming 0. 60.84. 10. ( Hint: . The te escopic cascode of Fig.n = 2VA. Determine the vo tage gain of the circuit depicted in Fig.83.81 59. 61. 10.80.81. 2007 at 13:42 527 (1) Sec. 10. 63.82. 10. A student has mistaken y used pnp cascode transistors in a differentia pair as i ustrated in Fig. The MOS cascode of Fig. Ca cu ate the vo tage gain of this to po ogy. If W=L = 20=0:18 for M1 M4 and n Cox = 100 A=V2 .1 .41(a) is designed for a vo tage gain of 200 with a 2 2 tai current of 1 mA. the studen t makes the modi cation shown in Fig. Is this to po ogy considered a te escopic cascode? 62. If Q1 Q4 are identica and so are Q5 Q8 .Gm Rout . determine the required tai current. p Cox = 50 A=V . n = 0:1 V.c s v. The MOS te escopi c cascode of Fig. and . p = 0:2 V 64. determi ne the minimum a owab e Ear y vo tage.p . 2006] June 30. Assume = 0:1 V. If n Cox = 100 A=V . (Hint: Av = . 10.81 suffers from a ow gain. 10.80 58. Rea izing that the circuit of Fig.38 is to operate as an op amp havi ng an open oop gain of 800.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.7 Chapter Summary 527 57.1 . 10.) VCC Av = Vout Q3 Vb V in1 Q1 RS Q2 Vin2 Q4 Figure 10. A student adventurous y modi es a CMOS te escopic c ascode as shown in Fig. where the PMOS cascode transistors are rep aced w ith NMOS devices. 10. Ca cu ate the vo tage gain of the circuit. deter mine W=L1 = = W=L8 . Ca cu ate the vo tage gain of the degenerated pair depicted in Fig.1 . compute ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤¡ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ . 10.

each having a degenera tion resistor equa to 2REE . 10 VCC Differentia Amp i ers Q3 Vb Vout V in1 Q1 Q4 Q2 Vin2 I EE Figure 10.c s v. Now draw a vertica ine of symmetry through the c ircuit and decompose it to two common mode ha f circuits. 2007 at 13:42 528 (1) 528 Chap. 10. 2006] June 30.85 must exhibit a common mode gain of ess than 0.175) sti ho ds. 10. Compute the common mode gain of the MOS differentia pair shown in Fig. 66.219) ¤ ¤ ¡ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¡ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . (Hint: the impedance seen ooking into the sour ce of M5 or M6 is not equa to 1=gmjjrO . prove that RC IC 0:02VA + VT : (10.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. Assuming VA = 1 for Q1 and Q2 but VA 1 for Q3 .83 the vo tage gain of the circuit. Prove RD ISS ACM = 2 . + VGS . VTH eq: (10.218) 67.4 3(a) and rep ace REE with two para e resistors equa to 2REE p aces on the two sides of the current source. The bipo ar differentia pair depicted in Fig. Consider the circuit of Fig. Assume = 0 for M1 and M2 but 6= 0 for M3 .01. Prove that Eq.) 65. (10.8 6. 10.82 VCC V b3 Q7 V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 Q6 Vout Q4 Q8 I EE Figure 10.

84 VCC RC v out1 Q1 v CM Vb Q3 I EE Q2 RC v out2 Figure 10. VTH eq: denotes the equi ibrium overdrive of M1 and M2 . and use the re ationship Av = . 71. 10. Neg ect channe ength modu ation. For simp icity. where VGS . Determine the sma signa g ain vout =i1 in the circuit of Fig.90 if W=L3 = N W=L4 .88. 70.89 and compare the resu ts. Repeat Prob em 68 for the circuits shown i n Fig.85 VDD RD X V in1 Vb M1 M2 M3 RD Y Vin2 Figure 10.Gm Rout . 10. 2006] June 30. 2007 at 13:42 529 (1) Sec. gm rO 1. neg ect channe ength mo du ation in M1 and M2 but not in other transistors.87. Assume 0.BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi.c s v. 10.86 68. ¤¡¤ ¤ ¤ ¤ ¡¤¤ ¤¡¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¡ ¤ ¤ ¤ ¡ ¤ ¤ ¤ . Ca cu ate the common mode gain of the circuit depicted in Fig. 10. 10. Compute the common mode rejection ratio of the stages i ustrated in Fig.7 Chapter Summary VDD M7 V b3 V b2 M5 M3 V b1 V in1 M1 M2 I SS M6 Vout M4 Vin2 M8 529 Figure 10. 69.

calculate Vout efore and aft er the change if (a) W=L3 = W=L4 . Assume M1 and M2 are ident ical and so are M3 and M4 . In the circuit shown in Fig. 2007 at 13:42 530 (1) 530 Chap. where the inputs are tied to a common-mode level. 10 VDD V b1 M3 V in1 V b2 Vout M1 M2 M5 Vin2 M4 Differentia Amp i ers Figure 10.88 V 1 M3 V 2 V 3 M3 M4 ( ) (a) Figure 10.89 72. 2006] June 30.91.87 VDD V b1 M3 V in1 V b2 V b3 Vout M1 M2 M5 M6 Vin2 V in1 V b2 M4 V b3 V b1 M3 Vou t M1 M2 M7 (b) VDD M5 M6 M4 Vin2 (a) Figure 10. calculate the voltage at node N . Consider the circuit of Fig. (a) Neglecting channel-length modulation. ( ) W=L3 = 2W=L4 73. I1 changes from I0 to I0 +I and I2 from I 0 to I0 .BR Wi ey/Razavi/Fundamenta s of Microe ectronics [Razavi. determine the voltage at node Y . 10. 92. ( ) Invoking symmetry. I .c s v. Neglecting channel-length modulation. 10. £ £ £ ¢ £ ¢ ¢¢ V R + ∆R v out2 Vin2 ¢ ¢ VDD RD v out1 V in1 M1 P M2 R D + ∆R ¤ ¤ ¤ ¤ ¤ ¤ £ £ v out2 Vin2 R v out1 V in1 M1 P M2 £ .

2006] June 30. Re peat the analysis in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. £ ¢¢ £ £ £ £ ¢ ¢¢ V ¢¢ V ¢¢ ¢¢ M3 M4 Vout I1 I2 RL M4 . 10. what is the required Early voltage for the pnp transistors? 76. We wish to design the stage shown in Fig. 77. 10.90 Figure 10. 10.n = 5 V. 10.93 75. Neglecting channel-length modulation.54. 2007 at 13:42 531 (1) Sec. etermine the output impedance of the circuit shown in Fig. compute the small-signal g ains vout =i1 and vout =i2 in Fig.cls v.7 Chapter Summary V M3 M4 Vout I1 RL 531 Figure 10. I f VA.93. Assume gm rO 1.94 for a voltage gain of 100. 10.91 M3 N M1 v CM I SS P Y M2 Figure 10.92 (c) What happens to the results o tained in (a) and ( ) if V changes y a smal l amount V ? 74. V M3 M4 Vout I1 I2 RL Figure 10.56 ut y constructing a Norton equivalent for the input differential pair.

Assume ¢ £ £ £ ¢ £ £ £ £ £ ¢ £ £ ¢ £ £ £ ¢ ¢ . Using the result o tained in Pro lem 77 and the relationship Av = . Moreover. esign the ipolar d ifferential pair of Fig.94 78. 2007 at 13:42 532 (1) 532 VCC Q3 Q4 Chap. The differential pair depicted in Fig. esign the circuit of Fig.95 mW. 80.cls v. 10. esign the circuit for maximum voltage gain and a power udget of 3 mW. 10 ifferential Ampli ers Vout V in1 Q1 Q2 Vin2 I EE Figure 10.2 V without driving the transistors into saturation.6(a) for a voltage gain of 10 and a power udget of 2 mW. 10. compute the voltage gain of the stage. 1 0.96 for a gain of 50 and a power udget of 1 mW. (Hint: a 10 change in IC leads to a 10 change in gm . esign Pro lems 79. des ign the circuit. the gain of the circuit must change y less than 2 if the collector current of either transistor changes y 10. 83.96 VA. 81.) 82. 10. Assume VCC V Q3 V in1 Q1 Vout Q2 Vin2 Q4 I EE Figure 10. Assuming VCC = 2:5 V and VA = 1.6(a) must operate with an input common-mode level of 1.95 must provide a gain of 5 and a power udget of 4 VCC RC Vout V in1 Q1 RE Q2 Vin2 RC I EE I EE Figure 10. The ipolar differential pair of Fig. esign the circuit of Fig. Assume VCC = 2:5 V.97 for a gain of 100 and a power udget of 1 m W. Assume VCC = 2:5 V and VA = 1.n = 6 V and VCC = 2:5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.Gm Rout . 2006] June 30.

87. VCC = 2:5 V.1 . design 2 the circuit. Assume = 0. 10. 90. p = 0:2 V. Assume R = 500 .29 for a voltage gain of 5 and a power dissipation of 1 mW if the equili rium overdrive must e at least 150 mV. 10. If V = 1. = 100. and the power udget is 1 mW. 85. 10. Also. n Cox = 100 A=V . R1 = R2 . and VCC = 2:5 V. VA. Assume n = 0:1 V. Assume = 0. The differential pair depicted in Fig. VA.97 84.n = 0:5 V. 2006] June 30. esign the MOS differential pair of Fig.29 for Vin. 10. 88. n Cox = 100 A=V . n Cox = 100 A=V2 .29 for an equili rium overdrive voltage of 100 mV and a power udget of 2 mW.1 . esign the telescopic cascode of Fig.cls v.37(a) for a vo ltage gain of 4000.38(a) for a voltage gain of 2000. Also. As suming the same V V 1 M3 V in1 V 2 Vout M1 M2 M5 Vin2 M4 Figure 10.p = 5 V.n = 5 V. n Cox = 100 A=V . p Cox = 50 A=V . Select the value of R to place th e transistor at the edge of 2 triode region for an input common-mode level of 1 V. esign the MOS differential pair of Fig. and V = 1:8 V . 10. Also. esign the telescopic cascode of Fig. 89. VCC = 2:5 V.41(a ) for a voltage gain of 600 and a power udget of 4 mW.7 Chapter Summary VCC Q3 R1 Vout V in1 Q1 P I EE Q2 Vin2 R2 Q4 533 Figure 10. VTH. 10.n = 10 V. and V = 1:8 V. and V = 1:8 V. p = 50. n Cox = 100 A=V2 .98 (equili rium) overdrive for all of the transistors and a power dissipation of 2 mW. and the power udget is 2 mW. p Co x = 2 100 A=V .98 must provide a gain of 40. Assume Q1 -Q4 a re identical and so are Q5 -Q8 . 2007 at 13:42 533 (1) Sec. Assume an (equili rium) overdrive of 100 mV for the NMOS devices and 150 mV 2 2 for the PMOS devices. esign the circuit of Fig. and V = 1:8 V. What is the volt age gain of the resulting design? 86. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and ¢¢ £ £ ¢ ¢ £ ¢ £ ¢¢ £ ¢¢ £ ¢ ¢ ¢ £ ¢¢ £ £ £ £ £ ¢ ¢¢ ¢¢ ¢ .8 V. Assume Q1 -Q4 are identical and determine the required Early voltage. = 0.max = 0:3 V and a power udget of 3 mW. 1 0. esign the MOS differe ntial pair of Fig. n = 100. VA.

VTH.2 V. ¢ £ ¢ £ ¢¢ £ ¢ ¢¢ £ ¢ £ ¢ £ £ £ £ £ £ ¢ ¢¢ £ £ ¢ £ .p . The differential ampli er depicted in Fig. V 1 M3 Figure 10.n = 2VA.5 V V Vout V in1 Q1 Q2 Vin2 Q4 1 mA I EE Figure 10.npn = 5 V.0:4 V. Assume W=L = 10 m=0:18 m for M1 -M6 . 10. The input CM level is equal to 1. As sume a power V R v out1 V in1 M1 P M2 R + ∆R v out2 Vin2 n = 0:1 V. Consider the differential ampli er shown in Fig. and neglecting channel -length modulation in M1 and M2 . 10 ifferential Ampli ers 91.p = . use the MOS device models given in the Appen dix I. 10.99 must achieve a CMRR of 60 dB (= 100).n = 0:5 V. npn = 100.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. n Cox = 100 A=V2 . Also. n C ox = 2p Cox = 100 A=V . and R=R = 2. determine the required value of p . 94.5 V. pnp = 50. Assume M1 -M4 are identical an d so are M5 -M8 . a nominal differential voltage gain of 5. compute the minimum required for M3 .2 = 10=0:18. The differential pair of Fig. ( ) eterm ine the small-signal differential gain of the circuit.16 A. VA.) (c) What happens to the output CM level and the gain if V varies y 10 mV? 95. VA.1 .16 A. VTH. IS. SPICE Pro lems In the following pro lems. 93. 2006] June 30.npn = 5 10. esign the differen tial pair of Fig.48 for a voltage gain of 200 and a power udget of 3 mW wit h a 2.pnp = 8 10. 10.cls v.2 V. 92.100 (a) Adjust the value of V so as to set the output CM level to 1.1 . V = 1:8 V. VCC = 2. Assume M1 ope rates at the edge of 2saturation if the input common-mode level is 1 V.1 01 employs two current mirrors to esta lish the ias for the input and load devi ces.54 for a voltage gain of 20 and a power udget of 1 mW with V = 1:8 V. assume IS. (Hint: to provide differe ntial inputs. 10.100. Assume VA. esign the circuit of Fig. For ipolar transistors.pnp = 3:5 V. 10. 2007 at 13:42 534 (1) 534 Chap. Assume W =L1. n = 0:5p = 0:1 V.5-V supply.99 udget of 2 mW. use an independent voltage source for one side and a voltage-depen dent voltage source for the other. where the input CM level is equal to 1.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume an in ut CM level of 1 V and Vb = 1:5 V. (b) Select the value of R1 (= R2 ) such that these resistors reduce the differential gain by no more than 20.cls v.102. (Assume L7 = 0:18 m.7 Chapter Summary V = 1. 10. VDD = 1. VCC = 2. W=L = 10 m=0:18 m for all of the transistors.102 (a) Select the in ut CM level to lace Q1 and Q2 at the edge of saturation.103.101 (a) Select W=L7 so as to set the out ut CM level to 1. In the differential am li er of Fig. I1 so that the out ut CM level laces M3 and M4 at the edge of ¡ ¢¢ . 97.) (b ) Determine the small signal differential gain of the circuit. 96.8 V M7 1 kΩ 535 M3 V in1 M4 Vout M1 M2 M5 Vin2 M6 Figure 10. Assume a small dc dro across R1 and R2 . 10.5 V.5 V Q3 R1 Vout V in1 Q1 Q2 Vin2 R2 Q4 1 mA I EE Figure 10. (c) Plot the diff erential in ut/out ut characteristic. Consider the circuit illustrated in Fi g. 10. 2006] June 30. 2007 at 13:42 535 (1) Sec.8 V M7 M9 I1 Vb V in1 M1 1 mA M8 Vout M4 M2 I SS Vin2 M3 Figure 10.103 (a) Select the value of saturation.

vin2 .2 V.5 mA M1 M4. M3 X V in1 M1 0. 10 Differential Am li ers (b) Determine the small signal differential gain. (c) Determine th e change in the out ut dc level if W4 changes by 5. 10. 2007 at 13:42 536 (1) 536 Cha . In the circuit of Fig. Razavi. 2006] June 30. 98. B. Assume an in ut CM VDD = 1. ¡ ¡ ¡ ¡ .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. W=L = 10 m=0:18 m for level of 1. 104.104 (a) Determine the out ut dc level and ex lain why it is equal to VX / (b) Determ ine the small signal gains vout =vin1 . 2001.8 V M4 Vout M2 I SS Vin2 Figure 10.cls v. References 1. Design of Analog CMOS Integrated Circuits McGraw Hill. vin2 and vX =vin1 .

11.1.1 Ex lain why eo le’s voice over the hone sounds different from their voice in fac e to face conversation. 2006] June 30. Exam le 11. From radar and television systems in the 1940s to gigahertz micro rocessors today. we must ask: why is frequency res onse im ortant? The following exam le s illustrate the issue. 11. the circuit may exhibit a high gain at low frequencies but a “roll off” as the frequency increases. We assume bi olar transistors rema in in the active mode and MOSFETs in the saturation region.1(b) to re resent the circuit’s behavior at all frequencies of interest. As exem li ed by Fig. the idea is to a ly a sinusoid at the in ut of the circuit and observe the out ut while the in ut frequency is varied. a critical task in the study of stability and frequency com ensation (12). the demand for ushing circuits to higher frequencies has requ ired a solid understanding of their s eed limitations.cls v. identifying to ol ogies that better lend themselves to high frequency o eration. Fundamental Conce ts Bode’s Rules Association of Poles with Nodes Miller’s Theorem H igh−Frequency Models of Transistors Bi olar Model MOS Model Transit Frequency Freq uency Res onse of Circuits CE/CS Stages CB/CG Stages Followers Cascode Stage Dif ferential Pair 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we study the effects that limit the s eed of transistors and circuits. The outline is shown below. Before investigating the cause of this r oll off.1(a). In this cha ter.1 General Considerations What do we mean by “frequency res onse?” Illustrated i n Fig.1 Fundamental Conce ts 11. We lot the magnitude of the gain as in Fig. 2007 at 13:42 537 (1) 11 Frequency Res onse The need for o erating circuits at increasingly higher s eeds has always challen ged designers. 11. We may loosely call f1 the useful bandwidth of the circuit. 537 ¡ ¡ ¡ ¡ ¡ .1 (a). We also develo s kills for deriving transfer functions of circuits.

2006] June 30. (b) gain roll off with fr equency. 11. On the other hand. Solution Human voice contains frequency com onents from 20 Hz to 20 kHz [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Whose voice does the hone system alter more. circuits 20 Hz (a) 20 kHz f 400 Hz (b) 3. exhibiting the frequency res onse shown in Fig. 11. 2007 at 13:42 538 (1) 538 Cha . 11 Frequency Res onse Av Roll−Off f1 (a) (b) f Figure 11. the circuits are designed to cover the entire frequency range. Unfortunately. when you s eak and listen to your own voice simultane ¡ ¡ . on the other hand.1 (a) Conce tual test of frequency res onse.5 kHz f Figure 11. eac h erson’s voice is altered.5 kHz.cls v.2(b). T hus. your voice ro agates through the air and reaches the audio re corder. Since the hone su resses frequencies above 3. it sounds somewhat different from t he way you hear it directly when you s eak.2 rocessing the voice must accommodate this frequency range. In high quality audio systems. men’s or women’s? Exam le 11. Ex lain why? Solution During recording.2(a)]. the hone system suffers from a limited bandwidth.2 When you record your voice and listen to it.

your skull asses some frequencies more easily than others). Exercise Ex lain what ha ens to your voice when you have a cold? . your voice ro agates not only through the air but also from your mouth t hrough your skull to your ear. Since the frequency res onse of the ath through your skull is different from that through the air (i.. the way you hear your own voice is differe nt from the way other eo le hear your voice.e.ously.

4(b). At high frequencies.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. the “shar ” edges on a dis lay become “soft. For exam le. 11. CL “steals” some of the signal current and shunts it to ground. the im edance of C1 falls and the voltage divider consisting of R1 and C1 attenuates Vin to a greate r extent. let us consider the low ass lter de icted in Fig.3 Exercise What ha ens if the dis lay is scanned from to to bottom? What causes the gain roll off in Fig..1? As a sim le exam le. the gra hics card delivering the video signal to the dis lay of a com uter must rovide at least 5 MHz of bandwidth. C1 is nearly o e n and the current through R1 Vout R1 V in C1 Vout f V in 1. As a more interesting exam le. nearly zero. leading to a lower voltage s wing at the out ut. Vout = Vin . ¡ ¡ ¡ ¡ ¡ ¡ ¡ . In fact. and (b) its frequency res onse.) (a) (b) Figure 11. CL . This is because the circuit driving the dis lay is not fast enough to abru tly change the contrast from. 11.4(a). on the other hand. 2007 at 13:42 539 (1) Sec. 11. from the small signal equivalent Exam le 11.” yielding a fuzzy icture.4 (a) Sim le low ass lter.3(a) and (b) illustrate this effect for a high bandwidth and low bandwidth driver. the signal current roduced by M1 refers to ow through RD because the im eda nce of CL . 11.0 Figure 11. The circuit therefore exhibits the behavior shown in Fig. At low frequencies. As the frequency increases. a ears at the out ut. 11. Figures 11.3 Video signals ty ically occu y a bandwidth of about 5 MHz.1 Fundamental Conce ts 539 Solution With insuf cient bandwidth. consider the common source stage illustrated in Fig. 1=CL s. remains high. At low frequenci es.5(a). Ex lain what ha ens if the bandwidth of a video sy stem is insuf cient. com lete white to com lete black from o ne ixel to the next. where a load ca acitance. res ectively. thus. e.g.cls v. (The dis lay is scanned from l eft to right.

the e am litude of arallel im edance falls and so does th ¡ . 11 Frequency Res onse Vout g V in m RD CL (a) (b) Figure 11. as the frequency increases.cls v. such signals can be viewed as a summation of many sinusoids with different frequencies (and hases).5 (a) CS stage with load ca acitance. After all. an am li er may sense a voice or video signal that bears no rese mblance to sinusoids. res onses such as that in Fig. 1 + !s 1 + !s z1 That is.gmVin RD jj C1 s : L (11. 2006] June 30. Fortunately.1 we note that RD and CL are in arallel and hence: Vout = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus.1) The reader may wonder why we use sinusoidal in uts in our study of frequency res onse. 2007 at 13:42 540 (1) 540 VDD RD Vout V in M1 CL V in Cha . circuit of Fig.5(b).1. (b) small signal model o f the circuit.5(b) rove useful so long as the circuit remains linear and henc e su er osition can be a lied. 11. 11. 11.2 Relationshi Between Transfer Function an d Frequency Res onse We know from basic circuit theory that the transfer functio n of a circuit can be written as Vout .2 The voltage gain therefore dro s at high frequencies.

H z2s = A0 .

s s . 1+ ! 1+ ! 1 2 .

.

2) ex ressed as where A0 denotes the low frequency gain because H s ! A0 as s ! 0. For exam le. th en the out ut can be yt = AjH j!j cos !t + 6 H j! .5(a). 1 Channel length modulation is neglected here.3) where H j! is obtained by making the substitution s = j! . The frequencies !zj and ! j re resent the zeros and oles of the transfer function. If the in ut to the circuit is a sinusoid of the form xt = A cos2ft = A cos !t.(11. Called the “magnitude” and the “ hase. we are rimarily concerned with the former.4 Determine the transfer function and frequency res onse of the CS stage shown in Fig.” jH j! j and 6 H j! res ectively reveal the frequency res onse of the circ uit. res ectivel y. Note that f (i n Hz) and ! (in radians er second) are related by a factor of 2 . In this cha ter. 11. 2 We use u er case letters for f requency domain quantities (La lace transforms) even though they denote small signal values. ¡ ¡ ¡ . (11. w e may write ! = 5 1010 rad/s = 27:96 GHz: Exam le 11.

7) 2 3 dB. Vin L . 11. 2007 at 13:42 541 (1) Sec. 11. (11.6) 2 2 Vin RD CL !2 + 1 2 2 As ex ected.5 Consider the common-emitter stage sho n in Fig. we have H s = Vout s = . Since 20 log 11.1 Fundamental Conce ts 541 Solution From Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11. the .4) (11.5(a).gm RD jj C1 s (11. and the po er consumption by IC VCC .1).gmRD : = R C s+1 D L (11. Ass ume VA = 1.3 dB bandwidth of the circuit is equal to 1=RD CL Vout V in −3−dB Bandwidth −3−dB Rolloff 1 R D CL ω Figure 11. the gain begins at gm RD at low frequencies. Example 11. For the highest performance. In a manner similar to the CS topology of Fig.cls v. Derive a relationship bet een the gain.3-dB band idth. we re lace s = j! and com ute the magnitude of the trans fer function:3 Vout = gm RD : (11. we say the .5) For a sinusoidal in ut. rolling off as RD CL ! 2 becomes com arable with unit y. and the po er consumption of the circuit. 2006] June 30.6 Exercise Derive the above results if 6= 0. At ! = 1=RD CL . ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¡ Vout = gm RD : Vin 2 . e ish to maximize both th (Fig. the band idt h is given by 1=RC CL .6).7. the lo -frequency gain by gm RC = IC =VT RC .

e gain and the band idth (and hence the 3 The magnitude of the complex number Solution p a + jb is equal to a2 + b2 . ¥ .

8) (11. Example 11. 2007 at 13:42 542 (1) 542 Chap. 11 Frequency Response VCC RC Vout V in Q1 CL Figure 11.4 (b) VCC but at the cost of limiting the voltage s ings. ite e vie the circuit as a voltage divider and r ¥ ¥ ¥ ¥ ¥ ¥ ¥ VCC 1 = V 1V C : ¥ ¥ . the overall performance can be improved by lo ering (a) the temperature.11) The frequency response is determined by replacing s ith j! and computing the ma gnitude: ¥ ¥ ¥ ¥ Solution To obtain the transfer function.9) becomes more complex for CS stages (Problem 15). or (c) the load capacita nce.6 Explain the relationship bet een the frequency response and step response of the simple lo pass lter sho n in Fig.7 product of the t o) and minimize the po er dissipation.cls v. In practice.10) = R C 1s + 1 : 1 1 1 (11. the load capacitance receives the greatest attention. 11. Equation (11.4(a). 2006] June 30.9) Thus. Exercise Derive the above results if VA 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. H s = Vout s = 1 C1 s Vin C1 s + R1 1 (11. We therefore de ne a “ gure of merit” as IC 1 Gain Band idth = VT RC RC CL Po er Consumption IC T CC L (11.

by immersing the circuit in liquid nitrogen (T around! = 77 K).12) 4 For example. but requiring that the user carry a tank .jH s = j!j = p R C ! +1 2 2 2 1 1 : (11.

H 1. Exercise At hat frequency does jH j fall by a factor of t o? 11.7 Solution Equation (11.1. the slope of jH j! j decreases by 20 dB/dec. Figure 11.13) The relationship bet een (11. The circuit’s response to a step of the fo rm V0 ut is given by t Vout t = V0 1 .5 Constru ct the Bode plot of jH j! j for the CS stage depicted in Fig.3(b): since the signal cannot rapidly jump from lo ( hite) to high (black). the ba nd idth drops and the step response becomes slo er.13) is that.5(a). This observation explains the effect seen in Fig. e often utilize Bode’s rules (approximations) to construct jH j! j rapidly. For this reason.) As ! passes each zero frequency. creating “fuzzy” edges.5) indicates a pole frequency of j!p1 j = R 1C : ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ .12) and (11. it spends some time at intermediate levels (shades of gray). Example 11. 11.3 Bode’s Rules The task of obtaining jH j! j from H s and plotting the result is some hat tedious.3-dB band idth is equal to 1=R1 C1 . Bode’s rules for jH j! j are as follo s: As ! passes eac h pole frequency. 11. 2006] June 30. exp R.cls v. revealing that a narro band idth results in a sluggish time response.8 11. (A slope of 20 dB/d ec simply means a tenfold change in H for a tenfold increase in frequency.1 Fundamental Concepts 543 The . 2007 at 13:42 543 (1) Sec.8 plots this behav ior.C ut: 1 1 (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.0 R 1C 1 R 1C 1 Vout f (a) (b) t Figure 11. as R1 C1 increases. the slope of jH j! j increases by 20 dB/dec.

14) The magnitude thus begins at gm RD at lo frequencies and remains at up to ! = j! p1 j. ¥ . At this point. In contrast 5 Complex poles may result in sharp peaks in the frequency response. an effect n eglected in Bode’s approximation.9 illu strates the result. Figure 11.D L (11. the slope changes from zero to .20 dB/dec.

11 Frequency Response to Fig.4 Association of Poles ith Nodes The poles of a circuit’s transfer function play a central role in the frequency response.cls v.5) reveals t hat the pole frequency is given by the inverse of the product of the total resis tance seen bet een the output node and ground and the total capacitance seen bet een the output node and ground.1 to the transfer function. ¥ ¥ ¥ ¥ ¥ ¥ ¥ . 2007 at 13:42 544 (1) 544 Chap. 11. Setting Vin to zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10 .6). Bode’s rule provides a good approximation. e recognize that the gate of M1 sees a resistance of RS an d a capacitance of Cin to ground.1 . RD = 2 k . Determine the poles of the circuit sho n in Fig. Equation (11.” The CS topology studied in Example 11. this observation c an be generalized as follo s: if node j in the signal path exhibits a small-sign al resistance of Rj to ground and a capacitance of Cj to ground. V 20log out V in g m RD −2 0 dB e /d c ω p1 Figure 11. Assume = 0 VDD RD RS M1 C in CL Vout Example 11. As evident from Eq. (11. 11.10. 11. Thus. for RD CL ! 2 1. 2006] June 30. the Bode approximation ignores the 3-dB roll-off at the pole fr equency—but 2 2 it greatly simpli es the algebra.4 serves as a good example for identifying poles by inspection.5(b).9 log ω Exercise Construct the Bode plot for gm = 150 . Applicable to many circuits.1.8 V in Figure 11. and CL = 100 fF. The designer must therefore be ab le to identify the poles intuitively so as to determine hich parts of the circu it appear as the “speed bottleneck. then it contrib utes a pole of magnitude Rj Cj .

Solution j!p1 j = R 1 : C S in (11.15) .

Assume = 0. (11. the small-signal resistance seen at the source of yielding a pole at Solution M1 is given by RS jj1=gm. 11.17) Compute the poles of the circuit sho n in Fig. 11. VDD RD Vout RS M1 Vb CL Example 11.1 Fundamental Concepts 545 We may call !p1 the “input pole” to indicate that it arises in the input net ork.gm RD . 2006] June 30. e can readily rite the magnitude of the transfer function as: gm RD Vout = q : Vin 2 2 1 + !2 =!p11 + !2 !p2 (11.18) !p1 = ¥ ¥ Exercise If !p1 = !p2 .16) Since the lo -frequency gain of the circuit is equal to .cls v. the “output pole” is given by j!p2 j = R 1C : D L (11. at hat frequency does the gain drop by 3 dB? ¥ ¥ ¥ ¥ . Si milarly. With Vin = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9 V in C in Figure 11.11 . 2007 at 13:42 545 (1) Sec.11.

The output pole is given by !p2 1: RS jj g1 Cin m = RD CL . Exercise Ho do e choose the value of pole frequency? RD such that the output pole frequency is ten times the input ¥ ¥ .1 .

11 . 11. 11. He then proposed an analysis that led to the theorem.13(b). John Miller had observed that parasitic capacitances app earing bet een the input and output of an ampli er may drastically lo er the input impedance.5 Miller’s Theorem Our above study and the example in Fig.13(b).13(a) must be equal to that injected by Z2 in Fig. 11. 11.13(a) must be equal to that dra n by Z1 in Fig. To determine Z1 and Z2 . Ho ever. ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ . ap1 ZF 2 1 2 V1 V2 Z1 V1 V2 Z2 (a) (b) Figure 11.. VDD RD CF V in RS M1 Vout 11. Miller’s theorem is such a method. (b) equivalent of pears bet een nodes 1 and 2. In the late 1910s.1. Consider the g eneral circuit sho n in Fig. oating impedance. and (2) the current injected to node 2 in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12 Circuit ith oating capacitor.13(b). as originally conceived for another rea son. Miller’s theorem. e make t o observations : (1) the current dra n by ZF from node 1 in Fig. 11. e cannot utilize thi s technique and must rite the circuit’s equations and obtain the transfer functio n. (These requirement ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ Figure 11.cls v. We ish to transform ZF to t o grounded impedances as depicted in Fig. 11.12).12 make it desi rable to obtain a method that “transforms” a oating capacitor to t o grounded capacit ors. an approximation given by “Miller’s Theorem” can simplify the task in some cases. here the oating impedance. ho ever. 11 Frequency Response The reader may onder ho the foregoing technique can be applied if a node is lo aded ith a “ oating” capacitor. a capacitor hose other terminal is also connec ted to a node in the signal path (Fig. In general.13(a). thereby allo ing association of one pole ith each node.e. i. 2007 at 13:42 546 (1) 546 Chap. hile ensuring all of the currents and voltages in the circuit remain unchanged. 11.13 (a) General circuit including a (a) as obtained from Miller’s theorem. 2006] June 30. ZF .

V2 = V1 ZF Z1 V1 . V1 .20) (11.21) ¥ .s guarantee that the circuit does not “feel” the transformation. V2 : ZF Z2 Denoting the voltage gain from node 1 to node 2 by Av .) Thus. e obtain Z1 = ZF V V1 V 1. 2 (11. V2 = .19) (11.

22) suggests that the oatin g impedance is reduced by a factor of 1 .A0 is made. tied bet een the input and output of an inverting ampli er [Fig.FA 1 = 1 + A C s . the results expressed by (11. as if CF is “ampli ed” by a factor of 1 + A0 . a capacitor CF tied bet een the input and output of an inverting ampli er ith a gain of A0 raises the input capacitance by an amount equal to 1+ A0 CF . A v (11.1 Fundamental Concepts 547 Z = 1 .24) Called Miller’s theorem. let us assume ZF is a single capacitor.FA and v (11. We say such a circuit suffers from “Miller multiplication” of the capacitor.25) (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In particular. 0 F v (11. What type of impedance is Z1 ? The 1=s dependence suggests a capacitor of value 1 + A0 CF . 11. 11. Av hen “seen” at node 1. Applying (11. 2V 1 2 ZF : = 1 1.2 2). In other ords.22) V Z2 = ZF V .cls v. CF V in −A 0 Vout −A 0 ∆ V V in CF ( 1 + A 0 ( ¥ ¥ ¥ ¥ ¥ ¥ ¥ . e have Z Z1 = 1 . As an important example of Miller’s theorem. (11. CF ..26) here the substitution Av = .14(a)].24) prove extrem ely useful in analysis and design.22) and (11.23) (11. 2006] June 30. 2007 at 13:42 547 (1) Sec.

Z2 = ZF 1 1.−A 0 Vout CF ( 1 + 1 ( A0 ∆V (a) ( ) Figure 11.27) £ £ The effect of CF at the output can e o tained from (11. ( ) equivalent circuit as o tained from Miller’s theorem.14 (a) Inverting circuit with oating capacitor.24): £ £ £ . A v = (11.

28) which is close to CF s. That is.14(a) goes up y a small amount V .1. the voltage across CF increases y 1 + A0 V . Suppose the input voltage in Fig. Figure 11. The output then goe s down y A0 V .1 if A0 1. 11. requiring th at the input provide a