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Realize the following Logic gates – NOT gate and two input AND, OR, NOR, XOR, XNOR gates respectively using NAND gates only to verify NAND as a universal logic gate. Use a single schematic diagram on the same screen for the above purpose. Realise the following Logic gates – NOT and two input AND, OR, NAND, XOR, XNOR gates respectively using NOR gates only to verify NOR as a universal logic gate. Use a single schematic diagram on the same screen for the above purpose. Verify the following Demorgan’s theorem by using logic gates: Using a single schematic diagram on the same screen for both the theorem. a) A + B = A.B

2.

3.

b) A.B = A + B 4. Realise the following logical functions using combination of Logic gates: i) Without minimising the logical function and ii) By minimising the logical function. Comment on the difference between the two approaches. b) f (A, B, C) = A. B.C + B. C + A . C . c) f (A, B, C, D) = A. B. C. D + B . C + B. C. 5. Design a five-bit EVEN/ODD parity generator circuit using the following gates: a) NAND gates only. b) NOR gates only. c) Combination of NOT, OR and AND gates. 6. How would you use the following? a) A four input OR and NOR gate using two input OR and NOR gates respectively. b) A four input AND and NAND gate using two input AND and NAND gates respectively. c) How three input AND gate can be used as inhibit gate? 7. How would you realise NOT gate, and two input AND gate and NAND gate using Diode-Resistor and Transistor logic? 8. Minimise and synthesize the following logical function using NAND gates only: F (A, B, C, D, E, F) = ∑m (0, 2, 5, 7, 9, 13, 16, 19, 21, 26, 31, 35, 37, 39, 45, 51, 58, 60, 61, 63). (For this use Multisim-2001 simulation Package) 9. Design a Full adder circuit using Half adder circuits only. (For this use Electronics Work Bench simulation Package) 10. Design a 4-bit 9’S complement circuit using a) SSI gates and b) Decoder and any logic gates required. 11. Analyse the following circuit of Fig (a) using Multisim-2001, hence determine the truth table of the following combinational circuit i.e. express Y as a function of A, B, C and D.

U1A

A B

1 2 7400N U2A 1 2 7408N

3 1 2

U3A 3

Y

C D

7432N 3

Fig (a)

12. How would you realise a 16:1 multiplexer using lower order multiplexers only? 13. Using circuitmaker design a 5-bit majority and minority function circuit respectively using decoder and any other gates required. 14. Using circuitmaker design a) a 4-bit Binary to Gray and b) a 4-bit Gray to Binary converter circuits. 15. Design and simulate a 4:1 Multiplexer using NAND gates only. 16. Design and simulate a 2 to 4 line decoder using NAND gates only. -1-

How would you realise a counter of modulus 5. Find A + B and A – B using 4bit Adder/Subtractor circuit a) in 1’s complement system. 6. c) Synchronous decade up counter using J-K flip-flops whose initial count is 0 without preventing lockout. b) Synchronous decade up counter using J-K flip-flops whose initial count is 0 by preventing lockout. 31. Design the following counters: a) Asynchronous decade up counter using J-K flip-flops whose initial count is 0 by preventing lockout. b) in 2’s complement system and c) Sign and Magnitude binary system respectively. Design a 4-bit bi-directional shift register using several D flip-flops and logic gates. by using a) D flip-flops and logic gates and b) by using multiplexer. 29. 28. d) 16-bit EVEN/ODD parity checker circuit. 7. using 74160 chip. Design a combinational circuit using decoder and any logic gates required which will perform Full adder operation among three inputs A. How would you modify the clock circuit of a positive edge triggered flip-flop to make it negative edge triggered? 27. B. 20. D) = ∑m (0. Prevent lockout in the design. 32. a) Design a single digit Decimal adder Circuit using 4-bit parallel adder IC 7483 and logic gates. 12. 38. Design a synchronous counter of modulus 5 having the following sequence: 1⇒2⇒3⇒5⇒7⇒1 i) Using J-K Flip Flops. Design a circuit to display any multiple digit decimal number from 0 to 9999 using suitable decoder driver IC’s and seven segment display devices. 21. Display the timing diagram of the counter using a logic scope of the circuitmaker simulation package. B. a) Design a counter of modulus 6 having the following sequence: 0⇒1⇒2⇒3⇒4⇒5⇒0. 18. ii) Using D Flip-Flops. 15). How would you realise counters of modulus 3. 10. 7 and 10 respectively using the asynchronous counter chip 7490? 34. D) =∑m (4. F2 (A. How would you realise a counter of modulus 5. C. For A = (0100)2 and B = (0101)2 and ii) For A = (0010)2 and B = (0101)2. 9. Design a Priority Encoder with 5 inputs and 3 outputs i) using SSI gates: ii) using Decoder and any other gates. Design an 8-bit digital magnitude comparator by cascading two 4-bit digital magnitude comparator 7485. Design the following using 8-bit Parity Generator/Checker IC 74280 IC: a) 8 bit EVEN/ODD parity checker. Design an 8-bit serial-in-serial-out (right) shift register using D flip-flops. b) 9-bit EVEN/ODD parity generator circuit. 33. 5. 24.17. a) How would you cascade two asynchronous counter IC 7490 to realize counter of modulus 100? b) How would you cascade two asynchronous counter IC 7493 to realize counter of modulus 256? 39. 23. B. Design the following multiple output functions using decoder and any logic gates required: F1 (A. Design a Normal Encoder with 16 active high inputs and 4 active high outputs using SSI gates. -2- . using J-K Flip Flops. b) How would you modify the circuit of fig (a) to design/realise two-digit decimal adder circuit? 26. 10 and 12 respectively using the asynchronous counter chip 7493? 35. c) 10-bit EVEN/ODD parity generator circuit. 8. 30. Design an asynchronous counter of modulus 6 having the following sequence: 0⇒1⇒2⇒3⇒4⇒5⇒0⇒1⇒2⇒3⇒4⇒5. Design a Mod-8 ripple/asynchronous counter using J-K flip-flops. B and C when the control input M=1. Design a synchronous counter using D flip-flops having the sequence: 1⇒2⇒3⇒5⇒7⇒6⇒1⇒2⇒3⇒5⇒7⇒6 — by preventing lockout. D) = ∑m (1. C. 14) and F3 (A. 7. 14) 22. 41. 19. Prevent lockout in the design. 36. counter etc. B and C when the control input M=0 and the same circuit will perform Full subtractor operation among the three inputs A. b) Design a counter of modulus 6 having the following sequence: 0⇒1⇒2⇒3⇒4⇒5⇒0. using 74161 chip. Design a sequence generator which generates a prescribed sequence 11011. 5. C. 25. 53 and 83 using synchronous counter chip(s) 74160? 37. 40. Design a synchronous 3-bit up/down counter of modulus 8 using J-K Flip Flops. Design a 3-bit synchronous UP Gray Code counter using J-K Flip-Flops.

B. How would you cascade two 4-bit Universal shift register IC 74194 to realise all 8-bit functions of shift registers? 47. 29. 27. 44. minutes (1 to 59) and second (1 to 59). Design or realize the following flip-flops using NAND gates only: a) J-K flip-flop and b) D flip-flop. an icon on the main menu showing a person running for circuit maker or by CLICKING 1 in Electronics Work Bench or Multisim). C. 31). and the day of arrival using the following convention. 16. 16. Design a 12 hours digital clock using Circuitmaker by using several counters. c) Design an 8-bit ring counter using data selector of circuitmaker. Now simulate the schematics by using a mouse click on the appropriate GUI (i. 3 on your first day in this laboratory. which will display any single digit decimal number from 0 to 9 on a common anode seven-segment display device. using D flip-flops without preventing lockout. How would you use a 555 timer IC to generate a) Monostable multivibrator waveform b) Unsymmetrical square wave? and c) Symmetrical square wave? (For this use Electronics Work Bench simulation Package). 18. How would you use a 25×8 bit PROM chip to realise the following multiple output functions? F1 (A. b) Design a 1 to 4 line de-multiplexer using NAND gates only. E) = ∑M (0. 18 19. 11. a) Use a D/A converter device to produce analog voltage for different digital inputs. a) Design a 2-bit Parallel type/Simultaneous type /Flash type Analog to Digital converter using comparators and logic gates. 4. -3- . 23. 48. 6. c) Synchronous counter using D flip-flops by preventing lockout which will produce the following bi-quinary sequence: 0⇒2⇒4⇒6⇒8⇒1⇒3⇒5⇒7⇒9⇒0⇒2⇒4⇒6⇒8⇒1⇒3⇒5⇒7⇒9. For this do the following after drawing the schematic using Circuitmaker. b) Design an 8-bit Switch tail ring counter/ Johnson counter using D flip-flops. 15. display devices and logic gates. 25. 7. 49. E) = ∑M (0. 21. 9. Try to draw a single schematic diagram for each experiment wherever possible. B. 46. 44. 51. problem no. 5. B. (For this use Electronics Work Bench simulation Package). using D flipflops by preventing lockout. 15. Design the following counters: a) Synchronous decade up counter whose initial count is 0. Draw the necessary schematics for all the above experiments/problems using CIRCUITMAKER or ELECTRONICS WORK BENCH or Multisim 10 simulation package. b) Synchronous decade up counter whose initial count 0. 30. 13. 21. D. 8. D. Using the A/D converter device of Electronics Workbench simulate an 8-bit A/D conversion operation by applying the necessary control inputs to the A/D converter device. 4. 53.42. Realise an Astable multivibrator circuit using several NAND gates only and hence determine the propagation delay of the NAND gate. After this vary the inputs by varying the position of input logic switches (also by a mouse click on the logic switches) and note the corresponding output (for each combination of the input) by observing the status of the logic display or observing the outputs on a CRO.e. 23. Design a Mod-2 counter using a 2:1 multiplexer only. 52. 20. D. which will display hours (1 to 12). 54. Note: Save all the schematic diagrams experiment wise under the folder name Ece-451 in the C drive of the respective PC. 31) F3 (A. 9. b) Use a D/A converter device to generate RAMP signal? (For this use Electronics Work Bench simulation Package). 27. 11. C. 6. 27) F2 (A. E) = ∑M (1. 50. Note down all your observations experiment wise using tables/truth tables and use required minimisation using Karnaugh Map or Logic converter of Electronics Work bench or Multisim 2001/ Multisim 2009 wherever necessary. C. according to group number. 43. 23. d) Synchronous counter using D flip-flops without preventing lockout which will produce the following bi-quinary sequence: 0⇒2⇒4⇒6⇒8⇒1⇒3⇒5⇒7⇒9⇒0⇒2⇒4⇒6⇒8⇒1⇒3⇒5⇒7⇒9. 4. 9. Suppose your group no is 3 and you have to save the schematic diagram for say problem no. 5. b) Design a 4-bit weighted-resistor D/A converter that will produce analog voltage from 0 to 15 V. a) Design an 8-bit Ring counter using D-flip-flops. a) Design a BCD to Decimal decoder driver circuit with active low outputs. 45.

Click F (for File). 3 and d1 ⇒ on the first day in the Digital Software Laboratory. then enter file name as gr3pr3d1. The different portion of the name of the file gr3pr3d1 implies: gr3 ⇒ Group3. pr3 ⇒ you are saving problem no. then select save as. Note: Laboratory report should be submitted group wise. then select folder Ece-451. -4- .

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