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# Digital Electronics Laboratory Using Circuit Simulation Packages (ECE-451) 1.

Realize the following Logic gates – NOT gate and two input AND, OR, NOR, XOR, XNOR gates respectively using NAND gates only to verify NAND as a universal logic gate. Use a single schematic diagram on the same screen for the above purpose. Realise the following Logic gates – NOT and two input AND, OR, NAND, XOR, XNOR gates respectively using NOR gates only to verify NOR as a universal logic gate. Use a single schematic diagram on the same screen for the above purpose. Verify the following Demorgan’s theorem by using logic gates: Using a single schematic diagram on the same screen for both the theorem. a) A + B = A.B

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b) A.B = A + B 4. Realise the following logical functions using combination of Logic gates: i) Without minimising the logical function and ii) By minimising the logical function. Comment on the difference between the two approaches. b) f (A, B, C) = A. B.C + B. C + A . C . c) f (A, B, C, D) = A. B. C. D + B . C + B. C. 5. Design a five-bit EVEN/ODD parity generator circuit using the following gates: a) NAND gates only. b) NOR gates only. c) Combination of NOT, OR and AND gates. 6. How would you use the following? a) A four input OR and NOR gate using two input OR and NOR gates respectively. b) A four input AND and NAND gate using two input AND and NAND gates respectively. c) How three input AND gate can be used as inhibit gate? 7. How would you realise NOT gate, and two input AND gate and NAND gate using Diode-Resistor and Transistor logic? 8. Minimise and synthesize the following logical function using NAND gates only: F (A, B, C, D, E, F) = ∑m (0, 2, 5, 7, 9, 13, 16, 19, 21, 26, 31, 35, 37, 39, 45, 51, 58, 60, 61, 63). (For this use Multisim-2001 simulation Package) 9. Design a Full adder circuit using Half adder circuits only. (For this use Electronics Work Bench simulation Package) 10. Design a 4-bit 9’S complement circuit using a) SSI gates and b) Decoder and any logic gates required. 11. Analyse the following circuit of Fig (a) using Multisim-2001, hence determine the truth table of the following combinational circuit i.e. express Y as a function of A, B, C and D.
U1A

A B

1 2 7400N U2A 1 2 7408N

3 1 2

U3A 3

Y

C D

7432N 3

Fig (a)

12. How would you realise a 16:1 multiplexer using lower order multiplexers only? 13. Using circuitmaker design a 5-bit majority and minority function circuit respectively using decoder and any other gates required. 14. Using circuitmaker design a) a 4-bit Binary to Gray and b) a 4-bit Gray to Binary converter circuits. 15. Design and simulate a 4:1 Multiplexer using NAND gates only. 16. Design and simulate a 2 to 4 line decoder using NAND gates only. -1-