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Discrete event simulation based on Archimedes law based on

[ typedef map < char , unknown x > CompressMap ]
Author: Said Mchaalia
draft copy septum 12th 2012

1. Abstract: in windows cmd command and all other leaflike operating system, the root creationism is the aim object. Thereby, starting with potential intentional works in 17xx in London and within the British empire hard work to achieve civilization continuity and to bring out what kind of human been could be realized, electricity did take its way to reach the desirable requirement of any householder. On the hand, the old Greece work inside philosophy and water proceeding processing were intentional inside secret light sign and brain powerfulness to be. Keywords: water proceeding processing, electricity, root creationism and cmd command. 2. Introduction: Electricity is basic to power any discrete event simulation, whereby the dimension of electrons could be the object of the best philosophy branch filed in advanced computer sciences and physics electricity environment dynamism. Figure 001, presents the keymotor flow of any discrete event simulation. Therefore, discrete event simulation basics need event occurrence inputs and event occurrence outputs to be identified during searching studying sign systems of signals inside any core processing units. As shown in figure 001, the first discrete event simulation signal inputs inside any modeling system for simulation requirement is the just data coming in input buffers. Indeed, leaflike water motor flow, the source of water production is not yet defined. Thus, based on hydro language electricity productions, the first fundamental following flow is the differential values in water variation levels. Hence, the interruption of the mechanical system to get motion and by this way the first step in just language of frequencies. Where this just language of frequencies is defined to be the number of tours per just language of one second time event value. Although, the intellectual integrated intentional input is the language (see figure 001 for more details), which is defined as couple of just language of two operands, such that the timeevent is a secret system sign, Therefore, in some synchronization significations of signalizing discrete event simulation models, the timeevent secret sign system has to be defined as frequency synchronization. Event though the valueevent secret sign system has to be defined as instantaneous event occurrence values. Hence, in the example of hydro language electricity productions, the just data coming in, is water depth performance. Furthermore, timeevent secret sign system is frequency synchronization of water depth amount quantity. Moreover valueevent secret sign system is the instantaneous sinusoidal following description function of the turbine. On the other hand, the background of figure 01 is to define and clarify civilization based on dictionary language as Lemepel and Ziv did it, whereby whose works did achieve sequential digital data encoding and waveform compression. Therefore, a civilization is a system in advanced progress and achievement of any enlivenment development involution inside dynamics environment mechanism. Hence, Archimedes laws, were background

database information of many scientific true right postulates, such that any wood flat surface could be swim on any water volume design. Therefore, apply Newton's law to Archimedes law, intentional secret sign is that the Earth's center is a kernel surface and could never be a just language of one kernel point. Figure 002 illustrates the main original principles of discrete event simulation based on Archimedes law. Because, just language of hydro electrical production productivity is original main sufficient suitable sophistical clean clear energy-to-light proceeding processing.

Figure 001: principles of discrete event simulation compile-compute-conclude processing analysis

Figure 001 presents

discrete event transaction core processor design, where the incoming in data are signal

transactions [3].

Figure 002: discrete event simulation based on Archimedes laws.

Figure 002 shows the discrete event simulation principles based on Archimedes laws, whereby any wood flat surface-form could be used to achieve this discrete event simulation modeling and design, In fact a selfish set of flat surfaceform woods could be defined for any instantaneous instant time event value. Though, a global simulation time is required. Thus, a global clock or timer, which could be bringing to a flat surface on the Earth's Moon, because it is just language of one Earth's Moon for all alive active human persons inside Earth. 3. Light from transistor basic logic influence system: In fact, chemical substances are natural keymotor flow for anything involving water, which is root creationism of electrical hydro language. Hence, transistor chemical substances are basic logic influence system of semiconductor, whereby electrical current flows are not clear defined. The most around semi-conductors used within Integrated circuits. Even though, doping silicon or geranium to create transistor is intentional signalizing for studying core proceeding and processing, whereby just language of logic and arithmetic operations are implemented. Therefore, this just language of logic and arithmetic operations are measurable units in binary bit registers and control data flow graphs, whereby parallel scheduling jobs [1,4,5,7] appear to be optimized for any core make neutralism language. Hence, for most around transistor applications, current digit displays are light emit diodes.

Figure 003: three pin semi-conductor switcher laws.

Figure 004: original main hertz counter.

Figure 005: two pin semi-conductor switcher laws.

Figure 006: overview viewpoint of electricity production.

In fact, in hertz definition [11], the counting is the basic logic influence system of Hz measurement unit. Indeed, Hz measurable amount quantity (echos waveform during modeling-simulation) is a number of tours per just language of one second time. Therefore, converting the number of tours for any movable mechanical system, require mathematical background. In Greece reading and Archimedes laws, this number of tours per second time could be easy converted to number of sines or cosines or sinusoidal similar periodic mathematical following description functions. Even though, transistor switching number could be then used to depict this sinusoidal similar periodic mathematical following description functions. Furthermore, as leaflike locking transistor selfish set, which could be easy to count the number of any sinusoidal periodic mathematical following description functions, the 555 trigger basics circuit described in figure 007.

Figure 007: basic transistor 555 trigger circuit.

Figure 007 illustrates the involution of transistor inside triggering opcodes, whereby the next step in this kind of simulation is to define the clock or the exactly time of discrete event occurrences. Although, in figure 006, the turbine has periodically sinusoidal movement waveform, which could be easy converted to {(onevent, offevent)}index throughout a digit sensor of rotation motion. Therefore the brain powerfulness of digital-analog design in this kind of discrete event simulation is to invent and evolved a powerful sensor for exactly delivering gathering number of tours of the production turbine per just language of one second time value unit. Indeed, from background work in frequency modeling cycle basics synchronization timer [6], requires fundamental mathematical functional description flow of envisaged signification synchronization timer, which could be then evolved inside the co-core processor to synchronize itself the cycle core basics proceeding processing.

Figure 008: co-core processor design to capture turbine rotation velocity in order to transfer it to triggering signal Figure 008:

co-core processor design to capture turbine rotation velocity in order to transfer it to triggering signal, which could then used as 555 IC incoming input to output designed square waveforms, whereby this square waveform could be then used inside discrete event simulation core signification synchronization.

4. Verification methodologies for deep-sub-micron circuits: During last decade micro-electronics devices have extended for functionality of many consumer and industry production dramatically. This tend is partly due to the continuously increasing complexity digital design circuits. However, this complexity also adds a significant burden to the design verification phase of digital circuits. In particular timing and functional verification are important parts in the validation of digital systems, especially digital designs. Due to the above mentioned complexity of those designs the validation phase frequently is the

most time consuming task. This statement is especially true for future generation of digital design chips, which will integrate more than 500 million transistor on a single die (deep submicron designs). Because of this complexity, exhaustive functional verification is the only way to test the functionality of the design. Further, post layout timing verification must ensure that all elements on the chip are meeting the projected timing conditions. Unfortunately, the huge amount of active and passive elements within deep submicron designs will push current verification methodologies and tools to and beyond their limits. Presently, verification efforts can be divided into three categories; which are dynamic analysis, static analysis and formal verification. Thus, dynamic analysis is also known as simulation. This techniques is very common and there are a lot of commercial tools available. However, usual uni-processor simulation platforms often reach their performance limits dealing with large design. While special methods are capable of reaching high simulation throughout this performance gain achieved by neglecting important timing information. Furthermore, static tools are usually used to check timing of digital design. They are computational less expensive but require manual support from designers. Unfortunately, this may be significant drawback when chip complexity increases. Finally, formal verification tools verify design aim objects based on formal description of digital circuits. Although, due to involution complexity of implemented algorithms only designs of small to moderate size can be handled by these tools efficiently at this time. Alternatively, parallel timing simulation [1,4,5,6,7] on computer (whose abstract review shown in figure 009) has been suggested to speed up functional and timing simulation. However, parallel simulation is difficult thread task due to sequential digital data encoding and compression [2], whereby dictionary techniques dictate orders in computational “have to be exceeded representation”. Consequently, it is often not possible to reach intentional speedup gain. Hence, figure 010 depict the proposal famous fundamental fatal fast following cycle basics for parallel timing simulation [10]. Figure 010 depicts an electrical circuit of the phenomena of light emission. Light could only emitted and transmitted using Light Emit Diodes and light bulbs or similarly. Therefore, the measurement amount quantities of lights and whose velocity is depending on those involving tools, such electrical energy-to-light converter toolboxes. Indeed, these energy-to-light converter toolboxes allow light motion anywhere. The most around application is the disco emit light gaming-operations, optical-fiber data transmission, electrical arcs, the color of Earth's Sky at night and so on, whereby the movable distance of the produced light could be may be attained 400000 meters or more in the next high-tech light bulb production processing. In fact, the motion of light is hard thread-task to be achieved. Nevertheless, the true right light motion velocity is original main sufficient suitable organization flow for researchers in electrical branch and field's disciplines, whereby the true right definitions of velocity should have been integrated within any light motion phenomena study. The insight of logic processing analysis of light motion velocity with source energy batteries of cars and trucks, is the distance variations belong to this light velocity motion mechanism from 1 meter (car rear-light) to 300 meter bright light (headlight of car). Hereby, to calculate light motion velocity, the time event value would be needed. For example, for 10 seconds time, the above detailed distances could so easy reached (1 meter to 300 meters). By this way, the light motion velocity, which is defined as:
velocity= ∂ distance (t) , proves that the light motion velocity could never be constant and ∂t
8

till now not yet reached the C, C=2.99 x 10 m/ s value identified by Einstein and co. The most around intense light motion velocity is the electrical arc motions' production within the insight of high power voltages.

Figure 009: basic principal primordial structure of core proceeding processing unit (computer)

Figure 009 shows the basic principal primordial structure of core proceeding processing unit (computer), whereby fast functional parallel timing simulation and parallel scheduling job simulations are aim object of any inside research environment dynamism. Therefore, to speed up cycle based timing simulation and then the parallel scheduling jobs, a possible proposal high frequency timer, which is shown in figure 010 could be then implemented inside circuit to generated clock triggering waveform from just language of usage inductorcapacitor filter, laser light emit diode, laser light receive transistor and 555 IC. Thus, based on advanced NASA works, the visible like light as bright laser light is a gigs hertz rotation motion into fundamental following frequency flow. Therefore, figure 011 illustrates natural visible light transmissionreception-absorption phenomena. Although, primordial problem is to synchronize principally frequent reading bytes and writing into byte-matrix with core processor frequency. Hence, the original main sufficient suitable definition of frequency is the number of sinusoidal periodically following description function of core processor, whereby parallel timing simulation [1] and scheduling jobs [10] take places. Furthermore, speeding up functional timing simulation inside core processor is aim object of discrete event simulation. By this way, Said Mchaalia [10] did investigate the complexity of synchronizing signalizing searching studying core processor opcodes (see page 9 in reference [10]) to significant sophistical global timer frequency, which is issued from laser light diode. Indeed, figure 010 depicts an idea of using this laser like light to proceed timing simulation and

parallel scheduling job (pipelines, which are following event occurrences: ready to be executed, in queue, fetched (picked up from queue), ran(scheduled), stored back into byte-matrix) inside core processors.

Light transmission and magnetic reception into LRD

Light absorption and magnetic amplification

Figure 010: basic principal primordial structure of light signalizing frequency signification synchronization

As reference application for light motion velocity, the primordial thread-task production is to take the beam bicycle lighting production, which is based on the physical power that could be involved within such an organization flow. When this power is less ore mere, the produced beam bicycle light is not clear bright, and when this power becomes stronger, the produced beam bicycle light becomes intense bright. The mathematical format of the energy inside such a thread-task processing, is the integration of produced power within instantaneous time values; E=∭ClearVolume (∫ power (t) dt)dV , whereby the clearness of envisaged surface-form is depending on the power within the light production mechanisms. This power could be varied between 2.5 micro Watts LED to unknown x tera Watts light bulbs. Therefore, fundamental following flow for light production is just language of frequency to make nucleus bright light leaflike laser light. Indeed, the most around signalizing significant applicable light implementation manipulation is the compilecompute-conclude brain usage in many industrial branch field disciplines. Figure 011 shows a compact model of the primordial principally industrial brain power of compile-compute-conclude proceeding processing, whereby the main original component is the byte matrix (typedef map<char, unknown x> CompressMap ) component such that, memory, registers inside core processing unit, and hard disk or portable memory sticks (see figure 011).

xAX

xBX

xCX

xDX
store back

xSP
stack pointer

xSI
stack index

xDP
data pointer

XDI
data index

purpose bitregister purpose bitregister purpose counter

Figure 011: basic principal primordial structure of natural light signalizing frequency signification synchronization

Although, Von Neuman [2], did bring out the depicted viewpoint of core proceeding processing uniformity, which is shown in figure 011. Figure 011 depicts the intentional inspiration item inside sequential digital data proceeding processing basics. Therefore four basic component kernel keymotor flows, which are the memory component whose measurable data edge values are number of instantaneous couple bits, connection communication digit sensors whose measurable data edge values are voltage variation level of instantaneous current data edges inside any connection component, wires whose measurable data edge values are ratios of instantaneous basic logic influence systems such as temperatures, and the core processing unit whose measurable data edge values are number of bit registers used during instantaneous arithmetic and logic couple opcode organization flows. Indeed, the first step in intentional inspiration item inside sequential digital data proceeding processing basics was the transistor foundation, whose measurable data edge values are number of instantaneous couple (on, off) switching operations. The main sufficient suitable picture flow of transistor measurable unit could be shown in figure 018. Thus, following fundamental fatal functional flows define within any transistor hardware

description, shown in Figure 018, illustrates basic transistor transistor programmable push-pull involvement development dynamics environment mechanism. Therefore the movable measurable centric metric bitwise opcodes are measurements of voltage level variations inside load nil (see color brown shown in figure 018) or load one (see color magenta shown in figure 018). Hence, during fundamental fatal following functional fact flows of sequential digital data involvement inside figure 011 require just language, which is defined in figure 018, of logic bitwise opcodes at any instantaneous time event value, which will be then converted to iteration value inside co-software design of this just language of logic bitwise opcodes [10]. In fact, the main idea to drive the define circuit shown in figure 011, is to search the logic functional fact flows, whereby the principal logic AND, and logic OR should be then used to achieve desirable aim object functionalism. Furthermore, the primordial logic NOT could then be evolved during direct connection of the drain of Gate0 = {(push, pull)}(0)(n) to the source of Gate1 = {(push, pull)}(1)(i). Indeed, based on transistor programmable language depicting in figure 002, the normal transistor output is defined within load0 functionalism. The rest of possible other logic operations such that logic XOR, logic NAND and so on could be easy defined during enlivenment development of envisaged circuits shown in figure 011 and figure 018. Although, transistor basics modification is the intentional aim object of many workers inside sequential digital data proceeding processing basics. By this way Intel [11] consumer electronics and system on chip fabrication fact flows are objective destinations into basic elementary gate composed of just language of three transistors, because the variable resistor magnitude variation levels could be converted to transistor incoming voltage variation levels (see figure 018). Therefore Intel and co gates, which are composed of basic transistorowners, are just language of three transistors inside the first following elementary gate, which is the logic NOT gate. The transformation is involved in figure 001, which illustrates the three basic transistor gate. Thus, this gate represents the digital elementary component. Hence, all implemented Intel consumer electronics and system on chip components are gate associated sets. Therefore a core processing unit is a brain powerfulness whose measurable data edge values are number of instantaneous bit register architectures. Even though these instantaneous bit register architectures advance with a double unit measurement, which indicates that the database information could be double the required number of connection communication wires. 5. Verification methodologies based on dictionary keymotor flow (map<char, unknown x>) In fact, the aim object of this section is to present discrete event simulation based on Archimedes laws during combining fast functional timing simulation techniques [3] and parallel scheduling job simulation [1], which are static and formal timing aspect analysis. Hence, to fill in the requirement of the exactly true right definition of discrete event simulation, number counting processing of years should be involved within any modelingsimulation proceeding inside discrete event simulation. In fact, the start of year is first month birthday in any year. Even though, event activity is add(month's birthday, one day). Although, increment(month's birthday) in order to schedule one complete month counting, is proceeding processing to reach the second month and so on. Furthermore, event attribute is characteristics within any event occurrence. Therefore event attribute is magnitude variation level inside processing environment dynamics. Herewith, the envisaged event is the counting of the number of years. Therefore, event attribute is an account identification, which is the most significant number of days within any month, whereby December's account identification is thirty one days. On other hand, discrete event based on Archimedes laws is selfish set of wood flat surfaceforms placed on any water location. Therefore, the dictionary keymotor flow (map<char, unknown x>) is to associate a character keyword to any wood flat surfaceform in a given water location. Thus, the unknown is a list to engender instantaneous event occurrences on this wood flat surfaceform.

Character a b c d

Water location Californian - Hawaii border Japanese - Russian border Australia - Southern border Norway - Northern border

Unknown x assignment {(timeindex, eventindex)occurrence}j ∈IN {(timeindex, eventindex)occurrence}i ∈IN {(timeindex, eventindex)occurrence}p ∈IN {(timeindex, eventindex)occurrence}q ∈IN

Table 001: Water local for based Archimedes discrete event simulation

Hence water locations are Californian-Hawaii border, Japanese-Russian border, Australia-Southern border and Norway-Northern border. Indeed, this sinusoidal following description function indicates the frequency signification synchronization, which could be then used to drive the timing simulation and parallel job scheduling for any occurrence. Thus, the occurrence description is basic logic influence systems.

1.5 1
magnitude level variation

0.5 0 0 -0.5 -1 -1.5
iteration number

20

40

60

80

100

120

140

160

Figure 012: Shadow of turbine motor tour numbers per unknown float x seconds time

Figure 012 illustrates the shadow of turbine motor tour number per unknown float x seconds. This any turbine motor could be involved within any parallel hydro electrical power production in considered above water locations, which are Californian-Hawaii border, Japanese-Russian border, Australia-Southern border and Norway-Northern border. Indeed, this sinusoidal following description function indicates the frequency signification synchronization, which could be then used to drive the timing simulation and parallel job scheduling for any occurrence. Thus, the occurrence description is basic logic influence systems. In fact, for any discrete event simulation based on Archimedes law, system and signal need to be defined and clarified before any modeling-simulation thread-task proceeding processing. Even though, in this envisaged

discrete event simulation based on Archimedes law, a system is selfish set of following instantaneous item {(flat surface wood, water location such that Norway-Northern border, natural wind, natural rain, natural snow, robot mobile to control and proceed simulation)}. Though, a signal in this envisaged discrete event simulation based on Archimedes law is putpixel(.,.,.,) following description functionalism function. Hence, this putpixel(.,.,.,) following description functionalism function illustration require hardware IBM-AT interface cards and whose co-design software inspiration item. Although, to avoid any hardware damage, this discrete event simulation proceeding processing requires a responsible householder in any Earth's location near the considered water locations, which are CalifornianHawaii border, Japanese-Russian border, Australia-Southern border and Norway-Northern border. Furthermore, the evolved developed dynamics environment antennas are intentional requirement for any putpixel(.,.,.,) following description functionalism function inside the built house for co-modeling simulation hardware software co-design. Therefore, the antenna assignments could be wireless based on 4G+ technique methodologies or similarly [19]. During proceeding processing of this discrete event simulation based on Archimedes law, the simulation result effect are putpixel(.,.,.,) following description functionalism functions, which have to be shown as follows:

1.2 1
magnitude level variation

0.8 0.6 0.4 0.2 0 0 20 40 60 80
iteration number

100

120

140

160

Figure 013: Shadow of fixed frequency modulation function per unknown float x seconds time

Figure 013 illustrates the shadow of the 2.5GHz fixed frequency modulation-correlation following timing description function, whereby whose level variation represents a modeling-simulation envelop environment dynamism. In fact, in 1948, Claude Shannon [9], did invent effort to mathematically formulate this modelingsimulation envelop environment dynamism as

˙ ∑ [ p i log10[ p ]]
i∈ ℤ i

1

, where pi is a stochastic parameter value to

measure uncertainty amount quantity for each simulation iteration and joined incoming signal. In fact based on the timing functional echo works of Worgang Becker and Diekmann [11,12], Said Mchaalia [10] and co working on this modeling-simulation envelop environment dynamism, did bring out the following

mathematical dynamics environment mechanism:

i∈ ℤ , j ∈ℤ

[

1 ] . [1+[theta i + phi j ]]

The simulation results of this movable flat surface wood in any defined water location (see table 001) have to be illustrated in the following section. 6. Simulation result overview viewpoints: In fact, simulation result have to depict the movable fountain functionalism functional proceeding processing of considered flat surfaceform wood. Thus, figure 014 shows the shadow of flat surfaceform wood motion following fountain description function. Though, for just language of inside one period, the engendered envisaged binary number, which is similar to VHDL-language and cadence VCD file encoding of binary numbers, is the following binary number: binary 0x010x0z010z0x01b. Therefore, the binary xb and binary zb are two fuzzy binary values. The original main sufficient suitable parameter presentation of these fuzzy binary values is the “half bit representation”, which could be switched to either binary nil (logic false) or binary one (logic true). In fact, converting logic value ((logic false) or (logic true)) to measurable amount quantities of current data edge flows (see figure 016 for details about current data edge flow), is achievable thread-task of Intel and consumer electronics fabrication following flows.

1.5 1
magnitude level variation

0.5 0 0 -0.5 -1 -1.5
iteration number

20

40

60

80

100

120

140

160

Figure 014: Shadow of wood flat surface motion following description function

Thus, the main sufficient suitable aim object of sequential digital data encoding and compression [2], is to predict undefined binary bits such that the binary xb and binary zb (see said-thesis.pdf, page 44). Therefore, the hex-decimal “encoding representation” of a movable fixed 2.5 GHz frequency [18].

0 0 0
magnitude level variation

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 -0.01 -0.01 -0.01 -0.01 -0.01 -0.02 -0.02
time in nano seconds

Figure 015: Shadow based frequency of wood flat surface motion following description function

Figure 015 shows the shadow based on the frequency of wood flat surface motion following description function. From shown in figure 015 magnitude level variation inside the considered interval time, which is [0 nano seconds, 1.8 nano seconds], the compiled-computed-concluded frequency is then frequency value of
5 GHz , whereby this 9

5 GHz is intentional original main root mean frequency. Furthermore, the next up steps of 9

researchers within sequential digital data encoding and compression are to determine the harmonic frequencies and then to provide necessary sequential digital data encoding leaflike scalar quantization (used in JPEG-LS data compression techniques) and vector quantization too (see said-thesis.pdf, page 55 for more details). Thus, David Huffman [17, 18] did invent in 1950 as student in MIT university (USA). Figure 016 illustrates Shadow based current data edge flows of wood flat surface motion following description function. Hence, this control data flow graph is event basics logic influence system for any counting-computing opcodes signalizing signification synchronization environment dynamism. In fact, the best compiler optimization is to directly implement a co-design hardware-software based on control data flow graph involving transistor language transition transactions. The “start interruption” process node within figure 016 has role

to interrupt most around circuit to start collect data to be measured within any simulation time. “End interruption” process node plays a similar rule as cutoff link switcher. Furthermore, the other nodes are arithmetic-logic operation nodes. The following motor flows of data edges is that the following values are binary “made representation”, whose last values are instantaneously stored inside “grounded to gathering information database” node. Figure 016 depicts an original primordial “made representation” of control data flow graph, whereby a( . )sin2 ( . ) function could be then used to identify selfish set of current data edge flow stepping scales. During modeling-simulation thread-task of co-design hardware-software based on control data flow graph involving transistor language transition transactions , a list of couples (timeevent, valueevent) would be involved within this simulation processing analysis.

Figure 016: Shadow based current data edge flows of wood flat surface motion following description function

Therefore, the main task in this modeling simulation proceeding processing analysis is to identify event values for each time value, whereby mathematical ratios are equations of xi to yj, which depict the fraction between xi and yj;
xi yj

.

Thus, probabilities occur often in measurement processing analysis. Thus, probabilities are ratio values less or equal to one. To associate with measurement processing analysis probabilities, which are determined as ratios of values at time t to maximum value for all time. Therefore, consider a set of measurements; {(t1,V1), (t2,V2), (t3,V3), ..,(tn,Vn)}. The maximum value of all time is (tj, , Vmax). The probability determination is defined as follows;

{(t1,

V2 V3 Vn V1 ), (t2, ), (t3, ), ..,(tn, )}. V max V max V max V max

Those probabilities would be involving within each measurement processing analysis of amounts and quantities, which are gains in magnitudes or gains in amounts, legacies, error corrections and other kinds of measurement processing analysis. 7. Transistor language transition transaction In fact, transistor language transition transaction is background information database for sequential digital data encoding and compression. Hence, figure 017 illustrates the main principally of sequential digital transmissionreception-absorption based on transistor language transition transactions. During modeling-simulation threadtask opcode organization flows, many dynamics environment mechanics depict any functional timing simulation of just language of considered digital-analog component, whereby inertial functional functionalism and characteristics are viewpoints of modeling and simulation event blowing language inside systems (MaS-EBLiS).

Figure 017: basic logic influence systems on toggle template class map<char, unknown x>

Therefore, in figure 017, the main keymotor flow inside technical methodologies of sequential digital encoding and compression is the powerfulness of voltage level variations form 0.9 Volts to may be mega (1000 kilo volts) Volts or perhaps tera (1000 giga volts) Volts. Furthermore, the intentional secret surround system is the wireless antenna and connection communication principles [19]. Moreover, transistor language transition transaction [3], involves involution investigate involvement of any sequential digital data encoding. Thus, during register transfer logics from elaboration of VHDL-language models based on XLINX and co digital background database for syntheses toolboxes [6].

Figure 018: Shadow based current data edge of fountain motion following description function

Figure 018 illustrates current data edge shadow based on following fountain motion description function, whereby event basic logic influence systems (basic logic influence system based on event occurrences) are just languages of incoming distinct voltage levels from the wireless dynamics environment dynamism. Even though, Figure 017 illustrates current data edge shadow based on following fountain motion description function, whereby event basic logic influence systems (basic logic influence system based on event occurrences) are just languages of incoming distinct voltage levels from toggling dynamics environment dynamism, whereby timing simulation and parallel job scheduling (magnetic flux, sequential binary outputs, sinusoidal inputs), are involvement insight involution inside sequential digital data encoding technique idea brain powerfulness,

Figure 019: Shadow of transistor language basic logics during current data edge fountain motion flow

Figure 019 depicts the shadow of transistor language basic logics during following current data edge fountain motion function flows. Thus, this basic logic transistor transition transaction could be easy detected during the elaboration of sequential digital database inside load 0 or load 1. The difference between the sequential digital database inside load 0 and load 1 is intentional aim object of searchers inside system on chips and deep submicron designing description background languages [3] and [5]. Said Mchaalia [8,10] and other leaflike locking transistor logics inside digital design background, however, use transistor language transition transaction as Petri nets defined in [4] and control data flow graph defined in [3, 10], to implement directly transistor language transition transaction inside digital design background. Even though, figure 019 shows a basic logic influence system based on direct implementation of transistor language transition transactions.

Figure 020: Shadow of transistor language basic logics inside digital design background language

Figure 020 depicts Shadow of transistor language basic logics inside digital design background language. Therefore, modeling transistor language basic logics within any timing simulation [1] and parallel scheduling job simulation [3, 4, 6], describe hard thread and tasks for many searchers during digital design background description. In switching controlling mode, the transistor language could be modeled with some synchronized opcode organization flows based on searching studying capacitance, whereby the original primordial principally threads and tasks involving in this proceeding processing are saturation and cutoff frequencies. For me, Said Mchaalia, the basic idea to model such a proceeding processing is to vary frequency ranges from nil (null) variation level

value to unknown x variation level values.

Figure 021: inductor-capacitor-resistor circuit for frequency variation realization.

Figure 021 depicts the realization of frequency variation inside a circuit to filter the signal output. The inductor L receive signal input edge characterizes current flows in Amperes. These current flows sustain or incur some basic logic influences. These current flows incur phase shifting and magnitude modification. Then they maintain their following flows within the circuit. Some of them will traverse the resistor and others will contribute for capacitor charge. The output node is resistor-capacitor filter characterizing the 3dB lossy magnitude for cutoff frequency. Thus, to measure this cutoff frequency within the 3dB lossy magnitude, the following mathematical functional operation
Gain dB=20.Log10 (

1−e

−a.RC.t

. Although, the input voltage waveform is depicted by: sin(2.pi.f.t). Hence, 3dB lossy
V out ) V¿

V out ) V¿

should be onward proceeded. The output voltage waveform is illustrated by , allow then short time interval

magnitude from the maximum gain, GaindB=20.Log10 (

1 in Hz. In fact, frequency oscillation dt realizations is the aim object of digital data transmission branch fields. The simple way to achieve this is the usage of circuit included in figure 021. measurement dt, which is characterizing cutoff frequency; Incurring onwards send-receive those frequency is the subject aim of digital data transmission such this involved within digital satellites processing analysis. The main original theme of this incurring onwards is the data encoding decoding processing analysis. Hence, Shannon did propose an idea of data encoding based on the bit-word-length calculations thus the minimum amount of bits to be used to encode a character a for example found in an alphabet set of N characters. This number is thus calculated 2 x = N +1 . To search x, just introduce the logarithm function as follows: x x 2 = N +1→ log 2( 2 )=log 2 ( N +1) . Therefore, this x number could be determine as follows;
x=log2 ( N +1 )

. Indeed, the logarithm conversion between bases is: log a ( y)= ln ( y) . Although,
ln (a)

ln ( N +1) x=log2 ( N +1 )= ln( 2)

, where ln(.) is the natural logarithm function. As example, where the ASCII

code (255 characters) were encoded, the amount of bits was eight bits. In fact, to encode one character

from the 255 character alphabet set, a sequence of eight bits is required for example 10011010b. To send this character, the above techniques such the charging and discharging of the capacitor of figure 11 eight times or more would be involved. In fact, the 1b represents the highest magnitude amount, however the 0b represents the nil environment of the magnitude amount. An other methodology is to convert such a binary sequence to integer value and to use the potentiometer command and controlling for digital-analog converting. Figure 022 represents such a processing analysis. For further gathering discovering database's information, functional description equation details are distinct.
[sin(.)] .[exp(.)] wave-form modeling simlation processing

magnitude

time

Figure 022: waveform within modulation and modeling-simulation processing analysis.

Figure 22 shows the waveform depicted by the mathematical function [sin ( .)]. e(.) . Thus, within this mathematical function the magnitude change values indicates the resistor value variations for resistorcapacitor filter. The nil values indicates the logic false and the summit magnitude value indicates the logic true. The between value variation determines the fuzzy logic processing analysis. Notice the original frequency within this waveform is the ratio of one to the interval time separating two successive magnitude summit values. This frequency is measured in Hertz (unit is Hz). So, varying resistor values allows magnitude variations of output node. This produces a frequency variation inside the envisaged circuit. For equivalence task, an inductor could be involved. Therefore, the new circuit would be depicted with inductor-capacitor circuit. The inside circuit frequency could be measured throughout this mathematical formula; L.C.4.p 2 . f 2 =1 , where p is a ratio of 314 to 100, and f is the frequency to be calculated. The frequency calculation is background variations of L when C is constant or vice versus or together varying in time. Therefore, the frequency is a ratio of 1 to 2.p √ L.C . In fact, when wanting to set the frequency to its highest possible value, the inductance L and the capacitance C, should be less as they could be. As example for given values of C = 1 micro Farads, and L = 1 micro Henry, the frequency is then equal to about 159.23 Hz.

8. Multi-frequencies searching studying opcode organization flows: Searching frequency for applied waves in some branch field applications, need basic liable intentional smart modeling-simulation proceeding processing analysis. Although, the applicable frequency units are subject of discussion in many frequency application disciplines. Even though, as shown in figure 022, the magnitude level variation is a float number, which is the nearest float to fourth (0.25). Not only his searching magnitude level variations based on frequency searching studying opcode organization flows allow to investigate resonance effect aspects, but also bring out power involution principles, where the lowest used power for controlling transistor language transition transaction is 1.5Volts. By this way, the fourth of such a float number is 0.375 Volts, which may be present the lowest voltage magnitude level variation in abs(x) value for drive transistor language transition transaction.

0.3 0.25 0.2
magnitude level variation

0.15 0.1 0.05 0 -0.05 -0.1 -0.15
time in nano seconds

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Figure 023 fourth magnitude level variation

Figure 023, depicts the magnitude level variation of frequency range . This frequency range allow to conclude that there is a float number, which is the nearest float to fourth (0.25), depicting the maximum variation of considered magnitudes. Although, the frequency amount quantity in digital signal processing is determine throughout the famous fundamental following formulation: magnitudemax – 3dB (sub(max (magnitudemax ), 3dB)) (and then search the corresponding inductance, capacitance and resistance values for validation. On the hand, the primordial principal organized aim object of transistor language transaction is searching studying of opcode organization based on just language of magnitude level variation, which is characterized by following table: sub(max (magnitudemax ), 3dB) = magnitude 1 −3dB
max ( N

∑ [weighti , j ,m ,n , p , q ×[ magnitude i ]])
0

N

Table 002: magnitude level variations based on frequency searching studying opcode organization flows

Table 002 presents the basic logic intentional swing dynamics environment dynamism, whereby the magnitude level variation make neutralism inside basic combination composition components during digital design elaboration and compile-compute-conclude proceeding processing involving timing simulation and parallel job scheduling for any possible mnemonic brain powerfulness and ideal aim objects.

9. Interfacing transistor language transition transaction Indeed, based on Lempel and Ziv [2], dictionary basic logic insight system is brain powerfulness effect resistance and capacitance results. Therefore, to transact is to carry or conduct database information, whereby the trade agreement assignment are the keymotor flows for any timing simulation and parallel job scheduling [1,3,4,7]. Hence, as shown in figure 017, a database transaction comprises a unit of work performed within a database management neural system or similar system against a database and proceeded in a coherent and liable intentional way independent of other transactions. Transactions in a database environment have two main purposes, which are - first of all, it is to provide liable intentional central metric measurable units of searching studying opcode organization flows, which allow correct recovery from failures and keep going database consistence even though in cases of system failure. Although, when execution stops completely or partially and many operations upon database remain completely with unclear status, then transition transactions are requirement involutions. - secondly, it is to provide isolation between programs accessing a database concurrently. Thus, without isolation the outcomes of programs are possible erroneous basic logic influence systems. Furthermore, a database, by definition, must be atomic consistent isolated and durable. Thus, database practitioner often refer to these properties of database transactions using the acronym synthesis toolboxes. Transactions provide in fact an “all or nothing” proposition, starting that each centric metric measurable methodology measurement unit performed in a database must either complete in its entirety or have no effect whatsoever. Further, the system must isolate each transaction from other transactions, results must conform to existing constraints in the database, and transactions that complete successfully must get written to durable storage. Moreover database and other stochastic storage space, which treat and proceed the integrity of database of data as paramount often include the ability to handle transactions to maintain the integrity of data. A single transaction consists of one or more independent units of work, each reading and/or writing information to a database or other data store. When this happens it is often important to ensure that all such processing leaves the database or data store in a consistent state. Therefore, during interfacing transistor language transition transaction, bitwise operation operate on one or more bit patterns or binary numerals at the level of their individual bits. Thus, on the most older micro-electronics digital design description, bitwise operations are slightly faster than addition and subtraction operations and usually significantly faster than multiplication and division operations. However, on modern Archimedes law discrete event simulation (digital design architectures), this is not the case, whereby bitwise operations are generally the same speed up as it wants for addition (though still faster than multiplication). In fact, bitwise operations have to consider sequential digital amount data measurable equivalence length for centric metric measurable methodology modeling at any instantaneous inspiration insight inside time

environment dynamism. Thereby, bitwise NOT is a unary opcode organization flow and though bitwise OR, AND, XOR, NAND and co are binary opcode organization flows.

Figure 024: shadows of some bitwise opcodes organization flows.

Figure 024 presents some synchronized opcode organization flows, whereby bitwise operations are involving. 10. Conclusion viewpoint overview In nowadays designers have to verify a huge of complex levels of digital circuits, embedded software and onchip analog circuitry with fragmented methodologies that substantially impede verification speed and efficiency. They also face a large number of technical issues including design performance, capacity, test development, test coverage, mixed-signal verification, and hardware-software co-verification methodologies. In fact, optimizing verification speed is a complex research subject. Overall, verification methodologies are used by the designers at a variety of design integration levels. To improve digital hardware design using these verification methodologies, many digital simulation techniques are used. One of them is discrete event simulation, which has successful track record in the improvement of hardware verification process. In contrast to other simulation methods (leaflike differential equations) in which systems evolve continuously in continuous time, the systems in discrete event simulation are described by discrete events and appropriate processes. Discrete event simulation performs, indeed, each event or transaction or item individually using an appropriate process.

In fact, simulation, however, is not a satisfactory solution to the validation problem of digital hardware for many reasons such as: each schedule (run) proves only the correctness of the design under verification for that particular sequence of inputs (stimuli); and only one design under verification state and input combination are visited per simulated clock cycle. However cycle-based simulation involves these simulation limitations, it is still a sophisticated technology choice for the validation process of

large synchronous systems, in which logical simulation is nicely scalable regarding to designer requests. To propagate values from system inputs to system outputs, a simulation clock cycle is required. After finishing one cycle, the next cycle will be begun. Moreover, practical cycle-based simulators allow for circuits with multiple clocks and interface to event-based simulation. However, cycle-based simulation ignores system delays and inter-phase relationships. This limits the amount of information about the design that can be extracted from the simulation. Note that cyclebased simulation does not work for asynchronous designs and cannot be used in timing verification. Event-driven simulation environments uses the traditional discrete event simulation mechanism and considers system delays and inter-phases. Thus, during each verification process using either cycle-base
simulation or event-driven simulation, we have the opportunity of outputting the simulation results to waveform diagrams.

Figure 025: model card meilhaus300 for basic logic bus interface communication during measurement principles proceeding processing dynamics analysis

11. Reference papers

[1] Uwe Schwiegelsohn, A system-centric metric for the evaluation of online job schedules, 2011, Journal of Scheduling, 14, 6, 571 -581 [2] J. Ziv and A. Lempel, A Universal algorithm for sequential data compression, IEEE transaction on information theory, vol. IT-23, No-03, 1997 May. [3] Edwin Naroska, Parallel VHDL simulation, Proceedings of the Design, Automation and Test in Europe Conference DATE'98, 159--163, 1998 [4] Uwe Schwiegelshohn and Lothar Thiele, Proceedings of the 19th International Conference on Application and Theory of Petri Nets, Workshop Hardware Design and Petri Nets (HWPN 98), 12--25, 1998 [5] Uwe Schwiegelshohn and Lothar Thiele, Periodic and Non-periodic Min-Max Equations, Proceedings of the 24th International Colloquium on Automata, Languages, and Programming (ICALP 97), 379--389, Springer, 1997 [6] Naroska and Uwe Schwiegelshohn, A New Scheduling Method for Parallel Discrete-Event Simulation, Proc. 2nd International Euro-Par Conference on Parallel Processing, 582--593, Springer-Verlag, 1996 [7] Uwe Schwiegelsohn, Preemptive Weighted Completion Time Scheduling of Parallel Jobs Proceedings of the 4th Annual European Symposium on Algorithms (ESA96), 39--51, Springer, 1996 [8] Said Mchaalia, Waveform compression draft copy, December 11th 2002, CEI, Dortmund University, Germany

[9] Claude Shannon, mathematical information theory, IEEE, 1948. [10] Edwin Naroska and Said Mchaalia, Free HDL Compiler Control Data Flow Graph and its application in Waveform compression draft copy, August 07th 2002, CEI, Dortmund University, Germany [11] Worgang Becker and al., Magetic Localization of EEG Electrodes for Simultaneous EEG and MEG measurement, IEEE confirence on medicine biology, Lyon 1992, pp 34-36. [12] Diekmann and al., Comparison of MEG, EEG and frequency MRI responses to identical electrical stimuli delivered peripheral nerve.[ [14] Bodanis, David (2005), Electric Universe, New York: Three Rivers Press, ISBN-978-0-307-33598-2. [15] Background electrical electronics courses. [16] http://www.nasa.sciences.gov [17] G. E. Blelloch, Introduction to data compression technical report, computer science department, Carnegie Mellon University, October 2001. [18] J. Vitter, Design and analysis of dynamic Huffman codes, Journal of ACM, 1987 [19] W. A. P. F. Ltd., Wireless Application Protocol, Wireless Session Protocol Specification. 5, Wireless Application Protocol Forum, 1999.