Grid Connected Photovoltaic (PV) Inverter with
Robust PhaseLocked Loop (PLL)
T. Ostrem, W. Sulkowski, L. E. Norum, and C. Wang
Index Terms— Field programmable gate array, integer
arithmetic, inverter, multivariable filter, phaselocked loop,
photovoltaic power system, voltage oriented control.
I. INTRODUCTION
PV system consisting of 16 strings of solar panels is
situated at Norwegian University for Science and
Technology, Trondheim. Fig. 1 shows the overall structure of
this PV system.
PV String 1
PV String 2
JB 1
PV String 15
PV String 16
JB 8
Inverter
Combiner
Box
Inverter Protection
Transformer
Grid
Fig. 1.. PV system at Norwegian University for Science and Technology,
system block diagram.
T. Ostrem is with Narvik University College, Narvik, Norway (email:
trondo@hin.no).
W. Sulkowski is also with University College, Narvik, Norway (email:
ws@hin.no).
L. E. Norum is with Norwegian University for Science and Technology ,
Trondheim, Norway (email: norum@elkraft.ntnu.no).
C. Wang is with Narvik University College, Narvik, Norway (email:
Chen.Wang@student.hin.no).
The work of this article aims at connecting one single PV
string to the grid by means of a stepup dc/dc converter and a
grid connected three phase inverter, as described in Fig. 2.
PV String
dc/dc
converter
3phase
inverter
Transformer
Grid
Fig. 2. Block diagram of inverter system with one single PV string connected
to the grid.
Table 1 presents some of the electrical data for the PV
string. The dc/dc converter will both cover maximum power
point tracking and keeping the dc voltage of the inverter at a
constant level.
In this article the inverter is directly connected to the PV
string, leaving maximum power point tracking and protection
systems for future work.
The PV system of Norwegian University for Science and
Technology is thoroughly described in [1].
TABLE I
ELECTRICAL DATA FOR THE PV STRING AT NORWEGIAN UNIVERSITY FOR
SCIENCE AND TECHNOLOGY
Nominal Array Voltage 210 VDC
Maximum Array Voltage 300 VDC
Maximum Array Current 5 A
II. PHASELOCKED LOOP WITH MULTIVARIABLE FILTER
The PLL is depicted in Fig. 3 and is proposed in [2]. The
circuit is using input's quadrate, but what makes it robust, is
the multivariable filter following the Clark transform
(abcĺĮȕ), tuned at 50Hz . Thereby all internal harmonics
caused by unbalanced voltages or voltage harmonics will be
filtered out. The PLL operates even at heavily distorted
voltages and will continue to generate a rotating reference
angle ș during a severe voltage sag, and by blocking input
noise at voltage interruption, the PLL will continue to run
even under such conditions. That may be useful for stand
alone operation. When the grid voltage is restored, the PLL
A
1424402883/06/$20.00 ©2006 IEEE
2006 IEEE PES Transmission and Distribution Conference and Exposition Latin America, Venezuela
2
will effectively synchronize, and the system may be
reconnected to the grid.
The feedback loop in Fig. 3 will tend to change the output
angle u
ˆ
until the latter is locked to the grid voltages at
minimum input’s quadrate v
d
. This angle acts as the reference
angle for the VOC system, and the trigonometric expressions
( ) u sin
and
( ) u cos
are utilized in the Park Transform of the
VOC.
A PLL based on zero voltage crossings is described in [3], also
based on an FPGA. The benefit of using zero voltage
crossings as synchronization signals is a simpler design, but
the main drawback is a lack of grid information in the
intervals between the zero crossings. It can also be difficult to
tune the loop filter, making a tradeoff between response and
reliability.
Fig. 3. Robust PLL with 50 Hz multivariable filter.
A. Multivariable Filter
The multivariable filter is shown in Fig. 4 and is proposed
in [2]. With a 50 Hz grid frequency, the angular frequency of
the filter is e
c
=2tf§314, and the filter constant k was chosen
to be k=20, thereby achieving a suitable bandwidth of the
filter. If the bandwidth is too narrow, the filter will suppress
even the control signals v
o
and v

if the grid frequency
deviates significantly from 50 Hz, and if the bandwidth is too
wide, unwanted voltage harmonics will pass through the filter.
Unbalanced grid voltages creates a 2
nd
harmonic
component on the vector angle u
ˆ
and eventual Park
Transform, while voltage harmonics tend to create a 6
th
harmonic. The multivariable filter removes both kinds of
disturbances effectively.
B. Loop Filter and Voltage Controlled Oscillator (VCO)
The loop filter (LF) is a PI controller, and the transfer function
of this controller is given in (1).
( )
s
s
k s F
i
i
p LF
t
t +
=
1
(1)
Fig. 4. Multivariable filter.
where k
p
=2.23 and t
i
=9 ms. This gives a good tradeoff
between stability and dynamic performance.
The VCO is simply an integrator, since the relationship
between eˆ and u
ˆ
is an integration, as stated in (2).
s
e
u
ˆ
ˆ
= (2)
III. VOLTAGE ORIENTED CONTROL
The structure of the current controller system is shown in
Fig. 5. The dc voltage is measured and compared to a
reference voltage. The output of the voltage PI controller in
the left of Fig. 5 makes a reference for the current component
i
d
, i.e. the active component of the line currents. The reference
of the reactive current component i
q
is set to zero, thereby
seeking for unity power factor (UPF).
The outputs of the current controllers is converted to a
polar representation, outputting a voltage reference amplitude
and angle correction, the latter added to the reference angle
u. These signals controls the pulse width modulator (PWM).
By the time this article was submitted, the different parts of
the design was successfully tested, but energizing the inverter,
tuning the controllers and closing the feedback loop still need
to be done, in order to experimentally verify the overall
design.
The inductors between the inverter and the grid have an
inductance of about 10 mH. The inverter switches are
insulated gate bipolar (IGBT) transistors.
The design of Fig. 5 may be expanded, thereby decoupling
the active and reactive current components, as suggested in
[4].
k
k
s
1
s
1
e
c
e
c
v
o
v

v
o
v

_
+
+
_
+
_
+
+
^
^
LF VCO
sin
cos
abc
o
v
dref
=
0
e u
v
a
v
b
v
c
v
o
v

ˆ ˆ
+
_
+
+
v
d
3
Fig. 5. Inverter with Voltage Oriented Control (VOC) system .
IV. SIMULATION RESULTS
The PLL with multivariable filter was simulated in
Simulink, and the results are presented in Fig. 5 – Fig. 7. In
each figure the uppermost plot shows the grid voltages, the
middle shows the angle u, and the last plot shows sin u and
cos u. In Fig. 5 there is a considerable grid voltage
unsymmetry, in Fig. 6 the voltages sudden drops, and in Fig. 7
there are voltage harmonics present. As can be seen from
these simulations, confirming the results in [2], the PLL is
very robust and not much influenced by these disturbances.
V. FPGAIMPLEMENTATION
A. Hardware and Software Environment
The design is implemented on a Xilinx FPGA of type
Virtex2, mounted on a National Instruments PXI7831R
device with 8 analog inputs, 8 analog outputs and 16 digital
input/output signals.
Fig. 5. Simulation of robust PLL with unsymmetrical grid voltages. From the
top: Grid voltages, reference angle u, sin u and cos u.
Fig. 6. Simulation of robust PLL with voltage drop. From the top: Grid
voltages, reference angle u, sin u and cos u.
The voltage and current measurements are supplied through
analog inputs, and the switching signals for the inverter are
allocated at the digital outputs. The resolution of the ADCs is
16 bits, and they are of successive approximation type with a
conversion time of 4µs, which gives a sampling rate of
200kS/s. The clock frequency of the FPGA is 40MHz.
Fig. 7. Simulation of robust PLL with grid voltage harmonics. From the top:
Grid voltages, reference angle u, sin u and cos u.
The PXI7831R device is running on a NI PXI computer
with LabView 7.1 software. All FPGA programming is done
in LabView, even though almost all of the design is put in the
FPGA. Only a monitoring and control interface is located with
LabView as execution target.
DC
Source
PI
PI PI
PWM
PLL
Trans
former
u
dc,ref
i
d,ref
i
q,ref
=0
u
dc
u
ab
u
bc
i
a
i
b
abc
o
o
dq
i
d
i
q
, u
dq
u
sin u
cos u
FPGA
4
B. Integer Arithmetic
Floating point calculations are not possible on the FPGA.
Multiplying a signal with a constant gain can be done as
shown in (3).
M
N
k
2
~ (3)
where k is the gain to be reached, and M and N are integers. In
(3) the signal is multiplied by N, and then shifted M bits to the
right. The order of the operations can be opposite, but then the
signal resolution is decreased.
In integer arithmetic a tradeoff between resolution and
overflow problems needs to be done. Besides, high resolution
leads to space and timeconsuming multipliers.
Also in summations and subtractions one must be aware of
overflow problems.
C. Lookup Tables
Sine and cosine calculations are made through 1dimentional
lookup tables. Each table has 1024 addresses with a
resolution of 16 bits.
D. Parallel Structures
One of the major benefits of the FPGA circuits, is the ability
to have several processes running in parallel. The data
caption, the Clark (abc to o) and Park (o to dq) Transforms,
the PLL, the PWM and the VOC are all running in parallel,
sharing signals. There is no need for interrupting a main
program sequence to carry out more critical tasks, since all
functions are running constantly.
E. PI Controllers
The proportional part of the controller is made according to
(3). Adding a shift register gives an integrator, as described in
[5], and expressed in (4).
( )
1
1
÷
=
z
z F
i
(4)
The input (or output) signal must be scaled to obtain correct
time scale, depending on the sample interval z.
F. Rectangular to Polar Transform
The most challenging part of the FPGA design is to
implement the rectangular to polar transform in the middle of
Fig. 5 in a simple and accurate way. This transform is
expressed in (5)


.

\

=
+ =
d
q
q d
u
u
u u u
arctan
2 2
¢
(5)
where u
d
and u
q
is the active and reactive reference voltages,
respectively, u is the absolute value of the reference voltage,
and ¢ is the reference angle correction given by the VOC
system. Both the arctan and square root calculation are
difficult to perform in integer arithmetic.
One solution is to approximate the output variables as
shown in (6).
q
d
u k
u u
~
~
¢
(6)
where k is some constant. These approximations are only valid
if u
d
>> u
q
and that u
d
is close to its nominal value.
VI. EXPERIMENTAL RESULTS
A. Robust PLL
Fig. 8 shows a test result for the PLL under normal voltage
conditions, showing two line voltages plus the reference angle.
The signals look a little bit “sloppy”, and the reason is that the
data captions of these plots are quite slow. The figure shows
anyway that the reference angle is locked to the grid voltages.
In Fig. 9, the c phase is disconnected, but still the PLL
synchronizes to the grid.
Fig. 8. Robust PLL during normal voltage conditions. From the top: line
voltages u
ab
, u
bc
and the reference angle u.
5
Fig. 9. Robust PLL with phase c disconnected. From the top: line voltages
u
ab
, u
bc
and the reference angle u.
B. Park Transform
The Park Transform of the line currents where tested,
measuring the line currents of a partly inductive threephase
load (Fig. 10) and a resistive load (Fig. 11). The figures shows
the line voltage u
ab
, the line current i
a
, and the transformed
currents i
d
and i
q
. The plots show that the Park Transform is
working properly, and so is the PLL. Otherwise, significant
ripple should occur on the transformed currents. The ripple on
these currents is probably caused by unsymmetrical load or
lack of symmetry in the current measurements.
It can be seen form the figures that it takes about 0.2 s
before the PLL has fully stabilized. One should also notice
that the reactive current component has a negative value when
the load is partly inductive. The reason is the synchronous
reference frame, where the active current component is in
phase with the voltage reference, and a leading current
component (capasitive load) will be interpreted as positive.
Fig. 10. Park Transform of line currents with partly inductive load. From the
top: Line voltage u
ab
, line current i
a
, transformed currents i
d
(positive) and i
q
(negative).
Fig. 11. Park Transform of line currents with resistive load. From the top:
Line voltage u
ab
, line current i
a
, transformed currents i
d
(positive) and i
q
(close
to zero).
C. Pulse Width Modulator
In the tests of the PWM, a voltage source was connected to
the dc bus of the inverter, and the inverter ac voltages were
measured for different values of the reference voltages u
d
and
u
q
. Fig. 12 – 14 show the line voltage u
line,ab
and the inverter
voltage u
inverter,ab
for different values of u
q
. It can be seen that
the inverter voltage is phase shifted to the line voltage when u
d
is changed, as expected.
VII. FURTHER WORK
Further tests need to be done in order to verify the
performance of the overall design. Both the PI controllers and
the rectangular to polar transform must be thoroughly tested.
For the former, lack of precision of small integer values may
cause problems like deadband or hysteresis, and for the latter,
startup conditions may be critical. It remains to be seen
whether any of these components of the design must be moved
to the high level part (LabView) of the design, or redesigned
in the FPGA.
Fig. 12. PWM test with u
d
positive and u
q
=0. From the top: u
line,ab
, u
inverter,ab
.
6
Fig. 13. PWM test with u
d
positive and u
q
negative. From the top: u
line,ab
,
u
inverter,ab
.
Fig. 14. PWM test with both u
d
positive and u
q
positive. From the top: u
line,ab
,
u
inverter,ab
.
A successful solution for the FPGA design described in this
article should extended with a dc/dc converter between the PV
string and the inverter, and procedures for maximum power
point tracking should be implemented. Monitoring and
protection schemes are also needed, to meet the requirements
of [6] and [7], concerning islanding conditions and de
energizing of the grid.
VII. CONCLUSIONS
Simulations and practical tests of a combined system
consisting of a PLL, a VOC current control system and a
PWM, all embedded in an FPGA, shows promising results.
Some further tests need to be done in order to verify the
overall inverter system supplied by a PV string. Successful test
results will provide a fast, compact and reliable control device
for the threephase inverter.
IX. ACKNOWLEDGMENT
The authors gratefully acknowledge the contributions of V.
Klubicka, Norwegian University for Science and Technology,
and J. Tokle and Z. Dokic for their technical support in this
project.
X. REFERENCES
[1] BP Solar Limited, “PV System Specification, Solar Skin PVNorway
(Trondheim)”, Mar. 2000.
[2] M. C. Benhabib, S. Saadate, “A New Robust Experimentally Validated
Phase Locked Loop for Power Electronic Control,” EPE Journal, vol.
15, pp. 3647, Aug. 2005.
[3] H. Holmberg, T. Ostrem, W. sulkowski, “FPGA PLL for High Power
Factor and Low Harmonics Content Active Rectifier,” EPEPEMC,
Riga, Sept. 2004.
[4] M. Malinowski, “Sensorless Control Strategies for ThreePhase PWM
Rectifiers,” Ph.D. dissertation, Fac. of Electr. Eng., Warsaw University
of Technology, Poland, 2001.
[5] F. Haugen, Regulering av dynamiske systemer, Trondheim: Tapir, 2001,
p. 75.
[6] IEEE 1547 Standard for Interconnecting Distributed Resources with
Electric Power Systems, 2003.
[7] IEEE 929 Recommended Practice for Utility Interface of Photovoltaic
(PV)Systems, 2000.
XI. BIOGRAPHIES
Trond Ostrem (SM’2004) was born in Kjollefjord
in Norway, on August 12, 1956. He received his
M.S. degree in Electrical Engineering from Narvik
University College, Narvik, in 2002. At the moment
he is a Ph.D. student, situated at Narvik University
College, and he is going to finish his thesis at spring
2007.
Waldemar Sulkowski (M’1998) got Dr.eng. from
Warsaw Institute of Technology Poland in 1987. He
worked as project researcher at Institute of Control
and Industrial Electronics in period 19871990. In
the period 19841990 he joined Institute of
Agricultural Mechanization at Warsaw Agricultural
University. In the period 19871988 he was on leave
as a research Project Engineer at Power Electronics
and drives division of EFAGlina Transformer
Company in Otwock Poland. In the period 1990
1992 he was on the postdoctoral visiting researcher at Norwegian Institute of
Technology NTH at Institute of Electrical Engineering in Power Electronics
and Electrical machines group. From 1993 he works as Assoc. Prof. at Narvik
University College at the Institute for Computer and Electrical Engineering in
Norway.
Lars E Norum (M’1989) received his M.S and Ph.D
degrees in Electrical Engineering from the
Norwegian Institute of Technology (NTH),
Trondheim in 1975 and 1985 respectively. From
1975 to 1980 he was a member of the research staff
at the Norwegian Electric Power Research Institute.
He then joined the Norwegian University of Science
and Technology (NTNU), where he is currently a
Professor in Industrial Electronics at the Faculty of
Information Technology, Mathematics and Electrical
Engineering. He served as Head of the Department of Electrical Power
Engineering at NTNU (19962000) and as a Scientific Advisor to SINTEF
Energy Research. He has been involved in many research and industrial
development projects in the field of power and industrial electronics. Presently
7
his research activities are within the field of digital and analogue signal
processing, mathematical modelling and control of electrical energy
conversion in renewable energy systems.
Dr. Norum is a member of IEEE, ACM and ISES. He has served as President
for the Board of Science and Technology at the Norwegian Society of
Chartered Engineers (19972001).
Wang Chenxi was born in Beijing in China, on June
20, 1981. She finished her Bachelor Degree in
Electrical Engineering in North China University of
Technology, 2004. The same year she attended her
Master Degree of Electrical Engineering at Narvik
University College, and at the moment she is doing
her Master Thesis.
5 makes a reference for the current component id. The outputs of the current controllers is converted to a polar representation. the angular frequency of the filter is c=2 f 314. in order to experimentally verify the overall design. Robust PLL with 50 Hz multivariable filter. The multivariable filter removes both kinds of disturbances effectively. 3 will tend to change the output angle ˆ until the latter is locked to the grid voltages at minimum input’s quadrate vd. The inverter switches are insulated gate bipolar (IGBT) transistors. as suggested in [4]. The benefit of using zero voltage crossings as synchronization signals is a simpler design. Loop Filter and Voltage Controlled Oscillator (VCO) The loop filter (LF) is a PI controller. since the relationship between ˆ and ˆ is an integration. Multivariable filter. The design of Fig. This angle acts as the reference angle for the VOC system.2 will effectively synchronize. thereby achieving a suitable bandwidth of the filter. B. i. tuning the controllers and closing the feedback loop still need to be done. 5. FLF s kp 1 i i s s (1) . 3. but the main drawback is a lack of grid information in the intervals between the zero crossings. thereby seeking for unity power factor (UPF). This gives a good tradeoff between stability and dynamic performance. and the trigonometric expressions and cos are utilized in the Park Transform of the sin VOC. while voltage harmonics tend to create a 6th harmonic. A PLL based on zero voltage crossings is described in [3]. 4. and the filter constant k was chosen to be k=20. outputting a voltage reference amplitude and angle correction. Multivariable Filter The multivariable filter is shown in Fig. also based on an FPGA. but energizing the inverter. and the system may be reconnected to the grid. With a 50 Hz grid frequency. the different parts of the design was successfully tested. making a tradeoff between response and reliability. Fig. as stated in (2). The output of the voltage PI controller in the left of Fig. the latter added to the reference angle These signals controls the pulse width modulator (PWM). the active component of the line currents. Unbalanced grid voltages creates a 2nd harmonic ˆ and eventual Park component on the vector angle Transform. unwanted voltage harmonics will pass through the filter.23 and i=9 ms. and the transfer function of this controller is given in (1). VOLTAGE ORIENTED CONTROL The structure of the current controller system is shown in Fig. 4 and is proposed in [2]. ˆ ˆ s (2) III.e. It can also be difficult to tune the loop filter. The VCO is simply an integrator. By the time this article was submitted. thereby decoupling the active and reactive current components. 5 may be expanded. The feedback loop in Fig. The reference of the reactive current component iq is set to zero. A. the filter will suppress even the control signals v and v if the grid frequency deviates significantly from 50 Hz. The dc voltage is measured and compared to a reference voltage. The inductors between the inverter and the grid have an inductance of about 10 mH. ˆ ˆ _ v + + k _ 1 s ^ v c c v + k _ + + 1 s ^ v Fig. vdref= + 0 _ vd sin + cos + va abc vb vc v v LF VCO where kp=2. If the bandwidth is too narrow. and if the bandwidth is too wide.
The resolution of the ADCs is 16 bits. in Fig. 5 there is a considerable grid voltage unsymmetry. reference angle . Simulation of robust PLL with unsymmetrical grid voltages.1 software. sin and cos . reference angle . Fig. 5.ref . 7. confirming the results in [2]. Hardware and Software Environment The design is implemented on a Xilinx FPGA of type Virtex2. From the top: Grid voltages. which gives a sampling rate of 200kS/s. mounted on a National Instruments PXI7831R device with 8 analog inputs. Fig. FPGA IMPLEMENTATION A. PI dq sin cos PLL abc PWM uab ubc Transformer IV. Simulation of robust PLL with grid voltage harmonics. SIMULATION RESULTS The PLL with multivariable filter was simulated in Simulink.ref id iq. The PXI7831R device is running on a NI PXI computer with LabView 7.ref=0 iq FPGA Fig. Fig. 6 the voltages sudden drops.3 DC Source ia ib udc udc. 7 there are voltage harmonics present. From the top: Grid voltages. and the last plot shows sin and cos In Fig. sin and cos . and the results are presented in Fig. the middle shows the angle . V. 5. From the top: Grid voltages. All FPGA programming is done in LabView. The clock frequency of the FPGA is 40MHz. 7. reference angle . Inverter with Voltage Oriented Control (VOC) system . even though almost all of the design is put in the FPGA. As can be seen from these simulations. sin and cos . Only a monitoring and control interface is located with LabView as execution target. In each figure the uppermost plot shows the grid voltages. . and in Fig. The voltage and current measurements are supplied through analog inputs. u dq PI PI id. 6. Simulation of robust PLL with voltage drop. and the switching signals for the inverter are allocated at the digital outputs. 8 analog outputs and 16 digital input/output signals. and they are of successive approximation type with a conversion time of 4 s. the PLL is very robust and not much influenced by these disturbances. 5 – Fig.
8. These approximations are only valid if ud >> uq and that ud is close to its nominal value. the PLL. the c phase is disconnected. but still the PLL synchronizes to the grid. and expressed in (4). The order of the operations can be opposite. There is no need for interrupting a main program sequence to carry out more critical tasks. showing two line voltages plus the reference angle. In integer arithmetic a tradeoff between resolution and overflow problems needs to be done.and timeconsuming multipliers. Besides. Multiplying a signal with a constant gain can be done as shown in (3). Rectangular to Polar Transform The most challenging part of the FPGA design is to implement the rectangular to polar transform in the middle of Fig. This transform is expressed in (5) Fig. Integer Arithmetic Floating point calculations are not possible on the FPGA. One solution is to approximate the output variables as shown in (6). E. and the reason is that the data captions of these plots are quite slow.4 B. where ud and uq is the active and reactive reference voltages. 9. and M and N are integers. Adding a shift register gives an integrator. is the ability to have several processes running in parallel. F. and then shifted M bits to the right. Also in summations and subtractions one must be aware of overflow problems. Robust PLL during normal voltage conditions. u is the absolute value of the reference voltage. Robust PLL Fig. C. 5 in a simple and accurate way. In (3) the signal is multiplied by N. ubc and the reference angle . since all functions are running constantly. Each table has 1024 addresses with a resolution of 16 bits. In Fig. and is the reference angle correction given by the VOC system. high resolution leads to space. the PWM and the VOC are all running in parallel. u ud k uq (6) where k is some constant. EXPERIMENTAL RESULTS A. Parallel Structures One of the major benefits of the FPGA circuits. From the top: line voltages uab. The signals look a little bit “sloppy”. The figure shows anyway that the reference angle is locked to the grid voltages. . D. Both the arctan and square root calculation are difficult to perform in integer arithmetic. VI. The data caption. Fi z 1 z 1 (4) The input (or output) signal must be scaled to obtain correct time scale. the Clark (abc to ) and Park ( to dq) Transforms. PI Controllers The proportional part of the controller is made according to (3). sharing signals. depending on the sample interval z. u ud 2 uq uq ud 2 (5) arctan k N 2M (3) where k is the gain to be reached. as described in [5]. respectively. but then the signal resolution is decreased. 8 shows a test result for the PLL under normal voltage conditions. Lookup Tables Sine and cosine calculations are made through 1dimentional lookup tables.
ab. and the inverter ac voltages were measured for different values of the reference voltages ud and uq. It can be seen form the figures that it takes about 0. Both the PI controllers and the rectangular to polar transform must be thoroughly tested. 11. Fig. The plots show that the Park Transform is working properly. lack of precision of small integer values may cause problems like deadband or hysteresis.ab for different values of uq. Otherwise. Fig.2 s before the PLL has fully stabilized. Fig. startup conditions may be critical. transformed currents id (positive) and iq (negative). and for the latter.ab and the inverter voltage uinverter. Robust PLL with phase c disconnected.ab. or redesigned in the FPGA. 10) and a resistive load (Fig. From the top: uline. and the transformed currents id and iq. From the top: Line voltage uab. FURTHER WORK Further tests need to be done in order to verify the performance of the overall design. 10. One should also notice that the reactive current component has a negative value when the load is partly inductive. The figures shows the line voltage uab. a voltage source was connected to the dc bus of the inverter. line current ia. where the active current component is in phase with the voltage reference. ubc and the reference angle . From the top: Line voltage uab. the line current ia. 12. For the former. The ripple on these currents is probably caused by unsymmetrical load or lack of symmetry in the current measurements. . C. as expected. and so is the PLL. Park Transform of line currents with partly inductive load. It can be seen that the inverter voltage is phase shifted to the line voltage when ud is changed. Pulse Width Modulator In the tests of the PWM. 11). measuring the line currents of a partly inductive threephase load (Fig.5 Fig. Park Transform of line currents with resistive load. transformed currents id (positive) and iq (close to zero). 9. significant ripple should occur on the transformed currents. It remains to be seen whether any of these components of the design must be moved to the high level part (LabView) of the design. B. 12 – 14 show the line voltage uline. line current ia. VII. and a leading current component (capasitive load) will be interpreted as positive. PWM test with ud positive and uq=0. Park Transform The Park Transform of the line currents where tested. The reason is the synchronous reference frame. Fig. From the top: line voltages uab. uinverter.
“PV System Specification. 14. and J. situated at Narvik University College. S. Presently . pp. In the period 19901992 he was on the postdoctoral visiting researcher at Norwegian Institute of Technology NTH at Institute of Electrical Engineering in Power Electronics and Electrical machines group. Narvik.ab. X. 2000.D. vol. shows promising results. compact and reliable control device for the threephase inverter.6 IX.ab. “FPGA PLL for High Power Factor and Low Harmonics Content Active Rectifier. H. Malinowski. He has been involved in many research and industrial development projects in the field of power and industrial electronics. “Sensorless Control Strategies for ThreePhase PWM Rectifiers. in 2002. VII.” EPEPEMC. concerning islanding conditions and deenergizing of the grid.S. Dokic for their technical support in this project. Norwegian University for Science and Technology. Eng. where he is currently a Professor in Industrial Electronics at the Faculty of Information Technology. to meet the requirements of [6] and [7]. Haugen. [5] [6] [7] XI. Waldemar Sulkowski (M’1998) got Dr. Fac. Some further tests need to be done in order to verify the overall inverter system supplied by a PV string. 1956. C. A successful solution for the FPGA design described in this article should extended with a dc/dc converter between the PV string and the inverter. Benhabib. 2000. BIOGRAPHIES Trond Ostrem (SM’2004) was born in Kjollefjord in Norway. PWM test with ud positive and uq negative. degree in Electrical Engineering from Narvik University College. Holmberg. PWM test with both ud positive and uq positive. “A New Robust Experimentally Validated Phase Locked Loop for Power Electronic Control. Tokle and Z. from Warsaw Institute of Technology Poland in 1987.D. sulkowski. a VOC current control system and a PWM.ab. REFERENCES [1] [2] BP Solar Limited. F. 15. Sept. He worked as project researcher at Institute of Control and Industrial Electronics in period 19871990. He then joined the Norwegian University of Science and Technology (NTNU). From the top: uline. ACKNOWLEDGMENT The authors gratefully acknowledge the contributions of V. IEEE 929 Recommended Practice for Utility Interface of Photovoltaic (PV)Systems. at Narvik University College at the Institute for Computer and Electrical Engineering in Norway. IEEE 1547 Standard for Interconnecting Distributed Resources with Electric Power Systems. Fig.eng. Solar Skin PVNorway (Trondheim)”. From 1975 to 1980 he was a member of the research staff at the Norwegian Electric Power Research Institute. and procedures for maximum power point tracking should be implemented. 75. uinverter. In the period 19871988 he was on leave as a research Project Engineer at Power Electronics and drives division of EFAGlina Transformer Company in Otwock Poland. Mar. He received his M. Riga. Regulering av dynamiske systemer. p. uinverter. 2005.S and Ph. T.ab. dissertation. Lars E Norum (M’1989) received his M. Warsaw University of Technology. Monitoring and protection schemes are also needed. At the moment he is a Ph.. 2001. From 1993 he works as Assoc. Trondheim in 1975 and 1985 respectively. of Electr. on August 12. From the top: uline. CONCLUSIONS Simulations and practical tests of a combined system consisting of a PLL. 2003. Poland. 2004. and he is going to finish his thesis at spring 2007. Ostrem. M. 13. 3647. 2001. all embedded in an FPGA. W. Prof. M. student. Aug. Trondheim: Tapir.” Ph. Klubicka. Successful test results will provide a fast.D degrees in Electrical Engineering from the Norwegian Institute of Technology (NTH). Mathematics and Electrical Engineering. [3] [4] Fig. He served as Head of the Department of Electrical Power Engineering at NTNU (19962000) and as a Scientific Advisor to SINTEF Energy Research. In the period 19841990 he joined Institute of Agricultural Mechanization at Warsaw Agricultural University.” EPE Journal. Saadate.
7 his research activities are within the field of digital and analogue signal processing. . mathematical modelling and control of electrical energy conversion in renewable energy systems. She finished her Bachelor Degree in Electrical Engineering in North China University of Technology. and at the moment she is doing her Master Thesis. Wang Chenxi was born in Beijing in China. Norum is a member of IEEE. Dr. He has served as President for the Board of Science and Technology at the Norwegian Society of Chartered Engineers (19972001). ACM and ISES. on June 20. The same year she attended her Master Degree of Electrical Engineering at Narvik University College. 1981. 2004.