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True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 1 / 71

Acknowledgements



First of all, I would like to express my appreciation of Dr.-Ing Jens Sauerbrey for his invitation to do a master
thesis project under his supervision and for his patient guidance during my master thesis project hold at Infineon
Technologies AG in Munich. I was truly very fortunate to have the opportunity to work under him as a master student.
In addition to providing his expert guidance in circuit design issues for Sigma-Delta modulators, he also provided help
in technical writing style and presentation style, and I found this guidance to be extremely valuable from which I
learned many practical issues concerning real analog circuit design. I enjoyed also his tips for hiking trips through the
Alps and explanations of the funny embarrassing bureaucracy organization in Germany.


I would also like to express my appreciation to Dr.-Ing. Roland Thewes who made it possible to have my
master thesis project done at the Corporate Research group at Infineon Technologies AG in Munich. I think that the
atmosphere in this research group was very good. When I started working in this group, I immediately noticed and
valued the high level of communication and the free flow of ideas. I also found the environment to be very comfortable
to work in, and people were very accepting and helpful. I feel very fortunate to have had the opportunity to work with
the other workmates in this group.


I appreciate Birgit Holzapfl for her guidance on CADENCE Spectre software system settings and friendship at
Infineon Technologies AG. I also appreciate Dr.-Ing. Ralf Brederlow, who also did a work on true random number
generator technique and also helped me get started on this project. I also enjoyed talking with him about a variety of
things, including trips to the mountains close to the Alps south of Munich.


I would also be thankful for Prof. Dr. Svante Signell from the Royal Institute of Technology – KTH – IMIT –
in Stockholm in Sweden who was my supervisor and final examiner for this project as well as his support with
administration matters related to the University and guidance on final adjustment on the thesis writing style and report’s
publication. I am thankful for the big support given by Ms. May-Britt Eklund Larsson before my trip to Sweden and
during my study time at KTH caring about bureaucracy matters for master students and giving advices for documents
required by the Swedish government. I should include my appreciation to all other Professors and university personal
stuff during my master thesis program at KTH. I should not forget the valuable comments and suggestion given by my
master student friends and opponents on the thesis presentation Michael Wester and Maksim Bryzgalov besides other
master student friends like Sezi Yamac, Sevag Balkorkian and Hendrik Tengstedt with whose I had very funny times by
doing laboratory projects during my study time in Sweden.


I am very thankful to Ph.D. Prof. Claudio Garcia, Ph. D. Prof. José Roberto Castilho Pereira and Ph.D. Prof.
Silvio Ernesto Barbin from the Electrical Engineering Faculty at the Polytechnic School of São Paulo University during
my bachelor degree graduation time in Brazil and enthusiastic support for my applications to a master degree
scholarship in Europe as well as office university personal stuff who cared about special required documents and
certificates.


I would like to express my lovely appreciation to my mother Rosemarie Klan Wilde, brother Daniel Emiliano
Klan Wilde and sister Marcia Gabriela Klan Wilde who always encouraged me to do my master thesis in Europe and
helped me on document matters in Brazil while I was in Sweden and Germany.


I am also very thankful to the IMIT and to the Royal Institute of Technology – KTH – both based in Stockholm
in Sweden who accepted me as a master student on the Master of Science Program on System-on-Chip Design and to
the financial support given by the Swedish Foundation for International Cooperation in Research and Higher Education
– STINT – during all my study and project thesis’ period. I should not forget that the whole project was performed at
Infineon Technologies AG in Munich in Germany which conceded me very useful and state-of-the-art computers and
software to conduct and finish this work.





True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 2 / 71

Index

1. Abstract ........................................................................................................................................................ 3
2. Introduction.................................................................................................................................................. 3
3. Current and Common Random Number Generators Methods and the AIS 31 Standard Document .. 4
3.1 Metastability Method.............................................................................................................................. 4
3.2 Astable Multivibrator Method ............................................................................................................... 4
3.3 Dual Oscillator Sampling Method......................................................................................................... 5
3.4 Direct Noise Amplification Method ...................................................................................................... 5
3.5 Discrete-Time Chaotic Method ............................................................................................................. 6
3.6 Hybrid Mixed Method............................................................................................................................. 6
3.7 AIS 31 Document Standard for True Random Number Generators.................................................. 7
Class P1 TRNGs.................................................................................................................................... 7
Class P2 TRNGs.................................................................................................................................... 8
AIS 31 Standard Statistical Tests........................................................................................................ 8
4. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter.......................................... 11
4.1 Sigma-Delta Modulator Analog-to-Digital Converters...................................................................... 11
4.1.1 Advantages of Oversampling Converters .................................................................................. 11
4.1.2 Oversampling without Noise Shaping ........................................................................................ 11
Quantization Noise Modelling ........................................................................................................... 11
White Noise Assumption ................................................................................................................... 11
Oversampling without Noise Shaping.............................................................................................. 12
4.1.3 Oversampling with Noise Shaping.............................................................................................. 13
Noise Shaped Sigma-Delta Modulator.............................................................................................. 15
First-Order Noise Shaping................................................................................................................. 15
Second-Order Noise Shaping............................................................................................................ 17
4.1.4 Sigma-Delta Modulator and Noise Modelling............................................................................. 18
4.2 Second Order Low Pass Sigma-Delta Modulator ............................................................................. 19
4.3 Fourth Order Band Pass Sigma-Delta Modulator............................................................................. 20
4.4 Second Order High Pass Sigma-Delta Modulator ............................................................................ 22
4.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures .................................. 24
4.5.1 Digital Signal-Processing Decimation Filter Structure.......................................................... 24
4.5.2 Thermal Noise, Quantization Noise and Oversampling Rate Analysis................................ 27
4.5.3 Choice of the Digital Bit Stream Generator System and Analysis ....................................... 29
4.5.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests............................................. 30
5. High Pass Sigma-Delta Modulator System Level Design...................................................................... 34
5.1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization.................................. 34
The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................... 34
The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit....... 36
The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................ 38
The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit .... 40
6. Requirements for the Different Components of the Analog Circuit System....................................... 41
6.1 Switched-Capacitor Circuit Requirements........................................................................................ 41
Differential Sinusoidal Input Signal Amplitude Influence Analysis............................................... 41
Switched-Capacitor Coefficients Scaling Analysis......................................................................... 42
Switched-Capacitor Parasitic Capacitance Analysis...................................................................... 43
6.2 Operational Amplifier Requirements ................................................................................................. 45
Operational Amplifier Gain Analysis ................................................................................................ 45
Operational Amplifier Input Capacitance Analysis ......................................................................... 46
Operational Amplifier Bandwidth Analysis...................................................................................... 47
6.3 Comparator Requirements.................................................................................................................. 48
Comparator Offset Analysis .............................................................................................................. 48
Comparator Hysteresis Analysis ...................................................................................................... 48
7. Analog Components Circuit Design........................................................................................................ 50
7.1 Operational Amplifier Transistor Circuit Design .............................................................................. 50
7.2 Comparator Transistor Circuit Design .............................................................................................. 56
7.3 Transmission-Gate Transistor Circuit Design .................................................................................. 57
8. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design, Simulation & Analysis.......... 58
9. Conclusion and Future Works ................................................................................................................. 64
10. References ............................................................................................................................................... 66
11. Appendix .................................................................................................................................................. 71

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 3 / 71

1. Abstract

Random number generators are essential components of many cryptographic systems. In contrast to pseudo
random number generators which are based on digital algorithms, true random number generators produce a random bit
stream from a nondeterministic natural source. Thermal noise is a possible source of unpredictable random noise.

The intention of the work is to analyze the feasibility of using a Sigma-Delta modulator based analog-to-digital
converter for true random number generation, whereas the noise source is integrated into modulator’s loop as well as
design a Sigma-Delta modulator ADC circuit structure on 90nm CMOS technology and additional digital-signal
processing blocks for generation of a random bit stream. Besides that the work includes compliance comparations to
international standard requirements given by international standard randomness tests as well as optimization and non-
idealities analysis of the Sigma-Delta modulator related to its switched-capacitor, operational amplifier, comparator and
transmission-gate circuit design requirements and additionally external environment influence analyses over the final
implementation in transistor level circuit design of the Sigma-Delta modulator analog-to-digital converter and
aggregated digital-signal processing blocks for constitution of a whole true random number generation system.

2. Introduction

The continuous and fast growing use of digital communication, mobile, computer and network systems has
aroused data security issue concerns where some type of data cryptography protection is required. Cryptography allows
for the private and secure exchange of authentic messages using carefully generated and distributed cryptographic keys
for encryption and decryption. The security of most cryptographic systems relies on unpredictable and irreproducible
digital keystreams using a nondeterministic random number generator [1].

Cryptographers often base RNG (Random Number Generator) designs on hidden sources such as keyboard
latency [2], hard disk drive air turbulence [3] and computer system clock state [1]. Nevertheless, the security of these
designs is often limited on the obscurity and the secrecy of the quasirandom source. Due to this fact, systems that use
truly random noise mechanism, such as electronic thermal noise, radioactive decay and atmospheric noise provide the
utmost cryptographic security because there is no need to protect the obscurity of the key generation method [1].

With the widespread application of system-on-chip on electronic systems, robust integrated-circuit RNG
designs will be needed for secure communication applications. Hardware RNG can feature a very high throughput when
well designed, but the produced bit streams usually show a certain level of correlation due to bandwidth limitation,
fabrication tolerances, flicker noise, aging and temperature drifts as well as external electromagnetic deterministic
interferences. Random noise sources, such as thermal and shot noise, which are actually the only white stochastic
processes which can be exploited at the integrated-circuit level, are often masked by deterministic disturbances like
substrate noise, flicker noise, power supply noise and external electromagnetic interferences requiring special hardware
and EMC shielding to comply with the international standards for true random number generation [4 5 6 7]. A common
procedure to remove statistical imperfections in the output bit stream is to process the sequence with a carefully
designed correcting or decorrelating algorithm which, from a high speed near-random input stream, generates a lower
speed bit stream with increased statistical quality, rising up the entropy contained in the input sequence [8 9 10 11].

The present work wants to study and design a robust, thermal noise-based TRNG IC subcell, suitable for
integration with digital encryption circuitry by using a Sigma-Delta modulator Analog-to-Digital Converter in which
after digital signal-processing just the desired frequency band portion of the spectrum which contains the useful thermal
noise is used to generate a random bit stream at the output of the system.

The next Section 3 describes current and common RNG techniques as well as the AIS 31 Standard Statistical
Tests for randomness analysis of the output random bit stream. Section 4 discusses the different options of Sigma Delta
modulator structures and choice of one of them for the current work based on oversampling rate, thermal and flicker
noise influences over the modulator’s output spectrum and AIS 31 Standard Statistical Tests results of the TRNG
system model. Still in the same section are defined the digital signal-processing decimation filter and algorithm for
generation of the output random bit stream. Section 5 presents two Sigma-Delta modulator circuit construction options
for the previous section chosen structure, reporting the circuit model simulation results and choice of one of the circuits.
Section 6 comes with the system requirements for the each of different components of the analog circuit design. Section
7 gives the electronic design of each component to be used on the final Sigma-Delta modulator circuit using the 90nm
CMOS technology library in CADENCE Spectre [73] including theirs transient, small-signal AC and large-signal DC
simulation results and analysis. Section 8 presents the final Sigma-Delta modulator ADC circuit its simulation results
and tolerance analysis to external environment influences and final TRNG with a Sigma-Delta modulator ADC system
followed by Section 9 discussing conclusions, observations and future researches themes for this random number
generation solution.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 4 / 71

3. Current and Common Random Number Generators Methods and the AIS 31 Standard Document

From references it is possible to classify some different integrated-circuit methods for producing random data
sequences, which are given as follow: metastability, astable multivibrator, dual oscillator sampling, direct noise
amplification, discrete-time chaotic systems and hybrid techniques. All these methods generate output bit streams that
can be statistically proved by standard randomness tests.

3.1 Metastability Method

The metastability method [12 13 14], shown in Fig. 3.1, uses the known metastability behaviour of digital
circuits when the input to a flip-flop is asynchronous to the system clock to generate random bit stream sequences. The
metastability occurs when the input changes in unison with the clock setup time. This phenomenon creates instability in
the circuit and produces oscillations, which can determine the high or low state of a comparator to generate a truly
random bit stream.



Fig. 3.1: Metastability method for true random number generator

Usually this method requires some type of negative feedback loop control to adjust the probability of the
output bit stream bias to 50%, which also generates some colouring on the output spectrum that reduces the final output
entropy. Due to this fact, this method usually has a post-processing unit [13 14] which reduces the output bit stream rate.

3.2 Astable Multivibrator Method

The astable multivibrator method, shown in Fig. 3.2, usually uses and electron trap [15] or the capacitor
voltage [16] fluctuations in one of the arm branches from an astable multivibrator which output is used to trigger a 1 bit
counter that generates a one-bit random number.


Fig. 3.2: Astable Multivibrator method for true random number generator
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 5 / 71

The electron trap fluctuations are usually very large compared with those of thermal noise, eliminating the
amplification of the noise source which saves area and reduces power consumption [15]. The drawback lies on the high
evident flicker noise property, which adversely affects the statistical balance of the output random numbers. One
proposed solution is to use the capacitor voltage fluctuation instead of a pure MOS device which eliminates the flicker
property and is approximately six orders of magnitude greater than the thermal noise signal [16].


3.3 Dual Oscillator Sampling Method

The dual oscillator sampling method [8 9 10 17 18], shown in Fig. 3.3, produces randomness from phase noise
in free-running oscillators. The output of the fast oscillator is sampled on the rising edge of a slower clock using a D
flip-flop. Oscillator jitters causes uncertainty in the exact sample values, ideally producing a random bit for each sample.
By carefully selecting the ratio between the two oscillator frequencies an artificially enhanced randomness can be
achieved [18].



Fig. 3.3: Dual Oscillator Sampling method for true random number generator

Previous experiments have proven that this method is more robust in the presence of deterministic noise
because of nonlinear aliasing phenomenon associated with sampling [18]. The drawback on this topology is that typical
levels of oscillator jitter are not enough to produce statistical randomness and bit-to-bit uncorrelation which invokes the
necessity of post-processing units at the output to further randomize it, potentially compromising the unpredictability of
the system.


3.4 Direct Noise Amplification Method

The direct noise amplification method [19 20 21 22 23 24], shown in Fig. 3.4, uses a high-bandwidth amplifier
to process the tiny ac voltage produced by a noise source such as thermal or shot noise. Due to the low magnitude of
these types of noise sources very high requirements are put in the design of the amplifier which needs to accurately
amplified the signal to thresholds levels with no bias to a clocked comparator.



Fig. 3.4: Direct Noise Amplification method for true random number generator

This technique permits a good shielding of the noise source from external electromagnetic interferes, but lacks
of adequate shielding from power supply and substrate signals in an IC environment which prohibits the exclusive use
of this method for IC-based cryptographic systems. Nevertheless, due to flicker noise and band limitation characteristics
of the amplifier output, usually a post-processing unit and a zero offset feedback control are required to randomize the
final output bit stream.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 6 / 71

3.5 Discrete-Time Chaotic Method

The discrete-time chaotic method can further be subdivided into categories, the first corresponding to
switching-capacitor dynamic systems [25 26], the second to switched-current [27 28 29 30] and the third to linear
unbalanced circuits or pipelined ADCs [31 32 11]. Chaotic systems are usually implemented using discrete-time analog
signal processing techniques [27]. As an example, take the Bernoulli shift map described by the following iterative
relationship:

X
n
= [2(X
n-1
– e(n)] mod 0.1 (3.1)

Where e(n) represents a Gaussian noise signal. It has been shown that sequences produced by the previous
iteration and similar systems are spectrally flat and uniformly distributed [33]. Furthermore, the divergence of
trajectories associated with chaos, along with the inclusion of noise, renders sequences from the previous iteration
unpredictable to an extent, qualifying the system to be used as a truly random bit source [3434].

Circuits which realize systems such as the previous iteration equation are similar to algorithmic A/D converters.
In addiction, the cascading of N stages of such a circuit that implements the given iteration equation turns into a
classical N-bit algorithmic A/D converter with an input range of [0, 1]. Fig. 3.5 shows such a type of A/D-based RNG
[11 32].





Fig. 3.5: Discrete-Time Chaotic method for true random number generator


3.6 Hybrid Mixed Method

The hybrid method is a mixture of the precedent direct noise amplification, dual oscillator sampling and
discrete-time chaotic methods [7], shown in Fig. 6. This method tries to take all advantages from these three methods to
reduce or overcome drawbacks when separately used.





Fig. 3.6: Hybrid method for true random number generator


These solution have shown to be insensitive to non-random influences and is unaffected by minor circuit errors,
such as mismatches, offsets, nonlinearities and process variations [7]. The drawback lies on the big amount of Si area
and power dissipation that the circuit requires as well as the limitations for the operational amplifiers used on the direct
amplification and on the A/D blocks.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 7 / 71

3.7 AIS 31 Document Standard for True Random Number Generators

Although random numbers play an important role in numerous cryptographic applications, ITSEC (Information
Technology Security Evaluation Criteria [35]) and CC (Common Criteria [36]) do not specify any uniform evaluation
criteria for random numbers. For this purpose the AIS 31 Document Standard [4] describes the evaluation criteria for
true (physical) random number generators.

Through this AIS 31 Document Standard, a TRNG (True Random Number Generator) contains an internal
physical noise source. It usually delivers an analogue signal that is digitized for further processing. The digitized noise
signal can be transformed into an internal random number sequence by means of post-processing in order to improve
the probability distribution of the digitized noise signal sequence.

For good physical noise sources, post-processing is not necessary and the digitized noise signal can be
transmitted directly to the output block. In this case, the sequence of internal random numbers corresponds to the
digitized noise signal sequence. The output block synchronizes the continuous or non-periodic generation of internal
random sequence with the calling of the (external) random number sequence.

The assessment of a physical random number generator is essentially based on statistical tests. On the basis of
different potential attack scenarios, various applications can place different requirements on the properties of the
external, and therefore of course also the internal, random numbers. In order to take this into account, the AIS 31
Standard Statistical Tests [4] introduces two functionality classes (P1 and P2).

Roughly explaining, the P1 property requires the internal random numbers to be statistically inconspicuous.
The P2-specific requirements should guarantee that they are practically impossible to determine even if the predecessors
or successors are known. Depending on the maximum attack potential attributed to a potential perpetrator, the target of
evaluation must itself recognize total failure or any interference that occurs in the noise source and may need to be able
to resist systematic manipulation attempts.

Fig.3.7 shows a diagram with the essential parts of a TRNG. It represents the typical sequential processing of
the signals.


Fig 3.7: AIS 31 Standard TRNG essential parts diagram

Class P1 TRNGs

TRNGs that belong to this class could be used in following type of applications:

- challenge-response protocols;
- openly transmitted, non-constant initialization vectors;
- seed generation for Deterministic RNGs of classes K1 and K2 [6]

The main requirements for the class P1 TRNGs are described by the AIS 31 Standard Statistical Tests
document [4] and resumed as follow:

- random vectors formed from internal random numbers sequences pass the disjointness test T0 and the test
procedure and evaluation rules specified in [4],
- if total failure of the noise source occurs when the TRNG is switched on, this must be detected
immediately,
- if total failure of the noise source occurs while the TRNG is being operated, it has to be prohibited that
random numbers are output whose internal random sequence was generated completely after the total
failure,
- the above properties must also be verified under the intended external usage conditions (temperature,
power supply, etc.) insofar as these can influence the function of the noise source,
- an online test must be implemented that checks the quality of the internal random numbers when triggered
externally.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 8 / 71

Class P2 TRNGs


TRNGs that belong to this class could be used in following type of applications:

- generation of signature key pairs,
- generation of DDS signature (private key x or random number k),
- generation of session keys for symmetric encryption mechanisms,
- random padding bits,
- zero-knowledge proofs,
- generation of seeds for Deterministic RNGs in classes K3 and K4 [6].


The main requirements for the class P2 TRNGs are as described by the AIS 31 Standard Statistical Tests
document [4] and resumed as follow:

- the TRNG belongs to class P1 with at least the same strength of mechanisms and functions;
- digitized noise signal sequences meet particular criteria or pass statistical tests intended to rule out features
such as multi-step dependencies. Moreover, the entropy test T8, specified in [4], is passed;
- if mathematical post-processing is present, it shall not reduce the average entropy per bit;
- statistical minimum properties of the digitized noise signal sequence must be proved each time the TRNG
is started;
- if total failure of the noise source occurs while the TRNG is in operation, it has to be prohibited that
random numbers are output whose corresponding internal random sequence was generated completely
after the total failure;
- an online test must be implemented with which the statistical quality of the digitized noise signal sequence
can be checked. It must be possible to trigger this online test externally or the TRNG must trigger at
regular intervals;
- the above properties must also be verified under the intended external usage conditions (temperature,
power supply, etc.) insofar as these can influence the function of the noise source;
- the TRNG must trigger the online test itself.


For detailed specification and how to apply the tests on the TRNG the original AIS 31 document [4] should be
analyzed more carefully.


AIS 31 Standard Statistical Tests

For the purpose of choice of the subsequent Sigma-Delta structures on the actual work the specified statistical
tests on AIS 31 document [4] will be used as quality parameters of the intended final solution. Tests to classify a TRNG
under Class P1 and P2 are described as follow according to the AIS 31 document [4]:

Test T0 (Disjointness Test)

The sequence w
1
, …, w
65535
∈{0,1}
48
passes the disjointness test if the subsequent members are
pairwise different.

From a sequence of 3145680 generated bits w
1
, …, w
65535
numbers of 48 bits each one are built which
are then compared one after other to check for the condition that one w
n
number is not equal to its
preceding w
n-1
. If this condition passes for all numbers the test is fulfilled.

Test T1 (Monobit Test)

X =

=
20000
1 j
j
b (3.2)

The bit sequence b
1
, …, b
20000
passes the monobit test if 9654 < X < 10346.



True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 9 / 71

Test T2 (Poker Test)

For j = 1, … , 5000 let cj = 8.b
4j-3
+ 4.b
4j-2
+ 2.b
4j-1
+ b
4j
. Furthermore, f[i]:=| {j: cj=i} |, i ∈[0,15] .

5000 ] [ .
5000
16
15
0
2
− |
.
|

\
|
=

= i
i f Y (3.3)

From a set of 20000 generated bits 5000 numbers c
j
are created each from 4 subsequent bits as stated.
From these 5000 numbers a frequency distribution for its values from 0 till 15 is built to later evaluate
the Pocker Test parameter Y. The bit sequence b
1
, …, b
20000
passes the Pocker Test (=χ2 modification
test with 15 degrees of freedom ) if 1.03 < Y < 57.4.

Test T3 (Run Test)

A run is a maximum sub-sequence of consecutive zeroes or ones. The bit sequence b
1
, …, b
20000

passes the run test if the number of occurring lengths lies within the permitted intervals, as specified at
the Table 3.1. The runs of zeroes and ones are evaluated separately.

Run length Permitted Interval
1 2267 – 2733
2 1079 – 1421
3 502 – 748
4 233 – 402
5 90 – 223
≥ 6 90 – 233
Table 3.1: Limits for Run Test

Test T4 (Long Run Test)

A run of length ≥ 34 is called a long run. The bit sequence b
1
, …, b
20000
passes the long run test if no
long run occurs.

Test T5 (Autocorrelation Test)

For τ ∈{1,…, 5000},

=
+
⊕ =
5000
1
) (
j
k j j
b b Zτ (3.4)

The bit sequence b
1
, …, b
20000
passes the autocorrelation test (with shift τ ) if 2326 < Z
τ
< 2674.
(Please note that the sub-sequence b
10001
, …, b
20000
is not used in the test variable.)

Test T6 (Uniform Distribution Test)

The sequence w
1
, …, w
n
∈{0,1}
k
passes the uniform distribution test with parameters (k, n, a) if:

] 2 , 2 [ | .
1
a a x w n j
n
k k
j
+ − ∈ = ≤
− −
for all x ∈{0,1}
k
(3.5)



Test T7 (Comparative Test for Multinomial Distributions)

For each i ∈{1, …, h} let the n-element sample w
i,1
, …, w
i,n
assume values from the set {0,1, …(s-
1)}. According to the null hypothesis, the multinomial distributions on which the individual samples
are based are identical. Furthermore, for t ∈{0, …, (s-1)} let f
i
[t]:=|{j: w
ij
= t}|, and let
p
t
:= (f
1
[t]+ … + f
h
[t])/(hn) be the relative frequency for the occurrence of t determined from the total
of all samples. Under the null hypothesis, the test variable
t
s t
t i
h i
np np t f
∑ ∑
− = =

) 1 ,...,( 0
2
,..., 1
/ ) ] [ ( is
approximately χ2-distributed with (h-1)(s-1) degrees of freedom. In the special case where h = s = 2
and at the significance level α = 0.001, the rejection limit is 15.13.


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 10 / 71

Test T8 (Entropy Test)

The entropy test is performed in accordance with Coron [4]. The bit sequence b
1
, ..., b
(Q+K)L
is
segmented into non-overlapping output words w
1
, …, w
Q+K
of length L. A
n
is the distance from w
n
to
its predecessor with the same value, and

A
n
= n if no i < n exist with w
n
=w
n-i

Or

A
n
= min {i | i ≥ 1, w
n
= w
n-i
} in all other cases

Test variable f: {0,1}
(Q+K)L
→ R is determined for the Coron test by


+
+

=
K Q
Q
n c
A g
k
S f
1
) (
1
) ( where


=
=
1
1
1
) 2 log(
1
) (
i
k
k
i g (3.6)

For a stationary binary-value random source with a finite memory, the expected value for test variable
f
c
is closely related to the entropy increase per L-bit block. Indeed, if the noise source is independent,
the two are equal. For ideal noise sources, a good approximation of the distribution of test variable f
c

is provided by a normal distribution with expected value µ
c
and variance (τ
c
)
2
:

K
A g Var
K L c
n
c c
)) ( (
) , ( = τ ,
K
L e
L d K L c
L
c
2 ). (
) ( ) , ( + = (3.7)

Where the parameters of the preceding equation 3.7 are given by following Table 3.2:

L Variance Var(g(A
n
)) d(L) e(L)
3 2.5769918 0.3313257 0.4381809
4 2.9191004 0.3516506 0.4050170
5 3.1291382 0.3660832 0.3856668
6 3.2547450 0.3758725 0.3743782
7 3.3282150 0.3822459 0.3678269
8 3.3704039 0.3862500 0.3640569
9 3.3942629 0.3886906 0.3619091
10 3.4075860 0.3901408 0.3606982
11 3.4149476 0.3909846 0.3600222
12 3.4189794 0.3914671 0.3596484
13 3.4211711 0.3917390 0.3594433
14 3.4223549 0.3918905 0.3593316
15 3.4229908 0.3919740 0.3592712
16 3.4233308 0.3920198 0.3592384
infinite 3.4237147 0.3920729 0.3592016
Table 3.2: Entropy Tests Parameters

For the case of L = 8, K = 256000 and Q = 256 the test passes if f
c
≥ 7.976.














True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 11 / 71

4. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter

4.1 Sigma-Delta Modulator Analog-to-Digital Converters

4.1.1 Advantages of Oversampling Converters

Oversampling A/D converters have become popular for high-resolution medium-to-low speed applications.
The major reasons for their popularity include the following characteristics: oversampling converters relax the
requirements placed on analogue circuitry at the expense of more complicated digital circuitry.

This trade-off becomes more desirable for modern submicron technologies with low power supplies where
complicated high-speed digital circuitry is more easily realized in less area, but the realization of high-resolution analog
circuitry is complicated by low power-supply voltages and poor transistor output impedance (caused by short-channel
effects).

With oversampling data converters, the analogue components have reduced requirements on matching
tolerances and amplifier gains. A second advantage of oversampling converters is that they simplify the requirements
placed on analogue anti-aliasing filters for A/D converters. Furthermore, a sample-and-hold is usually not required at
the input of an oversampling A/D converter. In this item, the basics of oversampling converters are discussed. Extra bits
of resolution can be extracted from converters that sample much faster than the Nyquist rate.

In addiction, this extra resolution can be obtained with lower oversampling rates by spectrally shaping the
quantization noise through the use of a feedback structure. The use of shaped quantization noise applied to
oversampling signals is commonly referred to as Sigma-Delta modulation. Simple first- and second- order Sigma-Delta
modulators are discussed, followed by a discussion of which structure of the second-order Sigma-delta modulator
should be used for the current development of a TRNG.

4.1.2 Oversampling without Noise Shaping

It is possible to show that extra dynamic range can be obtained by spreading the quantization noise power over
a larger frequency range, but only 3dB for every doubling of the sample rate. To obtain much higher dynamic-range
improvements as the sampling rate is increased, noise shaping through the use of feedback can be used and is discussed
on the following texts.

Quantization Noise Modelling

It is possible to model a quantizer as adding quantization error e(n), as show in Fig. 4.1. The output signal, y(n),
is equal to the closest quantized value of x(n). The quantization error is the difference between the input and output
values. This model is exact if one recognizes that the quantization noise error is not an independent signal but may be
strongly related to the input signal, x(n). However, this linear model becomes approximate when assumptions are made
about the statistical properties of e(n), such as e(n) being an independent white-noise signal. However, even though
approximate, it has been found that this models leads to a much simpler understanding of Sigma-Delta modulators and
with some exceptions is usually reasonably accurate.

White Noise Assumption

If x(n) is assumed uncorrelated and very active, e(n) can be approximated as an independent random number
uniformly distributed between ±∆/2, where ∆ equals the difference between two adjacent quantization levels. Thus, the
quantization noise power equals ∆
2
/12 [38] and is independent of the sampling frequency, f
s
. The spectral density of
e(n), Se(f), is white and all its power is within ±f
s
/2 as shown in Fig. 4.1.



Fig. 4.1: Quantization Noise Modelling


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 12 / 71

Where k
x
in Fig. 4.1 is calculated by:

12
) (
2
2
2 /
2 /
2
2 /
2 /
2

= = =
∫ ∫
+

+

s x
fs
fs
x
fs
fs
f k df k df f Se (4.1)

s
x
f
k
1
12
|
.
|

\
| ∆
= (4.2)
Oversampling without Noise Shaping

Oversampling occurs when the signals of interest are band-limited to f
0
yet the sample rate is f
s
, where f
s
>2f
0

(2f
0
being the Nyquist rate or, equivalently, the minimum sampling rate for signals band-limited to f
0
). We define the
oversampling ratio, OSR, as:

o
s
f
f
OSR
2
= (4.3)

After quantization, since the signals of interest are all below f
0
, y1(n) is filtered by H(f) to create the signal
y2(n), as shown in Fig. 4.2. This filter eliminates quantization noise greater than f
0
. Assuming the input signal is a
sinusoidal wave, its maximum peak value without clipping is 2
N
(∆/2). For this maximum sinusoidal wave, the signal
power, Ps, has a power equal to:

8
2
2 2
2
2 2
2
N N
Ps

=
|
|
.
|

\
| ∆
= (4.4)

The power of the input signal within y2(n) remains the same as before since it was assumed the signal’s
frequency content is below f
0
. However, noticing that the quantization noise is assumed to be a uniformly distributed
spectrum over –f
s
/2 till f
s
/2, the quantization noise power is reduced to:

|
.
|

\
|

=

= = =
∫ ∫

+

OSR f
f
df k df f H f Se Pe
s
f
f
x
fs
fs
1
12 12
2
) ( ) (
2 2
0
2
2 /
2 /
2
2
0
0
(4.5)

Therefore, doubling OSR decreases the quantization noise power by one-half or, equivalently, 3 dB. It is
possible also to calculate the maximum SNR (in dB) to be the ratio of the maximum sinusoidal power to the
quantization noise in the signal y2(n):
) log( 10 2
2
3
log 10 log 10 max
2
OSR
Pe
Ps
SNR
N
+
|
.
|

\
|
=
|
.
|

\
|
= (4.6)
Which is:

) log( 10 76 . 1 02 . 6 max OSR N SNR + + = (4.7)

The first term is the SNR due to the N-bit quantizer while the OSR term is the SNR enhancement obtained
from oversampling. Here we see that straight oversampling gives a SNR improvement of 3 dB/octave or, equivalently,
0.5 bits/octave. The reason for this SNR improvement through the use of oversampling is that when quantized samples
are averaged together, the signal portion adds linearly, whereas the noise portion adds as the square root of the sum of
the squares.

Fig. 4.2: Oversampling System without Noise Shaping
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 13 / 71

While oversampling improves the signal-to-noise ratio, it does not improve linearity [38]. However, with a
high enough sampling rate, the output from a 1-bit converter can be filtered to obtain a higher bit resolution. This
linearity is a result of a 1-bit A/D converter having only two output values and, since two points define a straight line,
no trimming or calibration is required. This inherent linearity is one of the major motivations for making use of
oversampling techniques with 1-bit A/D converters.


4.1.3 Oversampling with Noise Shaping


The system architecture of a Sigma-Delta oversampling A/D converter and its related signals are shown in Fig.
4.3. The first stage is a continuous-time anti-aliasing filter and is required to band-limit the input signal to frequencies
less than the difference between the sampling frequency f
s
minus the input signal Xin(t) bandwidth f
0
as depicted on the
block diagram of Fig. 4.4.

When the oversampling ratio is large, the anti-aliasing filter can often be quite simple. Following the anti-
aliasing filter, the continuous-time signal, Xc(t) (Fig. 4.4a), is sampled by a sample-an-hold circuit. The resulting signal,
Xsh(t) (Fig. 4.4b), is then processed by a Sigma-Delta modulator, which converts the analog signal into a noise-shaped
low-resolution digital signal Xdsm(n) (Fig. 4.4c). This 1-bit digital signal is assumed to be linearly related to the input
signal Xc(t) (Fig. 4.4a), although it includes a large amount of out-of-band quantization noise.

To remove this out-of-band quantization noise, the fourth block in the system is a digital decimation filter,
which converts the oversampled low-resolution digital signal into a high-resolution digital signal at a lower sampling
rate usually equal or a little higher than twice the frequency of the desired bandwidth of the input signal. The
decimation filter can be conceptually thought of as a low-pass filter, which generates Xlp(n) (Fig. 4.4d). Note that this
low-pass filter will also remove any higher-frequency signal content that was originally on the signal, Xc(t) (Fig. 4.4a),
and thus also acts as an anti-aliasing filter to limit signals to one-half the final output sampling rate, 2f
0
, as opposed to
the anti-aliasing filter at the input, which needed to only limit signals to frequencies less than f
s
/2.

Next the Xlp(n) (Fig. 4.4d) signal is resampled by a down sampler at 2f
0
generating finally the output signal
Xs(t) (Fig. 4.4e) by simply keeping samples at a submultiple of the oversampling rate and throwing away the rest.
Depicted on Fig4.4e is an oversampling rate of 6.

This decimation process does not result in any loss of information, since the bandwidth of the signal was
assumed to be f
0
. In other words, the signal Xlp(n) has redundant spectra information since it is an oversampled signal
where all of its spectral information lies well below π, and by throwing away samples, the spectral information is spread
over 0 and π.

It should be mentioned that in many realizations where the Sigma-Delta modulator is built using switched-
capacitor circuitry, a separate sample-and-hold is not required, as the continuous-time signal is inherently sampled by
the switches and input capacitors on the switched-capacitor Sigma-Delta modulator.

It is of interest to look at what element most strongly affects the linearity of this oversampling A/D system.
From the Sigma-Delta modulator, it should be noticed that an internal D/A converter is used whose output signal is
combined with the input signal. As a result, the overall linearity of this Sigma-Delta modulator converter depends
strongly on the linearity of its internal D/A converter especially in the case that the Sigma-Delta modulator uses multi
bit D/A converters. However on this current work there is used a 1-bit D/A converter which is always linear and will
not affect the linearity of the system as mentioned before.




Fig. 4.3: Block Diagram of a Low Pass Sigma-Delta oversampling A/D Converter
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 14 / 71




Fig. 4.4: Signals and Spectra of the Low Pass Sigma-Delta oversampled A/D Converter

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 15 / 71

Noise Shaped Sigma-Delta Modulator

A general noise-shaped Sigma-Delta modulator and its linear model are shown in Fig. 4.5. This arrangement is
known as an interpolative structure and is analogous to an amplifier realized using an operational amplifier and
feedback. In this analogy, the feedback reduces the effect of noise of the output stage of the operational amplifier in the
closed-loop amplifier’s output signal at low frequencies when the operational amplifier gain is high.

At high frequencies, when the operational amplifier’s gain is low, the noise is not reduced. Note that the
quantizer is shown for the general case where many output levels occur. While most present oversampling converters
make use of 1-bit quantizers due to reasons already discussed, there is certainly no reason to restrict ourselves to such
implementations.

From Fig. 4.5 it is possible two write to different transfer functions, one called the Signal Transfer Function
(STF) and the second defined as the Noise Transfer Function (NTF) which are given by following equations:

) ( 1
) (
) (
) (
) (
z H
z H
z U
z Y
z STF
+
= = (4.8)
) ( 1
1
) (
) (
) (
z H z E
z Y
z NFT
+
= = (4.9)


Fig. 4.5: A general Sigma-Delta Modulator (a) and its equivalent linear model (b)

From equations (4.8) and (4.9) it is possible to observe that the zeros of the noise transfer function are equal to
the poles of H(z). That means that, when H(z) goes to infinity, NTF(z) will go to zero. It is possible to write the output
signal as the combination of the input signal and the noise signal as follow:

) ( ) ( ) ( ) ( ) ( z E z NFT z U z STF z Y + = (4.10)

To shape the quantization noise in the case of a low-pass implementation, we choose H(z) such that its
magnitude is large from 0 to f
0
. With such a choice, the signal transfer function, SFT(z), will approximate unity over the
frequency band of interest very similarly to an opamp in a unity-gain feedback configuration. Furthermore, the noise
transfer function, NTF(z), will approximate zero over the same band.

Thus, the quantization noise is reduced over the frequency band of interest while the signal itself is largely
unaffected. The high-frequency noise is not reduced by the feedback as there is little loop gain at high frequencies.
However, additional post filtering can remove the out-of-band quantization noise with little effect on the desired signal.

First-Order Noise Shaping

The first-order noise shaping is realized when the noise transfer function, NTF(z), has a zero at dc (z = 1), so
that the quantization noise is high-pass filtered. Since the zeros of NTF(z) are equal to the poles of H(z), it is possible to
obtain first-order noise shaping by letting H(z) be a discrete-time integrator. Specifically:

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 16 / 71

1
1
) (

=
z
z H (4.11)

From a frequency domain view, the signal transfer function, STF(z), from equation (4.8) is:

1
1
1
1
1
1
) (
) (
) (

=

+

= = z
z
z
z U
z Y
z STF (4.12)

And the noise transfer function, NTF(z), from equation (4.9) is:

) 1 (
1
1
1
1
) (
) (
) (
1 −
− =

+
= = z
z
z U
z Y
z NTF (4.13)

The signal transfer function, STF(z), resumes into just a delay, while the noise transfer function, NTF(z), is a
discrete-time differentiator, equivalently, a high-pass filter. The magnitude of the noise transfer function is given by:

fs
f
j
fs
f
j
fs
f
j
fs
f
j
fs
f
j
fs
f
j
e j
fs
f
e j
j
e e
e f NFT e z
π π
π π
π π
π
− −


× ×
|
|
.
|

\
|
= × ×

= − = ⇒ → 2 sin 2
2
1 ) (
2 2
(4.14)

Taking the magnitude of both sides, it comes out the high-pass function:

|
|
.
|

\
|
=
s
f
f
f NFT
π
sin 2 ) ( (4.15)

The quantization noise power over the frequency band from 0 to f
0
is given using equations (4.1) and (4.15) by:

∫ ∫
− −
(
¸
(

¸

|
|
.
|

\
|
|
|
.
|

\
|
|
|
.
|

\
| ∆
= =
fo
fo s s
fo
fo
df
f
f
f
df f NFT f Se Pe
2
2
2
2
sin 2
1
12
) ( ) (
π
(4.16)

Making the approximation that f
0
<<f
s
, so that it is possible to approximate sin(πf/f
s
) to be πf/f
s
:

3
2 2
3
0
2 2
1
36
2
3 12
|
.
|

\
|

=
|
|
.
|

\
|
|
|
.
|

\
|
|
|
.
|

\
| ∆
=
OSR f
f
Pe
s
π π
(4.17)

Assuming the maximum signal power is the same as that obtained before in equation (4.4), the maximum SNR
for this case is given by:

(
¸
(

¸

+
|
.
|

\
|
= =
3
2
2
) (
3
log 10 2
2
3
log 10 log 10 max OSR
Pe
Ps
SNR
N
π
(4.18)

Or, equivalently:

) log( 30 17 . 5 76 . 1 02 . 6 max OSR N SNR + − + = (4.19)

It is possible to observe that doubling the OSR gives an SNR improvement for a first-order modulator of 9dB
or, equivalently, a gain of 1.5 bit/octave.



True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 17 / 71

Second-Order Noise Shaping

The modulator shown in Fig. 4.6 realizes second-order noise shaping. For this modulator the signal transfer
function using the same H(z) equation (4.11) is given by:

2
) (

= z z STF (4.20)

And the noise transfer function is given by:

2 1
) 1 ( ) (

− = z z NTF (4.21)


Fig. 4.6: Second-Order Sigma-Delta Modulator System

The magnitude of the noise transfer function can be shown to be given by:

2
sin 2 ) (
(
¸
(

¸

|
|
.
|

\
|
=
s
f
f
f NFT
π
(4.22)

This results in the quantization noise power over the frequency band of interest being given by:

5
4 2
1
60
|
.
|

\
|

=
OSR
Pe
π
(4.23)

Assuming the maximum signal power is that obtained in equation (4.4), the maximum SNR for this case is:

(
¸
(

¸

+
|
.
|

\
|
= =
5
4
2
) (
5
log 10 2
2
3
log 10 log 10 max OSR
Pe
Ps
SNR
N
π
(4.24)

Or, equivalently:

) log( 50 9 . 12 76 . 1 02 . 6 max OSR N SNR + − + = (4.25)

By doubling the OSR the SNR for a second-order modulator is improved by 15 dB or, equivalently, a gain of
2.5bit/octave. Fig. 4.7 depicts the different noise-shaping functions reported till now.


Fig. 4.7: Different Noise Shaping Transfer Functions
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 18 / 71

From Fig. 4.7 is it possible to observe that the second order system has a better noise-shaping function
compared to the first-order system on the bandwidth

on interest f
0
for the case of a Low Pass Sigma-Delta Modulator,
which turns into a better SNDR for the system as it can be compared between equations (4.19) and (4.25). Additionally,
the second order system is unconditionally stable in opposite to higher order systems which stability needs to be
certified and the behaviour of the real second order system approaches much more to the ideal system model compared
to the real first order system behaviour to the ideal system model [38 39]. For this reason as first solution approach for
this work further analysis will be done using a second-order Sigma-Delta modulator system which has also a better
controllable parameterization by choosing the appropriate circuit structure.

4.1.4 Sigma-Delta Modulator and Noise Modelling

The present work proposes a new method to generate random numbers in which a Sigma-Delta modulator
ADC is used to filter out the natural thermal noise present on the switched capacitors which further is processed by a
digital signal processing block to give out the random bit stream. The overall system view with Sigma-Delta Modulator
ADC for use as a TRNG is shown in Fig. 4.8.



Fig. 4.8: TRNG with a Sigma-Delta Modulator A/D Converter

Consider the general structure of a two stage Sigma-Delta modulator as shown in Fig. 4.9 with the noise due to
the 1
st
and 2
nd
stage switched-capacitor circuits (Et1(z) and Et2(z)) and the quantization noise from the 1-bit ADC
(Eq(z)) at the output included in the model.



Fig. 4.9: General structure of a Sigma-Delta Modulator with thermal and quantization noise modelling

The general expressions for the transfer functions of this model are then as follow:

) ( ) ( 2 1
) (
) (
) (
) (
) ( ) ( 2 1
) (
) ( 2
) (
) (
) ( ) ( 2 1
) (
) ( 1
) (
) (
) ( ) ( 2 1
1
) (
) (
) (
2
2
2 2
2
2
1
2
z H z H
z H
z U
z Y
z STF
z H z H
z H
z Et
z Y
z NTF
z H z H
z H
z Et
z Y
z NTF
z H z H z Eq
z Y
z NTF
Et
Et
Eq
+ +
= =
+ +
= =
+ +
= =
+ +
= =
(4.26)

Setting H(z) with an appropriate transfer function there are three possible Sigma-Delta modulators that can be
gotten from this structure which are given as follow:

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 19 / 71

4.2 Second Order Low Pass Sigma-Delta Modulator

For

1
1
1
) (



=
z
z
z H (4.27)

The general expressions for the transfer functions translate into:

2 1 1
2
2
1
2 1
) ( ), 1 ( ) ( , ) ( , ) 1 ( ) (
− − − − −
= − = = − = z z STF z z z NTF z z NTF z z NTF
Et Et Eq
(4.28)

Whose spectra when applying the transformation 1 = = T for e z
T jϖ
can be seen on following Fig. 4.10:
0 0.5 1
0
1
2
3
4
|STF(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Eq
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et1
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et2
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e

Fig. 4.10: Transfer functions frequency response for the 2nd Order Low Pass Sigma-Delta Modulator

Applying a sinusoidal signal with frequency equal to 2π/ratio/OSR/2 [rad/s] at the modulator’s input with ratio
set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the
following SNDR curve depicted on Fig. 4.11 is generated.

The left graphic on Fig. 4.11 presents the SNDR curves at the low frequency bandwidth of interest for different
oversampling rates from 4 to 256 calculated by applying different sinusoidal signal amplitudes from -100dB to 0dB into
the modulator’s circuit depicted of Fig. 4.9 using equation (4.27) for H(z).

The right graphic on Fig 4.11 shows the maximum SNDR obtained for the used oversampling rates. As it is
possible to see, for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will
be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements.

From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical
value calculated by equation (4.29) taken from reference [40] and the simulated value due to the fact that the equation
(4.29) does not take into account non-linearity’s on the real system, but still gives a reasonable approach to the
behaviour and quantification of the SNDR on the real system.

(
¸
(

¸
+
=
+ ) 1 2 (
) 2 (
) 1 2 (
2
3
log 10
L
l theoretica
OSR
L
L
SNR
π
, where L is the order of the system (4.29)

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 20 / 71

-100 -80 -60 -40 -20 0
0
20
40
60
80
100
120
Lowpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256
Vin [dB]
S
N
D
R

[
d
B
]
10
1
10
2
0
20
40
60
80
100
120
OSR
S
N
D
R

[
d
B
]
Lowpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256
Theoretical
Simulated

Fig. 4.11: SNDR for different OSR on a 2nd Order Low Pass Sigma-Delta Modulator

4.3 Fourth Order Band Pass Sigma-Delta Modulator

To get a Band Pass Sigma-Delta Modulator a discrete-time low-pass-to-band-pass transformation [3] can be
used:

1 1
1
) (
< < −
+
+ −
→ a
az
a z z
z , which gives:
2 1
2 1
2 1
) (
− −
− −
+ +
− −
=
z az
z az
z H (4.30)

Where the case a = 0 generates
2
z z − → . Negative a gives systems closer to DC and positive a gives
systems with passband closer to π. By choosing a = 0 the Band Pass Sigma-Delta Modulator is placed exactly over π/2
which simplifies further digital signal processing algorithms.

The general expressions for the transfer functions of this model are then as follow:

2 2 1
4 3 2 2
2 2 1
4 3 2 2 1
2
2 2 1
4 3 2 2
1
2 2 1
4 3 2 2 1
2 1
2
) (
2 1
3 ) 1 2 (
) (
2 1
2
) (
2 1
4 ) 4 2 ( 4 1
) (
− −
− − −
− −
− − − −
− −
− − −
− −
− − − −
+ +
+ +
=
+ +
− − + − −
=
+ +
+ +
=
+ +
+ + + + +
=
z a az
z az z a
z STF
z a az
z az z a az
z NTF
z a az
z az z a
z NTF
z a az
z az z a az
z NTF
Et
Et
Eq
(4.31)
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 21 / 71

Whose spectra when applying the transformation 1 = = T for e z
T jϖ
can be seen on following Fig. 4.12:
0 0.5 1
0
1
2
3
4
|STF(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Eq
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et1
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et2
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e


Fig. 4.12: Transfer functions frequency response for the 4th Order Band Pass Sigma-Delta Modulator

Applying a sinusoidal signal with frequency equal to ( (2.pi/4) + (2.pi/ratio/OSR/4) ) [rad/s] at the modulator’s
input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input
amplitudes the following SNDR curve depicted on Fig. 4.13 is generated:
-100 -80 -60 -40 -20 0
0
20
40
60
80
100
120
Bandpass 4th Order SDM, OSR = 4 8 16 32 64 128 256
Vin [dB]
S
N
D
R

[
d
B
]
10
1
10
2
0
20
40
60
80
100
120
OSR
S
N
D
R

[
d
B
]
Bandpass 4th Order SDM, OSR = 4 8 16 32 64 128 256
Theoretical
Simulated
Fig. 4.13: SNDR for different OSR on a 4th Order Band Pass Sigma-Delta Modulator
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 22 / 71


The left graphic on Fig. 4.13 presents the SNDR curves at the band pass frequency bandwidth of interest for
different oversampling rates from 4 to 256 calculated by applying different sinusoidal signal input amplitudes from -
100dB to 0dB into the modulator’s circuit depicted of Fig. 4.9 using the equation (4.30) for H(z) with parameter a set to
zero to get a bandwidth of interest with central frequency on π/2 [rads/s].

The right graphic on Fig 4.13 shows the maximum SNDR obtained for the different used oversampling rates.
As it is possible to see, again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which
further will be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements.

From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical
value calculated by equation (4.29) from [40] and the simulated value for the cases of oversampling rates lower than 64
whose reasons were already explained previously.


4.4 Second Order High Pass Sigma-Delta Modulator

For
1
1
1
) (


+

=
z
z
z H (4.32)

The general expressions for the transfer functions translate into:

2 1 1
2
2
1
2 1
) ( ), 1 ( ) ( , ) ( , ) 1 ( ) (
− − − − −
= + − = = + = z z STF z z z NTF z z NTF z z NTF
Et Et Eq
(4.33)

Whose spectra when applying the transformation 1 = = T for e z
T jϖ
can be seen on following Fig. 4.14:

0 0.5 1
0
1
2
3
4
|STF(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Eq
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et1
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e
0 0.5 1
0
1
2
3
4
|NTF
Et2
(z=e

)|
ω [x(2π) rad/s]
M
a
g
n
i
t
u
d
e


Fig. 4.14: Transfer functions frequency response for the 2nd Order High Pass Sigma-Delta Modulator


Applying a sinusoidal signal with frequency equal to ( pi - (2.pi/ratio/OSR/2) ) [rad/s] at the modulator’s input
with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input
amplitudes the following SNDR curve depicted on Fig. 4.15 is generated.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 23 / 71

The left graphic on Fig. 4.15 presents the SNDR curves at the high frequency bandwidth of interest for
different oversampling rates from 4 to 256 calculated by applying different sinusoidal input signal amplitudes from -
100dB to 0dB into the modulator’s circuit depicted of Fig. 4.9 using the equation (4.32) for H(z).

The right graphic on Fig 4.15 shows the maximum SNDR obtained for the different used oversampling rates.
As it is possible to see, again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which
further will be seeing in this work as enough to fulfil the AIS 31 Standard Statistical Tests requirements.

-100 -80 -60 -40 -20 0
0
20
40
60
80
100
120
Highpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256
Vin [dB]
S
N
D
R

[
d
B
]
10
1
10
2
0
20
40
60
80
100
120
OSR
S
N
D
R

[
d
B
]
Highpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256
Theoretical
Simulated

Fig. 4.15: SNDR for different OSR on a 2nd Order High Pass Sigma-Delta Modulator

In a first system structure analysis, if it is considered that the noise present in the circuit is just composed of thermal and
quantization noise then due to their uniform distributed spectral characteristics it would be possible to apply directly a
Low Pass Sigma-Delta Modulator and the appropriate digital signal processing filters to obtain a final noise spectrum at
the output composed by just thermal noise with the remaining quantization noise damped as much as possible with a
magnitude as low as possible compared to the thermal noise.

But in a real application the total noise of the circuit is the summation of the power of the theoretical loop
quantization noise, switched-capacitors thermal noise, digital signal processing truncation noise, operational amplifier
thermal noise and the intrinsic flicker noise [38 52 53 54 55 56 57 58 59 60 61] which yields to the use of Sigma-Delta
modulators that work in band frequencies where these remaining noise sources have less power magnitude than the
circuit’s thermal noise.

Taking into account the last observation then from the possible analyzed Sigma-Delta modulators the suitable
ones to this application would be the band pass or the high pass structures. From previous Figs. 4.13 and 4.15 it is
possible to observe that the band pass Sigma-Delta modulator has a slightly 6dB SNDR advantage over the high pass
one for oversampling rates greater than 64, but it should be remembered that the high pass system in this case is a 2
nd

order system compared to 4
th
order band pass system which requires more area, circuitry and power consumption on the
die.

The further analysis then should be to find out which of the two appointed structures: band pass or high pass
give out the best uniform distributed spectrum at the bandwidth of interest for later generation of the random output bit
stream considering the amount of chip area, complexity to build the circuit, power consumption, required digital-signal
processing filters and influence of the flicker noise at the output of each system.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 24 / 71

4.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures

4.5.1 Digital Signal-Processing Decimation Filter Structure

One usual approach [38] to digital signal process the output of a Sigma-Delta modulator system is shown in
Fig. 4.16.




Fig. 4.16: Usual Sigma-Delta Modulator Output Decimation Processing System


The TSinc Filter block removes much of the quantization noise such that the output can be downsampled later.
The TSinc Filter block is a cascade of L+1 (L is equal to order of the Sigma-Delta modulator) averaging filters with the
following transfer function TSinc(z) given on next equation (4.34) taken from [38] and shown in Fig. 4.17 for OSR =
256 and cases L = 2 and L = 4:

0
) 1 (
1 ) 1 (
2 4
1
,
1
1 1
) (
f
f
OSR and OSR M where
z
z
M
z TSinc
s
L
M
L
= =
|
|
.
|

\
|


=
+


+
(4.34)

0 0.2 0.4 0.6 0.8 1
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
ω [xπ rad/s]
M
a
g
n
i
t
u
d
e

[
d
B
]
TSinc Filter Transfer Functions
M = 64, L = 2
M = 64, L = 4

Fig. 4.17: TSinc transfer functions for OSR = 256 with L = 2 and L = 4


Note that the factor M in equation (4.34) is the integer ratio of f
s
to 8f
0
. It is important to notify that the impulse
response of this filter is finite, implying it is a FIR-type filter. In addiction, all of its impulse response coefficients are
symmetric, and thus it is also a linear-phase filter [38].
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 25 / 71

The reason for choosing to use L+1 of these averaging filters in cascade is similar to the argument that the
order of an analogue low-pass filter in an oversampling D/A converter should be higher than the order of the Sigma-
Delta modulator. Specifically, the slope of the attenuation for this low pass filter should be greater than the rising
quantization noise, so that the resulting noise falls off at a relatively low frequency. Otherwise, the noise would be the
integrated over a very large bandwidth usually causing excessive total noise [38].

The Half Band Filter is characterized by the constrains that their passband and stopband ripples are the same
(i.e., s p δ δ = ) and that the cutoff frequencies are symmetrical around π/2 such that:

π ω ω = +
s p
(4.35)

These properties, illustrated in Fig. 4.18, lead to a family of filters that exhibits odd symmetry around π/2 and
whose impulse response h(n) have zero values for all even values of n except n = 0. Therefore, these filters can be
implemented with half the number of multiplications than arbitrary choices of filter designs. They are appropriate for
sampling rate conversion ratios 2:1 and are useful for higher rate stages of multirate decimators or interpolators where
conversion ratios of 2 occurs in each stage.

Fig. 4.18: Design Criteria for each stage Half Band Filter

The previous Sigma-Delta modulator output decimation processing system depicted on Fig. 4.16 can be
simplified by transforming the last three filter stages into one like depicted on Fig. 4.19 for simulation simplification
purposes, where the two previous half filters were converted into a one fourth band filter including the TSinc
compensation transfer function.



Fig. 4.19: Simplified Sigma-Delta Modulator Output Decimation Processing System

The One Fourth Band Filter is characterized by the constrains that their passband and stopband ripples are the
same (i.e., s p δ δ = ) and that the cutoff frequencies are symmetrical around π/4 such that:

2
π
ω ω = +
s p
(4.36)
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 26 / 71


Fig. 4.20: Design Criteria for the One Fourth Band Filter

As mentioned the One Fourth Band Filter has included into its final transfer function the TSinc Compensation
function. On the following Fig. 4.21 it is possible to see the TSinc transfer function frequency response for the case of L
= 2 and OSR = 256, as well as the One Fourth Band Filter with TSinc Compensation and the final product of both filter
transfer functions at the output of the DSP decimation filter.
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
ω [xπ rad/s]
M
a
g
n
i
t
u
d
e

anti-TSinc One Fourth Band Filter
TSinc Filter (M = OSR/4)
Product

0.24 0.242 0.244 0.246 0.248 0.25 0.252 0.254 0.256 0.258 0.26
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
ω [xπ rad/s]
M
a
g
n
itu
d
e

[
d
B
]
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-350
-300
-250
-200
-150
-100
-50
0
50
ω [xπ rad/s]
M
a
g
n
itu
d
e

[
d
B
]
anti-TSinc One Fourth Band Filter
TSinc Filter (M = OSR/4)
Product
anti-TSinc One Fourth Band Filter
TSinc Filter (M = OSR/4)
Product

Fig. 4.21: Spectrums from the TSinc Filter (OSR = 256, L = 2), One Fourth Band Filter with TSinc Compensation and
the final product of the transfer functions.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 27 / 71

4.5.2 Thermal Noise, Quantization Noise and Oversampling Rate Analysis

With the previous simplified Sigma-Delta modulator output decimation processing system, two different
simulation structures depicted in Fig. 4.22a and Fig. 4.22b, one applying the high pass Sigma-Delta modulator and the
other one applying the band pass Sigma Delta modulator structures were built to find out which is the minimum
required oversampling rate that generates a Sigma-Delta modulator output’s spectrum flatten enough to further fulfill
the AIS 31 Standard Statistical Tests. It should be noticed as depicted on Fig. 4.22a and Fig. 4.22b that the outputs of
the Sigma-Delta modulators must be multiplied by an appropriate sinus signal to modulate the signal Y(z) down to the
low frequency baseband of work of the low pass decimation filter system.

Remembering that the proposed work uses the thermal noise to generate random numbers one possible source
comes from the switched-capacitors on the modulator circuit structure. From this physical phenomenon the total
thermal noise mean-squared value on a capacitor [48] is calculated as:


C
kT
V
rms noise
=
2
) (
, where k is the Boltzmann constant (1.38x10
-23
J/K), (4.37)
T is the temperature in Kelvin and
C is the capacitor size given in Fahrads.

It should be stated that this noise phenomenon for capacitors gives a fundamental limit on the minimum noise
level across a capacitor. Thus, to lower the noise level, either the temperature must be lowered or the capacitance value
must be increased. In this work instead, as it will be seen further, the thermal noise generated by the switched-capacitor
must be as high as possible, but there are some limitations on the capacitor’s size concerning their relation to the flicker
noise generated by the switching-transistors. For this actual analysis it will be considered just the thermal noise
generated by the switched-capacitors, later the switching-transistors’ flicker noise will be introduced on the model.



Fig. 4.22 Simulation Structures for the Band Pass and High Pass Sigma-Delta Modulator Systems


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 28 / 71

From equation (4.37) it is possible to conclude that the thermal noise scaling factor on Fig. 4.22 is equivalent
to the thermal noise generated by all the capacitors from the first stage of the switched-capacitor Sigma-Delta modulator
circuit structure calculated by:
Thermal Noise Scaling Factor
C
kT
= , (4.38)

It should be remembered from Figs. 4.12 and 4.14 and equations (4.31) and (4.33) for the transfer function
NTF
Et2
(z) that the thermal noise generated by the capacitors that belong to the second stage for these Sigma-Delta
modulator structures is shaped and is not appropriate to the generation of random numbers. On the other hand that
means that the integrating-capacitor’s size on the modulator’s first stage will have a greater influence on the final output
spectrum if the same integrating-capacitor size is used for both stages. If necessary the first stage switched-capacitors
could be scaled even more down to get a higher non-shaped thermal noise at the output of the modulator.

For these first simulations it was considered a temperature of 300 K and a capacitor of the size of 10fF. Later
on this work, these two parameters and specially the last one will be modified to analyze their influence on the
performance of the final electronic circuit design and over the AIS 31 Standard Statistical Tests results.

Performing some simulations with both Sigma-Delta modulator structures it is possible to see from the
decimated output spectra on Fig. 4.23 that oversampling rates greater or equal to 128 generate noise power spectrums
that start to approximate to a flatten white noise power spectrum desired for the this application. This happens because
at considerable higher oversampling rates the thermal noise turns dominant in the spectrum once the quantization noise
is damped and shaped by the Sigma-Delta modulator transfer function to lower magnitudes compared to the thermal
noise.

It is also possible to percept that the high pass Sigma-Delta modulator has a slightly advantage over the band
pass Sigma-Delta modulator once the first structure requires a lower oversampling rate to achieve a flat spectrum with a
lower order system transfer function which yields to two less operational amplifiers and less additional circuitry on a
real system.

To certify this advantage a further AIS 31 Standard Statistical Tests analysis over the generated output bit
stream needs to be performed, but before that there is still open which kind of digital bit stream generator is going to be
used after the decimation filter system and how the switching-transistors’ flicker noise influences the AIS 31 Standard
Statistical Tests results.

4
th
Order Band Pass Sigma-Delta Modulator
0 0.2 0.4 0.6 0.8 1
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
itu
d
e

[
d
B
]
OSR =64
Thermal Noise
Sigma-Delta Modulator Decimated Output
0 0.2 0.4 0.6 0.8 1
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
itu
d
e

[
d
B
]
OSR =128
Thermal Noise
Sigma-Delta Modulator Decimated Output
0 0.2 0.4 0.6 0.8 1
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
it
u
d
e

[
d
B
]
OSR =256
Thermal Noise
Sigma-Delta Modulator Decimated Output
2
nd
Order High Pass Sigma-Delta Modulator
0 0.2 0.4 0.6 0.8 1
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
itu
d
e

[
d
B
]
OSR =64
Thermal Noise
Sigma-Delta Modulator Decimated Output
0 0.2 0.4 0.6 0.8 1
-200
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
i
tu
d
e

[
d
B
]
OSR =128
Thermal Noise
Sigma-Delta Modulator Decimated Output

0 0.2 0.4 0.6 0.8 1
-200
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
ω [xπ rad/s]
M
a
g
n
i
tu
d
e

[
d
B
]
OSR =256
Thermal Noise
Sigma-Delta Modulator Decimated Output


Fig. 4.22: Output’s spectra for different oversampling rates using a 4
th
order Band Pass Sigma-Delta Modulator and a
2
nd
order High Pass Sigma-Delta Modulator

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 29 / 71

4.5.3 Choice of the Digital Bit Stream Generator System and Analysis

To translate the decimated output signal of the Sigma-Delta modulator ADC into a digital bit stream two
digital post-processing system approaches were taken. The first was applying a simple “Zero-Cross Comparator”
algorithm to generate the output bit states one and zero, which gives a digital output stream Bit Rate equal to:


0
2 f BitRate
Compator Cross Zero
=
− −
(4.38)

The second approach was using a here named “Gauss Distribution Comparator” algorithm which translates one
decimated output sample value into one or more bits depending on how many areas the Gauss distribution of the
decimated output signal was divided. In this case the digital output stream Bit Rate would be given by the following
equation:


*
2 0
2 , ) ( log 2
+ − −
Ν ∈ = = = i c where c N for N f BitRate
i
Comparator Distrib Gauss
(4.39)

Fig. 4.24 shows the definition of parameter N as the number of areas by which the Gauss distribution of the
decimation filter output in subdivided, as well as how the areas are calculated and defined under the same distribution.

The coefficients c
i
are calculated through the Error Gauss Distribution Area Function [73] defined by:



=
x
t
dt e erf
0
2 2
π
(4.40)

It should be noticed that equation (4.40) is twice the integral of the Gauss Distribution function for variation
σ(x) = ½ and mean value Ē{x} = 0.

By applying just thermal noise at the input of the system depicted on Fig. 4.22 with a oversampling rate set to
256, performing a first set of simulations with a band pass and a second set with a high pass Sigma-Delta modulator
ADC using in both the proposed “Gauss Distribution Comparator” algorithm at the output of the decimation filter it has
shown that for values of N set from 4 to 262144 all AIS 31 Statistical Standard Tests where fulfilled certifying until this
maximum value that the “Gauss Distribution Comparator” algorithm works. That means also that for this upper N limit
it would be possible to generate 18 random bits for one decimated output value from the Sigma-Delta modulator ADC.

Greater N values could not be simulated due to the extensive amount of time and computation capacity that it
would take which is beyond the purpose of this work and was left for future studies. Nevertheless this first maximum N
value limit shows that these 256 times oversampled with either high pass or band pass Sigma-Delta modulator ADC
structures achieve a resolution greater or equal than 18 bits which mainly comes from its high order decimation filter
output systems and enables the lost bit rate due to oversampling method to be recovered by applying this algorithm
without loss of entropy.

Additionally analysis would be required to measure the upper N value limit, but for simplification purposes
and due to limited amount of time and computing processing capacity further simulations used the “Zero-Cross
Comparator” algorithm to generate the digital random bit stream output.

Fig. 4.24: Areas definition on the Gauss Distribution Function for σ = ½ and Ē{x} = 0 of the output signal from the
DSP Decimation Filter for the cases of N equal to 4 and 8.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 30 / 71

4.5.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests

The flicker noise is not a totally modelled phenomenon nonetheless one main physical behaviour that could
describe it happens in the interface between the gate oxide and the silicon substrate in a MOSFET. Since the silicon
crystal reaches an end at this interface, many dangling bonds appear, giving rise to extra energy states as shown of Fig.
4.25. As charge carriers move at the interface, some are randomly trapped and later released by such energy states,
introducing flicker noise in the drain current. In addition to trapping, several other mechanisms are believed to generate
flicker noise [4].


Fig. 4.25 Dangling Bonds at the Oxide-Silicon Interface Fig. 4.26 Flicker Noise Spectrum

Unlike thermal noise, the average power of flicker noise can not be predicted easily. Depending on the
cleanness of the oxide-silicon interface, flicker noise may assume considerably different values and as such varies from
one CMOS technology to another. The flicker noise is more easily modelled as a voltage source in series with the
transistor’s gate [48] and roughly given by the power spectral density equation (4.42):

( )
f
K
f WL C
K
V
flic
ox
tech
n
1 1
2
ker
2
=
|
|
.
|

\
|
= (4.42)

Where K
tech
is a process-dependent constant of the order of 10
-27
V
2
F for 90nm technology [52 53 54 55 56 57
58 59 60 61], C
ox
it the capacitance per unit area, W is the width and L the length of the device. As shown in Fig. 4.26
the noise spectral density is inversely proportional to the frequency. For this reason, flicker noise is also called 1/f noise.
Equation (4.42) is only an approximation and in reality, the Flicker noise equation is somewhat more complex [4]. The
inverse dependence of equation (4.42) on the area of the transistor WL suggests that to decrease flicker noise, the device
area must be increased. It is also believed that PMOS devices exhibit less Flicker noise than NMOS transistors because
the former carry the holes in a buried channel, i.e., at some distance from oxide-silicon interface. Nonetheless, this
difference between PMOS and NMOS transistors is not consistently observed [48].

As shown in Fig 4.26 the Flicker noise has a stronger influence over the low and medium band frequencies
which suggests that the high pass Sigma-Delta modulator would return better AIS Standard Statistical Tests results
compared to the band pass Sigma Delta modulator structure.

To analyze the Flicker noise influence over the Sigma-Delta modulator structure and over the results of AIS 31
Standard Statistical Tests, a flicker filter (-10dB/dec) transfer function was designed and added to the simulation system
model depicted on Fig. 4.27 followed by an adjustable Flicker Noise Scaling Factor (K
flicker
) parameter that for analyses
purposes will be related to a new defined α parameter that represents the ratio between the frequency at which the
flicker noise density spectrum magnitude is equal to the thermal noise density spectrum magnitude and half of the
desired system sampling frequency. By multiplying half of the system sampling frequency f
s
by the α parameter one
determines the Flicker Noise Corner Frequency of the system. The α and K
flicker
parameters are defined on equations
(4.42) and (4.43) and graphically shown on Fig. 4.28. For the case in which the thermal and flicker noise densities
spectra have the same magnitude for a given α value, as exemplified on Fig. 4.28, it comes to:

1 0
2
2
1
ker ker
ker
2
ker
< < = ⇒ = ⇒ = α α α
C
kT
K
f
f
f
K
f
C
kT
flic
s
Corner
Flic
Corner
Flic
flic
s
(4.43)

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 31 / 71




Fig. 4.27 Modified Simulation System Structure for the Band Pass and High Pass Sigma-Delta Modulators including
the Thermal & Flicker Noise Sources



Fig. 4.28 Parameter α definition and concept of Flicker Noise Corner Frequency

From equations (4.42) and (4.43) it is possible to define a relation between the area of the transistors and the
size of the switched-capacitors in use as follow:

1 0
2
ker
< <
|
.
|

\
|
|
|
.
|

\
|
= ⇒ = α
α
ε ε
C
kT
t
K
WL
WL C
K
K
ox
r o
tech
ox
tech
flic
(4.44)
Where:
- K
tech
process-dependent constant on the order of 10
-27
V
2
F for the 90nm technology,
- ε
o
permeability constant equal to 8.85x10
-12
F/m,
- ε
r
relative permeability of the material in this 90nm technology equal to 3.9,
- t
ox
thickness of the gate dioxide to the channel of the transistor for 90nm technology equal to 1.3nm.

From equation (4.43) for a given parameter α and integrating-capacitor C values it is possible to calculate the
K
flicker
constant which is defined as the Flicker Noise Scaling Factor on the model of Fig. 4.27 and from there on using
equation (4.44) calculate the maximum area of the switching transistors.

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Using for simulation time processing reduction the previous defined “Zero-Cross Comparator” algorithm and
generating some sets of 6 million output bit streams from the high pass Sigma-Delta modulator ADC system for
different α parameter and integrating-capacitor C values it is possible to find out which are the switched-capacitor
values that fulfil the complete set of AIS 31 Standard Statistical Tests as well as determines the estimated optimal area
of the transistors as shown on Table 4.1 and Fig. 4.30.

Parameter α
C [fF] 0.005 0.002 0.001 0.0005 0.0002 0.0001
100 0 0 0 0 0 0
80 0 0 0 1 1 1
60 0 0 1 1 1 1
40 0 0 1 1 1 1
20 0 0 1 1 1 1

Table 4.1: Fulfilled or not fulfilled complete set of AIS 31 Standard Statistical Tests for different Flicker Noise Corner
Frequency α parameter and integrating-capacitor values using the High Pass Sigma-Delta Modulator structure with a
oversampling rate of 256 and system sampling frequency f
s
of 25MHz


From Table 4.1 and equation (4.44) it is possible to find out for different α parameters values the transistor
areas for the technology of 90nm as shown in Fig. 4.30 and to calculate the total noise power density spectrum
generated by the flicker and thermal noises as depicted on Fig. 4.29 in the case a integrating-capacitor of 25fF is used
on the switched-capacitor circuit.



Fig. 4.29 Total [black], Thermal [blue] and Flicker [red] Noise Power Density spectra for a capacitor of 25fF and
different Flicker Noise Corner Frequency α parameter values.


From the previous Table 4.1 and Fig. 4.29 it is also possible to predict that the flicker noise will have a much
higher influence on the final AIS31 Standard Statistical Tests for the band pass Sigma-Delta modulator that works in a
frequency range two times lower than that for the high pass Sigma-Delta modulator structure. Beside this characteristic
the band pass Sigma-Delta modulator would use twice operational amplifiers to get a 4
th
order system which yields to
more area, power consumption, flicker noise, time and complexity to design the overall circuit.
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Taking into account these observations and from the previous analysis the work is going to be conducted
studying the high pass Sigma-Delta modulator topology structure, its design and circuit implementation.

10
-4
10
-3
10
-2
0
100
200
300
400
500
600
700
800
900
1000
W
L

/

(
W
L

α
=
0
.
1
)
α
Normalized Transistor Area versus α parameter | C = 25fF

Fig. 4.30 Normalized Transistors’ Area on 90nm technology for different Flicker Noise Corner Frequency α parameter
values using a capacitor of 25fF


Table 4.2 shows the results of AIS 31 Standard Statistical Tests ran over 6 million random bits generated by
the high pass Sigma-Delta modulator with integrating capacitor set to 25fF and Flicker Noise Corner Frequency
parameter α set to 0.001 using the third order TSinc FIR filter together with the One Fourth Band with TSinc
compensation FIR Filter and “Zero-Cross Comparator” algorithm on the system simulation model on Fig. 4.28. As it is
possible to see all tests are fulfilled for this case.

AIS 31 Standard Statistical Tests Result Limits
Test 0 (Disjointness Test) Passed Passed or not Passed
Test 1 (Monobit Test) Monobit = 9986 9654 < Monobit < 10346
Test 2 (Pocker Test) Χ = 4.498 1.03 < Χ < 57.4
Test 3 (Run Test) All passed Limits section 3.7 Test 3
Test 4 (Long Run Test) Long Run = 1 Long Run < 34
Test 5 (Autocorrelation) MaxCorr(4075) = 2572 2326 < MaxCorr < 2674
Test 6a (Empirical distribution for 1 disjoint sub-sequences) Χ = 0.001 Χ < 0.025
Test 6b (Emprcl distb 2 disj s-s) Χ = 0.005 Χ < 0.020
Test 7a (Emprcl dstrb 4 disj s-s) Χ
2
(1) = 5.264 Χ
2
(1) < 15.3
Test 7a (Emprcl dstrb 4 disj s-s) Χ
2
(2) = 0.986 Χ
2
(2) < 15.3
Test 7b (Emprcl dstrb 8 disj s-s) Χ
2
(1) = 0.648 Χ
2
(1) < 15.3
Test 7b (Emprcl dstrb 8 disj s-s) Χ
2
(2) = 0.269 Χ
2
(2) < 15.3
Test 7b (Emprcl dstrb 8 disj s-s) Χ
2
(3) = 6.228 Χ
2
(3) < 15.3
Test 7b (Emprcl dstrb 8 disj s-s) Χ
2
(4) = 0.925 Χ
2
(4) < 15.3
Test 8 (Strong Entropy) SE = 369.339 SE > 7.976

Table 4.2: Fulfilment of all AIS 31 Standard Statistical Tests for α = 0.001 and integrating capacitor set to 25fF on the
High Pass Sigma-Delta Modulator with a oversampling rate of 256 and system sampling frequency f
s
of 25MHz

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5. High Pass Sigma-Delta Modulator System Level Design

5.1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization

The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure

From the previous analysis on section 4.4 the basic transfer function cell to implement a High Pass Sigma-
Delta Modulator is given by:

1
1
1
) (


+

=
z
z
z H (5.1)

From [38] the following circuit on Fig. 5.1 gives a similar transfer function for the Low Pass Sigma-Delta
Modulator structure that needs to be modified on its pole for the new implementation as a High Pass version:





Fig. 5.1: Basic Low Pass Sigma-Delta Modulator Cell Circuit structure


The actual Basic Low Pass Sigma-Delta Cell transfer function is given by:

|
.
|

\
|

|
.
|

\
|
− =


1
1
1
1
2
1
) (
) (
z
z
C
C
z Vi
z Vo
(5.2)

For C1 = C2 this system can be modelled as depicted on Fig. 5.2:





Fig 5.2: Basic Low Pass Sigma-Delta Modulator Cell Model


Which has the transfer function given by:

1
1
1 ) (
) (




=
z
z
z U
z Y
(5.3)

If instead of taking the positive feedback from the output someone takes the negative one, the new system will
have a high pass behaviour as given by equation (5.4) and modeled by Fig. 5.3.

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1
1
1 ) (
) (


+

=
z
z
z U
z Y
(5.4)

Then rewriting the equation (5.2) to:

) ( 1 ) ( 2 ) ( 2 ) ( 1 ) ( 2 ) ( 2
1 1
T nT Vi C T nT Vo C nT Vo C z z Vi C z z Vo C z Vo C − − = − − ⇒ − = −
− −


And taking the negative value of Vo(nT-T) from the capacitor C2 the final expression would then be:

1 1
) ( 1 ) ( 2 ) ( 2 ) ( 1 ) ( 2 ) ( 2
− −
− = + ⇒ − − = − + z z Vi C z z Vo C z Vo C T nT Vi C T nT Vo C nT Vo C



Fig 5.3: Basic high pass Sigma-Delta modulator cell model

That would yield to the desired expression on equation 5.1 when C1 = C2. The idea is then to design a circuit
which takes the negative value of the last integration stored on the capacitor C2. One possible structure that can execute
such action using known circuits from [38] is given on Fig. 5.5 as well as the related circuit analysis and transfer
function given on Fig 5.4 and equation (5.5).




Fig. 5.4: Basic High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analyze
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Fig. 5.5: Basic High Pass Sigma-Delta Modulator Cell Structure

From Fig. 5.5 the following difference-equation system analysis can be done:

) ( 4 )
2
( 4
) ( 2 )
2
( 2
4 3 1
)
2
( 4 ( ) ( 1 )
2
( 2
nT Vo C
T
nT Vo C
T nT Vo C
T
nT Vo C
C C C
T
nT Vo C nT Vi C
T
nT Vo C
− = − −
+ = +
= =
− − + + = +


Thus:

) ( 1 ) 1 )( ( 2
)) ( 4 ( ) ( 1 ) ( 2
nT Vi C z z Vo C
nT Vo C nT Vi C T nT Vo C
= +
− + + = +


This results into the following transfer function for the basic high pass cell given by:

|
.
|

\
|
+
=


1
1
1
1
2
1
) (
) (
z
z
C
C
z Vi
z Vo
(5.5)

The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit

Using the classic basic cell from Fig. 5.5 the following switched-capacitor circuit can be designed to
implement a 2
nd
order high pass Sigma-Delta modulator circuit as shown in Fig. 5.7. The same circuit has the equivalent
model as the structure depicted on Fig. 5.6.



Fig. 5.6 The classic 2
nd
Order High Pass Sigma-Delta Modulator Model.
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It should be noticed that the equation (5.5) does not have a signal phase shift of 180˚ from the input to the
output which will result on the required wiring cross connection from the first to the second stages on the Sigma-Delta
modulator circuit on Fig. 5.7 as well as the crossing of the input stage on the modulator which in this case is not
necessary and independent of the input signal polarization.


Another observation that should be taken into account is that on the same switched-circuit both operational
amplifiers and comparator are ideal models with high gain, infinite bandwidth and high slew rate characteristics for
execution of first circuit simulations.


Through simulation of the discrete-time model on Fig. 5.6 and simulation of the switching-capacitor circuit
model on Fig. 5.7 it is possible to validate the circuit and its functionality as shown in Fig. 5.8 where on the upper
graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view
of the high pass output baseband spectrum are shown.


As it can be seen on Fig. 5.7 this switching-circuit requires at least 22 switched-capacitors and enhanced
current driving operational amplifier outputs, especially the first stage which outputs have 3 capacitors to drive per
output.


This circuit needs four distinguished clock signals to work compared to a classical 2
nd
second order low pass
Sigma-Delta modulator version which has just two clocks.


There are visible some possible modifications that could reduce the number of the switching gates on the
circuit, but looking carefully again to some of the previous difference-equations a reduced and simplified version of the
circuit can be designed.



Fig. 5.7 Classic 2
nd
Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-150
-100
-50
0
Spectral Comparation Classic 2nd Ord High Pass SDM | OSR = 256
ω [xπ rad/s]
A
m
p
l
i
t
u
d
e

[
d
B
]
0.993 0.994 0.995 0.996 0.997 0.998 0.999 1
-150
-100
-50
0
Spectral Comparation at the Baseband Classic 2nd Ord High Pass SDM | OSR = 256
ω [xπ rad/s]
A
m
p
l
i
t
u
d
e

[
d
B
]
Discrete-Time System Model
Switched-Capacitor Circuit

Fig. 5.8 Spectral simulation results for the classic 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor
circuit with a differential sinusoidal input signal of 0.25Vpp (-12dB) at the frequency of (0.998π) rads/s and OSR = 256.




The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure



Another possible circuit structure that realizes the same basic cell transfer function from equation (5.1) with
less transistors and capacitors is depicted in Fig. 5.9 and analyzed on Fig. 5.10:






Fig. 5.9: Reduced basic High Pass Sigma-Delta Modulator Cell Structure




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Fig. 5.10: Reduced High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analysis


From the analysis on Fig 5.10 the resulting transfer function for this basic structure is:


|
.
|

\
|
+
− =


1
1
1
1
2
1
) (
) (
z
z
C
C
z Vi
z Vo
(5.4)


With the same analysis used on the first structure on Fig. 5.10 it is also possible to derive more two other
structures as given in Fig. 5.11 as well as their corresponding transfer functions:



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Fig. 5.11: Reduced basic High Pass Sigma-Delta Modulator Cell Structures with different transfer functions




The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit



Using the reduced basic cell structure from Fig. 5.11a the following switched-capacitor circuit can be designed
to implement a 2
nd
order high pass Sigma-Delta modulator circuit as shown in Fig. 5.12. The same circuit has the
equivalent model as the structure depicted on Fig. 5.6. Through simulation of both models it is possible to check the
validation of the circuit and its functionality as shown if Fig. 5.13.




Fig. 5.12 Reduced 2
nd
Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-150
-100
-50
0
Spectral Comparation Reduced 2nd Ord High Pass SDM | OSR = 256
ω [xπ rad/s]
A
m
p
l
i
t
u
d
e

[
d
B
]
0.993 0.994 0.995 0.996 0.997 0.998 0.999 1
-150
-100
-50
0
Spectral Comparation at the Baseband Reduced 2nd Ord High Pass SDM | OSR = 256
ω [xπ rad/s]
A
m
p
l
i
t
u
d
e

[
d
B
]
Discrete-Time System Model
Switched-Capacitor Circuit

Fig. 5.13 Spectral simulation results for the reduced 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor
Circuit with a differential sinus input signal of 0.25Vpp (-12dB) at the frequency of (0.998π) rads/s with OSR = 256.

Through simulation of the discrete-time model on Fig. 5.6 and simulation of the switched-capacitor circuit
model on Fig. 5.12 it is possible to validate the circuit and its functionality as shown in Fig. 5.13 where on the upper
graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view
of the high pass output baseband spectrum are shown.

As it can be seen on Fig. 5.12 this switching-circuit requires 50% less switched-capacitors compared to the
previous version and operational amplifier’s outputs with less driving strength. The only drawback is that it still
requires four distinguished clock signals to work compared to a classical 2nd order low pass Sigma-Delta modulator
version which has just two clocks, required is this new structure due to the polarization switching behaviour on the
integrating capacitors to get a high pass transfer function of the reduced basic cells.

From both analyzed switching-circuits it is evident the advantage of the reduced version which is going to be
used at analysis for the determination on further components requirements. However, it should be noticed that one
possible disadvantage of this reduced structure could arise from the parasitic capacitance on the switched integrating-
capacitor which is not built as in the conventional layout structure as on the classic structure. This circuit characteristic
will be analyzed more carefully on the coming section.

6. Requirements for the Different Components of the Analog Circuit System

6.1 Switched-Capacitor Circuit Requirements

Differential Sinusoidal Input Signal Amplitude Influence Analysis

One factor that should be taken into account is the need or not for a differential sinusoidal input signal at the
frequency of π/2 rad/s for a better shape on the final output spectrum and its influence on the SNDR curves for different
amplitude values. For this purpose, through some simulations using the equivalent discrete-time system model from Fig.
5.6, the following SNDR curve depicted on Fig. 6.1 was calculated.

Applying two differential sinusoidal signals at the input of the circuit, one signal named Vin
π/2
with a frequency
exactly on π/2 rad/s and with differential amplitude changing from 0.00Vpp to 1.00Vpp and the other one called
Vin
0.998π
with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the
SNDR for this last sinus signal at the output results on the following left SNDR curves depicted on Fig. 6.1 for a
oversampling rate of 256.
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As it is possible to see on the right SNDR versus Vin
π/2
curve on Fig. 6.1, there is no influence of Vin
π/2,
the
differential sinusoidal input signal amplitude at the frequency of π/2 rad/s, on the final SNDR curve, which suggests
that the system input path could be probably taken out from the final circuit topology depicted on Fig. 5.12. However,
due to initial conditions on the circuit structure on Fig. 5.12 this input path should be implemented to start-up the
Sigma-Delta modulator circuit at initial power on conditions and to result on a better spectrum shape and decorrelation
of the output of the Sigma-Delta modulator ADC.
-50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNDR HPSDM 2nd Order | OSR =256 | Diff Vin
π/2

Vin
0.998π
[dB]
S
N
D
R

[
d
B
]
0 0.2 0.4 0.6 0.8 1
0
20
40
60
80
100
120
Vin
π/2
[V] | Vin
0.998π
= -6 dB
S
N
D
R

[
d
B
]
SNDR HPSDM 2nd Order | OSR =256 | Diff Vin
π/2

0.00 Vpp
0.25 Vpp
0.50 Vpp
0.75 Vpp
1.00 Vpp

Fig. 6.1 SNDR for different amplitudes of the differential sinus input signal at the frequency of π/2 for the 2
nd
Order
High Pass Sigma-Delta Modulator Circuit

Switched-Capacitor Coefficients Scaling Analysis

Concerning the power source and reference voltages on which the switched-capacitor circuit will be
implemented later, a scaling factor should be applied over the capacitor values to limit the internal operational amplifier
output signals to the reference voltages of the circuit. To find out the scaling factors that should be used the following
2
nd
order high pass Sigma-Delta modulator system shown in Fig. 6.2 can be modeled to later apply the scaling factors
over the capacitors on the switched-capacitor circuit for the high pass Sigma-Delta modulator circuit from Fig. 5.12.



Fig. 6.2 System model of 2
nd
Order High Pass Sigma-Delta Modulator with scaling factors



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Defining two parameters γ and β it is possible to control the values for the k parameters of the given system
through following relations:

K11 = γ k12 = 1 k13 = γ k21 = β / γ k22 = 1 k23 = β (6.1)

By setting γ = 1/3.5 and β = 1/6.5 and applying a differential sinus signal input of -3dB at the frequency 0.998π
rad/s the signals o1 and o2 are scaled as depicted on Fig. 6.3:
0 1 2 3 4 5 6 7 8 9 10
x 10
5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Scaled HPSDM 2nd Ord - o1 Signal
M
a
g
n
i
t
u
d
e

[
V
]
[s]
0 1 2 3 4 5 6 7 8 9 10
x 10
5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Scaled HPSDM 2nd Ord - o2 Signal
M
a
g
n
i
t
u
d
e

[
V
]
[s]

Fig: 6.3 Signals o1 and o2 from 2
nd
Order High Pass Sigma-Delta Modulator of Fig. 6.5

From Fig. 6.3 it is possible to see that the signals o1 and o2 are within the reference voltages Vref+ = +1.00V
and Vref- = -1.00 V in the model. Just to notice, these scaling factor values will be applied over the capacitor values
from the switched-capacitor circuit from Fig. 5.12 later on the transistor circuit level design. In addiction to that, it
should be reinforced that for this scaling method the parameters k12 and k22 do not need to be scaled and remain
unchanged as well as their corresponding integrating-capacitors on the circuit on Fig. 5.12.

Switched-Capacitor Parasitic Capacitance Analysis

Contrary to classical switched-capacitor circuits where sensitive capacitor nodes are placed always on the top
plate, resulting into low parasites the proposed reduced modulator structure uses integrating-capacitors with changing
polarity where this is not possible. Due to this fact and due to the existence of intrinsic parasitic capacitances from the
switched-capacitor top and bottom plates a set of simulations including parasitic capacitances in the circuit structure of
Fig. 6.4 were performed to check the influences and quantify the minimum tolerance required to achieve a SNDR curve
as close as possible to the theoretical SNDR curve of the high pass Sigma-Delta modulator on Fig. 4.15.

The top parasitic capacitor was disconsidered, due to its little parasitic influence on the capacitor value and the
bottom parasitic capacitor was scaled to 0.3%, 0.5%, 0.7%, 1%, 2% and 5% of the correspondent capacitor value.
Applying two differential sinusoidal input signals, one named Vin
π/2
at the frequency of π/2 rad/s with differential
amplitude of 0.5Vpp and the second differential sinusoidal input signal called Vin0.998
π
at the frequency of 0.998π
rad/s with differential amplitude ranging from -48 to -3 dB the following left SNDR curves shown on Fig. 6.5 were
calculate for these different parasitic scaling factors for an OSR equal to 256.

From the right SNDR versus Bottom Parasitic Capacitor curve on Fig. 6.5 the bottom parasitic capacitance
should then have a parasitic value lower than 1% to achieve the desired theoretical SNDR curve from Fig. 4.15. From
previous works and layout methodologies it is possible to achieve such tolerance values [62 63 64 65 66].
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 44 / 71





Fig. 6.4 2
nd
Order High Pass Sigma-Delta Modulator switching-capacitor circuit including the top and bottom parasitic
capacitances from the switched-capacitor plates


-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics
Vin
0.998π
[dB] | Vin
π/2
= 0.5V
S
N
D
R

[
d
B
]
5.0%
2.0%
1.0%
0.7%
0.5%
0.3%
0 1 2 3 4 5
0
20
40
60
80
100
120
S
N
D
R

[
d
B
]
Bottom Cap Parasitic [%] | Vin
0.998π
= -6dB
SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics

Fig. 6.5 SNDR for different bottom capacitor parasitic tolerances on the 2
nd
High Pass Sigma-Delta Modulator Circuit

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6.2 Operational Amplifier Requirements

Operational Amplifier Gain Analysis

With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its
minimum gain must be analyzed to achieve a SNDR curve close to the theoretical one from Fig. 4.15. Implementing the
circuit shown in Fig. 5.12 and modeling the operational amplifier like depicted on Fig. 6.6 a set of circuit simulations
and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig. 6.7. Note
that for this first operational amplifier’s characteristic estimation the frequency bandwidth is not modeled and is
considered infinite.



Fig. 6.6 Operational amplifier with gain modelling for PSPICE simulations
-50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNDR Simulink Scaled HPSDM 2nd Ord | Vin
π/2
= 0.5Vpp | Diff OpAmp Gain
Vin
0.998π
[dB]
S
N
D
R

[
d
B
]
0 10 20 30 40 50 60 70 80
0
20
40
60
80
100
120
S
N
D
R

[
d
B
]
Gain [dB] | Vin
0.998π
= -6 dB
SNDR Simulink Scaled HPSDM 2nd Ord | Vin
π/2
= 0.5Vpp | Diff OpAmp Gain
G = 74dB
G = 66dB
G = 60dB
G = 54dB
G = 46dB
G = 40dB
G = 34dB
G = 26dB
G = 20dB
G = 14dB
G = 6dB
G = 0dB

Fig. 6.7: SNDR for different operational amplifier gains on the 2
nd
Order High Pass Sigma-Delta Modulator Circuit

By giving different gain values and applying two differential sinusoidal signals at the input of the circuit, one
named Vin
π/2
with a frequency exactly on π/2 rad/s and with differential amplitude 0.5V and another one called Vin
0.998π
with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for
this last sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig. 6.8 for an
oversampling rate of 256.

As it possible to see from the right SNDR versus Gain curve on Fig. 6.8 the minimum required operational
amplifier gain should be greater than 40dB.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 46 / 71

Operational Amplifier Input Capacitance Analysis


With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its
maximum input capacitance requirements must be analyzed to achieve a SNDR curve close to the theoretical one from
Fig. 4.15.


Implementing the circuit shown in Fig. 5.12, scaling the input and feedback circuit paths with the
corresponding scaling factors calculated on the previous section 6.2 and connecting to each of the two operational
amplifier’s signal inputs a capacitor, a set of circuit simulations with different values for this input capacitor and further
SNDR calculations where performed resulting on the following SNDR curves given on Fig. 6.8. Note that for the
estimation of the operational amplifier input capacitance its gain was set to 40dB from the minimum established from
last analysis and its frequency bandwidth is considered infinite.


By giving different operational amplifier input capacitance values ranging from 0.20 to 5.00 times the value of
the integrating-capacitor, applying two differential sinusoidal signals at the input of the circuit, one named Vin
π/2
with a
frequency exactly on π/2 rad/s and with a differential amplitude of 0.5Vpp, another one called Vin
0.998π
with a frequency
of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last
sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig. 6.9 for a oversampling
rate of 256.


From the right SNDR versus Input Capacitance curve on Fig. 6.9 it is possible to percept that for an input
capacitance value of the same other or lower than the integrating capacitor value it is possible to achieve a SNDR curve
close to the theoretical one on Fig. 4.15. It means that the input capacitance of the individual operational amplifier
inputs should be maximum of the order or lower than the integrating-capacitor value that will be used on the final
circuit.



-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNDR HPSDM 2nd Ord | OSR = 256 | Diff Cin
OpAmp

Vin
0.998π
[dB] | Vin
π/2
= 0.0V
S
N
D
R

[
d
B
]
0 1 2 3 4 5
0
20
40
60
80
100
120
S
N
D
R

[
d
B
]
(Cin
OpAmp
/Ci) [fF] | Vin
0.998π
= -3dB
SNDR HPSDM 2nd Ord | OSR = 256 | Diff Cin
OpAmp

5.00 x Ci
2.00 x Ci
1.00 x Ci
0.50 x Ci
0.20 x Ci

Fig. 6.8: SNDR for different operational amplifier’s input capacitance values on the 2
nd
Order High Pass Sigma-Delta
Modulator Circuit
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 47 / 71

Operational Amplifier Bandwidth Analysis

With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its
bandwidth must also be analyzed to achieve a SNDR curve close to the theoretical one from Fig. 4.15. Implementing
the circuit shown in Fig. 5.12 and modelling the operational amplifier like depicted on Fig. 6.9 a set of circuit
simulations and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig.
6.12.

Fig. 6.9 Operational amplifier with frequency bandwidth modelling for simulations

From circuit in Fig. 6.10 it is possible to find out the relation between the -3dB gain frequency and the 0dB
gain frequency for an amplifier with a RC low pass filter at its output:



Fig 6.10 Operational amplifier with a low pass filter at the output circuit modelling


2
2
2
2
2
2
2
) ( 1 ) (
) (
|
|
.
|

\
|
=
|
|
.
|

\
|
+
=
RCw
G
w Vin
w Vout
(6.1)

1 ,
2
3
>> =

G for
RC
G
f
dB
π
(6.2)

The same can be found for the 0dB frequency:

( )
2
2
2
2
2
1
) ( 1 ) (
) (
=
|
|
.
|

\
|
+
=
RCw
G
w Vin
w Vout
(6.3)

1 ,
2
0
>> = G for
RC
G
f
dB
π
(6.4)

From equations (6.2) and (6.4) it is possible to find the relation:

dB dB
f f
0 3
2 =

(6.5)

It should be noticed that for the purpose of the simulations the gain in the voltage gain source model in Fig. 6.9
are set to 5000 (74dB) which is enough given the SNDR versus Gain curve on Fig. 6.2. The value of the resistor R is
given by equation (6.6):
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 48 / 71

dB
f C
R
0
1
5000 2
2
1
× × × =
π
(6.6)

The parameter R on the model on Fig 6.9 is then related through equation (6.6) to the 0dB gain frequency of
the operational amplifier for a given capacitor value C on this simulation set on 1nF. By specifying different R values
and applying two differential sinusoidal signals at the input of the circuit, one named Vin
π/2
with a frequency exactly on
π/2 rad/s and with differential amplitude of 0.5Vpp and the other one called Vin
0.998π
with a frequency of 0.998π rad/s
and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the
output of the system results on the following left SNDR curves depicted on Fig. 6.11 for a oversampling rate of 256.

As it possible to see from the right SNDR versus f
0dB
curve on Fig. 6.11 the minimum required operational
amplifier 0dB gain frequency, f
0dB
,

should be greater than 4 times the sampling frequency f
s
in use on the system.
-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp f
0dB

Vin
0.998π
[dB] | Vin
π/2
= 0.5V
S
N
D
R

[
d
B
]
0 2 4 6 8 10 12 14 16
0
20
40
60
80
100
120
S
N
D
R

[
d
B
]
(f
0dB
/f
s
) | Vin
0.998π
= -6dB
SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp f
0dB

16 x f
0dB
/f
s
12 x f
0dB
/f
s
8 x f
0dB
/f
s
4 x f
0dB
/f
s
3 x f
0dB
/f
s
2 x f
0dB
/f
s
1 x f
0dB
/f
s

Fig. 6.11: SNDR for different f
0dB
values of the operational amplifier on the 2
nd
Order High Pass Sigma-Delta
Modulator Circuit
6.3 Comparator Requirements

Comparator Offset Analysis

With the same idea of the operational amplifier requirement analysis the comparator should be checked for its
offset influence over the SNDR curve. Using the scaled model of Fig. 6.3 and setting different switching voltage values
for the comparator (1-bit A/D Converter) the following SNDR curves result as depicted on left Fig. 6.12. From the right
SNDR versus Offset curve on Fig. 6.12 it is possible to see that for an offset voltage value ranging from -50mV to
50mV the SNDR curve achieves the desired values compared to the theoretical one from Fig. 4.15 for OSR equal 256.

Comparator Hysteresis Analysis

The comparator should also be checked for its hysteresis influence over the SNDR curve. Using the scaled
model of Fig. 6.3 and setting different switching value points for a hypothetical symmetrical comparator’s hysteresis
curve the following left SNDR curves result as depicted on Fig. 6.13. From the right SNDR versus Hysteresis Switching
Point curve on Fig. 6.13 it is possible to observe that for hysteresis symmetrical switching voltage values lower than
|100mV| the SNDR curve achieves the desired values compared to the theoretical one from Fig. 4.15 for OSR equal 256.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 49 / 71

-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNR HPSDM 2nd Ord | V
π/2
= 0.5V | Diff Offset Comp
V
0.998π
[dB]
S
N
D
R

[
d
B
]
-0.90
-0.70
-0.50
-0.20
-0.10
-0.05
-0.02
0.00
+0.02
+0.05
+0.10
+0.20
+0.50
+0.70
+0.90
-1 -0.5 0 0.5 1
0
20
40
60
80
100
120
Offset [V] | V
0.998π
= -21 dB
S
N
D
R

[
d
B
]
SNR HPSDM 2nd Ord | V
π/2
= 0.5V | Diff Offset Comp
Fig. 6.12 SNDR for different comparator’s offset switching voltage values on the 2
nd
Order High Pass Sigma-Delta
Modulator Circuit

-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNR HPSDM 2nd Ord | V
π/2
= 0.5V | Diff Histeresis Comp
V
0.998π
[dB]
S
N
D
R

[
d
B
]
0.00
+0.01
+0.02
+0.05
+0.10
+0.20
+0.50
+0.90
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0
20
40
60
80
100
120
Hysteresis Switchting Point [V] | V
0.998π
= -21 dB
SNR HPSDM 2nd Ord | V
π/2
= 0.5V | Diff Histeresis Comp

Fig. 6.13 SNDR for different comparator’s symmetrical hysteresis witching voltage values on the 2
nd
Order High Pass
Sigma-Delta Modulator Circuit

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 50 / 71

7. Analog Components Circuit Design

7.1 Operational Amplifier Transistor Circuit Design

Having in mind that the main application of this TRNG with a Sigma-Delta modulator ADC is oriented to
low power and restricted area on die applications, it should be established a sampling frequency that fulfils the usually
necessary random bit stream rates and leaves a big security margin concerning to influences of the flicker noise of the
switching-transistors over the AIS Standard Statistical Test results. It should also be remembered that if needed the
random bit stream rate could be increased by applying the “Gauss Distribution Comparator” algorithm as mentioned
before. For the purpose of this work it was considered a sampling frequency of 25MHz which translates to an output
random bit stream close to 100k bits/s with a clock signal waveform drawn as it follows on Fig. 7.1.

Fig. 7.1 Signal “o” sampling frequency clock waveform

From previous section 4.5.4 concerning the thermal and flicker noise analysis the integrating-capacitor value
for the switching-circuit design should lay between 20fF to 60fF and in this case was chosen to be 25fF which imposes
some additional characteristics and limits that the operational amplifier, comparator and transmission gate need to
satisfy to allow the proper operation of the system.

Using the parameters on Fig. 7.1 it is possible to calculate the required minimal output driving current of the
operational amplifier if it is taken into account that it needs to drive at least 750fF of capacitive load at each of its
outputs as it is possible to see from the switched-capacitor circuit in Fig. 5.12 once the scaling factor are properly
applied for the chosen integrating-capacitor value and taking also into account the capacitors of the common-mode
feedback control circuit in the operational amplifier output stage. For the 90nm MOS technology in use the nominal Vss
to Vdd source voltage is 1.20V which follows to a minimal output driving current given by:

) ( 5
5
1
) (
Vss Vdd f C
T
Vss Vdd
C
dt
dV
C Iout
s load load load
− × × × =

= > (7.1)

As stated on equation (7.1) if it is taken into account that the sampled voltage needs to reach its 100% value in
one fifth of the sampling period time and additionally applying a security factor of 2 times then it comes to a minimum
required driving current Iout of 225uA.

The second important factor to be taken in account is the operational amplifier input capacitance which for a
differential MOS pair input is mainly given by the size of the differential input pair transistors. From previous section
6.2 it was mentioned that the operational amplifier input capacitance should be equal or less than the integrating
capacitor value. In this design, the integrating capacitor was established to 25fF then the simulation measured
operational amplifier input capacitance should be equal or lower than this value.

From the previously determined requirements the following operational amplifier circuit with bias and
additional common-mode feedback control (CMFB) circuit was designed as depicted on Fig. 7.2 and Fig. 7.3. As shown
on Figs. 7.4 and 7.5 through CADENCE Spectre small-signal AC and large-signal DC simulation analysis the circuit
satisfies the previous determined operational amplifier requirements for nominal conditions (Vdd-Vss = 1.20V,
Temperature = 27 °C) as stated on Table 7.1:

Parameter Simulated Required Limit
DC Gain 43dB DC Gain>40dB
f
0dB
182MHz f
0dB
/f
s
>4, f
s
=25MHz
Phase Margin 70° Phase Margin > 50°
Iout 300uA Iout>=225uA
Cin 4fF Cin≤25fF
Table 7.1: Operational amplifier simulated and required parameters
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 51 / 71




Fig. 7.2 Operational Amplifier Transistor Circuit Design

As it is possible to observe on Fig. 7.2 the operational amplifier is built on two amplification stages: the first
stage being a folded-cascode circuit composed by the biasing current-mirrored transistors Q6, Q10 and Q11, differential
input pair Q7 and Q8, cascode transistors Q12 and Q13 and by the folded transistors Q14 and Q15. The second stage
being composed by two common-source circuits through transistors Q18 and Q19 and biasing transistors Q16 and Q17.

Additionally there is a simple current mirror biasing circuit composed by transistors Q1, Q2, Q3, Q4 and Q5. It
should be noticed that transistors Q7 and Q8 must be reduced on area size as much as possible to reduce the input
capacitance of the operational amplifier’s input, the drawback is that they have a strong contribution on the first stage
folded-cascode amplification which for this configuration achieves less than 10dB gain, for that reason a second
amplification stage was added to achieve an overall gain higher than the required 40dB and that could drive at least
300uA at each output. To satisfy the required phase margin additionally phase compensation capacitors C1 and C2 were
inserted between the input and output of the second stage as seen on the circuit.

When using fully-differential operational amplifiers in a feedback application, the applied feedback determines
the differential signal voltages, but does not affect the common-mode voltages. It is therefore necessary to add
additional circuitry to determine the output common-mode voltage and to control it to be equal the halfway between the
power-supply voltages. The circuit that does this functionality on the operational amplifier circuit is the common-mode
feedback circuit (CMFB) given on Fig. 7.3 [49 50].

In this circuit, capacitors named Cc generate the average of the output voltages, which is used to create control
voltages for the operational amplifier current sources. The DC voltage across Cc is determined by capacitors Cs, which
are switched between bias voltages and between being the parallel with Cc. This circuit behaves like a switched-
capacitor low-pass filter having a DC input signal. The bias voltage is designed to be equal to the difference between
the desired common-mode voltage and the desired control voltage used for the operational amplifier current sources
[38].


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 52 / 71

The capacitors labelled Cs should be between one-quarter the sizes of the non-switched capacitors Cc. Due to
the fact that the operational amplifiers’ outputs need to drive at least 225uA each, a high capacitor value is necessary on
the CMFB circuit, but using a larger capacitance value overloads the operational amplifier more than necessary during
the “e” clock phase. Reducing the capacitor too much causes common-mode offset voltages due to charge injection of
the switches [38] and additionally by reducing the capacitor too much it creates a possible capacitor voltage-divider
between the parasitic capacitance of transistors Q16 and Q17 and their correspondents Cc capacitors on the CMFB
circuit structure which also yields to common-mode offset voltages. There is an optimum value which for this circuit
was achieved after some circuit simulations and controllability performance verification of the common-mode feedback
circuit yielding to the capacitor values given on the circuit depicted on Fig. 7.3.




Fig. 7.3 Operational Amplifier Transistor Common Feedback Circuit Design


The final phase and gain small-signal AC circuit simulation for this operational amplifier configuration can be
seen on Fig. 7.4 which returns the DC Gain, f
0dB
and Phase Margin parameters given on Table 7.1 fulfilling the previous
determined requirements for each one.


The large-signal DC Vin Sweep analysis depicted on Fig. 7.5 shows the voltage swing of the internal signals
“int_outp” and “int_outn” relative to the first amplification stage of the circuit of Fig. 7.2 as well as the voltage swing of
the operational amplifier output signals “outp” and “outn” which saturation limits comply with the maximum and
minimum values of the previous scaled output signals “o1” and “o2” from Fig. 6.3.


Additionally to these nominal condition simulations a set of Monte-Carlo circuit simulations were performed
to check out the robustness and tolerance of the designed operational amplifier to temperature, power-source voltage,
process fabrication and mismatch variations as well as to measure the distributions of parameters DC Gain, f0dB and
Phase Margin and yield fabrication of the operational amplifier circuit.


For these Monte Carlo simulations there were taken into account statistical models for process fabrication and
mismatch variations on the 90nm MOS technology used by the CADENCE Spectre [73] simulation CAD tool. For
each temperature there were simulated three different power-source voltages and the respective distributions of the
parameters DC Gain, f
0dB
and Phase Margin shown on Figs. 7.6, 7.7 and 7.8.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 53 / 71




Fig. 7.4 Operational amplifier CADENCE Spectre small-signal AC gain and phase analysis



Fig. 7.5 Operational amplifier CADENCE Spectre large-signal DC Vin Sweep analysis

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 54 / 71




Fig. 7.6 Operational amplifier Monte Carlo phase margin, DC gain and f
0dB
histograms for different power supply
voltages at the temperature of -40°C





Fig. 7.7 Operational Amplifier Monte Carlo phase margin, DC gain and f
0dB
histograms for different power supply
voltages at the temperature of +27°C

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 55 / 71



Fig. 7.8 Operational Amplifier Monte Carlo phase margin, DC gain and f
0dB
histograms for different power supply
voltages at the temperature of +100°C


As it can be seen on Figs. 7.6, 7.7 and 7.8 the chosen temperatures are -40°C, +27°C and +100°C, two extreme
environment temperatures and one ambient temperature. For the power-supply voltage it was considered a tolerance of
+/- 10% over the nominal value of 1.20V taken into account possible variations of such order for the kind of application
where this system could be applied.


From the right distribution curves on Figs. 7.6, 7.7 and 7.8 it is possible to observe that the f
0dB
parameter
fulfils in 95% of the cases its minimum allowed value of 4f
s
with f
s
equal to 25MHz for any temperature and power-
supply voltage and that the higher the temperature the lower gets the distribution mean value and more narrowed
becomes the distribution curve for different power-supply voltages.


Looking at the middle distribution curves on Figs. 7.6, 7.7 it shows that the DC Gain parameter fulfils on at
least 85% of the cases its minimum required value of 40dB having just a low performance of 60% on the case for the
extreme temperature of +100°C like depicted on the middle distribution curve on Fig. 7.8. It is also possible to see that
the distribution mean value keeps relative constant as well as the distribution curve keeps the same wide spreading
under different temperature and power-source voltage conditions.


Finally at the left distribution curves on Fig. 7.7 and 7.8 it is also possible to see that the Phase Margin
parameter fulfils on at least 82% of the cases the minimum required value of 50° having just a low performance of 40%
on the case of extreme low temperature of -40°C like depicted on the middle distribution curve on Fig. 7.6. It it also
possible to observe that the higher the temperature the higher gets the distribution mean value and more narrowed
becomes the distribution curve for different power-supply voltages.


From these distribution curves some improvements should be done on the design of the operational amplifier
circuit, but that would take more time on its design and due to the lack of time and considering that for the nominal
conditions the current design has an average simulation process yield higher than 80% it was decided to keep using it as
it is and further works could improve it if stronger requirements are imposed on the environment temperature that such
application would be used.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 56 / 71

7.2 Comparator Transistor Circuit Design

From the previously determined requirements the following comparator circuit was designed as depicted on
Fig. 7.9. As it is possible to see the comparator is built on two stages: the first being a clocked differential pair amplifier
composed by transistor Q1 to Q10 and the second a NAND based SR latch composed by transistor Q11 to Q22.



Fig. 7.9 Comparator Circuit Design

Performing a large-signal DC Vin Sweep CADENCE Spectre circuit simulation of the circuit the following
hysteresis curve for the comparator output under nominal temperature and power-source conditions was taken depicted
on Fig. 7.10. The comparator fulfils its requirements with hysteresis symmetrical switching value between -100mV to
100mV.


Fig. 7.10 Comparator Hysteresis Curve

The offset voltage is possible to estimate if we take into account that the threshold voltage mismatch σ
∆Vt
of a
transistor pair is proportional to the inverse of the square root of the active device area with the matching parameter
A
∆Vt
[67 68 69 70]:


WL
A
Vt
Vt


= σ (7.2)

Taken from the reference [67] that A
∆Vt
is estimated to be around 3mVµm for the 90nm CMOS technology
then using the input pair transistors’ size, it is possible to calculate that the comparator’s offset will be between -11mV
to 11mV which is in compliance to the previous determined offset limits for the comparator between -50mV and 50mV.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 57 / 71

7.3 Transmission-Gate Transistor Circuit Design

To design the transmission-gate it should be remembered from section 7.1 that the switched-capacitors drive
currents of the maximum order of 300uA from the operational amplifier. Establishing that the sampled voltage on the
integrating switched-capacitor should achieve 100% of its magnitude before one-fourth the system’s sampling period
the transmission-gate on resistance should then be lower than:

s
on s on
Cf
R T C R
10
1
2
1
5 < ⇒ < (7.2)

This gives a transmission gate on resistance of maximum 160kΩ for an integrating switched-capacitor of 25fF
and system sampling frequency of 25MHz. Besides this requirement, the switching transistors should have an area that
reduces as much as possible the flicker noise of the system. Through CADENCE Spectre [73] circuit simulation the
designed transmission-gate depicted on Fig. 7.11 gives a maximum on resistance of 6.3kΩ as shown on Fig. 7.12 and a
transistor area of 51200 nm
2
which fulfils the desired Flicker Noise Corner frequency from Fig. 4.30 if it is considered
that the Flicker Noise Corner Frequency is 1000 times smaller than half the system sampling frequency.



Fig. 7.11 Transmission Gate Transistor Circuit Design





Fig. 7.12 Transmission Gate Active On Resistance



True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 58 / 71

8. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design, Simulation & Analysis

Once designed all basic analog components circuits the following switched-capacitor Sigma-Delta modulator
was built as depicted on Fig. 8.1 with corresponding clock signals given on Fig. 8.2.



Fig. 8.1 Switched-Capacitor Sigma-Delta Modulator Circuit Design




Fig. 8.2 Clock Signals for the Switched-Capacitor Transistor Circuit Design

Using the Input Circuit on Fig. 8.3a with the circuit on Fig. 8.1 to reduce computation for first simulations
some CADENCE Spectre [73] transient simulations were performed to check out the robustness and calculate the
output spectrum and limitations of the circuit under ambient temperature of +27°C and different power-supply voltages
as shown of Figs. 8.4, 8.5 and 8.6. For this simulations the differential sinusoidal signal input was set to -18dB with
frequency at 12.48MHz which corresponds to 0.998π rad/s with a system sampling frequency of 25MHz.



True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 59 / 71




Fig. 8.3 Switched-Capacitor Input Circuit


Looking at the shape of the output spectrum on Figs. 8.4, 8.5 and 8.6 it is possible to recognize a high pass
transfer function system. Looking carefully on the high pass baseband of work spectrum it is also possible to observe
that the lower the temperature the less tolerance the circuit has to lower values of power-supply voltages. On Fig. 8.4 it
is shown that for a power-supply voltage below minus 5% of its nominal value of 1.20V the noise is increased at the
desired high pass baseband of work which would succeed on a lower SNDR operation point for the Sigma-Delta
modulator. The same appointment and behaviour happens for the ambient temperature of +27°C, but for power-supply
voltage minus 10% under its nominal value.

One reason for this drawback is that by lowering the power supply voltage the operational amplifier
operational working point derivates from its nominal polarization condition which degrades the required parameters for
a proper operation of the Sigma-Delta modulator. The second reason is that by lowering the power-supply voltage the
90nm transistor MOS characteristics for nominal operation voltage of 1.20V are taken out from their voltage source-
drain quiescent operation point that could be overcome just with lower transistor voltage threshold which design and
study is beyond this work and open for further ones. One possible simpler solution would be to increase the nominal
power-supply voltage on at least 10% to achieve then an overall tolerance of ±10% for any case of extreme
temperatures.

The second set of circuit simulations was to determine the SNDR curve of the Sigma-Delta modulator for
different differential sinusoidal input signal amplitudes ranging from -48dB to -3dB for different power-supply voltages
at the ambient temperature of +27°C as depicted on Fig. 8.7. As previously mentioned for power-supply voltages below
minus 5% of the nominal value the Sigma-Delta modulator does not achieve its proper operation, meaning that either
the nominal power-supply voltage should be increased or the nominal power-supply voltage of 1.20V should have a
tolerance on the range of ±5%.

Applying then the Input Circuit of Fig. 8.3b and introducing the additional clock signals of Fig. 8.8 to control
the transmission-gates of the Input Circuit so that an artificial inbuilt sinusoidal sampled signal of one fourth of the
system sampling frequency could be generated without additionally external circuitry for a future die fabrication some
CADENCE Spectre [73] transient simulations were ran for different first stage input capacitor scaling factors to find the
optimum value for which the Sigma-Delta modulator outputs a flatten spectrum at the high pass baseband frequency
range of work as shown on Fig. 8.9. Finally on Fig. 8.11 are shown the optimum first stage input capacitor’s values and
the final scaled switched-capacitor 2
nd
Order High Pass Sigma-Delta Modulator Transistor Design for this project.

To run the fully set of statistical tests it would be required to sample at least 1.54 billion samples from
CADENCE Spectre [73] transient simulation which its beyond the computer’s memory size and computation time
processing. Only a real integrated-circuit system version could give that amount of samples in much less time. The only
way to apply all tests is by producing a real die and performing real measures, but that was left for future works.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 60 / 71

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-140
-120
-100
-80
-60
-40
-20
0
Output q Spectrum / T = -40°C
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s]
0.985 0.99 0.995 1
-140
-120
-100
-80
-60
-40
-20
0
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s] Baseband
Discrete-Time System Model
CADENCE Spectre Vdd-Vss = 1.08V
CADENCE Spectre Vdd-Vss = 1.14V
CADENCE Spectre Vdd-Vss = 1.20V
CADENCE Spectre Vdd-Vss = 1.26V
CADENCE Spectre Vdd-Vss = 1.32V

Fig. 8.4 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of -40°C with
a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-140
-120
-100
-80
-60
-40
-20
0
Output q Spectrum / T = +27°C
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s]
0.985 0.99 0.995 1
-140
-120
-100
-80
-60
-40
-20
0
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s] Baseband
Discrete-Time System Model
CADENCE Spectre Vdd-Vss = 1.08V
CADENCE Spectre Vdd-Vss = 1.14V
CADENCE Spectre Vdd-Vss = 1.20V
CADENCE Spectre Vdd-Vss = 1.26V
CADENCE Spectre Vdd-Vss = 1.32V

Fig. 8.5 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +27°C with
a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 61 / 71

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-140
-120
-100
-80
-60
-40
-20
0
Output q Spectrum / T = +100°C
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s]
0.985 0.99 0.995 1
-140
-120
-100
-80
-60
-40
-20
0
M
a
g
n
i
t
u
d
e

[
d
B
]
ω [xπ rad/s] Baseband
Discrete-Time System Model
CADENCE Spectre Vdd-Vss = 1.08V
CADENCE Spectre Vdd-Vss = 1.14V
CADENCE Spectre Vdd-Vss = 1.20V
CADENCE Spectre Vdd-Vss = 1.26V
CADENCE Spectre Vdd-Vss = 1.32V

Fig. 8.6 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +100°C
with a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz

-60 -50 -40 -30 -20 -10 0
0
20
40
60
80
100
120
SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C
Vin
0.998π
[dB]
S
N
D
R

[
d
B
]
Vdd-Vss = 1.08V
Vdd-Vss = 1.14V
Vdd-Vss = 1.20V
Vdd-Vss = 1.26V
Vdd-Vss = 1.32V
1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
0
20
40
60
80
100
120
S
N
D
R

[
d
B
]
(Vdd-Vss) [V] | Vin
0.998π
= -15dB[dB]
SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C
Fig. 8.7: High Pass Sigma-Delta Modulator SNDR curve for different power-supply voltage values at the ambient
temperature of +27°C

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 62 / 71




Fig. 8.8 Clock Signals for the Input Transistor Circuit Design


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-120
-100
-80
-60
-40
-20
0
HPSDM 2nd Orded Output Spectrum | OSR = 256 | T = 27°C | Vdd-Vss = 1.20V
ω [xπ rad/s] | f
s
= 25MHz
M
a
g
n
i
t
u
d
e

[
d
B
]

Fig. 8.9 Clock Signals for the Input Transistor Circuit Design


This final 256 times oversampled 2
nd
order high pass Sigma-Delta modulator with a sampling frequency of
25MHz, under nominal power-supply voltage of 1.20V and ambient temperature of +27°C together with the digital
signal-processing decimation filter with a “Zero-Cross Comparator” algorithm explained before gives a random bit
stream of 100Kbs/s at the output of the final TRNG system structure depicted on Fig. 8.10. The simulated dynamic
power consumption for the Sigma-Delta modulator transistor circuit on Fig. 8.11 is 1.6mW. For estimation of Sigma-
Delta modulator on die chip area it was taken from reference [51] the non-cascaded second order Sigma-Delta
modulator with total capacitance per stage of 2pF which has an area of 0.096 mm
2
and due to the fact that the area is
mainly determined by the size of the capacitors the estimated area for this totally new 2
nd
order high pass Sigma-Delta
modulator built on 90nm CMOS technology would be around 3 times smaller given an area of 0.032 mm
2
which is
comparable to other TRNG references and integrated-circuits mentioned at the introduction of this work and listed on
Table 8.1 for comparisons.

Looking on the system of Fig. 8.10 besides the 2
nd
order high pass Sigma-Delta modulator it would be also
interesting to implement the sinusoidal multiplication and the 3
rd
Order TSinc FIR Filter in a CMOS hardware system
due to the required high clock frequency for this filter in this system and known effective hardware implementation for
this kind of filter [38]. The One Fourth Band with TSinc Compensation FIR Filter and the “Zero-Cross Comparator”
algorithm could then be implemented in a DSP microprocessor system with such filters’ orders that it does not degrade
the resolution of the previous Sigma-Delta modulator once its resolution is going to decide the performance of the
overall system and additionally leaves the option to implement the “Gauss Distribution Comparator” algorithm
described before if a higher random output bit stream rate is desired for an application with possibility to achieve more
then 1.76Mbs/s at the output of the system.
True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 63 / 71



Fig. 8.10 Final TRNG with a Sigma-Delta Modulator ADC System


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 64 / 71

Fig. 8.11 Switched-Capacitor Sigma-Delta Modulator Circuit Design with additional Input Circuit
Ref. / Year Method Technology Area Voltage Power Clk Freq. Bit Rate Tests
[12] 2001 Metastability n. a. n. a. 5.0V n. a. 25MHz n.a. n. s.
[13] 2002 Metastability AMS 0.6um n. a. 3.3V n. a. 100MHz 100Mbs/s n. s.
[16] 2004 Astable Multivibrator SBD-MOS n. a. 5.0V n. a. 16MHz 50Kbs/s FIPS [37]
[9 10] 1999 Dual Osc. Sampling n. a. n. a. 3.3V n. a. n. a. 75Kbs/s FIPS [37]
[17] 2004 Dual Osc. Sampling CMOS 0.18um n. a. 1.8V n. a. 1GHz 1Gbs/s FIPS [37]
[8] 2003 Dual Osc. Sampling CMOS 0.18um 0.0016mm
2
3.3V 2.3mW 10GHz 10Mbs/s FIPS [37]
[19] 1997 Direct-Noise Amplif. CMOS 1.2um 2.92mm
2
5.0V 37mW 10KHz 5Kbs/s n. s.
[22] 2003 Direct-Noise Amplif. CMOS 2um 0.443mm
2
1.8V 1mW 2.5KHz 2Kbs/s n. s.
[24] 2002 Direct-Noise Amplif. CMOS 0.18um 0.025mm
2
3.3V 3.6mW 10MHz 5Mbs/s n. s.
[23] 2001 Chaotic System CMOS 0.8um 0.0042mm
2
5.0V 1mW 1MHz 1Mbs/s n. s.
[28] 2005 Chaotic System CMOS 0.25um 0.022mm
2
2.5V 117mW 10MHz n.a. n. s.
[29 30] 2001 Chaotic System CMOS 0.8um n. a. 5.0V n. a. 5MHz 1Mbs/s n. s.
[31] 2000 Chaotic System AMS 0.6um n. a. 5.0V n. a. 12MHz 4Mbs/s FIPS [37]
[32] 2005 Chaotic System n. a. n. a. 1.5V n. a. n.a. 10Mbs/s FIPS [37]
[7] 2000 Hybrid System CMOS 2um 1.5mm
2
3.0V 3.9mW n.a. 1Mbs/s n. s.
[21] 2006 Direct-Noise Amplif. CMOS 0.12um 0.009mm
2
1.5V 50uW 5MHz 200Kbs/s n. s.


This Work


Sigma-Delta Mod.


CMOS 90nm


~0.032mm
2



1.2V


1.6mW


25MHz
with ZCC
~ 100Kbs/s

with GDC
≥1.76Mbs/s


AIS 31 [4]
n. a. = not available / n. s. = not standard / ZCC = Zero-Cross Comparator / GDC = Gauss-Distribution Comparator
Table 8.1 Characteristics performance comparison for different TRNG methodologies

It should be noticed that the FIPS [37] Standard Statistical Tests (SSTs) have similarities to the AIS 31 SSTs
[4], but the FIPS allows that some tests to have a certain percentage of error on the randomness on the generated bit
stream which is not allowed on the AIS 31 Standard Statistical Tests. For better comparison it would be necessary to
make a carefully analysis over the FIPS SSTs results with the AIS 31 SSTs results.


9. Conclusion and Future Works

As stated at the beginning, this work intended to study the feasibility of random number generation through a
Sigma-Delta modulator with additional digital signal-processing block system through a noise source integrated into the
modulator’s feedback loop. This was accomplished through the final built on 90nm CMOS technology totally new 2
nd

order high pass Sigma-Delta modulator transistor circuit and established requirements for additional digital-signal
processing blocks for conception of an entire True Random Number Generation system based on a totally new principle
besides the other ones already mentioned at the references.

From the initial three possible studied low pass, band pass and high pass Sigma-Delta modulator structures it
came out through system model simulations concerning the oversampling rate, thermal noise magnitude and Flicker
Noise Corner Frequency influences over the output spectrum and AIS 31 Standard Statistical Tests results that the high
pass system has the desired robustness and qualified itself appropriate to be implemented as a circuit solution.

It should be mentioned that for the first time a totally new designed high pass Sigma-Delta modulator was built
and used, but it should be noticed that due to the fact that the thermal noise is the useful signal to be extracted from the
system, there is no need for a high order decimation filter rather than if a high pass Sigma-Delta modulator would be
used to other analog signal-processing application which in this case it would be very difficult to design a decimation
filter that fulfills the desired Nyquist frequency. The fact that the thermal noise is the useful signal in this work also
allows the use of a relaxed decimation filter because the convolution of part of the upper side spectrum at half the
sampling frequency will not effect the proper operation of the high pass Sigma-Delta modulator because there would be
added just more thermal noise at the baseband frequency of work which could still be used to generate random numbers.
Additionally to these relaxing requirements this high pass system also holds an enhanced advantage regarding
influences of the Flicker noise over the output spectrum and generated random output bit stream.

Together with the first system simulations there were also determined the DSP decimation filter requirements
as well as there were defined and implemented two possible algorithms for the generation of the final random output bit
stream where one of them named “Gauss Distribution Comparator” algorithm enables the increase of the out bit stream
rate despite of the reduction caused by to the oversampling rate process that follows the signal-processing decimation
and without lose of the output entropy if instead a “Zero-Cross Comparator” algorithm is applied. Although many
simulations were ran to certify this new “Gauss Distribution Comparation” approach, due to the high amount of
necessary computation capacity and lack of time further simulations were decided to be done using the “Zero-Cross
Comparator” algorithm leaving the option open for the use or not of a higher bit rate on future works.

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 65 / 71


Followed by this analysis there came out two possible topologies to implement the high pass transfer function
with a switched-capacitor circuit. Through a carefully analyze on the transfer function equations it was found out that
by switching the polarity of the integrating-capacitor on the classic basic low pass cell circuit on alternating clock
cycles a high pass transfer function could be implemented with less switching-gates and switched-capacitors for a
whole 2
nd
order high pass Sigma-Delta modulator structure.



One classical and one reduced circuit structures were built testifying that they were equivalent and that the
reduced version could be used on the further requirement analysis for the different components of the analog circuit
design. Using this reduced version and its equivalent discrete-time system model there were determined the parameter
requirements characterization for the operational amplifier, comparator, transmission gate and scaled switched-capacitor
for their further implementation using a 90nm CMOS library technology on transistor circuit level design.



Through these required parameters the operational amplifier with common-mode feedback control, the latched
comparator, the transmission gate and the switched-capacitor transistor circuits were built compounding finally the
whole Sigma-Delta modulator Analog-to-Digital converter circuit. There were then ran circuit simulations for different
power-supply voltages and environment temperatures to measure the Sigma-Delta modulator circuit robustness,
limitations and characteristic SNDR curve for different differential sinusoidal input amplitudes under these different
conditions for comparations with theoretical previous results.



Through these analysis it was determined the required scaling factor for the input signal circuit and finally
using the previous designed digital signal-processing decimation filter and “Zero-Cross Comparator” algorithm an
entire TRNG system was built.


The totally new concept of TRNG with a totally new 2
nd
order high pass Sigma-Delta modulator built on this
work shows that this concept of random number generation is one more possible solution and comparable in
performance to other mentioned works. It should be noticed that this is just an initial and original study which opens
themes for many other researches like the usage of higher order high-pass Sigma-Delta modulator ADCs with multi bit
structures and analysis of the required decimation signal-processing filter resolution which could yield to less digital-
signal processing area and power consumption.



Another possible study would be the design of an enhanced operational amplifier on 90nm CMOS technology
which Monte-Carlo analysis achieve higher percentage process and mismatch fabrication yields. One interesting study
would also be the design of a decimation signal-processing system which could make fulfill all those AIS 31 Standard
Statistical Tests that does not pass when the Flicker Noise Corner frequency gets higher.



Besides that it would be interesting to implement a layout version of this 2
nd
order high pass Sigma-Delta
modulator to generate the requested amount of random bits to apply the fully AIS 31 Standard Statistical Tests as well
as implement on a DSP system the “Gauss Distribution Comparator” algorithm to achieve higher output bit stream rates
and analyze the trade offs between the One Fourth with TSinc Compensation Filter requirements and the parameter N
for the “Gauss Distribution Comparator” algorithm.



It would be also interesting to check out the robustness of the system on a real hardware application to power-
source supply tolerance, environment temperature, electromagnetic interference and other external influences over the
generated random output bit stream to better classify this system accordingly to the AIS 31 Document Standard
requirements [4]. Additionally to the present built circuit it would be probably required and automatic feedback control
system which measures the distribution of the random bits to recalibrate it to AIS 31 Standard Statistical Tests limits.


True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 66 / 71

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Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 71 / 71

11. Appendix

True Random Number Generator based on a Sigma-Delta Modulator Index 1. Abstract ........................................................................................................................................................ 3 2. Introduction.................................................................................................................................................. 3 3. Current and Common Random Number Generators Methods and the AIS 31 Standard Document .. 4 3.1 Metastability Method.............................................................................................................................. 4 3.2 Astable Multivibrator Method ............................................................................................................... 4 3.3 Dual Oscillator Sampling Method......................................................................................................... 5 3.4 Direct Noise Amplification Method ...................................................................................................... 5 3.5 Discrete-Time Chaotic Method ............................................................................................................. 6 3.6 Hybrid Mixed Method............................................................................................................................. 6 3.7 AIS 31 Document Standard for True Random Number Generators.................................................. 7 Class P1 TRNGs.................................................................................................................................... 7 Class P2 TRNGs.................................................................................................................................... 8 AIS 31 Standard Statistical Tests........................................................................................................ 8 4. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter.......................................... 11 4.1 Sigma-Delta Modulator Analog-to-Digital Converters...................................................................... 11 4.1.1 Advantages of Oversampling Converters .................................................................................. 11 4.1.2 Oversampling without Noise Shaping ........................................................................................ 11 Quantization Noise Modelling ........................................................................................................... 11 White Noise Assumption ................................................................................................................... 11 Oversampling without Noise Shaping .............................................................................................. 12 4.1.3 Oversampling with Noise Shaping .............................................................................................. 13 Noise Shaped Sigma-Delta Modulator.............................................................................................. 15 First-Order Noise Shaping ................................................................................................................. 15 Second-Order Noise Shaping............................................................................................................ 17 4.1.4 Sigma-Delta Modulator and Noise Modelling ............................................................................. 18 4.2 Second Order Low Pass Sigma-Delta Modulator ............................................................................. 19 4.3 Fourth Order Band Pass Sigma-Delta Modulator ............................................................................. 20 4.4 Second Order High Pass Sigma-Delta Modulator ............................................................................ 22 4.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures .................................. 24 4.5.1 Digital Signal-Processing Decimation Filter Structure .......................................................... 24 4.5.2 Thermal Noise, Quantization Noise and Oversampling Rate Analysis ................................ 27 4.5.3 Choice of the Digital Bit Stream Generator System and Analysis ....................................... 29 4.5.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests............................................. 30 5. High Pass Sigma-Delta Modulator System Level Design...................................................................... 34 5.1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization .................................. 34 The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................... 34 The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit....... 36 The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................ 38 The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit .... 40 6. Requirements for the Different Components of the Analog Circuit System ....................................... 41 6.1 Switched-Capacitor Circuit Requirements ........................................................................................ 41 Differential Sinusoidal Input Signal Amplitude Influence Analysis............................................... 41 Switched-Capacitor Coefficients Scaling Analysis......................................................................... 42 Switched-Capacitor Parasitic Capacitance Analysis ...................................................................... 43 6.2 Operational Amplifier Requirements ................................................................................................. 45 Operational Amplifier Gain Analysis ................................................................................................ 45 Operational Amplifier Input Capacitance Analysis ......................................................................... 46 Operational Amplifier Bandwidth Analysis ...................................................................................... 47 6.3 Comparator Requirements.................................................................................................................. 48 Comparator Offset Analysis .............................................................................................................. 48 Comparator Hysteresis Analysis ...................................................................................................... 48 7. Analog Components Circuit Design ........................................................................................................ 50 7.1 Operational Amplifier Transistor Circuit Design .............................................................................. 50 7.2 Comparator Transistor Circuit Design .............................................................................................. 56 7.3 Transmission-Gate Transistor Circuit Design .................................................................................. 57 8. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design, Simulation & Analysis.......... 58 9. Conclusion and Future Works ................................................................................................................. 64 10. References ............................................................................................................................................... 66 11. Appendix .................................................................................................................................................. 71 Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 2 / 71

True Random Number Generator based on a Sigma-Delta Modulator 1. Abstract Random number generators are essential components of many cryptographic systems. In contrast to pseudo random number generators which are based on digital algorithms, true random number generators produce a random bit stream from a nondeterministic natural source. Thermal noise is a possible source of unpredictable random noise. The intention of the work is to analyze the feasibility of using a Sigma-Delta modulator based analog-to-digital converter for true random number generation, whereas the noise source is integrated into modulator’s loop as well as design a Sigma-Delta modulator ADC circuit structure on 90nm CMOS technology and additional digital-signal processing blocks for generation of a random bit stream. Besides that the work includes compliance comparations to international standard requirements given by international standard randomness tests as well as optimization and nonidealities analysis of the Sigma-Delta modulator related to its switched-capacitor, operational amplifier, comparator and transmission-gate circuit design requirements and additionally external environment influence analyses over the final implementation in transistor level circuit design of the Sigma-Delta modulator analog-to-digital converter and aggregated digital-signal processing blocks for constitution of a whole true random number generation system. 2. Introduction The continuous and fast growing use of digital communication, mobile, computer and network systems has aroused data security issue concerns where some type of data cryptography protection is required. Cryptography allows for the private and secure exchange of authentic messages using carefully generated and distributed cryptographic keys for encryption and decryption. The security of most cryptographic systems relies on unpredictable and irreproducible digital keystreams using a nondeterministic random number generator [1]. Cryptographers often base RNG (Random Number Generator) designs on hidden sources such as keyboard latency [2], hard disk drive air turbulence [3] and computer system clock state [1]. Nevertheless, the security of these designs is often limited on the obscurity and the secrecy of the quasirandom source. Due to this fact, systems that use truly random noise mechanism, such as electronic thermal noise, radioactive decay and atmospheric noise provide the utmost cryptographic security because there is no need to protect the obscurity of the key generation method [1]. With the widespread application of system-on-chip on electronic systems, robust integrated-circuit RNG designs will be needed for secure communication applications. Hardware RNG can feature a very high throughput when well designed, but the produced bit streams usually show a certain level of correlation due to bandwidth limitation, fabrication tolerances, flicker noise, aging and temperature drifts as well as external electromagnetic deterministic interferences. Random noise sources, such as thermal and shot noise, which are actually the only white stochastic processes which can be exploited at the integrated-circuit level, are often masked by deterministic disturbances like substrate noise, flicker noise, power supply noise and external electromagnetic interferences requiring special hardware and EMC shielding to comply with the international standards for true random number generation [4 5 6 7]. A common procedure to remove statistical imperfections in the output bit stream is to process the sequence with a carefully designed correcting or decorrelating algorithm which, from a high speed near-random input stream, generates a lower speed bit stream with increased statistical quality, rising up the entropy contained in the input sequence [8 9 10 11]. The present work wants to study and design a robust, thermal noise-based TRNG IC subcell, suitable for integration with digital encryption circuitry by using a Sigma-Delta modulator Analog-to-Digital Converter in which after digital signal-processing just the desired frequency band portion of the spectrum which contains the useful thermal noise is used to generate a random bit stream at the output of the system. The next Section 3 describes current and common RNG techniques as well as the AIS 31 Standard Statistical Tests for randomness analysis of the output random bit stream. Section 4 discusses the different options of Sigma Delta modulator structures and choice of one of them for the current work based on oversampling rate, thermal and flicker noise influences over the modulator’s output spectrum and AIS 31 Standard Statistical Tests results of the TRNG system model. Still in the same section are defined the digital signal-processing decimation filter and algorithm for generation of the output random bit stream. Section 5 presents two Sigma-Delta modulator circuit construction options for the previous section chosen structure, reporting the circuit model simulation results and choice of one of the circuits. Section 6 comes with the system requirements for the each of different components of the analog circuit design. Section 7 gives the electronic design of each component to be used on the final Sigma-Delta modulator circuit using the 90nm CMOS technology library in CADENCE Spectre [73] including theirs transient, small-signal AC and large-signal DC simulation results and analysis. Section 8 presents the final Sigma-Delta modulator ADC circuit its simulation results and tolerance analysis to external environment influences and final TRNG with a Sigma-Delta modulator ADC system followed by Section 9 discussing conclusions, observations and future researches themes for this random number generation solution. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 3 / 71

1. Fig. uses the known metastability behaviour of digital circuits when the input to a flip-flop is asynchronous to the system clock to generate random bit stream sequences. The metastability occurs when the input changes in unison with the clock setup time. Current and Common Random Number Generators Methods and the AIS 31 Standard Document From references it is possible to classify some different integrated-circuit methods for producing random data sequences. 3. This phenomenon creates instability in the circuit and produces oscillations. 3. 3.1: Metastability method for true random number generator Usually this method requires some type of negative feedback loop control to adjust the probability of the output bit stream bias to 50%. All these methods generate output bit streams that can be statistically proved by standard randomness tests. astable multivibrator. Fig. 3. dual oscillator sampling. which are given as follow: metastability. direct noise amplification. discrete-time chaotic systems and hybrid techniques. shown in Fig.2 Astable Multivibrator Method The astable multivibrator method.1 Metastability Method The metastability method [12 13 14]. which can determine the high or low state of a comparator to generate a truly random bit stream. which also generates some colouring on the output spectrum that reduces the final output entropy. Due to this fact. 3.True Random Number Generator based on a Sigma-Delta Modulator 3. usually uses and electron trap [15] or the capacitor voltage [16] fluctuations in one of the arm branches from an astable multivibrator which output is used to trigger a 1 bit counter that generates a one-bit random number. 3.Sweden 4 / 71 . this method usually has a post-processing unit [13 14] which reduces the output bit stream rate.2. shown in Fig.2: Astable Multivibrator method for true random number generator Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .

Sweden 5 / 71 . shown in Fig.3: Dual Oscillator Sampling method for true random number generator Previous experiments have proven that this method is more robust in the presence of deterministic noise because of nonlinear aliasing phenomenon associated with sampling [18]. eliminating the amplification of the noise source which saves area and reduces power consumption [15]. 3. uses a high-bandwidth amplifier to process the tiny ac voltage produced by a noise source such as thermal or shot noise. which adversely affects the statistical balance of the output random numbers. By carefully selecting the ratio between the two oscillator frequencies an artificially enhanced randomness can be achieved [18]. shown in Fig. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . Fig. potentially compromising the unpredictability of the system. The output of the fast oscillator is sampled on the rising edge of a slower clock using a D flip-flop. 3. One proposed solution is to use the capacitor voltage fluctuation instead of a pure MOS device which eliminates the flicker property and is approximately six orders of magnitude greater than the thermal noise signal [16].4. Due to the low magnitude of these types of noise sources very high requirements are put in the design of the amplifier which needs to accurately amplified the signal to thresholds levels with no bias to a clocked comparator.3 Dual Oscillator Sampling Method The dual oscillator sampling method [8 9 10 17 18]. 3.3. The drawback lies on the high evident flicker noise property.4 Direct Noise Amplification Method The direct noise amplification method [19 20 21 22 23 24]. ideally producing a random bit for each sample. 3. usually a post-processing unit and a zero offset feedback control are required to randomize the final output bit stream. 3. but lacks of adequate shielding from power supply and substrate signals in an IC environment which prohibits the exclusive use of this method for IC-based cryptographic systems. Oscillator jitters causes uncertainty in the exact sample values.4: Direct Noise Amplification method for true random number generator This technique permits a good shielding of the noise source from external electromagnetic interferes.True Random Number Generator based on a Sigma-Delta Modulator The electron trap fluctuations are usually very large compared with those of thermal noise. due to flicker noise and band limitation characteristics of the amplifier output. Fig. produces randomness from phase noise in free-running oscillators. Nevertheless. 3. The drawback on this topology is that typical levels of oscillator jitter are not enough to produce statistical randomness and bit-to-bit uncorrelation which invokes the necessity of post-processing units at the output to further randomize it.

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 3.6 Hybrid Mixed Method The hybrid method is a mixture of the precedent direct noise amplification. In addiction. nonlinearities and process variations [7]. such as mismatches. This method tries to take all advantages from these three methods to reduce or overcome drawbacks when separately used. dual oscillator sampling and discrete-time chaotic methods [7]. take the Bernoulli shift map described by the following iterative relationship: Xn = [2(Xn-1 – e(n)] mod 0. qualifying the system to be used as a truly random bit source [3434]. shown in Fig.True Random Number Generator based on a Sigma-Delta Modulator 3. 3. Fig. the first corresponding to switching-capacitor dynamic systems [25 26]. Circuits which realize systems such as the previous iteration equation are similar to algorithmic A/D converters.1) Where e(n) represents a Gaussian noise signal. 1]. Fig.5 Discrete-Time Chaotic Method The discrete-time chaotic method can further be subdivided into categories.5: Discrete-Time Chaotic method for true random number generator 3. 6. Fig. Furthermore. 3. the second to switched-current [27 28 29 30] and the third to linear unbalanced circuits or pipelined ADCs [31 32 11]. offsets. It has been shown that sequences produced by the previous iteration and similar systems are spectrally flat and uniformly distributed [33].1 (3. As an example. The drawback lies on the big amount of Si area and power dissipation that the circuit requires as well as the limitations for the operational amplifiers used on the direct amplification and on the A/D blocks. renders sequences from the previous iteration unpredictable to an extent. the cascading of N stages of such a circuit that implements the given iteration equation turns into a classical N-bit algorithmic A/D converter with an input range of [0. the divergence of trajectories associated with chaos.5 shows such a type of A/D-based RNG [11 32]. Chaotic systems are usually implemented using discrete-time analog signal processing techniques [27].6: Hybrid method for true random number generator These solution have shown to be insensitive to non-random influences and is unaffected by minor circuit errors. along with the inclusion of noise.Sweden 6 / 71 .

For good physical noise sources. openly transmitted. Through this AIS 31 Document Standard.7 AIS 31 Document Standard for True Random Number Generators Although random numbers play an important role in numerous cryptographic applications. In this case. if total failure of the noise source occurs when the TRNG is switched on. etc. the AIS 31 Standard Statistical Tests [4] introduces two functionality classes (P1 and P2). and therefore of course also the internal. the sequence of internal random numbers corresponds to the digitized noise signal sequence. 7 / 71 Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .True Random Number Generator based on a Sigma-Delta Modulator 3. The assessment of a physical random number generator is essentially based on statistical tests. The output block synchronizes the continuous or non-periodic generation of internal random sequence with the calling of the (external) random number sequence. if total failure of the noise source occurs while the TRNG is being operated. non-constant initialization vectors. In order to take this into account. Fig.) insofar as these can influence the function of the noise source. Depending on the maximum attack potential attributed to a potential perpetrator. It represents the typical sequential processing of the signals. The P2-specific requirements should guarantee that they are practically impossible to determine even if the predecessors or successors are known. It usually delivers an analogue signal that is digitized for further processing. ITSEC (Information Technology Security Evaluation Criteria [35]) and CC (Common Criteria [36]) do not specify any uniform evaluation criteria for random numbers. Fig 3. an online test must be implemented that checks the quality of the internal random numbers when triggered externally. Roughly explaining. the target of evaluation must itself recognize total failure or any interference that occurs in the noise source and may need to be able to resist systematic manipulation attempts. the above properties must also be verified under the intended external usage conditions (temperature. various applications can place different requirements on the properties of the external.Sweden .7 shows a diagram with the essential parts of a TRNG. a TRNG (True Random Number Generator) contains an internal physical noise source. seed generation for Deterministic RNGs of classes K1 and K2 [6] The main requirements for the class P1 TRNGs are described by the AIS 31 Standard Statistical Tests document [4] and resumed as follow: random vectors formed from internal random numbers sequences pass the disjointness test T0 and the test procedure and evaluation rules specified in [4]. the P1 property requires the internal random numbers to be statistically inconspicuous. this must be detected immediately.7: AIS 31 Standard TRNG essential parts diagram Class P1 TRNGs TRNGs that belong to this class could be used in following type of applications: challenge-response protocols. For this purpose the AIS 31 Document Standard [4] describes the evaluation criteria for true (physical) random number generators. post-processing is not necessary and the digitized noise signal can be transmitted directly to the output block. it has to be prohibited that random numbers are output whose internal random sequence was generated completely after the total failure. The digitized noise signal can be transformed into an internal random number sequence by means of post-processing in order to improve the probability distribution of the digitized noise signal sequence. On the basis of different potential attack scenarios. random numbers. power supply.3.

the TRNG must trigger the online test itself. generation of DDS signature (private key x or random number k). the entropy test T8. if total failure of the noise source occurs while the TRNG is in operation. Test T1 (Monobit Test) 20000 X= ∑b j =1 j (3. is passed. From a sequence of 3145680 generated bits w1. The main requirements for the class P2 TRNGs are as described by the AIS 31 Standard Statistical Tests document [4] and resumed as follow: the TRNG belongs to class P1 with at least the same strength of mechanisms and functions. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . generation of session keys for symmetric encryption mechanisms. zero-knowledge proofs. …. w65535 ∈ {0.1}48 passes the disjointness test if the subsequent members are pairwise different. …. etc.Sweden 8 / 71 . Moreover. it shall not reduce the average entropy per bit. random padding bits. For detailed specification and how to apply the tests on the TRNG the original AIS 31 document [4] should be analyzed more carefully.True Random Number Generator based on a Sigma-Delta Modulator Class P2 TRNGs TRNGs that belong to this class could be used in following type of applications: generation of signature key pairs.2) The bit sequence b1. Tests to classify a TRNG under Class P1 and P2 are described as follow according to the AIS 31 document [4]: Test T0 (Disjointness Test) The sequence w1. it has to be prohibited that random numbers are output whose corresponding internal random sequence was generated completely after the total failure. AIS 31 Standard Statistical Tests For the purpose of choice of the subsequent Sigma-Delta structures on the actual work the specified statistical tests on AIS 31 document [4] will be used as quality parameters of the intended final solution. the above properties must also be verified under the intended external usage conditions (temperature. …. digitized noise signal sequences meet particular criteria or pass statistical tests intended to rule out features such as multi-step dependencies. w65535 numbers of 48 bits each one are built which are then compared one after other to check for the condition that one wn number is not equal to its preceding wn-1. b20000 passes the monobit test if 9654 < X < 10346. if mathematical post-processing is present. If this condition passes for all numbers the test is fulfilled. specified in [4]. statistical minimum properties of the digitized noise signal sequence must be proved each time the TRNG is started. generation of seeds for Deterministic RNGs in classes K3 and K4 [6]. power supply. an online test must be implemented with which the statistical quality of the digitized noise signal sequence can be checked.) insofar as these can influence the function of the noise source. It must be possible to trigger this online test externally or the TRNG must trigger at regular intervals.

1.….. …. Y = 16  15  .b4j-3 + 4. …. According to the null hypothesis. Under the null hypothesis. (s-1)} let fi[t]:=|{j: wij = t}|. ∑ f [i ]2  − 5000 5000  i =0  (3. and let pt:= (f1[t]+ … + fh[t])/(hn) be the relative frequency for the occurrence of t determined from the total of all samples. Furthermore.. i ∈ [0.. Run length Permitted Interval 1 2267 – 2733 2 1079 – 1421 3 502 – 748 4 233 – 402 5 90 – 223 ≥6 90 – 233 Table 3. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . the rejection limit is 15.1. wn ∈ {0.( s −1) ∑ ∑ ( f [t ] − np ) i t 2 /npt is approximately χ2-distributed with (h-1)(s-1) degrees of freedom. 5000 let cj = 8.1}k passes the uniform distribution test with parameters (k. the multinomial distributions on which the individual samples are based are identical.. n.15] .1}k n Test T7 (Comparative Test for Multinomial Distributions) (3. Test T3 (Run Test) A run is a maximum sub-sequence of consecutive zeroes or ones. (Please note that the sub-sequence b10001. The bit sequence b1. ….b4j-2 + 2. wi.Sweden 9 / 71 .03 < Y < 57.4) The bit sequence b1. a) if: 1 . b20000 passes the run test if the number of occurring lengths lies within the permitted intervals.13. From these 5000 numbers a frequency distribution for its values from 0 till 15 is built to later evaluate the Pocker Test parameter Y. …(s1)}. …. b20000 is not used in the test variable.. …..b4j-1 + b4j. Furthermore. The bit sequence b1. ….. …. The runs of zeroes and ones are evaluated separately..1: Limits for Run Test Test T4 (Long Run Test) A run of length ≥ 34 is called a long run.3) From a set of 20000 generated bits 5000 numbers cj are created each from 4 subsequent bits as stated. h} let the n-element sample wi.True Random Number Generator based on a Sigma-Delta Modulator Test T2 (Poker Test) For j = 1. j ≤ n | w j = x ∈ [2 − k − a . the test variable i =1. b20000 passes the long run test if no long run occurs. …. Test T5 (Autocorrelation Test) For τ ∈ {1.1. b20000 passes the Pocker Test (=χ2 modification test with 15 degrees of freedom ) if 1. In the special case where h = s = 2 and at the significance level α = 0. Zτ = 5000 j =1 ∑ (b j ⊕ b j+k ) (3. for t ∈ {0. as specified at the Table 3. 5000}.4. … .001.) Test T6 (Uniform Distribution Test) The sequence w1. f[i]:=| {j: cj=i} |.5) For each i ∈ {1. The bit sequence b1.h t = 0 . b20000 passes the autocorrelation test (with shift τ ) if 2326 < Z τ < 2674.2 −k + a ] for all x ∈ {0.n assume values from the set {0. ….

. cc ( L.3886906 0.4189794 13 3..3594433 0. wQ+K of length L.3856668 0.3909846 0.4229908 16 3.3901408 0. An is the distance from wn to its predecessor with the same value.9191004 5 3.3743782 0. if the noise source is independent.True Random Number Generator based on a Sigma-Delta Modulator Test T8 (Entropy Test) The entropy test is performed in accordance with Coron [4].2 L .3678269 0.3862500 0.3704039 9 3.3592384 0. b(Q+K)L is segmented into non-overlapping output words w1.976.3313257 0.3918905 0.4075860 11 3.3606982 0.4233308 infinite 3. K ) = d ( L) + K K (3.3919740 0.3822459 0.3914671 0.4237147 Table 3. ….4223549 15 3.3920729 e(L) 0. the two are equal.4381809 0. The bit sequence b1.1291382 6 3.3942629 10 3. and An = n if no i < n exist with wn=wn-i Or An = min {i | i ≥ 1. . a good approximation of the distribution of test variable fc 2 is provided by a normal distribution with expected value µc and variance ( τ c) : τ c = cc ( L.3592712 0.3619091 0.3516506 0.2547450 7 3.Sweden 10 / 71 .3282150 8 3.4211711 14 3.7) Where the parameters of the preceding equation 3.4050170 0.3920198 0. K ) Var ( g ( An )) e( L).4149476 12 3. the expected value for test variable fc is closely related to the entropy increase per L-bit block.5769918 4 2. K = 256000 and Q = 256 the test passes if fc ≥ 7.3660832 0. Indeed.3917390 0.3600222 0. wn = wn-i} in all other cases Test variable f: {0..7 are given by following Table 3. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .3593316 0.3592016 For the case of L = 8.3758725 0.1}(Q+K)L → R is determined for the Coron test by fc (S ) = − 1 Q+K 1 i −1 1 g ( An ) where g (i ) = ∑ ∑ k Q +1 log(2) k =1 k (3. For ideal noise sources.3640569 0.2: L Variance Var(g(An)) 3 2.3596484 0.2: Entropy Tests Parameters d(L) 0.6) For a stationary binary-value random source with a finite memory.

4. In addiction.1. Se(f). Simple first.order Sigma-Delta modulators are discussed. Extra bits of resolution can be extracted from converters that sample much faster than the Nyquist rate. A second advantage of oversampling converters is that they simplify the requirements placed on analogue anti-aliasing filters for A/D converters. Thus.2 Oversampling without Noise Shaping It is possible to show that extra dynamic range can be obtained by spreading the quantization noise power over a larger frequency range. To obtain much higher dynamic-range improvements as the sampling rate is increased. This trade-off becomes more desirable for modern submicron technologies with low power supplies where complicated high-speed digital circuitry is more easily realized in less area.1 Advantages of Oversampling Converters Oversampling A/D converters have become popular for high-resolution medium-to-low speed applications. the basics of oversampling converters are discussed. Fig. 4. Furthermore. However. such as e(n) being an independent white-noise signal. The quantization error is the difference between the input and output values. a sample-and-hold is usually not required at the input of an oversampling A/D converter. but the realization of high-resolution analog circuitry is complicated by low power-supply voltages and poor transistor output impedance (caused by short-channel effects). Quantization Noise Modelling It is possible to model a quantizer as adding quantization error e(n). In this item.1.1. as show in Fig. even though approximate. it has been found that this models leads to a much simpler understanding of Sigma-Delta modulators and with some exceptions is usually reasonably accurate. y(n). this extra resolution can be obtained with lower oversampling rates by spectrally shaping the quantization noise through the use of a feedback structure. With oversampling data converters. This model is exact if one recognizes that the quantization noise error is not an independent signal but may be strongly related to the input signal. is equal to the closest quantized value of x(n). The use of shaped quantization noise applied to oversampling signals is commonly referred to as Sigma-Delta modulation. 4.and second. the analogue components have reduced requirements on matching tolerances and amplifier gains. The spectral density of e(n). is white and all its power is within ±fs/2 as shown in Fig. where ∆ equals the difference between two adjacent quantization levels. followed by a discussion of which structure of the second-order Sigma-delta modulator should be used for the current development of a TRNG. this linear model becomes approximate when assumptions are made about the statistical properties of e(n). fs.Sweden 11 / 71 . However. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter 4.1. White Noise Assumption If x(n) is assumed uncorrelated and very active. The major reasons for their popularity include the following characteristics: oversampling converters relax the requirements placed on analogue circuitry at the expense of more complicated digital circuitry. noise shaping through the use of feedback can be used and is discussed on the following texts. The output signal.True Random Number Generator based on a Sigma-Delta Modulator 4. 4. e(n) can be approximated as an independent random number uniformly distributed between ±∆/2. but only 3dB for every doubling of the sample rate. x(n).1: Quantization Noise Modelling Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .1 Sigma-Delta Modulator Analog-to-Digital Converters 4. the quantization noise power equals ∆2/12 [38] and is independent of the sampling frequency.

3 dB.5 bits/octave. Fig. However. as shown in Fig. The reason for this SNR improvement through the use of oversampling is that when quantized samples are averaged together.7) The first term is the SNR due to the N-bit quantizer while the OSR term is the SNR enhancement obtained from oversampling. its maximum peak value without clipping is 2N(∆/2). doubling OSR decreases the quantization noise power by one-half or. 0. For this maximum sinusoidal wave.True Random Number Generator based on a Sigma-Delta Modulator Where kx in Fig. 4.1)  ∆  1 kx =    12  f s Oversampling without Noise Shaping (4.02 N + 1. the quantization noise power is reduced to: Pe = + fs / 2 − fs / 2 ∫ Se ( f ) H ( f ) df = ∫ k x df = 2 2 2 − f0 f0 2 f 0 ∆2 ∆2  1  =   f s 12 12  OSR  (4. Ps. y1(n) is filtered by H(f) to create the signal y2(n). This filter eliminates quantization noise greater than f0. 4. Here we see that straight oversampling gives a SNR improvement of 3 dB/octave or. We define the oversampling ratio. 4. whereas the noise portion adds as the square root of the sum of the squares. since the signals of interest are all below f0. as: OSR = fs 2 fo (4. noticing that the quantization noise is assumed to be a uniformly distributed spectrum over –fs/2 till fs/2. the signal power. the signal portion adds linearly.4) The power of the input signal within y2(n) remains the same as before since it was assumed the signal’s frequency content is below f0. the minimum sampling rate for signals band-limited to f0). Assuming the input signal is a sinusoidal wave. It is possible also to calculate the maximum SNR (in dB) to be the ratio of the maximum sinusoidal power to the quantization noise in the signal y2(n):  Ps  3  SNR max = 10 log  = 10 log 2 2 N  + 10 log(OSR )  Pe  2  Which is: (4.6) SNR max = 6. equivalently.5) Therefore.76 + 10 log(OSR ) (4.Sweden 12 / 71 .3) After quantization.2) Oversampling occurs when the signals of interest are band-limited to f0 yet the sample rate is fs. equivalently. where fs>2f0 (2f0 being the Nyquist rate or. has a power equal to:  ∆2 N  ∆2 2 2 N  = Ps =  2 2 8   2 (4. equivalently.1 is calculated by: + fs / 2 2 ∫ Se ( f )df = + fs / 2 − fs / 2 − fs / 2 ∫ k x df = k x f s = 2 2 ∆2 12 (4.2. OSR.2: Oversampling System without Noise Shaping Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .

as the continuous-time signal is inherently sampled by the switches and input capacitors on the switched-capacitor Sigma-Delta modulator.4a). This linearity is a result of a 1-bit A/D converter having only two output values and. The decimation filter can be conceptually thought of as a low-pass filter. it should be noticed that an internal D/A converter is used whose output signal is combined with the input signal. Xsh(t) (Fig.4c). the continuous-time signal. the overall linearity of this Sigma-Delta modulator converter depends strongly on the linearity of its internal D/A converter especially in the case that the Sigma-Delta modulator uses multi bit D/A converters. 4.1. 2f0. Following the antialiasing filter. and by throwing away samples. 4. which converts the oversampled low-resolution digital signal into a high-resolution digital signal at a lower sampling rate usually equal or a little higher than twice the frequency of the desired bandwidth of the input signal.3 Oversampling with Noise Shaping The system architecture of a Sigma-Delta oversampling A/D converter and its related signals are shown in Fig. In other words.3. Depicted on Fig4. 4. 4. the anti-aliasing filter can often be quite simple. However on this current work there is used a 1-bit D/A converter which is always linear and will not affect the linearity of the system as mentioned before. The resulting signal. it does not improve linearity [38]. the fourth block in the system is a digital decimation filter. 4. 4.4d) signal is resampled by a down sampler at 2f0 generating finally the output signal Xs(t) (Fig. As a result. 4.3: Block Diagram of a Low Pass Sigma-Delta oversampling A/D Converter Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .4e is an oversampling rate of 6. Note that this low-pass filter will also remove any higher-frequency signal content that was originally on the signal. It should be mentioned that in many realizations where the Sigma-Delta modulator is built using switchedcapacitor circuitry. This 1-bit digital signal is assumed to be linearly related to the input signal Xc(t) (Fig. since the bandwidth of the signal was assumed to be f0. and thus also acts as an anti-aliasing filter to limit signals to one-half the final output sampling rate. is sampled by a sample-an-hold circuit. since two points define a straight line. a separate sample-and-hold is not required. It is of interest to look at what element most strongly affects the linearity of this oversampling A/D system. Next the Xlp(n) (Fig. which converts the analog signal into a noise-shaped low-resolution digital signal Xdsm(n) (Fig. Xc(t) (Fig. which needed to only limit signals to frequencies less than fs/2.4. From the Sigma-Delta modulator. which generates Xlp(n) (Fig. This inherent linearity is one of the major motivations for making use of oversampling techniques with 1-bit A/D converters. When the oversampling ratio is large. Fig.4e) by simply keeping samples at a submultiple of the oversampling rate and throwing away the rest. This decimation process does not result in any loss of information. the spectral information is spread over 0 and π. the output from a 1-bit converter can be filtered to obtain a higher bit resolution. The first stage is a continuous-time anti-aliasing filter and is required to band-limit the input signal to frequencies less than the difference between the sampling frequency fs minus the input signal Xin(t) bandwidth f0 as depicted on the block diagram of Fig. However. 4.Sweden 13 / 71 .4b). 4.True Random Number Generator based on a Sigma-Delta Modulator While oversampling improves the signal-to-noise ratio. 4. 4. with a high enough sampling rate.4a). 4.4a). To remove this out-of-band quantization noise. no trimming or calibration is required. as opposed to the anti-aliasing filter at the input. the signal Xlp(n) has redundant spectra information since it is an oversampled signal where all of its spectral information lies well below π. is then processed by a Sigma-Delta modulator. Xc(t) (Fig. although it includes a large amount of out-of-band quantization noise.4d).

Sweden 14 / 71 .4: Signals and Spectra of the Low Pass Sigma-Delta oversampled A/D Converter Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .True Random Number Generator based on a Sigma-Delta Modulator Fig. 4.

At high frequencies. one called the Signal Transfer Function (STF) and the second defined as the Noise Transfer Function (NTF) which are given by following equations: STF ( z ) = Y (z) H ( z) = U ( z) 1 + H ( z) Y (z) 1 NFT ( z ) = = E ( z) 1 + H ( z) (4. it is possible to obtain first-order noise shaping by letting H(z) be a discrete-time integrator.9) it is possible to observe that the zeros of the noise transfer function are equal to the poles of H(z). 4. With such a choice.9) Fig.10) To shape the quantization noise in the case of a low-pass implementation. 4. there is certainly no reason to restrict ourselves to such implementations. This arrangement is known as an interpolative structure and is analogous to an amplifier realized using an operational amplifier and feedback. the feedback reduces the effect of noise of the output stage of the operational amplifier in the closed-loop amplifier’s output signal at low frequencies when the operational amplifier gain is high.True Random Number Generator based on a Sigma-Delta Modulator Noise Shaped Sigma-Delta Modulator A general noise-shaped Sigma-Delta modulator and its linear model are shown in Fig. From Fig. when H(z) goes to infinity. the quantization noise is reduced over the frequency band of interest while the signal itself is largely unaffected. Since the zeros of NTF(z) are equal to the poles of H(z). the noise is not reduced. will approximate unity over the frequency band of interest very similarly to an opamp in a unity-gain feedback configuration. Note that the quantizer is shown for the general case where many output levels occur. However.8) (4. SFT(z). has a zero at dc (z = 1). NTF(z). First-Order Noise Shaping The first-order noise shaping is realized when the noise transfer function. The high-frequency noise is not reduced by the feedback as there is little loop gain at high frequencies.8) and (4. the noise transfer function. the signal transfer function.5. NTF(z) will go to zero. While most present oversampling converters make use of 1-bit quantizers due to reasons already discussed. we choose H(z) such that its magnitude is large from 0 to f0. 4. will approximate zero over the same band. when the operational amplifier’s gain is low. NTF(z).5 it is possible two write to different transfer functions.5: A general Sigma-Delta Modulator (a) and its equivalent linear model (b) From equations (4. Specifically: Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . That means that. Furthermore.Sweden 15 / 71 . It is possible to write the output signal as the combination of the input signal and the noise signal as follow: Y ( z ) = STF ( z )U ( z ) + NFT ( z ) E ( z ) (4. Thus. additional post filtering can remove the out-of-band quantization noise with little effect on the desired signal. In this analogy. so that the quantization noise is high-pass filtered.

resumes into just a delay.16) Making the approximation that f0<<fs. a gain of 1.4).11) From a frequency domain view.True Random Number Generator based on a Sigma-Delta Modulator H ( z) = 1 z −1 (4.15) by:  πf  ∆2  1   Pe = ∫ Se ( f ) NFT ( f ) df = ∫    2 sin  12  f   f  s    s − fo − fo  fo 2 2 fo   df   2 (4.9) is: (4. the signal transfer function.02 N + 1. it comes out the high-pass function:  πf NFT ( f ) = 2 sin  f  s     (4. NTF(z). equivalently: Ps 3   3  = 10 log 2 2 N  + 10 log  2 (OSR ) 3  Pe π  2  (4.15) The quantization noise power over the frequency band from 0 to f0 is given using equations (4. The magnitude of the noise transfer function is given by: j 2π f fs − j 2π f fs z→e ⇒ NFT ( f ) = 1 − e = e jπ f fs −e 2j − jπ f fs ×2j×e − jπ f fs − jπ  πf  = sin  × 2 j × e fs  fs    f (4. from equation (4. equivalently. STF(z). the maximum SNR for this case is given by: SNR max = 10 log Or. from equation (4. so that it is possible to approximate sin(πf/fs) to be πf/fs:  ∆2  π 2  2 f 0  ∆2π 2  1  Pe =     12  3  f  = 36  OSR        s  3 3 (4.8) is: 1 Y ( z) STF ( z ) = = z − 1 = z −1 U ( z) 1 + 1 z −1 And the noise transfer function.19) It is possible to observe that doubling the OSR gives an SNR improvement for a first-order modulator of 9dB or.17 + 30 log(OSR ) (4.76 − 5.13) The signal transfer function. a high-pass filter. equivalently.Sweden 16 / 71 .17) Assuming the maximum signal power is the same as that obtained before in equation (4.1) and (4. is a discrete-time differentiator. while the noise transfer function.12) NTF ( z ) = 1 Y ( z) = = (1 − z −1 ) U ( z) 1 + 1 z −1 (4.14) Taking the magnitude of both sides.18) SNR max = 6. NTF(z).5 bit/octave. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . STF(z).

Sweden 17 / 71 .23) Assuming the maximum signal power is that obtained in equation (4. Fig. the maximum SNR for this case is: SNR max = 10 log Or. a gain of 2. equivalently. equivalently: Ps 3   5  = 10 log 2 2 N  + 10 log  4 (OSR ) 5  Pe 2  π  (4.11) is given by: STF ( z ) = z −2 And the noise transfer function is given by: (4.7 depicts the different noise-shaping functions reported till now.20) NTF ( z ) = (1 − z −1 ) 2 (4.22) This results in the quantization noise power over the frequency band of interest being given by: ∆2π 4 Pe = 60  1     OSR  5 (4.9 + 50 log(OSR ) (4.6 realizes second-order noise shaping.02 N + 1.6: Second-Order Sigma-Delta Modulator System The magnitude of the noise transfer function can be shown to be given by:   πf NFT ( f ) = 2 sin  f  s      2 (4.7: Different Noise Shaping Transfer Functions Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .76 − 12. For this modulator the signal transfer function using the same H(z) equation (4.21) Fig. 4.4). Fig.5bit/octave. 4. 4.25) By doubling the OSR the SNR for a second-order modulator is improved by 15 dB or.24) SNR max = 6. 4.True Random Number Generator based on a Sigma-Delta Modulator Second-Order Noise Shaping The modulator shown in Fig.

9 with the noise due to the 1st and 2nd stage switched-capacitor circuits (Et1(z) and Et2(z)) and the quantization noise from the 1-bit ADC (Eq(z)) at the output included in the model.True Random Number Generator based on a Sigma-Delta Modulator From Fig. 4.26) Setting H(z) with an appropriate transfer function there are three possible Sigma-Delta modulators that can be gotten from this structure which are given as follow: Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . Fig. 4.9: General structure of a Sigma-Delta Modulator with thermal and quantization noise modelling The general expressions for the transfer functions of this model are then as follow: NTFEq ( z ) = Y ( z) 1 = Eq( z ) 1 + 2 H ( z ) + H 2 ( z ) Y ( z) H 2 ( z) = Et1( z ) 1 + 2 H ( z ) + H 2 ( z ) Y ( z) H ( z) = NTFEt 2 ( z ) = Et 2( z ) 1 + 2 H ( z ) + H 2 ( z ) NTFEt1 ( z ) = STF ( z ) = Y ( z) H 2 ( z) = U ( z) 1 + 2H ( z) + H 2 ( z) (4. 4. 4.4 Sigma-Delta Modulator and Noise Modelling The present work proposes a new method to generate random numbers in which a Sigma-Delta modulator ADC is used to filter out the natural thermal noise present on the switched capacitors which further is processed by a digital signal processing block to give out the random bit stream. For this reason as first solution approach for this work further analysis will be done using a second-order Sigma-Delta modulator system which has also a better controllable parameterization by choosing the appropriate circuit structure.8: TRNG with a Sigma-Delta Modulator A/D Converter Consider the general structure of a two stage Sigma-Delta modulator as shown in Fig.25). the second order system is unconditionally stable in opposite to higher order systems which stability needs to be certified and the behaviour of the real second order system approaches much more to the ideal system model compared to the real first order system behaviour to the ideal system model [38 39]. The overall system view with Sigma-Delta Modulator ADC for use as a TRNG is shown in Fig.8. which turns into a better SNDR for the system as it can be compared between equations (4. 4. Fig.1.7 is it possible to observe that the second order system has a better noise-shaping function compared to the first-order system on the bandwidth on interest f0 for the case of a Low Pass Sigma-Delta Modulator. Additionally. 4.Sweden 18 / 71 .19) and (4.

From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical value calculated by equation (4.  3 ( 2 L + 1)  SNRtheoretical = 10 log OSR ( 2 L+1)  . for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements.5 ω [x(2 rad/s] π) |NTF Et1(z=e )| 4 3 2 1 0 0 0.29) does not take into account non-linearity’s on the real system. 4.True Random Number Generator based on a Sigma-Delta Modulator 4.11 is generated. The left graphic on Fig.29) taken from reference [40] and the simulated value due to the fact that the equation (4. where L is the order of the system  2 ( 2 L)π  Magnitude (4. 4. The right graphic on Fig 4.5 ω [x(2 rad/s] π) |NTF Et2(z=e )| 4 Magnitude 3 2 1 0 0 0.2 Second Order Low Pass Sigma-Delta Modulator For H ( z) = z −1 1 − z −1 (4.10: Transfer functions frequency response for the 2nd Order Low Pass Sigma-Delta Modulator Applying a sinusoidal signal with frequency equal to 2π/ratio/OSR/2 [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig. STF ( z ) = z −2 (4.27) The general expressions for the transfer functions translate into: NTFEq ( z ) = (1 − z −1 ) 2 .11 presents the SNDR curves at the low frequency bandwidth of interest for different oversampling rates from 4 to 256 calculated by applying different sinusoidal signal amplitudes from -100dB to 0dB into the modulator’s circuit depicted of Fig. 4.10: |NTF Eq(z=e )| 4 Magnitude 3 2 1 0 0 0. As it is possible to see.11 shows the maximum SNDR obtained for the used oversampling rates. NTFEt 2 ( z ) = z −1 (1 − z −1 ). NTFEt1 ( z ) = z −2 .5 ω [x(2 rad/s] π) 1 jω 1 1 Fig.5 ω [x(2 rad/s] π) 1 jω jω 3 2 1 0 0 0.9 using equation (4.27) for H(z).28) Whose spectra when applying the transformation |STF(z=e )| 4 Magnitude jω z = e jϖT for T = 1 can be seen on following Fig. 4.Sweden 19 / 71 . but still gives a reasonable approach to the behaviour and quantification of the SNDR on the real system.29) Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 4.

11: SNDR for different OSR on a 2nd Order Low Pass Sigma-Delta Modulator 4.3 Fourth Order Band Pass Sigma-Delta Modulator To get a Band Pass Sigma-Delta Modulator a discrete-time low-pass-to-band-pass transformation [3] can be used: z→ − z( z + a ) az + 1 − 1 < a < 1 .True Random Number Generator based on a Sigma-Delta Modulator Lowpass 2nd Order SDM.31) NTFEt1 ( z ) = NTFEt 2 ( z ) = − az − ( 2a + 1) z − 3az 1 + 2az −1 + a 2 z −2 2 −1 −2 −3 −z −4 a 2 z −2 + 2az −3 + z −4 STF ( z ) = 1 + 2az −1 + a 2 z −2 Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . The general expressions for the transfer functions of this model are then as follow: NTFEq ( z ) = 1 + 4az −1 + (2 + 4a 2 ) z −2 + 4az −3 + z −4 1 + 2az −1 + a 2 z −2 a 2 z −2 + 2az −3 + z −4 1 + 2az −1 + a 2 z −2 (4. OSR = 4 8 16 32 64 128 256 Theoretical Simulated 100 100 80 80 SNDR [dB] 60 SNDR [dB] 60 40 40 20 20 0 -100 -80 -60 Vin [dB] -40 -20 0 0 10 1 10 OSR 2 Fig. 4.30) Where the case a = 0 generates z → − z . OSR = 4 120 8 16 32 64 128 256 120 Lowpass 2nd Order SDM. Negative a gives systems closer to DC and positive a gives systems with passband closer to π. By choosing a = 0 the Band Pass Sigma-Delta Modulator is placed exactly over π/2 which simplifies further digital signal processing algorithms. which gives: H ( z ) = 2 − az −1 − z −2 1 + 2az −1 + z −2 (4.Sweden 20 / 71 .

13: SNDR for different OSR on a 4th Order Band Pass Sigma-Delta Modulator Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 4.5 ω [x(2 ) rad/s] π |NTF Et2(z=e )| jω jω 1 1 Fig.5 ω [x(2 ) rad/s] π 1 4 3 2 1 0 0 0.12: |NTF Eq(z=e )| 4 3 2 1 0 0 0. OSR = 4 8 16 32 64 128 256 100 100 80 80 SNDR [dB] 60 SNDR [dB] 60 40 40 20 20 0 -100 -80 -60 Vin [dB] -40 -20 0 0 10 1 10 OSR 2 Fig. 4.5 ω [x(2 ) rad/s] π |NTF Et1(z=e )| 4 Magnitude Magnitude 3 2 1 0 0 0.pi/4) + (2.5 ω [x(2 ) rad/s] π 1 jω jω z = e jϖT for T = 1 can be seen on following Fig.Sweden 21 / 71 .12: Transfer functions frequency response for the 4th Order Band Pass Sigma-Delta Modulator Applying a sinusoidal signal with frequency equal to ( (2.pi/ratio/OSR/4) ) [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig.13 is generated: Bandpass 4th Order SDM. 4.True Random Number Generator based on a Sigma-Delta Modulator Whose spectra when applying the transformation |STF(z=e )| 4 Magnitude Magnitude 3 2 1 0 0 0. OSR = 4 120 8 16 32 64 128 256 120 Theoretical Simulated Bandpass 4th Order SDM. 4.

5 ω [x(2 rad/s] π) |NTF Et2(z=e )| 4 Magnitude 3 2 1 0 0 0.(2.14: Transfer functions frequency response for the 2nd Order High Pass Sigma-Delta Modulator Applying a sinusoidal signal with frequency equal to ( pi . 4. 4.13 shows the maximum SNDR obtained for the different used oversampling rates. 4.5 ω [x(2 rad/s] π) 1 jω jω |STF(z=e )| 4 Magnitude 3 2 1 0 0 0.5 ω [x(2 rad/s] π) |NTF Et1(z=e )| 4 Magnitude 3 2 1 0 0 0. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .9 using the equation (4. 4.33) Whose spectra when applying the transformation z = e jϖT for T = 1 can be seen on following Fig.29) from [40] and the simulated value for the cases of oversampling rates lower than 64 whose reasons were already explained previously.13 presents the SNDR curves at the band pass frequency bandwidth of interest for different oversampling rates from 4 to 256 calculated by applying different sinusoidal signal input amplitudes from 100dB to 0dB into the modulator’s circuit depicted of Fig. As it is possible to see. 4. STF ( z ) = z −2 (4. again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements. From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical value calculated by equation (4.14: |NTF Eq(z=e )| 4 Magnitude 3 2 1 0 0 0. The right graphic on Fig 4.15 is generated.True Random Number Generator based on a Sigma-Delta Modulator The left graphic on Fig.30) for H(z) with parameter a set to zero to get a bandwidth of interest with central frequency on π/2 [rads/s]. 4.pi/ratio/OSR/2) ) [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig.32) The general expressions for the transfer functions translate into: NTFEq ( z ) = (1 + z −1 ) 2 . NTFEt1 ( z ) = z −2 .4 Second Order High Pass Sigma-Delta Modulator For H ( z) = − z −1 1 + z −1 (4. NTFEt 2 ( z ) = − z −1 (1 + z −1 ).Sweden 22 / 71 .5 ω [x(2 rad/s] π) 1 jω jω 1 1 Fig.

4.True Random Number Generator based on a Sigma-Delta Modulator The left graphic on Fig. 4. if it is considered that the noise present in the circuit is just composed of thermal and quantization noise then due to their uniform distributed spectral characteristics it would be possible to apply directly a Low Pass Sigma-Delta Modulator and the appropriate digital signal processing filters to obtain a final noise spectrum at the output composed by just thermal noise with the remaining quantization noise damped as much as possible with a magnitude as low as possible compared to the thermal noise.15 presents the SNDR curves at the high frequency bandwidth of interest for different oversampling rates from 4 to 256 calculated by applying different sinusoidal input signal amplitudes from 100dB to 0dB into the modulator’s circuit depicted of Fig. The further analysis then should be to find out which of the two appointed structures: band pass or high pass give out the best uniform distributed spectrum at the bandwidth of interest for later generation of the random output bit stream considering the amount of chip area. digital signal processing truncation noise. but it should be remembered that the high pass system in this case is a 2nd order system compared to 4th order band pass system which requires more area. OSR = 4 120 8 16 32 64 128 256 120 Highpass 2nd Order SDM. 4. Highpass 2nd Order SDM. OSR = 4 8 16 32 64 128 256 Theoretical Simulated 100 100 80 80 SNDR [dB] 60 SNDR [dB] 60 40 40 20 20 0 -100 -80 -60 Vin [dB] -40 -20 0 0 10 1 10 OSR 2 Fig.32) for H(z). Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . The right graphic on Fig 4.15 shows the maximum SNDR obtained for the different used oversampling rates.Sweden 23 / 71 . power consumption.13 and 4.15 it is possible to observe that the band pass Sigma-Delta modulator has a slightly 6dB SNDR advantage over the high pass one for oversampling rates greater than 64. again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfil the AIS 31 Standard Statistical Tests requirements. circuitry and power consumption on the die. From previous Figs. switched-capacitors thermal noise. operational amplifier thermal noise and the intrinsic flicker noise [38 52 53 54 55 56 57 58 59 60 61] which yields to the use of Sigma-Delta modulators that work in band frequencies where these remaining noise sources have less power magnitude than the circuit’s thermal noise. required digital-signal processing filters and influence of the flicker noise at the output of each system. 4. Taking into account the last observation then from the possible analyzed Sigma-Delta modulators the suitable ones to this application would be the band pass or the high pass structures. As it is possible to see. But in a real application the total noise of the circuit is the summation of the power of the theoretical loop quantization noise.9 using the equation (4. complexity to build the circuit.15: SNDR for different OSR on a 2nd Order High Pass Sigma-Delta Modulator In a first system structure analysis.

5. Fig. where M = 1 OSR 4 and OSR = fs 2 f0 (4. 4. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .34) is the integer ratio of fs to 8f0.34) TSinc Filter Transfer Functions 0 -50 -100 -150 Magnitude [dB] -200 -250 -300 -350 -400 -450 M = 64. and thus it is also a linear-phase filter [38].16: Usual Sigma-Delta Modulator Output Decimation Processing System The TSinc Filter block removes much of the quantization noise such that the output can be downsampled later. L = 2 M = 64.4 0.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures 4. 4.True Random Number Generator based on a Sigma-Delta Modulator 4. In addiction. L = 4 0 0.Sweden 24 / 71 .2 0. implying it is a FIR-type filter.16.8 1 Fig.34) taken from [38] and shown in Fig. The TSinc Filter block is a cascade of L+1 (L is equal to order of the Sigma-Delta modulator) averaging filters with the following transfer function TSinc(z) given on next equation (4. 4. It is important to notify that the impulse response of this filter is finite.1 Digital Signal-Processing Decimation Filter Structure One usual approach [38] to digital signal process the output of a Sigma-Delta modulator system is shown in Fig.17: TSinc transfer functions for OSR = 256 with L = 2 and L = 4 Note that the factor M in equation (4.6 ω [xπ rad/s] 0. all of its impulse response coefficients are symmetric.17 for OSR = 256 and cases L = 2 and L = 4:  1 − z−M TSinc( z ) = ( L +1)   1 − z −1 M  1     ( L +1) . 4.

. the slope of the attenuation for this low pass filter should be greater than the rising quantization noise. (i. the noise would be the integrated over a very large bandwidth usually causing excessive total noise [38].Sweden . Therefore.. lead to a family of filters that exhibits odd symmetry around π/2 and whose impulse response h(n) have zero values for all even values of n except n = 0.18. these filters can be implemented with half the number of multiplications than arbitrary choices of filter designs.True Random Number Generator based on a Sigma-Delta Modulator The reason for choosing to use L+1 of these averaging filters in cascade is similar to the argument that the order of an analogue low-pass filter in an oversampling D/A converter should be higher than the order of the SigmaDelta modulator. Fig. so that the resulting noise falls off at a relatively low frequency.35) These properties. 4. Specifically. They are appropriate for sampling rate conversion ratios 2:1 and are useful for higher rate stages of multirate decimators or interpolators where conversion ratios of 2 occurs in each stage. 4. 4.18: Design Criteria for each stage Half Band Filter The previous Sigma-Delta modulator output decimation processing system depicted on Fig.36) 25 / 71 Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . δp = δs ) and that the cutoff frequencies are symmetrical around π/4 such that: ω p + ωs = π 2 (4. Otherwise. δp = δs ) and that the cutoff frequencies are symmetrical around π/2 such that: The Half Band Filter is characterized by the constrains that their passband and stopband ripples are the same ω p + ωs = π (4. Fig.e.e. where the two previous half filters were converted into a one fourth band filter including the TSinc compensation transfer function. illustrated in Fig. 4.19: Simplified Sigma-Delta Modulator Output Decimation Processing System The One Fourth Band Filter is characterized by the constrains that their passband and stopband ripples are the same (i. 4.16 can be simplified by transforming the last three filter stages into one like depicted on Fig.19 for simulation simplification purposes.

as well as the One Fourth Band Filter with TSinc Compensation and the final product of both filter transfer functions at the output of the DSP decimation filter.246 0.True Random Number Generator based on a Sigma-Delta Modulator Fig.5 ω [xπ rad/s] 0. 4. One Fourth Band Filter with TSinc Compensation and the final product of the transfer functions. On the following Fig.5 Magnitude [dB] -1 -1.6 0.258 0.4 0.2 0.2 0 0 0.1 0.6 ω [xπ rad/s] 0.8 0.26 anti-TSinc One Fourth Band Filter TSinc Filter (M = OSR/4) Product 50 0 -50 Magnitude [dB] -100 -150 -200 -250 -300 -350 anti-TSinc One Fourth Band Filter TSinc Filter (M = OSR/4) Product 0 0.6 0. 4.7 0.8 0.3 0.21 it is possible to see the TSinc transfer function frequency response for the case of L = 2 and OSR = 256.20: Design Criteria for the One Fourth Band Filter As mentioned the One Fourth Band Filter has included into its final transfer function the TSinc Compensation function.5 -4 0.2 1 Magnitude 0.254 0.8 1 1 0. 4.4 anti-TSinc One Fourth Band Filter TSinc Filter (M = OSR/4) Product 1.5 0 -0. 1.2 0.Sweden 26 / 71 . Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .5 -2 -2.244 0.21: Spectrums from the TSinc Filter (OSR = 256.9 1 Fig.24 0. L = 2).4 0.5 -3 -3.4 0.25 ω [xπ rad/s] 0.256 0.242 0.248 0.252 0.

as it will be seen further.5. From this physical phenomenon the total thermal noise mean-squared value on a capacitor [48] is calculated as: 2 Vnoise ( rms ) = kT . For this actual analysis it will be considered just the thermal noise generated by the switched-capacitors. Fig. Quantization Noise and Oversampling Rate Analysis With the previous simplified Sigma-Delta modulator output decimation processing system. In this work instead. 4. one applying the high pass Sigma-Delta modulator and the other one applying the band pass Sigma Delta modulator structures were built to find out which is the minimum required oversampling rate that generates a Sigma-Delta modulator output’s spectrum flatten enough to further fulfill the AIS 31 Standard Statistical Tests. C T is the temperature in Kelvin and C is the capacitor size given in Fahrads. two different simulation structures depicted in Fig. either the temperature must be lowered or the capacitance value must be increased. where k is the Boltzmann constant (1.Sweden 27 / 71 .22b. Thus.22a and Fig. to lower the noise level.22b that the outputs of the Sigma-Delta modulators must be multiplied by an appropriate sinus signal to modulate the signal Y(z) down to the low frequency baseband of work of the low pass decimation filter system.22 Simulation Structures for the Band Pass and High Pass Sigma-Delta Modulator Systems Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 4. later the switching-transistors’ flicker noise will be introduced on the model.38x10-23 J/K). the thermal noise generated by the switched-capacitor must be as high as possible.37) It should be stated that this noise phenomenon for capacitors gives a fundamental limit on the minimum noise level across a capacitor. 4. 4. 4. (4. It should be noticed as depicted on Fig.2 Thermal Noise.True Random Number Generator based on a Sigma-Delta Modulator 4.22a and Fig. Remembering that the proposed work uses the thermal noise to generate random numbers one possible source comes from the switched-capacitors on the modulator circuit structure. but there are some limitations on the capacitor’s size concerning their relation to the flicker noise generated by the switching-transistors.

23 that oversampling rates greater or equal to 128 generate noise power spectrums that start to approximate to a flatten white noise power spectrum desired for the this application.4 0.12 and 4.Sweden 28 / 71 . C (4.4 0.22: Output’s spectra for different oversampling rates using a 4th order Band Pass Sigma-Delta Modulator and a 2nd order High Pass Sigma-Delta Modulator Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .4 0.4 0.37) it is possible to conclude that the thermal noise scaling factor on Fig.6 ω [xπ rad/s] 0.31) and (4. On the other hand that means that the integrating-capacitor’s size on the modulator’s first stage will have a greater influence on the final output spectrum if the same integrating-capacitor size is used for both stages.8 1 2nd Order High Pass Sigma-Delta Modulator OSR =64 -100 -110 -120 OSR =128 -100 -110 -120 -130 -100 -110 -120 -130 Magnitude [dB] -140 -150 -160 -170 -180 Thermal Noise Sigma-Delta Modulator Decimated Output 0 0.2 0. 4.38) It should be remembered from Figs.4 0.2 0.2 OSR =256 Magnitude [dB] Magnitude [dB] Thermal Noise Sigma-Delta Modulator Decimated Output 0 0.33) for the transfer function NTFEt2(z) that the thermal noise generated by the capacitors that belong to the second stage for these Sigma-Delta modulator structures is shaped and is not appropriate to the generation of random numbers.8 1 -190 -200 0 0.22 is equivalent to the thermal noise generated by all the capacitors from the first stage of the switched-capacitor Sigma-Delta modulator circuit structure calculated by: Thermal Noise Scaling Factor = kT . 4.2 0.2 0.4 0.6 ω [xπ rad/s] 0. Performing some simulations with both Sigma-Delta modulator structures it is possible to see from the decimated output spectra on Fig.6 ω [xπ rad/s] 0.8 1 -130 -140 -150 -160 -170 -180 -140 -150 -160 -170 -180 -190 -200 Thermal Noise Sigma-Delta Modulator Decimated Output 0. but before that there is still open which kind of digital bit stream generator is going to be used after the decimation filter system and how the switching-transistors’ flicker noise influences the AIS 31 Standard Statistical Tests results. Later on this work.8 1 Fig.8 1 -180 -190 Thermal Noise Sigma-Delta Modulator Decimated Output 0 0.True Random Number Generator based on a Sigma-Delta Modulator From equation (4. 4th Order Band Pass Sigma-Delta Modulator OSR =64 -100 -110 -120 Magnitude [dB] OSR =128 -100 -110 -120 -130 Magnitude [dB] -140 -150 -160 OSR =256 -100 -110 -120 -130 Magnitude [dB] -140 -150 -160 -170 -130 -140 -150 -160 -170 -180 -170 Thermal Noise Sigma-Delta Modulator Decimated Output 0 0. To certify this advantage a further AIS 31 Standard Statistical Tests analysis over the generated output bit stream needs to be performed. 4. This happens because at considerable higher oversampling rates the thermal noise turns dominant in the spectrum once the quantization noise is damped and shaped by the Sigma-Delta modulator transfer function to lower magnitudes compared to the thermal noise. For these first simulations it was considered a temperature of 300 K and a capacitor of the size of 10fF.6 ω [xπ rad/s] 0. 4.6 ω [xπ rad/s] 0.2 0. these two parameters and specially the last one will be modified to analyze their influence on the performance of the final electronic circuit design and over the AIS 31 Standard Statistical Tests results.6 ω [xπ rad/s] 0. If necessary the first stage switched-capacitors could be scaled even more down to get a higher non-shaped thermal noise at the output of the modulator. It is also possible to percept that the high pass Sigma-Delta modulator has a slightly advantage over the band pass Sigma-Delta modulator once the first structure requires a lower oversampling rate to achieve a flat spectrum with a lower order system transfer function which yields to two less operational amplifiers and less additional circuitry on a real system.14 and equations (4.8 1 -180 -190 Thermal Noise Sigma-Delta Modulator Decimated Output 0 0.

5. Greater N values could not be simulated due to the extensive amount of time and computation capacity that it would take which is beyond the purpose of this work and was left for future studies.22 with a oversampling rate set to 256. In this case the digital output stream Bit Rate would be given by the following equation: BitRateGauss − Distrib−Comparator = 2 f 0 log 2 ( N ) for N = c.True Random Number Generator based on a Sigma-Delta Modulator 4.24 shows the definition of parameter N as the number of areas by which the Gauss distribution of the decimation filter output in subdivided. 4. but for simplification purposes and due to limited amount of time and computing processing capacity further simulations used the “Zero-Cross Comparator” algorithm to generate the digital random bit stream output.Sweden 29 / 71 . 4. Fig. By applying just thermal noise at the input of the system depicted on Fig. Additionally analysis would be required to measure the upper N value limit.39) Fig.40) is twice the integral of the Gauss Distribution function for variation σ(x) = ½ and mean value Ē{x} = 0. performing a first set of simulations with a band pass and a second set with a high pass Sigma-Delta modulator ADC using in both the proposed “Gauss Distribution Comparator” algorithm at the output of the decimation filter it has shown that for values of N set from 4 to 262144 all AIS 31 Statistical Standard Tests where fulfilled certifying until this maximum value that the “Gauss Distribution Comparator” algorithm works.24: Areas definition on the Gauss Distribution Function for σ = ½ and Ē{x} = 0 of the output signal from the DSP Decimation Filter for the cases of N equal to 4 and 8. as well as how the areas are calculated and defined under the same distribution.40) It should be noticed that equation (4. which gives a digital output stream Bit Rate equal to: BitRateZero −Cross −Compator = 2 f 0 (4. Nevertheless this first maximum N value limit shows that these 256 times oversampled with either high pass or band pass Sigma-Delta modulator ADC structures achieve a resolution greater or equal than 18 bits which mainly comes from its high order decimation filter output systems and enables the lost bit rate due to oversampling method to be recovered by applying this algorithm without loss of entropy. 4. where c = 2i i ∈ Ν* + (4. The coefficients ci are calculated through the Error Gauss Distribution Area Function [73] defined by: erf = 2 π ∫e 0 x −t 2 dt (4. The first was applying a simple “Zero-Cross Comparator” algorithm to generate the output bit states one and zero. That means also that for this upper N limit it would be possible to generate 18 random bits for one decimated output value from the Sigma-Delta modulator ADC.38) The second approach was using a here named “Gauss Distribution Comparator” algorithm which translates one decimated output sample value into one or more bits depending on how many areas the Gauss distribution of the decimated output signal was divided. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .3 Choice of the Digital Bit Stream Generator System and Analysis To translate the decimated output signal of the Sigma-Delta modulator ADC into a digital bit stream two digital post-processing system approaches were taken.

For this reason. flicker noise may assume considerably different values and as such varies from one CMOS technology to another.26 Flicker Noise Spectrum Unlike thermal noise. flicker noise is also called 1/f noise. 4. 4. As shown in Fig.43) Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . Fig. some are randomly trapped and later released by such energy states.28.42):  K 1 1 Vn2 =  tech  = (K 2 ker ) flic  C WL  f f  ox  (4. as exemplified on Fig. To analyze the Flicker noise influence over the Sigma-Delta modulator structure and over the results of AIS 31 Standard Statistical Tests.26 the Flicker noise has a stronger influence over the low and medium band frequencies which suggests that the high pass Sigma-Delta modulator would return better AIS Standard Statistical Tests results compared to the band pass Sigma Delta modulator structure.25. W is the width and L the length of the device. In addition to trapping.42) on the area of the transistor WL suggests that to decrease flicker noise. the Flicker noise equation is somewhat more complex [4].True Random Number Generator based on a Sigma-Delta Modulator 4.42) is only an approximation and in reality.26 the noise spectral density is inversely proportional to the frequency. several other mechanisms are believed to generate flicker noise [4]. a flicker filter (-10dB/dec) transfer function was designed and added to the simulation system model depicted on Fig. As shown in Fig 4.e. The flicker noise is more easily modelled as a voltage source in series with the transistor’s gate [48] and roughly given by the power spectral density equation (4. 4. the device area must be increased. introducing flicker noise in the drain current. By multiplying half of the system sampling frequency fs by the α parameter one determines the Flicker Noise Corner Frequency of the system.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests The flicker noise is not a totally modelled phenomenon nonetheless one main physical behaviour that could describe it happens in the interface between the gate oxide and the silicon substrate in a MOSFET. this difference between PMOS and NMOS transistors is not consistently observed [48]. 4. It is also believed that PMOS devices exhibit less Flicker noise than NMOS transistors because the former carry the holes in a buried channel. Cox it the capacitance per unit area. many dangling bonds appear. The inverse dependence of equation (4. giving rise to extra energy states as shown of Fig.28.Sweden 30 / 71 . it comes to: K2 kT 1 = flic ker C fs f Flic ker Corner 2 ⇒ f Flic ker = α f s Corner 2 ⇒ K flic ker = α kT C 0 <α <1 (4.42) Where Ktech is a process-dependent constant of the order of 10-27 V2F for 90nm technology [52 53 54 55 56 57 58 59 60 61]. As charge carriers move at the interface. Depending on the cleanness of the oxide-silicon interface.25 Dangling Bonds at the Oxide-Silicon Interface Fig. i. Nonetheless. The α and Kflicker parameters are defined on equations (4. 4. the average power of flicker noise can not be predicted easily.43) and graphically shown on Fig. For the case in which the thermal and flicker noise densities spectra have the same magnitude for a given α value.5.42) and (4. Since the silicon crystal reaches an end at this interface. 4.27 followed by an adjustable Flicker Noise Scaling Factor (Kflicker) parameter that for analyses purposes will be related to a new defined α parameter that represents the ratio between the frequency at which the flicker noise density spectrum magnitude is equal to the thermal noise density spectrum magnitude and half of the desired system sampling frequency. Equation (4. at some distance from oxide-silicon interface. 4..

44) calculate the maximum area of the switching transistors. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .27 Modified Simulation System Structure for the Band Pass and High Pass Sigma-Delta Modulators including the Thermal & Flicker Noise Sources Fig.εr relative permeability of the material in this 90nm technology equal to 3.3nm. . 4.tox thickness of the gate dioxide to the channel of the transistor for 90nm technology equal to 1.9.Ktech process-dependent constant on the order of 10-27 V2F for the 90nm technology. . From equation (4.27 and from there on using equation (4.Sweden 31 / 71 .43) it is possible to define a relation between the area of the transistors and the size of the switched-capacitors in use as follow: K 2 ker = flic Where: K tech K tech ⇒ WL = CoxWL  ε oε r  kT    t  C α     ox  0 <α <1 (4.εo permeability constant equal to 8.42) and (4.44) .43) for a given parameter α and integrating-capacitor C values it is possible to calculate the Kflicker constant which is defined as the Flicker Noise Scaling Factor on the model of Fig.85x10-12 F/m. 4. .28 Parameter α definition and concept of Flicker Noise Corner Frequency From equations (4.True Random Number Generator based on a Sigma-Delta Modulator Fig. 4.

Beside this characteristic the band pass Sigma-Delta modulator would use twice operational amplifiers to get a 4th order system which yields to more area. 4.29 it is also possible to predict that the flicker noise will have a much higher influence on the final AIS31 Standard Statistical Tests for the band pass Sigma-Delta modulator that works in a frequency range two times lower than that for the high pass Sigma-Delta modulator structure. time and complexity to design the overall circuit.29 in the case a integrating-capacitor of 25fF is used on the switched-capacitor circuit. 4.1 and Fig.29 Total [black].30.0002 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 C [fF] 100 80 60 40 20 0.30 and to calculate the total noise power density spectrum generated by the flicker and thermal noises as depicted on Fig. 4. Fig.0005 0.0001 0 1 1 1 1 Table 4.001 0. From the previous Table 4.005 0. power consumption. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 4.Sweden 32 / 71 .1 and equation (4.1: Fulfilled or not fulfilled complete set of AIS 31 Standard Statistical Tests for different Flicker Noise Corner Frequency α parameter and integrating-capacitor values using the High Pass Sigma-Delta Modulator structure with a oversampling rate of 256 and system sampling frequency fs of 25MHz From Table 4. Thermal [blue] and Flicker [red] Noise Power Density spectra for a capacitor of 25fF and different Flicker Noise Corner Frequency α parameter values. 4. Parameter α 0.44) it is possible to find out for different α parameters values the transistor areas for the technology of 90nm as shown in Fig.1 and Fig.True Random Number Generator based on a Sigma-Delta Modulator Using for simulation time processing reduction the previous defined “Zero-Cross Comparator” algorithm and generating some sets of 6 million output bit streams from the high pass Sigma-Delta modulator ADC system for different α parameter and integrating-capacitor C values it is possible to find out which are the switched-capacitor values that fulfil the complete set of AIS 31 Standard Statistical Tests as well as determines the estimated optimal area of the transistors as shown on Table 4.002 0. flicker noise.

30 Normalized Transistors’ Area on 90nm technology for different Flicker Noise Corner Frequency α parameter values using a capacitor of 25fF Table 4.001 and integrating capacitor set to 25fF on the High Pass Sigma-Delta Modulator with a oversampling rate of 256 and system sampling frequency fs of 25MHz Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .648 Χ2(2) = 0.264 Χ2(2) = 0.3 Χ2(4) < 15.28. Normalized Transistor Area versus α parameter | C = 25fF 1000 900 800 700 600 WL / (WL α=0. its design and circuit implementation. As it is possible to see all tests are fulfilled for this case.020 Χ2(1) < 15.001 Χ = 0.7 Test 3 Long Run < 34 2326 < MaxCorr < 2674 Χ < 0.498 All passed Long Run = 1 MaxCorr(4075) = 2572 Χ = 0.1) 500 400 300 200 100 0 -4 10 10 α -3 10 -2 Fig.025 Χ < 0.005 Χ2(1) = 5.3 SE > 7. AIS 31 Standard Statistical Tests Test 0 (Disjointness Test) Test 1 (Monobit Test) Test 2 (Pocker Test) Test 3 (Run Test) Test 4 (Long Run Test) Test 5 (Autocorrelation) Test 6a (Empirical distribution for 1 disjoint sub-sequences) Test 6b (Emprcl distb 2 disj s-s) Test 7a (Emprcl dstrb 4 disj s-s) Test 7a (Emprcl dstrb 4 disj s-s) Test 7b (Emprcl dstrb 8 disj s-s) Test 7b (Emprcl dstrb 8 disj s-s) Test 7b (Emprcl dstrb 8 disj s-s) Test 7b (Emprcl dstrb 8 disj s-s) Test 8 (Strong Entropy) Result Passed Monobit = 9986 Χ = 4. 4.2 shows the results of AIS 31 Standard Statistical Tests ran over 6 million random bits generated by the high pass Sigma-Delta modulator with integrating capacitor set to 25fF and Flicker Noise Corner Frequency parameter α set to 0. 4.3 Χ2(1) < 15.03 < Χ < 57.3 Χ2(2) < 15.001 using the third order TSinc FIR filter together with the One Fourth Band with TSinc compensation FIR Filter and “Zero-Cross Comparator” algorithm on the system simulation model on Fig.986 Χ2(1) = 0.3 Χ2(3) < 15.925 SE = 369.Sweden 33 / 71 .976 Table 4.228 Χ2(4) = 0.3 Χ2(2) < 15.True Random Number Generator based on a Sigma-Delta Modulator Taking into account these observations and from the previous analysis the work is going to be conducted studying the high pass Sigma-Delta modulator topology structure.4 Limits section 3.2: Fulfilment of all AIS 31 Standard Statistical Tests for α = 0.339 Limits Passed or not Passed 9654 < Monobit < 10346 1.269 Χ2(3) = 6.

1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure From the previous analysis on section 4.1) From [38] the following circuit on Fig. 5.2) For C1 = C2 this system can be modelled as depicted on Fig.1 gives a similar transfer function for the Low Pass Sigma-Delta Modulator structure that needs to be modified on its pole for the new implementation as a High Pass version: Fig. the new system will have a high pass behaviour as given by equation (5.4 the basic transfer function cell to implement a High Pass SigmaDelta Modulator is given by: H ( z) = − z −1 1 + z −1 (5. 5. 5.4) and modeled by Fig.1: Basic Low Pass Sigma-Delta Modulator Cell Circuit structure The actual Basic Low Pass Sigma-Delta Cell transfer function is given by: Vo( z )  C1  −1  1  = − z  −1  Vi ( z )  C2   1 − z  (5.2: Basic Low Pass Sigma-Delta Modulator Cell Model Which has the transfer function given by: Y (z) − z −1 = U ( z ) 1 − z −1 (5.Sweden 34 / 71 .3. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .2: Fig 5. High Pass Sigma-Delta Modulator System Level Design 5.True Random Number Generator based on a Sigma-Delta Modulator 5.3) If instead of taking the positive feedback from the output someone takes the negative one. 5.

5 as well as the related circuit analysis and transfer function given on Fig 5.True Random Number Generator based on a Sigma-Delta Modulator Y (z) − z −1 = U ( z ) 1 + z −1 (5.5).3: Basic high pass Sigma-Delta modulator cell model That would yield to the desired expression on equation 5.Sweden 35 / 71 . 5.4: Basic High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analyze Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . Fig.2) to: C 2Vo( z ) − C 2Vo( z ) z −1 = −C1Vi ( z ) z −1 ⇒ C 2Vo(nT ) − C 2Vo(nT − T ) = −C1Vi ( nT − T ) And taking the negative value of Vo(nT-T) from the capacitor C2 the final expression would then be: C 2Vo( nT ) + C 2Vo( nT − T ) = −C1Vi ( nT − T ) ⇒ C 2Vo( z ) + C 2Vo( z ) z −1 = −C1Vi ( z ) z −1 Fig 5.4) Then rewriting the equation (5. One possible structure that can execute such action using known circuits from [38] is given on Fig.4 and equation (5. The idea is then to design a circuit which takes the negative value of the last integration stored on the capacitor C2. 5.1 when C1 = C2.

5 the following difference-equation system analysis can be done: C 2Vo ( nT + T T ) = +C1Vi ( nT ) + ( −C 4Vo ( nT − ) 2 2 C1 = C 3 = C 4 T ) = C 2Vo ( nT + T ) 2 T − C 4Vo ( nT − ) = −C 4Vo ( nT ) 2 C 2Vo ( nT + Thus: C 2Vo( nT + T ) = +C1Vi (nT ) + ( −C 4Vo( nT )) C 2Vo( z )(1 + z ) = C1Vi ( nT ) This results into the following transfer function for the basic high pass cell given by: Vo( z ) C1 −1  1  = z   Vi ( z ) C 2  1 + z −1  (5.6.7.5: Basic High Pass Sigma-Delta Modulator Cell Structure From Fig. The same circuit has the equivalent model as the structure depicted on Fig. 5. 5. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .Sweden 36 / 71 . 5.5 the following switched-capacitor circuit can be designed to implement a 2nd order high pass Sigma-Delta modulator circuit as shown in Fig. 5.5) The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit Using the classic basic cell from Fig.6 The classic 2nd Order High Pass Sigma-Delta Modulator Model. 5.True Random Number Generator based on a Sigma-Delta Modulator Fig. Fig. 5.

7 this switching-circuit requires at least 22 switched-capacitors and enhanced current driving operational amplifier outputs. 5. but looking carefully again to some of the previous difference-equations a reduced and simplified version of the circuit can be designed. As it can be seen on Fig. Another observation that should be taken into account is that on the same switched-circuit both operational amplifiers and comparator are ideal models with high gain. Fig. 5.True Random Number Generator based on a Sigma-Delta Modulator It should be noticed that the equation (5. infinite bandwidth and high slew rate characteristics for execution of first circuit simulations. especially the first stage which outputs have 3 capacitors to drive per output. 5. 5. 5. This circuit needs four distinguished clock signals to work compared to a classical 2nd second order low pass Sigma-Delta modulator version which has just two clocks.7 it is possible to validate the circuit and its functionality as shown in Fig.Sweden 37 / 71 .8 where on the upper graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view of the high pass output baseband spectrum are shown.5) does not have a signal phase shift of 180˚ from the input to the output which will result on the required wiring cross connection from the first to the second stages on the Sigma-Delta modulator circuit on Fig. Through simulation of the discrete-time model on Fig.6 and simulation of the switching-capacitor circuit model on Fig. There are visible some possible modifications that could reduce the number of the switching gates on the circuit.7 Classic 2nd Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .7 as well as the crossing of the input stage on the modulator which in this case is not necessary and independent of the input signal polarization. 5.

3 0. 5. 5.True Random Number Generator based on a Sigma-Delta Modulator Spectral Comparation Classic 2nd Ord High Pass SDM | OSR = 256 0 Amplitude [dB] -50 -100 -150 0 0.9: Reduced basic High Pass Sigma-Delta Modulator Cell Structure Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .8 Spectral simulation results for the classic 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor circuit with a differential sinusoidal input signal of 0.25Vpp (-12dB) at the frequency of (0.5 ω [xπ rad/s] 0.998π) rads/s and OSR = 256.1) with less transistors and capacitors is depicted in Fig.8 0.4 0.994 0.996 ω [xπ rad/s] 0.9 1 Spectral Comparation at the Baseband Classic 2nd Ord High Pass SDM | OSR = 256 0 Discrete-Time System Model Switched-Capacitor Circuit Amplitude [dB] -50 -100 -150 0.7 0.993 0.6 0.998 0.997 0.Sweden 38 / 71 .9 and analyzed on Fig. 5.1 0.999 1 Fig. The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure Another possible circuit structure that realizes the same basic cell transfer function from equation (5.2 0.995 0.10: Fig. 5.

10: Reduced High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analysis From the analysis on Fig 5.Sweden 39 / 71 . 5.4) With the same analysis used on the first structure on Fig.10 it is also possible to derive more two other structures as given in Fig.11 as well as their corresponding transfer functions: Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 5.10 the resulting transfer function for this basic structure is: Vo( z ) C1 −1  1  =− z   Vi ( z ) C 2  1 + z −1  (5.True Random Number Generator based on a Sigma-Delta Modulator Fig. 5.

The same circuit has the equivalent model as the structure depicted on Fig.6. Fig.Sweden 40 / 71 . 5. 5. 5.11: Reduced basic High Pass Sigma-Delta Modulator Cell Structures with different transfer functions The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit Using the reduced basic cell structure from Fig. 5. Through simulation of both models it is possible to check the validation of the circuit and its functionality as shown if Fig.True Random Number Generator based on a Sigma-Delta Modulator Fig.11a the following switched-capacitor circuit can be designed to implement a 2nd order high pass Sigma-Delta modulator circuit as shown in Fig. 5.12. 5.12 Reduced 2nd Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .13.

998 0.8 0. The only drawback is that it still requires four distinguished clock signals to work compared to a classical 2nd order low pass Sigma-Delta modulator version which has just two clocks. 5. 6.12 this switching-circuit requires 50% less switched-capacitors compared to the previous version and operational amplifier’s outputs with less driving strength. it should be noticed that one possible disadvantage of this reduced structure could arise from the parasitic capacitance on the switched integratingcapacitor which is not built as in the conventional layout structure as on the classic structure.7 0. 5.25Vpp (-12dB) at the frequency of (0.2 0. For this purpose. 6.Sweden 41 / 71 .998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinus signal at the output results on the following left SNDR curves depicted on Fig. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .1 Switched-Capacitor Circuit Requirements Differential Sinusoidal Input Signal Amplitude Influence Analysis One factor that should be taken into account is the need or not for a differential sinusoidal input signal at the frequency of π/2 rad/s for a better shape on the final output spectrum and its influence on the SNDR curves for different amplitude values.5 ω [xπ rad/s] 0.1 0. Through simulation of the discrete-time model on Fig.1 for a oversampling rate of 256. 6. one signal named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude changing from 0.998π) rads/s with OSR = 256.13 Spectral simulation results for the reduced 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit with a differential sinus input signal of 0.1 was calculated.00Vpp and the other one called Vin0.995 0. required is this new structure due to the polarization switching behaviour on the integrating capacitors to get a high pass transfer function of the reduced basic cells.6 0. From both analyzed switching-circuits it is evident the advantage of the reduced version which is going to be used at analysis for the determination on further components requirements.6. Applying two differential sinusoidal signals at the input of the circuit.13 where on the upper graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view of the high pass output baseband spectrum are shown.6 and simulation of the switched-capacitor circuit model on Fig. 5.9 1 Spectral Comparation at the Baseband Reduced 2nd Ord High Pass SDM | OSR = 256 0 Discrete-Time System Model Switched-Capacitor Circuit Amplitude [dB] -50 -100 -150 0.3 0.993 0.4 0. 5.997 0.True Random Number Generator based on a Sigma-Delta Modulator Spectral Comparation Reduced 2nd Ord High Pass SDM | OSR = 256 0 Amplitude [dB] -50 -100 -150 0 0.999 1 Fig. through some simulations using the equivalent discrete-time system model from Fig. However.00Vpp to 1. As it can be seen on Fig.12 it is possible to validate the circuit and its functionality as shown in Fig. 5. Requirements for the Different Components of the Analog Circuit System 6.998π with a frequency of 0. the following SNDR curve depicted on Fig. 5.996 ω [xπ rad/s] 0. This circuit characteristic will be analyzed more carefully on the coming section.994 0.

5.75 1.1. 6.50 0.00 0.25 0. 6. 6.1 SNDR for different amplitudes of the differential sinus input signal at the frequency of π/2 for the 2nd Order High Pass Sigma-Delta Modulator Circuit Switched-Capacitor Coefficients Scaling Analysis Concerning the power source and reference voltages on which the switched-capacitor circuit will be implemented later. SNDR HPSDM 2nd Order | OSR =256 | Diff Vin π/2 120 0.998π = -6 dB 0. which suggests that the system input path could be probably taken out from the final circuit topology depicted on Fig.8 1 Fig. 5. However.12. 6.2 System model of 2nd Order High Pass Sigma-Delta Modulator with scaling factors Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .2 0.00 100 Vpp Vpp Vpp Vpp Vpp 100 120 SNDR HPSDM 2nd Order | OSR =256 | Diff Vin π/2 80 80 SNDR [dB] 60 SNDR [dB] -40 -30 -20 Vin0. on the final SNDR curve. there is no influence of Vinπ/2. a scaling factor should be applied over the capacitor values to limit the internal operational amplifier output signals to the reference voltages of the circuit.12 this input path should be implemented to start-up the Sigma-Delta modulator circuit at initial power on conditions and to result on a better spectrum shape and decorrelation of the output of the Sigma-Delta modulator ADC. To find out the scaling factors that should be used the following 2nd order high pass Sigma-Delta modulator system shown in Fig.6 Vinπ/2 [V] | Vin0.998π [dB] -10 0 60 40 40 20 20 0 -50 0 0 0. 5.True Random Number Generator based on a Sigma-Delta Modulator As it is possible to see on the right SNDR versus Vinπ/2 curve on Fig.2 can be modeled to later apply the scaling factors over the capacitors on the switched-capacitor circuit for the high pass Sigma-Delta modulator circuit from Fig. due to initial conditions on the circuit structure on Fig. the differential sinusoidal input signal amplitude at the frequency of π/2 rad/s.4 0. Fig.Sweden 42 / 71 .12.

2 -0.998π rad/s with differential amplitude ranging from -48 to -3 dB the following left SNDR curves shown on Fig. 6.5 From Fig. 5. Due to this fact and due to the existence of intrinsic parasitic capacitances from the switched-capacitor top and bottom plates a set of simulations including parasitic capacitances in the circuit structure of Fig. 6.4 -0. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .6 -0. Switched-Capacitor Parasitic Capacitance Analysis Contrary to classical switched-capacitor circuits where sensitive capacitor nodes are placed always on the top plate.12.3: Scaled HPSDM 2nd Ord .6 0. one named Vinπ/2 at the frequency of π/2 rad/s with differential amplitude of 0. The top parasitic capacitor was disconsidered. 6. In addiction to that. it should be reinforced that for this scaling method the parameters k12 and k22 do not need to be scaled and remain unchanged as well as their corresponding integrating-capacitors on the circuit on Fig.2 0 -0. 6.8 -1 0 1 2 3 4 5 [s] 6 7 8 9 10 x 10 5 Fig: 6.15.5 were calculate for these different parasitic scaling factors for an OSR equal to 256.4 Magnitude [V] 0. 2% and 5% of the correspondent capacitor value. Just to notice.8 0. 1%.5Vpp and the second differential sinusoidal input signal called Vin0.998π rad/s the signals o1 and o2 are scaled as depicted on Fig.6 -0.8 0.4 were performed to check the influences and quantify the minimum tolerance required to achieve a SNDR curve as close as possible to the theoretical SNDR curve of the high pass Sigma-Delta modulator on Fig.= -1.6 0.3%.00 V in the model.True Random Number Generator based on a Sigma-Delta Modulator Defining two parameters γ and β it is possible to control the values for the k parameters of the given system through following relations: K11 = γ k12 = 1 k13 = γ k21 = β / γ k22 = 1 k23 = β (6.3 it is possible to see that the signals o1 and o2 are within the reference voltages Vref+ = +1. due to its little parasitic influence on the capacitor value and the bottom parasitic capacitor was scaled to 0.4 -0. 6.2 0 -0. From previous works and layout methodologies it is possible to achieve such tolerance values [62 63 64 65 66].5 the bottom parasitic capacitance should then have a parasitic value lower than 1% to achieve the desired theoretical SNDR curve from Fig.5 and applying a differential sinus signal input of -3dB at the frequency 0.8 -1 0 1 2 3 4 5 [s] 6 7 8 9 10 x 10 5 Scaled HPSDM 2nd Ord .15.12 later on the transistor circuit level design. 4. From the right SNDR versus Bottom Parasitic Capacitor curve on Fig.4 Magnitude [V] 0. 4.2 -0. Applying two differential sinusoidal input signals.5%. 5. 6. resulting into low parasites the proposed reduced modulator structure uses integrating-capacitors with changing polarity where this is not possible.00V and Vref.7%.5 and β = 1/6.998π at the frequency of 0.o1 Signal 1 0. 0.1) By setting γ = 1/3.3 Signals o1 and o2 from 2nd Order High Pass Sigma-Delta Modulator of Fig.o2 Signal 1 0. 0.Sweden 43 / 71 . these scaling factor values will be applied over the capacitor values from the switched-capacitor circuit from Fig.

6.5 SNDR for different bottom capacitor parasitic tolerances on the 2nd High Pass Sigma-Delta Modulator Circuit Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .0% 0.3% 120 SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics 100 100 80 80 SNDR [dB] 60 SNDR [dB] -50 -40 -30 -20 Vin0.Sweden 44 / 71 . 6.0% 1.5% 0.7% 0.5V π/2 -10 0 60 40 40 20 20 0 -60 0 0 1 2 3 4 Bottom Cap Parasitic [%] | Vin = -6dB 0.4 2nd Order High Pass Sigma-Delta Modulator switching-capacitor circuit including the top and bottom parasitic capacitances from the switched-capacitor plates SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics 120 5.998π 5 Fig.True Random Number Generator based on a Sigma-Delta Modulator Fig.0% 2.998π [dB] | Vin = 0.

True Random Number Generator based on a Sigma-Delta Modulator 6.2 Operational Amplifier Requirements Operational Amplifier Gain Analysis With the previous circuit topology from Fig. As it possible to see from the right SNDR versus Gain curve on Fig.998π with a frequency of 0. 6.998π [dB] -10 0 60 40 40 20 20 0 -50 0 0 10 20 30 40 50 Gain [dB] | Vin0. 6. 5. 5.6 a set of circuit simulations and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig.998π = -6 dB 60 70 80 Fig.7. 6. Note that for this first operational amplifier’s characteristic estimation the frequency bandwidth is not modeled and is considered infinite.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig.12 and modeling the operational amplifier like depicted on Fig.8 for an oversampling rate of 256. Fig. 6.15. Implementing the circuit shown in Fig.5Vpp | Diff OpAmp Gain 120 100 100 80 80 SNDR [dB] 60 SNDR [dB] -40 -30 -20 Vin0.8 the minimum required operational amplifier gain should be greater than 40dB.7: SNDR for different operational amplifier gains on the 2nd Order High Pass Sigma-Delta Modulator Circuit By giving different gain values and applying two differential sinusoidal signals at the input of the circuit. 4.12 some operational amplifier characteristics concerning its minimum gain must be analyzed to achieve a SNDR curve close to the theoretical one from Fig. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .5V and another one called Vin0.Sweden 45 / 71 . 6.6 Operational amplifier with gain modelling for PSPICE simulations SNDR Simulink Scaled HPSDM 2nd Ord | Vinπ/2 = 0.5Vpp | Diff OpAmp Gain 120 G= G= G= G= G= G= G= G= G= G= G= G= 74dB 66dB 60dB 54dB 46dB 40dB 34dB 26dB 20dB 14dB 6dB 0dB SNDR Simulink Scaled HPSDM 2nd Ord | Vinπ/2 = 0. 6. one named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude 0.

5.Sweden 46 / 71 .50 0.00 1. From the right SNDR versus Input Capacitance curve on Fig. Implementing the circuit shown in Fig. Note that for the estimation of the operational amplifier input capacitance its gain was set to 40dB from the minimum established from last analysis and its frequency bandwidth is considered infinite. 6. 6. scaling the input and feedback circuit paths with the corresponding scaling factors calculated on the previous section 6.00 2.5Vpp.9 for a oversampling rate of 256. one named Vinπ/2 with a frequency exactly on π/2 rad/s and with a differential amplitude of 0.15.20 to 5. It means that the input capacitance of the individual operational amplifier inputs should be maximum of the order or lower than the integrating-capacitor value that will be used on the final circuit.12 some operational amplifier characteristics concerning its maximum input capacitance requirements must be analyzed to achieve a SNDR curve close to the theoretical one from Fig.998π [dB] | Vin = 0. SNDR HPSDM 2nd Ord | OSR = 256 | Diff Cin OpAmp 120 5.998π with a frequency of 0.0V π/2 -10 0 60 40 40 20 20 0 -60 0 0 1 2 3 (CinOpAmp/Ci) [fF] | Vin = -3dB 0.998π 4 5 Fig.2 and connecting to each of the two operational amplifier’s signal inputs a capacitor. applying two differential sinusoidal signals at the input of the circuit.8: SNDR for different operational amplifier’s input capacitance values on the 2nd Order High Pass Sigma-Delta Modulator Circuit Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .00 0.True Random Number Generator based on a Sigma-Delta Modulator Operational Amplifier Input Capacitance Analysis With the previous circuit topology from Fig.20 100 x Ci x Ci x Ci x Ci x Ci 100 120 SNDR HPSDM 2nd Ord | OSR = 256 | Diff Cin OpAmp 80 80 SNDR [dB] 60 SNDR [dB] -50 -40 -30 -20 Vin0. 4. 6.8.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig. 5.12.15. a set of circuit simulations with different values for this input capacitor and further SNDR calculations where performed resulting on the following SNDR curves given on Fig. 4. 6.9 it is possible to percept that for an input capacitance value of the same other or lower than the integrating capacitor value it is possible to achieve a SNDR curve close to the theoretical one on Fig. another one called Vin0.00 times the value of the integrating-capacitor. By giving different operational amplifier input capacitance values ranging from 0.

15.5) It should be noticed that for the purpose of the simulations the gain in the voltage gain source model in Fig.9 a set of circuit simulations and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig. 5.Sweden 47 / 71 . 6.4) it is possible to find the relation: f −3dB = 2 f 0dB (6. 2πRC for (6. The value of the resistor R is given by equation (6. 6. 6.2) The same can be found for the 0dB frequency: 2  Vout ( w) G2 =  1 + ( RCw) 2 Vin( w)    = (1)2   G >> 1 2 (6.2. 2πRC for (6. Fig.2) and (6. 6.12 and modelling the operational amplifier like depicted on Fig.10 it is possible to find out the relation between the -3dB gain frequency and the 0dB gain frequency for an amplifier with a RC low pass filter at its output: Fig 6. 6.3) f 0 dB = G .10 Operational amplifier with a low pass filter at the output circuit modelling 2  Vout ( w) G2  =  1 + ( RCw) 2 Vin( w)      = 2  2      G >> 1 2 2 (6.12. 5.9 are set to 5000 (74dB) which is enough given the SNDR versus Gain curve on Fig.9 Operational amplifier with frequency bandwidth modelling for simulations From circuit in Fig. Implementing the circuit shown in Fig. 4.6): Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .4) From equations (6. 6.True Random Number Generator based on a Sigma-Delta Modulator Operational Amplifier Bandwidth Analysis With the previous circuit topology from Fig.1) f −3dB = G .12 some operational amplifier characteristics concerning its bandwidth must also be analyzed to achieve a SNDR curve close to the theoretical one from Fig.

From the right SNDR versus Offset curve on Fig. Using the scaled model of Fig. SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp 0dB f 120 16 x f0dB/fs 12 x f0dB/fs 8 x f0dB/fs 4 x f0dB/fs 100 3 x f0dB/fs 2 x f0dB/fs 1 x f0dB/fs 100 120 SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp 0dB f 80 80 SNDR [dB] 60 SNDR [dB] -50 -40 -30 -20 Vin0.13. From the right SNDR versus Hysteresis Switching Point curve on Fig.998π with a frequency of 0.9 is then related through equation (6. 6.3 and setting different switching voltage values for the comparator (1-bit A/D Converter) the following SNDR curves result as depicted on left Fig.5Vpp and the other one called Vin0. should be greater than 4 times the sampling frequency fs in use on the system. 6. Using the scaled model of Fig. 6.998π 12 14 16 Fig.998π [dB] | Vin = 0. f0dB. 4. By specifying different R values and applying two differential sinusoidal signals at the input of the circuit. 6.11: SNDR for different f0dB values of the operational amplifier on the 2nd Order High Pass Sigma-Delta Modulator Circuit 6.5V π/2 -10 0 60 40 40 20 20 0 -60 0 0 2 4 6 8 10 (f0dB/fs) | Vin = -6dB 0.11 the minimum required operational amplifier 0dB gain frequency. 6.3 and setting different switching value points for a hypothetical symmetrical comparator’s hysteresis curve the following left SNDR curves result as depicted on Fig.Sweden 48 / 71 . Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . As it possible to see from the right SNDR versus f0dB curve on Fig.15 for OSR equal 256.15 for OSR equal 256. one named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude of 0. 6.12 it is possible to see that for an offset voltage value ranging from -50mV to 50mV the SNDR curve achieves the desired values compared to the theoretical one from Fig. 4.6) to the 0dB gain frequency of the operational amplifier for a given capacitor value C on this simulation set on 1nF. Comparator Hysteresis Analysis The comparator should also be checked for its hysteresis influence over the SNDR curve. 6.3 Comparator Requirements Comparator Offset Analysis With the same idea of the operational amplifier requirement analysis the comparator should be checked for its offset influence over the SNDR curve.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the following left SNDR curves depicted on Fig.13 it is possible to observe that for hysteresis symmetrical switching voltage values lower than |100mV| the SNDR curve achieves the desired values compared to the theoretical one from Fig.11 for a oversampling rate of 256.12. 6.True Random Number Generator based on a Sigma-Delta Modulator R= 1 1 × 2 × 5000 × 2πC f 0dB (6. 6.6) The parameter R on the model on Fig 6.

True Random Number Generator based on a Sigma-Delta Modulator

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0.9

Fig. 6.13 SNDR for different comparator’s symmetrical hysteresis witching voltage values on the 2nd Order High Pass Sigma-Delta Modulator Circuit Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 49 / 71

True Random Number Generator based on a Sigma-Delta Modulator 7. Analog Components Circuit Design 7.1 Operational Amplifier Transistor Circuit Design Having in mind that the main application of this TRNG with a Sigma-Delta modulator ADC is oriented to low power and restricted area on die applications, it should be established a sampling frequency that fulfils the usually necessary random bit stream rates and leaves a big security margin concerning to influences of the flicker noise of the switching-transistors over the AIS Standard Statistical Test results. It should also be remembered that if needed the random bit stream rate could be increased by applying the “Gauss Distribution Comparator” algorithm as mentioned before. For the purpose of this work it was considered a sampling frequency of 25MHz which translates to an output random bit stream close to 100k bits/s with a clock signal waveform drawn as it follows on Fig. 7.1.

Fig. 7.1 Signal “o” sampling frequency clock waveform From previous section 4.5.4 concerning the thermal and flicker noise analysis the integrating-capacitor value for the switching-circuit design should lay between 20fF to 60fF and in this case was chosen to be 25fF which imposes some additional characteristics and limits that the operational amplifier, comparator and transmission gate need to satisfy to allow the proper operation of the system. Using the parameters on Fig. 7.1 it is possible to calculate the required minimal output driving current of the operational amplifier if it is taken into account that it needs to drive at least 750fF of capacitive load at each of its outputs as it is possible to see from the switched-capacitor circuit in Fig. 5.12 once the scaling factor are properly applied for the chosen integrating-capacitor value and taking also into account the capacitors of the common-mode feedback control circuit in the operational amplifier output stage. For the 90nm MOS technology in use the nominal Vss to Vdd source voltage is 1.20V which follows to a minimal output driving current given by:

Iout > Cload

dV (Vdd − Vss ) = Cload = 5 × Cload × f s × (Vdd − Vss ) 1 dt T 5

(7.1)

As stated on equation (7.1) if it is taken into account that the sampled voltage needs to reach its 100% value in one fifth of the sampling period time and additionally applying a security factor of 2 times then it comes to a minimum required driving current Iout of 225uA. The second important factor to be taken in account is the operational amplifier input capacitance which for a differential MOS pair input is mainly given by the size of the differential input pair transistors. From previous section 6.2 it was mentioned that the operational amplifier input capacitance should be equal or less than the integrating capacitor value. In this design, the integrating capacitor was established to 25fF then the simulation measured operational amplifier input capacitance should be equal or lower than this value. From the previously determined requirements the following operational amplifier circuit with bias and additional common-mode feedback control (CMFB) circuit was designed as depicted on Fig. 7.2 and Fig. 7.3. As shown on Figs. 7.4 and 7.5 through CADENCE Spectre small-signal AC and large-signal DC simulation analysis the circuit satisfies the previous determined operational amplifier requirements for nominal conditions (Vdd-Vss = 1.20V, Temperature = 27 °C) as stated on Table 7.1: Parameter Simulated Required Limit 43dB DC Gain>40dB DC Gain 182MHz f0dB/fs>4, fs=25MHz f0dB 70° Phase Margin > 50° Phase Margin 300uA Iout>=225uA Iout 4fF Cin≤25fF Cin Table 7.1: Operational amplifier simulated and required parameters Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 50 / 71

True Random Number Generator based on a Sigma-Delta Modulator

Fig. 7.2 Operational Amplifier Transistor Circuit Design As it is possible to observe on Fig. 7.2 the operational amplifier is built on two amplification stages: the first stage being a folded-cascode circuit composed by the biasing current-mirrored transistors Q6, Q10 and Q11, differential input pair Q7 and Q8, cascode transistors Q12 and Q13 and by the folded transistors Q14 and Q15. The second stage being composed by two common-source circuits through transistors Q18 and Q19 and biasing transistors Q16 and Q17. Additionally there is a simple current mirror biasing circuit composed by transistors Q1, Q2, Q3, Q4 and Q5. It should be noticed that transistors Q7 and Q8 must be reduced on area size as much as possible to reduce the input capacitance of the operational amplifier’s input, the drawback is that they have a strong contribution on the first stage folded-cascode amplification which for this configuration achieves less than 10dB gain, for that reason a second amplification stage was added to achieve an overall gain higher than the required 40dB and that could drive at least 300uA at each output. To satisfy the required phase margin additionally phase compensation capacitors C1 and C2 were inserted between the input and output of the second stage as seen on the circuit. When using fully-differential operational amplifiers in a feedback application, the applied feedback determines the differential signal voltages, but does not affect the common-mode voltages. It is therefore necessary to add additional circuitry to determine the output common-mode voltage and to control it to be equal the halfway between the power-supply voltages. The circuit that does this functionality on the operational amplifier circuit is the common-mode feedback circuit (CMFB) given on Fig. 7.3 [49 50]. In this circuit, capacitors named Cc generate the average of the output voltages, which is used to create control voltages for the operational amplifier current sources. The DC voltage across Cc is determined by capacitors Cs, which are switched between bias voltages and between being the parallel with Cc. This circuit behaves like a switchedcapacitor low-pass filter having a DC input signal. The bias voltage is designed to be equal to the difference between the desired common-mode voltage and the desired control voltage used for the operational amplifier current sources [38].

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden

51 / 71

a high capacitor value is necessary on the CMFB circuit.Sweden 52 / 71 .8. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .3 Operational Amplifier Transistor Common Feedback Circuit Design The final phase and gain small-signal AC circuit simulation for this operational amplifier configuration can be seen on Fig. There is an optimum value which for this circuit was achieved after some circuit simulations and controllability performance verification of the common-mode feedback circuit yielding to the capacitor values given on the circuit depicted on Fig.True Random Number Generator based on a Sigma-Delta Modulator The capacitors labelled Cs should be between one-quarter the sizes of the non-switched capacitors Cc.3. Additionally to these nominal condition simulations a set of Monte-Carlo circuit simulations were performed to check out the robustness and tolerance of the designed operational amplifier to temperature. f0dB and Phase Margin parameters given on Table 7. 6. 7.5 shows the voltage swing of the internal signals “int_outp” and “int_outn” relative to the first amplification stage of the circuit of Fig. The large-signal DC Vin Sweep analysis depicted on Fig. 7. 7.2 as well as the voltage swing of the operational amplifier output signals “outp” and “outn” which saturation limits comply with the maximum and minimum values of the previous scaled output signals “o1” and “o2” from Fig. but using a larger capacitance value overloads the operational amplifier more than necessary during the “e” clock phase. Reducing the capacitor too much causes common-mode offset voltages due to charge injection of the switches [38] and additionally by reducing the capacitor too much it creates a possible capacitor voltage-divider between the parasitic capacitance of transistors Q16 and Q17 and their correspondents Cc capacitors on the CMFB circuit structure which also yields to common-mode offset voltages. f0dB and Phase Margin and yield fabrication of the operational amplifier circuit. For each temperature there were simulated three different power-source voltages and the respective distributions of the parameters DC Gain. 7.4 which returns the DC Gain.1 fulfilling the previous determined requirements for each one. 7. 7.3. Fig. Due to the fact that the operational amplifiers’ outputs need to drive at least 225uA each. 7. process fabrication and mismatch variations as well as to measure the distributions of parameters DC Gain. f0dB and Phase Margin shown on Figs. power-source voltage.6.7 and 7. For these Monte Carlo simulations there were taken into account statistical models for process fabrication and mismatch variations on the 90nm MOS technology used by the CADENCE Spectre [73] simulation CAD tool.

4 Operational amplifier CADENCE Spectre small-signal AC gain and phase analysis Fig.5 Operational amplifier CADENCE Spectre large-signal DC Vin Sweep analysis Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 7.True Random Number Generator based on a Sigma-Delta Modulator Fig. 7.Sweden 53 / 71 .

True Random Number Generator based on a Sigma-Delta Modulator Fig. DC gain and f0dB histograms for different power supply voltages at the temperature of +27°C Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .7 Operational Amplifier Monte Carlo phase margin.Sweden 54 / 71 . DC gain and f0dB histograms for different power supply voltages at the temperature of -40°C Fig. 7.6 Operational amplifier Monte Carlo phase margin. 7.

From the right distribution curves on Figs.7 and 7.8 the chosen temperatures are -40°C.6. 7. 7. For the power-supply voltage it was considered a tolerance of +/. It is also possible to see that the distribution mean value keeps relative constant as well as the distribution curve keeps the same wide spreading under different temperature and power-source voltage conditions. Finally at the left distribution curves on Fig. Looking at the middle distribution curves on Figs. DC gain and f0dB histograms for different power supply voltages at the temperature of +100°C As it can be seen on Figs. 7. 7. but that would take more time on its design and due to the lack of time and considering that for the nominal conditions the current design has an average simulation process yield higher than 80% it was decided to keep using it as it is and further works could improve it if stronger requirements are imposed on the environment temperature that such application would be used. two extreme environment temperatures and one ambient temperature.Sweden 55 / 71 . From these distribution curves some improvements should be done on the design of the operational amplifier circuit. 7.6.20V taken into account possible variations of such order for the kind of application where this system could be applied.True Random Number Generator based on a Sigma-Delta Modulator Fig. 7. It it also possible to observe that the higher the temperature the higher gets the distribution mean value and more narrowed becomes the distribution curve for different power-supply voltages. 7.7 it shows that the DC Gain parameter fulfils on at least 85% of the cases its minimum required value of 40dB having just a low performance of 60% on the case for the extreme temperature of +100°C like depicted on the middle distribution curve on Fig. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .8 it is also possible to see that the Phase Margin parameter fulfils on at least 82% of the cases the minimum required value of 50° having just a low performance of 40% on the case of extreme low temperature of -40°C like depicted on the middle distribution curve on Fig.8 it is possible to observe that the f0dB parameter fulfils in 95% of the cases its minimum allowed value of 4fs with fs equal to 25MHz for any temperature and powersupply voltage and that the higher the temperature the lower gets the distribution mean value and more narrowed becomes the distribution curve for different power-supply voltages. +27°C and +100°C. 7. 7.6.6.7 and 7.8.10% over the nominal value of 1.7 and 7. 7.8 Operational Amplifier Monte Carlo phase margin.

10. 7.9 Comparator Circuit Design Performing a large-signal DC Vin Sweep CADENCE Spectre circuit simulation of the circuit the following hysteresis curve for the comparator output under nominal temperature and power-source conditions was taken depicted on Fig. it is possible to calculate that the comparator’s offset will be between -11mV to 11mV which is in compliance to the previous determined offset limits for the comparator between -50mV and 50mV.True Random Number Generator based on a Sigma-Delta Modulator 7.Sweden 56 / 71 . As it is possible to see the comparator is built on two stages: the first being a clocked differential pair amplifier composed by transistor Q1 to Q10 and the second a NAND based SR latch composed by transistor Q11 to Q22.10 Comparator Hysteresis Curve The offset voltage is possible to estimate if we take into account that the threshold voltage mismatch σ∆Vt of a transistor pair is proportional to the inverse of the square root of the active device area with the matching parameter A∆Vt [67 68 69 70]: σ ∆Vt = A∆Vt WL (7. Fig. The comparator fulfils its requirements with hysteresis symmetrical switching value between -100mV to 100mV. 7.9.2 Comparator Transistor Circuit Design From the previously determined requirements the following comparator circuit was designed as depicted on Fig.2) Taken from the reference [67] that A∆Vt is estimated to be around 3mVµm for the 90nm CMOS technology then using the input pair transistors’ size. 7. 7. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . Fig.

Through CADENCE Spectre [73] circuit simulation the designed transmission-gate depicted on Fig. the switching transistors should have an area that reduces as much as possible the flicker noise of the system.Sweden 57 / 71 . 7. 7.2) This gives a transmission gate on resistance of maximum 160kΩ for an integrating switched-capacitor of 25fF and system sampling frequency of 25MHz. 7.1 that the switched-capacitors drive currents of the maximum order of 300uA from the operational amplifier. 4. Fig.11 gives a maximum on resistance of 6. Besides this requirement.3 Transmission-Gate Transistor Circuit Design To design the transmission-gate it should be remembered from section 7.30 if it is considered that the Flicker Noise Corner Frequency is 1000 times smaller than half the system sampling frequency. 7.12 and a transistor area of 51200 nm2 which fulfils the desired Flicker Noise Corner frequency from Fig.12 Transmission Gate Active On Resistance Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .3kΩ as shown on Fig.11 Transmission Gate Transistor Circuit Design Fig.True Random Number Generator based on a Sigma-Delta Modulator 7. Establishing that the sampled voltage on the integrating switched-capacitor should achieve 100% of its magnitude before one-fourth the system’s sampling period the transmission-gate on resistance should then be lower than: 5Ron C < 1 1 Ts ⇒ Ron < 2 10Cf s (7.

8. 8.48MHz which corresponds to 0. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design.5 and 8.4.True Random Number Generator based on a Sigma-Delta Modulator 8. 8. 8.1 with corresponding clock signals given on Fig. 8. 8.2.1 Switched-Capacitor Sigma-Delta Modulator Circuit Design Fig. 8.998π rad/s with a system sampling frequency of 25MHz.2 Clock Signals for the Switched-Capacitor Transistor Circuit Design Using the Input Circuit on Fig. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .1 to reduce computation for first simulations some CADENCE Spectre [73] transient simulations were performed to check out the robustness and calculate the output spectrum and limitations of the circuit under ambient temperature of +27°C and different power-supply voltages as shown of Figs.6.3a with the circuit on Fig. For this simulations the differential sinusoidal signal input was set to -18dB with frequency at 12. Fig. Simulation & Analysis Once designed all basic analog components circuits the following switched-capacitor Sigma-Delta modulator was built as depicted on Fig. 8.Sweden 58 / 71 .

20V the noise is increased at the desired high pass baseband of work which would succeed on a lower SNDR operation point for the Sigma-Delta modulator. 8. The second reason is that by lowering the power-supply voltage the 90nm transistor MOS characteristics for nominal operation voltage of 1.3 Switched-Capacitor Input Circuit Looking at the shape of the output spectrum on Figs. The only way to apply all tests is by producing a real die and performing real measures.7. 8. The second set of circuit simulations was to determine the SNDR curve of the Sigma-Delta modulator for different differential sinusoidal input signal amplitudes ranging from -48dB to -3dB for different power-supply voltages at the ambient temperature of +27°C as depicted on Fig. but that was left for future works. 8. Applying then the Input Circuit of Fig. To run the fully set of statistical tests it would be required to sample at least 1.6 it is possible to recognize a high pass transfer function system. 8. meaning that either the nominal power-supply voltage should be increased or the nominal power-supply voltage of 1.Sweden 59 / 71 . On Fig. 8. 8.54 billion samples from CADENCE Spectre [73] transient simulation which its beyond the computer’s memory size and computation time processing.3b and introducing the additional clock signals of Fig. As previously mentioned for power-supply voltages below minus 5% of the nominal value the Sigma-Delta modulator does not achieve its proper operation.True Random Number Generator based on a Sigma-Delta Modulator Fig. 8.5 and 8.20V should have a tolerance on the range of ±5%. Only a real integrated-circuit system version could give that amount of samples in much less time. Looking carefully on the high pass baseband of work spectrum it is also possible to observe that the lower the temperature the less tolerance the circuit has to lower values of power-supply voltages.4 it is shown that for a power-supply voltage below minus 5% of its nominal value of 1. Finally on Fig.20V are taken out from their voltage sourcedrain quiescent operation point that could be overcome just with lower transistor voltage threshold which design and study is beyond this work and open for further ones. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . The same appointment and behaviour happens for the ambient temperature of +27°C. but for power-supply voltage minus 10% under its nominal value. One reason for this drawback is that by lowering the power supply voltage the operational amplifier operational working point derivates from its nominal polarization condition which degrades the required parameters for a proper operation of the Sigma-Delta modulator.11 are shown the optimum first stage input capacitor’s values and the final scaled switched-capacitor 2nd Order High Pass Sigma-Delta Modulator Transistor Design for this project.4.8 to control the transmission-gates of the Input Circuit so that an artificial inbuilt sinusoidal sampled signal of one fourth of the system sampling frequency could be generated without additionally external circuitry for a future die fabrication some CADENCE Spectre [73] transient simulations were ran for different first stage input capacitor scaling factors to find the optimum value for which the Sigma-Delta modulator outputs a flatten spectrum at the high pass baseband frequency range of work as shown on Fig. 8. 8. One possible simpler solution would be to increase the nominal power-supply voltage on at least 10% to achieve then an overall tolerance of ±10% for any case of extreme temperatures.9.

99 ω [xπ rad/s] Baseband 0.4 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of -40°C with a differential sinusoidal signal input of -18dB at 12.20V 1.7 0.99 ω [xπ rad/s] Baseband 0.08V 1.8 0.4 0.32V 0. 8.8 0.5 ω [xπ rad/s] 0.4 0.9 1 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 Discrete-Time System Model CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = 1.3 0.48MHz and sampling frequency of 25MHz Output q Spectrum / T = +27°C 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 0 0.5 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +27°C with a differential sinusoidal signal input of -18dB at 12.26V 1.2 0.20V 1.995 1 Fig.9 1 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 Discrete-Time System Model CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = 1.26V 1.985 0.985 0.Sweden 60 / 71 .1 0.14V 1.6 0.5 ω [xπ rad/s] 0.32V 0.6 0.14V 1.2 0.08V 1.48MHz and sampling frequency of 25MHz Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .True Random Number Generator based on a Sigma-Delta Modulator Output q Spectrum / T = -40°C 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 0 0.7 0.1 0. 8.995 1 Fig.3 0.

995 1 Fig. 8.48MHz and sampling frequency of 25MHz SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C 120 Vdd-Vss Vdd-Vss Vdd-Vss Vdd-Vss Vdd-Vss 100 = 1.998π 1.14V = 1.3 0.9 1 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 Discrete-Time System Model CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = CADENCE Spectre Vdd-Vss = 1.8 0.1 1.True Random Number Generator based on a Sigma-Delta Modulator Output q Spectrum / T = +100°C 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 -140 0 0.5 ω [xπ rad/s] 0.08V = 1. 8.32V 100 120 SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C 80 80 SNDR [dB] 60 SNDR [dB] -50 -40 -30 Vin0.3 (Vdd-Vss) [V] | Vin = -15dB[dB] 0.2 0.35 1.20V 1.6 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +100°C with a differential sinusoidal signal input of -18dB at 12.7: High Pass Sigma-Delta Modulator SNDR curve for different power-supply voltage values at the ambient temperature of +27°C Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .25 1.4 0.6 0.20V = 1.26V 1.2 1.32V 0.15 1.985 0.1 0.26V = 1.05 1.08V 1.998π [dB] -20 -10 0 60 40 40 20 20 0 -60 0 1 1.7 0.99 ω [xπ rad/s] Baseband 0.4 Fig.14V 1.Sweden 61 / 71 .

8.20V 0 -20 -40 Magnitude [dB] -60 -80 -100 -120 0 0.096 mm2 and due to the fact that the area is mainly determined by the size of the capacitors the estimated area for this totally new 2nd order high pass Sigma-Delta modulator built on 90nm CMOS technology would be around 3 times smaller given an area of 0.8 0.9 1 Fig.10 besides the 2nd order high pass Sigma-Delta modulator it would be also interesting to implement the sinusoidal multiplication and the 3rd Order TSinc FIR Filter in a CMOS hardware system due to the required high clock frequency for this filter in this system and known effective hardware implementation for this kind of filter [38]. 8.1 for comparisons. The simulated dynamic power consumption for the Sigma-Delta modulator transistor circuit on Fig. 8.9 Clock Signals for the Input Transistor Circuit Design This final 256 times oversampled 2nd order high pass Sigma-Delta modulator with a sampling frequency of 25MHz.Sweden 62 / 71 .2 0. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . 8.10.11 is 1.4 0.6mW.True Random Number Generator based on a Sigma-Delta Modulator Fig.8 Clock Signals for the Input Transistor Circuit Design HPSDM 2nd Orded Output Spectrum | OSR = 256 | T = 27°C | Vdd-Vss = 1.5 0.032 mm2 which is comparable to other TRNG references and integrated-circuits mentioned at the introduction of this work and listed on Table 8.1 0. Looking on the system of Fig.3 0. 8. For estimation of SigmaDelta modulator on die chip area it was taken from reference [51] the non-cascaded second order Sigma-Delta modulator with total capacitance per stage of 2pF which has an area of 0.6 ω [xπ rad/s] | f = 25MHz s 0.76Mbs/s at the output of the system. under nominal power-supply voltage of 1. The One Fourth Band with TSinc Compensation FIR Filter and the “Zero-Cross Comparator” algorithm could then be implemented in a DSP microprocessor system with such filters’ orders that it does not degrade the resolution of the previous Sigma-Delta modulator once its resolution is going to decide the performance of the overall system and additionally leaves the option to implement the “Gauss Distribution Comparator” algorithm described before if a higher random output bit stream rate is desired for an application with possibility to achieve more then 1.7 0.20V and ambient temperature of +27°C together with the digital signal-processing decimation filter with a “Zero-Cross Comparator” algorithm explained before gives a random bit stream of 100Kbs/s at the output of the final TRNG system structure depicted on Fig.

True Random Number Generator based on a Sigma-Delta Modulator Fig. 8.Sweden 63 / 71 .10 Final TRNG with a Sigma-Delta Modulator ADC System Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .

n.5V 5.0V 5. n. a.0016mm2 2. a. Sampling Dual Osc. 8. a. For better comparison it would be necessary to make a carefully analysis over the FIPS SSTs results with the AIS 31 SSTs results.025mm2 0. but it should be noticed that due to the fact that the thermal noise is the useful signal to be extracted from the system. n. n. n.0V 1. Sampling Dual Osc. Additionally to these relaxing requirements this high pass system also holds an enhanced advantage regarding influences of the Flicker noise over the output spectrum and generated random output bit stream. a. This was accomplished through the final built on 90nm CMOS technology totally new 2nd order high pass Sigma-Delta modulator transistor circuit and established requirements for additional digital-signal processing blocks for conception of an entire True Random Number Generation system based on a totally new principle besides the other ones already mentioned at the references.92mm2 0.5KHz 10MHz 1MHz 10MHz 5MHz 12MHz n.18um CMOS 1. Direct-Noise Amplif. n. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . n.25um CMOS 0.5V 3. a. FIPS [37] FIPS [37] n. this work intended to study the feasibility of random number generation through a Sigma-Delta modulator with additional digital signal-processing block system through a noise source integrated into the modulator’s feedback loop.3V 5. n. a.022mm2 n.2um CMOS 2um CMOS 0. there is no need for a high order decimation filter rather than if a high pass Sigma-Delta modulator would be used to other analog signal-processing application which in this case it would be very difficult to design a decimation filter that fulfills the desired Nyquist frequency.3V 5. n. thermal noise magnitude and Flicker Noise Corner Frequency influences over the output spectrum and AIS 31 Standard Statistical Tests results that the high pass system has the desired robustness and qualified itself appropriate to be implemented as a circuit solution. s.009mm2 ~0. 1Mbs/s 4Mbs/s 10Mbs/s 1Mbs/s 200Kbs/s with ZCC ~ 100Kbs/s Tests n. n. n.443mm2 0.0V 2. n. s. s. n.18um CMOS 0. a.0V 1. FIPS [37] FIPS [37] FIPS [37] FIPS [37] n.8V 3. Bit Rate [12] 2001 [13] 2002 [16] 2004 [9 10] 1999 [17] 2004 [8] 2003 [19] 1997 [22] 2003 [24] 2002 [23] 2001 [28] 2005 [29 30] 2001 [31] 2000 [32] 2005 [7] 2000 [21] 2006 This Work Metastability Metastability Astable Multivibrator Dual Osc. n. s. s.8um AMS 0. It should be mentioned that for the first time a totally new designed high pass Sigma-Delta modulator was built and used. 2. a. s. n.3mW 37mW 1mW 3.1 Characteristics performance comparison for different TRNG methodologies It should be noticed that the FIPS [37] Standard Statistical Tests (SSTs) have similarities to the AIS 31 SSTs [4].6mW 1mW 117mW n.0042mm2 0. Sigma-Delta Mod. 5MHz 25MHz with GDC ≥1.76Mbs/s n.3V 5. Conclusion and Future Works As stated at the beginning. n. = not standard / ZCC = Zero-Cross Comparator / GDC = Gauss-Distribution Comparator Table 8. n.032mm2 5.3V 1. a. The fact that the thermal noise is the useful signal in this work also allows the use of a relaxed decimation filter because the convolution of part of the upper side spectrum at half the sampling frequency will not effect the proper operation of the high pass Sigma-Delta modulator because there would be added just more thermal noise at the baseband frequency of work which could still be used to generate random numbers.Sweden 64 / 71 . s. s. Sampling Direct-Noise Amplif.a. a. 9.0V 3. a.a.5V 1. 0.0V 1. CMOS 2um CMOS 0. a. Direct-Noise Amplif. AIS 31 [4] n.6um n. n.8um CMOS 0. a.a. a.a. band pass and high pass Sigma-Delta modulator structures it came out through system model simulations concerning the oversampling rate. due to the high amount of necessary computation capacity and lack of time further simulations were decided to be done using the “Zero-Cross Comparator” algorithm leaving the option open for the use or not of a higher bit rate on future works. a.0V 3.12um CMOS 90nm n. n. n.18um CMOS 0. s. Although many simulations were ran to certify this new “Gauss Distribution Comparation” approach. / Year Method Technology Area Voltage Power Clk Freq. From the initial three possible studied low pass.9mW 50uW 1. 1. CMOS 0. Together with the first system simulations there were also determined the DSP decimation filter requirements as well as there were defined and implemented two possible algorithms for the generation of the final random output bit stream where one of them named “Gauss Distribution Comparator” algorithm enables the increase of the out bit stream rate despite of the reduction caused by to the oversampling rate process that follows the signal-processing decimation and without lose of the output entropy if instead a “Zero-Cross Comparator” algorithm is applied. n.5mm2 0. a. = not available / n. 1GHz 10GHz 10KHz 2.6um SBD-MOS n.True Random Number Generator based on a Sigma-Delta Modulator Fig. s.2V n.6mW 25MHz 100MHz 16MHz n. Chaotic System Chaotic System Chaotic System Chaotic System Chaotic System Hybrid System Direct-Noise Amplif. a. 3.11 Switched-Capacitor Sigma-Delta Modulator Circuit Design with additional Input Circuit Ref. 100Mbs/s 50Kbs/s 75Kbs/s 1Gbs/s 10Mbs/s 5Kbs/s 2Kbs/s 5Mbs/s 1Mbs/s n. a. a. s. a. a. but the FIPS allows that some tests to have a certain percentage of error on the randomness on the generated bit stream which is not allowed on the AIS 31 Standard Statistical Tests. AMS 0.8V 3.

Through these required parameters the operational amplifier with common-mode feedback control. Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm . The totally new concept of TRNG with a totally new 2nd order high pass Sigma-Delta modulator built on this work shows that this concept of random number generation is one more possible solution and comparable in performance to other mentioned works.Sweden 65 / 71 . Besides that it would be interesting to implement a layout version of this 2nd order high pass Sigma-Delta modulator to generate the requested amount of random bits to apply the fully AIS 31 Standard Statistical Tests as well as implement on a DSP system the “Gauss Distribution Comparator” algorithm to achieve higher output bit stream rates and analyze the trade offs between the One Fourth with TSinc Compensation Filter requirements and the parameter N for the “Gauss Distribution Comparator” algorithm. Using this reduced version and its equivalent discrete-time system model there were determined the parameter requirements characterization for the operational amplifier. There were then ran circuit simulations for different power-supply voltages and environment temperatures to measure the Sigma-Delta modulator circuit robustness.True Random Number Generator based on a Sigma-Delta Modulator Followed by this analysis there came out two possible topologies to implement the high pass transfer function with a switched-capacitor circuit. electromagnetic interference and other external influences over the generated random output bit stream to better classify this system accordingly to the AIS 31 Document Standard requirements [4]. One classical and one reduced circuit structures were built testifying that they were equivalent and that the reduced version could be used on the further requirement analysis for the different components of the analog circuit design. transmission gate and scaled switched-capacitor for their further implementation using a 90nm CMOS library technology on transistor circuit level design. comparator. the transmission gate and the switched-capacitor transistor circuits were built compounding finally the whole Sigma-Delta modulator Analog-to-Digital converter circuit. the latched comparator. It would be also interesting to check out the robustness of the system on a real hardware application to powersource supply tolerance. One interesting study would also be the design of a decimation signal-processing system which could make fulfill all those AIS 31 Standard Statistical Tests that does not pass when the Flicker Noise Corner frequency gets higher. Another possible study would be the design of an enhanced operational amplifier on 90nm CMOS technology which Monte-Carlo analysis achieve higher percentage process and mismatch fabrication yields. It should be noticed that this is just an initial and original study which opens themes for many other researches like the usage of higher order high-pass Sigma-Delta modulator ADCs with multi bit structures and analysis of the required decimation signal-processing filter resolution which could yield to less digitalsignal processing area and power consumption. Through a carefully analyze on the transfer function equations it was found out that by switching the polarity of the integrating-capacitor on the classic basic low pass cell circuit on alternating clock cycles a high pass transfer function could be implemented with less switching-gates and switched-capacitors for a whole 2nd order high pass Sigma-Delta modulator structure. environment temperature. Additionally to the present built circuit it would be probably required and automatic feedback control system which measures the distribution of the random bits to recalibrate it to AIS 31 Standard Statistical Tests limits. limitations and characteristic SNDR curve for different differential sinusoidal input amplitudes under these different conditions for comparations with theoretical previous results. Through these analysis it was determined the required scaling factor for the input signal circuit and finally using the previous designed digital signal-processing decimation filter and “Zero-Cross Comparator” algorithm an entire TRNG system was built.

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Appendix Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm .Sweden 71 / 71 .True Random Number Generator based on a Sigma-Delta Modulator 11.