Version: 4 September 2012 University of Cincinnati School of Electronic and Computing Systems EECE1975 – Introduction to Digital Systems Laboratory

Project 1

Design a Door Code Detector
Fall 2012

1 Introduction This is a continuation of Lab 9 from the Spring Quarter. The purpose of this laboratory is to fully understand the sequential circuit design process, from specification to the final circuit design, using Verilog and FPGA. It is important to note that you are not allowed to re-use the structurallevel (i.e., gate-level) design from Lab 9. You MUST use data-flow design and behaviorallevel design. 2 Tasks You have probably seen doors that require a person to press a particular sequence of buttons. For example, there might be 16 buttons including 0-9, and A-F. You have to press the start button and then the following sequence 5, A, 4, F to unlock the door, while any other sequence does not unlock the door. Design a door code detector (Moore machine) that has two inputs S and Y where S is the start signal (by a push button) and Y gives the code that is a sequence of logic 0’s and 1’s (by a switch). The detector has one output Z (LED). To open the door (i.e., Z=1), you have to press the S button once and then input Y with sequence 101*0*10 where 1* (0*) means one or more logic 1 (0). Once a correct sequence to unlock the door has been detected, the machine goes back to the initial state unconditionally, and be ready for the next input sequence. You have to use data-flow modeling and behavioral modeling for the sequential circuit design. 2.1 Task 1: Data-Flow Design An architectural-level diagram of the circuit to be implemented in the FPGA is shown in Figure 1. Design the sequential circuit using D-flip-flops. First, implement the sequential circuit in Verilog using data-flow modeling, that is using assign statements to implement the combinational circuit of the sequential machine in Verilog. The D-FF model is provided in Figure 2. 2.2 Task 2: Behavioral Design In this task, implement the sequential circuit using behavioral modeling, i.e., using always, case, ... instructions. 2.3. Clock model and debouncing model One practical design issue using FPGA is that the clock signal of the board is too fast (e.g., 50 MHz) for you to enter the inputs. Thus, you have to reduce the clock frequency. Further, the push buttons on the Basys board are not debounced. Verilog modules for a debounce circuit and related clock model are shown in Figures 3 and 4 below. The relationship between these two modules, and the sequential circuit module is defined by the input/output ports of the modules.
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Debouncing. output reg q ).Version: 4 September 2012 2. Note that the Top module is used to connect all modules together. // clear else q = D. Code_detector (i. posedge clr) if (clr) q=0. In your Verilog design. etc.5Hz R Reset S Debouncing CKT CLK 50MHz CLK-down converter Figure 1. input D. Z LED Y D Combinational circuit R . Note that the goal of the design of this project is a synthesizable. D 1. // latch D input endmodule DFF_wCLear D flip-flop with asynch clear Figure 2. . you should have at least the following modules: D_FF.) to create a single interface to the testbench (for simulation) or the Basys board physical components (for synthesis). and Top. Verilog module of a D flip-flop with asynch clear 2/5 . input clr. the sequential circuit). debounce. clock. Use a top module instantiating all components (sequence detector.e. Overall architecture of the door code decoder. . Also note that a Reset signal must be used to initialize the sequential circuit. always @ (posedge clk. module D_FF( // File name: // Description: input clk..4 Implementation Details The organization of these modules along with any modules created to implement the door code detector should be consistent with the architecture shown in Figure 1. Clock_down_converter.

endmodule Figure 3. reg delay2. reg delay1. // ~1. Verilog model of a push-button debounce circuit. end else begin delay1 <= dbin. module Clock_down_converter( input clock. always @ (posedge clock. delay2 <= 1'b0. // Delays pushbutton by three 4-ms clock periods input clear. 3/5 . delay3 <= delay2. reg delay3.5 Hz clock output clk200 // 200 Hz clock ).Version: 4 September 2012 module Debounce( // File name: debounce. posedge clear) begin if (clear) begin delay1 <= 1'b0. end end assign dbout = delay1 & delay2 & delay3. always @ (posedge clock. else q <= q+1. posedge clear) begin if (clear) q <= 0. delay3 <= 1'b0.v // Description: Delays output of pushbutton until bounce has // settled out. // Resets the debounce action to start of delay input dbin. delay2 <= delay1. // 25-bit counter reg[24:0] q. // Reset down-converter output clk1. // 50 MHz clock input clear. input clock. // from un-debounced push button output dbout // debounced output from pushbutton ). Use with the clock downconverter shown in Figure 4.

The final report must include: 1. 1). 4/5 . The waveform or text display showing the output of your simulation must be viewed in person during the laboratory session. or complete text display of inputs vs outputs showing the simulation results of your Verilog component model. and the hardcopy signed. //80 ns period (for simulation) // assign clk200 = q[17]. and the overall system architecture (like Fig. 3.5 Hz (for board) endmodule Figure 4. A short description of the design requirements. //~1. the testbench. Verilog model of a clock down-converter to provide a 200-Hz clock for the debounce circuit shown in Figure 3. Simulation Waveform or Text Display Results Attach at end of report a signed window capture of the full output waveform. by the TA. This will greatly help the TA to judge the design correctness. Testbench used for simulation. and the photo signed. A 30% bonus will be given if ALL components/modules are properly integrated in a top module and are working. 5. The hardware executing the synthesized Verilog model must be viewed in person during the laboratory session. by the TA.5-Hz clock to clock the counter FF’s slow enough to visually read the counter output.Version: 4 September 2012 end // Uncomment and comment following statements as needed for // simulation and synthesis assign clk200 = q[0]. 2. You must design at least two or more test set with each one represented as a table shown in Table 1. Test plan including tests. 6. and an approximate 1. //200 Hz (for board) // assign clk1 = q[24]. Codes of all modules that are fully functional. You must have the TA sign for each test. //40 ns period (for simulation) assign clk1 = q[1]. 4. Photo Documenting Correct Hardware Implementation Attach at end of report a still photo of your Basys board correctly executing the door code detector design. and simulation waveforms for both codes. including testbench simulation and Basys board execution. 3.0 Reports The design report must include Verilog codes (data flow and behavioral) for the sequential circuit (combinational gates and FFs).

Test set to be used to test the implemented door code detector. 5/5 .Version: 4 September 2012 INPUTS Reset CLK1 CLK2 Y S Expected RESULTS Simulation Basys Board TA Signature Simulation: ______________________________ Basys Board: ______________________________ Table 1.