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Version: 4 September 2012 University of Cincinnati School of Electronic and Computing Systems EECE1975 Introduction to Digital Systems Laboratory

y Project 1

Design a Door Code Detector

Fall 2012

1 Introduction This is a continuation of Lab 9 from the Spring Quarter. The purpose of this laboratory is to fully understand the sequential circuit design process, from specification to the final circuit design, using Verilog and FPGA. It is important to note that you are not allowed to re-use the structurallevel (i.e., gate-level) design from Lab 9. You MUST use data-flow design and behaviorallevel design. 2 Tasks You have probably seen doors that require a person to press a particular sequence of buttons. For example, there might be 16 buttons including 0-9, and A-F. You have to press the start button and then the following sequence 5, A, 4, F to unlock the door, while any other sequence does not unlock the door. Design a door code detector (Moore machine) that has two inputs S and Y where S is the start signal (by a push button) and Y gives the code that is a sequence of logic 0s and 1s (by a switch). The detector has one output Z (LED). To open the door (i.e., Z=1), you have to press the S button once and then input Y with sequence 101*0*10 where 1* (0*) means one or more logic 1 (0). Once a correct sequence to unlock the door has been detected, the machine goes back to the initial state unconditionally, and be ready for the next input sequence. You have to use data-flow modeling and behavioral modeling for the sequential circuit design. 2.1 Task 1: Data-Flow Design An architectural-level diagram of the circuit to be implemented in the FPGA is shown in Figure 1. Design the sequential circuit using D-flip-flops. First, implement the sequential circuit in Verilog using data-flow modeling, that is using assign statements to implement the combinational circuit of the sequential machine in Verilog. The D-FF model is provided in Figure 2. 2.2 Task 2: Behavioral Design In this task, implement the sequential circuit using behavioral modeling, i.e., using always, case, ... instructions. 2.3. Clock model and debouncing model One practical design issue using FPGA is that the clock signal of the board is too fast (e.g., 50 MHz) for you to enter the inputs. Thus, you have to reduce the clock frequency. Further, the push buttons on the Basys board are not debounced. Verilog modules for a debounce circuit and related clock model are shown in Figures 3 and 4 below. The relationship between these two modules, and the sequential circuit module is defined by the input/output ports of the modules.
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2.4 Implementation Details The organization of these modules along with any modules created to implement the door code detector should be consistent with the architecture shown in Figure 1. Note that the goal of the design of this project is a synthesizable. Use a top module instantiating all components (sequence detector, debounce, clock, etc.) to create a single interface to the testbench (for simulation) or the Basys board physical components (for synthesis). In your Verilog design, you should have at least the following modules: D_FF, Clock_down_converter, Debouncing, Code_detector (i.e., the sequential circuit), and Top. Note that the Top module is used to connect all modules together. Also note that a Reset signal must be used to initialize the sequential circuit.
Z LED Y D Combinational circuit R . . . D 1.5Hz R Reset

Debouncing CKT

CLK 50MHz

CLK-down converter

Figure 1. Overall architecture of the door code decoder.

module D_FF( // File name: // Description: input clk, input clr, input D, output reg q ); always @ (posedge clk, posedge clr) if (clr) q=0; // clear else q = D; // latch D input endmodule

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module Debounce( // File name: debounce.v // Description: Delays output of pushbutton until bounce has // settled out. input clock, // Delays pushbutton by three 4-ms clock periods input clear, // Resets the debounce action to start of delay input dbin, // from un-debounced push button output dbout // debounced output from pushbutton ); reg delay1; reg delay2; reg delay3; always @ (posedge clock, posedge clear) begin if (clear) begin delay1 <= 1'b0; delay2 <= 1'b0; delay3 <= 1'b0; end else begin delay1 <= dbin; delay2 <= delay1; delay3 <= delay2; end end assign dbout = delay1 & delay2 & delay3; endmodule

Figure 3. Verilog model of a push-button debounce circuit. Use with the clock downconverter shown in Figure 4.

module Clock_down_converter( input clock, // 50 MHz clock input clear, // Reset down-converter output clk1, // ~1.5 Hz clock output clk200 // 200 Hz clock ); // 25-bit counter reg[24:0] q; always @ (posedge clock, posedge clear) begin if (clear) q <= 0; else q <= q+1;

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end // Uncomment and comment following statements as needed for // simulation and synthesis assign clk200 = q[0]; //40 ns period (for simulation) assign clk1 = q[1]; //80 ns period (for simulation) // assign clk200 = q[17]; //200 Hz (for board) // assign clk1 = q[24]; //~1.5 Hz (for board) endmodule

Figure 4. Verilog model of a clock down-converter to provide a 200-Hz clock for the debounce circuit shown in Figure 3, and an approximate 1.5-Hz clock to clock the counter FFs slow enough to visually read the counter output.

3.0 Reports The design report must include Verilog codes (data flow and behavioral) for the sequential circuit (combinational gates and FFs), the testbench, and simulation waveforms for both codes. This will greatly help the TA to judge the design correctness. A 30% bonus will be given if ALL components/modules are properly integrated in a top module and are working. The final report must include: 1. A short description of the design requirements, and the overall system architecture (like Fig. 1). 2. Codes of all modules that are fully functional. 3. Testbench used for simulation. 4. Test plan including tests. You must design at least two or more test set with each one represented as a table shown in Table 1. You must have the TA sign for each test, including testbench simulation and Basys board execution. 5. Simulation Waveform or Text Display Results Attach at end of report a signed window capture of the full output waveform, or complete text display of inputs vs outputs showing the simulation results of your Verilog component model. The waveform or text display showing the output of your simulation must be viewed in person during the laboratory session, and the hardcopy signed, by the TA. 6. Photo Documenting Correct Hardware Implementation
Attach at end of report a still photo of your Basys board correctly executing the door code detector design. The hardware executing the synthesized Verilog model must be viewed in person during

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TA Signature Simulation: ______________________________ Basys Board: ______________________________

Table 1. Test set to be used to test the implemented door code detector.

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