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Abhishek
Department of Electrical and Computer Engineering
University of Toronto
September 5, 2012
Abhishek Incremental Power Grid Veriﬁcation 1 / 32
Outline
1
Introduction
Vectorless Veriﬁcation
Incremental Grid Veriﬁcation
Contributions
2
Background
RC Grid Veriﬁcation
RLC Grid Veriﬁcation
Model Order Reduction
3
Proposed Approach
Efﬁcient Bounds
Macromodeling
Results
4
Extensions
Dimensionality Reduction
Chip Power Model
5
Conclusions
Abhishek Incremental Power Grid Veriﬁcation 2 / 32
Introduction Vectorless Veriﬁcation
The Need
Modern integrated circuits (IC) designs are susceptible to supply
voltage ﬂuctuations:
Reduced supply voltage levels
Increase in active and leakage currents
Traditional veriﬁcation ﬂows based on circuit simulation has
serious drawbacks:
Number of traces to cover the space of voltage drops is intractable
Require complete knowledge of current waveforms
Grid veriﬁcation should be done early in the design ﬂow
Solution:
A vectorless and early power grid veriﬁcation approach
Abhishek Incremental Power Grid Veriﬁcation 3 / 32
Introduction Vectorless Veriﬁcation
Constraintsbased Veriﬁcation
Vectorless approach based on partial current speciﬁcations
Current constraints are used to capture uncertainty about circuit
behavior
Grid veriﬁcation is reduced to ﬁnding worstcase voltage drop over
all possible currents satisfying the constraints
Two types of constraints:
Local constraints: upper bounds on individual current sources
Global constraints: upper bounds on sums of groups of currents
Combined together, local and global constraints form a feasible
space of currents F
Abhishek Incremental Power Grid Veriﬁcation 4 / 32
Introduction Incremental Grid Veriﬁcation
Motivation
Abhishek Incremental Power Grid Veriﬁcation 5 / 32
Grid veriﬁcation requires solving a linear program (LP) for every
node
Veriﬁcation of the entire grid can become overkill:
Large size of modern power grids
Design changes made to local region of previously veriﬁed grid
need to be analyzed
Cases like IP reuse, where a portion of grid need not be veriﬁed
Incremental Power Grid Veriﬁcation becomes a necessity!!!
Introduction Incremental Grid Veriﬁcation
Introducing Incremental Veriﬁcation
Abhishek Incremental Power Grid Veriﬁcation 6 / 32
User identiﬁes part of the grid,
that need not be veriﬁed,
referred to as subgrid
Veriﬁcation is required for nodes
outside the subgrid, also known
as external nodes
Nodes inside the subgrid can
either be port or internal nodes:
Port nodes connect the
subgrid to external nodes
All other subgrid nodes are
internal nods
Introduction Contributions
Incremental Vectorless Veriﬁcation
Abhishek Incremental Power Grid Veriﬁcation 7 / 32
A technique for incremental vectorless veriﬁcation for R grids
was proposed by Kouroussis et al. [ICCAD 05]
In this work, incremental vectorless veriﬁcation is extended to
the transient case through the following two contributions:
Efﬁcient computation of upper bounds on worstcase voltage
drops at internal nodes
Macromodeling of the internal grid section by:
Adapting multiport Norton’s theorem proposed in HiPRIME by
Lee et al. [TCAD 05] to our veriﬁcation framework
Combining moment matchingbased reduction by Liao and
Dai [ICCAD 95] with node eliminationbased reduction proposed
by B. Sheehan [TCAD 07] to reduce the resultant passive RC
circuit
Background RC Grid Veriﬁcation
Grid Model
Abhishek Incremental Power Grid Veriﬁcation 8 / 32
g
c
g
g
c
g g
g
g
c c
V
dd
i
(s,1)
(t)
c
g
c
g g g
g
c c c
g g
c
g g g
c c
g
i (t)
(s,2)
System equation:
Gv(t ) +C
˙
v(t ) = i (t )
Background RC Grid Veriﬁcation
Veriﬁcation
Applying a ﬁnitedifference approximation to RC system equation:
Av(t ) =
C
∆t
v(t −∆t ) + i (t )
where
A = G+
C
∆t
An upper bound on the worstcase voltage drop vector was
proposed by Ferzli et al. [ICCAD 07]:
v
ub
=
_
I +G
−1 C
∆t
_
V
a
where V
a
is the worstcase voltage drop vector at t = ∆t in the
special case when i (t ) = 0, ∀t ≤ 0 and is expressed as:
V
a
= emax
∀i ∈F
(A
−1
i )
with emax being an operator to perform elementwise
maximization of its vector argument.
Abhishek Incremental Power Grid Veriﬁcation 9 / 32
Background RLC Grid Veriﬁcation
Grid Model
Abhishek Incremental Power Grid Veriﬁcation 10 / 32
g
i
(s,1)
(t)
g
l g
c
g g
g
V
dd
g
l g
l
c
g g
c c i (t)
(s,2)
c
g g
c c c
l g
g g
c
g g
c c c
g
System equations:
Gv(t ) +C
˙
v(t ) −Mi (t ) = i
s
(t )
M
T
v(t ) +L
˙
i (t ) = 0
Background RLC Grid Veriﬁcation
Veriﬁcation
The RLC grid can be transformed into a reduced circuit by
eliminating the inductive branch currents as proposed by Abdul
Ghani et al. [TCAD 11]
v(t ) = D
−1
Ev(t −∆t ) +D
−1
i
s
(t )
where D =
_
G+
C
∆t
+M
L
∆t
−1
M
T
_
and E =
_
C
∆t
+M
ˆ
G
_
To compute the bounds at inﬁnity, upper and lower bounds on
voltage drops for r time steps ahead in time are computed and are
given by:
w
r
= w
r −1
+ eopt
∀i
s
∈F
[(D
−1
E)
r −1
D
−1
i
s
]
The upper and lower bounds at inﬁnity are now given by:
_
v
ub
(∞)
v
lb
(∞)
_
= (I −R)
−1
w
r
where R is composed of N and elementwise absolute values of
the entries in N.
Abhishek Incremental Power Grid Veriﬁcation 11 / 32
Background Model Order Reduction
RC MOR
A large RC interconnect network is partitioned into smaller
subnetworks
Admittance matrix looking into the ports is approximated using the
ﬁrst two order moments as:
Y(s) ≈ M
0
+M
1
s
where M
0
and M
1
are zero and ﬁrstorder moment matrices
respectively
A 2π model is constructed between each pair of ports by matching
the moments:
Circuit between pair of ports is synthesized using Tmodel
Porttoground elements are modeled using parallel RC model
Abhishek Incremental Power Grid Veriﬁcation 12 / 32
Background Model Order Reduction
Node Elimination (TICER)
Abhishek Incremental Power Grid Veriﬁcation 13 / 32
The reduction is based on the time
constant of a node
_
τ
N
=
C
N
G
N
_
where C
N
and G
N
are respectively, the sums of
capacitances and conductances incident
on the node.
If τ
N
is less than a userspeciﬁed value of
time constant, the node is removed as
follows:
If nodes i and j were connected to node
N by conductances g
iN
and g
jN
, insert a
conductance
_
g
iN
g
jN
G
N
_
between i and j
If node i had a capacitor c
iN
and j had a
resistor g
jN
, insert a capacitor
_
c
iN
g
jN
G
N
_
between i and j
port  i
C
R
ij2
R
ij1
ij
port  j
Tmodel
ii
port  i R
ii
C
parallel RC model
Proposed Approach Efﬁcient Bounds
Estimating Internal Nodes’ Voltage Drops
Partitioned system equation:
_
_
G
11
G
12
0
G
T
12
G
22
G
23
0 G
T
23
G
33
_
_
_
_
v
ext
(t )
v
prt
(t )
v
int
(t )
_
_
+
_
_
C
ext
0 0
0 C
prt
0
0 0 C
int
_
_
_
_
˙
v
ext
(t )
˙
v
prt
(t )
˙
v
int
(t )
_
_
=
_
_
i
s,ext
(t )
i
s,prt
(t )
i
s,int
(t )
_
_
An upper bound on v
ub
can be found as:
v
ub
≤
_
I +G
−1 C
∆t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
−1
int
_
_
emax
∀i
s
∈F
_
_
v
ext
(∆t )
v
prt
(∆t )
i
s,int
(∆t )
_
_
Because emax
∀i
s
∈F
(i
s,int
(∆t )) = i
L,int
(vector of local constraint values
for internal current sources), computing an upper bound on v
ub
requires:
Solving LPs for external and port nodes,
Standard system solve
Abhishek Incremental Power Grid Veriﬁcation 14 / 32
Proposed Approach Macromodeling
Norton Equivalent Current Sources
Abhishek Incremental Power Grid Veriﬁcation 15 / 32
To ﬁnd Norton equivalent currents at port nodes that will
replace the internal current sources:
Disconnect the subgrid from rest of the grid
Connect each port node to ground
Evaluate current ﬂowing through short circuits
Proposed Approach Macromodeling
Modiﬁed Grid
System equation for the isolated subgrid with port nodes
connected to ground:
G
33
v
int
(t ) +C
int
˙
v
int
(t ) = i
s,int
(t )
Current through port node to ground will be given by:
i
(t ) = −G
23
v
int
(t )
Using the special case used to deﬁne V
a
, the voltage at time
t = ∆t in this modiﬁed grid will be given by:
ˆ
v(∆t ) = A
−1
ˆ
Ji
s
(∆t )
where
ˆ
J =
_
_
I
ext
0 0
0 I
prt
T
0 0 0
_
_
Abhishek Incremental Power Grid Veriﬁcation 16 / 32
Proposed Approach Macromodeling
Reducing the Passive Subgrid
Abhishek Incremental Power Grid Veriﬁcation 17 / 32
After moving internal current sources to port nodes, we are left
with a passive RC internal network:
To reduce the passive network:
RC MOR to give porttoport connections using Tmodel and
parallel RC model
Node elimination on every new internal node generated by the
Tmodel
Conductance values smaller than a threshold are removed by
setting those entries to 0
Proposed Approach Macromodeling
Veriﬁcation after Macromodeling
New system matrices:
˜
G =
_
_
G
11
G
12
0
G
T
12
˜
G
22
˜
G
23
0
˜
G
T
23
˜
G
33
_
_
,
˜
C =
_
_
C
ext
0 0
0
˜
C
prt
0
0 0
˜
C
int
_
_
Reduced size:
˜
n = n
ext
+ n
prt
+
˜
n
int
Voltage at time t = ∆t for the reduced grid:
˜
v(∆t ) =
˜
A
−1
˜
Ji
s
(∆t )
Upper bound on worstcase voltage drop:
˜
v
ub
=
_
I +G
−1 C
∆t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
−1
int
_
_
_
¸
¸
_
emax
∀i
s
∈F
(
˜
v
ext
(∆t ))
emax
∀i
s
∈F
(
˜
v
prt
(∆t ))
i
L,int
_
¸
¸
_
Abhishek Incremental Power Grid Veriﬁcation 18 / 32
Proposed Approach Results
Experimental Setup
A C++ implementation was written to test the proposed approach
Test grids were generated from user speciﬁcations:
Grid dimensions
Metal layers, pitch and width per layer
Supply voltage sites and current source distribution
Consistent with 1.1 V 65nm CMOS technology
SPAI (Abdul Ghani et al. [DAC 09]) was used to compute
approximate inverse
Computations were done using a 2.6 GHz Linux machine with
24Gb of RAM
Abhishek Incremental Power Grid Veriﬁcation 19 / 32
Proposed Approach Results
Experimental Results
δ
1
= 0.1mV δ
2
= 0.01mV τ = 5ps κ = 5 ×10
−3
Speed and accuracy after using efﬁcient bounds computation
Power Grid Subgrid Max Error Speed
Name Nodes n
int
n
prt
(mV) Up
G1 32,554 15,714 208 0.07 2.17x
G2 72,692 42,764 348 0.07 2.47x
G3 128,241 95,294 413 0.08 4.46x
G4 162,087 124,824 518 0.08 4.8x
Speed and accuracy after applying macromodeling
Power Max Error Avg. % CPU time Speed
Grid (mV) Error (s) Up
G1 1.35 1.05 1.06 h. 2.83x
G2 2.01 0.88 2.36 h. 3.26x
G3 3.13 1.11 2.64 h. 7.08x
G4 2.6 1.14 3.14 h. 8.05x
Abhishek Incremental Power Grid Veriﬁcation 20 / 32
Proposed Approach Results
Error Analysis
0 0.02 0.04 0.06 0.08 0.1
−30
−20
−10
0
10
20
30
voltage drop (V)
r
e
l
a
t
i
v
e
e
r
r
o
r
(
%
)
3mV
Relative Error Plot (macromodeling)
Abhishek Incremental Power Grid Veriﬁcation 21 / 32
Proposed Approach Results
Runtime Analysis
0 20 40 60 80 100
0
10
20
30
40
50
60
70
80
Size of Subgrid (% of Full Grid)
S
p
e
e
d
u
p
(
x
)
0 20 40 60
0
2
4
1
3
Using Efficient Bounds
After Macromodeling
Theoretical
Abhishek Incremental Power Grid Veriﬁcation 22 / 32
Extensions Dimensionality Reduction
New Feasible Space
In the original approach, the internal current sources were not
physically moved to port nodes
Since port nodes are less in number, runtime savings can be a
result if internal current sources are replaced by current sources
at port nodes
A new feasible space in the modiﬁed current source conﬁguration:
ˆ
F =
_
i
s
: ∃ i
s
∈ F, for which i
s
= (
˜
Ji
s
)
η
_
where η = n
ext
+ n
prt
and the notation 
η
implies either ﬁrst η
entries of vector argument or the ﬁrst η ×η elements of a matrix
argument
The upper bound can now be computed as:
˜
v
ub
=
_
I +G
−1 C
∆t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
−1
int
_
_
_
emax
∀i
s
∈
ˆ
F
(
˜
A
−1

η
i
s
)
i
L,int
_
Abhishek Incremental Power Grid Veriﬁcation 23 / 32
Extensions Dimensionality Reduction
Deﬁning
ˆ
F
ˆ
F can be deﬁned by ﬁnding the convex hull of the points lying
inside the space that is computationally very expensive
An approximate algorithm to compute multidimensional convex
hull of the points in space was proposed by Xu et al. [AMC 98]
Choose direction vectors that are distributed regularly on the unit
hypersphere
Maximize and minimize the inner product over all points inside
ˆ
F
Above algorithm is modiﬁed to better approximate the space
ˆ
F
Direction vectors are chosen based on transformation matrix and
original constraint matrix
Since extreme points of
ˆ
F are not known, optimization operations
are done in F
Abhishek Incremental Power Grid Veriﬁcation 24 / 32
Extensions Dimensionality Reduction
Experimental Results
δ
1
= 0.1mV δ
2
= 0.01mV τ = 5ps κ = 5 ×10
−3
Flat Original Modified
0
50
100
150
200
250
300
350
400
R
u
n
t
i
m
e
(
m
i
n
u
t
e
s
)
Verification Approaches
Original Modified
0
20
40
SPAI
Macro
LP
Abhishek Incremental Power Grid Veriﬁcation 25 / 32
Extensions Dimensionality Reduction
Error Analysis
Relative Error Plot (modiﬁed approach)
Abhishek Incremental Power Grid Veriﬁcation 26 / 32
Extensions Chip Power Model
Introducing CPM
Abhishek Incremental Power Grid Veriﬁcation 27 / 32
CPM is a reduced order model that captures the electrical
behavior of the onchip power grid
Such models are used to design the chippackage PDNs while
taking into account the behavior of onchip interconnects
Similar to incremental veriﬁcation:
Verify only the package (external) nodes
Macromodel the onchip network (subgrid)
V
dd
V
dd
RLC Package Interconnections RC Onchip Interconnections
Extensions Chip Power Model
Constructing CPM in Vectorless Veriﬁcation Context
Incremental veriﬁcation is adapted to RLC veriﬁcation context
The lower and upper bounds on worstcase voltage drops at time
t = r ∆t after macromodeling can be expressed as:
_
˜
w
r ,ext
˜
w
r ,prt
_
=
_
˜
w
r −1,ext
˜
w
r −1,prt
_
+ eopt
∀i
s
∈
˜
F
r ∆t
[((
˜
D
−1
˜
E)
r −1
˜
D
−1
)
η
i
s
]
_
w
r ,int ,max
≈
_
A
−1
int
C
int
∆t
_
r −1
A
−1
int
i
L,int
+T
T
r ∆t
˜
w
r ,prt ,max
w
r ,int ,min
≈ T
T
r ∆t
˜
w
r ,prt ,min
_
where i
s
is the ηvector of modiﬁed current source conﬁguration,
˜
F
r ∆t
is an approximation for the new feasible space at t = r ∆t
with the transformation matrix given by:
T
r ∆t
= −G
23
_
A
−1
int
C
int
∆t
_
r −1
A
−1
int
A
int
T
T
r ∆t
=
C
T
int
∆t
T
T
(r −1)∆t
T
r ∆t
can be computed iteratively by using the above relation
Abhishek Incremental Power Grid Veriﬁcation 28 / 32
Extensions Chip Power Model
Experimental Results
δ
1
= 0.1mV δ
2
= 0.01mV τ = 5ps κ = 5 ×10
−3
Speed and accuracy after constructing the CPM using Approach I
Power Grid Onchip Grid Max Error (mV) Avg. % Error Speed
Name n n
int
n
prt
v
ub
v
lb
v
ub
v
lb
Up
A1 13,905 12,577 664 4 2.6 8.8 1.2 18.16x
A2 24,548 22,208 1,170 5.5 4 10.2 5.1 13.36x
A3 34,183 30,925 1,629 10.9 3.2 12.8 4.3 10.95x
A4 52,968 47,920 2,524 11.19 3.2 12.9 2.7 11.83x
Approaches to Construct CPM
Name Construct T
r ∆t
Moving Current Sources Speedup Rank Accuracy
Approach I Iterative Modiﬁed I II
Approach II SPAI Modiﬁed III II
Approach III Iterative Original II I
Relatively: I = best, II = better, III = good
Abhishek Incremental Power Grid Veriﬁcation 29 / 32
Extensions Chip Power Model
Runtime Analysis
A1 A2 A3 A4
0
1
2
3
4
5
6
7
Test Grids
R
u
n
t
i
m
e
(
h
o
u
r
s
)
Flat
Approach I
Approach II
Approach III
Abhishek Incremental Power Grid Veriﬁcation 30 / 32
Conclusions
To Sum Up
Power grid veriﬁcation is essential to design veriﬁcation
Constraintsbased veriﬁcation allows for early veriﬁcation of the
power grids
We proposed a vectorless approach for incremental grid
veriﬁcation for conductiveonly and RC grid models:
It provides the ability to efﬁciently perform veriﬁcation of a part of
the grid
It reduces the size of the problem by macromodeling the subgrid
It can efﬁciently compute the upper bounds vector without verifying
the internal nodes
We also applied this approach to construct Chip Power Model for
onchip interconnects that provide an efﬁcient way to design the
package while considering the behavior of onchip PDN.
Abhishek Incremental Power Grid Veriﬁcation 31 / 32
Thank You
Questions
Abhishek Incremental Power Grid Veriﬁcation 32 / 32
Outline
1
Introduction Vectorless Veriﬁcation Incremental Grid Veriﬁcation Contributions Background RC Grid Veriﬁcation RLC Grid Veriﬁcation Model Order Reduction Proposed Approach Efﬁcient Bounds Macromodeling Results Extensions Dimensionality Reduction Chip Power Model Conclusions
Abhishek Incremental Power Grid Veriﬁcation 2 / 32
2
3
4
5
Introduction
Vectorless Veriﬁcation
The Need
Modern integrated circuits (IC) designs are susceptible to supply voltage ﬂuctuations:
Reduced supply voltage levels Increase in active and leakage currents
Traditional veriﬁcation ﬂows based on circuit simulation has serious drawbacks:
Number of traces to cover the space of voltage drops is intractable Require complete knowledge of current waveforms Grid veriﬁcation should be done early in the design ﬂow
Solution:
A vectorless and early power grid veriﬁcation approach
Abhishek Incremental Power Grid Veriﬁcation 3 / 32
local and global constraints form a feasible space of currents F Abhishek Incremental Power Grid Veriﬁcation 4 / 32 .Introduction Vectorless Veriﬁcation Constraintsbased Veriﬁcation Vectorless approach based on partial current speciﬁcations Current constraints are used to capture uncertainty about circuit behavior Grid veriﬁcation is reduced to ﬁnding worstcase voltage drop over all possible currents satisfying the constraints Two types of constraints: Local constraints: upper bounds on individual current sources Global constraints: upper bounds on sums of groups of currents Combined together.
where a portion of grid need not be veriﬁed Incremental Power Grid Veriﬁcation becomes a necessity!!! Abhishek Incremental Power Grid Veriﬁcation 5 / 32 .Introduction Incremental Grid Veriﬁcation Motivation Grid veriﬁcation requires solving a linear program (LP) for every node Veriﬁcation of the entire grid can become overkill: Large size of modern power grids Design changes made to local region of previously veriﬁed grid need to be analyzed Cases like IP reuse.
referred to as subgrid Veriﬁcation is required for nodes outside the subgrid.Introduction Incremental Grid Veriﬁcation Introducing Incremental Veriﬁcation User identiﬁes part of the grid. also known as external nodes Nodes inside the subgrid can either be port or internal nodes: Port nodes connect the subgrid to external nodes All other subgrid nodes are internal nods Abhishek Incremental Power Grid Veriﬁcation 6 / 32 . that need not be veriﬁed.
[ICCAD 05] In this work. [TCAD 05] to our veriﬁcation framework Combining moment matchingbased reduction by Liao and Dai [ICCAD 95] with node eliminationbased reduction proposed by B.Introduction Contributions Incremental Vectorless Veriﬁcation A technique for incremental vectorless veriﬁcation for R grids was proposed by Kouroussis et al. Sheehan [TCAD 07] to reduce the resultant passive RC circuit Abhishek Incremental Power Grid Veriﬁcation 7 / 32 . incremental vectorless veriﬁcation is extended to the transient case through the following two contributions: Efﬁcient computation of upper bounds on worstcase voltage drops at internal nodes Macromodeling of the internal grid section by: Adapting multiport Norton’s theorem proposed in HiPRIME by Lee et al.
Background RC Grid Veriﬁcation Grid Model g g c c g g g c g g c c g g g i (s.2) (t) c g V dd c System equation: ˙ Gv (t) + Cv (t) = i(t) Abhishek Incremental Power Grid Veriﬁcation 8 / 32 .1) (t) c g g g c g g c c g g c i (s.
∀t ≤ 0 and is expressed as: Va = emax(A−1 i) ∀i∈F with emax being an operator to perform elementwise maximization of its vector argument. [ICCAD 07]: C vub = I + G−1 ∆t Va where Va is the worstcase voltage drop vector at t = ∆t in the special case when i(t) = 0. Abhishek Incremental Power Grid Veriﬁcation 9 / 32 .Background RC Grid Veriﬁcation Veriﬁcation Applying a ﬁnitedifference approximation to RC system equation: Av (t) = C ∆t v (t − ∆t) + i(t) where A=G+ C ∆t An upper bound on the worstcase voltage drop vector was proposed by Ferzli et al.
2) (t) c g l g c g l g V dd c c System equations: ˙ Gv (t) + Cv (t) − Mi(t) = is (t) ˙ MT v (t) + Li(t) = 0 Abhishek Incremental Power Grid Veriﬁcation 10 / 32 .1) (t) c g c g g c c g g g g c c i (s.Background RLC Grid Veriﬁcation Grid Model l g g c g g l g c g g i (s.
Abhishek Incremental Power Grid Veriﬁcation 11 / 32 . upper and lower bounds on voltage drops for r time steps ahead in time are computed and are given by: wr = wr −1 + eopt [(D−1 E)r −1 D−1 is ] ∀is ∈F The upper and lower bounds at inﬁnity are now given by: vub (∞) vlb (∞) = (I − R)−1 wr where R is composed of N and elementwise absolute values of the entries in N. [TCAD 11] v (t) = D−1 Ev (t − ∆t) + D−1 is (t) where D = G + C ∆t L + M ∆t −1 MT and E = C ∆t ˆ + MG To compute the bounds at inﬁnity.Background RLC Grid Veriﬁcation Veriﬁcation The RLC grid can be transformed into a reduced circuit by eliminating the inductive branch currents as proposed by Abdul Ghani et al.
Background Model Order Reduction RC MOR A large RC interconnect network is partitioned into smaller subnetworks Admittance matrix looking into the ports is approximated using the ﬁrst two order moments as: Y(s) ≈ M0 + M1 s where M0 and M1 are zero and ﬁrstorder moment matrices respectively A 2π model is constructed between each pair of ports by matching the moments: Circuit between pair of ports is synthesized using Tmodel Porttoground elements are modeled using parallel RC model Abhishek Incremental Power Grid Veriﬁcation 12 / 32 .
insert a conductance between i and j If node i had a capacitor ciN and j had a c g resistor gjN .j Tmodel port .Background Model Order Reduction Node Elimination (TICER) The reduction is based on the time C constant of a node τN = GN where CN N and GN are respectively. the node is removed as follows: If nodes i and j were connected to node N by conductances giN and gjN . If τN is less than a userspeciﬁed value of time constant. insert a capacitor iN NjN G between i and j Abhishek Incremental Power Grid Veriﬁcation Rij1 Rij2 port . the sums of capacitances and conductances incident on the node.i Rii Cii giN gjN GN parallel RC model 13 / 32 .i Cij port .
Proposed Approach Efﬁcient Bounds Estimating Internal Nodes’ Voltage Drops Partitioned system equation: G11 G12 0 vext (t) Cext GT G22 G23 vprt (t) + 0 12 vint (t) 0 0 GT G33 23 0 Cprt 0 ˙ 0 vext (t) is.int (∆t)) = iL. computing an upper bound on vub requires: Solving LPs for external and port nodes.int (vector of local constraint values ∀is ∈F for internal current sources).int (∆t) A−1 int Because emax(is.int (t) An upper bound on vub can be found as: vub ≤ I + C G−1 ∆t Iext 0 0 0 Iprt TT 0 vext (∆t) emax vprt (∆t) 0 ∀is ∈F is. Standard system solve Abhishek Incremental Power Grid Veriﬁcation 14 / 32 .ext (t) ˙ 0 vprt (t) = is.prt (t) ˙ Cint vint (t) is.
Proposed Approach Macromodeling Norton Equivalent Current Sources To ﬁnd Norton equivalent currents at port nodes that will replace the internal current sources: Disconnect the subgrid from rest of the grid Connect each port node to ground Evaluate current ﬂowing through short circuits Abhishek Incremental Power Grid Veriﬁcation 15 / 32 .
Proposed Approach Macromodeling Modiﬁed Grid System equation for the isolated subgrid with port nodes connected to ground: G33 v int (t) ˙ + Cint vint (t) = is. the voltage at time t = ∆t in this modiﬁed grid will be given by: ˆ ˆ v (∆t) = A−1 Jis (∆t) where Iext ˆ= 0 J 0 0 Iprt 0 0 T 0 Abhishek Incremental Power Grid Veriﬁcation 16 / 32 .int (t) Current through port node to ground will be given by: i (t) = −G23 v int (t) Using the special case used to deﬁne Va .
we are left with a passive RC internal network: To reduce the passive network: RC MOR to give porttoport connections using Tmodel and parallel RC model Node elimination on every new internal node generated by the Tmodel Conductance values smaller than a threshold are removed by setting those entries to 0 Abhishek Incremental Power Grid Veriﬁcation 17 / 32 .Proposed Approach Macromodeling Reducing the Passive Subgrid After moving internal current sources to port nodes.
12 ˜ ˜ 0 GT G33 23 Cext ˜ C= 0 0 0 ˜ Cprt 0 0 0 ˜ Cint Reduced size: ˜ ˜ n = next + nprt + nint Voltage at time t = ∆t for the reduced grid: ˜ ˜ ˜ v (∆t) = A−1 Jis (∆t) Upper bound on worstcase voltage drop: C ˜ vub = I + G−1 ∆t Iext 0 0 0 Iprt TT emax(vext (∆t)) ˜ 0 ∀is ∈F 0 emax(vprt (∆t)) ∀is ∈F ˜ A−1 int iL.int Abhishek Incremental Power Grid Veriﬁcation 18 / 32 .Proposed Approach Macromodeling Veriﬁcation after Macromodeling New system matrices: G11 G12 0 ˜ ˜ ˜ G = GT G22 G23 .
pitch and width per layer Supply voltage sites and current source distribution Consistent with 1. [DAC 09]) was used to compute approximate inverse Computations were done using a 2.6 GHz Linux machine with 24Gb of RAM Abhishek Incremental Power Grid Veriﬁcation 19 / 32 .1 V 65nm CMOS technology SPAI (Abdul Ghani et al.Proposed Approach Results Experimental Setup A C++ implementation was written to test the proposed approach Test grids were generated from user speciﬁcations: Grid dimensions Metal layers.
8x Speed and accuracy after applying macromodeling Power Grid G1 G2 G3 G4 Max Error (mV) 1. 2.08 0.241 162.07 0.83x 3.14 h.14 CPU time (s) 1.88 1.Proposed Approach Results Experimental Results δ1 = 0. 2.26x 7.05x Abhishek Incremental Power Grid Veriﬁcation 20 / 32 .6 Avg.05 0.294 124.47x 4.714 42.11 1.13 2.087 Subgrid nint nprt 15. % Error 1.64 h.764 95.554 72.692 128.46x 4.08 Speed Up 2. 3.01mV τ = 5ps κ = 5 × 10−3 Speed and accuracy after using efﬁcient bounds computation Power Grid Name Nodes G1 G2 G3 G4 32.1mV δ2 = 0.07 0.824 208 348 413 518 Max Error (mV) 0.17x 2.35 2.08x 8.36 h. Speed Up 2.01 3.06 h.
Proposed Approach Results Error Analysis 30 3mV 20 relative error (%) 10 0 −10 −20 −30 0 0.06 voltage drop (V) 0.02 0.1 Relative Error Plot (macromodeling) Abhishek Incremental Power Grid Veriﬁcation 21 / 32 .04 0.08 0.
Proposed Approach Results Runtime Analysis 80 70 60 4 Speed up (x) 50 3 40 30 20 10 0 0 2 1 0 0 20 Using Efficient Bounds After Macromodeling Theoretical 20 40 60 80 100 40 60 Size of Subgrid (% of Full Grid) Abhishek Incremental Power Grid Veriﬁcation 22 / 32 .
the internal current sources were not physically moved to port nodes Since port nodes are less in number.int 23 / 32 Abhishek Incremental Power Grid Veriﬁcation . runtime savings can be a result if internal current sources are replaced by current sources at port nodes A new feasible space in the modiﬁed current source conﬁguration: ˜ ˆ F = is : ∃ is ∈ F. for which is = (Jis )η where η = next + nprt and the notation η implies either ﬁrst η entries of vector argument or the ﬁrst η × η elements of a matrix argument The upper bound can now be computed as: ˜ vub = I + C G−1 ∆t Iext 0 0 0 Iprt TT 0 0 A−1 int ˜ emax(A−1 η is ) ˆ ∀is ∈F iL.Extensions Dimensionality Reduction New Feasible Space In the original approach.
[AMC 98] Choose direction vectors that are distributed regularly on the unit hypersphere ˆ Maximize and minimize the inner product over all points inside F ˆ Above algorithm is modiﬁed to better approximate the space F Direction vectors are chosen based on transformation matrix and original constraint matrix ˆ Since extreme points of F are not known. optimization operations are done in F Abhishek Incremental Power Grid Veriﬁcation 24 / 32 .Extensions Dimensionality Reduction ˆ Deﬁning F ˆ F can be deﬁned by ﬁnding the convex hull of the points lying inside the space that is computationally very expensive An approximate algorithm to compute multidimensional convex hull of the points in space was proposed by Xu et al.
01mV τ = 5ps κ = 5 × 10−3 400 350 300 Runtime (minutes) 250 40 200 150 100 50 0 Flat Original Verification Approaches Modified 20 0 SPAI Macro LP Original Modified Abhishek Incremental Power Grid Veriﬁcation 25 / 32 .Extensions Dimensionality Reduction Experimental Results δ1 = 0.1mV δ2 = 0.
Extensions Dimensionality Reduction Error Analysis Relative Error Plot (modiﬁed approach) Abhishek Incremental Power Grid Veriﬁcation 26 / 32 .
Extensions Chip Power Model Introducing CPM CPM is a reduced order model that captures the electrical behavior of the onchip power grid Such models are used to design the chippackage PDNs while taking into account the behavior of onchip interconnects Similar to incremental veriﬁcation: Verify only the package (external) nodes Macromodel the onchip network (subgrid) Vdd Vdd RLC Package Interconnections RC Onchip Interconnections Abhishek Incremental Power Grid Veriﬁcation 27 / 32 .
int + TT∆t wr .prt = ˜ wr −1.ext ˜ wr −1.prt ˜ ˜ ˜ + eopt [((D−1 E)r −1 D−1 )η is ] ˜ ∀is ∈Fr ∆t wr .max r int ˜ ≈ TT∆t wr .min r r −1 where is is the ηvector of modiﬁed current source conﬁguration.ext ˜ wr .prt.max ≈ A−1 Cint int ∆t wr .min ˜ A−1 iL.prt.int.int.Extensions Chip Power Model Constructing CPM in Vectorless Veriﬁcation Context Incremental veriﬁcation is adapted to RLC veriﬁcation context The lower and upper bounds on worstcase voltage drops at time t = r ∆t after macromodeling can be expressed as: ˜ wr . ˜ Fr ∆t is an approximation for the new feasible space at t = r ∆t with the transformation matrix given by: Tr ∆t = −G23 A−1 Cint int ∆t Aint TT∆t = r r −1 A−1 int CT T int ∆t T(r −1)∆t Tr ∆t can be computed iteratively by using the above relation Abhishek Incremental Power Grid Veriﬁcation 28 / 32 .
170 1.83x Approaches to Construct CPM Name Approach I Approach II Approach III Construct Tr ∆t Iterative SPAI Iterative Moving Current Sources Modiﬁed Modiﬁed Original Relatively: I = best.2 Avg.9 11.3 2.8 10.9 1.95x 11.629 2.01mV τ = 5ps κ = 5 × 10−3 Speed and accuracy after constructing the CPM using Approach I Power Grid Name n A1 A2 A3 A4 13.968 Onchip Grid nint nprt 12.5 10. III = good Speedup Rank I III II Accuracy II II I Abhishek Incremental Power Grid Veriﬁcation 29 / 32 .920 664 1.2 3.1mV δ2 = 0.8 12.548 34.208 30.16x 13.577 22.36x 10.2 5.Extensions Chip Power Model Experimental Results δ1 = 0.19 2.905 24. II = better.183 52.6 4 3. % Error vub vlb 8.925 47.524 Max Error (mV) vub vlb 4 5.7 Speed Up 18.1 4.2 12.
Extensions Chip Power Model Runtime Analysis 7 6 5 Runtime (hours) 4 3 2 1 0 Flat Approach I Approach II Approach III A1 A2 Test Grids A3 A4 Abhishek Incremental Power Grid Veriﬁcation 30 / 32 .
Conclusions To Sum Up Power grid veriﬁcation is essential to design veriﬁcation Constraintsbased veriﬁcation allows for early veriﬁcation of the power grids We proposed a vectorless approach for incremental grid veriﬁcation for conductiveonly and RC grid models: It provides the ability to efﬁciently perform veriﬁcation of a part of the grid It reduces the size of the problem by macromodeling the subgrid It can efﬁciently compute the upper bounds vector without verifying the internal nodes We also applied this approach to construct Chip Power Model for onchip interconnects that provide an efﬁcient way to design the package while considering the behavior of onchip PDN. Abhishek Incremental Power Grid Veriﬁcation 31 / 32 .
Thank You Questions Abhishek Incremental Power Grid Veriﬁcation 32 / 32 .
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