SABANCI UNIVERSITY Faculty of Engineering And Natural Sciences Microelectronics Engineering EL 202 - Electronic Circuits II Spring-2003

Course Instructor: Assoc. Prof. Yasar Gürbüz e-mail: yasar@sabanciuniv.edu Office: FENS 1044 Tel: ext. 9533 TAs: İhsan Çicek (ihsanc@su.sabanciuniv.edu), Head TA Mustafa Parlak (mparlak@su.sabanciuniv.edu) Mansoor Naseer (mansoor@su.sabanciuniv.edu) Beril S Çiftçi (beril@su.sabanciuniv.edu) Aylin Ekşim (ayline@su.sabanciuniv.edu)

Class Information
Lecture Recitation Labs : Section Office Hours:
Course Instructor: Monday 13:10 - 14:10 (Location: FENS 1044) TAs: Thursday 17:10-16:10 (Location: FENS 1040)

Time Mon. 09:10-10:00 Wed. 11:10-13:00 Fri. 11:10-13:00 Thursday 19:00 – 22:00

Place FENS L045 FENS L045 FENS G032 FENS 1067

Description:
Characteristics, applications, analysis, and design of circuits using BJTs and field-effect transistors (FET) with small and large-signal behaviors. Classroom concepts are reinforced through laboratory experiments and design exercises. Two in-class exams and one final exam will be prepared. No makeup exams will be given. It is in your best interest to attend all exams on the date of their delivery. Conflicts must be stated before the fact. Failure to attend an exam or to make previous arrangements results in a score of zero. Incompletes are not given out as course grades as a consequence of missing an exam, laboratory, or homework assignment. Examinations are normally closed-book, closed-notes, and closed homeworks. Single sheets of summary notes are, however, permitted.

Textbooks:

1 student edition. since solutions to the homework will be posted on the class website immediately after the homework is handed in. Computers and Software: HP-VEE software will be used in the lab experiments and available on the PC’s in the lab. Only PSpice A/D and Capture will be used in this course.sedrasmith. New York: McGraw-Hill. Sedra. but strongly recommended since you are responsible for any material covered in class and any handouts distributed during this time. it is most important that your work be legible. Homework is due at the end of class one week from the day it was handed out. 1997. Microelectronics. T. This includes Pspice A/D. New York: McGraw-Hill. Calculators: An electronic hand calculator is necessary for both the exams and homeworks in this class. 4th Edition.com. Students are responsible for knowing how to use their own calculators. and on one side of the page only for full credit. Homework should be in order. Be sure to use PSpice 9. and PSpice Optimizer. Sodini. Capture. You are encouraged to work together on the problems. N. Microelectronic circuits and devices Homework: Homework will consist of problems given out on a weekly basis. A programmable calculator or one that offers an equation “solver” function is not required. 1996 M. A. Kenneth C. Schematics.g. e. The grading of homework (as well as the exams) will emphasize the method used to arrive at the answer rather than the numerical result itself. Second Edition. Smith. Electronic Circuit Analysis and Design. Microelectronic Circuit Design. organized. 1998 (www. Gordon Roberts and Adel Sedra. Jaeger. G. Microelectronic Circuits.• • Adel S. but please insure that the final work handed in is your own. Late homework is not accepted under any circumstances. R.com) SPICE. from SPICE. 1996 Reference Books (available for the short-loan at the Information Center): • • • • R. must be properly annotated to explain and label its key features. Neamen. nominally on Wednesdays. Hence. Prentice Hall D. Lectures: Lecture attendance is not required.orcad. and understandable. C. Oxford University Press. Hornstein. This class will also involve computer simulation of circuits using PSPICE. but strongly recommended. computer output. stapled. Grading: Midterms: Homework: Lab: Final: 40% (2 x 20%) 10% 20% 30% . In addition. This program will be available on the course web-site for downloading or you obtain the same PSPICE student version software from the OrCAD website: http://www. Howe and C.

7 The Transistor as and Amplifier 4.2 Operation of the npn Transistor in the Active Mode 4.1 Structure and Physical Operation of the Enhancement-Type MOSFET 5.5 Graphical Representation of Transistor Characteristics 4.12 The Transistor as a Switch-Cutoff and Saturation 4.8 The CMOS Digital Logic Inverter 5.7 BiCMOS Amplifiers (3 weeks) .1 The BJT Differential Pair 6.Circuits II Course Outline Chapter 4 Bipolar Junction Transistors (BJTs) (2.2 Small-Signal Operation of the BJT Differential Amplifier 6.5 weeks) Introduction 4.5 The MOSFET as an Amplifier 5.5 The BJT Differential Amplifier with Active Load 6.8 Small-Signal Equivalent Circuit Models 4.13 A General Large-Signal Model for the BJT: The Ebers-Moll (EM) Model 4.16 The SPICE BJT Model and Simulation Example Chapter 5 Field-Effect Transistors (FETs) Introduction 5.4 Biasing in BJT Integrated Circuits 6.9 The MOSFET as an Analog Switch 5. Internal Capacitances.11 Basic Single-Stage BJT Amplifier Configurations 4.3 The pnp Transistor 4.EL 202 .3 Other Nonideal Characteristics of the Differential Amplifier 6.12 Gallium Arsenide (GaAs) Devices-The MESFET 5.1 Physical Structure and Modes of Operation 4.10 Biasing the BJT for Discrete Circuit Design 4.2 Current-Voltage Characteristics of the Enhancement MOSFET 5.3 The Deletion-Type MOSFET 5.4 Circuit Symbols and Conventions 4.6 MOS Differential Amplifiers 6.6 Analysis of Transistor Circuits at DC 4.4 MOSFET Circuits at DC 5.14 The Basic BJT Logic Inverter 4.6 Biasing in MOS Amplifiers 5.7 Basic Configurations of Single-Stage IC MOS Amplifiers 5.10 Internal Capacitances of the MOSFET 5.13 The SPICE MOSFET Model and Simulation Examples (4 weeks) Midterm I Chapter 6 Differential and Multistage Amplifiers Introduction 6.15 Complete Static Characteristics. and Second-Order Effects 4.9 Graphical Analysis 4.11 The Junction Field-Effect Transistor (JFET) 5.

8 IC Power Amplifiers 9.5 The Common-Base.7 Variations on the Class AB Configuration 9.2 The Amplifier Transistor Function 7.3 Class B Output Stage 9.1 s-Domain Analysis: Poles.2 Some Properties of Negative Feedback 8.10 SPICE Simulation Examples Chapter 7 Frequency Response (2 weeks) Introduction 7.6.7 Determining the Loop Gain 8.3 Low-Frequency Response of the Common-Source Amplifiers and Common-Emitter 7.end ------------------------------------------ (….4 High.9 Multistage Amplifiers 6.5 The Series-Series Feedback Amplifier 8.8 The Stability Problem 8. Zeros and Bode Plots 7.8 GaAs Amplifiers 6.6 Power BJTs 9.3 The Four Basic Feedback Topologies 8.4 The Series-Shunt Feedback Amplifier 8.9 MOS Power Transistors 9.9 SPICE Simulation Examples Midterm II Chapter 8 Feedback Introduction 8.7 The Common-Collector Common-Emitter Cascade 7.Frequency Response of the Common-Source Amplifiers and Common-Emitter 7.6 The Shunt-Shunt and Shunt-Series Feedback Amplifiers 8.1 The General Feedback Structure 8.8 Frequency Response of the Differential Amplifier 7.9 Effect of Feedback on the Amplifier Poles 8.1 Classification and Output Stages 9.11 Frequency Compensation 8.10 SPICE Simulation Examples ------------------------.10 Stability Study Using Bode Plats 8. and Cascade Configurations 7.6 Frequency Response of the Emitter and Source Followers 7.12 SPICE Simulation Examples (2 weeks) Chapter 9 Output Stages and Power Amplifiers Introduction 9.4 Class AB Output Stage 9. weeks) .2 Class A Output Stage 9. Common-Gate.5 Biasing the Class AB Circuit 9.