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INDEX S.NO 1.0 1.1 1.2 1.3 1.4 2.0 3.0 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 4.0 4.

1 Introduction Abstract Existing system limitations Proposed system limitations Applications List of components used in the system Inverter Mosfet Mosfet operation Mosfet structure and channel formation Modes of operation of mosfet Mosfet types Dual gate mosfet Depletion mode mosfet NMOS logic Power mosfet DMOS RHBD mosfets Peripheral interface controller(PIC) Core architecture PAGE NO 3 4 4 4 4 5 5 6 10 11 13 17 17 18 19 20 21 22 22 23


4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 5.0 6.0 7 .0 8.0 9.0 9.1 9.2 10.0 10.1

Data space (RAM) Code space Word size Stacks Instruction set Performance Advantages Instruction set Compiler development Family core architectural differences Baseline core devices (12-bit) Bridge rectifier Driver circuit Filters Transformers Three phase a.c. motor Squirrel cage rotor Operation Traction Factors affecting traction

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In this project, a Three Phase A.C motor using MOSFET is proposed. A.C Motor is the most widely used motors for appliances, industrial control, and automation. They are robust, reliable, and durable. When the power is supplied to an induction motor at the recommended specifications, it runs at its rated speed. However, many applications need variable speed operations. Recently, electronic power and control systems have matured to allow these components to be used for motor control in place of mechanical gears. These electronics not only control the motor’s speed, but can improve the motor’s dynamic and steady state characteristics. In addition, electronics can reduce the system’s average power consumption and noise generation of the motor.


1.2 EXISTING SYSTEM LIMITATIONS:  Traditional Induction motor control is complex due to its nonlinear characteristics.  Ac motor control by using inverter is impossible.  Wound DC motor is preferred in past because they were easier to control.

1.3 PROPOSED SYSTEM LIMITATIONS:  Low maintenance cost  It is a flexible design which allows innovations and newer technologies to be incorporated easily without incurring extra costs or necessitating changes in basic design.  Fully Self-protected against faults.

1.4 APPLICATIONS:  Electrical Traction.  Industrial control Application.  Automation.

 Speed control of AC motor.


Inverters are commonly used to supply AC power from DC sources such as solar panels or batteries. 5 . Solid-state inverters have no moving parts and are used in a wide range of applications. MOTOR  DRIVER CIRCUIT FOR PULSE GENERATION (TRIGGERING)  BRIDGE RECTIFIER  FILTERS  BATTERY FOR STORAGE PURPOSE 3 INVERTER: A power inverter. or inverter. to large electric utility high-voltage direct current applications that transport bulk power.C. the converted AC can be at any required voltage and frequency with the use of appropriate transformers. The inverter performs the opposite function of a rectifier. switching. from small switching power supplies in computers.2 COMPONENTS USED IN THE PROJECT  INVERTER USING MOSFET  PIC  TRANSFORMERS  THREE PHASE A. and control circuits. is an electrical device that changes direct current (DC) to alternating current (AC).

making it a three-terminal device like other field-effect transistors. gate (G).three phase inverter using MOSFETs 3.In this project we are using MOSFET based inverter: Fig. though the bipolar junction transistor was at one time much more common. or MOS FET) is a transistor used for amplifying or switching electronic signals. When two terminals are connected to each other (short-circuited) only three terminals appear in electrical diagrams.1. Although the MOSFET is a four-terminal device with source (S).3.1 MOSFET: The metal–oxide–semiconductor field-effect transistor (MOSFET. the body (or substrate) of the MOSFET often is connected to the source terminal. 6 . and body (B) terminals. MOS-FET. drain (D). The MOSFET is by far the most common transistor in both digital and analog circuits.

The 'metal' in the name MOSFET is now often a misnomer because the previously metal gate material is now often a layer of poly-silicon (polycrystalline silicon).In the less common depletion mode MOSFET. The channel can contain electrons (called an n-MOSFET or n-MOS). and p-MOS with an n-type substrate . the channel consists of carriers in a surface impurity layer of opposite type to the substrate. described further later on.Fig. when poly-silicon became dominant. the 'oxide' in the name can be a misnomer. as different dielectric materials are used with the aim of obtaining strong channels with applied smaller voltages. drain and source (b) MOSFET pictured with match stick for scale In enhancement mode MOSFETs.2. Metallic gates are regaining popularity. or holes (called a p-MOSFET or p-MOS).3. and conductivity is decreased by application of a field that depletes carriers from this surface layer. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel. 7 . a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. Likewise. opposite in type to the substrate. Aluminum had been the gate material until the mid-1970s. due to its capability to form self-aligned gates. so n-MOS is made with a p-type substrate. since it is difficult to increase the speed of operation of transistors without metal gates. (a) MOSFET showing gate. also referred to as the inversion layer.

3. Note that the threshold voltage for this device lies around 0.3. and body (B) terminals. The body (or substrate) of the MOSFET often is connected to the source terminal.3. there is little or no conduction between the terminals source and drain. drain (D). Although the MOSFET is a four-terminal device with source (S). Fig.4. When the gate is more positive. characteristics of drain current and gate-source voltage Simulation result for formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET.45 V. gate (G). which allows electrons to flow between the n-doped terminals. and the switch is on. and the switch is off. showing layers of MOSFET A cross section through an n-MOSFET when the gate voltage VGS is below the threshold for making a conductive channel. making it a three-terminal device like other field-effect 8 . it attracts electrons. inducing an n-type conductive channel in the substrate below the oxide.Fig. The Metal oxide field effect transistor is used for amplifying or switching electronic signals.

The term may be more inclusive. or holes (called a p-MOSFET or p-MOS). Metallic gates are regaining popularity. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel. since it is difficult to increase the speed of operation of transistors without metal gates. and conductivity is decreased by application of a field that depletes carriers from this surface layer. the channel consists of carriers in a surface impurity layer of opposite type to the substrate. Another synonym is MISFET for metal–insulator–semiconductor FET. The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925. when poly-silicon became dominant. and a gate insulator that is not oxide. The channel can contain electrons (called an n-MOSFET or n-MOS).transistors. though the bipolar junction transistor was at one time much more common. also referred to as the inversion layer. 9 . due to its capability to form self-aligned gates. a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. and p-MOS with an n-type substrate. In the less common depletion mode MOSFET. described further later on. In enhancement mode MOSFETs. An insulated-gate field-effect transistor or IGFET is a related term almost synonymous with MOSFET. The MOSFET is by far the most common transistor in both digital and analog circuits. so n-MOS is made with a p-type substrate. The 'metal' in the name MOSFET is now often a misnomer because the previously metal gate material is now often a layer of poly-silicon (polycrystalline silicon). since many "MOSFETs" use a gate that is not metal. opposite in type to the substrate. Aluminum had been the gate material until the mid-1970s. When two terminals are connected to each other (short-circuited) only three terminals appear in electrical diagrams.

3. This structure with p-type body is the basis of the n-type MOSFET. the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. it modifies the distribution of charges in the semiconductor. negatively charged acceptor ions.3. p = NA in neutral from gate to body (see figure). a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. If we consider a p-type semiconductor (with bulk). leaving exposed a carrier-free region of immobile. 10 . its structure is equivalent to a planar capacitor.2 MOSFET operation: Fig. Creates a depletion layer by forcing the positively charged holes away from the gate-insulator or semiconductor interface. in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers’ in the depletion region. where the inversion layer electrons are supplied rapidly from the source/drain electrodes. When a voltage is applied across a MOS structure.5 Metal–oxide–semiconductor structure on p-type silicon A traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline (the latter is commonly used). a positive voltage. Unlike the MOSFET. As the silicon dioxide is a dielectric material. Conventionally. p the density of holes. If is high enough. with one of the electrodes replaced by a semiconductor. which requires the addition of an n-type source and drain regions. the density of acceptors.

The source and drain are highly doped as signified by a '+' sign after the type of doping. Compared to the MOS capacitor. A metal–oxide–semiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide. The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right).3. depleting holes from surface (left). but they must both be of the same type. such as silicon dioxide.showing MOSFET channel formation Channel formation in n-MOS MOSFET: Top panels: An applied gate voltage bends bands. the MOSFET includes two additional terminals (source and drain). These regions can be either p or n type. 11 . each connected to individual highly doped regions that are separated by the body region.3 MOSFET structure and channel formation: Fig. Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel.3. If dielectrics other than an oxide such as silicon dioxide (often referred to as oxide) are employed the device may be referred to as a metal–insulator–semiconductor FET (MISFET). and of opposite type to the body region.6.

The device may comprise Silicon On Insulator (SOI) device in which a buried oxide (BOX) is formed below a thin semiconductor layer. For gate voltages below the threshold value. similarly. holes for p-channel) that flow through the channel. the channel disappears and only a very small sub-threshold current can flow between the source and the drain. analogous to the n-channel case. Alternatively. and holes from the body are driven away from the gate. As described above. and shown in the figure. If the channel region between the gate dielectric and a BOX region is very thin. but with opposite polarities of charges and voltages. At larger gate bias still. and current is conducted through it when a voltage is applied between source and drain. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. the valence band edge is driven far from the Fermi level. populating the surface with electrons in an inversion layer or n-channel at the interface between the p region and the oxide. the channel is lightly populated. the drain is where the charge carriers leave the channel. The source is so named because it is the source of the charge carriers (electrons for n-channel. near the semiconductor surface the conduction band edge is brought close to the Fermi level. When a negative gate-source voltage (positive source-gate) is applied. the very thin channel region is referred to as an ultrathin channel (UTC) region with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. When a voltage less negative than the threshold value (a negative voltage for p-channel) is applied between gate and source. then the source and drain are 'p+' regions and the body is an ‘n’ region. and only a very small sub-threshold leakage current can flow between the source and the drain. This conducting channel extends between the source and the drain. it creates a pchannel at the surface of the n region.If the MOSFET is an n-channel or n-MOS FET. the device may 12 . The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative to the semiconductor energy-band edges. with sufficient gate voltage. then the source and drain are 'n+' regions and the body is a 'p' region. If the MOSFET is a p-channel or p-MOS FET.

3. 3. When the source and drain regions are formed above the channel in whole or in part. Many alternative semiconductor materials may be employed. they are referred to as raised source/drain (RSD) regions. top 13 .4 Modes of operation: Fig.comprise a semiconductor on insulator (SEMOI) device in which semiconductors other than silicon are employed.7. top left: sub-threshold. showing modes of operation of MOSFET Example application of an N-Channel MOSFET: When the switch is pushed the LED lights up Ohmic contact to body to ensure no body bias.

bottom left: Active mode at onset of pinch-off. there is no drain voltage dependence of the current once . In a long-channel device. sub-threshold. bottom right: Active mode well into pinch-off channel length modulation evident. A more accurate model considers the effect of thermal energy on the Boltzmann distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a sub-threshold current that is an exponential function of gate–source voltage.right: Ohmic mode. or weak-inversion mode When VGS < Vth: Where gate-to-source is bias and is the threshold voltage of the device. Modern MOSFET characteristics require computer models that have rather more complex behavior. The operation of a MOSFET can be separated into three different modes. the transistor is turned off. there is a weak-inversion current. a simplified algebraic model is used that is accurate only for old technology. depending on the voltages at the terminals. With = capacitance of the depletion layer and = capacitance of the oxide layer. According to the basic threshold model. but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the 14 . In the following discussion. In weak inversion the current varies exponentially with as given approximately by: Where = current at . sometimes called subthreshold leakage. n-channel MOSFET. For an enhancement-mode. and there is no conduction between drain and source. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch. the thermal voltage and the slope factor n is given by . the three operational modes are:    Cutoff.

By working in the weakinversion region. controlled by the gate voltage relative to both the source and drain voltages. is is the gate oxide capacitance per unit area. almost that of a bipolar transistor The subthreshold I–V curve depends exponentially upon threshold voltage. introducing a strong dependence on any manufacturing variation that affects threshold voltage. is the gate width. Frequently. for example: variations in oxide thickness. The current from drain to source is modeled as: Where the gate length and is the charge-carrier effective mobility. and a channel has been created which allows current to flow between the drain and the source. namely: . ID0 = 1 μA. which may not be the same Vth-value used in the equations for the following modes. Some micro power analog circuits are designed to take advantage of sub-threshold conduction. The resulting sensitivity to fabrication variations complicates optimization for leakage and performance.device geometry (for example. the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio. The transition from the exponential sub-threshold region to the triode region is not as sharp as the equations suggest. the channel doping. or body doping that change the degree of drain-induced barrier lowering. The transistor is turned on. threshold voltage Vth for this mode is defined as the gate voltage at which a selected value of current ID0 occurs. The MOSFET operates like a resistor. 15 . the junction doping and so on). for example. junction depth.

The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage.Saturation or active mode: When VGS > Vth and VDS > ( VGS – Vth ) The switch is turned on. Another key design .or three-dimensional current distribution extending away from the interface and deeper in the substrate. and modeled approximately as: The additional factor involving λ. and conduction is not through a narrow channel but through a broader. models current dependence on drain voltage due to the early effect. 16 . or channel length modulation. the MOSFET transconductance is: Where the combination Vov = VGS – Vth is called the overdrive voltage and where VDSsat = VGS – Vth accounts for a small discontinuity in parameter is the MOSFET output resistance rout given by: which would otherwise appear at the transition between the triode and saturation regions. a key design parameter. Since the drain voltage is higher than the gate voltage. two. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. According to this equation. the channel-length modulation parameter. and a channel has been created. the electrons spread out. which allows current to flow between the drain and source.

carriers transport with near zero scattering. these equations become quite inaccurate. known as quasi-ballistic transport.8 showing dual gate MOSFET 17 . the saturation drain current is more nearly linear than quadratic in VGS.5 Other MOSFET types: 3. As the channel length becomes very short. an infinite output resistance of the device results that leads to unrealistic circuit predictions. When velocity saturation dominates. particularly in analog circuits. At even shorter lengths. Other common uses in RF circuits include gain control and mixing (frequency conversion). replacing two separate transistors in cascade configuration. For example.rout is the inverse of gDS where . carrier transport in the active mode may become limited by velocity saturation. In addition. 3. 3. If λ is taken as zero. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by Miller effect. ID is the expression in saturation region. the output current is affected by drain-induced barrier lowering of the threshold voltage. New physical effects arise.1 Dual-gate MOSFET: The dual-gate MOSFET has a tetrode configuration.5. where both gates control the current in the device. Fig.

is a double-gate silicon-on-insulator device. The "fin" refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. 18 . a negative voltage is applied to the gate (for an n-channel device). To control the channel. see figure to right. which are less commonly used than the standard enhancement-mode devices already described.9 showing depletion mode MOSFETs There are depletion-mode MOSFET devices. SOI FinFETs with a thick oxide on top of the fin are called double-gate and those with a thin oxide on top as well as on the sides are called triple-gate FinFETs. 3. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source.The FinFET. Depletion-mode MOSFETs: Fig. one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering.

10 showing NMOS logic MOSFET N-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler.depleting the channel. NMOS logic consumes power even when no switching is taking place. Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by Philips (dated 1980s). whose derivatives are still used in AGC and RF mixer front-ends. unlike CMOS logic. and better gain. which reduces the current flow through the device. NMOS logic: Fig. the depletion-mode device is equivalent to a normally closed (on) switch. With advances in technology. while the enhancement-mode device is equivalent to a normally open (off) switch. However.3. Due to their low noise figure in the RF region. these devices are often preferred to bipolar in RF front-ends such as in TV sets. In essence. 19 . CMOS logic displaced NMOS logic in the mid-1980s to become the preferred process for digital chips. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively.

With the vertical structure. Using a vertical structure.11 showing Cross section of a Power MOSFET. In a planar structure. the structure is vertical and not planar. the component area is roughly proportional to the current it can sustain. with square cells. Vertical MOSFETs are designed for switching applications 20 . resulting in inefficient use of the "silicon estate". Their advantage is a better behavior in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Power have a different structure than the one presented above. the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel).3. As with most power devices. A typical transistor is constituted of several thousand cells. it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section). the higher the current). and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage. while the current rating is a function of the channel width (the wider the channel.Power MOSFET: Fig.

One of the design approaches for making a radiation-hardened-by-design (RHBD) device is Enclosed-Layout-Transistor (ELT). Newer technologies are emerging for smaller devices for cost saving. RHBD MOSFETs: Semiconductor sub-micro meter and Nano-meter electronic circuits are the primary concern for operating within the normal tolerance in harsh radiation environments like outer space. the gate of the MOSFET surrounds the drain. 21 . However. Most power MOSFETs are made using this technology. The source of the MOSFET surrounds the gate. A lot more research works should be completed before space electronics can safely use RHBD MOSFET circuits of nanotechnology. Another RHBD MOSFET is called H-Gate. they are large in size and take more space on silicon than a standard MOSFET.DMOS: Fig. Normally. The standard MOSFET is also becoming extremely sensitive to radiation for the newer technologies.12 D MOS DMOS stands for double-diffused metal–oxide–semiconductor. 3. low power and increased operating speed. Both of these transistors have very low leakage current with respect to radiation. which is placed in the center of the ELT.

gamma ray etc. solar flare magnetic energy dissipation in earth's space. The ELT offers many advantages. If the charges are large enough. causing device to turn on. the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. These advantages include improvement of reliability by reducing unwanted surface inversion at the gate edges that occurs in the standard MOSFET. So the reliability of circuits degrades severely. extensive collection of application notes. communication devices and monitoring systems in space shuttle and satellites are very different than what we use on earth. and thus the transistor off-state leakage is reduced very much.) tolerant circuits. there is no gate oxide edge (STI at gate interface). wide availability. large user base. Since the gate edges are enclosed in ELT.PICs are popular with both industrial developers and hobbyists alike due to their low cost. and serial programming (and reprogramming with flash memory) capability. The name PIC initially referred to "Peripheral Interface Controller" . They are radiation (high-speed atomic particles like proton and neutron. These special electronics are designed by applying very different techniques using RHBD MOSFETs to ensure the safe space journey and also space-walk of astronauts. the channel inversion occurs at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. energetic cosmic rays like X-ray. 22 . availability of low cost or free development tools. Low-power microelectronic circuits including computers.When radiation strikes near the silicon oxide region (STI) of the MOSFET. 4 Peripheral Interface Controllers (MICRO CONTROLLER) (PIC): PIC is a family of modified Harvard architecture microcontrollers made by Microchip Technology. Thus the device channel inversion occurs along the channel edges and the device creates off-state leakage path. derived from the PIC1650 originally developed by General Instrument's Microelectronics Division.

1 showing PIC microcontroller 4. extended through banking  Data space mapped CPU.  A small number of fixed length instructions  Most instructions are single cycle execution (2 clock cycles. with one delay cycle on branches and skips  One accumulator (W0). the use of which (as source operand) is implied (i. is not encoded in the op-code)  All RAM locations function as registers as both source and/or destination of math and other functions.4. and peripheral registers  The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).  A hardware stack for storing return addresses  A fairly small amount of addressable data space (typically 256 bytes).e. 23 . or 4 clock cycles in 8bit models). which has Von Neumann architecture.1 Core architecture: The PIC architecture is characterized by its multiple attributes:  Separate code and data spaces (Harvard architecture) for devices other than PIC32.Fig. port.

To implement indirect addressing. In general. independent of the selected bank. This also allows FSR to be treated almost like a stack pointer (SP).increment/decrement for greater efficiency in accessing sequentially stored data. 4. A register number is written to the FSR.2 Data space (RAM): PICs have a set of registers that function as general purpose RAM. Later series of devices feature move instructions which can cover the whole addressable space. 4. external code memory is not directly addressable due to the lack of an external memory interface. There is no distinction between memory space and register space because the RAM serves the job of both memory and registers. In earlier devices.3 Code space: The code space is generally implemented as ROM. a "file select register" (FSR) and "indirect register" (INDF) are used.and pre. Later devices extended this concept with post. The addressability of memory varies depending on device series. and all PIC devices have some banking mechanism to extend addressing to additional memory. Special purpose control registers for on-chip hardware resources are also mapped into the data space. and the RAM is usually just referred to as the register file or simply as the registers. EPROM or flash ROM. any register move had to be achieved via the accumulator. after which reads from or writes to INDF will actually be to or from the register pointed to by FSR.External data memory is not directly addressable except in some high pin count PIC18 devices. 24 . The exceptions are PIC17 and select high pin count PIC18 devices.

making the 18 series architecture friendlier to high level language compilers.4. but this greatly improved in the 18 series. The hardware stack is not software accessible on earlier devices. in the PIC18 series. which differ from the instruction width of 16 bits. such as bit setting and testing. and program branching. 4. can be performed on any numbered register. Hardware support for a general purpose parameter stack was lacking in early series. Some operations.5 Stacks: PICs have a hardware call stack. PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same word size as the instruction width. which is used to save return addresses. writing the result back to either W or the other operand register. The instruction set includes instructions to perform a variety of operations on registers directly. However.e.6 Instruction set: A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. In contrast. i. 4. rather than in bytes. For example. In order to be clear. but bi-operand arithmetic operations always involve W (the accumulator).4 Word size: All PICs handle (and address) data in 8-bit chunks. it is necessary to load it into W before it can be moved into another register. On the older cores. the program memory capacity is usually stated in number of (single word) instructions. all register moves needed to pass through W. the unit of addressability of the code space is not generally the same as the data space. 25 . but this changed on the "high end" cores. but this changed with the 18 series devices. the program memory is addressed in 8-bit increments (bytes). 12 or 14 bits respectively. the accumulator and a literal constant or the accumulator and a register. To load a constant. as well as for conditional execution.

PIC cores have skip instructions which are used for conditional execution and branching.  A few miscellaneous zero-operand instructions. In general. addwf reg. E. The result can be written to either the Working register (e. andlw (AND literal with WREG). Other than the skip instructions previously mentioned. PIC instructions fall into 5 classes:  Operation on working register (WREG) with 8-bit immediate ("literal") operand. movlw (move literal to WREG). and perform one of 4 actions: set or clear a bit. 26 .g. w). Because cores before PIC18 had only unconditional branch instructions. These take a register number and a bit number. Or the selected register (e.  Bit operations. providing hardware support for automatically saving processor state when servicing interrupts. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible. The latter are used to perform conditional branches.g. and test and skip on set/clear.  Operation with WREG and indexed register. w). addwf reg. such as return from subroutine.  Control transfers. One instruction peculiar to the PIC is retlw.g. conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. and sleep to enter low-power mode. Skips are also of utility for conditional execution of any immediate single following instruction. there are only two: goto and call. load immediate into WREG and return. The skip instructions are 'skip if bit set' and 'skip if bit not set'. The 18 series implemented shadow registers which save several important registers during an interrupt. which is used with computed branches to produce lookup tables.

7 Performance: The architectural decisions are directed at the maximization of speed-to-cost ratio. The Harvard architecture—in which instructions and data come from separate sources—simplify timing and microcircuit design greatly. Internal interrupts are already synchronized. 4096 × 14-bit words on the 16F690) and by the design of the instruction set. An example of this is a video sync pulse generator. and this benefits clock speed. PWM. PSP. USB. External interrupts have to be synchronized with the four clock instruction cycle. a branch instruction's target may be indexed by W. LIN. which allows for embedded constants. Many functions can be modeled in this way. A/D. Such lookups take one instruction and two instruction cycles. and Ethernet 27 . and execute a "RETLW" which does as it is named .return with literal in W. because they have a synchronous interrupt latency of three or four cycles. USART. Optimization is facilitated by the relatively large program space of the PIC (e. The PIC instruction set is suited to implementation of fast lookup tables in the program space.8 Advantages: The PIC architectures have these advantages:  Small instruction set to learn  RISC architecture  Built in oscillator with selectable speeds  Easy entry level. SPI. and power consumption. Interrupt latency is constant at three instruction cycles.g.[citation needed] and is still among the simplest and cheapest. otherwise there can be a one instruction cycle jitter. CAN. This is no longer true in the newest PIC models.4. For example. programmable comparators. The PIC architecture was among the first scalar CPU designs. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. in circuit programming plus in circuit debugging PIC Kit units available for less than $50  Inexpensive microcontrollers  Wide range of interfaces including I²C. price. 4.

the page size is 256 instruction words. It has macro instructions like "mov b. Judicious use of simple macros can increase the readability of PIC assembly language. Microchip released their own C compilers. for the line of 18F 24F and 30/33F processors. the upper address bits are provided by the PCLATH register. For example. but still apply to earlier cores:  The hardware call stack is not addressable. there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups).9 Limitations: The PIC architectures have these limitations:  One accumulator  Register-bank switching is required to access the entire RAM of many devices  Operations and registers are not orthogonal. In both cases. 28 . while others can only use the accumulator The following stack limitations have been addressed in the PIC18 series.10 Compiler development: While several commercial compilers are available. a" (move the data from address a to address b) and "add b. so preemptive task switching cannot be implemented  Software-implemented stacks are not efficient. on PIC16. so it is difficult to generate reentrant code and support local variables With paged program memory. 4. C18 and C30. For computed GOTOs. For example. the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. CALL and GOTO have 11 bits of addressing. The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. PCLATH must also be preserved by any interrupt handler. where you add to PCL. so the page size is 2048 instruction words. some instructions can address RAM and/or immediate constants. This register must be changed every time control transfers between pages.4. in 2008.

CALL and GOTO instructions specify the low 9 bits of the new code location. If banked RAM is implemented. but written by special instructions (OPTION and TRIS). the bank number is selected by the high 3 bits of the FSR. Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions. b. allowing additional address bits. and 9-bit branch destinations. and may only specify addresses in the first half of each 512-word page. 29 . which may be extended to 2048 words by banking. 4. dest" (compare a with b and jump to dest if they are not equal). Later revisions added op-code bits. They are represented by the PIC10 series. 12-bit instructions included 5 address bits to specify the memory operand. 4 rarely-read registers were not assigned addresses. Baseline devices are available in 6-pin to 40-pin packages.The ROM address space is 512 words (12 bits each). This affects register numbers 16–31. additional high-order bits are taken from the status register.11 Family core architectural differences: PIC microchips have Harvard architecture. It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a. 4. as well as by some PIC12 and PIC16 devices. Pointers are implemented using a register pair: after writing an address to the FSR (file select register). Because of the very limited register space (5 bits). and a tiny two level deep call stack. Note that a CALL instruction only includes 8 bits of address.12 Baseline core devices (12 bit): These devices feature a 12-bit wide code memory.a" (add data from address a to data in address b). the INDF (indirect f) register becomes an alias for the addressed register. Generally the first 7 to 9 bytes of the register file are special-purpose registers. Originally. and instruction words are unusual sizes. a 32-byte register file. and the remaining bytes are general purpose RAM. registers 0–15 are global and not affected by the bank select bits.

Register numbers are referred to as "f". When used in its most common application. otherwise they are unmodified. The size is generally related to the current handling capability. resulting in lower cost and weight as compared to a rectifier with a 3-wire input from a transformer with a centertapped secondary winding. while constants are referred to as "k". 5 BRIDGE RECTIFIERS: Fig. while 1 indicates that the result is written back to source register f. for conversion of an alternating current (AC) input into direct current a (DC) output. The "d" bit Selects the destination: 0 indicates W. the carry from bit 3 to bit 4.1 three bridge rectifiers. A diode bridge is an arrangement of four (or more) diodes in a bridge circuit configuration that provides the same polarity of output for either polarity of input.5. 30 . Bit numbers (0–7) are selected by "b". A bridge rectifier provides full-wave rectification from a two-wire AC input. The C and Z status flags may be set based on the result. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag. which is useful for BCD arithmetic. it is known as a bridge rectifier.The instruction set is as follows.

or a constant voltage circuit that keeps an attached component operating within a broad range of input voltages. or both. The term is often used. and low output impedance to avoid or minimize distortion. some devices in the circuit. Electronic filters can be: 31 . a driver is an electrical circuit or other electronic component used to control another circuit or other component. typically the driver circuit requires current gain. to enhance wanted ones. 7 FILTERS: Electronic filters are electronic circuits which perform signal processing functions. such as a high-power transistor. for example.6 DRIVER CIRCUIT: Fig. for a specialized integrated circuit that controls high-power switches in switchedmode power converters. 6. often the ability to discharge the following transistor bases rapidly.1showing driver circuit for triggering the MOSFETs In electronics. They are usually used to regulate current flowing through a circuit or are used to control the other factors such as other components. Typically the driver stage(s) of a circuit requires different characteristics to other circuit stages. An amplifier can also be considered a driver for loudspeakers. specifically to remove unwanted frequency components from the signal. For example in a transistor power amplifier.

1 showing various types of filters in various sizes 8 TRANSFORMERS: Fig. low-pass. band-reject (band reject. notch). or all-pass. 7. passive or active  analog or digital  High-pass. band pass.8.1 showing transformer 32 .  discrete-time (sampled) or continuous-time  linear or non-linear  infinite impulse response (IIR type) or finite impulse response (FIR type) Fig.

current will flow in the secondary winding. in the secondary winding.1 three phase a. This varying magnetic field induces a varying electromotive force (EMF). the induced voltage in the secondary winding (Vs) is in proportion to the primary voltage (Vp) and is given by the ratio of the number of turns in the secondary (Ns) to the number of turns in the primary (Np) as follows: In this kit we are using the step down transformers one of which is 230v/50v and another is 50v/7v 9 THREE PHASE A. This effect is called inductive coupling. If a load is connected to the secondary.A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors—the transformer's coils. or "voltage".9. MOTOR: Fig. A varying current in the first or primary winding creates a varying magnetic flux in the transformer's core and thus a varying magnetic field through the secondary winding. motor 33 . In an ideal transformer. and electrical energy will be transferred from the primary circuit through the transformer to the load.C.c.

Tesla conceived the rotating magnetic field in 1882 and used it to invent the first induction motor in 1883. where he detailed the foundations of motor operation. practical induction motors were independently invented by Nikola Tesla in 1883 and Galileo Ferraris in 1885. 9. was granted U.An induction or asynchronous motor is a type of AC motor where power is supplied to the rotor by means of electromagnetic induction. Ferraris developed the idea in 1885. and this term is sometimes used for induction motors generally. rather than a commutator or slip rings as in other types of motor. using variable frequency drives are becoming more common. According to his 1915 autobiography.2 showing squirrel cage rotor The idea of a rotating magnetic field was developed by François Arago in 1824. Ferraris published his research to the Royal Academy of Sciences in Turin. particularly polyphase induction motors. These motors are widely used in industrial drives. so they are most widely used in constant-speed applications. 34 . Tesla. Patent 381. Single-phase versions are used in small appliances.9. and first implemented by Walter Baily. although variable speed versions. The induction motor with a cage was invented by Mikhail Dolivo-Dobrovolsky a year later. in the same year. In 1888. Their speed is determined by the frequency of the supply current.1 Squirrel cage rotor: Fig. Based on this.S. because they are rugged and have no brushes. The most common type is the squirrel cage motor.968 for his motor.

in an induction motor the rotor rotates at a slower speed than the stator field. The cause of induced current in the rotor is the rotating stator magnetic field. These currents in turn create magnetic fields in the rotor.2 Operation: Fig. so to oppose this rotor will start to rotate in the direction of the rotating stator magnetic field to make the relative speed between rotor and rotating stator magnetic field zero. By contrast. the direction of the magnetic field created will be such as to oppose the change in current through the windings.9. the speed of the physical rotor must be lower than that of the stator's rotating magnetic field ( ). In a synchronous motor. The rotating magnetic flux induces currents in the windings of the rotor as in a transformer. the stator is powered with alternating current (polyphase current in large machines) and designed to create a rotating magnetic field which rotates in time with the AC oscillations. or the magnetic field would not be moving relative to the rotor conductors and no currents would be induced. Therefore the magnetic field through the rotor is changing (rotating). Due to Lenz's law. the rotor turns at the same rate as the stator field. In both induction and synchronous motors. the rotation rate of the magnetic field in the rotor 35 . that interact with (push against) the stator field.9.3 a 3-phase power supply provides a rotating magnetic field in an induction motor. The rotor has windings in the form of closed loops of wire. As the speed of the rotor drops below synchronous speed. For these currents to be induced.

increases. An induction motor can be used as induction. which means p = 1. equivalent to in the formula at left).4Typical torque curve as a function of slip (slip is represented by g here. For this reason. and for a line frequency of 50 Hz the synchronous speed is 3000 RPM. The ratio between the rotation rate of the magnetic field as seen by the rotor (slip speed) and the rotation rate of the stator's rotating field is called "slip". or it can be unrolled to form the linear induction motor which can directly generate linear motion. induction motors are sometimes referred to as asynchronous motors. For example.9. the speed drops and the slip increases enough to create sufficient torque to turn the load. Under load. use 120 as constant instead of 60. So there is one pair of poles per phase. a small 3-phase motor typically has six magnetic poles organized as three opposing pairs 120° apart. Slip: Fig. 36 . The synchronous speed ns in revolutions per minute (RPM) is given by: Where f is the frequency of the AC supply current in Hz and p is the number of magnetic pole pairs per phase. inducing more current in the windings and creating more torque. Synchronous speed: The synchronous speed of an AC motor is the rotation rate of the rotating magnetic field created by the stator. each powered by one phase of the supply current. When using total number of poles. It is always an integer fraction of the supply frequency.

Slip s is the rotation rate of the magnetic field. so induction motors have good speed regulation and are considered constant-speed motors. the torque goes to zero at 100% slip (zero speed). but still around 300% of rated torque. a small slip induces a large current in the rotor and produces large torque. Torque curve: The torque exerted by the motor as a function of slip is given by a torque curve. the motor will stall. Since the short-circuited rotor windings have small resistance. In 2-pole single-phase motors. Finally at a slip of around 20% of the motor reaches its maximum torque. the torque decreases. increases in slip provide less additional torque. so these motors are self-starting. Over a motor's normal load range. 37 . The starting torque of an induction motor is less than other types of motor. so the torque line begins to curve over. If the load torque reaches this value. relative to the rotor. In 3-phase motors the torque drops but still remains high at a slip of 100% (stationary rotor). the torque line is close to a straight line. typical values of slip are 4-6% for small motors and 1. divided by the absolute rotation rate of the stator magnetic field Where is the rotor rotation speed in rpm? It is zero at synchronous speed and 1 (100%) when the rotor is stationary. The slip determines the motor's torque. so the torque is proportional to slip. called the "breakdown torque". At full rated load. As the load increases above the rated load.5-2% for large motors. so these require alterations to the stator such as shaded polesto provide starting torque. At values of slip above this.

However. When used in this way. However. By varying the line frequency with an inverter.Speed control: Fig. depending on the nature of the mechanical load. the speed tends to be unstable and the motor may stall or run at reduced shaft speed. it was difficult to vary the frequency. 38 . induction motors are usually run so that in operation the shaft rotation speed is kept above the peak torque point. and induction motors were mainly used in fixed speed applications. loading the motor reduces the rotation speed. induction motors can be kept on the stable part of the torque curve above the peak over a wide range of rotation speeds.5showing speed characteristics with respect to slip Typical torque curves for different line frequencies. and fixed line frequencies and other start up schemes are often employed instead. The theoretical unloaded speed (with slip approaching zero) of the induction motor is controlled by the number of pole pairs and the frequency of the supply voltage. Before the development of semiconductor power electronics. the inverters can be expensive. Below this point. many older DC motors have now been replaced with induction motors and accompanying inverters in industrial applications.9. then the motor will tend to run at reasonably constant speed. When driven from a fixed line frequency.

6showing types of torques for different motors Torque curves for 4 types of asynchronous induction motors: A)Single-phasemotor B)Poly-phasesquirrel-cagemotor C)Polyphasesquirrelcagedeepbarmotor D) Polyphase double squirrel cage motor A single phase induction motor is not self-starting. This imparts sufficient rotational character to start the motor. so the starting circuit determines the operating direction. The four methods of starting an induction motor are direct on-line. 39 .9.Starting: Fig. These motors are typically used in applications such as desk fans and record players. The normal running windings within such a motor can cause the rotor to turn in either direction. The current induced in this turn lags behind the supply current. as the starting torque is very low and low efficiency is not objectionable. Unlike a wound-rotor motor. reactor. it is necessary to provide a starting circuit and associated start windings to give the initial rotation in a single phase induction motor. A polyphase induction motor is self-starting and produces torque even at standstill. thus. starting is done by a shaded pole. autotransformer and star-delta. the rotor circuit is inaccessible and it is not feasible to introduce extra resistance for starting or speed control. with a turn of copper wire around part of the pole. creating a delayed magnetic field around the shaded part of the pole face. For small single-phase shaded-pole motor of a few watts.

the rotor current is the same frequency as the stator current. such currents may be created by feeding the winding through a capacitor or having it have different values of inductance and resistance from the main winding. Other designs keep the second winding on when running. In a wound rotor motor. reducing the current through the second winding to an insignificant level. The different bar shapes can give usefully different speed/torque characteristics as well as some control over the inrush current at startup. The current distribution within the rotor bars varies depending on the frequency of the inducted current. slip rings are provided and external resistance can be inserted in the rotor circuit. Polyphase motors have rotor bars shaped to give different speed/torque characteristics. As the rotor accelerates. and current tends to travel deeper within the squirrel cage bars. improving torque. 40 . In some designs. the slip frequency declines.Larger single phase motors have a second stator winding fed with out-of-phase current. At standstill. so no extra mechanism is required to initiate rotation. allowing the speed/torque characteristic to be changed for purposes of acceleration control and speed control. and tends to travel at the outermost parts of the squirrel-cage rotor bars. usually either by a centrifugal switch acting on weights on the motor shaft or a thermistor which heats up and increases its resistance. Polyphase motors can generate torque from standstill. the second winding is disconnected once the motor is up to speed.

10 TRACTION: Fig.) i. showing traction used in electric train . also known as limiting friction. 41 . stoppage or the transmission of power. or tractive force.e. and closely related to the term drawbar pull..: Usable Traction = coefficient of Traction x Weight As the coefficient of traction refers to two surfaces which are not slipping relative to one another it is the same as Coefficient of static friction. Coefficient of traction The coefficient of traction is defined as the usable force for traction divided by the weight on the running gear (wheels. The traction produced by a vehicle if expressed as a force is synonymous with tractive effort.a physical process in which a tangential force is transmitted across an interface between two bodies through dry friction or an intervening fluid film resulting in motion. tracks etc.

42 .1 Factors affecting tractive coefficient: Fig. macro texture and micro texture)  Normal force pressing contact surfaces together. Current traction control systems do not work on untreated ice.  Relative motion of tractive surfaces .g.  Macroscopic and microscopic shape (texture.  Contaminants at the material boundary including lubricants and adhesives.causing loss of traction. traction used in elevators  Traction between two surfaces depends on several factors including:  Material composition of each surface.10.e. a wheel on gritted ice when in motion may displace the grit and melt the ice .